diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
35 files changed, 3186 insertions, 150 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index d3347b375b..0467d00d6a 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o obj-y += cpu.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 453effa541..803aa9c545 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -149,6 +149,7 @@ __weak void am33xx_spl_board_init(void) do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); } +#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) static void rtc32k_enable(void) { struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; @@ -164,6 +165,7 @@ static void rtc32k_enable(void) /* Enable the RTC 32K OSC by setting bits 3 and 6. */ writel((1 << 3) | (1 << 6), &rtc->osc); } +#endif static void uart_soft_reset(void) { @@ -232,8 +234,10 @@ void s_init(void) #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) prcm_init(); set_mux_conf_regs(); +#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) /* Enable RTC32K clock */ rtc32k_enable(); +#endif sdram_init(); #endif } diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fa697c74ab..5b0454c3ea 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -89,15 +89,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); - writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff); writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); - writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff); writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); - writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff); writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); } @@ -121,10 +118,6 @@ void config_ddr_data(const struct ddr_data *data, int nr) &(ddr_data_reg[nr]+i)->dt0fwsratio0); writel(data->datawrsratio0, &(ddr_data_reg[nr]+i)->dt0wrsratio0); - writel(data->datauserank0delay, - &(ddr_data_reg[nr]+i)->dt0rdelays0); - writel(data->datadldiff0, - &(ddr_data_reg[nr]+i)->dt0dldiff0); } } diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c index 51f0a6dff1..78ecfc882a 100644 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c @@ -15,7 +15,7 @@ unsigned int has_emac() { - return cpu_is_sama5d31() || cpu_is_sama5d35(); + return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36(); } unsigned int has_gmac() @@ -42,6 +42,8 @@ char *get_cpu_name() return "SAMA5D34"; case ARCH_EXID_SAMA5D35: return "SAMA5D35"; + case ARCH_EXID_SAMA5D36: + return "SAMA5D36"; default: return "Unknown CPU type"; } @@ -82,7 +84,7 @@ void at91_seriald_hw_init(void) at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_DBGU); } #if defined(CONFIG_ATMEL_SPI) diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c index 3808aedc79..e3ebfe0c52 100644 --- a/arch/arm/cpu/armv7/at91/timer.c +++ b/arch/arm/cpu/armv7/at91/timer.c @@ -60,7 +60,7 @@ int timer_init(void) at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; /* Enable PITC Clock */ - at91_periph_clk_enable(ATMEL_ID_SYS); + at91_periph_clk_enable(ATMEL_ID_PIT); /* Enable PITC */ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 36fedd630c..84a50470aa 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1410,7 +1410,8 @@ void set_mmc_clk(int dev_index, unsigned int div) else { if (proid_is_exynos4412()) exynos4x12_set_mmc_clk(dev_index, div); - exynos4_set_mmc_clk(dev_index, div); + else + exynos4_set_mmc_clk(dev_index, div); } } diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 8002bce79c..74cc7009ff 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC3: case PERIPH_ID_SDMMC4: - printf("SDMMC device %d not implemented\n", peripheral); + debug("SDMMC device %d not implemented\n", peripheral); return -1; default: debug("%s: invalid peripheral %d", __func__, peripheral); diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index 3651c00859..ade45fd5d3 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -10,8 +10,11 @@ #include <asm/arch/clock.h> #include <asm/arch/clk.h> #include <asm/arch/dmc.h> +#include <asm/arch/periph.h> +#include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/arch/spl.h> +#include <asm/arch/spi.h> #include "common_setup.h" #include "clock_init.h" @@ -59,6 +62,121 @@ static int config_branch_prediction(int set_cr_z) } #endif +#ifdef CONFIG_SPI_BOOTING +static void spi_rx_tx(struct exynos_spi *regs, int todo, + void *dinp, void const *doutp, int i) +{ + uint *rxp = (uint *)(dinp + (i * (32 * 1024))); + int rx_lvl, tx_lvl; + uint out_bytes, in_bytes; + + out_bytes = todo; + in_bytes = todo; + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + + while (in_bytes) { + uint32_t spi_sts; + int temp; + + spi_sts = readl(®s->spi_sts); + rx_lvl = ((spi_sts >> 15) & 0x7f); + tx_lvl = ((spi_sts >> 6) & 0x7f); + while (tx_lvl < 32 && out_bytes) { + temp = 0xffffffff; + writel(temp, ®s->tx_data); + out_bytes -= 4; + tx_lvl += 4; + } + while (rx_lvl >= 4 && in_bytes) { + temp = readl(®s->rx_data); + if (rxp) + *rxp++ = temp; + in_bytes -= 4; + rx_lvl -= 4; + } + } +} + +/* + * Copy uboot from spi flash to RAM + * + * @parma uboot_size size of u-boot to copy + * @param uboot_addr address in u-boot to copy + */ +static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) +{ + int upto, todo; + int i, timeout = 100; + struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE; + + set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* set the spi1 GPIO */ + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + + /* set pktcnt and enable it */ + writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + /* set FB_CLK_SEL */ + writel(SPI_FB_DELAY_180, ®s->fb_clk); + /* set CH_WIDTH and BUS_WIDTH as word */ + setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + + /* clear rx and tx channel if set priveously */ + clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + + setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN | + SPI_RX_BYTE_SWAP | + SPI_RX_HWORD_SWAP); + + /* do a soft reset */ + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + + /* now set rx and tx channel ON */ + setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + + /* Send read instruction (0x3h) followed by a 24 bit addr */ + writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data); + + /* waiting for TX done */ + while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) { + if (!timeout) { + debug("SPI TIMEOUT\n"); + break; + } + timeout--; + } + + for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { + todo = min(uboot_size - upto, (1 << 15)); + spi_rx_tx(regs, todo, (void *)(uboot_addr), + (void *)(SPI_FLASH_UBOOT_POS), i); + } + + setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + + /* + * Let put controller mode to BYTE as + * SPI driver does not support WORD mode yet + */ + clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + writel(0, ®s->swap_cfg); + + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} +#endif + /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -70,6 +188,9 @@ void copy_uboot_to_ram(void) u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL; u32 offset = 0, size = 0; +#ifdef CONFIG_SPI_BOOTING + struct spl_machine_param *param = spl_get_machine_params(); +#endif #ifdef CONFIG_SUPPORT_EMMC_BOOT u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); void (*end_bootop_from_emmc)(void); @@ -91,9 +212,8 @@ void copy_uboot_to_ram(void) switch (bootmode) { #ifdef CONFIG_SPI_BOOTING case BOOT_MODE_SERIAL: - offset = SPI_FLASH_UBOOT_POS; - size = CONFIG_BL2_SIZE; - copy_bl2 = get_irom_func(SPI_INDEX); + /* Customised function to copy u-boot from SF */ + exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE); break; #endif case BOOT_MODE_MMC: diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 24b4c18bd4..6367e09612 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -14,6 +14,7 @@ .arch_extension sec .arch_extension virt + .align 5 /* the vector table for secure state and HYP mode */ _monitor_vectors: .word 0 /* reset */ @@ -32,7 +33,6 @@ _monitor_vectors: * to non-secure state. * We use only r0 and r1 here, due to constraints in the caller. */ - .align 5 _secure_monitor: mrc p15, 0, r1, c1, c1, 0 @ read SCR bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 4d3a165f59..59f5352b26 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -17,6 +17,11 @@ obj-y += vc.o obj-y += abb.o endif +ifneq ($(CONFIG_OMAP54XX),) +obj-y += pipe3-phy.o +obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o +endif + ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index b0e1caa356..5a3f2858cd 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -206,7 +206,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } } -static void ddr3_leveling(u32 base, const struct emif_regs *regs) +static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -217,47 +217,86 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) /* * Set invert_clkout (if activated)--DDR_PHYCTRL_1 - * Invert clock adds an additional half cycle delay on the command - * interface. The additional half cycle, is usually meant to enable - * leveling in the situation that DQS is later than CK on the board.It - * also helps provide some additional margin for leveling. + * Invert clock adds an additional half cycle delay on the + * command interface. The additional half cycle, is usually + * meant to enable leveling in the situation that DQS is later + * than CK on the board.It also helps provide some additional + * margin for leveling. */ - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1); + + writel(regs->emif_ddr_phy_ctlr_1, + &emif->emif_ddr_phy_ctrl_1_shdw); __udelay(130); writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) - & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); /* Launch Full leveling */ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); /* Wait till full leveling is complete */ readl(&emif->emif_rd_wr_lvl_ctl); - __udelay(130); + __udelay(130); /* Read data eye leveling no of samples */ config_data_eye_leveling_samples(base); - /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */ - writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl); + /* + * Launch 8 incremental WR_LVL- to compensate for + * PHY limitation. + */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, + &emif->emif_rd_wr_lvl_ctl); + __udelay(130); /* Launch Incremental leveling */ writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); - __udelay(130); + __udelay(130); } -static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs) +static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + u32 fifo_reg; + + fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1); + writel(fifo_reg | 0x00000100, + &emif->emif_ddr_fifo_misaligned_clear_1); + + fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2); + writel(fifo_reg | 0x00000100, + &emif->emif_ddr_fifo_misaligned_clear_2); + + /* Launch Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + /* Wait till full leveling is complete */ + readl(&emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Read data eye leveling no of samples */ config_data_eye_leveling_samples(base); - writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); - writel(regs->sdram_config, &emif->emif_sdram_config); + /* + * Disable leveling. This is because if leveling is kept + * enabled, then PHY triggers a false leveling during + * EMIF-idle scenario which results in wrong delay + * values getting updated. After this the EMIF becomes + * unaccessible. So disable it after the first time + */ + writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); +} + +static void ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + if (is_omap54xx()) + omap5_ddr3_leveling(base, regs); + else + dra7_ddr3_leveling(base, regs); } static void ddr3_init(u32 base, const struct emif_regs *regs) @@ -270,9 +309,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * defined, contents of mode Registers must be fully initialized. * H/W takes care of this initialization */ - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); /* Update timing registers */ @@ -283,15 +319,24 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - do_ext_phy_settings(base, regs); + /* + * The same sequence should work on OMAP5432 as well. But strange that + * it is not working + */ + if (omap_revision() == DRA752_ES1_0) { + do_ext_phy_settings(base, regs); + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + } else { + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); + writel(regs->sdram_config_init, &emif->emif_sdram_config); + do_ext_phy_settings(base, regs); + } /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - if (omap_revision() == DRA752_ES1_0) - ddr3_sw_leveling(base, regs); - else - ddr3_leveling(base, regs); + ddr3_leveling(base, regs); } #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1079,10 +1124,7 @@ static void do_sdram_init(u32 base) if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - if (omap_revision() == DRA752_ES1_0) - ddr3_sw_leveling(base, regs); - else - ddr3_leveling(base, regs); + ddr3_leveling(base, regs); } /* Write to the shadow registers */ @@ -1244,6 +1286,42 @@ void dmm_init(u32 base) } +static void do_bug0039_workaround(u32 base) +{ + u32 val, i, clkctrl; + struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; + const struct read_write_regs *bug_00339_regs; + u32 iterations; + u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; + u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; + + if (is_dra7xx()) + phy_status_base++; + + bug_00339_regs = get_bug_regs(&iterations); + + /* Put EMIF in to idle */ + clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); + __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); + + /* Copy the phy status registers in to phy ctrl shadow registers */ + for (i = 0; i < iterations; i++) { + val = __raw_readl(phy_status_base + + bug_00339_regs[i].read_reg - 1); + + __raw_writel(val, phy_ctrl_base + + ((bug_00339_regs[i].write_reg - 1) << 1)); + + __raw_writel(val, phy_ctrl_base + + (bug_00339_regs[i].write_reg << 1) - 1); + } + + /* Disable leveling */ + writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); + + __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); +} + /* * SDRAM initialization: * SDRAM initialization has two parts: @@ -1319,5 +1397,11 @@ void sdram_init(void) debug("get_ram_size() successful"); } + if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && + (!in_sdram && !warm_reset())) { + do_bug0039_workaround(EMIF1_BASE); + do_bug0039_workaround(EMIF2_BASE); + } + debug("<<sdram_init()\n"); } diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c new file mode 100644 index 0000000000..b71d769410 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c @@ -0,0 +1,231 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <sata.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/errno.h> +#include "pipe3-phy.h" + +/* PLLCTRL Registers */ +#define PLL_STATUS 0x00000004 +#define PLL_GO 0x00000008 +#define PLL_CONFIGURATION1 0x0000000C +#define PLL_CONFIGURATION2 0x00000010 +#define PLL_CONFIGURATION3 0x00000014 +#define PLL_CONFIGURATION4 0x00000020 + +#define PLL_REGM_MASK 0x001FFE00 +#define PLL_REGM_SHIFT 9 +#define PLL_REGM_F_MASK 0x0003FFFF +#define PLL_REGM_F_SHIFT 0 +#define PLL_REGN_MASK 0x000001FE +#define PLL_REGN_SHIFT 1 +#define PLL_SELFREQDCO_MASK 0x0000000E +#define PLL_SELFREQDCO_SHIFT 1 +#define PLL_SD_MASK 0x0003FC00 +#define PLL_SD_SHIFT 10 +#define SET_PLL_GO 0x1 +#define PLL_TICOPWDN BIT(16) +#define PLL_LDOPWDN BIT(15) +#define PLL_LOCK 0x2 +#define PLL_IDLE 0x1 + +/* PHY POWER CONTROL Register */ +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE + +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 +#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 + +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 +#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 + + +#define PLL_IDLE_TIME 100 /* in milliseconds */ +#define PLL_LOCK_TIME 100 /* in milliseconds */ + +static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) +{ + return __raw_readl(addr + offset); +} + +static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, + u32 data) +{ + __raw_writel(data, addr + offset); +} + +static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 + *pipe3) +{ + u32 rate; + struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; + + rate = get_sys_clk_freq(); + + for (; dpll_map->rate; dpll_map++) { + if (rate == dpll_map->rate) + return &dpll_map->params; + } + + printf("%s: No DPLL configuration for %u Hz SYS CLK\n", + __func__, rate); + return NULL; +} + + +static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_LOCK_TIME; + + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (val & PLL_LOCK) + break; + } while (--timeout); + + if (!(val & PLL_LOCK)) { + printf("%s: DPLL failed to lock\n", __func__); + return -EBUSY; + } + + return 0; +} + +static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) +{ + u32 val; + struct pipe3_dpll_params *dpll_params; + + dpll_params = omap_pipe3_get_dpll_params(phy); + if (!dpll_params) { + printf("%s: Invalid DPLL parameters\n", __func__); + return -EINVAL; + } + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGN_MASK; + val |= dpll_params->n << PLL_REGN_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val &= ~PLL_SELFREQDCO_MASK; + val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); + val &= ~PLL_REGM_MASK; + val |= dpll_params->m << PLL_REGM_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); + val &= ~PLL_REGM_F_MASK; + val |= dpll_params->mf << PLL_REGM_F_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); + + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); + val &= ~PLL_SD_MASK; + val |= dpll_params->sd << PLL_SD_SHIFT; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); + + omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); + + return omap_pipe3_wait_lock(phy); +} + +static void omap_control_phy_power(struct omap_pipe3 *phy, int on) +{ + u32 val, rate; + + val = readl(phy->power_reg); + + rate = get_sys_clk_freq(); + rate = rate/1000000; + + if (on) { + val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + val |= rate << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; + } else { + val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; + val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << + OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; + } + + writel(val, phy->power_reg); +} + +int phy_pipe3_power_on(struct omap_pipe3 *phy) +{ + int ret; + u32 val; + + /* Program the DPLL only if not locked */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if (!(val & PLL_LOCK)) { + ret = omap_pipe3_dpll_program(phy); + if (ret) + return ret; + } else { + /* else just bring it out of IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + if (val & PLL_IDLE) { + val &= ~PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, + PLL_CONFIGURATION2, val); + ret = omap_pipe3_wait_lock(phy); + if (ret) + return ret; + } + } + + /* Power up the PHY */ + omap_control_phy_power(phy, 1); + + return 0; +} + +int phy_pipe3_power_off(struct omap_pipe3 *phy) +{ + u32 val; + int timeout = PLL_IDLE_TIME; + + /* Power down the PHY */ + omap_control_phy_power(phy, 0); + + /* Put DPLL in IDLE mode */ + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); + val |= PLL_IDLE; + omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); + + /* wait for LDO and Oscillator to power down */ + do { + mdelay(1); + val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); + if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) + break; + } while (--timeout); + + if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { + printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", + __func__, val); + return -EBUSY; + } + + return 0; +} + diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h new file mode 100644 index 0000000000..441f49a3f9 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h @@ -0,0 +1,36 @@ +/* + * TI PIPE3 PHY + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_PIPE3_PHY_H +#define __OMAP_PIPE3_PHY_H + +struct pipe3_dpll_params { + u16 m; + u8 n; + u8 freq:3; + u8 sd; + u32 mf; +}; + +struct pipe3_dpll_map { + unsigned long rate; + struct pipe3_dpll_params params; +}; + +struct omap_pipe3 { + void __iomem *pll_ctrl_base; + void __iomem *power_reg; + struct pipe3_dpll_map *dpll_map; +}; + + +int phy_pipe3_power_on(struct omap_pipe3 *phy); +int phy_pipe3_power_off(struct omap_pipe3 *pipe3); + +#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c new file mode 100644 index 0000000000..f5468c4c97 --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -0,0 +1,75 @@ +/* + * TI SATA platform driver + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ahci.h> +#include <scsi.h> +#include <asm/arch/clock.h> +#include <asm/arch/sata.h> +#include <asm/io.h> +#include "pipe3-phy.h" + +static struct pipe3_dpll_map dpll_map_sata[] = { + {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ + {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ + {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ + {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ + {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ + {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ + { }, /* Terminator */ +}; + +struct omap_pipe3 sata_phy = { + .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, + /* .power_reg is updated at runtime */ + .dpll_map = dpll_map_sata, +}; + +int omap_sata_init(void) +{ + int ret; + u32 val; + + u32 const clk_domains_sata[] = { + 0 + }; + + u32 const clk_modules_hw_auto_sata[] = { + (*prcm)->cm_l3init_ocp2scp3_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_sata[] = { + (*prcm)->cm_l3init_sata_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_sata, + clk_modules_hw_auto_sata, + clk_modules_explicit_en_sata, + 0); + + /* Enable optional functional clock for SATA */ + setbits_le32((*prcm)->cm_l3init_sata_clkctrl, + SATA_CLKCTRL_OPTFCLKEN_MASK); + + sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; + + /* Power up the PHY */ + phy_pipe3_power_on(&sata_phy); + + /* Enable SATA module, No Idle, No Standby */ + val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; + writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); + + ret = ahci_init(DWC_AHSATA_BASE); + scsi_scan(1); + + return ret; +} diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 14fc7e8e81..1bc27bdc7f 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -730,8 +730,6 @@ void per_clocks_enable(void) sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON); sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON); } - sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON); - sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON); sdelay(1000); } diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 6a225c8cb2..1b2f439241 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -288,17 +288,21 @@ struct vcores_data omap4460_volts = { .mm.pmic = &twl6030, }; +/* + * Take closest integer part of the mV value corresponding to a TWL6032 SMPS + * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. + */ struct vcores_data omap4470_volts = { - .mpu.value = 1200, + .mpu.value = 1202, .mpu.addr = SMPS_REG_ADDR_SMPS1, .mpu.pmic = &twl6030, .core.value = 1126, - .core.addr = SMPS_REG_ADDR_SMPS1, + .core.addr = SMPS_REG_ADDR_SMPS2, .core.pmic = &twl6030, - .mm.value = 1137, - .mm.addr = SMPS_REG_ADDR_SMPS1, + .mm.value = 1139, + .mm.addr = SMPS_REG_ADDR_SMPS5, .mm.pmic = &twl6030, }; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index e4c8316370..6903696e1b 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -32,7 +32,7 @@ #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { +const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, .ref_ctrl = 0x0000030c, @@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff808 }; -static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { +const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .sdram_config_init = 0x80000eb1, .sdram_config = 0x80001ab1, .ref_ctrl = 0x000005cd, @@ -321,3 +321,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) { *regs = &mr_regs; } + +__weak const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + return 0; +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index a1b249e734..82910e87a0 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -600,6 +600,7 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = { .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, }; const struct ctrl_ioregs ioregs_omap5432_es2 = { @@ -610,16 +611,18 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, }; const struct ctrl_ioregs ioregs_dra7xx_es1 = { .ctrl_ddrch = 0x40404040, .ctrl_lpddr2ch = 0x40404040, .ctrl_ddr3ch = 0x80808080, - .ctrl_ddrio_0 = 0xbae8c631, - .ctrl_ddrio_1 = 0xb46318d8, + .ctrl_ddrio_0 = 0xA2084210, + .ctrl_ddrio_1 = 0x84210840, .ctrl_ddrio_2 = 0x84210000, - .ctrl_emif_sdram_config_ext = 0xb2c00000, + .ctrl_emif_sdram_config_ext = 0x0001C1A7, + .ctrl_emif_sdram_config_ext_final = 0x000101A7, .ctrl_ddr_ctrl_ext_0 = 0xA2000000, }; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 1065891ae1..5386ae0568 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -168,12 +168,6 @@ void do_io_settings(void) io_settings_lpddr2(); else io_settings_ddr3(); - - /* Efuse settings */ - writel(EFUSE_1, (*ctrl)->control_efuse_1); - writel(EFUSE_2, (*ctrl)->control_efuse_2); - writel(EFUSE_3, (*ctrl)->control_efuse_3); - writel(EFUSE_4, (*ctrl)->control_efuse_4); } static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { @@ -297,13 +291,17 @@ void srcomp_enable(void) void config_data_eye_leveling_samples(u32 emif_base) { + const struct ctrl_ioregs *ioregs; + + get_ioregs(&ioregs); + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ if (emif_base == EMIF1_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif1_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif1_sdram_config_ext); else if (emif_base == EMIF2_BASE) - writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - (*ctrl)->control_emif2_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext_final, + (*ctrl)->control_emif2_sdram_config_ext); } void init_omap_revision(void) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 304ac1c173..77c428b535 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009360, .cm_l3init_hsusbtll_clkctrl = 0x4a009368, .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_sata_clkctrl = 0x4a009388, .cm_l3init_fsusb_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009400, @@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, @@ -373,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_phy_power_sata = 0x4A002374, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, .control_core_mac_id_1_lo = 0x4A00251C, @@ -698,6 +702,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009660, .cm_l3init_hsusbtll_clkctrl = 0x4a009668, .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_sata_clkctrl = 0x4a009688, .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, @@ -891,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_l3init_sata_clkctrl = 0x4a009388, .cm_gmac_clkstctrl = 0x4a0093c0, .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index e65c1160e2..2e1870609a 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -148,13 +148,13 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0E20400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_3 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_4 = 0x009E009E, - .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_ddr_phy_ctlr_1_init = 0x0024400A, + .emif_ddr_phy_ctlr_1 = 0x0024400A, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -172,13 +172,13 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { .read_idle_ctrl = 0x00050000, .zq_config = 0x0007190B, .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0020400A, - .emif_ddr_phy_ctlr_1 = 0x0E24400A, - .emif_ddr_ext_phy_ctrl_1 = 0x04040100, - .emif_ddr_ext_phy_ctrl_2 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_3 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_4 = 0x009D009D, - .emif_ddr_ext_phy_ctrl_5 = 0x009D009D, + .emif_ddr_phy_ctlr_1_init = 0x0024400A, + .emif_ddr_phy_ctlr_1 = 0x0024400A, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_3 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, + .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, .emif_rd_wr_lvl_rmp_win = 0x00000000, .emif_rd_wr_lvl_rmp_ctl = 0x80000000, .emif_rd_wr_lvl_ctl = 0x00000000, @@ -306,7 +306,7 @@ void emif_get_device_details(u32 emif_nr, #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ -const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ext_phy_ctrl_const_base[] = { 0x01004010, 0x00001004, 0x04010040, @@ -329,7 +329,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x0 }; -const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es1[] = { 0x01004010, 0x00001004, 0x04010040, @@ -352,7 +352,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x0 }; -const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es2[] = { 0x50D4350D, 0x00000D43, 0x04010040, @@ -376,51 +376,61 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { }; const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = { - 0x009E009E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x002E002E, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x004D004D, - 0x0, - 0x600020, +dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = { + 0x00B000B0, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00800080, + 0x00800080, + 0x00800080, + 0x00800080, + 0x00800080, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00800080, + 0x00800080, 0x40010080, - 0x8102040 + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; const u32 -dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = { - 0x009D009D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x002D002D, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, - 0x00570057, +dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = { + 0x00BB00BB, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x00440044, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x007F007F, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, + 0x00600060, 0x0, - 0x600020, + 0x00600020, 0x40010080, - 0x8102040 + 0x08102040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 }; const struct lpddr2_mr_regs mr_regs = { @@ -431,27 +441,38 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY }; -static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs) +static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, + const u32 **regs, + u32 *size) { switch (omap_revision()) { case OMAP5430_ES1_0: case OMAP5430_ES2_0: *regs = ext_phy_ctrl_const_base; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base); break; case OMAP5432_ES1_0: *regs = ddr3_ext_phy_ctrl_const_base_es1; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1); break; case OMAP5432_ES2_0: *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); break; case DRA752_ES1_0: - if (emif_nr == 1) + if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; - else + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1); + } else { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; + *size = + ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2); + } break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2; + *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2); } } @@ -468,6 +489,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; u32 i = 0; + u32 size; emif_nr = (base == EMIF1_BASE) ? 1 : 2; @@ -487,8 +509,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ - emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs); - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + emif_get_ext_phy_ctrl_const_regs(emif_nr, + &ext_phy_ctrl_const_regs, &size); + + for (i = 0; i < size; i++) { writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); /* Update shadow registers */ @@ -545,6 +569,74 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = { .min_tck = &min_tck, }; +/* + * List of status registers to be controlled back to control registers + * after initial leveling + * readreg, writereg + */ +const struct read_write_regs omap5_bug_00339_regs[] = { + { 8, 5 }, + { 9, 6 }, + { 10, 7 }, + { 14, 8 }, + { 15, 9 }, + { 16, 10 }, + { 11, 2 }, + { 12, 3 }, + { 13, 4 }, + { 17, 11 }, + { 18, 12 }, + { 19, 13 }, +}; + +const struct read_write_regs dra_bug_00339_regs[] = { + { 7, 7 }, + { 8, 8 }, + { 9, 9 }, + { 10, 10 }, + { 11, 11 }, + { 12, 2 }, + { 13, 3 }, + { 14, 4 }, + { 15, 5 }, + { 16, 6 }, + { 17, 12 }, + { 18, 13 }, + { 19, 14 }, + { 20, 15 }, + { 21, 16 }, + { 22, 17 }, + { 23, 18 }, + { 24, 19 }, + { 25, 20 }, + { 26, 21} +}; + +const struct read_write_regs *get_bug_regs(u32 *iterations) +{ + const struct read_write_regs *bug_00339_regs_ptr = NULL; + + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + bug_00339_regs_ptr = omap5_bug_00339_regs; + *iterations = sizeof(omap5_bug_00339_regs)/ + sizeof(omap5_bug_00339_regs[0]); + break; + case DRA752_ES1_0: + bug_00339_regs_ptr = dra_bug_00339_regs; + *iterations = sizeof(dra_bug_00339_regs)/ + sizeof(dra_bug_00339_regs[0]); + break; + default: + printf("\n Error: UnKnown SOC"); + } + + return bug_00339_regs_ptr; +} + void emif_get_device_timings_sdp(u32 emif_nr, const struct lpddr2_device_timings **cs0_device_timings, const struct lpddr2_device_timings **cs1_device_timings) diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index 5e296c4208..22219990dd 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -5,14 +5,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y = lowlevel_init.o -obj-y += cpu_info.o +obj-y = cpu_info.o obj-y += emac.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o obj-$(CONFIG_GLOBAL_TIMER) += timer.o -obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o -obj-$(CONFIG_R8A7740) += pfc-r8a7740.o -obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o -obj-$(CONFIG_SH73A0) += pfc-sh73a0.o +obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o +obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o +obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o +obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk deleted file mode 100644 index 3a36ab65e1..0000000000 --- a/arch/arm/cpu/armv7/rmobile/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v7a. -PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c new file mode 100644 index 0000000000..7232e23774 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c @@ -0,0 +1,22 @@ +/* + * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c + * This file is r8a7790 processor support. + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <common.h> +#include <asm/io.h> + +#define PRR 0xFF000044 + +u32 rmobile_get_cpu_type(void) +{ + return (readl(PRR) & 0x00007F00) >> 8; +} + +u32 rmobile_get_cpu_rev_integer(void) +{ + return (readl(PRR) & 0x000000F0) >> 4; +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c new file mode 100644 index 0000000000..2de58ed273 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c @@ -0,0 +1,29 @@ +/* + * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ +#include <common.h> +#include <asm/io.h> + +#define PRR 0xFF000044 + +u32 rmobile_get_cpu_type(void) +{ + u32 product; + + product = readl(PRR); + + return (u32)((product & 0x00007F00) >> 8); +} + +u32 rmobile_get_cpu_rev_integer(void) +{ + u32 product; + + product = readl(PRR); + + return (u32)((product & 0x000000F0) >> 4); +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 07a33fb2ae..83d5282e3e 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -58,6 +58,16 @@ int print_cpuinfo(void) rmobile_get_cpu_rev_fraction()); break; + case 0x45: + printf("CPU: Renesas Electronics R8A7790 rev %d\n", + rmobile_get_cpu_rev_integer()); + break; + + case 0x47: + printf("CPU: Renesas Electronics R8A7791 rev %d\n", + rmobile_get_cpu_rev_integer()); + break; + default: printf("CPU: Renesas Electronics CPU rev %d.%d\n", rmobile_get_cpu_rev_integer(), diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S new file mode 100644 index 0000000000..e07cc8093a --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -0,0 +1,60 @@ +/* + * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S + * This file is lager low level initialize. + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + mrc p15, 0, r4, c0, c0, 5 /* mpidr */ + orr r4, r4, r4, lsr #6 + and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ + + b do_lowlevel_init + + .pool + +/* + * CPU ID #1-#3 come here + */ + .align 4 +do_cpu_waiting: + ldr r1, =0xe6180000 /* sysc */ +1: ldr r0, [r1, #0x20] /* sbar */ + tst r0, r0 + beq 1b + bx r0 + +/* + * Only CPU ID #0 comes here + */ + .align 4 +do_lowlevel_init: + /* surpress wfe if ca15 */ + tst r4, #4 + mrceq p15, 0, r0, c1, c0, 1 /* actlr */ + orreq r0, r0, #(1<<7) + mcreq p15, 0, r0, c1, c0, 1 + /* and set l2 latency */ + mrceq p15, 1, r0, c9, c0, 2 /* l2ctlr */ + orreq r0, r0, #0x00000800 + orreq r0, r0, #0x00000003 + mcreq p15, 1, r0, c9, c0, 2 + + ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) + sub sp, r3, #4 + str lr, [sp] + + /* initialize system */ + bl s_init + + ldr lr, [sp] + mov pc, lr + nop +ENDPROC(lowlevel_init) + .ltorg diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c new file mode 100644 index 0000000000..1259062a64 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c @@ -0,0 +1,829 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c + * This file is r8a7790 processor support - PFC hardware block. + * + * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013 Magnus Damm + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> +#include "pfc-r8a7790.h" + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, + FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, + FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, + FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, + FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, + FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, + FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, + FN_IP3_14_12, FN_IP3_17_15, + + /* GPSR1 */ + FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, + FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, + FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, + FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, + FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, + FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, + + /* GPSR2 */ + FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, + FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, + FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, + FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, + FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, + FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, + FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, + + /* GPSR3 */ + FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, + FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, + FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, + FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, + FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, + FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, + FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, + + /* GPSR4 */ + FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, + FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, + FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, + FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, + FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, + FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, + FN_IP14_15_12, FN_IP14_18_16, + + /* GPSR5 */ + FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, + FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, + FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, + FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, + FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, + FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, + FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, + + /* IPSR0 - IPSR5 */ + /* IPSR6 */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, + FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER, + FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, + FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0, + FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, + FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, + FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, + FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, + + /* IPSR7 */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, + FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, + FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, + FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, + FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, + FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, + FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, + FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, + FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, + FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, + FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + + /* IPSR8 - IPSR16 */ + + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIF1_4, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFB1_4, + FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_SOF1_0, FN_SEL_SOF1_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, + FN_SEL_VI3_0, FN_SEL_VI3_1, + FN_SEL_VI2_0, FN_SEL_VI2_1, + FN_SEL_VI1_0, FN_SEL_VI1_1, + FN_SEL_VI0_0, FN_SEL_VI0_1, + FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, + FN_SEL_LBS_0, FN_SEL_LBS_1, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF3_0, FN_SEL_SOF3_1, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, + + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_ADI_0, FN_SEL_ADI_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, + FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, + FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, + FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, + + FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC2_4, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C2_4, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, + DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, + SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, + INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, + ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, + TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK, + SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, + STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, + SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, + STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, + SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, + RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, + TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, + RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, + STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, + ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, + STP_IVCXO27_1_B_MARK, HRX0_F_MARK, + + ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, + SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, + RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, + ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, + HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, + SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, + STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, + ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, + TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, + SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, + GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, + STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, + PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, + PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, + AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, + ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, + VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, + MII_RXD2_MARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_IPSR_DATA(IP6_2_0, DACK0), + PINMUX_IPSR_DATA(IP6_2_0, IRQ0), + PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), + PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), + PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP6_8_6, DACK1), + PINMUX_IPSR_DATA(IP6_8_6, IRQ1), + PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), + PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_13_11, DACK2), + PINMUX_IPSR_DATA(IP6_13_11, IRQ2), + PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), + PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), + PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4), + PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), + PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), + PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), + PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), + PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), + PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), + + PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), + PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), + PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), + PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), + PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), + PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), + PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), + PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), + PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), + PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_18_16, PWM0), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PWM1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), + PINMUX_IPSR_DATA(IP7_24_22, PWM2), + PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), + PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), + PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), + PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), + PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), + PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), + PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), + PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), + PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), + PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), + +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + /*IPSR0 - IPSR5*/ + /*IPSR6*/ + GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N), + GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B), + GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB), + GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B), + GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B), + GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B), + GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2), + GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B), + GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV), + GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D), + GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E), + GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B), + GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E), + GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0), + GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C), + GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1), + GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B), + GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G), + GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E), + GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E), + GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E), + GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F), + + /*IPSR7*/ + GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E), + GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1), + GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G), + GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN), + GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC), + GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0), + GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C), + GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC), + GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C), + GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B), + GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1), + GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C), + GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0), + GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C), + GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C), + GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1), + GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N), + GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2), + /*IPSR8 - IPSR16*/ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP3_17_15, + GP_0_30_FN, FN_IP3_14_12, + GP_0_29_FN, FN_IP3_11_8, + GP_0_28_FN, FN_IP3_7_4, + GP_0_27_FN, FN_IP3_3_0, + GP_0_26_FN, FN_IP2_28_26, + GP_0_25_FN, FN_IP2_25_22, + GP_0_24_FN, FN_IP2_21_18, + GP_0_23_FN, FN_IP2_17_15, + GP_0_22_FN, FN_IP2_14_12, + GP_0_21_FN, FN_IP2_11_9, + GP_0_20_FN, FN_IP2_8_6, + GP_0_19_FN, FN_IP2_5_3, + GP_0_18_FN, FN_IP2_2_0, + GP_0_17_FN, FN_IP1_29_28, + GP_0_16_FN, FN_IP1_27_26, + GP_0_15_FN, FN_IP1_25_22, + GP_0_14_FN, FN_IP1_21_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_12, + GP_0_11_FN, FN_IP1_11_8, + GP_0_10_FN, FN_IP1_7_4, + GP_0_9_FN, FN_IP1_3_0, + GP_0_8_FN, FN_IP0_30_27, + GP_0_7_FN, FN_IP0_26_23, + GP_0_6_FN, FN_IP0_22_20, + GP_0_5_FN, FN_IP0_19_16, + GP_0_4_FN, FN_IP0_15_12, + GP_0_3_FN, FN_IP0_11_9, + GP_0_2_FN, FN_IP0_8_6, + GP_0_1_FN, FN_IP0_5_3, + GP_0_0_FN, FN_IP0_2_0 } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_FN, FN_IP6_13_11, + GP_1_28_FN, FN_IP6_10_9, + GP_1_27_FN, FN_IP6_8_6, + GP_1_26_FN, FN_IP6_5_3, + GP_1_25_FN, FN_IP6_2_0, + GP_1_24_FN, FN_IP5_29_27, + GP_1_23_FN, FN_IP5_26_24, + GP_1_22_FN, FN_IP5_23_21, + GP_1_21_FN, FN_IP5_20_18, + GP_1_20_FN, FN_IP5_17_15, + GP_1_19_FN, FN_IP5_14_13, + GP_1_18_FN, FN_IP5_12_10, + GP_1_17_FN, FN_IP5_9_6, + GP_1_16_FN, FN_IP5_5_3, + GP_1_15_FN, FN_IP5_2_0, + GP_1_14_FN, FN_IP4_29_27, + GP_1_13_FN, FN_IP4_26_24, + GP_1_12_FN, FN_IP4_23_21, + GP_1_11_FN, FN_IP4_20_18, + GP_1_10_FN, FN_IP4_17_15, + GP_1_9_FN, FN_IP4_14_12, + GP_1_8_FN, FN_IP4_11_9, + GP_1_7_FN, FN_IP4_8_6, + GP_1_6_FN, FN_IP4_5_3, + GP_1_5_FN, FN_IP4_2_0, + GP_1_4_FN, FN_IP3_31_29, + GP_1_3_FN, FN_IP3_28_26, + GP_1_2_FN, FN_IP3_25_23, + GP_1_1_FN, FN_IP3_22_20, + GP_1_0_FN, FN_IP3_19_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, FN_IP7_15_13, + GP_2_28_FN, FN_IP7_12_10, + GP_2_27_FN, FN_IP7_9_8, + GP_2_26_FN, FN_IP7_7_6, + GP_2_25_FN, FN_IP7_5_3, + GP_2_24_FN, FN_IP7_2_0, + GP_2_23_FN, FN_IP6_31_29, + GP_2_22_FN, FN_IP6_28_26, + GP_2_21_FN, FN_IP6_25_23, + GP_2_20_FN, FN_IP6_22_20, + GP_2_19_FN, FN_IP6_19_17, + GP_2_18_FN, FN_IP6_16_14, + GP_2_17_FN, FN_VI1_DATA7_VI1_B7, + GP_2_16_FN, FN_IP8_27, + GP_2_15_FN, FN_IP8_26, + GP_2_14_FN, FN_IP8_25_24, + GP_2_13_FN, FN_IP8_23_22, + GP_2_12_FN, FN_IP8_21_20, + GP_2_11_FN, FN_IP8_19_18, + GP_2_10_FN, FN_IP8_17_16, + GP_2_9_FN, FN_IP8_15_14, + GP_2_8_FN, FN_IP8_13_12, + GP_2_7_FN, FN_IP8_11_10, + GP_2_6_FN, FN_IP8_9_8, + GP_2_5_FN, FN_IP8_7_6, + GP_2_4_FN, FN_IP8_5_4, + GP_2_3_FN, FN_IP8_3_2, + GP_2_2_FN, FN_IP8_1_0, + GP_2_1_FN, FN_IP7_30_29, + GP_2_0_FN, FN_IP7_28_27 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP11_21_18, + GP_3_30_FN, FN_IP11_17_15, + GP_3_29_FN, FN_IP11_14_13, + GP_3_28_FN, FN_IP11_12_11, + GP_3_27_FN, FN_IP11_10_9, + GP_3_26_FN, FN_IP11_8_7, + GP_3_25_FN, FN_IP11_6_5, + GP_3_24_FN, FN_IP11_4, + GP_3_23_FN, FN_IP11_3_0, + GP_3_22_FN, FN_IP10_29_26, + GP_3_21_FN, FN_IP10_25_23, + GP_3_20_FN, FN_IP10_22_19, + GP_3_19_FN, FN_IP10_18_15, + GP_3_18_FN, FN_IP10_14_11, + GP_3_17_FN, FN_IP10_10_7, + GP_3_16_FN, FN_IP10_6_4, + GP_3_15_FN, FN_IP10_3_0, + GP_3_14_FN, FN_IP9_31_28, + GP_3_13_FN, FN_IP9_27_26, + GP_3_12_FN, FN_IP9_25_24, + GP_3_11_FN, FN_IP9_23_22, + GP_3_10_FN, FN_IP9_21_20, + GP_3_9_FN, FN_IP9_19_18, + GP_3_8_FN, FN_IP9_17_16, + GP_3_7_FN, FN_IP9_15_12, + GP_3_6_FN, FN_IP9_11_8, + GP_3_5_FN, FN_IP9_7_6, + GP_3_4_FN, FN_IP9_5_4, + GP_3_3_FN, FN_IP9_3_2, + GP_3_2_FN, FN_IP9_1_0, + GP_3_1_FN, FN_IP8_30_29, + GP_3_0_FN, FN_IP8_28 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP14_18_16, + GP_4_30_FN, FN_IP14_15_12, + GP_4_29_FN, FN_IP14_11_9, + GP_4_28_FN, FN_IP14_8_6, + GP_4_27_FN, FN_IP14_5_3, + GP_4_26_FN, FN_IP14_2_0, + GP_4_25_FN, FN_IP13_30_29, + GP_4_24_FN, FN_IP13_28_26, + GP_4_23_FN, FN_IP13_25_23, + GP_4_22_FN, FN_IP13_22_19, + GP_4_21_FN, FN_IP13_18_16, + GP_4_20_FN, FN_IP13_15_13, + GP_4_19_FN, FN_IP13_12_10, + GP_4_18_FN, FN_IP13_9_7, + GP_4_17_FN, FN_IP13_6_3, + GP_4_16_FN, FN_IP13_2_0, + GP_4_15_FN, FN_IP12_30_28, + GP_4_14_FN, FN_IP12_27_25, + GP_4_13_FN, FN_IP12_24_23, + GP_4_12_FN, FN_IP12_22_20, + GP_4_11_FN, FN_IP12_19_17, + GP_4_10_FN, FN_IP12_16_14, + GP_4_9_FN, FN_IP12_13_11, + GP_4_8_FN, FN_IP12_10_8, + GP_4_7_FN, FN_IP12_7_6, + GP_4_6_FN, FN_IP12_5_4, + GP_4_5_FN, FN_IP12_3_2, + GP_4_4_FN, FN_IP12_1_0, + GP_4_3_FN, FN_IP11_31_30, + GP_4_2_FN, FN_IP11_29_27, + GP_4_1_FN, FN_IP11_26_24, + GP_4_0_FN, FN_IP11_23_22 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP7_24_22, + GP_5_30_FN, FN_IP7_21_19, + GP_5_29_FN, FN_IP7_18_16, + GP_5_28_FN, FN_DU_DOTCLKIN2, + GP_5_27_FN, FN_IP7_26_25, + GP_5_26_FN, FN_DU_DOTCLKIN0, + GP_5_25_FN, FN_AVS2, + GP_5_24_FN, FN_AVS1, + GP_5_23_FN, FN_USB2_OVC, + GP_5_22_FN, FN_USB2_PWEN, + GP_5_21_FN, FN_IP16_7, + GP_5_20_FN, FN_IP16_6, + GP_5_19_FN, FN_USB0_OVC_VBUS, + GP_5_18_FN, FN_USB0_PWEN, + GP_5_17_FN, FN_IP16_5_3, + GP_5_16_FN, FN_IP16_2_0, + GP_5_15_FN, FN_IP15_29_28, + GP_5_14_FN, FN_IP15_27_26, + GP_5_13_FN, FN_IP15_25_23, + GP_5_12_FN, FN_IP15_22_20, + GP_5_11_FN, FN_IP15_19_18, + GP_5_10_FN, FN_IP15_17_16, + GP_5_9_FN, FN_IP15_15_14, + GP_5_8_FN, FN_IP15_13_12, + GP_5_7_FN, FN_IP15_11_9, + GP_5_6_FN, FN_IP15_8_6, + GP_5_5_FN, FN_IP15_5_3, + GP_5_4_FN, FN_IP15_2_0, + GP_5_3_FN, FN_IP14_30_28, + GP_5_2_FN, FN_IP14_27_25, + GP_5_1_FN, FN_IP14_24_22, + GP_5_0_FN, FN_IP14_21_19 } + }, + + /*IPSR0 - IPSR5*/ + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { + /* IP6_31_29 [3] */ + FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, + FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, + /* IP6_28_26 [3] */ + FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, + FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, + /* IP6_25_23 [3] */ + FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, + FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, + /* IP6_22_20 [3] */ + FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, + FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, + /* IP6_19_17 [3] */ + FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, + FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0, + /* IP6_16_14 [3] */ + FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, + FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E, + FN_SCL2_CIS_E, 0, + /* IP6_13_11 [3] */ + FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + /* IP6_10_9 [2] */ + FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, + /* IP6_8_6 [3] */ + FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, + FN_SSI_SDATA8_C, 0, 0, 0, + /* IP6_5_3 [3] */ + FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, + FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, + /* IP6_2_0 [3] */ + FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { + /* IP7_31 [1] */ + 0, 0, + /* IP7_30_29 [2] */ + FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, + FN_MII_RXD2, + /* IP7_28_27 [2] */ + FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, + /* IP7_26_25 [2] */ + FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, + /* IP7_24_22 [3] */ + FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, + 0, 0, 0, + /* IP7_21_19 [3] */ + FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, + FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, + /* IP7_18_16 [3] */ + FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, + FN_GLO_SS_C, 0, 0, 0, + /* IP7_15_13 [3] */ + FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, + FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, + /* IP7_12_10 [3] */ + FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, + FN_GLO_SCLK_C, 0, 0, 0, + /* IP7_9_8 [2] */ + FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, + /* IP7_7_6 [2] */ + FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, + /* IP7_5_3 [3] */ + FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, + 0, 0, 0, + /* IP7_2_0 [3] */ + FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, + FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } + }, + /*IPSR8 - IPSR16*/ + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + GP_1_29_IN, GP_1_29_OUT, + GP_1_28_IN, GP_1_28_OUT, + GP_1_27_IN, GP_1_27_OUT, + GP_1_26_IN, GP_1_26_OUT, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_IN, GP_2_29_OUT, + GP_2_28_IN, GP_2_28_OUT, + GP_2_27_IN, GP_2_27_OUT, + GP_2_26_IN, GP_2_26_OUT, + GP_2_25_IN, GP_2_25_OUT, + GP_2_24_IN, GP_2_24_OUT, + GP_2_23_IN, GP_2_23_OUT, + GP_2_22_IN, GP_2_22_OUT, + GP_2_21_IN, GP_2_21_OUT, + GP_2_20_IN, GP_2_20_OUT, + GP_2_19_IN, GP_2_19_OUT, + GP_2_18_IN, GP_2_18_OUT, + GP_2_17_IN, GP_2_17_OUT, + GP_2_16_IN, GP_2_16_OUT, + GP_2_15_IN, GP_2_15_OUT, + GP_2_14_IN, GP_2_14_OUT, + GP_2_13_IN, GP_2_13_OUT, + GP_2_12_IN, GP_2_12_OUT, + GP_2_11_IN, GP_2_11_OUT, + GP_2_10_IN, GP_2_10_OUT, + GP_2_9_IN, GP_2_9_OUT, + GP_2_8_IN, GP_2_8_OUT, + GP_2_7_IN, GP_2_7_OUT, + GP_2_6_IN, GP_2_6_OUT, + GP_2_5_IN, GP_2_5_OUT, + GP_2_4_IN, GP_2_4_OUT, + GP_2_3_IN, GP_2_3_OUT, + GP_2_2_IN, GP_2_2_OUT, + GP_2_1_IN, GP_2_1_OUT, + GP_2_0_IN, GP_2_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, GP_1_29_DATA, GP_1_28_DATA, + GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { + 0, 0, GP_2_29_DATA, GP_2_28_DATA, + GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA, + GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA, + GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA, + GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, + GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, + GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, + GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } + }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { }, +}; + +static struct pinmux_info r8a7790_pinmux_info = { + .name = "r8a7790_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7790_pinmux_init(void) +{ + register_pinmux(&r8a7790_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h new file mode 100644 index 0000000000..a13317be0b --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h @@ -0,0 +1,92 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __PFC_R8A7790_H__ +#define __PFC_R8A7790_H__ + +#include <sh_pfc.h> +#include <asm/gpio.h> + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT2(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#if defined(CONFIG_R8A7790) +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) \ +/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT2(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx) + +#elif defined(CONFIG_R8A7791) +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +/* + * GP_0_0_DATA -> GP_7_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31] + * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_32_PORT1(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_32_PORT(fn, pfx##_5_, sfx), \ + CPU_32_PORT(fn, pfx##_6_, sfx), \ + CPU_32_PORT1(fn, pfx##_7_, sfx) +#else +#error "NO support" +#endif + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +#endif /* __PFC_R8A7790_H__ */ diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c new file mode 100644 index 0000000000..f49f990a02 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c @@ -0,0 +1,1117 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c + * + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> +#include "pfc-r8a7790.h" + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5, + FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11, + FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19, + FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29, + FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8, + FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20, + + /* GPSR1 */ + FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3, + FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16, + FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25, + FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N, + FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18, + FN_IP3_21_20, + + /* GPSR2 */ + FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, + FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19, + FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, + FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9, + FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22, + FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0, + FN_IP6_5_3, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13, + FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24, + FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9, + FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24, + FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7, + FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16, + FN_IP9_18_17, + + /* GPSR4 */ + FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25, + FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2, + FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5, + FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15, + FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25, + FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6, + FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4, + + /* GPSR5 */ + FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19, + FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24, + FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30, + FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10, + FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20, + FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3, + FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22, + + /* GPSR6 */ + FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14, + FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23, + FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0, + FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7, + FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17, + FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29, + + /* GPSR7 */ + FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24, + FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8, + FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, + FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27, + FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12, + FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, + + /* IPSR0 - IPSR10 */ + + /* IPSR11 */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, + FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5, + FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7, + FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, + FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, + FN_VI1_DATA7, FN_AVB_MDC, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, + + /* IPSR12 */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + + /* IPSR13 */ + /* MOD_SEL */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + FN_SEL_QSP_0, FN_SEL_QSP_1, + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3, + FN_SEL_HSCIF1_4, + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, + + /* MOD_SEL2 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF0_4, + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, + FN_SEL_ADG_0, FN_SEL_ADG_1, + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, + FN_SEL_SIM_0, FN_SEL_SIM_1, + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + + /* MOD_SEL3 */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_MMC_0, FN_SEL_MMC_1, + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + + /* MOD_SEL4 */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, + FN_SEL_RAD_0, FN_SEL_RAD_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, + FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, + FN_SEL_SCIF2_4, + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, + FN_SEL_SOF2_4, + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + EX_CS0_N_MARK, RD_N_MARK, + + AUDIO_CLKA_MARK, + + VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK, + VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK, + VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, + + /* IPSR0 IPSR10 */ + /* IPSR11 */ + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, + VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, + SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, + TX4_B_MARK, SCIFA4_TXD_B_MARK, + VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, + RX4_B_MARK, SCIFA4_RXD_B_MARK, + VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK, + VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK, + VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK, + VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK, + VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, + VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, + VI1_DATA7_MARK, AVB_MDC_MARK, + ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, + ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, + + /* IPSR12 */ + ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, + ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, + ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, + SCL2_D_MARK, MSIOF1_RXD_E_MARK, + ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, + SDA2_D_MARK, MSIOF1_SCK_E_MARK, + ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, + CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, + ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, + CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, + ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, + ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, + ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, + ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, + STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, + ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, + STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, + ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, + + /* IPSR13 */ + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + /* OTHER IPSR0 - IPSR10 */ + /* IPSR11 */ + PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), + PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), + PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), + PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), + PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), + PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), + PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), + PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), + PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), + PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), + PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), + PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), + PINMUX_IPSR_DATA(IP11_27, AVB_MDC), + PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), + PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), + PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), + + /* IPSR12 */ + PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), + PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), + PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), + PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), + PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), + PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), + PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), + PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), + PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), + PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), + PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), + PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), + PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), + PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), + PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), + PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), + + /* IPSR13 - IPSR16 */ +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + /* OTHER, IPSR0 - IPSR10 */ + /* IPSR11 */ + GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B), + GPIO_FN(RX0_C), GPIO_FN(SDA1_D), + GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7), + GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B), + GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B), + GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E), + GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D), + GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B), + GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B), + GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B), + GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B), + GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B), + GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B), + GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4), + GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5), + GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6), + GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7), + GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO), + GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC), + GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC), + GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C), + GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C), + + /* IPSR12 */ + GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7), + GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7), + GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C), + GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E), + GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C), + GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E), + GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B), + GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E), + GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B), + GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E), + GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3), + GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C), + GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C), + GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C), + GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D), + GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C), + GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D), + GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C), + + /* IPSR13 - IPSR16 */ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP1_22_20, + GP_0_30_FN, FN_IP1_19_17, + GP_0_29_FN, FN_IP1_16_14, + GP_0_28_FN, FN_IP1_13_11, + GP_0_27_FN, FN_IP1_10_8, + GP_0_26_FN, FN_IP1_7_6, + GP_0_25_FN, FN_IP1_5_4, + GP_0_24_FN, FN_IP1_3_2, + GP_0_23_FN, FN_IP1_1_0, + GP_0_22_FN, FN_IP0_30_29, + GP_0_21_FN, FN_IP0_28_27, + GP_0_20_FN, FN_IP0_26_25, + GP_0_19_FN, FN_IP0_24_23, + GP_0_18_FN, FN_IP0_22_21, + GP_0_17_FN, FN_IP0_20_19, + GP_0_16_FN, FN_IP0_18_16, + GP_0_15_FN, FN_IP0_15, + GP_0_14_FN, FN_IP0_14, + GP_0_13_FN, FN_IP0_13, + GP_0_12_FN, FN_IP0_12, + GP_0_11_FN, FN_IP0_11, + GP_0_10_FN, FN_IP0_10, + GP_0_9_FN, FN_IP0_9, + GP_0_8_FN, FN_IP0_8, + GP_0_7_FN, FN_IP0_7, + GP_0_6_FN, FN_IP0_6, + GP_0_5_FN, FN_IP0_5, + GP_0_4_FN, FN_IP0_4, + GP_0_3_FN, FN_IP0_3, + GP_0_2_FN, FN_IP0_2, + GP_0_1_FN, FN_IP0_1, + GP_0_0_FN, FN_IP0_0, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_IP3_21_20, + GP_1_24_FN, FN_IP3_19_18, + GP_1_23_FN, FN_IP3_17_16, + GP_1_22_FN, FN_IP3_15_14, + GP_1_21_FN, FN_IP3_13_12, + GP_1_20_FN, FN_IP3_11_9, + GP_1_19_FN, FN_RD_N, + GP_1_18_FN, FN_IP3_8_6, + GP_1_17_FN, FN_IP3_5_3, + GP_1_16_FN, FN_IP3_2_0, + GP_1_15_FN, FN_IP2_29_27, + GP_1_14_FN, FN_IP2_26_25, + GP_1_13_FN, FN_IP2_24_23, + GP_1_12_FN, FN_EX_CS0_N, + GP_1_11_FN, FN_IP2_22_21, + GP_1_10_FN, FN_IP2_20_19, + GP_1_9_FN, FN_IP2_18_16, + GP_1_8_FN, FN_IP2_15_13, + GP_1_7_FN, FN_IP2_12_10, + GP_1_6_FN, FN_IP2_9_7, + GP_1_5_FN, FN_IP2_6_5, + GP_1_4_FN, FN_IP2_4_3, + GP_1_3_FN, FN_IP2_2_0, + GP_1_2_FN, FN_IP1_31_29, + GP_1_1_FN, FN_IP1_28_26, + GP_1_0_FN, FN_IP1_25_23, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_3, + GP_2_29_FN, FN_IP6_2_0, + GP_2_28_FN, FN_AUDIO_CLKA, + GP_2_27_FN, FN_IP5_31_29, + GP_2_26_FN, FN_IP5_28_26, + GP_2_25_FN, FN_IP5_25_24, + GP_2_24_FN, FN_IP5_23_22, + GP_2_23_FN, FN_IP5_21_20, + GP_2_22_FN, FN_IP5_19_17, + GP_2_21_FN, FN_IP5_16_15, + GP_2_20_FN, FN_IP5_14_12, + GP_2_19_FN, FN_IP5_11_9, + GP_2_18_FN, FN_IP5_8_6, + GP_2_17_FN, FN_IP5_5_3, + GP_2_16_FN, FN_IP5_2_0, + GP_2_15_FN, FN_IP4_30_28, + GP_2_14_FN, FN_IP4_27_26, + GP_2_13_FN, FN_IP4_25_24, + GP_2_12_FN, FN_IP4_23_22, + GP_2_11_FN, FN_IP4_21, + GP_2_10_FN, FN_IP4_20, + GP_2_9_FN, FN_IP4_19, + GP_2_8_FN, FN_IP4_18_16, + GP_2_7_FN, FN_IP4_15_13, + GP_2_6_FN, FN_IP4_12_10, + GP_2_5_FN, FN_IP4_9_8, + GP_2_4_FN, FN_IP4_7_5, + GP_2_3_FN, FN_IP4_4_2, + GP_2_2_FN, FN_IP4_1_0, + GP_2_1_FN, FN_IP3_30_28, + GP_2_0_FN, FN_IP3_27_25 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP9_18_17, + GP_3_30_FN, FN_IP9_16, + GP_3_29_FN, FN_IP9_15_13, + GP_3_28_FN, FN_IP9_12, + GP_3_27_FN, FN_IP9_11, + GP_3_26_FN, FN_IP9_10_8, + GP_3_25_FN, FN_IP9_7, + GP_3_24_FN, FN_IP9_6, + GP_3_23_FN, FN_IP9_5_3, + GP_3_22_FN, FN_IP9_2_0, + GP_3_21_FN, FN_IP8_30_28, + GP_3_20_FN, FN_IP8_27_26, + GP_3_19_FN, FN_IP8_25_24, + GP_3_18_FN, FN_IP8_23_21, + GP_3_17_FN, FN_IP8_20_18, + GP_3_16_FN, FN_IP8_17_15, + GP_3_15_FN, FN_IP8_14_12, + GP_3_14_FN, FN_IP8_11_9, + GP_3_13_FN, FN_IP8_8_6, + GP_3_12_FN, FN_IP8_5_3, + GP_3_11_FN, FN_IP8_2_0, + GP_3_10_FN, FN_IP7_29_27, + GP_3_9_FN, FN_IP7_26_24, + GP_3_8_FN, FN_IP7_23_21, + GP_3_7_FN, FN_IP7_20_19, + GP_3_6_FN, FN_IP7_18_17, + GP_3_5_FN, FN_IP7_16_15, + GP_3_4_FN, FN_IP7_14_13, + GP_3_3_FN, FN_IP7_12_11, + GP_3_2_FN, FN_IP7_10_9, + GP_3_1_FN, FN_IP7_8_6, + GP_3_0_FN, FN_IP7_5_3 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP15_5_4, + GP_4_30_FN, FN_IP15_3_2, + GP_4_29_FN, FN_IP15_1_0, + GP_4_28_FN, FN_IP11_8_6, + GP_4_27_FN, FN_IP11_5_3, + GP_4_26_FN, FN_IP11_2_0, + GP_4_25_FN, FN_IP10_31_29, + GP_4_24_FN, FN_IP10_28_27, + GP_4_23_FN, FN_IP10_26_25, + GP_4_22_FN, FN_IP10_24_22, + GP_4_21_FN, FN_IP10_21_19, + GP_4_20_FN, FN_IP10_18_17, + GP_4_19_FN, FN_IP10_16_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_31_29, + GP_4_12_FN, FN_VI0_DATA0_VI0_B7, + GP_4_11_FN, FN_VI0_DATA0_VI0_B6, + GP_4_10_FN, FN_VI0_DATA0_VI0_B5, + GP_4_9_FN, FN_VI0_DATA0_VI0_B4, + GP_4_8_FN, FN_IP9_28_27, + GP_4_7_FN, FN_VI0_DATA0_VI0_B2, + GP_4_6_FN, FN_VI0_DATA0_VI0_B1, + GP_4_5_FN, FN_VI0_DATA0_VI0_B0, + GP_4_4_FN, FN_IP9_26_25, + GP_4_3_FN, FN_IP9_24_23, + GP_4_2_FN, FN_IP9_22_21, + GP_4_1_FN, FN_IP9_20_19, + GP_4_0_FN, FN_VI0_CLK } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + GP_5_31_FN, FN_IP3_24_22, + GP_5_30_FN, FN_IP13_9_7, + GP_5_29_FN, FN_IP13_6_5, + GP_5_28_FN, FN_IP13_4_3, + GP_5_27_FN, FN_IP13_2_0, + GP_5_26_FN, FN_IP12_29_27, + GP_5_25_FN, FN_IP12_26_24, + GP_5_24_FN, FN_IP12_23_22, + GP_5_23_FN, FN_IP12_21_20, + GP_5_22_FN, FN_IP12_19_18, + GP_5_21_FN, FN_IP12_17_16, + GP_5_20_FN, FN_IP12_15_13, + GP_5_19_FN, FN_IP12_12_10, + GP_5_18_FN, FN_IP12_9_7, + GP_5_17_FN, FN_IP12_6_4, + GP_5_16_FN, FN_IP12_3_2, + GP_5_15_FN, FN_IP12_1_0, + GP_5_14_FN, FN_IP11_31_30, + GP_5_13_FN, FN_IP11_29_28, + GP_5_12_FN, FN_IP11_27, + GP_5_11_FN, FN_IP11_26, + GP_5_10_FN, FN_IP11_25, + GP_5_9_FN, FN_IP11_24, + GP_5_8_FN, FN_IP11_23, + GP_5_7_FN, FN_IP11_22, + GP_5_6_FN, FN_IP11_21, + GP_5_5_FN, FN_IP11_20, + GP_5_4_FN, FN_IP11_19, + GP_5_3_FN, FN_IP11_18_17, + GP_5_2_FN, FN_IP11_16_15, + GP_5_1_FN, FN_IP11_14_12, + GP_5_0_FN, FN_IP11_11_9 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + GP_6_29_FN, FN_IP14_31_29, + GP_6_28_FN, FN_IP14_28_26, + GP_6_27_FN, FN_IP14_25_23, + GP_6_26_FN, FN_IP14_22_20, + GP_6_25_FN, FN_IP14_19_17, + GP_6_24_FN, FN_IP14_16_14, + GP_6_23_FN, FN_IP14_13_11, + GP_6_22_FN, FN_IP14_10_8, + GP_6_21_FN, FN_IP14_7, + GP_6_20_FN, FN_IP14_6, + GP_6_19_FN, FN_IP14_5, + GP_6_18_FN, FN_IP14_4, + GP_6_17_FN, FN_IP14_3, + GP_6_16_FN, FN_IP14_2, + GP_6_15_FN, FN_IP14_1_0, + GP_6_14_FN, FN_IP13_30_28, + GP_6_13_FN, FN_IP13_27, + GP_6_12_FN, FN_IP13_26, + GP_6_11_FN, FN_IP13_25, + GP_6_10_FN, FN_IP13_24_23, + GP_6_9_FN, FN_IP13_22, + 0, 0, + GP_6_7_FN, FN_IP13_21_19, + GP_6_6_FN, FN_IP13_18_16, + GP_6_5_FN, FN_IP13_15, + GP_6_4_FN, FN_IP13_14, + GP_6_3_FN, FN_IP13_13, + GP_6_2_FN, FN_IP13_12, + GP_6_1_FN, FN_IP13_11, + GP_6_0_FN, FN_IP13_10 } + }, + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_FN, FN_USB1_PWEN, + GP_7_24_FN, FN_USB0_OVC, + GP_7_23_FN, FN_USB0_PWEN, + GP_7_22_FN, FN_IP15_14_12, + GP_7_21_FN, FN_IP15_11_9, + GP_7_20_FN, FN_IP15_8_6, + GP_7_19_FN, FN_IP7_2_0, + GP_7_18_FN, FN_IP6_29_27, + GP_7_17_FN, FN_IP6_26_24, + GP_7_16_FN, FN_IP6_23_21, + GP_7_15_FN, FN_IP6_20_19, + GP_7_14_FN, FN_IP6_18_16, + GP_7_13_FN, FN_IP6_15_14, + GP_7_12_FN, FN_IP6_13_12, + GP_7_11_FN, FN_IP6_11_10, + GP_7_10_FN, FN_IP6_9_8, + GP_7_9_FN, FN_IP16_11_10, + GP_7_8_FN, FN_IP16_9_8, + GP_7_7_FN, FN_IP16_7_6, + GP_7_6_FN, FN_IP16_5_3, + GP_7_5_FN, FN_IP16_2_0, + GP_7_4_FN, FN_IP15_29_27, + GP_7_3_FN, FN_IP15_26_24, + GP_7_2_FN, FN_IP15_23_21, + GP_7_1_FN, FN_IP15_20_18, + GP_7_0_FN, FN_IP15_17_15 } + }, + /* IPSR0 - IPSR10 */ + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 3, 3, 3, 3, 3) { + /* IP11_31_30 [2] */ + FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, + /* IP11_29_28 [2] */ + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, + /* IP11_27 [1] */ + FN_VI1_DATA7, FN_AVB_MDC, + /* IP11_26 [1] */ + FN_VI1_DATA6, FN_AVB_MAGIC, + /* IP11_25 [1] */ + FN_VI1_DATA5, FN_AVB_RX_DV, + /* IP11_24 [1] */ + FN_VI1_DATA4, FN_AVB_MDIO, + /* IP11_23 [1] */ + FN_VI1_DATA3, FN_AVB_RX_ER, + /* IP11_22 [1] */ + FN_VI1_DATA2, FN_AVB_RXD7, + /* IP11_21 [1] */ + FN_VI1_DATA1, FN_AVB_RXD6, + /* IP11_20 [1] */ + FN_VI1_DATA0, FN_AVB_RXD5, + /* IP11_19 [1] */ + FN_VI1_CLK, FN_AVB_RXD4, + /* IP11_18_17 [2] */ + FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0, + /* IP11_16_15 [2] */ + FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0, + /* IP11_14_12 [3] */ + FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, + FN_RX4_B, FN_SCIFA4_RXD_B, + 0, 0, 0, + /* IP11_11_9 [3] */ + FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, + FN_TX4_B, FN_SCIFA4_TXD_B, + 0, 0, 0, + /* IP11_8_6 [3] */ + FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, + /* IP11_5_3 [3] */ + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + 0, 0, 0, + /* IP11_2_0 [3] */ + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, + 0, 0, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, + 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { + /* IP12_31_30 [2] */ + 0, 0, 0, 0, + /* IP12_29_27 [3] */ + FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + 0, 0, 0, + /* IP12_26_24 [3] */ + FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B, FN_MSIOF0_SYNC_C, + 0, 0, 0, + /* IP12_23_22 [2] */ + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0, + /* IP12_21_20 [2] */ + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0, + /* IP12_19_18 [2] */ + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0, + /* IP12_17_16 [2] */ + FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, + /* IP12_15_13 [3] */ + FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, + FN_CAN1_TX_C, FN_MSIOF1_TXD_E, + 0, 0, 0, + /* IP12_12_10 [3] */ + FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, + FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, + 0, 0, 0, + /* IP12_9_7 [3] */ + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, + FN_SDA2_D, FN_MSIOF1_SCK_E, + 0, 0, 0, + /* IP12_6_4 [3] */ + FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, + FN_SCL2_D, FN_MSIOF1_RXD_E, + 0, 0, 0, + /* IP12_3_2 [2] */ + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + /* IP12_1_0 [2] */ + FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + }, + + /* IPSR13 - IPSR16 */ + + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 1, 2, 2, 2, 3, 2, 1, 1, 1, 1, + 3, 2, 2, 2, 1, 2, 2, 2) { + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, + /* SEL_SCIFB [2] */ + FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3, + /* SEL_SCIFB2 [2] */ + FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, + FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3, + /* SEL_SCIFB1 [3] */ + FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, + FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, + 0, 0, 0, 0, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* SEL_SCFA [1] */ + FN_SEL_SCFA_0, FN_SEL_SCFA_1, + /* SEL_QSP [1] */ + FN_SEL_QSP_0, FN_SEL_QSP_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_HSCIF1 [3] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, + FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_VI1 [2] */ + FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_TMU [1] */ + FN_SEL_TMU1_0, FN_SEL_TMU1_1, + /* SEL_LBS [2] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_SOF0 [2] */ + FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 3, 1, 1, 3, 2, 1, 1, 2, 2, + 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) { + /* SEL_SCIF0 [3] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, + FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIF [1] */ + FN_SEL_SCIF_0, FN_SEL_SCIF_1, + /* SEL_CAN0 [3] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN0_4, FN_SEL_CAN0_5, + 0, 0, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* RESEVED [1] */ + 0, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIF4 [2] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_ADG [1] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, + /* SEL_FM [3] */ + FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, + FN_SEL_FM_3, FN_SEL_FM_4, + 0, 0, 0, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_GPS [2] */ + FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, + /* SEL_SCIFA3 [2] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, + /* SEL_SIM [1] */ + FN_SEL_SIM_0, FN_SEL_SIM_1, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 2, 2, 2, 2, 2, + 1, 1, 2, 2, 3, 2, 2, 2, 1) { + /* SEL_HSCIF2 [2] */ + FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, + FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, + /* SEL_CANCLK [2] */ + FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, + FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, + /* SEL_IIC8 [2] */ + FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, + /* SEL_IIC7 [2] */ + FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, + /* SEL_IIC4 [2] */ + FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, + /* SEL_IIC3 [2] */ + FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + /* SEL_SCIF3 [2] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + /* SEL_MMC [1] */ + FN_SEL_MMC_0, FN_SEL_MMC_1, + /* SEL_SCIF5 [1] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_IIC2 [2] */ + FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, + /* SEL_IIC1 [3] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, + FN_SEL_IIC1_4, + 0, 0, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, + 3, 2, 2, 1, 1, 1, 1, 3, 2, + 2, 3, 1, 1, 1, 2, 2, 2, 2) { + /* SEL_SOF1 [3] */ + FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, + FN_SEL_SOF1_4, + 0, 0, 0, + /* SEL_HSCIF0 [2] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0, + /* SEL_DIS [2] */ + FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIF2 [3] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, + FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, + 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* SEL_SOF2 [3] */ + FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, + FN_SEL_SOF2_3, FN_SEL_SOF2_4, + 0, 0, 0, + /* RESEVED [1] */ + 0, 0, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI0 [1] */ + FN_SEL_SSI0_0, FN_SEL_SSI0_1, + /* SEL_SSP [2] */ + FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, + /* RESEVED [2] */ + 0, 0, 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } }, + { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_7_25_IN, GP_7_25_OUT, + GP_7_24_IN, GP_7_24_OUT, + GP_7_23_IN, GP_7_23_OUT, + GP_7_22_IN, GP_7_22_OUT, + GP_7_21_IN, GP_7_21_OUT, + GP_7_20_IN, GP_7_20_OUT, + GP_7_19_IN, GP_7_19_OUT, + GP_7_18_IN, GP_7_18_OUT, + GP_7_17_IN, GP_7_17_OUT, + GP_7_16_IN, GP_7_16_OUT, + GP_7_15_IN, GP_7_15_OUT, + GP_7_14_IN, GP_7_14_OUT, + GP_7_13_IN, GP_7_13_OUT, + GP_7_12_IN, GP_7_12_OUT, + GP_7_11_IN, GP_7_11_OUT, + GP_7_10_IN, GP_7_10_OUT, + GP_7_9_IN, GP_7_9_OUT, + GP_7_8_IN, GP_7_8_OUT, + GP_7_7_IN, GP_7_7_OUT, + GP_7_6_IN, GP_7_6_OUT, + GP_7_5_IN, GP_7_5_OUT, + GP_7_4_IN, GP_7_4_OUT, + GP_7_3_IN, GP_7_3_OUT, + GP_7_2_IN, GP_7_2_OUT, + GP_7_1_IN, GP_7_1_OUT, + GP_7_0_IN, GP_7_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } }, + { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) { + 0, 0, 0, 0, + 0, 0, GP_7_25_DATA, GP_7_24_DATA, + GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA, + GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA, + GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA, + GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA, + GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA, + GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7791_pinmux_info = { + .name = "r8a7791_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7791_pinmux_init(void) +{ + register_pinmux(&r8a7791_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c index 72e0c12545..04700e7d34 100644 --- a/arch/arm/cpu/armv7/rmobile/timer.c +++ b/arch/arm/cpu/armv7/rmobile/timer.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/arch-armv7/globaltimer.h> #include <asm/arch/rmobile.h> @@ -38,13 +39,16 @@ static u64 get_time_us(void) u64 timer = get_cpu_global_timer(); timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); - timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK); + do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); return timer; } static ulong get_time_ms(void) { - return (ulong)(get_time_us() / 1000); + u64 us = get_time_us(); + + do_div(us, 1000); + return us; } int timer_init(void) diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index dac2bbdac1..3e84a0c9f9 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -9,4 +9,4 @@ obj-y := lowlevel_init.o obj-y += misc.o timer.o reset_manager.o system_manager.o -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c new file mode 100644 index 0000000000..b8c9bce1e0 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2013 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/freeze_controller.h> +#include <asm/arch/timer.h> +#include <asm/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_freeze_controller *freeze_controller_base = + (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS); + +/* + * Default state from cold reset is FREEZE_ALL; the global + * flag is set to TRUE to indicate the IO banks are frozen + */ +static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM] + = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN, + FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN}; + +/* Freeze HPS IOs */ +void sys_mgr_frzctrl_freeze_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_value; + u32 reg_cfg_mask; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Freeze channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset = (u32)( + &freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low enrnsl, plniotri + * and niotri signals + */ + reg_cfg_mask = + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * Assert active low bhniotri signal and de-assert + * active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; + } + + /* Freeze channel 3 */ + /* + * Assert active low enrnsl, plniotri and + * niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK + | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * assert active low bhniotri & nfrzdrv signals, + * de-assert active high csrdone and assert + * active high frzreg and nfrzdrv signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK; + reg_value + = (reg_value & ~reg_cfg_mask) + | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK + | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * assert active high reinit signal and de-assert + * active high pllbiasen signals + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value + = (reg_value & + ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK) + | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* Set global flag to indicate channel is frozen */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN; +} + +/* Unfreeze/Thaw HPS IOs */ +void sys_mgr_frzctrl_thaw_req(void) +{ + u32 ioctrl_reg_offset; + u32 reg_cfg_mask; + u32 reg_value; + u32 channel_id; + + /* select software FSM */ + writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); + + /* Thaw channel 0 to 2 */ + for (channel_id = 0; channel_id <= 2; channel_id++) { + ioctrl_reg_offset + = (u32)(&freeze_controller_base->vioctrl + + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT)); + + /* + * Assert active low bhniotri signal and + * de-assert active high csrdone + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low plniotri and niotri signals + */ + reg_cfg_mask + = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK; + setbits_le32(ioctrl_reg_offset, reg_cfg_mask); + + /* + * Note: Delay for 20ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(ioctrl_reg_offset, + SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; + } + + /* Thaw channel 3 */ + /* de-assert active high reinit signal */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK); + + /* + * Note: Delay for 40ns at min + * assert active high pllbiasen signals + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); + + /* + * Delay 1000 intosc. intosc is based on eosc1 + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 1000 = 20us + */ + udelay(20); + + /* + * de-assert active low bhniotri signals, + * assert active high csrdone and nfrzdrv signal + */ + reg_value = readl(&freeze_controller_base->hioctrl); + reg_value = (reg_value + | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK + | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK) + & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK; + writel(reg_value, &freeze_controller_base->hioctrl); + + /* + * Delay 33 intosc + * Use worst case which is fatest eosc1=50MHz, delay required + * is 1/50MHz * 33 = 660ns ~= 1us + */ + udelay(1); + + /* de-assert active low plniotri and niotri signals */ + reg_cfg_mask + = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK + | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK; + + setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); + + /* + * Note: Delay for 40ns at min + * de-assert active high frzreg signal + */ + clrbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK); + + /* + * Note: Delay for 40ns at min + * de-assert active low enrnsl signal + */ + setbits_le32(&freeze_controller_base->hioctrl, + SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK); + + /* Set global flag to indicate channel is thawed */ + frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c index 74bceab183..36a00c39b7 100644 --- a/arch/arm/cpu/armv7/socfpga/spl.c +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -13,6 +13,7 @@ #include <asm/arch/reset_manager.h> #include <spl.h> #include <asm/arch/system_manager.h> +#include <asm/arch/freeze_controller.h> DECLARE_GLOBAL_DATA_PTR; @@ -27,6 +28,10 @@ u32 spl_boot_device(void) void spl_board_init(void) { #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET + debug("Freezing all I/O banks\n"); + /* freeze all IO banks */ + sys_mgr_frzctrl_freeze_req(); + /* configure the pin muxing through system manager */ sysmgr_pinmux_init(); #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */ @@ -34,6 +39,10 @@ void spl_board_init(void) /* de-assert reset for peripherals and bridges based on handoff */ reset_deassert_peripherals_handoff(); + debug("Unfreezing/Thaw all I/O banks\n"); + /* unfreeze / thaw all IO banks */ + sys_mgr_frzctrl_thaw_req(); + /* enable console uart printing */ preloader_console_init(); } diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 2bb38438ae..9af340e75e 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -16,23 +16,24 @@ void lowlevel_init(void) int arch_cpu_init(void) { zynq_slcr_unlock(); - /* remap DDR to zero, FILTERSTART */ - writel(0, &scu_base->filter_start); /* Device config APB, unlock the PCAP */ writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); +#if (CONFIG_SYS_SDRAM_BASE == 0) + /* remap DDR to zero, FILTERSTART */ + writel(0, &scu_base->filter_start); + /* OCM_CFG, Mask out the ROM, map ram into upper addresses */ writel(0x1F, &slcr_base->ocm_cfg); /* FPGA_RST_CTRL, clear resets on AXI fabric ports */ writel(0x0, &slcr_base->fpga_rst_ctrl); - /* TZ_DDR_RAM, Set DDR trust zone non-secure */ - writel(0xFFFFFFFF, &slcr_base->trust_zone); /* Set urgent bits with register */ writel(0x0, &slcr_base->ddr_urgent_sel); /* Urgent write, ports S2/S3 */ writel(0xC, &slcr_base->ddr_urgent); +#endif zynq_slcr_lock(); |
