1 files changed, 58 insertions, 8 deletions

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 2d6d359e5f..d64ae6936c 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -19,19 +19,31 @@
 #include <common.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/common_def.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+#endif
 
 /*
  * early system init of muxing and clocks.
  */
-void s_init(u32 in_ddr)
+void s_init(void)
 {
 	/* WDT1 is already running when the bootloader gets control
 	 * Disable it to avoid "random" resets
@@ -43,24 +55,62 @@ void s_init(u32 in_ddr)
 	while (readl(&wdtimer->wdtwwps) != 0x0)
 		;
 
+#ifdef CONFIG_SPL_BUILD
 	/* Setup the PLLs and the clocks for the peripherals */
-#ifdef CONFIG_SETUP_PLL
 	pll_init();
+
+	/* UART softreset */
+	u32 regVal;
+
+	enable_uart0_pin_mux();
+
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_RESET;
+	writel(regVal, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_SMART_IDLE_EN;
+	writel(regVal, &uart_base->uartsyscfg);
+
+	/* Initialize the Timer */
+	init_timer();
+
+	preloader_console_init();
+
+	config_ddr();
 #endif
-	if (!in_ddr)
-		config_ddr();
+
+	/* Enable MMC0 */
+	enable_mmc0_pin_mux();
 }
 
 /* Initialize timer */
 void init_timer(void)
 {
 	/* Reset the Timer */
-	writel(0x2, (&timerreg->tsicrreg));
+	writel(0x2, (&timer_base->tscir));
 
 	/* Wait until the reset is done */
-	while (readl(&timerreg->tiocpcfgreg) & 1)
+	while (readl(&timer_base->tiocp_cfg) & 1)
 		;
 
 	/* Start the Timer */
-	writel(0x1, (&timerreg->tclrreg));
+	writel(0x1, (&timer_base->tclr));
+}
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif
+
+void setup_clocks_for_console(void)
+{
+	/* Not yet implemented */
+	return;
 }