diff options
85 files changed, 1773 insertions, 466 deletions
@@ -2359,16 +2359,20 @@ CBFS (Coreboot Filesystem) support - drivers/i2c/i2c_mxc.c - activate this driver with CONFIG_SYS_I2C_MXC + - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 + - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 + - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 + - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE + - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED + - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE If those defines are not set, default value is 100000 for speed, and 0 for slave. - - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 - - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - drivers/i2c/rcar_i2c.c: - activate this driver with CONFIG_SYS_I2C_RCAR diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0b07e08db6..3a336e6fdf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -538,6 +538,10 @@ config TARGET_COLIBRI_VF bool "Support Colibri VF50/61" select CPU_V7 +config TARGET_PCM052 + bool "Support pcm-052" + select CPU_V7 + config ARCH_ZYNQ bool "Xilinx Zynq Platform" select CPU_V7 @@ -753,6 +757,7 @@ source "board/maxbcm/Kconfig" source "board/mpl/vcma9/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" source "board/phytec/pcm051/Kconfig" +source "board/phytec/pcm052/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ba6cc75a7b..11efd12c9a 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) if (freq < ENET_25MHZ || freq > ENET_125MHZ) return -EINVAL; + reg = readl(&anatop->pll_enet); + if (fec_id == 0) { reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT; reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index b40198b36e..d11365b65b 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -21,6 +21,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> +#include <asm/arch/spl.h> #include <asm/arch/sys_proto.h> #include <asm/arch/timer.h> #include <asm/arch/tzpc.h> @@ -152,7 +153,7 @@ u32 spl_boot_device(void) * binary over USB. If it is found, it determines where SPL was * read from. */ - if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */ + if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ return BOOT_DEVICE_BOARD; /* The BROM will try to boot from mmc0 first, so try that first. */ @@ -198,11 +199,6 @@ void board_init_f(ulong dummy) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif sunxi_board_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - board_init_r(NULL, 0); } #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5f10243fe6..6a11b12f27 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -158,6 +158,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ diff --git a/arch/arm/dts/sun8i-a33-q8-tablet.dts b/arch/arm/dts/sun8i-a33-q8-tablet.dts new file mode 100644 index 0000000000..44b32296a0 --- /dev/null +++ b/arch/arm/dts/sun8i-a33-q8-tablet.dts @@ -0,0 +1,65 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-q8-common.dtsi" + +/ { + model = "Q8 A33 Tablet"; + compatible = "allwinner,q8-a33", "allwinner,sun8i-a33"; +}; + +/* + * FIXME for now we only support host mode and rely on u-boot to have + * turned on Vbus which is controlled by the axp223 pmic on the board. + * + * Once we have axp223 support we should switch to fully supporting otg. + */ +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-q8-common.dtsi b/arch/arm/dts/sun8i-q8-common.dtsi new file mode 100644 index 0000000000..07cd268a4b --- /dev/null +++ b/arch/arm/dts/sun8i-q8-common.dtsi @@ -0,0 +1,84 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "sunxi-q8-common.dtsi" + +/ { + aliases { + serial0 = &r_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&pio { + bl_en_pin_q8: bl_en_pin@0 { + allwinner,pins = "PH6"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin_q8: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c index e46263144d..daf3c7ebfa 100644 --- a/arch/arm/imx-common/ddrmc-vf610.c +++ b/arch/arm/imx-common/ddrmc-vf610.c @@ -12,9 +12,9 @@ #include <asm/arch/iomux-vf610.h> #include <asm/arch/ddrmc-vf610.h> -void ddrmc_setup_iomux(void) +void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count) { - static const iomux_v3_cfg_t ddr_pads[] = { + static const iomux_v3_cfg_t default_pads[] = { VF610_PAD_DDR_A15__DDR_A_15, VF610_PAD_DDR_A14__DDR_A_14, VF610_PAD_DDR_A13__DDR_A_13, @@ -65,76 +65,54 @@ void ddrmc_setup_iomux(void) VF610_PAD_DDR_RESETB, }; - imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads)); -} + if ((pads == NULL) || (pads_count == 0)) { + pads = default_pads; + pads_count = ARRAY_SIZE(default_pads); + } -void ddrmc_phy_init(void) -{ - struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; + imx_iomux_v3_setup_multiple_pads(pads, pads_count); +} - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]); - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]); - writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]); +static struct ddrmc_phy_setting default_phy_settings[] = { + { DDRMC_PHY_DQ_TIMING, 0 }, + { DDRMC_PHY_DQ_TIMING, 16 }, + { DDRMC_PHY_DQ_TIMING, 32 }, - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]); - writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]); + { DDRMC_PHY_DQS_TIMING, 1 }, + { DDRMC_PHY_DQS_TIMING, 17 }, - writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]); - writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]); - writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]); + { DDRMC_PHY_CTRL, 2 }, + { DDRMC_PHY_CTRL, 18 }, + { DDRMC_PHY_CTRL, 34 }, - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]); - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]); - writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]); + { DDRMC_PHY_MASTER_CTRL, 3 }, + { DDRMC_PHY_MASTER_CTRL, 19 }, + { DDRMC_PHY_MASTER_CTRL, 35 }, - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]); - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]); - writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]); + { DDRMC_PHY_SLAVE_CTRL, 4 }, + { DDRMC_PHY_SLAVE_CTRL, 20 }, + { DDRMC_PHY_SLAVE_CTRL, 36 }, /* LPDDR2 only parameter */ - writel(DDRMC_PHY_OFF, &ddrmr->phy[49]); + { DDRMC_PHY_OFF, 49 }, - writel(DDRMC_PHY50_DDR3_MODE | - DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]); + { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 }, /* Processor Pad ODT settings */ - writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]); -} - -static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl) -{ - struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; - u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0; + { DDRMC_PHY_PROC_PAD_ODT, 52 }, - if (lvl->wrlvl_reg_en) { - writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]); - writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]); - writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]); - } - - if (lvl->rdlvl_reg_en) { - cr102 |= DDRMC_CR102_RDLVL_REG_EN; - cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0); - cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1); - } - - if (lvl->rdlvl_gt_reg_en) { - cr102 |= DDRMC_CR102_RDLVL_GT_REGEN; - cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0); - cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1); - } - - writel(cr102, &ddrmr->cr[102]); - writel(cr105, &ddrmr->cr[105]); - writel(cr106, &ddrmr->cr[106]); - writel(cr110, &ddrmr->cr[110]); -} + /* end marker */ + { 0, -1 } +}; void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, - struct ddrmc_lvl_info *lvl, - int col_diff, int row_diff) + struct ddrmc_cr_setting *board_cr_settings, + struct ddrmc_phy_setting *board_phy_settings, + int col_diff, int row_diff) { struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; + struct ddrmc_cr_setting *cr_setting; + struct ddrmc_phy_setting *phy_setting; writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); @@ -144,7 +122,9 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, writel(DDRMC_CR12_WRLAT(timings->wrlat) | DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) | - DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]); + DDRMC_CR13_TCCD(timings->tccd) | + DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval), + &ddrmr->cr[13]); writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | DDRMC_CR14_TWTR(timings->twtr) | DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]); @@ -156,18 +136,19 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); - writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | - DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]); + writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN | + DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout), + &ddrmr->cr[21]); writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]); - writel(DDRMC_CR23_BSTLEN(3) | + writel(DDRMC_CR23_BSTLEN(timings->bstlen) | DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]); writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]); writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); writel(DDRMC_CR26_TREF(timings->tref) | DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]); - writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]); + writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]); writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]); writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]); @@ -177,7 +158,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, writel(DDRMC_CR34_CKSRX(timings->cksrx) | DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]); - writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]); + writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]); writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) | DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); @@ -191,13 +172,14 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]); - writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]); + writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]); writel(DDRMC_CR73_APREBIT(timings->aprebit) | DDRMC_CR73_COL_DIFF(col_diff) | DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]); writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN | - DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64), + DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) | + DDRMC_CR74_AGE_CNT(timings->age_cnt), &ddrmr->cr[74]); writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN | DDRMC_CR75_PLEN, &ddrmr->cr[75]); @@ -205,13 +187,15 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE | DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); - writel(DDRMC_CR78_Q_FULLNESS(7) | + writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) | DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); - writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]); + writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) | + DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0), + &ddrmr->cr[87]); writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); @@ -219,58 +203,33 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, writel(DDRMC_CR96_WLMRD(timings->wlmrd) | DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]); - if (lvl != NULL) - ddrmc_ctrl_lvl_init(lvl); - - writel(DDRMC_CR117_AXI0_W_PRI(0) | - DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]); - writel(DDRMC_CR118_AXI1_W_PRI(1) | - DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]); - - writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | - DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]); - writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | - DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]); - writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | - DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]); - writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | - DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]); - writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]); - - writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]); - writel(DDRMC_CR132_WRLAT_ADJ(5) | - DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]); - writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]); - writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | - DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]); - writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | - DDRMC_CR139_PHY_WRLV_DLL(3) | - DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]); - writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]); - writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | - DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]); - writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | - DDRMC_CR144_PHY_RDLV_DLL(3) | - DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]); - writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]); - writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]); - writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]); - writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]); - writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | - DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]); - - writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | - DDRMC_CR154_PAD_ZQ_MODE(1) | - DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | - DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]); - writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | - DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]); - writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]); - writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | - DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]); - - ddrmc_phy_init(); + /* execute custom CR setting sequence (may be NULL) */ + cr_setting = board_cr_settings; + if (cr_setting != NULL) + while (cr_setting->cr_rnum >= 0) { + writel(cr_setting->setting, + &ddrmr->cr[cr_setting->cr_rnum]); + cr_setting++; + } + + /* perform default PHY settings (may be overriden by custom settings */ + phy_setting = default_phy_settings; + while (phy_setting->phy_rnum >= 0) { + writel(phy_setting->setting, + &ddrmr->phy[phy_setting->phy_rnum]); + phy_setting++; + } + + /* execute custom PHY setting sequence (may be NULL) */ + phy_setting = board_phy_settings; + if (phy_setting != NULL) + while (phy_setting->phy_rnum >= 0) { + writel(phy_setting->setting, + &ddrmr->phy[phy_setting->phy_rnum]); + phy_setting++; + } + /* all inits done, start the DDR controller */ writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); while (!(readl(&ddrmr->cr[80]) && 0x100)) diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index acbec46cb8..a129dd4ee0 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -1,20 +1,50 @@ /* - * This is a copy of omap3/spl.h: - * - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_ARCH_SPL_H_ -#define BOOT_DEVICE_NONE 0 -#define BOOT_DEVICE_XIP 1 -#define BOOT_DEVICE_NAND 2 -#define BOOT_DEVICE_ONE_NAND 3 -#define BOOT_DEVICE_MMC2 5 /*emmc*/ -#define BOOT_DEVICE_MMC1 6 -#define BOOT_DEVICE_XIPWAIT 7 -#define BOOT_DEVICE_MMC2_2 0xff +#define BOOT0_MAGIC "eGON.BT0" +#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ +#define SPL_HEADER_VERSION 1 + +/* Note: A80 will require special handling here: SPL_ADDR 0x10000 */ +#define SPL_ADDR 0x0 + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + uint32_t b_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + uint32_t check_sum; /* generated by PC */ + uint32_t length; /* generated by PC */ + /* + * We use a simplified header, only filling in what is needed + * by the boot ROM. To be compatible with Allwinner tools we + * would need to implement the proper fields here instead of + * padding. + * + * Actually we want the ability to recognize our "sunxi" variant + * of the SPL. To do so, let's place a special signature into the + * "pub_head_size" field. We can reasonably expect Allwinner's + * boot0 to always have the upper 16 bits of this set to 0 (after + * all the value shouldn't be larger than the limit imposed by + * SRAM size). + * If the signature is present (at 0x14), then we know it's safe + * to use the remaining 8 bytes (at 0x18) for our own purposes. + * (E.g. sunxi-tools "fel" utility can pass information there.) + */ + union { + uint32_t pub_head_size; + uint8_t spl_signature[4]; + }; + uint32_t fel_script_address; + uint32_t reserved; /* padding, align to 32 bytes */ +}; + +#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) + #endif diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h index 6730cde1b8..9022c465a0 100644 --- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h +++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h @@ -11,18 +11,6 @@ #ifndef __ASM_ARCH_VF610_DDRMC_H #define __ASM_ARCH_VF610_DDRMC_H -struct ddrmc_lvl_info { - u16 wrlvl_reg_en; - u16 wrlvl_dl_0; - u16 wrlvl_dl_1; - u16 rdlvl_gt_reg_en; - u16 rdlvl_gt_dl_0; - u16 rdlvl_gt_dl_1; - u16 rdlvl_reg_en; - u16 rdlvl_dl_0; - u16 rdlvl_dl_1; -}; - struct ddr3_jedec_timings { u8 tinit; u32 trst_pwron; @@ -32,6 +20,7 @@ struct ddr3_jedec_timings { u8 trc; u8 trrd; u8 tccd; + u8 tbst_int_interval; u8 tfaw; u8 trp; u8 twtr; @@ -43,30 +32,51 @@ struct ddr3_jedec_timings { u8 tckesr; u8 tcke; u8 trcd_int; + u8 tras_lockout; u8 tdal; + u8 bstlen; u16 tdll; u8 trp_ab; u16 tref; u8 trfc; + u16 tref_int; u8 tpdex; u8 txpdll; u8 txsnr; u16 txsr; u8 cksrx; u8 cksre; + u8 freq_chg_en; u16 zqcl; u16 zqinit; u8 zqcs; u8 ref_per_zq; + u8 zqcs_rotate; u8 aprebit; + u8 cmd_age_cnt; + u8 age_cnt; + u8 q_fullness; + u8 odt_rd_mapcs0; + u8 odt_wr_mapcs0; u8 wlmrd; u8 wldqsen; }; -void ddrmc_setup_iomux(void); +struct ddrmc_cr_setting { + u32 setting; + int cr_rnum; /* CR register ; -1 for last entry */ +}; + +struct ddrmc_phy_setting { + u32 setting; + int phy_rnum; /* PHY register ; -1 for last entry */ +}; + +void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count); void ddrmc_phy_init(void); void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, - struct ddrmc_lvl_info *lvl, - int col_diff, int row_diff); + struct ddrmc_cr_setting *board_cr_settings, + struct ddrmc_phy_setting *board_phy_settings, + int col_diff, int row_diff); #endif diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 436698588c..9758323433 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -148,7 +148,7 @@ #define DDRMC_CR18_TCKE(v) ((v) & 0x7) #define DDRMC_CR20_AP_EN (1 << 24) #define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16) -#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8) +#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8) #define DDRMC_CR21_CCMAP_EN 1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) @@ -200,8 +200,8 @@ #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) #define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) #define DDRMC_CR82_INT_MASK 0x10000000 -#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) -#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) +#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24) +#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16) #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index ea83e21d43..efd4d04ea8 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -214,32 +214,40 @@ static void setup_usb_phys(void) int arch_cpu_init(void) { -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X) + /* + * Only with disabled MMU its possible to switch the base + * register address on Armada 38x. Without this the SDRAM + * located at >= 0x4000.0000 is also not accessible, as its + * still locked to cache. + */ + mmu_disable(); +#endif + + /* Linux expects the internal registers to be at 0xf1000000 */ + writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); + set_cbar(SOC_REGS_PHY_BASE + 0xC000); + +#if !defined(CONFIG_SPL_BUILD) + /* + * From this stage on, the SoC detection is working. As we have + * configured the internal register base to the value used + * in the macros / defines in the U-Boot header (soc.h). + */ if (mvebu_soc_family() == MVEBU_SOC_A38X) { struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; /* - * Only with disabled MMU its possible to switch the base - * register address on Armada 38x. Without this the SDRAM - * located at >= 0x4000.0000 is also not accessible, as its - * still locked to cache. - * - * So to fully release / unlock this area from cache, we need - * to first flush all caches, then disable the MMU and - * disable the L2 cache. + * To fully release / unlock this area from cache, we need + * to flush all caches and disable the L2 cache. */ icache_disable(); dcache_disable(); - mmu_disable(); clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } #endif - /* Linux expects the internal registers to be at 0xf1000000 */ - writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); - set_cbar(SOC_REGS_PHY_BASE + 0xC000); - /* * We need to call mvebu_mbus_probe() before calling * update_sdram_window_sizes() as it disables all previously diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c index c516c419ed..5449a8926c 100644 --- a/arch/arm/mach-mvebu/timer.c +++ b/arch/arm/mach-mvebu/timer.c @@ -41,7 +41,7 @@ #define timestamp gd->arch.tbl #define lastdec gd->arch.lastinc -static int init_done; +static int init_done __attribute__((section(".data"))) = 0; /* Timer reload and current value registers */ struct kwtmr_val { diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 28552fa15a..e51ca96eb7 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -72,9 +72,10 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) entries[num_entries].type = E820_RAM; else if (res_desc->type == RES_MEM_RESERVED) entries[num_entries].type = E820_RESERVED; + + num_entries++; } hdr = get_next_hob(hdr); - num_entries++; } /* Mark PCIe ECAM address range as reserved */ diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c index 4160acdcc9..78349317e0 100644 --- a/board/freescale/vf610twr/vf610twr.c +++ b/board/freescale/vf610twr/vf610twr.c @@ -28,63 +28,117 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) +static struct ddrmc_cr_setting vf610twr_cr_settings[] = { + /* levelling */ + { DDRMC_CR97_WRLVL_EN, 97 }, + { DDRMC_CR98_WRLVL_DL_0(0), 98 }, + { DDRMC_CR99_WRLVL_DL_1(0), 99 }, + { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, + { DDRMC_CR105_RDLVL_DL_0(0), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, + { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, + /* AXI */ + { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, + { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, + { DDRMC_CR120_AXI0_PRI1_RPRI(2) | + DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, + { DDRMC_CR121_AXI0_PRI3_RPRI(2) | + DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, + { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | + DDRMC_CR122_AXI0_PRIRLX(100), 122 }, + { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, + { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, + { DDRMC_CR126_PHY_RDLAT(8), 126 }, + { DDRMC_CR132_WRLAT_ADJ(5) | + DDRMC_CR132_RDLAT_ADJ(6), 132 }, + { DDRMC_CR137_PHYCTL_DL(2), 137 }, + { DDRMC_CR138_PHY_WRLV_MXDL(256) | + DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, + { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | + DDRMC_CR139_PHY_WRLV_DLL(3) | + DDRMC_CR139_PHY_WRLV_EN(3), 139 }, + { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, + { DDRMC_CR143_RDLV_GAT_MXDL(1536) | + DDRMC_CR143_RDLV_MXDL(128), 143 }, + { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | + DDRMC_CR144_PHY_RDLV_EN(3), 144 }, + { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, + { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, + { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, + { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, + { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, + + { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, + { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, + { DDRMC_CR158_TWR(6), 158 }, + { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), 161 }, + /* end marker */ + { 0, -1 } +}; + int dram_init(void) { - struct ddrmc_lvl_info lvl = { - .wrlvl_reg_en = 1, - .wrlvl_dl_0 = 0, - .wrlvl_dl_1 = 0, - .rdlvl_gt_reg_en = 1, - .rdlvl_gt_dl_0 = 4, - .rdlvl_gt_dl_1 = 4, - .rdlvl_reg_en = 1, - .rdlvl_dl_0 = 0, - .rdlvl_dl_1 = 0, - }; - static const struct ddr3_jedec_timings timings = { - .tinit = 5, - .trst_pwron = 80000, - .cke_inactive = 200000, - .wrlat = 5, - .caslat_lin = 12, - .trc = 21, - .trrd = 4, - .tccd = 4, - .tfaw = 20, - .trp = 6, - .twtr = 4, - .tras_min = 15, - .tmrd = 4, - .trtp = 4, - .tras_max = 28080, - .tmod = 12, - .tckesr = 4, - .tcke = 3, - .trcd_int = 6, - .tdal = 12, - .tdll = 512, - .trp_ab = 6, - .tref = 3120, - .trfc = 44, - .tpdex = 3, - .txpdll = 10, - .txsnr = 48, - .txsr = 468, - .cksrx = 5, - .cksre = 5, - .zqcl = 256, - .zqinit = 512, - .zqcs = 64, - .ref_per_zq = 64, - .aprebit = 10, - .wlmrd = 40, - .wldqsen = 25, + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 21, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 0, + .tfaw = 20, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 28080, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 0, + .tdal = 12, + .bstlen = 0, + .tdll = 512, + .trp_ab = 6, + .tref = 3120, + .trfc = 44, + .tref_int = 0, + .tpdex = 3, + .txpdll = 10, + .txsnr = 48, + .txsr = 468, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 0, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 0, + .aprebit = 10, + .cmd_age_cnt = 64, + .age_cnt = 64, + .q_fullness = 7, + .odt_rd_mapcs0 = 0, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, }; - ddrmc_setup_iomux(); + ddrmc_setup_iomux(NULL, 0); - ddrmc_ctrl_init_ddr3(&timings, &lvl, 1, 3); + ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig new file mode 100644 index 0000000000..d67a69a747 --- /dev/null +++ b/board/phytec/pcm052/Kconfig @@ -0,0 +1,15 @@ +if TARGET_PCM052 + +config SYS_BOARD + default "pcm052" + +config SYS_VENDOR + default "phytec" + +config SYS_SOC + default "vf610" + +config SYS_CONFIG_NAME + default "pcm052" + +endif diff --git a/board/phytec/pcm052/MAINTAINERS b/board/phytec/pcm052/MAINTAINERS new file mode 100644 index 0000000000..a877436bd3 --- /dev/null +++ b/board/phytec/pcm052/MAINTAINERS @@ -0,0 +1,6 @@ +PCM052 BOARD +M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> +S: Maintained +F: board/phytec/pcm052/ +F: include/configs/pcm052.h +F: configs/pcm052_defconfig diff --git a/board/phytec/pcm052/Makefile b/board/phytec/pcm052/Makefile new file mode 100644 index 0000000000..144f4e7316 --- /dev/null +++ b/board/phytec/pcm052/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pcm052.o diff --git a/board/phytec/pcm052/imximage.cfg b/board/phytec/pcm052/imximage.cfg new file mode 100644 index 0000000000..f5a97475cb --- /dev/null +++ b/board/phytec/pcm052/imximage.cfg @@ -0,0 +1,17 @@ +/* + * Copyright 2015 3ADEV <http://www.3adev.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include <asm/imx-common/imximage.cfg> + +/* image version */ +IMAGE_VERSION 2 + +/* Boot Offset 0x400, valid for both SD and NAND boot */ +BOOT_OFFSET FLASH_OFFSET_STANDARD diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c new file mode 100644 index 0000000000..e4f61e1b92 --- /dev/null +++ b/board/phytec/pcm052/pcm052.c @@ -0,0 +1,515 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-vf610.h> +#include <asm/arch/ddrmc-vf610.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h + * do not match our settings. Let us (re)define our own settings here. + */ + +#define PCM052_VF610_DDR_PAD_CTRL PAD_CTL_DSE_20ohm +#define PCM052_VF610_DDR_PAD_CTRL_1 (PAD_CTL_DSE_20ohm | \ + PAD_CTL_INPUT_DIFFERENTIAL) +#define PCM052_VF610_DDR_RESET_PAD_CTL (PAD_CTL_DSE_150ohm | \ + PAD_CTL_PUS_100K_UP | \ + PAD_CTL_INPUT_DIFFERENTIAL) + +enum { + PCM052_VF610_PAD_DDR_RESETB = IOMUX_PAD(0x021c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_RESET_PAD_CTL), + PCM052_VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_A0__DDR_A_0 = IOMUX_PAD(0x025c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), + PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), + PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL_1), + PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 = IOMUX_PAD(0x02dc, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), + PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 = IOMUX_PAD(0x02e0, __NA_, 0, __NA_, 0, PCM052_VF610_DDR_PAD_CTRL), +}; + +static struct ddrmc_cr_setting pcm052_cr_settings[] = { + /* not in the datasheets, but in the original code */ + { 0x00002000, 105 }, + { 0x00000020, 110 }, + /* AXI */ + { DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1), 117 }, + { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, + { DDRMC_CR120_AXI0_PRI1_RPRI(2) | + DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, + { DDRMC_CR121_AXI0_PRI3_RPRI(2) | + DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, + { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | + DDRMC_CR122_AXI0_PRIRLX(100), 122 }, + { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, + { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, + { DDRMC_CR126_PHY_RDLAT(11), 126 }, + { DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6), 132 }, + { DDRMC_CR137_PHYCTL_DL(2), 137 }, + { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | + DDRMC_CR139_PHY_WRLV_DLL(3) | + DDRMC_CR139_PHY_WRLV_EN(3), 139 }, + { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(0), 154 }, + { DDRMC_CR155_PAD_ODT_BYTE1(5) | DDRMC_CR155_PAD_ODT_BYTE0(5), 155 }, + { DDRMC_CR158_TWR(6), 158 }, + { DDRMC_CR161_ODT_EN(0) | DDRMC_CR161_TODTH_RD(0) | + DDRMC_CR161_TODTH_WR(6), 161 }, + /* end marker */ + { 0, -1 } +}; + +/* PHY settings -- most of them differ from default in imx-regs.h */ + +#define PCM052_DDRMC_PHY_DQ_TIMING 0x00002213 +#define PCM052_DDRMC_PHY_CTRL 0x00290000 +#define PCM052_DDRMC_PHY_SLAVE_CTRL 0x00002c00 +#define PCM052_DDRMC_PHY_PROC_PAD_ODT 0x00010020 + +static struct ddrmc_phy_setting pcm052_phy_settings[] = { + { PCM052_DDRMC_PHY_DQ_TIMING, 0 }, + { PCM052_DDRMC_PHY_DQ_TIMING, 16 }, + { PCM052_DDRMC_PHY_DQ_TIMING, 32 }, + { PCM052_DDRMC_PHY_DQ_TIMING, 48 }, + { DDRMC_PHY_DQS_TIMING, 1 }, + { DDRMC_PHY_DQS_TIMING, 17 }, + { DDRMC_PHY_DQS_TIMING, 33 }, + { DDRMC_PHY_DQS_TIMING, 49 }, + { PCM052_DDRMC_PHY_CTRL, 2 }, + { PCM052_DDRMC_PHY_CTRL, 18 }, + { PCM052_DDRMC_PHY_CTRL, 34 }, + { DDRMC_PHY_MASTER_CTRL, 3 }, + { DDRMC_PHY_MASTER_CTRL, 19 }, + { DDRMC_PHY_MASTER_CTRL, 35 }, + { PCM052_DDRMC_PHY_SLAVE_CTRL, 4 }, + { PCM052_DDRMC_PHY_SLAVE_CTRL, 20 }, + { PCM052_DDRMC_PHY_SLAVE_CTRL, 36 }, + { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 }, + { PCM052_DDRMC_PHY_PROC_PAD_ODT, 52 }, + + /* end marker */ + { 0, -1 } +}; + +int dram_init(void) +{ + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 4, + .tfaw = 18, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 14040, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 10, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 1542, + .trfc = 64, + .tref_int = 5, + .tpdex = 3, + .txpdll = 10, + .txsnr = 68, + .txsr = 506, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; + + static const iomux_v3_cfg_t pcm052_pads[] = { + PCM052_VF610_PAD_DDR_A15__DDR_A_15, + PCM052_VF610_PAD_DDR_A14__DDR_A_14, + PCM052_VF610_PAD_DDR_A13__DDR_A_13, + PCM052_VF610_PAD_DDR_A12__DDR_A_12, + PCM052_VF610_PAD_DDR_A11__DDR_A_11, + PCM052_VF610_PAD_DDR_A10__DDR_A_10, + PCM052_VF610_PAD_DDR_A9__DDR_A_9, + PCM052_VF610_PAD_DDR_A8__DDR_A_8, + PCM052_VF610_PAD_DDR_A7__DDR_A_7, + PCM052_VF610_PAD_DDR_A6__DDR_A_6, + PCM052_VF610_PAD_DDR_A5__DDR_A_5, + PCM052_VF610_PAD_DDR_A4__DDR_A_4, + PCM052_VF610_PAD_DDR_A3__DDR_A_3, + PCM052_VF610_PAD_DDR_A2__DDR_A_2, + PCM052_VF610_PAD_DDR_A1__DDR_A_1, + PCM052_VF610_PAD_DDR_A0__DDR_A_0, + PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, + PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, + PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, + PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, + PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, + PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, + PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, + PCM052_VF610_PAD_DDR_D15__DDR_D_15, + PCM052_VF610_PAD_DDR_D14__DDR_D_14, + PCM052_VF610_PAD_DDR_D13__DDR_D_13, + PCM052_VF610_PAD_DDR_D12__DDR_D_12, + PCM052_VF610_PAD_DDR_D11__DDR_D_11, + PCM052_VF610_PAD_DDR_D10__DDR_D_10, + PCM052_VF610_PAD_DDR_D9__DDR_D_9, + PCM052_VF610_PAD_DDR_D8__DDR_D_8, + PCM052_VF610_PAD_DDR_D7__DDR_D_7, + PCM052_VF610_PAD_DDR_D6__DDR_D_6, + PCM052_VF610_PAD_DDR_D5__DDR_D_5, + PCM052_VF610_PAD_DDR_D4__DDR_D_4, + PCM052_VF610_PAD_DDR_D3__DDR_D_3, + PCM052_VF610_PAD_DDR_D2__DDR_D_2, + PCM052_VF610_PAD_DDR_D1__DDR_D_1, + PCM052_VF610_PAD_DDR_D0__DDR_D_0, + PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, + PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, + PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, + PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, + PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, + PCM052_VF610_PAD_DDR_WE__DDR_WE_B, + PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, + PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, + PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, + PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, + PCM052_VF610_PAD_DDR_RESETB, + }; + + imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + + ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, 2); + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static void setup_iomux_uart(void) +{ + static const iomux_v3_cfg_t uart1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) + +static void setup_iomux_enet(void) +{ + static const iomux_v3_cfg_t enet0_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), + }; + + imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); +} + +/* + * I2C2 is the only I2C used, on pads PTA22/PTA23. + */ + +static void setup_iomux_i2c(void) +{ + static const iomux_v3_cfg_t i2c_pads[] = { + VF610_PAD_PTA22__I2C2_SCL, + VF610_PAD_PTA23__I2C2_SDA, + }; + + imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); +} + +#ifdef CONFIG_NAND_VF610_NFC +static void setup_iomux_nfc(void) +{ + static const iomux_v3_cfg_t nfc_pads[] = { + VF610_PAD_PTD31__NF_IO15, + VF610_PAD_PTD30__NF_IO14, + VF610_PAD_PTD29__NF_IO13, + VF610_PAD_PTD28__NF_IO12, + VF610_PAD_PTD27__NF_IO11, + VF610_PAD_PTD26__NF_IO10, + VF610_PAD_PTD25__NF_IO9, + VF610_PAD_PTD24__NF_IO8, + VF610_PAD_PTD23__NF_IO7, + VF610_PAD_PTD22__NF_IO6, + VF610_PAD_PTD21__NF_IO5, + VF610_PAD_PTD20__NF_IO4, + VF610_PAD_PTD19__NF_IO3, + VF610_PAD_PTD18__NF_IO2, + VF610_PAD_PTD17__NF_IO1, + VF610_PAD_PTD16__NF_IO0, + VF610_PAD_PTB24__NF_WE_B, + VF610_PAD_PTB25__NF_CE0_B, + VF610_PAD_PTB27__NF_RE_B, + VF610_PAD_PTC26__NF_RB_B, + VF610_PAD_PTC27__NF_ALE, + VF610_PAD_PTC28__NF_CLE + }; + + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); +} +#endif + +static void setup_iomux_qspi(void) +{ + static const iomux_v3_cfg_t qspi0_pads[] = { + VF610_PAD_PTD0__QSPI0_A_QSCK, + VF610_PAD_PTD1__QSPI0_A_CS0, + VF610_PAD_PTD2__QSPI0_A_DATA3, + VF610_PAD_PTD3__QSPI0_A_DATA2, + VF610_PAD_PTD4__QSPI0_A_DATA1, + VF610_PAD_PTD5__QSPI0_A_DATA0, + VF610_PAD_PTD7__QSPI0_B_QSCK, + VF610_PAD_PTD8__QSPI0_B_CS0, + VF610_PAD_PTD9__QSPI0_B_DATA3, + VF610_PAD_PTD10__QSPI0_B_DATA2, + VF610_PAD_PTD11__QSPI0_B_DATA1, + VF610_PAD_PTD12__QSPI0_B_DATA0, + }; + + imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); +} + +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) + +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {ESDHC1_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* eSDHC1 is always present */ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + static const iomux_v3_cfg_t esdhc1_pads[] = { + NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), + NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), + }; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + imx_iomux_v3_setup_multiple_pads( + esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} + +static void clock_init(void) +{ + struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; + struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; + + clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, + CCM_CCGR0_UART1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, + CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, + CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | + CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | + CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | + CCM_CCGR2_QSPI0_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, + CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, + CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | + CCM_CCGR4_GPC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, + CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, + CCM_CCGR7_SDHC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, + CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); + clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, + CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); + + clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, + ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); + clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, + ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); + + clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, + CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); + clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, + CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | + CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | + CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | + CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | + CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | + CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); + clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, + CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | + CCM_CACRR_ARM_CLK_DIV(0)); + clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, + CCM_CSCMR1_ESDHC1_CLK_SEL(3) | + CCM_CSCMR1_QSPI0_CLK_SEL(3) | + CCM_CSCMR1_NFC_CLK_SEL(0)); + clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, + CCM_CSCDR1_RMII_CLK_EN); + clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, + CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | + CCM_CSCDR2_NFC_EN); + clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, + CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | + CCM_CSCDR3_QSPI0_X2_DIV(1) | + CCM_CSCDR3_QSPI0_X4_DIV(3) | + CCM_CSCDR3_NFC_PRE_DIV(5)); + clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, + CCM_CSCMR2_RMII_CLK_SEL(0)); +} + +static void mscm_init(void) +{ + struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; + int i; + + for (i = 0; i < MSCM_IRSPRC_NUM; i++) + writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + clock_init(); + mscm_init(); + setup_iomux_uart(); + setup_iomux_enet(); + setup_iomux_i2c(); + setup_iomux_qspi(); + setup_iomux_nfc(); + + return 0; +} + +int board_init(void) +{ + struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Enable external 32K Oscillator + * + * The internal clock experiences significant drift + * so we must use the external oscillator in order + * to maintain correct time in the hwclock + */ + setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); + + return 0; +} + +int checkboard(void) +{ + puts("Board: PCM-052\n"); + + return 0; +} diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 2d424882a9..d82f1b73a7 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -90,7 +90,8 @@ static void smartweb_macb_hw_init(void) pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), &pioa->pudr); at91_phy_reset(); @@ -101,7 +102,8 @@ static void smartweb_macb_hw_init(void) pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), + pin_to_mask(AT91_PIN_PA28) | + pin_to_mask(AT91_PIN_PA29), &pioa->puer); /* Initialize EMAC=MACB hardware */ @@ -141,13 +143,6 @@ int board_early_init_f(void) int board_init(void) { - /* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - smartweb_nand_hw_init(); -#ifdef CONFIG_MACB - smartweb_macb_hw_init(); -#endif /* power LED red */ at91_set_gpio_output(AT91_PIN_PC6, 0); at91_set_gpio_output(AT91_PIN_PC7, 1); @@ -163,6 +158,13 @@ int board_init(void) at91_udc_probe(&board_udc_data); #endif + /* Adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + smartweb_nand_hw_init(); +#ifdef CONFIG_MACB + smartweb_macb_hw_init(); +#endif return 0; } @@ -197,6 +199,7 @@ void matrix_init(void) void spl_board_init(void) { + /* power LED orange */ at91_set_gpio_output(AT91_PIN_PC6, 1); at91_set_gpio_output(AT91_PIN_PC7, 1); /* alarm LED orange */ @@ -212,8 +215,8 @@ void spl_board_init(void) /* check if both button are pressed */ if (at91_get_gpio_value(AT91_PIN_PA28) == 0 && - at91_get_gpio_value(AT91_PIN_PA29) == 0) { - debug("Recovery button pressed\n"); + at91_get_gpio_value(AT91_PIN_PA29) == 0) { + smartweb_nand_hw_init(); nand_init(); spl_nand_erase_one(0, 0); } diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 8f95867fa6..f7a837a6eb 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -20,8 +20,6 @@ F: configs/mk802ii_defconfig F: configs/pov_protab2_ips9_defconfig F: include/configs/sun5i.h F: configs/A10s-OLinuXino-M_defconfig -F: configs/A10s-OLinuXino-M_defconfig -F: configs/A10s-Wobo-i5_defconfig F: configs/A13-OLinuXino_defconfig F: configs/A13-OLinuXinoM_defconfig F: configs/Auxtek-T003_defconfig @@ -35,6 +33,7 @@ F: include/configs/sun6i.h F: configs/CSQ_CS908_defconfig F: configs/Mele_A1000G_quad_defconfig F: configs/Mele_M9_defconfig +F: configs/Wobo_i5_defconfig F: include/configs/sun7i.h F: configs/A20-OLinuXino_MICRO_defconfig F: configs/Bananapi_defconfig @@ -51,6 +50,8 @@ F: configs/ga10h_v1_1_defconfig F: configs/gt90h_v4_defconfig F: configs/Ippo_q8h_v1_2_defconfig F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig +F: configs/q8_a33_tablet_800x480_defconfig +F: configs/q8_a33_tablet_1024x600_defconfig F: include/configs/sun9i.h F: configs/Merrii_A80_Optimus_defconfig diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 9c855f604d..096d12791c 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -516,6 +516,31 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif +#if !defined(CONFIG_SPL_BUILD) +#include <asm/arch/spl.h> + +/* + * Check the SPL header for the "sunxi" variant. If found: parse values + * that might have been passed by the loader ("fel" utility), and update + * the environment accordingly. + */ +static void parse_spl_header(const uint32_t spl_addr) +{ + struct boot_file_head *spl = (void *)spl_addr; + if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { + uint8_t spl_header_version = spl->spl_signature[3]; + if (spl_header_version == SPL_HEADER_VERSION) { + if (spl->fel_script_address) + setenv_hex("fel_scriptaddr", + spl->fel_script_address); + return; + } + printf("sunxi SPL version mismatch: expected %u, got %u\n", + SPL_HEADER_VERSION, spl_header_version); + } +} +#endif + #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { @@ -524,6 +549,16 @@ int misc_init_r(void) uint8_t mac_addr[6]; int ret; +#if !defined(CONFIG_SPL_BUILD) + setenv("fel_booted", NULL); + setenv("fel_scriptaddr", NULL); + /* determine if we are running in FEL mode */ + if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ + setenv("fel_booted", "1"); + parse_spl_header(SPL_ADDR); + } +#endif + ret = sunxi_get_sid(sid); if (ret == 0 && sid[0] != 0 && sid[3] != 0) { if (!getenv("ethaddr")) { diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index 8618fd068c..39bf0ac7d6 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -35,6 +35,61 @@ DECLARE_GLOBAL_DATA_PTR; #define USB_PEN_GPIO 83 +static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { + /* levelling */ + { DDRMC_CR97_WRLVL_EN, 97 }, + { DDRMC_CR98_WRLVL_DL_0(0), 98 }, + { DDRMC_CR99_WRLVL_DL_1(0), 99 }, + { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, + { DDRMC_CR105_RDLVL_DL_0(0), 105 }, + { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, + { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, + /* AXI */ + { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, + { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, + { DDRMC_CR120_AXI0_PRI1_RPRI(2) | + DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, + { DDRMC_CR121_AXI0_PRI3_RPRI(2) | + DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, + { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | + DDRMC_CR122_AXI0_PRIRLX(100), 122 }, + { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | + DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, + { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, + { DDRMC_CR126_PHY_RDLAT(8), 126 }, + { DDRMC_CR132_WRLAT_ADJ(5) | + DDRMC_CR132_RDLAT_ADJ(6), 132 }, + { DDRMC_CR137_PHYCTL_DL(2), 137 }, + { DDRMC_CR138_PHY_WRLV_MXDL(256) | + DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, + { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | + DDRMC_CR139_PHY_WRLV_DLL(3) | + DDRMC_CR139_PHY_WRLV_EN(3), 139 }, + { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, + { DDRMC_CR143_RDLV_GAT_MXDL(1536) | + DDRMC_CR143_RDLV_MXDL(128), 143 }, + { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | + DDRMC_CR144_PHY_RDLV_DLL(3) | + DDRMC_CR144_PHY_RDLV_EN(3), 144 }, + { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, + { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, + { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, + { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, + { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | + DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, + + { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | + DDRMC_CR154_PAD_ZQ_MODE(1) | + DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | + DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, + { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, + { DDRMC_CR158_TWR(6), 158 }, + { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | + DDRMC_CR161_TODTH_WR(2), 161 }, + /* end marker */ + { 0, -1 } +}; + static const iomux_v3_cfg_t usb_pads[] = { VF610_PAD_PTD4__GPIO_83, }; @@ -42,48 +97,59 @@ static const iomux_v3_cfg_t usb_pads[] = { int dram_init(void) { static const struct ddr3_jedec_timings timings = { - .tinit = 5, - .trst_pwron = 80000, - .cke_inactive = 200000, - .wrlat = 5, - .caslat_lin = 12, - .trc = 21, - .trrd = 4, - .tccd = 4, - .tfaw = 20, - .trp = 6, - .twtr = 4, - .tras_min = 15, - .tmrd = 4, - .trtp = 4, - .tras_max = 28080, - .tmod = 12, - .tckesr = 4, - .tcke = 3, - .trcd_int = 6, - .tdal = 12, - .tdll = 512, - .trp_ab = 6, - .tref = 3120, - .trfc = 64, - .tpdex = 3, - .txpdll = 10, - .txsnr = 48, - .txsr = 468, - .cksrx = 5, - .cksre = 5, - .zqcl = 256, - .zqinit = 512, - .zqcs = 64, - .ref_per_zq = 64, - .aprebit = 10, - .wlmrd = 40, - .wldqsen = 25, + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 21, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 0, + .tfaw = 20, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 28080, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 0, + .tdal = 12, + .bstlen = 0, + .tdll = 512, + .trp_ab = 6, + .tref = 3120, + .trfc = 64, + .tref_int = 0, + .tpdex = 3, + .txpdll = 10, + .txsnr = 48, + .txsr = 468, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 0, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 0, + .aprebit = 10, + .cmd_age_cnt = 64, + .age_cnt = 64, + .q_fullness = 7, + .odt_rd_mapcs0 = 0, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, }; - ddrmc_setup_iomux(); + ddrmc_setup_iomux(NULL, 0); - ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2); + ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; diff --git a/common/bootm.c b/common/bootm.c index 667c93471b..c0d0d09411 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -474,7 +474,9 @@ ulong bootm_disable_interrupts(void) #ifdef CONFIG_NETCONSOLE /* Stop the ethernet stack if NetConsole could have left it up */ eth_halt(); +# ifndef CONFIG_DM_ETH eth_unregister(eth_get_dev()); +# endif #endif #if defined(CONFIG_CMD_USB) diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 794b727e50..898631d963 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -11,5 +11,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHC # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_NETCONSOLE=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index e56ca71ca2..e9909d97c1 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -13,5 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHC # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_NETCONSOLE=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/A10s-Wobo-i5_defconfig b/configs/Wobo_i5_defconfig index 206fd488cc..206fd488cc 100644 --- a/configs/A10s-Wobo-i5_defconfig +++ b/configs/Wobo_i5_defconfig diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 1c10124e85..21e85f3c66 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -1,4 +1,5 @@ CONFIG_X86=y +CONFIG_SYS_MALLOC_F_LEN=0x1800 CONFIG_VENDOR_GOOGLE=y CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" CONFIG_TARGET_CHROMEBOOK_LINK=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig new file mode 100644 index 0000000000..e8dc402878 --- /dev/null +++ b/configs/pcm052_defconfig @@ -0,0 +1,6 @@ +CONFIG_ARM=y +CONFIG_TARGET_PCM052=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES=y diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig new file mode 100644 index 0000000000..fbbf1286a5 --- /dev/null +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -0,0 +1,25 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=456 +CONFIG_DRAM_ZQ=15291 +CONFIG_MMC0_CD_PIN="PB4" +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH8" +CONFIG_AXP_GPIO=y +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER="PH7" +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_AXP221_DLDO1_VOLT=3300 +CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig new file mode 100644 index 0000000000..8e8aa92adf --- /dev/null +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -0,0 +1,25 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_A33=y +CONFIG_DRAM_CLK=456 +CONFIG_DRAM_ZQ=15291 +CONFIG_MMC0_CD_PIN="PB4" +CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" +CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" +CONFIG_USB0_ID_DET="PH8" +CONFIG_AXP_GPIO=y +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_DCLK_PHASE=0 +CONFIG_VIDEO_LCD_POWER="PH7" +CONFIG_VIDEO_LCD_BL_EN="PH6" +CONFIG_VIDEO_LCD_BL_PWM="PH0" +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_AXP221_DLDO1_VOLT=3300 +CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB_MUSB_HOST=y diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index f1056e21a2..0f977d706d 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -612,16 +612,22 @@ static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) /* * Register mxc i2c adapters */ +#ifdef CONFIG_SYS_I2C_MXC_I2C1 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C1_SPEED, CONFIG_SYS_MXC_I2C1_SLAVE, 0) +#endif + +#ifdef CONFIG_SYS_I2C_MXC_I2C2 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, mxc_i2c_set_bus_speed, CONFIG_SYS_MXC_I2C2_SPEED, CONFIG_SYS_MXC_I2C2_SLAVE, 1) +#endif + #ifdef CONFIG_SYS_I2C_MXC_I2C3 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, mxc_i2c_read, mxc_i2c_write, diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 25f18adb67..e717c44216 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -120,17 +120,27 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) /* determine delays */ if (hz <= 400000) { oclk_dly = 0; - sclk_dly = 7; + sclk_dly = 0; } else if (hz <= 25000000) { oclk_dly = 0; sclk_dly = 5; +#ifdef CONFIG_MACH_SUN9I } else if (hz <= 50000000) { - oclk_dly = 3; - sclk_dly = 5; + oclk_dly = 5; + sclk_dly = 4; } else { /* hz > 50000000 */ oclk_dly = 2; sclk_dly = 4; +#else + } else if (hz <= 50000000) { + oclk_dly = 3; + sclk_dly = 4; + } else { + /* hz > 50000000 */ + oclk_dly = 1; + sclk_dly = 4; +#endif } writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c index 5985534e5f..b0e07aa2d0 100644 --- a/drivers/mtd/nand/sunxi_nand_spl.c +++ b/drivers/mtd/nand/sunxi_nand_spl.c @@ -356,18 +356,32 @@ static int nand_read_buffer(uint32_t offs, unsigned int size, void *dest, int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) { +#if CONFIG_SYS_NAND_U_BOOT_OFFS == CONFIG_SPL_PAD_TO + /* + * u-boot-dtb.bin appended to SPL, use syndrome (like the BROM does) + * and try different erase block sizes to find the backup. + */ const uint32_t boot_offsets[] = { 0 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, 1 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, 2 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, 4 * 1024 * 1024 + CONFIG_SYS_NAND_U_BOOT_OFFS, }; - int i, syndrome; - - if (CONFIG_SYS_NAND_U_BOOT_OFFS == CONFIG_SPL_PAD_TO) - syndrome = 1; /* u-boot-dtb.bin appended to SPL */ - else - syndrome = 0; /* u-boot-dtb.bin on its own partition */ + const int syndrome = 1; +#else + /* + * u-boot-dtb.bin on its own partition, do not use syndrome, u-boot + * partition sits after 2 eraseblocks (spl, spl-backup), look for + * backup u-boot 1 erase block further. + */ + const uint32_t eraseblock_size = CONFIG_SYS_NAND_U_BOOT_OFFS / 2; + const uint32_t boot_offsets[] = { + CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_U_BOOT_OFFS + eraseblock_size, + }; + const int syndrome = 0; +#endif + int i; if (offs == CONFIG_SYS_NAND_U_BOOT_OFFS) { for (i = 0; i < ARRAY_SIZE(boot_offsets); i++) { diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 31042a6b6b..bf972dc39b 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -170,7 +170,11 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, static void nc_send_packet(const char *buf, int len) { +#ifdef CONFIG_DM_ETH + struct udevice *eth; +#else struct eth_device *eth; +#endif int inited = 0; uchar *pkt; uchar *ether; @@ -183,7 +187,7 @@ static void nc_send_packet(const char *buf, int len) return; if (!memcmp(nc_ether, net_null_ethaddr, 6)) { - if (eth->state == ETH_STATE_ACTIVE) + if (eth_is_active(eth)) return; /* inside net loop */ output_packet = buf; output_packet_len = len; @@ -194,7 +198,7 @@ static void nc_send_packet(const char *buf, int len) return; } - if (eth->state != ETH_STATE_ACTIVE) { + if (!eth_is_active(eth)) { if (eth_is_on_demand_init()) { if (eth_init() < 0) return; @@ -292,7 +296,11 @@ static int nc_stdio_getc(struct stdio_dev *dev) static int nc_stdio_tstc(struct stdio_dev *dev) { +#ifdef CONFIG_DM_ETH + struct udevice *eth; +#else struct eth_device *eth; +#endif if (input_recursion) return 0; @@ -301,7 +309,7 @@ static int nc_stdio_tstc(struct stdio_dev *dev) return 1; eth = eth_get_dev(); - if (eth && eth->state == ETH_STATE_ACTIVE) + if (eth_is_active(eth)) return 0; /* inside net loop */ input_recursion = 1; diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 65c731afb6..a6023f1033 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -571,7 +571,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, memset(dev, 0, sizeof(*dev)); dev->duplex = -1; - dev->link = 1; + dev->link = 0; dev->interface = interface; dev->autoneg = AUTONEG_ENABLE; diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 43fbdd3d11..49fbcac776 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -317,6 +317,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 20afdd6bc0..f03297e137 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -189,6 +189,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7f diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 3d6b0ae0c3..a5990cec03 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -53,6 +53,13 @@ #define CONFIG_CMD_DHCP #ifdef CONFIG_SYS_USE_MMC + +#ifdef CONFIG_ENV_IS_IN_MMC +/* Use raw reserved sectors to save environment */ +#define CONFIG_ENV_OFFSET 0x2000 +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else /* u-boot env in sd/mmc card */ #define CONFIG_ENV_IS_IN_FAT #define CONFIG_FAT_WRITE @@ -60,6 +67,7 @@ #define FAT_ENV_DEVICE_AND_PART "0" #define FAT_ENV_FILE "uboot.env" #define CONFIG_ENV_SIZE 0x4000 +#endif #define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \ "setenv dtb_name at91-${board_name}.dtb; " \ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 7158ab0f2b..e0aa4b0894 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -39,6 +39,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 12734a10bf..05132047b7 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -198,6 +198,8 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_MXC_I2C3_SPEED 400000 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 58cee96ac3..f55ba9f706 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -33,6 +33,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 5b4b011957..f646feefa9 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -52,6 +52,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ #define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 231bea7855..484d76305f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -107,6 +107,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 86f327c827..3bea71b969 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -38,6 +38,8 @@ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b44f3264e3..f73900fe30 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -389,6 +389,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 7dcb719b01..f6bd5fcece 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -275,6 +275,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* EEPROM */ diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 2dbb5f70a9..55b909ceac 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -97,6 +97,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 35058e222a..8853d8fcc0 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -172,6 +172,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ #endif diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index bd7216e47b..04140865f4 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -115,6 +115,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ /* RTC */ #define CONFIG_RTC_IMXDI diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index c9983f3f58..6bfdaa6432 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -42,6 +42,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 0479195d6d..b889c254cc 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -48,6 +48,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 82c8af802f..4f304ed89f 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -41,6 +41,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Configs */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index ad2629da72..3a65861e5e 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -76,6 +76,8 @@ /* I2C Configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* PMIC Controller */ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index bcdb054360..e46f2eeecb 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -38,6 +38,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* MMC Configs */ diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h index 11cf538b0a..1c998058a9 100644 --- a/include/configs/mx6qsabreauto.h +++ b/include/configs/mx6qsabreauto.h @@ -51,6 +51,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 2970b83109..9dcc64ea57 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -80,6 +80,10 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONFIG_CONSOLE_DEV "\0" \ + "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ + "dfu_alt_info_spl=spl raw 0x400\0" \ + "dfu_alt_info_img=u-boot raw 0x10000\0" \ + "dfu_alt_info=spl raw 0x400\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ @@ -244,6 +248,12 @@ #define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 + +/* USB Device Firmware Update support */ +#define CONFIG_CMD_DFU +#define CONFIG_USB_FUNCTION_DFU +#define CONFIG_DFU_MMC +#define CONFIG_DFU_SF #endif #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 5f635ca6c5..e9e3b27f36 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -44,6 +44,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 51b297a1a3..ae39503542 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -35,6 +35,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 381eaa24d5..edf7d3f93a 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -127,6 +127,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 465ddee881..d5faae6a7b 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -54,6 +54,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC only for 9X9 EVK */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index ada5de8aca..f16f9c1271 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -47,7 +47,7 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index dd4cb0f893..b1137713e1 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -43,6 +43,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID diff --git a/include/configs/novena.h b/include/configs/novena.h index 0970fd7548..cd426be18c 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -102,6 +102,8 @@ /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MXC diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 0d06fce1eb..426ec7246f 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -44,6 +44,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h new file mode 100644 index 0000000000..903f94c17e --- /dev/null +++ b/include/configs/pcm052.h @@ -0,0 +1,231 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for the phytec PCM-052 SoM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +#define CONFIG_VF610 + +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* Enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_FSL_LPUART +#define LPUART_BASE UART1_BASE + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_UART_PORT (1) +#define CONFIG_BAUDRATE 115200 + +#undef CONFIG_CMD_IMLS + +/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#ifdef CONFIG_CMD_NAND +#define CONFIG_USE_ARCH_MEMCPY +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR + +#define CONFIG_JFFS2_NAND + +/* UBI */ +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO + +/* Dynamic MTD partition support */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define MTDIDS_DEFAULT "nand0=NAND,nor0=qspi0-a,nor1=qspi0-b" +#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ + ",384k(bootloader)"\ + ",128k(env1)"\ + ",128k(env2)"\ + ",3840k(kernel)"\ + ",-(rootfs)"\ + ",qspi0-a:-(jffs2),qspio0-b:-(jffs2)" +#endif + +#define CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/ +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL + +/* QSPI Configs*/ +#define CONFIG_FSL_QSPI + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#define CONFIG_SYS_FSL_QSPI_LE +#endif + +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C3 +#define CONFIG_SYS_I2C_MXC + +/* RTC (actually an RV-4162 but M41T62-compatible) */ +#define CONFIG_CMD_DATE +#define CONFIG_RTC_M41T62 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_RTC_BUS_NUM 2 + +/* EEPROM (24FC256) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_BUS 2 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x82000000 + +/* We boot from the gfxRAM area of the OCRAM. */ +#define CONFIG_SYS_TEXT_BASE 0x3f408000 +#define CONFIG_BOARD_SIZE_LIMIT 524288 + +#define CONFIG_BOOTCOMMAND "run bootcmd_sd" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootfile=uImage\0" \ + "bootargs_base=setenv bootargs rw mem=256M " \ + "console=ttymxc1,115200n8\0" \ + "bootargs_sd=setenv bootargs ${bootargs} " \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ + "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ + "bootargs_nand=setenv bootargs ${bootargs} " \ + "root=/dev/mtdblock2 rootfstype=jffs2\0" \ + "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; mmc rescan; " \ + "fatload mmc 0:1 ${loadaddr} ${bootfile}; bootm ${loadaddr}\0" \ + "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ + "tftpboot ${loadaddr} ${tftploc}${bootfile}; bootm\0" \ + "bootcmd_nand='run bootargs_base bootargs_nand bootargs_mtd; " \ + "nand read ${loadaddr} 0x000E0000 0x3C0000; " \ + "bootm ${loadaddr}\0" \ + "tftploc=/path/to/tftp/directory/\0" \ + "nfs_root=/path/to/nfs/root\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "update_kernel_from_sd=mw.b $(loadaddr) 0xff 0x3C0000; " \ + "mmc rescan; fatload mmc 0:2 ${loadaddr} ${bootfile}; " \ + "nand erase 0xE0000 0x3C0000; " \ + "nand write.i ${loadaddr} 0xE0000 0x3C0000\0" \ + "update_rootfs_from_tftp=mw.b ${loadaddr} 0xff 0x8F20000; " \ + "tftp ${loadaddr} ${tftp}${filesys}; " \ + "nand erase 0x4A0000 0x8F20000; " \ + "nand write.i ${loadaddr} 0x4A0000 0x8F20000\0" \ + "filesys=rootfs.jffs2\0" + +/* miscellaneous commands */ +#define CONFIG_CMD_ELF + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80010000 +#define CONFIG_SYS_MEMTEST_END 0x87C00000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* Physical memory map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM (0x80000000) +#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_OFFSET (12 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_OFFSET 0x80000 +#define CONFIG_ENV_SIZE_REDUND (8 * 1024) +#define CONFIG_ENV_OFFSET_REDUND 0xA0000 +#endif + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#endif diff --git a/include/configs/platinum.h b/include/configs/platinum.h index d65143240b..bb7e845183 100644 --- a/include/configs/platinum.h +++ b/include/configs/platinum.h @@ -45,6 +45,8 @@ /* I2C config */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d189c3fde9..e11c016aed 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -117,6 +117,9 @@ * */ #define CONFIG_MACB +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 #define CONFIG_RMII /* use reduced MII inteface */ #define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ #define CONFIG_AT91_WANTS_COMMON_PHY @@ -182,6 +185,7 @@ /* General Boot Parameter */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "run flashboot" +#define CONFIG_BOOT_RETRY_TIME 30 #define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE \ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 48cc4ed6f6..e1ba7914cd 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -13,6 +13,7 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H +#include <asm/arch/cpu.h> #include <linux/stringify.h> #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT @@ -39,23 +40,14 @@ #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ #endif -#include <asm/arch/cpu.h> /* get chip and board defs */ - -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL) -# define CONFIG_DW_SERIAL -#endif - -/* - * Display CPU information - */ -#define CONFIG_DISPLAY_CPUINFO - /* Serial & console */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #define CONFIG_SYS_NS16550_CLK 24000000 -#ifndef CONFIG_DM_SERIAL +#ifdef CONFIG_DM_SERIAL +# define CONFIG_DW_SERIAL +#else # define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE @@ -65,6 +57,7 @@ #endif /* CPU */ +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_CACHELINE_SIZE 64 /* @@ -152,8 +145,8 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ #endif -/* 4MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) +/* 64MB of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) /* * Miscellaneous configurable options @@ -282,11 +275,7 @@ extern int soft_i2c_gpio_scl; * The amount of RAM to keep free at the top of RAM when relocating u-boot, * to use as framebuffer. This must be a multiple of 4096. */ -#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 -#define CONFIG_SUNXI_MAX_FB_SIZE (12 << 20) -#else -#define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20) -#endif +#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) /* Do we want to initialize a simple FB? */ #define CONFIG_VIDEO_DT_SIMPLEFB @@ -393,12 +382,12 @@ extern int soft_i2c_gpio_scl; #define CONFIG_PRE_CON_BUF_SZ 4096 /* Aprox 2 80*25 screens */ /* - * 240M RAM (256M minimum minus space for the framebuffer), + * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end. */ #define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0xf000000\0" \ + "bootm_size=0xa000000\0" \ "kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \ "fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \ "scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \ @@ -423,7 +412,18 @@ extern int soft_i2c_gpio_scl; #define BOOT_TARGET_DEVICES_USB(func) #endif +/* FEL boot support, auto-execute boot.scr if a script address was provided */ +#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ + "bootcmd_fel=" \ + "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ + "echo '(FEL boot)'; " \ + "source ${fel_scriptaddr}; " \ + "fi\0" +#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ + "fel " + #define BOOT_TARGET_DEVICES(func) \ + func(FEL, fel, na) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 70b440340f..17b0213362 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -167,6 +167,8 @@ #ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_EDID @@ -190,7 +192,7 @@ "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ "rdinit=/sbin/init enable_wait_mode=off\0" \ "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ - "mmc read 0x10800000 0x800 0x4000; bootm\0" \ + "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ "run bootargs_upd; " \ diff --git a/include/configs/titanium.h b/include/configs/titanium.h index 1b4ca295bc..acfa84ab2c 100644 --- a/include/configs/titanium.h +++ b/include/configs/titanium.h @@ -33,6 +33,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index f7fade12f1..295e16303c 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -62,6 +62,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 4a7702cd09..714e3e2ca2 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -67,6 +67,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ /* Fuse */ #define CONFIG_CMD_FUSE diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index c5131af340..324ba8f0cc 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -110,6 +110,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index f4e9cf20c5..6e8aec267d 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -37,6 +37,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/include/configs/warp.h b/include/configs/warp.h index fa102bbae7..3e9a5a3ef3 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -98,6 +98,8 @@ #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* PMIC */ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 5d9f5297ce..fc4656567d 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -47,6 +47,8 @@ */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define CONFIG_MXC_SPI diff --git a/include/net.h b/include/net.h index f1671e38de..3a787cc4e9 100644 --- a/include/net.h +++ b/include/net.h @@ -149,7 +149,9 @@ struct udevice *eth_get_dev(void); /* get the current device */ */ struct udevice *eth_get_dev_by_name(const char *devname); unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ + /* Used only when NetConsole is enabled */ +int eth_is_active(struct udevice *dev); /* Test device for active state */ int eth_init_state_only(void); /* Set active state */ void eth_halt_state_only(void); /* Set passive state */ #endif @@ -195,6 +197,8 @@ static inline unsigned char *eth_get_ethaddr(void) return NULL; } +/* Used only when NetConsole is enabled */ +int eth_is_active(struct eth_device *dev); /* Test device for active state */ /* Set active state */ static inline __attribute__((always_inline)) int eth_init_state_only(void) { diff --git a/net/Kconfig b/net/Kconfig index 915371df91..77a2f7e07e 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -16,4 +16,10 @@ config NET_RANDOM_ETHADDR A new MAC address will be generated on every boot and it will not be added to the environment. +config NETCONSOLE + bool "NetConsole support" + help + Support the 'nc' input/output device for networked console. + See README.NetConsole for details. + endif # if NET @@ -389,6 +389,17 @@ void eth_halt(void) priv->state = ETH_STATE_PASSIVE; } +int eth_is_active(struct udevice *dev) +{ + struct eth_device_priv *priv; + + if (!dev || !device_active(dev)) + return 0; + + priv = dev_get_uclass_priv(dev); + return priv->state == ETH_STATE_ACTIVE; +} + int eth_send(void *packet, int length) { struct udevice *current; @@ -580,7 +591,7 @@ UCLASS_DRIVER(eth) = { .per_device_auto_alloc_size = sizeof(struct eth_device_priv), .flags = DM_UC_FLAG_SEQ_ALIAS, }; -#endif +#endif /* #ifdef CONFIG_DM_ETH */ #ifndef CONFIG_DM_ETH @@ -918,6 +929,11 @@ void eth_halt(void) eth_current->state = ETH_STATE_PASSIVE; } +int eth_is_active(struct eth_device *dev) +{ + return dev && dev->state == ETH_STATE_ACTIVE; +} + int eth_send(void *packet, int length) { if (!eth_current) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 3fa90d3a75..5e62d08a80 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -17,89 +17,6 @@ #include <stdint.h> #include "kwbimage.h" -#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1)) - -/* Structure of the main header, version 0 (Kirkwood, Dove) */ -struct main_hdr_v0 { - uint8_t blockid; /*0 */ - uint8_t nandeccmode; /*1 */ - uint16_t nandpagesize; /*2-3 */ - uint32_t blocksize; /*4-7 */ - uint32_t rsvd1; /*8-11 */ - uint32_t srcaddr; /*12-15 */ - uint32_t destaddr; /*16-19 */ - uint32_t execaddr; /*20-23 */ - uint8_t satapiomode; /*24 */ - uint8_t rsvd3; /*25 */ - uint16_t ddrinitdelay; /*26-27 */ - uint16_t rsvd2; /*28-29 */ - uint8_t ext; /*30 */ - uint8_t checksum; /*31 */ -}; - -struct ext_hdr_v0_reg { - uint32_t raddr; - uint32_t rdata; -}; - -#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg)) - -struct ext_hdr_v0 { - uint32_t offset; - uint8_t reserved[0x20 - sizeof(uint32_t)]; - struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT]; - uint8_t reserved2[7]; - uint8_t checksum; -}; - -/* Structure of the main header, version 1 (Armada 370, Armada XP) */ -struct main_hdr_v1 { - uint8_t blockid; /* 0 */ - uint8_t reserved1; /* 1 */ - uint16_t reserved2; /* 2-3 */ - uint32_t blocksize; /* 4-7 */ - uint8_t version; /* 8 */ - uint8_t headersz_msb; /* 9 */ - uint16_t headersz_lsb; /* A-B */ - uint32_t srcaddr; /* C-F */ - uint32_t destaddr; /* 10-13 */ - uint32_t execaddr; /* 14-17 */ - uint8_t reserved3; /* 18 */ - uint8_t nandblocksize; /* 19 */ - uint8_t nandbadblklocation; /* 1A */ - uint8_t reserved4; /* 1B */ - uint16_t reserved5; /* 1C-1D */ - uint8_t ext; /* 1E */ - uint8_t checksum; /* 1F */ -}; - -/* - * Header for the optional headers, version 1 (Armada 370, Armada XP) - */ -struct opt_hdr_v1 { - uint8_t headertype; - uint8_t headersz_msb; - uint16_t headersz_lsb; - char data[0]; -}; - -/* - * Various values for the opt_hdr_v1->headertype field, describing the - * different types of optional headers. The "secure" header contains - * informations related to secure boot (encryption keys, etc.). The - * "binary" header contains ARM binary code to be executed prior to - * executing the main payload (usually the bootloader). This is - * typically used to execute DDR3 training code. The "register" header - * allows to describe a set of (address, value) tuples that are - * generally used to configure the DRAM controller. - */ -#define OPT_HDR_V1_SECURE_TYPE 0x1 -#define OPT_HDR_V1_BINARY_TYPE 0x2 -#define OPT_HDR_V1_REGISTER_TYPE 0x3 - -#define KWBHEADER_V1_SIZE(hdr) \ - (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb) - static struct image_cfg_element *image_cfg; static int cfgn; @@ -174,17 +91,6 @@ struct image_cfg_element { #define IMAGE_CFG_ELEMENT_MAX 256 /* - * Byte 8 of the image header contains the version number. In the v0 - * header, byte 8 was reserved, and always set to 0. In the v1 header, - * byte 8 has been changed to a proper field, set to 1. - */ -static unsigned int image_version(void *header) -{ - unsigned char *ptr = header; - return ptr[8]; -} - -/* * Utility functions to manipulate boot mode and ecc modes (convert * them back and forth between description strings and the * corresponding numerical identifiers). diff --git a/tools/kwbimage.h b/tools/kwbimage.h index 8e4a4e2810..9d2585c0e7 100644 --- a/tools/kwbimage.h +++ b/tools/kwbimage.h @@ -29,57 +29,109 @@ #define IBR_HDR_UART_ID 0x69 #define IBR_DEF_ATTRIB 0x00 -enum kwbimage_cmd { - CMD_INVALID, - CMD_BOOT_FROM, - CMD_NAND_ECC_MODE, - CMD_NAND_PAGE_SIZE, - CMD_SATA_PIO_MODE, - CMD_DDR_INIT_DELAY, - CMD_DATA -}; +#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1)) -enum kwbimage_cmd_types { - CFG_INVALID = -1, - CFG_COMMAND, - CFG_DATA0, - CFG_DATA1 -}; - -/* typedefs */ -typedef struct bhr_t { - uint8_t blockid; /*0 */ - uint8_t nandeccmode; /*1 */ +/* Structure of the main header, version 0 (Kirkwood, Dove) */ +struct main_hdr_v0 { + uint8_t blockid; /*0 */ + uint8_t nandeccmode; /*1 */ uint16_t nandpagesize; /*2-3 */ uint32_t blocksize; /*4-7 */ uint32_t rsvd1; /*8-11 */ uint32_t srcaddr; /*12-15 */ uint32_t destaddr; /*16-19 */ uint32_t execaddr; /*20-23 */ - uint8_t satapiomode; /*24 */ - uint8_t rsvd3; /*25 */ + uint8_t satapiomode; /*24 */ + uint8_t rsvd3; /*25 */ uint16_t ddrinitdelay; /*26-27 */ uint16_t rsvd2; /*28-29 */ - uint8_t ext; /*30 */ - uint8_t checkSum; /*31 */ -} bhr_t, *pbhr_t; + uint8_t ext; /*30 */ + uint8_t checksum; /*31 */ +}; -struct reg_config { +struct ext_hdr_v0_reg { uint32_t raddr; uint32_t rdata; }; -typedef struct extbhr_t { - uint32_t dramregsoffs; - uint8_t rsrvd1[0x20 - sizeof(uint32_t)]; - struct reg_config rcfg[KWBIMAGE_MAX_CONFIG]; - uint8_t rsrvd2[7]; - uint8_t checkSum; -} extbhr_t, *pextbhr_t; +#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg)) + +struct ext_hdr_v0 { + uint32_t offset; + uint8_t reserved[0x20 - sizeof(uint32_t)]; + struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT]; + uint8_t reserved2[7]; + uint8_t checksum; +}; struct kwb_header { - bhr_t kwb_hdr; - extbhr_t kwb_exthdr; + struct main_hdr_v0 kwb_hdr; + struct ext_hdr_v0 kwb_exthdr; +}; + +/* Structure of the main header, version 1 (Armada 370, Armada XP) */ +struct main_hdr_v1 { + uint8_t blockid; /* 0 */ + uint8_t reserved1; /* 1 */ + uint16_t reserved2; /* 2-3 */ + uint32_t blocksize; /* 4-7 */ + uint8_t version; /* 8 */ + uint8_t headersz_msb; /* 9 */ + uint16_t headersz_lsb; /* A-B */ + uint32_t srcaddr; /* C-F */ + uint32_t destaddr; /* 10-13 */ + uint32_t execaddr; /* 14-17 */ + uint8_t reserved3; /* 18 */ + uint8_t nandblocksize; /* 19 */ + uint8_t nandbadblklocation; /* 1A */ + uint8_t reserved4; /* 1B */ + uint16_t reserved5; /* 1C-1D */ + uint8_t ext; /* 1E */ + uint8_t checksum; /* 1F */ +}; + +/* + * Header for the optional headers, version 1 (Armada 370, Armada XP) + */ +struct opt_hdr_v1 { + uint8_t headertype; + uint8_t headersz_msb; + uint16_t headersz_lsb; + char data[0]; +}; + +/* + * Various values for the opt_hdr_v1->headertype field, describing the + * different types of optional headers. The "secure" header contains + * informations related to secure boot (encryption keys, etc.). The + * "binary" header contains ARM binary code to be executed prior to + * executing the main payload (usually the bootloader). This is + * typically used to execute DDR3 training code. The "register" header + * allows to describe a set of (address, value) tuples that are + * generally used to configure the DRAM controller. + */ +#define OPT_HDR_V1_SECURE_TYPE 0x1 +#define OPT_HDR_V1_BINARY_TYPE 0x2 +#define OPT_HDR_V1_REGISTER_TYPE 0x3 + +#define KWBHEADER_V1_SIZE(hdr) \ + (((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb) + +enum kwbimage_cmd { + CMD_INVALID, + CMD_BOOT_FROM, + CMD_NAND_ECC_MODE, + CMD_NAND_PAGE_SIZE, + CMD_SATA_PIO_MODE, + CMD_DDR_INIT_DELAY, + CMD_DATA +}; + +enum kwbimage_cmd_types { + CFG_INVALID = -1, + CFG_COMMAND, + CFG_DATA0, + CFG_DATA1 }; /* @@ -87,4 +139,15 @@ struct kwb_header { */ void init_kwb_image_type (void); +/* + * Byte 8 of the image header contains the version number. In the v0 + * header, byte 8 was reserved, and always set to 0. In the v1 header, + * byte 8 has been changed to a proper field, set to 1. + */ +static inline unsigned int image_version(void *header) +{ + unsigned char *ptr = header; + return ptr[8]; +} + #endif /* _KWBIMAGE_H_ */ diff --git a/tools/kwboot.c b/tools/kwboot.c index af7a6ee3f6..c5f4492b5f 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -614,9 +614,10 @@ static int kwboot_img_patch_hdr(void *img, size_t size) { int rc; - bhr_t *hdr; + struct main_hdr_v1 *hdr; uint8_t csum; - const size_t hdrsz = sizeof(*hdr); + size_t hdrsz = sizeof(*hdr); + int image_ver; rc = -1; hdr = img; @@ -626,8 +627,20 @@ kwboot_img_patch_hdr(void *img, size_t size) goto out; } - csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checkSum; - if (csum != hdr->checkSum) { + image_ver = image_version(img); + if (image_ver < 0) { + fprintf(stderr, "Invalid image header version\n"); + errno = EINVAL; + goto out; + } + + if (image_ver == 0) + hdrsz = sizeof(*hdr); + else + hdrsz = KWBHEADER_V1_SIZE(hdr); + + csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checksum; + if (csum != hdr->checksum) { errno = EINVAL; goto out; } @@ -639,14 +652,18 @@ kwboot_img_patch_hdr(void *img, size_t size) hdr->blockid = IBR_HDR_UART_ID; - hdr->nandeccmode = IBR_HDR_ECC_DISABLED; - hdr->nandpagesize = 0; + if (image_ver == 0) { + struct main_hdr_v0 *hdr_v0 = img; - hdr->srcaddr = hdr->ext - ? sizeof(struct kwb_header) - : sizeof(*hdr); + hdr_v0->nandeccmode = IBR_HDR_ECC_DISABLED; + hdr_v0->nandpagesize = 0; + + hdr_v0->srcaddr = hdr_v0->ext + ? sizeof(struct kwb_header) + : sizeof(*hdr_v0); + } - hdr->checkSum = kwboot_img_csum8(hdr, hdrsz) - csum; + hdr->checksum = kwboot_img_csum8(hdr, hdrsz) - csum; rc = 0; out: diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c index 676d392fb4..9c1c5b7cee 100644 --- a/tools/mksunxiboot.c +++ b/tools/mksunxiboot.c @@ -15,23 +15,8 @@ #include <errno.h> #include <sys/types.h> #include <sys/stat.h> +#include "asm/arch/spl.h" -/* boot head definition from sun4i boot code */ -struct boot_file_head { - uint32_t b_instruction; /* one intruction jumping to real code */ - uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ - uint32_t check_sum; /* generated by PC */ - uint32_t length; /* generated by PC */ - /* - * We use a simplified header, only filling in what is needed - * by the boot ROM. To be compatible with Allwinner tools we - * would need to implement the proper fields here instead of - * padding. - */ - uint8_t pad[12]; /* align to 32 bytes */ -}; - -#define BOOT0_MAGIC "eGON.BT0" #define STAMP_VALUE 0x5F0A6C39 /* check sum functon from sun4i boot code */ @@ -133,6 +118,10 @@ int main(int argc, char *argv[]) ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE); img.header.b_instruction = cpu_to_le32(img.header.b_instruction); img.header.length = cpu_to_le32(img.header.length); + + memcpy(img.header.spl_signature, SPL_SIGNATURE, 3); /* "sunxi" marker */ + img.header.spl_signature[3] = SPL_HEADER_VERSION; + gen_check_sum(&img.header); count = write(fd_out, &img, le32_to_cpu(img.header.length)); |
