diff options
310 files changed, 14567 insertions, 30016 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index b348559ecc..785fccf56c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -117,7 +117,6 @@ Wolfgang Denk <wd@denx.de> c2mon MPC855 hermes MPC860 lwmon MPC823 - pcu_e MPC855 CU824 MPC8240 Sandpoint8240 MPC8240 @@ -208,8 +207,6 @@ Wolfgang Grandegger <wg@denx.de> ipek01 MPC5200 - CCM MPC855 - PN62 MPC8240 IPHASE4539 MPC8260 SCM MPC8260 @@ -501,6 +498,10 @@ Detlev Zundel <dzu@denx.de> inka4x0 MPC5200 +Tirumala Marri <tmarri@apm.com> + + bluestone APM821XX + ------------------------------------------------------------------------- Unknown / orphaned boards: @@ -994,6 +995,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF526-EZBRD BF526 BF527-EZKIT BF527 BF527-EZKIT-V2 BF527 + BF527-SDP BF527 BF533-EZKIT BF533 BF533-STAMP BF533 BF537-PNAV BF537 @@ -1023,9 +1025,12 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org> BF537-srv1 BF537 Wojtek Skulski <skulski@pas.rochester.edu> +Wojtek Skulski <info@skutek.com> +Blackfin Team <u-boot-devel@blackfin.uclinux.org> Benjamin Matthews <mben12@gmail.com> - BLACKSTAMP BF532 + BlackStamp BF533 + BlackVME BF561 I-SYST Micromodule <support@i-syst.com> Blackfin Team <u-boot-devel@blackfin.uclinux.org> @@ -1041,6 +1046,10 @@ Brent Kandetzki <brentk@teleco.com> IP04 BF532 +Peter Meerwald <devel@bct-electronic.com> + + bct-brettl2 BF536 + ######################################################################### # End of MAINTAINERS list # ######################################################################### @@ -1781,7 +1781,7 @@ The following options need to be configured: ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL, HERMES, IP860, RPXlite, LWMON, LANTEC, - PCU_E, FLAGADM, TQM8260 + FLAGADM, TQM8260 - Error Recovery: CONFIG_PANIC_HANG diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 137834e7ee..a3300841a0 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -25,7 +25,6 @@ CROSS_COMPILE ?= bfin-uclinux- STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin -CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU))) CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE))) CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET))) CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE))) @@ -36,15 +35,17 @@ PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN LDFLAGS += --gc-sections -m elf32bfin PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -ifneq (,$(CONFIG_BFIN_CPU)) +PLATFORM_CPPFLAGS += -DBFIN_CPU='"$(CONFIG_BFIN_CPU)"' PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) -endif ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) ALL += $(obj)u-boot.ldr endif ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o +HOSTCFLAGS_NOPED += \ + $(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \ + | awk '$$2 ~ /ADSP/ { print "-D" $$2 }') else CREATE_LDR_ENV = endif diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c index 4430c90d4d..e96413b639 100644 --- a/arch/blackfin/cpu/cmd_gpio.c +++ b/arch/blackfin/cpu/cmd_gpio.c @@ -8,6 +8,7 @@ #include <common.h> #include <command.h> +#include <linux/ctype.h> #include <asm/blackfin.h> #include <asm/gpio.h> @@ -45,8 +46,8 @@ int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* grab the [p]<port> portion */ ulong port_base; - if (*str_pin == 'p') ++str_pin; - switch (*str_pin) { + if (tolower(*str_pin) == 'p') ++str_pin; + switch (tolower(*str_pin)) { #ifdef GPIO_PA0 case 'a': port_base = GPIO_PA0; break; #endif @@ -90,29 +91,28 @@ int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) gpio_request(gpio, "cmd_gpio"); /* finally, let's do it: set direction and exec command */ + ulong value; if (sub_cmd == GPIO_INPUT) { gpio_direction_input(gpio); - printf("gpio: pin %lu on port %c set to input\n", pin, *str_pin); - return 0; - } - - ulong value; - switch (sub_cmd) { - case GPIO_SET: value = 1; break; - case GPIO_CLEAR: value = 0; break; - case GPIO_TOGGLE: value = !gpio_get_value(gpio); break; - default: goto show_usage; + value = gpio_get_value(gpio); + } else { + switch (sub_cmd) { + case GPIO_SET: value = 1; break; + case GPIO_CLEAR: value = 0; break; + case GPIO_TOGGLE: value = !gpio_get_value(gpio); break; + default: goto show_usage; + } + gpio_direction_output(gpio, value); } - gpio_direction_output(gpio, value); printf("gpio: pin %lu on port %c (gpio %lu) value is %lu\n", pin, *str_pin, gpio, value); gpio_free(gpio); - return 0; + return value; } U_BOOT_CMD(gpio, 3, 0, do_gpio, - "set/clear/toggle gpio output pins", - "<set|clear|toggle> <port><pin>\n" - " - set/clear/toggle the specified pin (e.g. PF10)"); + "input/set/clear/toggle gpio output pins", + "<input|set|clear|toggle> <port><pin>\n" + " - input/set/clear/toggle the specified pin (e.g. PF10)"); diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h index aa03f2ce4d..952444ed09 100644 --- a/arch/blackfin/include/asm/blackfin_cdef.h +++ b/arch/blackfin/include/asm/blackfin_cdef.h @@ -6,6 +6,18 @@ #ifndef __MACH_CDEF_BLACKFIN__ #define __MACH_CDEF_BLACKFIN__ +#ifdef __ADSPBF512__ +# include "mach-bf518/BF512_cdef.h" +#endif +#ifdef __ADSPBF514__ +# include "mach-bf518/BF514_cdef.h" +#endif +#ifdef __ADSPBF516__ +# include "mach-bf518/BF516_cdef.h" +#endif +#ifdef __ADSPBF518__ +# include "mach-bf518/BF518_cdef.h" +#endif #ifdef __ADSPBF522__ # include "mach-bf527/BF522_cdef.h" #endif @@ -42,8 +54,11 @@ #ifdef __ADSPBF537__ # include "mach-bf537/BF537_cdef.h" #endif -#ifdef __ADSPBF541__ -# include "mach-bf548/BF541_cdef.h" +#ifdef __ADSPBF538__ +# include "mach-bf538/BF538_cdef.h" +#endif +#ifdef __ADSPBF539__ +# include "mach-bf538/BF539_cdef.h" #endif #ifdef __ADSPBF542__ # include "mach-bf548/BF542_cdef.h" diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h index 18372f6a8a..385966a00b 100644 --- a/arch/blackfin/include/asm/blackfin_def.h +++ b/arch/blackfin/include/asm/blackfin_def.h @@ -6,6 +6,26 @@ #ifndef __MACH_DEF_BLACKFIN__ #define __MACH_DEF_BLACKFIN__ +#ifdef __ADSPBF512__ +# include "mach-bf518/BF512_def.h" +# include "mach-bf518/anomaly.h" +# include "mach-bf518/def_local.h" +#endif +#ifdef __ADSPBF514__ +# include "mach-bf518/BF514_def.h" +# include "mach-bf518/anomaly.h" +# include "mach-bf518/def_local.h" +#endif +#ifdef __ADSPBF516__ +# include "mach-bf518/BF516_def.h" +# include "mach-bf518/anomaly.h" +# include "mach-bf518/def_local.h" +#endif +#ifdef __ADSPBF518__ +# include "mach-bf518/BF518_def.h" +# include "mach-bf518/anomaly.h" +# include "mach-bf518/def_local.h" +#endif #ifdef __ADSPBF522__ # include "mach-bf527/BF522_def.h" # include "mach-bf527/anomaly.h" @@ -66,10 +86,15 @@ # include "mach-bf537/anomaly.h" # include "mach-bf537/def_local.h" #endif -#ifdef __ADSPBF541__ -# include "mach-bf548/BF541_def.h" -# include "mach-bf548/anomaly.h" -# include "mach-bf548/def_local.h" +#ifdef __ADSPBF538__ +# include "mach-bf538/BF538_def.h" +# include "mach-bf538/anomaly.h" +# include "mach-bf538/def_local.h" +#endif +#ifdef __ADSPBF539__ +# include "mach-bf538/BF539_def.h" +# include "mach-bf538/anomaly.h" +# include "mach-bf538/def_local.h" #endif #ifdef __ADSPBF542__ # include "mach-bf548/BF542_def.h" diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 7455685057..215e0f2918 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -9,11 +9,6 @@ #ifndef __ASM_BLACKFIN_CONFIG_POST_H__ #define __ASM_BLACKFIN_CONFIG_POST_H__ -/* Sanity check CONFIG_BFIN_CPU */ -#ifndef CONFIG_BFIN_CPU -# error CONFIG_BFIN_CPU: your board config needs to define this -#endif - #ifndef CONFIG_BFIN_SCRATCH_REG # define CONFIG_BFIN_SCRATCH_REG retn #endif diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h new file mode 100644 index 0000000000..21ff1cf9fb --- /dev/null +++ b/arch/blackfin/include/asm/dma.h @@ -0,0 +1,75 @@ +/* + * dma.h - Blackfin DMA defines/structures/etc... + * + * Copyright 2004-2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_DMA_H_ +#define _BLACKFIN_DMA_H_ + +#include <asm/mach-common/bits/dma.h> + +struct dmasg_large { + void *next_desc_addr; + unsigned long start_addr; + unsigned short cfg; + unsigned short x_count; + short x_modify; + unsigned short y_count; + short y_modify; +} __attribute__((packed)); + +struct dmasg { + unsigned long start_addr; + unsigned short cfg; + unsigned short x_count; + short x_modify; + unsigned short y_count; + short y_modify; +} __attribute__((packed)); + +struct dma_register { + void *next_desc_ptr; /* DMA Next Descriptor Pointer register */ + unsigned long start_addr; /* DMA Start address register */ + + unsigned short cfg; /* DMA Configuration register */ + unsigned short dummy1; /* DMA Configuration register */ + + unsigned long reserved; + + unsigned short x_count; /* DMA x_count register */ + unsigned short dummy2; + + short x_modify; /* DMA x_modify register */ + unsigned short dummy3; + + unsigned short y_count; /* DMA y_count register */ + unsigned short dummy4; + + short y_modify; /* DMA y_modify register */ + unsigned short dummy5; + + void *curr_desc_ptr; /* DMA Current Descriptor Pointer + register */ + unsigned long curr_addr_ptr; /* DMA Current Address Pointer + register */ + unsigned short irq_status; /* DMA irq status register */ + unsigned short dummy6; + + unsigned short peripheral_map; /* DMA peripheral map register */ + unsigned short dummy7; + + unsigned short curr_x_count; /* DMA Current x-count register */ + unsigned short dummy8; + + unsigned long reserved2; + + unsigned short curr_y_count; /* DMA Current y-count register */ + unsigned short dummy9; + + unsigned long reserved3; + +}; + +#endif diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h new file mode 100644 index 0000000000..db70e77409 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF512_cdef.h @@ -0,0 +1,1000 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF512_proc__ +#define __BFIN_CDEF_ADSP_BF512_proc__ + +#include "../mach-common/ADSP-EDN-core_cdef.h" + +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) +#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) +#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_IER() bfin_read16(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) +#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) +#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) +#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) +#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) +#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) +#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) +#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) +#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) +#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) +#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) +#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) +#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) +#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) +#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) +#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) +#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) +#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) +#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) +#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) +#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) +#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) +#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) +#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) +#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) +#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) +#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) +#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) +#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) +#define bfin_read_PORTFIO() bfin_read16(PORTFIO) +#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) +#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) +#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) +#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) +#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) +#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) +#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) +#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) +#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) +#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) +#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) +#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) +#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) +#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) +#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) +#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) +#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) +#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) +#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) +#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) +#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) +#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) +#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) +#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) +#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) +#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) +#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) +#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) +#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) +#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) +#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) +#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) +#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) +#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) +#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) +#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) +#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) +#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) +#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) +#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) +#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) +#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) +#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) +#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) +#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) +#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) +#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) +#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) +#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) +#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) +#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) +#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) +#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) +#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) +#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) +#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) +#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) +#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) +#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) +#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) +#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) +#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) +#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) +#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) +#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) +#define bfin_read_PORTGIO() bfin_read16(PORTGIO) +#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) +#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) +#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) +#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) +#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) +#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) +#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) +#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) +#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) +#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) +#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) +#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) +#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) +#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) +#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) +#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) +#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) +#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) +#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) +#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) +#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) +#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) +#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) +#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) +#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) +#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) +#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) +#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) +#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) +#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) +#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) +#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) +#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) +#define bfin_read_PORTHIO() bfin_read16(PORTHIO) +#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) +#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) +#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) +#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) +#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) +#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) +#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) +#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) +#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) +#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) +#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) +#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) +#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) +#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) +#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) +#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) +#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) +#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) +#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) +#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) +#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) +#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) +#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) +#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) +#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) +#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) +#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) +#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) +#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) +#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) +#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) +#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) +#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_IER() bfin_read16(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) +#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) +#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) +#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) +#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) +#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) +#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) +#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) +#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) +#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) +#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) +#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) +#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) +#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) +#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) +#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) +#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) +#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) +#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) +#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) +#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) +#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) +#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) +#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) +#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) +#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) +#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE) +#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val) +#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS) +#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val) +#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) +#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) +#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) +#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) +#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) +#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) +#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) +#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) +#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) +#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) +#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) +#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) +#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) +#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) +#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) +#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) +#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) +#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) +#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) +#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) +#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) +#define bfin_read_PWM_CTRL() bfin_read16(PWM_CTRL) +#define bfin_write_PWM_CTRL(val) bfin_write16(PWM_CTRL, val) +#define bfin_read_PWM_STAT() bfin_read16(PWM_STAT) +#define bfin_write_PWM_STAT(val) bfin_write16(PWM_STAT, val) +#define bfin_read_PWM_TM() bfin_read16(PWM_TM) +#define bfin_write_PWM_TM(val) bfin_write16(PWM_TM, val) +#define bfin_read_PWM_DT() bfin_read16(PWM_DT) +#define bfin_write_PWM_DT(val) bfin_write16(PWM_DT, val) +#define bfin_read_PWM_GATE() bfin_read16(PWM_GATE) +#define bfin_write_PWM_GATE(val) bfin_write16(PWM_GATE, val) +#define bfin_read_PWM_CHA() bfin_read16(PWM_CHA) +#define bfin_write_PWM_CHA(val) bfin_write16(PWM_CHA, val) +#define bfin_read_PWM_CHB() bfin_read16(PWM_CHB) +#define bfin_write_PWM_CHB(val) bfin_write16(PWM_CHB, val) +#define bfin_read_PWM_CHC() bfin_read16(PWM_CHC) +#define bfin_write_PWM_CHC(val) bfin_write16(PWM_CHC, val) +#define bfin_read_PWM_SEG() bfin_read16(PWM_SEG) +#define bfin_write_PWM_SEG(val) bfin_write16(PWM_SEG, val) +#define bfin_read_PWM_SYNCWT() bfin_read16(PWM_SYNCWT) +#define bfin_write_PWM_SYNCWT(val) bfin_write16(PWM_SYNCWT, val) +#define bfin_read_PWM_CHAL() bfin_read16(PWM_CHAL) +#define bfin_write_PWM_CHAL(val) bfin_write16(PWM_CHAL, val) +#define bfin_read_PWM_CHBL() bfin_read16(PWM_CHBL) +#define bfin_write_PWM_CHBL(val) bfin_write16(PWM_CHBL, val) +#define bfin_read_PWM_CHCL() bfin_read16(PWM_CHCL) +#define bfin_write_PWM_CHCL(val) bfin_write16(PWM_CHCL, val) +#define bfin_read_PWM_LSI() bfin_read16(PWM_LSI) +#define bfin_write_PWM_LSI(val) bfin_write16(PWM_LSI, val) +#define bfin_read_PWM_STAT2() bfin_read16(PWM_STAT2) +#define bfin_write_PWM_STAT2(val) bfin_write16(PWM_STAT2, val) +#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) +#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) +#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) +#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) + +#endif /* __BFIN_CDEF_ADSP_BF512_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/BF512_def.h b/arch/blackfin/include/asm/mach-bf518/BF512_def.h new file mode 100644 index 0000000000..abc88ca6d3 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF512_def.h @@ -0,0 +1,523 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF512_proc__ +#define __BFIN_DEF_ADSP_BF512_proc__ + +#include "../mach-common/ADSP-EDN-core_def.h" + +#define PLL_CTL 0xFFC00000 /* PLL Control Register */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ +#define PLL_STAT 0xFFC0000C /* PLL Status Register */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ +#define CHIPID 0xFFC00014 +#define SWRST 0xFFC00100 /* Software Reset Register */ +#define SYSCR 0xFFC00104 /* System Configuration register */ +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ +#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ +#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ +#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ +#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ +#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ +#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ +#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ +#define RTC_STAT 0xFFC00300 /* RTC Status Register */ +#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ +#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ +#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ +#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ +#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ +#define UART0_THR 0xFFC00400 /* Transmit Holding register */ +#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ +#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ +#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ +#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ +#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ +#define UART0_LCR 0xFFC0040C /* Line Control Register */ +#define UART0_MCR 0xFFC00410 /* Modem Control Register */ +#define UART0_LSR 0xFFC00414 /* Line Status Register */ +#define UART0_MSR 0xFFC00418 /* Modem Status Register */ +#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ +#define UART0_GCTL 0xFFC00424 /* Global Control Register */ +#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ +#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ +#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ +#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ +#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ +#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ +#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ +#define SPI1_CTL 0xFFC03400 /* SPI1 Control */ +#define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */ +#define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */ +#define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */ +#define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */ +#define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */ +#define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */ +#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ +#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ +#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ +#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ +#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ +#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ +#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ +#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ +#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ +#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ +#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ +#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ +#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ +#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ +#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ +#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ +#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ +#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ +#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ +#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ +#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ +#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ +#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ +#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ +#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ +#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ +#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ +#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ +#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ +#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ +#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ +#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ +#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ +#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ +#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ +#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ +#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ +#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ +#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ +#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ +#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ +#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ +#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ +#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ +#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ +#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ +#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ +#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ +#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ +#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ +#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ +#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ +#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ +#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ +#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ +#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ +#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ +#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ +#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ +#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ +#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ +#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ +#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ +#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ +#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ +#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ +#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ +#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ +#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ +#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ +#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ +#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ +#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ +#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ +#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ +#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ +#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ +#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ +#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ +#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ +#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ +#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ +#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ +#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ +#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ +#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ +#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ +#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ +#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ +#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ +#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ +#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ +#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ +#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ +#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ +#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ +#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ +#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ +#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ +#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ +#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ +#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ +#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ +#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ +#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ +#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ +#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ +#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ +#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ +#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ +#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ +#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ +#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ +#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ +#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ +#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ +#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ +#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ +#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ +#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ +#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ +#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ +#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ +#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ +#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ +#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ +#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ +#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ +#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ +#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ +#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ +#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ +#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ +#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ +#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ +#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ +#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ +#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ +#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ +#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ +#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ +#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ +#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ +#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ +#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ +#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ +#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ +#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ +#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ +#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ +#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ +#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ +#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ +#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ +#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ +#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ +#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ +#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ +#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ +#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ +#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ +#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ +#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ +#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ +#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ +#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ +#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ +#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ +#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ +#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ +#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ +#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ +#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ +#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ +#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ +#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ +#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ +#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ +#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ +#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ +#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ +#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ +#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ +#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ +#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ +#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ +#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ +#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ +#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ +#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ +#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ +#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ +#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ +#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ +#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ +#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ +#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ +#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ +#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ +#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ +#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ +#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ +#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ +#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ +#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ +#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ +#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ +#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ +#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ +#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ +#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ +#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ +#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ +#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ +#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ +#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ +#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ +#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ +#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ +#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ +#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ +#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ +#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ +#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ +#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ +#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ +#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ +#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ +#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ +#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ +#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ +#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ +#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ +#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ +#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ +#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ +#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ +#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ +#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ +#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ +#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ +#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ +#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ +#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ +#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ +#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ +#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ +#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ +#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ +#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ +#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ +#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ +#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ +#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ +#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ +#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ +#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ +#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ +#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ +#define UART1_THR 0xFFC02000 /* Transmit Holding register */ +#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ +#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ +#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ +#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ +#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ +#define UART1_LCR 0xFFC0200C /* Line Control Register */ +#define UART1_MCR 0xFFC02010 /* Modem Control Register */ +#define UART1_LSR 0xFFC02014 /* Line Status Register */ +#define UART1_MSR 0xFFC02018 /* Modem Status Register */ +#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ +#define UART1_GCTL 0xFFC02024 /* Global Control Register */ +#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ +#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ +#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ +#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ +#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ +#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ +#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ +#define PORTF_MUX 0xFFC03210 /* Port F mux control */ +#define PORTG_MUX 0xFFC03214 /* Port G mux control */ +#define PORTH_MUX 0xFFC03218 /* Port H mux control */ +#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ +#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ +#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ +#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ +#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ +#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ +#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ +#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ +#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */ +#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */ +#define CNT_STATUS 0xFFC03508 /* Status Register */ +#define CNT_COMMAND 0xFFC0350C /* Command Register */ +#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ +#define CNT_COUNTER 0xFFC03514 /* Counter Register */ +#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ +#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ +#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */ +#define SECURE_CONTROL 0xFFC03624 /* Secure Control */ +#define SECURE_STATUS 0xFFC03628 /* Secure Status */ +#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ +#define PWM_CTRL 0xFFC03700 /* PWM Control Register */ +#define PWM_STAT 0xFFC03704 /* PWM Status Register */ +#define PWM_TM 0xFFC03708 /* PWM Period Register */ +#define PWM_DT 0xFFC0370C /* PWM Dead Time Register */ +#define PWM_GATE 0xFFC03710 /* PWM Chopping Control */ +#define PWM_CHA 0xFFC03714 /* PWM Channel A Duty Control */ +#define PWM_CHB 0xFFC03718 /* PWM Channel B Duty Control */ +#define PWM_CHC 0xFFC0371C /* PWM Channel C Duty Control */ +#define PWM_SEG 0xFFC03720 /* PWM Crossover and Output Enable */ +#define PWM_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */ +#define PWM_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */ +#define PWM_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */ +#define PWM_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */ +#define PWM_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */ +#define PWM_STAT2 0xFFC03738 /* PWM Status Register */ +#define DMA_TC_CNT 0xFFC00B0C +#define DMA_TC_PER 0xFFC00B10 + +#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ +#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ +#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ +#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ +#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) +#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) +#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ +#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) +#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) + +#endif /* __BFIN_DEF_ADSP_BF512_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h new file mode 100644 index 0000000000..b13246f6dd --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF514_cdef.h @@ -0,0 +1,68 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF514_proc__ +#define __BFIN_CDEF_ADSP_BF514_proc__ + +#include "BF512_cdef.h" + +#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL) +#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val) +#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT) +#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val) +#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK) +#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val) +#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) + +#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/BF514_def.h b/arch/blackfin/include/asm/mach-bf518/BF514_def.h new file mode 100644 index 0000000000..708a4f7227 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF514_def.h @@ -0,0 +1,40 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF514_proc__ +#define __BFIN_DEF_ADSP_BF514_proc__ + +#include "BF512_def.h" + +#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ +#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ +#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ +#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ +#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ +#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ +#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ +#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ +#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ +#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ +#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ +#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ +#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ +#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ +#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ +#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ +#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ +#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ +#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ +#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ + +#endif /* __BFIN_DEF_ADSP_BF514_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h new file mode 100644 index 0000000000..8722944721 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF516_cdef.h @@ -0,0 +1,170 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF516_proc__ +#define __BFIN_CDEF_ADSP_BF516_proc__ + +#include "BF514_cdef.h" + +#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) +#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) +#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) +#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) +#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) +#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) +#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) +#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) +#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) +#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) +#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) +#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) +#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) +#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) +#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) +#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) +#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) +#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) +#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) +#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) +#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) +#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) +#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) +#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) +#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) +#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) +#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) +#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) +#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) +#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) +#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) +#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) +#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) +#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) +#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) +#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) +#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) +#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) +#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) +#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) +#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) +#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) +#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) +#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) +#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) +#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) +#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) +#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) +#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) +#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) +#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) +#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) +#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) +#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) +#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) +#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) +#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) +#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) +#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) +#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) +#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) +#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) +#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) +#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) +#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) +#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) +#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) +#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) +#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) +#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) +#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) +#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) +#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) +#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) +#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) +#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) +#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) +#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) +#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) +#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) +#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) +#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) +#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) +#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) +#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) +#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) +#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) +#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) +#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) +#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) +#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) +#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) +#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) +#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) +#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) +#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) +#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) +#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) +#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) +#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) +#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) +#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) +#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) +#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) +#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) +#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) +#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) +#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) +#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) +#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) +#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) +#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) +#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) +#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) +#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) +#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) +#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) +#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) +#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) +#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) +#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) +#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) +#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) +#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) +#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) +#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) +#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) +#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) +#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) +#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) +#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) +#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) +#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) +#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) +#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) +#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) +#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) +#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) +#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) +#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) +#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) +#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) +#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) +#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) +#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) +#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) +#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) +#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) +#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) +#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) +#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) +#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) +#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) +#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) +#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) +#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) +#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) +#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) + +#endif /* __BFIN_CDEF_ADSP_BF516_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/BF516_def.h b/arch/blackfin/include/asm/mach-bf518/BF516_def.h new file mode 100644 index 0000000000..8139c9b273 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF516_def.h @@ -0,0 +1,91 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF516_proc__ +#define __BFIN_DEF_ADSP_BF516_proc__ + +#include "BF514_def.h" + +#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ +#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ +#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ +#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ +#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ +#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ +#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ +#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ +#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ +#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ +#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ +#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ +#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ +#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ +#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ +#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ +#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ +#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ +#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ +#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ +#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ +#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ +#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ +#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ +#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ +#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ +#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ +#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ +#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ +#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ +#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ +#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ +#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ +#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ +#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ +#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ +#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ +#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ +#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ +#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ +#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ +#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ +#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ +#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ +#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ +#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ +#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ +#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ +#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ +#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ +#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ +#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ +#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ +#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ +#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ +#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ +#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ +#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ +#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ +#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ +#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ +#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ +#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ +#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ +#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ +#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ +#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ +#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ +#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ +#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ +#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ +#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ +#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ + +#endif /* __BFIN_DEF_ADSP_BF516_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h b/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h new file mode 100644 index 0000000000..0e582e10d1 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF518_cdef.h @@ -0,0 +1,58 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF518_proc__ +#define __BFIN_CDEF_ADSP_BF518_proc__ + +#include "BF516_cdef.h" + +#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) +#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) +#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE) +#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val) +#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT) +#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val) +#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF) +#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val) +#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1) +#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val) +#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2) +#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val) +#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3) +#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val) +#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND) +#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val) +#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR) +#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val) +#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET) +#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val) +#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO) +#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val) +#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI) +#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val) +#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO) +#define bfin_write_EMAC_PTP_RXSNAPLO(val) bfin_write32(EMAC_PTP_RXSNAPLO, val) +#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI) +#define bfin_write_EMAC_PTP_RXSNAPHI(val) bfin_write32(EMAC_PTP_RXSNAPHI, val) +#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO) +#define bfin_write_EMAC_PTP_TXSNAPLO(val) bfin_write32(EMAC_PTP_TXSNAPLO, val) +#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI) +#define bfin_write_EMAC_PTP_TXSNAPHI(val) bfin_write32(EMAC_PTP_TXSNAPHI, val) +#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO) +#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val) +#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI) +#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val) +#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF) +#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val) +#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP) +#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val) +#define bfin_read_EMAC_PTP_PPS_STARTLO() bfin_read32(EMAC_PTP_PPS_STARTLO) +#define bfin_write_EMAC_PTP_PPS_STARTLO(val) bfin_write32(EMAC_PTP_PPS_STARTLO, val) +#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI) +#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val) +#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) +#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) + +#endif /* __BFIN_CDEF_ADSP_BF518_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/BF518_def.h b/arch/blackfin/include/asm/mach-bf518/BF518_def.h new file mode 100644 index 0000000000..eec70d4666 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/BF518_def.h @@ -0,0 +1,35 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF518_proc__ +#define __BFIN_DEF_ADSP_BF518_proc__ + +#include "BF516_def.h" + +#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */ +#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */ +#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */ +#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */ +#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */ +#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */ +#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */ +#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */ +#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */ +#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */ +#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */ +#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */ +#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */ +#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */ +#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */ +#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */ +#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */ +#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */ +#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */ +#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */ +#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */ +#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ +#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ + +#endif /* __BFIN_DEF_ADSP_BF518_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf518/anomaly.h b/arch/blackfin/include/asm/mach-bf518/anomaly.h new file mode 100644 index 0000000000..d808b451e6 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/anomaly.h @@ -0,0 +1,158 @@ +/* + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE + * + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + */ + +/* This file should be up to date with: + * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List + */ + +/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ +#if __SILICON_REVISION__ < 0 +# error will not work on BF518 silicon version +#endif + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ +#define ANOMALY_05000254 (1) +/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ +#define ANOMALY_05000265 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ +#define ANOMALY_05000405 (1) +/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ +#define ANOMALY_05000408 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ +#define ANOMALY_05000421 (1) +/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ +#define ANOMALY_05000422 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* Software System Reset Corrupts PLL_LOCKCNT Register */ +#define ANOMALY_05000430 (__SILICON_REVISION__ < 1) +/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ +#define ANOMALY_05000431 (1) +/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ +#define ANOMALY_05000434 (1) +/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ +#define ANOMALY_05000435 (__SILICON_REVISION__ < 1) +/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */ +#define ANOMALY_05000438 (__SILICON_REVISION__ < 1) +/* Preboot Cannot be Used to Alter the PLL_DIV Register */ +#define ANOMALY_05000439 (__SILICON_REVISION__ < 1) +/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */ +#define ANOMALY_05000440 (__SILICON_REVISION__ < 1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) +/* Incorrect L1 Instruction Bank B Memory Map Location */ +#define ANOMALY_05000444 (__SILICON_REVISION__ < 1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) +/* PWM_TRIPB Signal Not Available on PG10 */ +#define ANOMALY_05000453 (__SILICON_REVISION__ < 1) +/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ +#define ANOMALY_05000455 (__SILICON_REVISION__ < 1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000469 (1) +/* Incorrect Default MSEL Value in PLL_CTL */ +#define ANOMALY_05000472 (1) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ +#define ANOMALY_05000473 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) +#define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000171 (0) +#define ANOMALY_05000179 (0) +#define ANOMALY_05000182 (0) +#define ANOMALY_05000183 (0) +#define ANOMALY_05000189 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000219 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000227 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000233 (0) +#define ANOMALY_05000234 (0) +#define ANOMALY_05000242 (0) +#define ANOMALY_05000244 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000257 (0) +#define ANOMALY_05000261 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000273 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000278 (0) +#define ANOMALY_05000281 (0) +#define ANOMALY_05000283 (0) +#define ANOMALY_05000285 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000301 (0) +#define ANOMALY_05000305 (0) +#define ANOMALY_05000307 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) +#define ANOMALY_05000315 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (0) +#define ANOMALY_05000357 (0) +#define ANOMALY_05000362 (1) +#define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) +#define ANOMALY_05000371 (0) +#define ANOMALY_05000380 (0) +#define ANOMALY_05000386 (0) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000402 (0) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000447 (0) +#define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000475 (0) +#define ANOMALY_05000485 (0) + +#endif diff --git a/arch/blackfin/include/asm/mach-bf518/def_local.h b/arch/blackfin/include/asm/mach-bf518/def_local.h new file mode 100644 index 0000000000..73f67d8388 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/def_local.h @@ -0,0 +1,5 @@ +#include "gpio.h" +#include "portmux.h" +#include "ports.h" + +#define CONFIG_BF51x 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf518/gpio.h b/arch/blackfin/include/asm/mach-bf518/gpio.h new file mode 100644 index 0000000000..9af6ce0f63 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/gpio.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2008 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 41 + +#define GPIO_PF0 0 +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PG0 16 +#define GPIO_PG1 17 +#define GPIO_PG2 18 +#define GPIO_PG3 19 +#define GPIO_PG4 20 +#define GPIO_PG5 21 +#define GPIO_PG6 22 +#define GPIO_PG7 23 +#define GPIO_PG8 24 +#define GPIO_PG9 25 +#define GPIO_PG10 26 +#define GPIO_PG11 27 +#define GPIO_PG12 28 +#define GPIO_PG13 29 +#define GPIO_PG14 30 +#define GPIO_PG15 31 +#define GPIO_PH0 32 +#define GPIO_PH1 33 +#define GPIO_PH2 34 +#define GPIO_PH3 35 +#define GPIO_PH4 36 +#define GPIO_PH5 37 +#define GPIO_PH6 38 +#define GPIO_PH7 39 +#define GPIO_PH8 40 + +#define PORT_F GPIO_PF0 +#define PORT_G GPIO_PG0 +#define PORT_H GPIO_PH0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf518/portmux.h b/arch/blackfin/include/asm/mach-bf518/portmux.h new file mode 100644 index 0000000000..cd84a569b0 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/portmux.h @@ -0,0 +1,201 @@ +/* + * Copyright 2008-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS + +/* EMAC MII/RMII Port Mux */ +#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0)) +#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0)) +#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0)) +#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0)) +#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0)) +#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0)) +#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0)) + +#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0)) +#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0)) +#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0)) +#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0)) +#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0)) +#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0)) +#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0)) +#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0)) +#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0)) +#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0)) +#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0)) + +#define P_MII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxD2, \ + P_MII0_ETxD3, \ + P_MII0_ETxEN, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_COL, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxD2, \ + P_MII0_ERxD3, \ + P_MII0_ERxDV, \ + P_MII0_ERxCLK, \ + P_MII0_ERxER, \ + P_MII0_CRS, \ + P_MII0_MDC, \ + P_MII0_MDIO, 0} + +#define P_RMII0 {\ + P_MII0_ETxD0, \ + P_MII0_ETxD1, \ + P_MII0_ETxEN, \ + P_MII0_ERxD0, \ + P_MII0_ERxD1, \ + P_MII0_ERxER, \ + P_MII0_TxCLK, \ + P_MII0_PHYINT, \ + P_MII0_CRS, \ + P_MII0_MDC, \ + P_MII0_MDIO, 0} + +/* PPI Port Mux */ +#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1)) +#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1)) +#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1)) +#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1)) +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1)) + +#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1)) +#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1)) +#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1)) +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1)) + +/* SPI Port Mux */ +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) +#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0)) +#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0)) +#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0)) + +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2)) + +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1)) +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1)) + +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2)) +#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2)) +#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2)) +#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2)) +#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2)) + +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 + +/* SPORT Port Mux */ +#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0)) +#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0)) +#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0)) +#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0)) +#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0)) +#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0)) +#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0)) +#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0)) + +#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0)) +#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0)) +#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0)) +#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0)) +#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0)) +#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0)) +#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0)) +#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0)) + +/* UART Port Mux */ +#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1)) +#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1)) + +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1)) + +/* Timer */ +#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2)) +#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2)) +#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2)) +#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2)) +#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2)) +#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2)) +#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2)) +#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2)) +#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2)) + +/* DMA */ +#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1)) +#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1)) + +/* TWI */ +#define P_TWI0_SCL (P_DONTCARE) +#define P_TWI0_SDA (P_DONTCARE) + +/* PWM */ +#define P_PWM0_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2)) +#define P_PWM0_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2)) +#define P_PWM0_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2)) +#define P_PWM0_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2)) +#define P_PWM0_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2)) +#define P_PWM0_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2)) +#define P_PWM0_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2)) + +#define P_PWM1_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2)) +#define P_PWM1_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2)) +#define P_PWM1_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2)) +#define P_PWM1_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2)) +#define P_PWM1_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2)) +#define P_PWM1_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2)) +#define P_PWM1_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2)) + +#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2)) + +/* RSI */ +#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1)) +#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1)) +#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1)) +#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1)) +#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2)) +#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2)) +#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2)) +#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2)) +#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1)) +#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1)) + +/* PTP */ +#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2)) +#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2)) + +/* AMS */ +#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1)) +#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2)) + +#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1)) + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf518/ports.h b/arch/blackfin/include/asm/mach-bf518/ports.h new file mode 100644 index 0000000000..f1e9cc00d4 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf518/ports.h @@ -0,0 +1,59 @@ +/* + * Port Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT__ +#define __BFIN_PERIPHERAL_PORT__ + +/* PORTx_MUX Masks */ +#define PORT_x_MUX_0_MASK 0x0003 +#define PORT_x_MUX_1_MASK 0x000C +#define PORT_x_MUX_2_MASK 0x0030 +#define PORT_x_MUX_3_MASK 0x00C0 +#define PORT_x_MUX_4_MASK 0x0300 +#define PORT_x_MUX_5_MASK 0x0C00 +#define PORT_x_MUX_6_MASK 0x3000 +#define PORT_x_MUX_7_MASK 0xC000 + +#define PORT_x_MUX_FUNC_1 (0x0) +#define PORT_x_MUX_FUNC_2 (0x1) +#define PORT_x_MUX_FUNC_3 (0x2) +#define PORT_x_MUX_FUNC_4 (0x3) +#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0) +#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0) +#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0) +#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0) +#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2) +#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2) +#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2) +#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2) +#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4) +#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4) +#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4) +#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4) +#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6) +#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6) +#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6) +#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6) +#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8) +#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8) +#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8) +#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8) +#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10) +#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10) +#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10) +#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10) +#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12) +#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12) +#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12) +#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12) +#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14) +#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14) +#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14) +#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14) + +#include "../mach-common/bits/ports-f.h" +#include "../mach-common/bits/ports-g.h" +#include "../mach-common/bits/ports-h.h" + +#endif diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h index f65b439c17..5381bf0af7 100644 --- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h @@ -6,1499 +6,988 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__ #define __BFIN_CDEF_ADSP_EDN_BF52x_extended__ -#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ #define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */ #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */ #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */ #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */ #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */ #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */ #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */ #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */ #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */ #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */ #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */ #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */ #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */ #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */ #define bfin_read_UART0_IER() bfin_read16(UART0_IER) #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */ #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */ #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */ #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */ #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */ #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) /* SPI Status register */ #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */ #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */ #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */ #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */ #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */ #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */ #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */ #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define pTIMER_STATUS ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */ #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) -#define pPORTFIO ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */ #define bfin_read_PORTFIO() bfin_read16(PORTFIO) #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define pPORTFIO_CLEAR ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */ #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define pPORTFIO_SET ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */ #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define pPORTFIO_TOGGLE ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */ #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define pPORTFIO_MASKA ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */ #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define pPORTFIO_MASKA_CLEAR ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */ #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define pPORTFIO_MASKA_SET ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */ #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define pPORTFIO_MASKA_TOGGLE ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */ #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define pPORTFIO_MASKB ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */ #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define pPORTFIO_MASKB_CLEAR ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */ #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define pPORTFIO_MASKB_SET ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */ #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define pPORTFIO_MASKB_TOGGLE ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */ #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define pPORTFIO_DIR ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */ #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define pPORTFIO_POLAR ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */ #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define pPORTFIO_EDGE ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */ #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define pPORTFIO_BOTH ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */ #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define pPORTFIO_INEN ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register */ #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */ #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */ #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */ #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */ #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */ #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */ #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */ #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */ #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */ #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */ #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */ #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */ #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */ #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */ #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */ #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */ #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */ #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */ #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */ #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */ #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */ #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */ #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */ #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */ #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */ #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */ #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */ #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */ #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */ #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */ #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */ #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */ #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */ #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */ #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */ #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */ #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */ #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */ #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */ #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */ #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */ #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */ #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */ #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */ #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */ #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */ #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */ #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */ #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */ #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */ #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */ #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */ #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */ #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */ #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */ #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */ #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */ #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */ #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */ #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */ #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */ #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */ #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */ #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */ #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define pTWI_CLKDIV ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */ #define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define pTWI_CONTROL ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */ #define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) #define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define pTWI_SLAVE_CTL ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */ #define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) #define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define pTWI_SLAVE_STAT ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */ #define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */ #define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */ #define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define pTWI_MASTER_STAT ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */ #define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */ #define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) #define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define pTWI_INT_MASK ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */ #define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) #define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define pTWI_FIFO_CTL ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */ #define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) #define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define pTWI_FIFO_STAT ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */ #define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) #define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define pTWI_XMT_DATA8 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) #define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define pTWI_XMT_DATA16 ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define pTWI_RCV_DATA8 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */ #define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) #define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define pTWI_RCV_DATA16 ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */ #define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) -#define pPORTGIO ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */ #define bfin_read_PORTGIO() bfin_read16(PORTGIO) #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define pPORTGIO_CLEAR ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */ #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define pPORTGIO_SET ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */ #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define pPORTGIO_TOGGLE ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */ #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define pPORTGIO_MASKA ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */ #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define pPORTGIO_MASKA_CLEAR ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */ #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define pPORTGIO_MASKA_SET ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */ #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define pPORTGIO_MASKA_TOGGLE ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */ #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define pPORTGIO_MASKB ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */ #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define pPORTGIO_MASKB_CLEAR ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */ #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define pPORTGIO_MASKB_SET ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */ #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define pPORTGIO_MASKB_TOGGLE ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */ #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define pPORTGIO_DIR ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */ #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define pPORTGIO_POLAR ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */ #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define pPORTGIO_EDGE ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */ #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define pPORTGIO_BOTH ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */ #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define pPORTGIO_INEN ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */ #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) -#define pPORTHIO ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */ #define bfin_read_PORTHIO() bfin_read16(PORTHIO) #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define pPORTHIO_CLEAR ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */ #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define pPORTHIO_SET ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */ #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define pPORTHIO_TOGGLE ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */ #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define pPORTHIO_MASKA ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */ #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define pPORTHIO_MASKA_CLEAR ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */ #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define pPORTHIO_MASKA_SET ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */ #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define pPORTHIO_MASKA_TOGGLE ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */ #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define pPORTHIO_MASKB ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */ #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define pPORTHIO_MASKB_CLEAR ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */ #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define pPORTHIO_MASKB_SET ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */ #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define pPORTHIO_MASKB_TOGGLE ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */ #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define pPORTHIO_DIR ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */ #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define pPORTHIO_POLAR ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */ #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define pPORTHIO_EDGE ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */ #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define pPORTHIO_BOTH ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */ #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define pPORTHIO_INEN ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */ #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */ #define bfin_read_UART1_THR() bfin_read16(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */ #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */ #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */ #define bfin_read_UART1_IER() bfin_read16(UART1_IER) #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */ #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */ #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */ #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */ #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */ #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */ #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */ #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */ #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */ #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */ #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */ #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */ #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */ #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pPORTF_MUX ((uint16_t volatile *)PORTF_MUX) /* Port F mux control */ #define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX) #define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val) -#define pPORTG_MUX ((uint16_t volatile *)PORTG_MUX) /* Port G mux control */ #define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX) #define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val) -#define pPORTH_MUX ((uint16_t volatile *)PORTH_MUX) /* Port H mux control */ #define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX) #define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val) -#define pPORTF_DRIVE ((uint16_t volatile *)PORTF_DRIVE) /* Port F drive strength control */ #define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE) #define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val) -#define pPORTG_DRIVE ((uint16_t volatile *)PORTG_DRIVE) /* Port G drive strength control */ #define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE) #define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val) -#define pPORTH_DRIVE ((uint16_t volatile *)PORTH_DRIVE) /* Port H drive strength control */ #define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE) #define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val) -#define pPORTF_SLEW ((uint16_t volatile *)PORTF_SLEW) /* Port F slew control */ #define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW) #define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val) -#define pPORTG_SLEW ((uint16_t volatile *)PORTG_SLEW) /* Port G slew control */ #define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW) #define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val) -#define pPORTH_SLEW ((uint16_t volatile *)PORTH_SLEW) /* Port H slew control */ #define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW) #define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val) -#define pPORTF_HYSTERESIS ((uint16_t volatile *)PORTF_HYSTERESIS) /* Port F Schmitt trigger control */ #define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS) #define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val) -#define pPORTG_HYSTERESIS ((uint16_t volatile *)PORTG_HYSTERESIS) /* Port G Schmitt trigger control */ #define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS) #define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val) -#define pPORTH_HYSTERESIS ((uint16_t volatile *)PORTH_HYSTERESIS) /* Port H Schmitt trigger control */ #define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS) #define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val) -#define pNONGPIO_DRIVE ((uint16_t volatile *)NONGPIO_DRIVE) /* Non-GPIO Port drive strength control */ #define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE) #define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val) -#define pNONGPIO_SLEW ((uint16_t volatile *)NONGPIO_SLEW) /* Non-GPIO Port slew control */ #define bfin_read_NONGPIO_SLEW() bfin_read16(NONGPIO_SLEW) #define bfin_write_NONGPIO_SLEW(val) bfin_write16(NONGPIO_SLEW, val) -#define pNONGPIO_HYSTERESIS ((uint16_t volatile *)NONGPIO_HYSTERESIS) /* Non-GPIO Port Schmitt trigger control */ #define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS) #define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOST Control Register */ #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOST Status Register */ #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOST Acknowledge Mode Timeout Register */ #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration/Control Register */ #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Prescaler Register */ #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Boundary Value Register */ #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Boundary Value Register */ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ #define bfin_read_NFC_RST() bfin_read16(NFC_RST) #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ #define bfin_read_NFC_READ() bfin_read16(NFC_READ) #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) diff --git a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h index 0b384808ec..7b97aee57d 100644 --- a/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h +++ b/arch/blackfin/include/asm/mach-bf527/ADSP-EDN-BF52x-extended_def.h @@ -497,12 +497,6 @@ #define NFC_CMD 0xFFC03744 /* NAND Command Register */ #define NFC_DATA_WR 0xFFC03748 /* NAND Data Write Register */ #define NFC_DATA_RD 0xFFC0374C /* NAND Data Read Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 #define DMA_TC_CNT 0xFFC00B0C #define DMA_TC_PER 0xFFC00B10 diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h index 987cc862ce..9ce41b16df 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF522_cdef.h @@ -10,332 +10,21 @@ #include "ADSP-EDN-BF52x-extended_cdef.h" -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) #endif /* __BFIN_CDEF_ADSP_BF522_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF522_def.h b/arch/blackfin/include/asm/mach-bf527/BF522_def.h index bc05029aac..a6b0787807 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF522_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF522_def.h @@ -18,106 +18,5 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ #endif /* __BFIN_DEF_ADSP_BF522_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h index 390f3dc16e..593330ebdc 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF523_cdef.h @@ -1,341 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF523_proc__ -#define __BFIN_CDEF_ADSP_BF523_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) - -#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */ +#include "BF522_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf527/BF523_def.h b/arch/blackfin/include/asm/mach-bf527/BF523_def.h index c27fd646b5..e88a450a91 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF523_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF523_def.h @@ -1,123 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF523_proc__ -#define __BFIN_DEF_ADSP_BF523_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ - -#endif /* __BFIN_DEF_ADSP_BF523_proc__ */ +#include "BF522_def.h" diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h index 9ec89c66ae..25612bfdda 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF524_cdef.h @@ -10,838 +10,358 @@ #include "ADSP-EDN-BF52x-extended_cdef.h" -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ #define bfin_read_USB_POWER() bfin_read16(USB_POWER) #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ #define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ #define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ #define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ #define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ #define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ #define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ #define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ #define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) diff --git a/arch/blackfin/include/asm/mach-bf527/BF524_def.h b/arch/blackfin/include/asm/mach-bf527/BF524_def.h index bd6aa8fdb6..0a0056adb0 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF524_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF524_def.h @@ -18,107 +18,6 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ #define USB_FADDR 0xFFC03800 /* Function address register */ #define USB_POWER 0xFFC03804 /* Power management register */ #define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h index 8fe29db07a..415eb07af0 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF525_cdef.h @@ -1,848 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF525_proc__ -#define __BFIN_CDEF_ADSP_BF525_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_BF525_proc__ */ +#include "BF524_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf527/BF525_def.h b/arch/blackfin/include/asm/mach-bf527/BF525_def.h index 5e88b3b468..930cb595c6 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF525_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF525_def.h @@ -1,292 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF525_proc__ -#define __BFIN_DEF_ADSP_BF525_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define USB_FADDR 0xFFC03800 /* Function address register */ -#define USB_POWER 0xFFC03804 /* Power management register */ -#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03820 /* USB frame number */ -#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_BF525_proc__ */ +#include "BF524_def.h" diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h index 943886210b..aa320ac8c4 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF526_cdef.h @@ -10,1075 +10,516 @@ #include "ADSP-EDN-BF52x-extended_cdef.h" -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ #define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ #define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ #define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ #define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ #define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ #define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ #define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ #define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ #define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ #define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ #define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ #define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ #define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ #define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ #define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ #define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ #define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ #define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ #define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ #define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ #define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ #define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ #define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ #define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ #define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ #define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ #define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ #define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ #define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ #define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ #define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ #define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ #define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ #define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ #define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ #define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ #define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ #define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ #define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ #define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ #define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ #define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ #define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ #define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ #define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ #define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ #define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ #define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ #define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ #define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ #define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ #define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ #define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ #define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ #define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ #define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ #define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ #define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ #define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ #define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ #define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ #define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ #define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ #define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ #define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ #define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ #define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ #define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ #define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ #define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ #define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ #define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ #define bfin_read_USB_POWER() bfin_read16(USB_POWER) #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ #define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ #define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ #define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ #define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ #define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ #define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ #define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ #define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) diff --git a/arch/blackfin/include/asm/mach-bf527/BF526_def.h b/arch/blackfin/include/asm/mach-bf527/BF526_def.h index 2644abf197..935d11ee65 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF526_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF526_def.h @@ -18,107 +18,6 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ #define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h index fb9b30793d..c5abe62dba 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h +++ b/arch/blackfin/include/asm/mach-bf527/BF527_cdef.h @@ -1,1085 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF527_proc__ -#define __BFIN_CDEF_ADSP_BF527_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF52x-extended_cdef.h" - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ -#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) -#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ -#define bfin_read_USB_POWER() bfin_read16(USB_POWER) -#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) -#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ -#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) -#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ -#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) -#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ -#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) -#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ -#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) -#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ -#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) -#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ -#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) -#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ -#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) -#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ -#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) -#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) -#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ -#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) -#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ -#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) -#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) -#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) -#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ -#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) -#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ -#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) -#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) -#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) -#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) -#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) -#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) -#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) -#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) -#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) -#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ -#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) -#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ -#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) -#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ -#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) -#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ -#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) -#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ -#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) -#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ -#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) -#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ -#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) -#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ -#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) -#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ -#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) -#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ -#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) -#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ -#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) -#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ -#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) -#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ -#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) -#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ -#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) -#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ -#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) -#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ -#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) -#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ -#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) -#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ -#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) -#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) -#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ -#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) -#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ -#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) -#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) -#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) -#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) -#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) -#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) -#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ -#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) -#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) -#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ -#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) -#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) -#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) -#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) -#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) -#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ -#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) -#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) -#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) -#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ -#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) -#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) -#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ -#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) -#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) -#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) -#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) -#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) -#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ -#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) -#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) -#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) -#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ -#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) -#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) -#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ -#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) -#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) -#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) -#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) -#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) -#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ -#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) -#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) -#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) -#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ -#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) -#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) -#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ -#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) -#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) -#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) -#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) -#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) -#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ -#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) -#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) -#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) -#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ -#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) -#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) -#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ -#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) -#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) -#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) -#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) -#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) -#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ -#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) -#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) -#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) -#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ -#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) -#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) -#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ -#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) -#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) -#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) -#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) -#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) -#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ -#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) -#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) -#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) -#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ -#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) -#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) -#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ -#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) -#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) -#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) -#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) -#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) -#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ -#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) -#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) -#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) -#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ -#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) -#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) -#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ -#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) -#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) -#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) -#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) -#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ -#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) -#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ -#define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) -#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) -#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) -#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) -#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) -#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ -#define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) -#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) -#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) -#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) -#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) -#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ -#define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) -#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) -#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) -#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) -#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) -#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ -#define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) -#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) -#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) -#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) -#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) -#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ -#define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) -#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) -#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) -#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) -#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) -#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ -#define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) -#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) -#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) -#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) -#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) -#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ -#define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) -#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) -#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) -#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) -#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) -#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ -#define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) -#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) -#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) -#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) -#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) -#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) - -#endif /* __BFIN_CDEF_ADSP_BF527_proc__ */ +#include "BF526_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf527/BF527_def.h b/arch/blackfin/include/asm/mach-bf527/BF527_def.h index c46c2b0ee8..95416745f6 100644 --- a/arch/blackfin/include/asm/mach-bf527/BF527_def.h +++ b/arch/blackfin/include/asm/mach-bf527/BF527_def.h @@ -1,371 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF527_proc__ -#define __BFIN_DEF_ADSP_BF527_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF52x-extended_def.h" - -#define PLL_CTL 0xFFC00000 /* PLL Control Register */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ -#define PLL_STAT 0xFFC0000C /* PLL Status Register */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define USB_FADDR 0xFFC03800 /* Function address register */ -#define USB_POWER 0xFFC03804 /* Power management register */ -#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ -#define USB_INTRRX 0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */ -#define USB_INTRTXE 0xFFC03810 /* Interrupt enable register for IntrTx */ -#define USB_INTRRXE 0xFFC03814 /* Interrupt enable register for IntrRx */ -#define USB_INTRUSB 0xFFC03818 /* Interrupt register for common USB interrupts */ -#define USB_INTRUSBE 0xFFC0381C /* Interrupt enable register for IntrUSB */ -#define USB_FRAME 0xFFC03820 /* USB frame number */ -#define USB_INDEX 0xFFC03824 /* Index register for selecting the indexed endpoint registers */ -#define USB_TESTMODE 0xFFC03828 /* Enabled USB 20 test modes */ -#define USB_GLOBINTR 0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */ -#define USB_GLOBAL_CTL 0xFFC03830 /* Global Clock Control for the core */ -#define USB_TX_MAX_PACKET 0xFFC03840 /* Maximum packet size for Host Tx endpoint */ -#define USB_CSR0 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_TXCSR 0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ -#define USB_RX_MAX_PACKET 0xFFC03848 /* Maximum packet size for Host Rx endpoint */ -#define USB_RXCSR 0xFFC0384C /* Control Status register for Host Rx endpoint */ -#define USB_COUNT0 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_RXCOUNT 0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ -#define USB_TXTYPE 0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ -#define USB_NAKLIMIT0 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_TXINTERVAL 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ -#define USB_RXTYPE 0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ -#define USB_RXINTERVAL 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ -#define USB_TXCOUNT 0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ -#define USB_EP0_FIFO 0xFFC03880 /* Endpoint 0 FIFO */ -#define USB_EP1_FIFO 0xFFC03888 /* Endpoint 1 FIFO */ -#define USB_EP2_FIFO 0xFFC03890 /* Endpoint 2 FIFO */ -#define USB_EP3_FIFO 0xFFC03898 /* Endpoint 3 FIFO */ -#define USB_EP4_FIFO 0xFFC038A0 /* Endpoint 4 FIFO */ -#define USB_EP5_FIFO 0xFFC038A8 /* Endpoint 5 FIFO */ -#define USB_EP6_FIFO 0xFFC038B0 /* Endpoint 6 FIFO */ -#define USB_EP7_FIFO 0xFFC038B8 /* Endpoint 7 FIFO */ -#define USB_OTG_DEV_CTL 0xFFC03900 /* OTG Device Control Register */ -#define USB_OTG_VBUS_IRQ 0xFFC03904 /* OTG VBUS Control Interrupts */ -#define USB_OTG_VBUS_MASK 0xFFC03908 /* VBUS Control Interrupt Enable */ -#define USB_LINKINFO 0xFFC03948 /* Enables programming of some PHY-side delays */ -#define USB_VPLEN 0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */ -#define USB_HS_EOF1 0xFFC03950 /* Time buffer for High-Speed transactions */ -#define USB_FS_EOF1 0xFFC03954 /* Time buffer for Full-Speed transactions */ -#define USB_LS_EOF1 0xFFC03958 /* Time buffer for Low-Speed transactions */ -#define USB_APHY_CNTRL 0xFFC039E0 /* Register that increases visibility of Analog PHY */ -#define USB_APHY_CALIB 0xFFC039E4 /* Register used to set some calibration values */ -#define USB_APHY_CNTRL2 0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ -#define USB_PHY_TEST 0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */ -#define USB_PLLOSC_CTRL 0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */ -#define USB_SRP_CLKDIV 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ -#define USB_EP_NI0_TXMAXP 0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */ -#define USB_EP_NI0_TXCSR 0xFFC03A04 /* Control Status register for endpoint 0 */ -#define USB_EP_NI0_RXMAXP 0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCSR 0xFFC03A0C /* Control Status register for Host Rx endpoint0 */ -#define USB_EP_NI0_RXCOUNT 0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */ -#define USB_EP_NI0_TXTYPE 0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ -#define USB_EP_NI0_TXINTERVAL 0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */ -#define USB_EP_NI0_RXTYPE 0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ -#define USB_EP_NI0_RXINTERVAL 0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ -#define USB_EP_NI0_TXCOUNT 0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ -#define USB_EP_NI1_TXMAXP 0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */ -#define USB_EP_NI1_TXCSR 0xFFC03A44 /* Control Status register for endpoint1 */ -#define USB_EP_NI1_RXMAXP 0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCSR 0xFFC03A4C /* Control Status register for Host Rx endpoint1 */ -#define USB_EP_NI1_RXCOUNT 0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */ -#define USB_EP_NI1_TXTYPE 0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ -#define USB_EP_NI1_TXINTERVAL 0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */ -#define USB_EP_NI1_RXTYPE 0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ -#define USB_EP_NI1_RXINTERVAL 0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ -#define USB_EP_NI1_TXCOUNT 0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ -#define USB_EP_NI2_TXMAXP 0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */ -#define USB_EP_NI2_TXCSR 0xFFC03A84 /* Control Status register for endpoint2 */ -#define USB_EP_NI2_RXMAXP 0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCSR 0xFFC03A8C /* Control Status register for Host Rx endpoint2 */ -#define USB_EP_NI2_RXCOUNT 0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */ -#define USB_EP_NI2_TXTYPE 0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ -#define USB_EP_NI2_TXINTERVAL 0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */ -#define USB_EP_NI2_RXTYPE 0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ -#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ -#define USB_EP_NI2_TXCOUNT 0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ -#define USB_EP_NI3_TXMAXP 0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */ -#define USB_EP_NI3_TXCSR 0xFFC03AC4 /* Control Status register for endpoint3 */ -#define USB_EP_NI3_RXMAXP 0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCSR 0xFFC03ACC /* Control Status register for Host Rx endpoint3 */ -#define USB_EP_NI3_RXCOUNT 0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */ -#define USB_EP_NI3_TXTYPE 0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ -#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */ -#define USB_EP_NI3_RXTYPE 0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ -#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ -#define USB_EP_NI3_TXCOUNT 0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ -#define USB_EP_NI4_TXMAXP 0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */ -#define USB_EP_NI4_TXCSR 0xFFC03B04 /* Control Status register for endpoint4 */ -#define USB_EP_NI4_RXMAXP 0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCSR 0xFFC03B0C /* Control Status register for Host Rx endpoint4 */ -#define USB_EP_NI4_RXCOUNT 0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */ -#define USB_EP_NI4_TXTYPE 0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ -#define USB_EP_NI4_TXINTERVAL 0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */ -#define USB_EP_NI4_RXTYPE 0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ -#define USB_EP_NI4_RXINTERVAL 0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ -#define USB_EP_NI4_TXCOUNT 0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ -#define USB_EP_NI5_TXMAXP 0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */ -#define USB_EP_NI5_TXCSR 0xFFC03B44 /* Control Status register for endpoint5 */ -#define USB_EP_NI5_RXMAXP 0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCSR 0xFFC03B4C /* Control Status register for Host Rx endpoint5 */ -#define USB_EP_NI5_RXCOUNT 0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */ -#define USB_EP_NI5_TXTYPE 0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ -#define USB_EP_NI5_TXINTERVAL 0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */ -#define USB_EP_NI5_RXTYPE 0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ -#define USB_EP_NI5_RXINTERVAL 0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ -#define USB_EP_NI5_TXCOUNT 0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ -#define USB_EP_NI6_TXMAXP 0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */ -#define USB_EP_NI6_TXCSR 0xFFC03B84 /* Control Status register for endpoint6 */ -#define USB_EP_NI6_RXMAXP 0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCSR 0xFFC03B8C /* Control Status register for Host Rx endpoint6 */ -#define USB_EP_NI6_RXCOUNT 0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */ -#define USB_EP_NI6_TXTYPE 0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ -#define USB_EP_NI6_TXINTERVAL 0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */ -#define USB_EP_NI6_RXTYPE 0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ -#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ -#define USB_EP_NI6_TXCOUNT 0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ -#define USB_EP_NI7_TXMAXP 0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */ -#define USB_EP_NI7_TXCSR 0xFFC03BC4 /* Control Status register for endpoint7 */ -#define USB_EP_NI7_RXMAXP 0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCSR 0xFFC03BCC /* Control Status register for Host Rx endpoint7 */ -#define USB_EP_NI7_RXCOUNT 0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */ -#define USB_EP_NI7_TXTYPE 0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ -#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */ -#define USB_EP_NI7_RXTYPE 0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ -#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ -#define USB_EP_NI7_TXCOUNT 0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ -#define USB_DMA_INTERRUPT 0xFFC03C00 /* Indicates pending interrupts for the DMA channels */ -#define USB_DMA0_CONTROL 0xFFC03C04 /* DMA master channel 0 configuration */ -#define USB_DMA0_ADDRLOW 0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_ADDRHIGH 0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ -#define USB_DMA0_COUNTLOW 0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA0_COUNTHIGH 0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ -#define USB_DMA1_CONTROL 0xFFC03C24 /* DMA master channel 1 configuration */ -#define USB_DMA1_ADDRLOW 0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_ADDRHIGH 0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ -#define USB_DMA1_COUNTLOW 0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA1_COUNTHIGH 0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ -#define USB_DMA2_CONTROL 0xFFC03C44 /* DMA master channel 2 configuration */ -#define USB_DMA2_ADDRLOW 0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_ADDRHIGH 0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ -#define USB_DMA2_COUNTLOW 0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA2_COUNTHIGH 0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ -#define USB_DMA3_CONTROL 0xFFC03C64 /* DMA master channel 3 configuration */ -#define USB_DMA3_ADDRLOW 0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_ADDRHIGH 0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ -#define USB_DMA3_COUNTLOW 0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA3_COUNTHIGH 0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ -#define USB_DMA4_CONTROL 0xFFC03C84 /* DMA master channel 4 configuration */ -#define USB_DMA4_ADDRLOW 0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_ADDRHIGH 0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ -#define USB_DMA4_COUNTLOW 0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA4_COUNTHIGH 0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ -#define USB_DMA5_CONTROL 0xFFC03CA4 /* DMA master channel 5 configuration */ -#define USB_DMA5_ADDRLOW 0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_ADDRHIGH 0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ -#define USB_DMA5_COUNTLOW 0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA5_COUNTHIGH 0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ -#define USB_DMA6_CONTROL 0xFFC03CC4 /* DMA master channel 6 configuration */ -#define USB_DMA6_ADDRLOW 0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_ADDRHIGH 0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ -#define USB_DMA6_COUNTLOW 0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA6_COUNTHIGH 0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ -#define USB_DMA7_CONTROL 0xFFC03CE4 /* DMA master channel 7 configuration */ -#define USB_DMA7_ADDRLOW 0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_ADDRHIGH 0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ -#define USB_DMA7_COUNTLOW 0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ -#define USB_DMA7_COUNTHIGH 0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ - -#endif /* __BFIN_DEF_ADSP_BF527_proc__ */ +#include "BF526_def.h" diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h index 49a2b2e1ab..2572bfa908 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h +++ b/arch/blackfin/include/asm/mach-bf533/BF531_cdef.h @@ -8,7 +8,865 @@ #include "../mach-common/ADSP-EDN-core_cdef.h" -#include "../mach-common/ADSP-EDN-extended_cdef.h" - +#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D) +#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val) +#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D) +#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val) +#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D) +#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val) +#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D) +#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val) +#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D) +#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val) +#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D) +#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val) +#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D) +#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val) +#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D) +#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val) +#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D) +#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val) +#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S) +#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val) +#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S) +#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val) +#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S) +#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val) +#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S) +#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val) +#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S) +#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val) +#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S) +#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val) +#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S) +#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val) +#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S) +#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val) +#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S) +#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val) +#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D) +#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val) +#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D) +#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val) +#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D) +#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val) +#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D) +#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val) +#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D) +#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val) +#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D) +#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val) +#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D) +#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val) +#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D) +#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val) +#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D) +#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val) +#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S) +#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val) +#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S) +#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val) +#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S) +#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val) +#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S) +#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val) +#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S) +#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val) +#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S) +#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val) +#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S) +#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val) +#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S) +#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val) +#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S) +#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val) +#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG) +#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val) +#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT) +#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val) +#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY) +#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val) +#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT) +#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val) +#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY) +#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val) +#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT) +#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val) +#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP) +#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val) +#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT) +#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val) +#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT) +#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val) +#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG) +#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val) +#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT) +#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val) +#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY) +#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val) +#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT) +#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val) +#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY) +#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val) +#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT) +#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val) +#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP) +#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val) +#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT) +#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val) +#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT) +#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val) +#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG) +#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val) +#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT) +#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val) +#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY) +#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val) +#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT) +#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val) +#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY) +#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val) +#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT) +#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val) +#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP) +#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val) +#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT) +#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val) +#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT) +#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val) +#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG) +#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val) +#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT) +#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val) +#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY) +#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val) +#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT) +#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val) +#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY) +#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val) +#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT) +#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val) +#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP) +#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val) +#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT) +#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val) +#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT) +#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val) +#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG) +#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val) +#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT) +#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val) +#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY) +#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val) +#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT) +#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val) +#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY) +#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val) +#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT) +#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val) +#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP) +#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val) +#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT) +#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val) +#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT) +#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val) +#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG) +#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val) +#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT) +#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val) +#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY) +#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val) +#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT) +#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val) +#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY) +#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val) +#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT) +#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val) +#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP) +#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val) +#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT) +#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val) +#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT) +#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val) +#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG) +#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val) +#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT) +#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val) +#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY) +#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val) +#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT) +#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val) +#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY) +#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val) +#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT) +#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val) +#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP) +#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val) +#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT) +#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val) +#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT) +#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val) +#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG) +#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val) +#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT) +#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val) +#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY) +#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val) +#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT) +#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val) +#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY) +#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val) +#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT) +#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val) +#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP) +#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val) +#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT) +#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val) +#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT) +#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) +#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) +#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) +#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) +#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) +#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) +#define bfin_read_UART_THR() bfin_read16(UART_THR) +#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) +#define bfin_read_UART_DLL() bfin_read16(UART_DLL) +#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val) +#define bfin_read_UART_DLH() bfin_read16(UART_DLH) +#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val) +#define bfin_read_UART_IER() bfin_read16(UART_IER) +#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val) +#define bfin_read_UART_IIR() bfin_read16(UART_IIR) +#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val) +#define bfin_read_UART_LCR() bfin_read16(UART_LCR) +#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val) +#define bfin_read_UART_MCR() bfin_read16(UART_MCR) +#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val) +#define bfin_read_UART_LSR() bfin_read16(UART_LSR) +#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val) +#define bfin_read_UART_SCR() bfin_read16(UART_SCR) +#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val) +#define bfin_read_UART_RBR() bfin_read16(UART_RBR) +#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val) +#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) +#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val) +#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0) +#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val) +#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1) +#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val) +#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0) +#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val) +#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1) +#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val) +#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX) +#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val) +#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX) +#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val) +#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV) +#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val) +#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV) +#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val) +#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV) +#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val) +#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV) +#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val) +#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT) +#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val) +#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0) +#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val) +#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1) +#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val) +#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2) +#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val) +#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3) +#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val) +#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0) +#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val) +#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1) +#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val) +#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2) +#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val) +#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3) +#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val) +#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1) +#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val) +#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2) +#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val) +#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL) +#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val) +#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0) +#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val) +#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1) +#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val) +#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0) +#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val) +#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1) +#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val) +#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX) +#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val) +#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX) +#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val) +#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV) +#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val) +#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV) +#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val) +#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV) +#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val) +#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV) +#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val) +#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT) +#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val) +#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0) +#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val) +#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1) +#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val) +#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2) +#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val) +#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3) +#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val) +#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0) +#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val) +#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1) +#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val) +#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2) +#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val) +#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3) +#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val) +#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1) +#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val) +#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2) +#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val) +#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL) +#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val) +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) +#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) +#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) +#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) +#define bfin_read_TBUF() bfin_readPTR(TBUF) +#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) +#define bfin_read_PFCTL() bfin_read32(PFCTL) +#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) +#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) +#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) +#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) +#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) +#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) +#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) +#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) +#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) +#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) +#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) +#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) +#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) +#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) +#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val) +#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) +#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val) +#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) +#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val) +#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) +#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val) +#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) +#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val) +#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) +#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val) +#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) +#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val) +#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) +#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val) +#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) +#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val) +#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) +#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val) +#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) +#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val) +#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) +#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val) +#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) +#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) +#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) +#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) +#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) +#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) +#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) +#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) +#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) +#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) +#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) +#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) +#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) +#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) +#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) +#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) +#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) +#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) +#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) +#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) +#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) +#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) +#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) +#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) +#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) +#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) +#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) +#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) +#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) +#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) +#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) +#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) +#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) +#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) +#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) +#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) +#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) +#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) +#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) +#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) +#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) +#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) +#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) +#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) +#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) +#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) +#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) +#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) +#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) +#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) +#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) +#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) +#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) +#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) +#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) +#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) +#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) +#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) +#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) +#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) +#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) +#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) +#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) +#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) +#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) +#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) +#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) +#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) +#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) +#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) +#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) +#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) +#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) +#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) +#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) +#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) +#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) +#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) +#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) +#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) +#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) #endif /* __BFIN_CDEF_ADSP_BF531_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF531_def.h b/arch/blackfin/include/asm/mach-bf533/BF531_def.h index d7278e56ec..5d61972176 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF531_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF531_def.h @@ -8,8 +8,433 @@ #include "../mach-common/ADSP-EDN-core_def.h" -#include "../mach-common/ADSP-EDN-extended_def.h" +#define MDMAFLX0_DMACNFG_D 0xFFC00E08 +#define MDMAFLX0_XCOUNT_D 0xFFC00E10 +#define MDMAFLX0_XMODIFY_D 0xFFC00E14 +#define MDMAFLX0_YCOUNT_D 0xFFC00E18 +#define MDMAFLX0_YMODIFY_D 0xFFC00E1C +#define MDMAFLX0_IRQSTAT_D 0xFFC00E28 +#define MDMAFLX0_PMAP_D 0xFFC00E2C +#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30 +#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38 +#define MDMAFLX0_DMACNFG_S 0xFFC00E48 +#define MDMAFLX0_XCOUNT_S 0xFFC00E50 +#define MDMAFLX0_XMODIFY_S 0xFFC00E54 +#define MDMAFLX0_YCOUNT_S 0xFFC00E58 +#define MDMAFLX0_YMODIFY_S 0xFFC00E5C +#define MDMAFLX0_IRQSTAT_S 0xFFC00E68 +#define MDMAFLX0_PMAP_S 0xFFC00E6C +#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70 +#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78 +#define MDMAFLX1_DMACNFG_D 0xFFC00E88 +#define MDMAFLX1_XCOUNT_D 0xFFC00E90 +#define MDMAFLX1_XMODIFY_D 0xFFC00E94 +#define MDMAFLX1_YCOUNT_D 0xFFC00E98 +#define MDMAFLX1_YMODIFY_D 0xFFC00E9C +#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8 +#define MDMAFLX1_PMAP_D 0xFFC00EAC +#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0 +#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8 +#define MDMAFLX1_DMACNFG_S 0xFFC00EC8 +#define MDMAFLX1_XCOUNT_S 0xFFC00ED0 +#define MDMAFLX1_XMODIFY_S 0xFFC00ED4 +#define MDMAFLX1_YCOUNT_S 0xFFC00ED8 +#define MDMAFLX1_YMODIFY_S 0xFFC00EDC +#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8 +#define MDMAFLX1_PMAP_S 0xFFC00EEC +#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0 +#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8 +#define DMAFLX0_DMACNFG 0xFFC00C08 +#define DMAFLX0_XCOUNT 0xFFC00C10 +#define DMAFLX0_XMODIFY 0xFFC00C14 +#define DMAFLX0_YCOUNT 0xFFC00C18 +#define DMAFLX0_YMODIFY 0xFFC00C1C +#define DMAFLX0_IRQSTAT 0xFFC00C28 +#define DMAFLX0_PMAP 0xFFC00C2C +#define DMAFLX0_CURXCOUNT 0xFFC00C30 +#define DMAFLX0_CURYCOUNT 0xFFC00C38 +#define DMAFLX1_DMACNFG 0xFFC00C48 +#define DMAFLX1_XCOUNT 0xFFC00C50 +#define DMAFLX1_XMODIFY 0xFFC00C54 +#define DMAFLX1_YCOUNT 0xFFC00C58 +#define DMAFLX1_YMODIFY 0xFFC00C5C +#define DMAFLX1_IRQSTAT 0xFFC00C68 +#define DMAFLX1_PMAP 0xFFC00C6C +#define DMAFLX1_CURXCOUNT 0xFFC00C70 +#define DMAFLX1_CURYCOUNT 0xFFC00C78 +#define DMAFLX2_DMACNFG 0xFFC00C88 +#define DMAFLX2_XCOUNT 0xFFC00C90 +#define DMAFLX2_XMODIFY 0xFFC00C94 +#define DMAFLX2_YCOUNT 0xFFC00C98 +#define DMAFLX2_YMODIFY 0xFFC00C9C +#define DMAFLX2_IRQSTAT 0xFFC00CA8 +#define DMAFLX2_PMAP 0xFFC00CAC +#define DMAFLX2_CURXCOUNT 0xFFC00CB0 +#define DMAFLX2_CURYCOUNT 0xFFC00CB8 +#define DMAFLX3_DMACNFG 0xFFC00CC8 +#define DMAFLX3_XCOUNT 0xFFC00CD0 +#define DMAFLX3_XMODIFY 0xFFC00CD4 +#define DMAFLX3_YCOUNT 0xFFC00CD8 +#define DMAFLX3_YMODIFY 0xFFC00CDC +#define DMAFLX3_IRQSTAT 0xFFC00CE8 +#define DMAFLX3_PMAP 0xFFC00CEC +#define DMAFLX3_CURXCOUNT 0xFFC00CF0 +#define DMAFLX3_CURYCOUNT 0xFFC00CF8 +#define DMAFLX4_DMACNFG 0xFFC00D08 +#define DMAFLX4_XCOUNT 0xFFC00D10 +#define DMAFLX4_XMODIFY 0xFFC00D14 +#define DMAFLX4_YCOUNT 0xFFC00D18 +#define DMAFLX4_YMODIFY 0xFFC00D1C +#define DMAFLX4_IRQSTAT 0xFFC00D28 +#define DMAFLX4_PMAP 0xFFC00D2C +#define DMAFLX4_CURXCOUNT 0xFFC00D30 +#define DMAFLX4_CURYCOUNT 0xFFC00D38 +#define DMAFLX5_DMACNFG 0xFFC00D48 +#define DMAFLX5_XCOUNT 0xFFC00D50 +#define DMAFLX5_XMODIFY 0xFFC00D54 +#define DMAFLX5_YCOUNT 0xFFC00D58 +#define DMAFLX5_YMODIFY 0xFFC00D5C +#define DMAFLX5_IRQSTAT 0xFFC00D68 +#define DMAFLX5_PMAP 0xFFC00D6C +#define DMAFLX5_CURXCOUNT 0xFFC00D70 +#define DMAFLX5_CURYCOUNT 0xFFC00D78 +#define DMAFLX6_DMACNFG 0xFFC00D88 +#define DMAFLX6_XCOUNT 0xFFC00D90 +#define DMAFLX6_XMODIFY 0xFFC00D94 +#define DMAFLX6_YCOUNT 0xFFC00D98 +#define DMAFLX6_YMODIFY 0xFFC00D9C +#define DMAFLX6_IRQSTAT 0xFFC00DA8 +#define DMAFLX6_PMAP 0xFFC00DAC +#define DMAFLX6_CURXCOUNT 0xFFC00DB0 +#define DMAFLX6_CURYCOUNT 0xFFC00DB8 +#define DMAFLX7_DMACNFG 0xFFC00DC8 +#define DMAFLX7_XCOUNT 0xFFC00DD0 +#define DMAFLX7_XMODIFY 0xFFC00DD4 +#define DMAFLX7_YCOUNT 0xFFC00DD8 +#define DMAFLX7_YMODIFY 0xFFC00DDC +#define DMAFLX7_IRQSTAT 0xFFC00DE8 +#define DMAFLX7_PMAP 0xFFC00DEC +#define DMAFLX7_CURXCOUNT 0xFFC00DF0 +#define DMAFLX7_CURYCOUNT 0xFFC00DF8 +#define TIMER0_CONFIG 0xFFC00600 +#define TIMER0_COUNTER 0xFFC00604 +#define TIMER0_PERIOD 0xFFC00608 +#define TIMER0_WIDTH 0xFFC0060C +#define TIMER1_CONFIG 0xFFC00610 +#define TIMER1_COUNTER 0xFFC00614 +#define TIMER1_PERIOD 0xFFC00618 +#define TIMER1_WIDTH 0xFFC0061C +#define TIMER2_CONFIG 0xFFC00620 +#define TIMER2_COUNTER 0xFFC00624 +#define TIMER2_PERIOD 0xFFC00628 +#define TIMER2_WIDTH 0xFFC0062C +#define TIMER_ENABLE 0xFFC00640 +#define TIMER_DISABLE 0xFFC00644 +#define TIMER_STATUS 0xFFC00648 +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ +#define UART_THR 0xFFC00400 /* Transmit Holding */ +#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */ +#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */ +#define UART_IER 0xFFC00404 +#define UART_IIR 0xFFC00408 +#define UART_LCR 0xFFC0040C +#define UART_MCR 0xFFC00410 +#define UART_LSR 0xFFC00414 +#define UART_SCR 0xFFC0041C +#define UART_RBR 0xFFC00400 /* Receive Buffer */ +#define UART_GCTL 0xFFC00424 +#define SPT0_TX_CONFIG0 0xFFC00800 +#define SPT0_TX_CONFIG1 0xFFC00804 +#define SPT0_RX_CONFIG0 0xFFC00820 +#define SPT0_RX_CONFIG1 0xFFC00824 +#define SPT0_TX 0xFFC00810 +#define SPT0_RX 0xFFC00818 +#define SPT0_TSCLKDIV 0xFFC00808 +#define SPT0_RSCLKDIV 0xFFC00828 +#define SPT0_TFSDIV 0xFFC0080C +#define SPT0_RFSDIV 0xFFC0082C +#define SPT0_STAT 0xFFC00830 +#define SPT0_MTCS0 0xFFC00840 +#define SPT0_MTCS1 0xFFC00844 +#define SPT0_MTCS2 0xFFC00848 +#define SPT0_MTCS3 0xFFC0084C +#define SPT0_MRCS0 0xFFC00850 +#define SPT0_MRCS1 0xFFC00854 +#define SPT0_MRCS2 0xFFC00858 +#define SPT0_MRCS3 0xFFC0085C +#define SPT0_MCMC1 0xFFC00838 +#define SPT0_MCMC2 0xFFC0083C +#define SPT0_CHNL 0xFFC00834 +#define SPT1_TX_CONFIG0 0xFFC00900 +#define SPT1_TX_CONFIG1 0xFFC00904 +#define SPT1_RX_CONFIG0 0xFFC00920 +#define SPT1_RX_CONFIG1 0xFFC00924 +#define SPT1_TX 0xFFC00910 +#define SPT1_RX 0xFFC00918 +#define SPT1_TSCLKDIV 0xFFC00908 +#define SPT1_RSCLKDIV 0xFFC00928 +#define SPT1_TFSDIV 0xFFC0090C +#define SPT1_RFSDIV 0xFFC0092C +#define SPT1_STAT 0xFFC00930 +#define SPT1_MTCS0 0xFFC00940 +#define SPT1_MTCS1 0xFFC00944 +#define SPT1_MTCS2 0xFFC00948 +#define SPT1_MTCS3 0xFFC0094C +#define SPT1_MRCS0 0xFFC00950 +#define SPT1_MRCS1 0xFFC00954 +#define SPT1_MRCS2 0xFFC00958 +#define SPT1_MRCS3 0xFFC0095C +#define SPT1_MCMC1 0xFFC00938 +#define SPT1_MCMC2 0xFFC0093C +#define SPT1_CHNL 0xFFC00934 +#define PPI_CONTROL 0xFFC01000 +#define PPI_STATUS 0xFFC01004 +#define PPI_DELAY 0xFFC0100C +#define PPI_COUNT 0xFFC01008 +#define PPI_FRAME 0xFFC01010 +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ +#define SYSCR 0xFFC00104 /* System Configuration register */ +#define CHIPID 0xFFC00014 +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ +#define RTC_STAT 0xFFC00300 +#define RTC_ICTL 0xFFC00304 +#define RTC_ISTAT 0xFFC00308 +#define RTC_SWCNT 0xFFC0030C +#define RTC_ALARM 0xFFC00310 +#define RTC_PREN 0xFFC00314 +#define SPI_CTL 0xFFC00500 +#define SPI_FLG 0xFFC00504 +#define SPI_STAT 0xFFC00508 +#define SPI_TDBR 0xFFC0050C +#define SPI_RDBR 0xFFC00510 +#define SPI_BAUD 0xFFC00514 +#define SPI_SHADOW 0xFFC00518 +#define FIO_FLAG_D 0xFFC00700 +#define FIO_FLAG_C 0xFFC00704 +#define FIO_FLAG_S 0xFFC00708 +#define FIO_FLAG_T 0xFFC0070C +#define FIO_MASKA_D 0xFFC00710 +#define FIO_MASKA_C 0xFFC00714 +#define FIO_MASKA_S 0xFFC00718 +#define FIO_MASKA_T 0xFFC0071C +#define FIO_MASKB_D 0xFFC00720 +#define FIO_MASKB_C 0xFFC00724 +#define FIO_MASKB_S 0xFFC00728 +#define FIO_MASKB_T 0xFFC0072C +#define FIO_DIR 0xFFC00730 +#define FIO_POLAR 0xFFC00734 +#define FIO_EDGE 0xFFC00738 +#define FIO_BOTH 0xFFC0073C +#define FIO_INEN 0xFFC00740 +#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ +#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ +#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ +#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ +#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ +#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ +#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ +#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ +#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ +#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ +#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ +#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ +#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ +#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ +#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ +#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ +#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ +#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ +#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 +#define DMA0_START_ADDR 0xFFC00C04 +#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ +#define DMA0_X_COUNT 0xFFC00C10 +#define DMA0_X_MODIFY 0xFFC00C14 +#define DMA0_Y_COUNT 0xFFC00C18 +#define DMA0_Y_MODIFY 0xFFC00C1C +#define DMA0_CURR_DESC_PTR 0xFFC00C20 +#define DMA0_CURR_ADDR 0xFFC00C24 +#define DMA0_IRQ_STATUS 0xFFC00C28 +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C +#define DMA0_CURR_X_COUNT 0xFFC00C30 +#define DMA0_CURR_Y_COUNT 0xFFC00C38 +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 +#define DMA1_START_ADDR 0xFFC00C44 +#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ +#define DMA1_X_COUNT 0xFFC00C50 +#define DMA1_X_MODIFY 0xFFC00C54 +#define DMA1_Y_COUNT 0xFFC00C58 +#define DMA1_Y_MODIFY 0xFFC00C5C +#define DMA1_CURR_DESC_PTR 0xFFC00C60 +#define DMA1_CURR_ADDR 0xFFC00C64 +#define DMA1_IRQ_STATUS 0xFFC00C68 +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C +#define DMA1_CURR_X_COUNT 0xFFC00C70 +#define DMA1_CURR_Y_COUNT 0xFFC00C78 +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 +#define DMA2_START_ADDR 0xFFC00C84 +#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ +#define DMA2_X_COUNT 0xFFC00C90 +#define DMA2_X_MODIFY 0xFFC00C94 +#define DMA2_Y_COUNT 0xFFC00C98 +#define DMA2_Y_MODIFY 0xFFC00C9C +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 +#define DMA2_CURR_ADDR 0xFFC00CA4 +#define DMA2_IRQ_STATUS 0xFFC00CA8 +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC +#define DMA2_CURR_X_COUNT 0xFFC00CB0 +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 +#define DMA3_START_ADDR 0xFFC00CC4 +#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ +#define DMA3_X_COUNT 0xFFC00CD0 +#define DMA3_X_MODIFY 0xFFC00CD4 +#define DMA3_Y_COUNT 0xFFC00CD8 +#define DMA3_Y_MODIFY 0xFFC00CDC +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 +#define DMA3_CURR_ADDR 0xFFC00CE4 +#define DMA3_IRQ_STATUS 0xFFC00CE8 +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC +#define DMA3_CURR_X_COUNT 0xFFC00CF0 +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 +#define DMA4_START_ADDR 0xFFC00D04 +#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ +#define DMA4_X_COUNT 0xFFC00D10 +#define DMA4_X_MODIFY 0xFFC00D14 +#define DMA4_Y_COUNT 0xFFC00D18 +#define DMA4_Y_MODIFY 0xFFC00D1C +#define DMA4_CURR_DESC_PTR 0xFFC00D20 +#define DMA4_CURR_ADDR 0xFFC00D24 +#define DMA4_IRQ_STATUS 0xFFC00D28 +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C +#define DMA4_CURR_X_COUNT 0xFFC00D30 +#define DMA4_CURR_Y_COUNT 0xFFC00D38 +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 +#define DMA5_START_ADDR 0xFFC00D44 +#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ +#define DMA5_X_COUNT 0xFFC00D50 +#define DMA5_X_MODIFY 0xFFC00D54 +#define DMA5_Y_COUNT 0xFFC00D58 +#define DMA5_Y_MODIFY 0xFFC00D5C +#define DMA5_CURR_DESC_PTR 0xFFC00D60 +#define DMA5_CURR_ADDR 0xFFC00D64 +#define DMA5_IRQ_STATUS 0xFFC00D68 +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C +#define DMA5_CURR_X_COUNT 0xFFC00D70 +#define DMA5_CURR_Y_COUNT 0xFFC00D78 +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 +#define DMA6_START_ADDR 0xFFC00D84 +#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ +#define DMA6_X_COUNT 0xFFC00D90 +#define DMA6_X_MODIFY 0xFFC00D94 +#define DMA6_Y_COUNT 0xFFC00D98 +#define DMA6_Y_MODIFY 0xFFC00D9C +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 +#define DMA6_CURR_ADDR 0xFFC00DA4 +#define DMA6_IRQ_STATUS 0xFFC00DA8 +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC +#define DMA6_CURR_X_COUNT 0xFFC00DB0 +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 +#define DMA7_START_ADDR 0xFFC00DC4 +#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ +#define DMA7_X_COUNT 0xFFC00DD0 +#define DMA7_X_MODIFY 0xFFC00DD4 +#define DMA7_Y_COUNT 0xFFC00DD8 +#define DMA7_Y_MODIFY 0xFFC00DDC +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 +#define DMA7_CURR_ADDR 0xFFC00DE4 +#define DMA7_IRQ_STATUS 0xFFC00DE8 +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC +#define DMA7_CURR_X_COUNT 0xFFC00DF0 +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 +#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 +#define MDMA_D0_START_ADDR 0xFFC00E04 +#define MDMA_D0_CONFIG 0xFFC00E08 +#define MDMA_D0_X_COUNT 0xFFC00E10 +#define MDMA_D0_X_MODIFY 0xFFC00E14 +#define MDMA_D0_Y_COUNT 0xFFC00E18 +#define MDMA_D0_Y_MODIFY 0xFFC00E1C +#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 +#define MDMA_D0_CURR_ADDR 0xFFC00E24 +#define MDMA_D0_IRQ_STATUS 0xFFC00E28 +#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C +#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 +#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 +#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 +#define MDMA_S0_START_ADDR 0xFFC00E44 +#define MDMA_S0_CONFIG 0xFFC00E48 +#define MDMA_S0_X_COUNT 0xFFC00E50 +#define MDMA_S0_X_MODIFY 0xFFC00E54 +#define MDMA_S0_Y_COUNT 0xFFC00E58 +#define MDMA_S0_Y_MODIFY 0xFFC00E5C +#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 +#define MDMA_S0_CURR_ADDR 0xFFC00E64 +#define MDMA_S0_IRQ_STATUS 0xFFC00E68 +#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C +#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 +#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 +#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 +#define MDMA_D1_START_ADDR 0xFFC00E84 +#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ +#define MDMA_D1_X_COUNT 0xFFC00E90 +#define MDMA_D1_X_MODIFY 0xFFC00E94 +#define MDMA_D1_Y_COUNT 0xFFC00E98 +#define MDMA_D1_Y_MODIFY 0xFFC00E9C +#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 +#define MDMA_D1_CURR_ADDR 0xFFC00EA4 +#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 +#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC +#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 +#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 +#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 +#define MDMA_S1_START_ADDR 0xFFC00EC4 +#define MDMA_S1_CONFIG 0xFFC00EC8 +#define MDMA_S1_X_COUNT 0xFFC00ED0 +#define MDMA_S1_X_MODIFY 0xFFC00ED4 +#define MDMA_S1_Y_COUNT 0xFFC00ED8 +#define MDMA_S1_Y_MODIFY 0xFFC00EDC +#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 +#define MDMA_S1_CURR_ADDR 0xFFC00EE4 +#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 +#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC +#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 +#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 +#define EBIU_AMGCTL 0xFFC00A00 +#define EBIU_AMBCTL0 0xFFC00A04 +#define EBIU_AMBCTL1 0xFFC00A08 +#define EBIU_SDGCTL 0xFFC00A10 +#define EBIU_SDBCTL 0xFFC00A14 +#define EBIU_SDRRC 0xFFC00A18 +#define EBIU_SDSTAT 0xFFC00A1C +#define DMA_TC_CNT 0xFFC00B0C +#define DMA_TC_PER 0xFFC00B10 +#ifndef __BFIN_DEF_ADSP_BF533_proc__ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) @@ -19,5 +444,6 @@ #define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ #define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) #define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) +#endif #endif /* __BFIN_DEF_ADSP_BF531_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h index 47b48acf15..09f25211d8 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h +++ b/arch/blackfin/include/asm/mach-bf533/BF532_cdef.h @@ -1,14 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF532_proc__ -#define __BFIN_CDEF_ADSP_BF532_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF532_proc__ */ +#include "BF531_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf533/BF532_def.h b/arch/blackfin/include/asm/mach-bf533/BF532_def.h index 86944d07ee..f7378b70a7 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF532_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF532_def.h @@ -6,10 +6,9 @@ #ifndef __BFIN_DEF_ADSP_BF532_proc__ #define __BFIN_DEF_ADSP_BF532_proc__ -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-extended_def.h" +#include "BF531_def.h" +#ifndef __BFIN_DEF_ADSP_BF533_proc__ #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) @@ -19,5 +18,6 @@ #define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ #define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) #define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) +#endif #endif /* __BFIN_DEF_ADSP_BF532_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h index f270d0188e..3044327069 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h +++ b/arch/blackfin/include/asm/mach-bf533/BF533_cdef.h @@ -1,14 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF533_proc__ -#define __BFIN_CDEF_ADSP_BF533_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "../mach-common/ADSP-EDN-extended_cdef.h" - - -#endif /* __BFIN_CDEF_ADSP_BF533_proc__ */ +#include "BF532_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf533/BF533_def.h b/arch/blackfin/include/asm/mach-bf533/BF533_def.h index 17b5d7f1c4..b77efe0a2c 100644 --- a/arch/blackfin/include/asm/mach-bf533/BF533_def.h +++ b/arch/blackfin/include/asm/mach-bf533/BF533_def.h @@ -6,9 +6,7 @@ #ifndef __BFIN_DEF_ADSP_BF533_proc__ #define __BFIN_DEF_ADSP_BF533_proc__ -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "../mach-common/ADSP-EDN-extended_def.h" +#include "BF532_def.h" #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) diff --git a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h index 07008755f0..bfe6d9f414 100644 --- a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h +++ b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_cdef.h @@ -6,2744 +6,1618 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF534_extended__ #define __BFIN_CDEF_ADSP_EDN_BF534_extended__ -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ +#include "../mach-common/ADSP-EDN-core_cdef.h" + #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ #define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) #define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */ #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */ #define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) #define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) -#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */ #define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) #define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */ #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */ #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */ #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */ #define bfin_read_UART0_IER() bfin_read16(UART0_IER) #define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */ #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */ #define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) #define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */ #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */ #define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) #define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */ #define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) #define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) /* SPI Status register */ #define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) #define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */ #define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) #define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */ #define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) #define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */ #define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) #define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */ #define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) #define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */ #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */ #define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) #define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */ #define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) #define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define pTIMER_STATUS ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */ #define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS) #define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val) -#define pPORTFIO ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */ #define bfin_read_PORTFIO() bfin_read16(PORTFIO) #define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) -#define pPORTFIO_CLEAR ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */ #define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) #define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) -#define pPORTFIO_SET ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */ #define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) #define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) -#define pPORTFIO_TOGGLE ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */ #define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) #define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) -#define pPORTFIO_MASKA ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */ #define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) #define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) -#define pPORTFIO_MASKA_CLEAR ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */ #define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) #define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) -#define pPORTFIO_MASKA_SET ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */ #define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) #define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) -#define pPORTFIO_MASKA_TOGGLE ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */ #define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) #define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) -#define pPORTFIO_MASKB ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */ #define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) #define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) -#define pPORTFIO_MASKB_CLEAR ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */ #define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) #define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) -#define pPORTFIO_MASKB_SET ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */ #define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) #define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) -#define pPORTFIO_MASKB_TOGGLE ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */ #define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) #define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) -#define pPORTFIO_DIR ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */ #define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) #define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) -#define pPORTFIO_POLAR ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */ #define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) #define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) -#define pPORTFIO_EDGE ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */ #define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) #define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) -#define pPORTFIO_BOTH ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */ #define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) #define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) -#define pPORTFIO_INEN ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register */ #define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) #define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi-Channel Transmit Select Register 0 */ #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi-Channel Transmit Select Register 1 */ #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi-Channel Transmit Select Register 2 */ #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi-Channel Transmit Select Register 3 */ #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi-Channel Receive Select Register 0 */ #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi-Channel Receive Select Register 1 */ #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi-Channel Receive Select Register 2 */ #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi-Channel Receive Select Register 3 */ #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi-Channel Transmit Select Register 0 */ #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi-Channel Transmit Select Register 1 */ #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi-Channel Transmit Select Register 2 */ #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi-Channel Transmit Select Register 3 */ #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi-Channel Receive Select Register 0 */ #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi-Channel Receive Select Register 1 */ #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi-Channel Receive Select Register 2 */ #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi-Channel Receive Select Register 3 */ #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register 0 */ #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register 1 */ #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) /* SDRAM Global Control Register */ #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) /* SDRAM Bank Control Register */ #define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) #define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) /* SDRAM Refresh Rate Control Register */ #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) /* SDRAM Status Register */ #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* MemDMA Stream 0 Source Start Address Register */ #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* MemDMA Stream 0 Source Configuration Register */ #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* MemDMA Stream 0 Source X Count Register */ #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* MemDMA Stream 0 Source X Modify Register */ #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* MemDMA Stream 0 Source Y Count Register */ #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* MemDMA Stream 0 Source Y Modify Register */ #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* MemDMA Stream 0 Source Current Address Register */ #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* MemDMA Stream 0 Source Interrupt/Status Register */ #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* MemDMA Stream 0 Source Peripheral Map Register */ #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* MemDMA Stream 0 Source Current X Count Register */ #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* MemDMA Stream 0 Source Current Y Count Register */ #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* MemDMA Stream 0 Destination Start Address Register */ #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* MemDMA Stream 0 Destination Configuration Register */ #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* MemDMA Stream 0 Destination X Count Register */ #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* MemDMA Stream 0 Destination X Modify Register */ #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* MemDMA Stream 0 Destination Y Count Register */ #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* MemDMA Stream 0 Destination Y Modify Register */ #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* MemDMA Stream 0 Destination Current Address Register */ #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* MemDMA Stream 0 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* MemDMA Stream 0 Destination Peripheral Map Register */ #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* MemDMA Stream 0 Destination Current X Count Register */ #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* MemDMA Stream 0 Destination Current Y Count Register */ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* MemDMA Stream 1 Source Start Address Register */ #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* MemDMA Stream 1 Source Configuration Register */ #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* MemDMA Stream 1 Source X Count Register */ #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* MemDMA Stream 1 Source X Modify Register */ #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* MemDMA Stream 1 Source Y Count Register */ #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* MemDMA Stream 1 Source Y Modify Register */ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* MemDMA Stream 1 Source Current Address Register */ #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* MemDMA Stream 1 Source Interrupt/Status Register */ #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* MemDMA Stream 1 Source Peripheral Map Register */ #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* MemDMA Stream 1 Source Current X Count Register */ #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* MemDMA Stream 1 Source Current Y Count Register */ #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* MemDMA Stream 1 Destination Start Address Register */ #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* MemDMA Stream 1 Destination X Count Register */ #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* MemDMA Stream 1 Destination X Modify Register */ #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* MemDMA Stream 1 Destination Y Count Register */ #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* MemDMA Stream 1 Destination Y Modify Register */ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* MemDMA Stream 1 Destination Current Address Register */ #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* MemDMA Stream 1 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* MemDMA Stream 1 Destination Peripheral Map Register */ #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* MemDMA Stream 1 Destination Current X Count Register */ #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* MemDMA Stream 1 Destination Current Y Count Register */ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) /* PPI Control Register */ #define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) /* PPI Status Register */ #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) /* PPI Transfer Count Register */ #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) #define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) /* PPI Delay Count Register */ #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) /* PPI Frame Length Register */ #define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) #define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define pTWI_CLKDIV ((uint16_t volatile *)TWI_CLKDIV) /* Serial Clock Divider Register */ #define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val) -#define pTWI_CONTROL ((uint16_t volatile *)TWI_CONTROL) /* TWI Control Register */ #define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) #define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val) -#define pTWI_SLAVE_CTL ((uint16_t volatile *)TWI_SLAVE_CTL) /* Slave Mode Control Register */ #define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) #define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val) -#define pTWI_SLAVE_STAT ((uint16_t volatile *)TWI_SLAVE_STAT) /* Slave Mode Status Register */ #define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) #define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val) -#define pTWI_SLAVE_ADDR ((uint16_t volatile *)TWI_SLAVE_ADDR) /* Slave Mode Address Register */ #define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) #define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val) -#define pTWI_MASTER_CTL ((uint16_t volatile *)TWI_MASTER_CTL) /* Master Mode Control Register */ #define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) #define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val) -#define pTWI_MASTER_STAT ((uint16_t volatile *)TWI_MASTER_STAT) /* Master Mode Status Register */ #define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) #define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val) -#define pTWI_MASTER_ADDR ((uint16_t volatile *)TWI_MASTER_ADDR) /* Master Mode Address Register */ #define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) #define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val) -#define pTWI_INT_STAT ((uint16_t volatile *)TWI_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) #define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val) -#define pTWI_INT_MASK ((uint16_t volatile *)TWI_INT_MASK) /* TWI Master Interrupt Mask Register */ #define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) #define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val) -#define pTWI_FIFO_CTL ((uint16_t volatile *)TWI_FIFO_CTL) /* FIFO Control Register */ #define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) #define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val) -#define pTWI_FIFO_STAT ((uint16_t volatile *)TWI_FIFO_STAT) /* FIFO Status Register */ #define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) #define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val) -#define pTWI_XMT_DATA8 ((uint16_t volatile *)TWI_XMT_DATA8) /* FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) #define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val) -#define pTWI_XMT_DATA16 ((uint16_t volatile *)TWI_XMT_DATA16) /* FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) #define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val) -#define pTWI_RCV_DATA8 ((uint16_t volatile *)TWI_RCV_DATA8) /* FIFO Receive Data Single Byte Register */ #define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) #define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val) -#define pTWI_RCV_DATA16 ((uint16_t volatile *)TWI_RCV_DATA16) /* FIFO Receive Data Double Byte Register */ #define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) #define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val) -#define pPORTGIO ((uint16_t volatile *)PORTGIO) /* Port G I/O Pin State Specify Register */ #define bfin_read_PORTGIO() bfin_read16(PORTGIO) #define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val) -#define pPORTGIO_CLEAR ((uint16_t volatile *)PORTGIO_CLEAR) /* Port G I/O Peripheral Interrupt Clear Register */ #define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR) #define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val) -#define pPORTGIO_SET ((uint16_t volatile *)PORTGIO_SET) /* Port G I/O Peripheral Interrupt Set Register */ #define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET) #define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val) -#define pPORTGIO_TOGGLE ((uint16_t volatile *)PORTGIO_TOGGLE) /* Port G I/O Pin State Toggle Register */ #define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE) #define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val) -#define pPORTGIO_MASKA ((uint16_t volatile *)PORTGIO_MASKA) /* Port G I/O Mask State Specify Interrupt A Register */ #define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA) #define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val) -#define pPORTGIO_MASKA_CLEAR ((uint16_t volatile *)PORTGIO_MASKA_CLEAR) /* Port G I/O Mask Disable Interrupt A Register */ #define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR) #define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val) -#define pPORTGIO_MASKA_SET ((uint16_t volatile *)PORTGIO_MASKA_SET) /* Port G I/O Mask Enable Interrupt A Register */ #define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET) #define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val) -#define pPORTGIO_MASKA_TOGGLE ((uint16_t volatile *)PORTGIO_MASKA_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt A Register */ #define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE) #define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val) -#define pPORTGIO_MASKB ((uint16_t volatile *)PORTGIO_MASKB) /* Port G I/O Mask State Specify Interrupt B Register */ #define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB) #define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val) -#define pPORTGIO_MASKB_CLEAR ((uint16_t volatile *)PORTGIO_MASKB_CLEAR) /* Port G I/O Mask Disable Interrupt B Register */ #define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR) #define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val) -#define pPORTGIO_MASKB_SET ((uint16_t volatile *)PORTGIO_MASKB_SET) /* Port G I/O Mask Enable Interrupt B Register */ #define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET) #define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val) -#define pPORTGIO_MASKB_TOGGLE ((uint16_t volatile *)PORTGIO_MASKB_TOGGLE) /* Port G I/O Mask Toggle Enable Interrupt B Register */ #define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE) #define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val) -#define pPORTGIO_DIR ((uint16_t volatile *)PORTGIO_DIR) /* Port G I/O Direction Register */ #define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR) #define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val) -#define pPORTGIO_POLAR ((uint16_t volatile *)PORTGIO_POLAR) /* Port G I/O Source Polarity Register */ #define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR) #define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val) -#define pPORTGIO_EDGE ((uint16_t volatile *)PORTGIO_EDGE) /* Port G I/O Source Sensitivity Register */ #define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE) #define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val) -#define pPORTGIO_BOTH ((uint16_t volatile *)PORTGIO_BOTH) /* Port G I/O Set on BOTH Edges Register */ #define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH) #define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val) -#define pPORTGIO_INEN ((uint16_t volatile *)PORTGIO_INEN) /* Port G I/O Input Enable Register */ #define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN) #define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val) -#define pPORTHIO ((uint16_t volatile *)PORTHIO) /* Port H I/O Pin State Specify Register */ #define bfin_read_PORTHIO() bfin_read16(PORTHIO) #define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val) -#define pPORTHIO_CLEAR ((uint16_t volatile *)PORTHIO_CLEAR) /* Port H I/O Peripheral Interrupt Clear Register */ #define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR) #define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val) -#define pPORTHIO_SET ((uint16_t volatile *)PORTHIO_SET) /* Port H I/O Peripheral Interrupt Set Register */ #define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET) #define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val) -#define pPORTHIO_TOGGLE ((uint16_t volatile *)PORTHIO_TOGGLE) /* Port H I/O Pin State Toggle Register */ #define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE) #define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val) -#define pPORTHIO_MASKA ((uint16_t volatile *)PORTHIO_MASKA) /* Port H I/O Mask State Specify Interrupt A Register */ #define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA) #define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val) -#define pPORTHIO_MASKA_CLEAR ((uint16_t volatile *)PORTHIO_MASKA_CLEAR) /* Port H I/O Mask Disable Interrupt A Register */ #define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR) #define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val) -#define pPORTHIO_MASKA_SET ((uint16_t volatile *)PORTHIO_MASKA_SET) /* Port H I/O Mask Enable Interrupt A Register */ #define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET) #define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val) -#define pPORTHIO_MASKA_TOGGLE ((uint16_t volatile *)PORTHIO_MASKA_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt A Register */ #define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE) #define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val) -#define pPORTHIO_MASKB ((uint16_t volatile *)PORTHIO_MASKB) /* Port H I/O Mask State Specify Interrupt B Register */ #define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB) #define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val) -#define pPORTHIO_MASKB_CLEAR ((uint16_t volatile *)PORTHIO_MASKB_CLEAR) /* Port H I/O Mask Disable Interrupt B Register */ #define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR) #define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val) -#define pPORTHIO_MASKB_SET ((uint16_t volatile *)PORTHIO_MASKB_SET) /* Port H I/O Mask Enable Interrupt B Register */ #define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET) #define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val) -#define pPORTHIO_MASKB_TOGGLE ((uint16_t volatile *)PORTHIO_MASKB_TOGGLE) /* Port H I/O Mask Toggle Enable Interrupt B Register */ #define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE) #define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val) -#define pPORTHIO_DIR ((uint16_t volatile *)PORTHIO_DIR) /* Port H I/O Direction Register */ #define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR) #define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val) -#define pPORTHIO_POLAR ((uint16_t volatile *)PORTHIO_POLAR) /* Port H I/O Source Polarity Register */ #define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR) #define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val) -#define pPORTHIO_EDGE ((uint16_t volatile *)PORTHIO_EDGE) /* Port H I/O Source Sensitivity Register */ #define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE) #define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val) -#define pPORTHIO_BOTH ((uint16_t volatile *)PORTHIO_BOTH) /* Port H I/O Set on BOTH Edges Register */ #define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH) #define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val) -#define pPORTHIO_INEN ((uint16_t volatile *)PORTHIO_INEN) /* Port H I/O Input Enable Register */ #define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN) #define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding register */ #define bfin_read_UART1_THR() bfin_read16(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer register */ #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */ #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable Register */ #define bfin_read_UART1_IER() bfin_read16(UART1_IER) #define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */ #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification Register */ #define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) #define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch Register */ #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pCAN_MC1 ((uint16_t volatile *)CAN_MC1) /* Mailbox config reg 1 */ #define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) #define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) -#define pCAN_MD1 ((uint16_t volatile *)CAN_MD1) /* Mailbox direction reg 1 */ #define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) #define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) -#define pCAN_TRS1 ((uint16_t volatile *)CAN_TRS1) /* Transmit Request Set reg 1 */ #define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) #define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) -#define pCAN_TRR1 ((uint16_t volatile *)CAN_TRR1) /* Transmit Request Reset reg 1 */ #define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) #define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) -#define pCAN_TA1 ((uint16_t volatile *)CAN_TA1) /* Transmit Acknowledge reg 1 */ #define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) #define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) -#define pCAN_AA1 ((uint16_t volatile *)CAN_AA1) /* Transmit Abort Acknowledge reg 1 */ #define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) #define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) -#define pCAN_RMP1 ((uint16_t volatile *)CAN_RMP1) /* Receive Message Pending reg 1 */ #define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) #define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) -#define pCAN_RML1 ((uint16_t volatile *)CAN_RML1) /* Receive Message Lost reg 1 */ #define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) #define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) -#define pCAN_MBTIF1 ((uint16_t volatile *)CAN_MBTIF1) /* Mailbox Transmit Interrupt Flag reg 1 */ #define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) #define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) -#define pCAN_MBRIF1 ((uint16_t volatile *)CAN_MBRIF1) /* Mailbox Receive Interrupt Flag reg 1 */ #define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) #define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) -#define pCAN_MBIM1 ((uint16_t volatile *)CAN_MBIM1) /* Mailbox Interrupt Mask reg 1 */ #define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) #define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) -#define pCAN_RFH1 ((uint16_t volatile *)CAN_RFH1) /* Remote Frame Handling reg 1 */ #define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) #define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) -#define pCAN_OPSS1 ((uint16_t volatile *)CAN_OPSS1) /* Overwrite Protection Single Shot Xmission reg 1 */ #define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) #define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) -#define pCAN_MC2 ((uint16_t volatile *)CAN_MC2) /* Mailbox config reg 2 */ #define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) #define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) -#define pCAN_MD2 ((uint16_t volatile *)CAN_MD2) /* Mailbox direction reg 2 */ #define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) #define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) -#define pCAN_TRS2 ((uint16_t volatile *)CAN_TRS2) /* Transmit Request Set reg 2 */ #define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) #define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) -#define pCAN_TRR2 ((uint16_t volatile *)CAN_TRR2) /* Transmit Request Reset reg 2 */ #define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) #define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) -#define pCAN_TA2 ((uint16_t volatile *)CAN_TA2) /* Transmit Acknowledge reg 2 */ #define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) #define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) -#define pCAN_AA2 ((uint16_t volatile *)CAN_AA2) /* Transmit Abort Acknowledge reg 2 */ #define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) #define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) -#define pCAN_RMP2 ((uint16_t volatile *)CAN_RMP2) /* Receive Message Pending reg 2 */ #define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) #define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) -#define pCAN_RML2 ((uint16_t volatile *)CAN_RML2) /* Receive Message Lost reg 2 */ #define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) #define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) -#define pCAN_MBTIF2 ((uint16_t volatile *)CAN_MBTIF2) /* Mailbox Transmit Interrupt Flag reg 2 */ #define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) #define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) -#define pCAN_MBRIF2 ((uint16_t volatile *)CAN_MBRIF2) /* Mailbox Receive Interrupt Flag reg 2 */ #define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) #define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) -#define pCAN_MBIM2 ((uint16_t volatile *)CAN_MBIM2) /* Mailbox Interrupt Mask reg 2 */ #define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) #define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) -#define pCAN_RFH2 ((uint16_t volatile *)CAN_RFH2) /* Remote Frame Handling reg 2 */ #define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) #define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) -#define pCAN_OPSS2 ((uint16_t volatile *)CAN_OPSS2) /* Overwrite Protection Single Shot Xmission reg 2 */ #define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) #define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) -#define pCAN_CLOCK ((uint16_t volatile *)CAN_CLOCK) /* Bit Timing Configuration register 0 */ #define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) #define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) -#define pCAN_TIMING ((uint16_t volatile *)CAN_TIMING) /* Bit Timing Configuration register 1 */ #define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) #define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) -#define pCAN_DEBUG ((uint16_t volatile *)CAN_DEBUG) /* Config register */ #define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) #define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) -#define pCAN_STATUS ((uint16_t volatile *)CAN_STATUS) /* Global Status Register */ #define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) #define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) -#define pCAN_CEC ((uint16_t volatile *)CAN_CEC) /* Error Counter Register */ #define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) #define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) -#define pCAN_GIS ((uint16_t volatile *)CAN_GIS) /* Global Interrupt Status Register */ #define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) #define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) -#define pCAN_GIM ((uint16_t volatile *)CAN_GIM) /* Global Interrupt Mask Register */ #define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) #define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) -#define pCAN_GIF ((uint16_t volatile *)CAN_GIF) /* Global Interrupt Flag Register */ #define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) #define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) -#define pCAN_CONTROL ((uint16_t volatile *)CAN_CONTROL) /* Master Control Register */ #define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) #define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) -#define pCAN_INTR ((uint16_t volatile *)CAN_INTR) /* Interrupt Pending Register */ #define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) #define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) -#define pCAN_VERSION ((uint16_t volatile *)CAN_VERSION) /* Version Code Register */ #define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) #define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) -#define pCAN_MBTD ((uint16_t volatile *)CAN_MBTD) /* Mailbox Temporary Disable Feature */ #define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) #define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) -#define pCAN_EWR ((uint16_t volatile *)CAN_EWR) /* Programmable Warning Level */ #define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) #define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) -#define pCAN_ESR ((uint16_t volatile *)CAN_ESR) /* Error Status Register */ #define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) #define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) -#define pCAN_UCREG ((uint16_t volatile *)CAN_UCREG) /* Universal Counter Register/Capture Register */ #define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) #define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) -#define pCAN_UCCNT ((uint16_t volatile *)CAN_UCCNT) /* Universal Counter */ #define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) #define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) -#define pCAN_UCRC ((uint16_t volatile *)CAN_UCRC) /* Universal Counter Force Reload Register */ #define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) #define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) -#define pCAN_UCCNF ((uint16_t volatile *)CAN_UCCNF) /* Universal Counter Configuration Register */ #define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) #define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) -#define pCAN_VERSION2 ((uint16_t volatile *)CAN_VERSION2) /* Version Code Register 2 */ #define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) #define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) -#define pCAN_AM00L ((uint16_t volatile *)CAN_AM00L) /* Mailbox 0 Low Acceptance Mask */ #define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) #define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) -#define pCAN_AM00H ((uint16_t volatile *)CAN_AM00H) /* Mailbox 0 High Acceptance Mask */ #define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) #define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) -#define pCAN_AM01L ((uint16_t volatile *)CAN_AM01L) /* Mailbox 1 Low Acceptance Mask */ #define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) #define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) -#define pCAN_AM01H ((uint16_t volatile *)CAN_AM01H) /* Mailbox 1 High Acceptance Mask */ #define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) #define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) -#define pCAN_AM02L ((uint16_t volatile *)CAN_AM02L) /* Mailbox 2 Low Acceptance Mask */ #define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) #define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) -#define pCAN_AM02H ((uint16_t volatile *)CAN_AM02H) /* Mailbox 2 High Acceptance Mask */ #define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) #define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) -#define pCAN_AM03L ((uint16_t volatile *)CAN_AM03L) /* Mailbox 3 Low Acceptance Mask */ #define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) #define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) -#define pCAN_AM03H ((uint16_t volatile *)CAN_AM03H) /* Mailbox 3 High Acceptance Mask */ #define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) #define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) -#define pCAN_AM04L ((uint16_t volatile *)CAN_AM04L) /* Mailbox 4 Low Acceptance Mask */ #define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) #define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) -#define pCAN_AM04H ((uint16_t volatile *)CAN_AM04H) /* Mailbox 4 High Acceptance Mask */ #define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) #define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) -#define pCAN_AM05L ((uint16_t volatile *)CAN_AM05L) /* Mailbox 5 Low Acceptance Mask */ #define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) #define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) -#define pCAN_AM05H ((uint16_t volatile *)CAN_AM05H) /* Mailbox 5 High Acceptance Mask */ #define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) #define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) -#define pCAN_AM06L ((uint16_t volatile *)CAN_AM06L) /* Mailbox 6 Low Acceptance Mask */ #define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) #define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) -#define pCAN_AM06H ((uint16_t volatile *)CAN_AM06H) /* Mailbox 6 High Acceptance Mask */ #define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) #define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) -#define pCAN_AM07L ((uint16_t volatile *)CAN_AM07L) /* Mailbox 7 Low Acceptance Mask */ #define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) #define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) -#define pCAN_AM07H ((uint16_t volatile *)CAN_AM07H) /* Mailbox 7 High Acceptance Mask */ #define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) #define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) -#define pCAN_AM08L ((uint16_t volatile *)CAN_AM08L) /* Mailbox 8 Low Acceptance Mask */ #define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) #define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) -#define pCAN_AM08H ((uint16_t volatile *)CAN_AM08H) /* Mailbox 8 High Acceptance Mask */ #define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) #define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) -#define pCAN_AM09L ((uint16_t volatile *)CAN_AM09L) /* Mailbox 9 Low Acceptance Mask */ #define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) #define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) -#define pCAN_AM09H ((uint16_t volatile *)CAN_AM09H) /* Mailbox 9 High Acceptance Mask */ #define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) #define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) -#define pCAN_AM10L ((uint16_t volatile *)CAN_AM10L) /* Mailbox 10 Low Acceptance Mask */ #define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) #define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) -#define pCAN_AM10H ((uint16_t volatile *)CAN_AM10H) /* Mailbox 10 High Acceptance Mask */ #define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) #define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) -#define pCAN_AM11L ((uint16_t volatile *)CAN_AM11L) /* Mailbox 11 Low Acceptance Mask */ #define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) #define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) -#define pCAN_AM11H ((uint16_t volatile *)CAN_AM11H) /* Mailbox 11 High Acceptance Mask */ #define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) #define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) -#define pCAN_AM12L ((uint16_t volatile *)CAN_AM12L) /* Mailbox 12 Low Acceptance Mask */ #define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) #define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) -#define pCAN_AM12H ((uint16_t volatile *)CAN_AM12H) /* Mailbox 12 High Acceptance Mask */ #define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) #define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) -#define pCAN_AM13L ((uint16_t volatile *)CAN_AM13L) /* Mailbox 13 Low Acceptance Mask */ #define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) #define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) -#define pCAN_AM13H ((uint16_t volatile *)CAN_AM13H) /* Mailbox 13 High Acceptance Mask */ #define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) #define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) -#define pCAN_AM14L ((uint16_t volatile *)CAN_AM14L) /* Mailbox 14 Low Acceptance Mask */ #define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) #define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) -#define pCAN_AM14H ((uint16_t volatile *)CAN_AM14H) /* Mailbox 14 High Acceptance Mask */ #define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) #define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) -#define pCAN_AM15L ((uint16_t volatile *)CAN_AM15L) /* Mailbox 15 Low Acceptance Mask */ #define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) #define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) -#define pCAN_AM15H ((uint16_t volatile *)CAN_AM15H) /* Mailbox 15 High Acceptance Mask */ #define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) #define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) -#define pCAN_AM16L ((uint16_t volatile *)CAN_AM16L) /* Mailbox 16 Low Acceptance Mask */ #define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) #define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) -#define pCAN_AM16H ((uint16_t volatile *)CAN_AM16H) /* Mailbox 16 High Acceptance Mask */ #define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) #define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) -#define pCAN_AM17L ((uint16_t volatile *)CAN_AM17L) /* Mailbox 17 Low Acceptance Mask */ #define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) #define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) -#define pCAN_AM17H ((uint16_t volatile *)CAN_AM17H) /* Mailbox 17 High Acceptance Mask */ #define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) #define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) -#define pCAN_AM18L ((uint16_t volatile *)CAN_AM18L) /* Mailbox 18 Low Acceptance Mask */ #define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) #define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) -#define pCAN_AM18H ((uint16_t volatile *)CAN_AM18H) /* Mailbox 18 High Acceptance Mask */ #define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) #define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) -#define pCAN_AM19L ((uint16_t volatile *)CAN_AM19L) /* Mailbox 19 Low Acceptance Mask */ #define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) #define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) -#define pCAN_AM19H ((uint16_t volatile *)CAN_AM19H) /* Mailbox 19 High Acceptance Mask */ #define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) #define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) -#define pCAN_AM20L ((uint16_t volatile *)CAN_AM20L) /* Mailbox 20 Low Acceptance Mask */ #define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) #define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) -#define pCAN_AM20H ((uint16_t volatile *)CAN_AM20H) /* Mailbox 20 High Acceptance Mask */ #define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) #define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) -#define pCAN_AM21L ((uint16_t volatile *)CAN_AM21L) /* Mailbox 21 Low Acceptance Mask */ #define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) #define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) -#define pCAN_AM21H ((uint16_t volatile *)CAN_AM21H) /* Mailbox 21 High Acceptance Mask */ #define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) #define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) -#define pCAN_AM22L ((uint16_t volatile *)CAN_AM22L) /* Mailbox 22 Low Acceptance Mask */ #define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) #define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) -#define pCAN_AM22H ((uint16_t volatile *)CAN_AM22H) /* Mailbox 22 High Acceptance Mask */ #define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) #define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) -#define pCAN_AM23L ((uint16_t volatile *)CAN_AM23L) /* Mailbox 23 Low Acceptance Mask */ #define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) #define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) -#define pCAN_AM23H ((uint16_t volatile *)CAN_AM23H) /* Mailbox 23 High Acceptance Mask */ #define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) #define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) -#define pCAN_AM24L ((uint16_t volatile *)CAN_AM24L) /* Mailbox 24 Low Acceptance Mask */ #define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) #define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) -#define pCAN_AM24H ((uint16_t volatile *)CAN_AM24H) /* Mailbox 24 High Acceptance Mask */ #define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) #define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) -#define pCAN_AM25L ((uint16_t volatile *)CAN_AM25L) /* Mailbox 25 Low Acceptance Mask */ #define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) #define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) -#define pCAN_AM25H ((uint16_t volatile *)CAN_AM25H) /* Mailbox 25 High Acceptance Mask */ #define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) #define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) -#define pCAN_AM26L ((uint16_t volatile *)CAN_AM26L) /* Mailbox 26 Low Acceptance Mask */ #define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) #define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) -#define pCAN_AM26H ((uint16_t volatile *)CAN_AM26H) /* Mailbox 26 High Acceptance Mask */ #define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) #define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) -#define pCAN_AM27L ((uint16_t volatile *)CAN_AM27L) /* Mailbox 27 Low Acceptance Mask */ #define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) #define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) -#define pCAN_AM27H ((uint16_t volatile *)CAN_AM27H) /* Mailbox 27 High Acceptance Mask */ #define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) #define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) -#define pCAN_AM28L ((uint16_t volatile *)CAN_AM28L) /* Mailbox 28 Low Acceptance Mask */ #define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) #define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) -#define pCAN_AM28H ((uint16_t volatile *)CAN_AM28H) /* Mailbox 28 High Acceptance Mask */ #define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) #define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) -#define pCAN_AM29L ((uint16_t volatile *)CAN_AM29L) /* Mailbox 29 Low Acceptance Mask */ #define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) #define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) -#define pCAN_AM29H ((uint16_t volatile *)CAN_AM29H) /* Mailbox 29 High Acceptance Mask */ #define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) #define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) -#define pCAN_AM30L ((uint16_t volatile *)CAN_AM30L) /* Mailbox 30 Low Acceptance Mask */ #define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) #define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) -#define pCAN_AM30H ((uint16_t volatile *)CAN_AM30H) /* Mailbox 30 High Acceptance Mask */ #define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) #define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) -#define pCAN_AM31L ((uint16_t volatile *)CAN_AM31L) /* Mailbox 31 Low Acceptance Mask */ #define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) #define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) -#define pCAN_AM31H ((uint16_t volatile *)CAN_AM31H) /* Mailbox 31 High Acceptance Mask */ #define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) #define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) -#define pCAN_MB00_DATA0 ((uint16_t volatile *)CAN_MB00_DATA0) /* Mailbox 0 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) #define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) -#define pCAN_MB00_DATA1 ((uint16_t volatile *)CAN_MB00_DATA1) /* Mailbox 0 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) #define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) -#define pCAN_MB00_DATA2 ((uint16_t volatile *)CAN_MB00_DATA2) /* Mailbox 0 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) #define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) -#define pCAN_MB00_DATA3 ((uint16_t volatile *)CAN_MB00_DATA3) /* Mailbox 0 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) #define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) -#define pCAN_MB00_LENGTH ((uint16_t volatile *)CAN_MB00_LENGTH) /* Mailbox 0 Data Length Code Register */ #define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) #define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) -#define pCAN_MB00_TIMESTAMP ((uint16_t volatile *)CAN_MB00_TIMESTAMP) /* Mailbox 0 Time Stamp Value Register */ #define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) #define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) -#define pCAN_MB00_ID0 ((uint16_t volatile *)CAN_MB00_ID0) /* Mailbox 0 Identifier Low Register */ #define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) #define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) -#define pCAN_MB00_ID1 ((uint16_t volatile *)CAN_MB00_ID1) /* Mailbox 0 Identifier High Register */ #define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) #define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) -#define pCAN_MB01_DATA0 ((uint16_t volatile *)CAN_MB01_DATA0) /* Mailbox 1 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) #define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) -#define pCAN_MB01_DATA1 ((uint16_t volatile *)CAN_MB01_DATA1) /* Mailbox 1 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) #define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) -#define pCAN_MB01_DATA2 ((uint16_t volatile *)CAN_MB01_DATA2) /* Mailbox 1 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) #define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) -#define pCAN_MB01_DATA3 ((uint16_t volatile *)CAN_MB01_DATA3) /* Mailbox 1 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) #define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) -#define pCAN_MB01_LENGTH ((uint16_t volatile *)CAN_MB01_LENGTH) /* Mailbox 1 Data Length Code Register */ #define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) #define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) -#define pCAN_MB01_TIMESTAMP ((uint16_t volatile *)CAN_MB01_TIMESTAMP) /* Mailbox 1 Time Stamp Value Register */ #define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) #define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) -#define pCAN_MB01_ID0 ((uint16_t volatile *)CAN_MB01_ID0) /* Mailbox 1 Identifier Low Register */ #define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) #define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) -#define pCAN_MB01_ID1 ((uint16_t volatile *)CAN_MB01_ID1) /* Mailbox 1 Identifier High Register */ #define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) #define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) -#define pCAN_MB02_DATA0 ((uint16_t volatile *)CAN_MB02_DATA0) /* Mailbox 2 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) #define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) -#define pCAN_MB02_DATA1 ((uint16_t volatile *)CAN_MB02_DATA1) /* Mailbox 2 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) #define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) -#define pCAN_MB02_DATA2 ((uint16_t volatile *)CAN_MB02_DATA2) /* Mailbox 2 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) #define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) -#define pCAN_MB02_DATA3 ((uint16_t volatile *)CAN_MB02_DATA3) /* Mailbox 2 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) #define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) -#define pCAN_MB02_LENGTH ((uint16_t volatile *)CAN_MB02_LENGTH) /* Mailbox 2 Data Length Code Register */ #define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) #define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) -#define pCAN_MB02_TIMESTAMP ((uint16_t volatile *)CAN_MB02_TIMESTAMP) /* Mailbox 2 Time Stamp Value Register */ #define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) #define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) -#define pCAN_MB02_ID0 ((uint16_t volatile *)CAN_MB02_ID0) /* Mailbox 2 Identifier Low Register */ #define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) #define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) -#define pCAN_MB02_ID1 ((uint16_t volatile *)CAN_MB02_ID1) /* Mailbox 2 Identifier High Register */ #define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) #define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) -#define pCAN_MB03_DATA0 ((uint16_t volatile *)CAN_MB03_DATA0) /* Mailbox 3 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) #define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) -#define pCAN_MB03_DATA1 ((uint16_t volatile *)CAN_MB03_DATA1) /* Mailbox 3 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) #define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) -#define pCAN_MB03_DATA2 ((uint16_t volatile *)CAN_MB03_DATA2) /* Mailbox 3 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) #define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) -#define pCAN_MB03_DATA3 ((uint16_t volatile *)CAN_MB03_DATA3) /* Mailbox 3 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) #define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) -#define pCAN_MB03_LENGTH ((uint16_t volatile *)CAN_MB03_LENGTH) /* Mailbox 3 Data Length Code Register */ #define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) #define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) -#define pCAN_MB03_TIMESTAMP ((uint16_t volatile *)CAN_MB03_TIMESTAMP) /* Mailbox 3 Time Stamp Value Register */ #define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) #define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) -#define pCAN_MB03_ID0 ((uint16_t volatile *)CAN_MB03_ID0) /* Mailbox 3 Identifier Low Register */ #define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) #define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) -#define pCAN_MB03_ID1 ((uint16_t volatile *)CAN_MB03_ID1) /* Mailbox 3 Identifier High Register */ #define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) #define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) -#define pCAN_MB04_DATA0 ((uint16_t volatile *)CAN_MB04_DATA0) /* Mailbox 4 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) #define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) -#define pCAN_MB04_DATA1 ((uint16_t volatile *)CAN_MB04_DATA1) /* Mailbox 4 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) #define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) -#define pCAN_MB04_DATA2 ((uint16_t volatile *)CAN_MB04_DATA2) /* Mailbox 4 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) #define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) -#define pCAN_MB04_DATA3 ((uint16_t volatile *)CAN_MB04_DATA3) /* Mailbox 4 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) #define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) -#define pCAN_MB04_LENGTH ((uint16_t volatile *)CAN_MB04_LENGTH) /* Mailbox 4 Data Length Code Register */ #define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) #define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) -#define pCAN_MB04_TIMESTAMP ((uint16_t volatile *)CAN_MB04_TIMESTAMP) /* Mailbox 4 Time Stamp Value Register */ #define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) #define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) -#define pCAN_MB04_ID0 ((uint16_t volatile *)CAN_MB04_ID0) /* Mailbox 4 Identifier Low Register */ #define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) #define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) -#define pCAN_MB04_ID1 ((uint16_t volatile *)CAN_MB04_ID1) /* Mailbox 4 Identifier High Register */ #define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) #define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) -#define pCAN_MB05_DATA0 ((uint16_t volatile *)CAN_MB05_DATA0) /* Mailbox 5 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) #define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) -#define pCAN_MB05_DATA1 ((uint16_t volatile *)CAN_MB05_DATA1) /* Mailbox 5 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) #define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) -#define pCAN_MB05_DATA2 ((uint16_t volatile *)CAN_MB05_DATA2) /* Mailbox 5 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) #define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) -#define pCAN_MB05_DATA3 ((uint16_t volatile *)CAN_MB05_DATA3) /* Mailbox 5 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) #define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) -#define pCAN_MB05_LENGTH ((uint16_t volatile *)CAN_MB05_LENGTH) /* Mailbox 5 Data Length Code Register */ #define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) #define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) -#define pCAN_MB05_TIMESTAMP ((uint16_t volatile *)CAN_MB05_TIMESTAMP) /* Mailbox 5 Time Stamp Value Register */ #define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) #define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) -#define pCAN_MB05_ID0 ((uint16_t volatile *)CAN_MB05_ID0) /* Mailbox 5 Identifier Low Register */ #define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) #define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) -#define pCAN_MB05_ID1 ((uint16_t volatile *)CAN_MB05_ID1) /* Mailbox 5 Identifier High Register */ #define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) #define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) -#define pCAN_MB06_DATA0 ((uint16_t volatile *)CAN_MB06_DATA0) /* Mailbox 6 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) #define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) -#define pCAN_MB06_DATA1 ((uint16_t volatile *)CAN_MB06_DATA1) /* Mailbox 6 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) #define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) -#define pCAN_MB06_DATA2 ((uint16_t volatile *)CAN_MB06_DATA2) /* Mailbox 6 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) #define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) -#define pCAN_MB06_DATA3 ((uint16_t volatile *)CAN_MB06_DATA3) /* Mailbox 6 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) #define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) -#define pCAN_MB06_LENGTH ((uint16_t volatile *)CAN_MB06_LENGTH) /* Mailbox 6 Data Length Code Register */ #define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) #define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) -#define pCAN_MB06_TIMESTAMP ((uint16_t volatile *)CAN_MB06_TIMESTAMP) /* Mailbox 6 Time Stamp Value Register */ #define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) #define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) -#define pCAN_MB06_ID0 ((uint16_t volatile *)CAN_MB06_ID0) /* Mailbox 6 Identifier Low Register */ #define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) #define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) -#define pCAN_MB06_ID1 ((uint16_t volatile *)CAN_MB06_ID1) /* Mailbox 6 Identifier High Register */ #define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) #define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) -#define pCAN_MB07_DATA0 ((uint16_t volatile *)CAN_MB07_DATA0) /* Mailbox 7 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) #define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) -#define pCAN_MB07_DATA1 ((uint16_t volatile *)CAN_MB07_DATA1) /* Mailbox 7 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) #define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) -#define pCAN_MB07_DATA2 ((uint16_t volatile *)CAN_MB07_DATA2) /* Mailbox 7 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) #define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) -#define pCAN_MB07_DATA3 ((uint16_t volatile *)CAN_MB07_DATA3) /* Mailbox 7 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) #define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) -#define pCAN_MB07_LENGTH ((uint16_t volatile *)CAN_MB07_LENGTH) /* Mailbox 7 Data Length Code Register */ #define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) #define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) -#define pCAN_MB07_TIMESTAMP ((uint16_t volatile *)CAN_MB07_TIMESTAMP) /* Mailbox 7 Time Stamp Value Register */ #define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) #define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) -#define pCAN_MB07_ID0 ((uint16_t volatile *)CAN_MB07_ID0) /* Mailbox 7 Identifier Low Register */ #define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) #define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) -#define pCAN_MB07_ID1 ((uint16_t volatile *)CAN_MB07_ID1) /* Mailbox 7 Identifier High Register */ #define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) #define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) -#define pCAN_MB08_DATA0 ((uint16_t volatile *)CAN_MB08_DATA0) /* Mailbox 8 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) #define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) -#define pCAN_MB08_DATA1 ((uint16_t volatile *)CAN_MB08_DATA1) /* Mailbox 8 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) #define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) -#define pCAN_MB08_DATA2 ((uint16_t volatile *)CAN_MB08_DATA2) /* Mailbox 8 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) #define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) -#define pCAN_MB08_DATA3 ((uint16_t volatile *)CAN_MB08_DATA3) /* Mailbox 8 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) #define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) -#define pCAN_MB08_LENGTH ((uint16_t volatile *)CAN_MB08_LENGTH) /* Mailbox 8 Data Length Code Register */ #define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) #define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) -#define pCAN_MB08_TIMESTAMP ((uint16_t volatile *)CAN_MB08_TIMESTAMP) /* Mailbox 8 Time Stamp Value Register */ #define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) #define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) -#define pCAN_MB08_ID0 ((uint16_t volatile *)CAN_MB08_ID0) /* Mailbox 8 Identifier Low Register */ #define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) #define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) -#define pCAN_MB08_ID1 ((uint16_t volatile *)CAN_MB08_ID1) /* Mailbox 8 Identifier High Register */ #define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) #define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) -#define pCAN_MB09_DATA0 ((uint16_t volatile *)CAN_MB09_DATA0) /* Mailbox 9 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) #define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) -#define pCAN_MB09_DATA1 ((uint16_t volatile *)CAN_MB09_DATA1) /* Mailbox 9 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) #define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) -#define pCAN_MB09_DATA2 ((uint16_t volatile *)CAN_MB09_DATA2) /* Mailbox 9 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) #define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) -#define pCAN_MB09_DATA3 ((uint16_t volatile *)CAN_MB09_DATA3) /* Mailbox 9 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) #define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) -#define pCAN_MB09_LENGTH ((uint16_t volatile *)CAN_MB09_LENGTH) /* Mailbox 9 Data Length Code Register */ #define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) #define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) -#define pCAN_MB09_TIMESTAMP ((uint16_t volatile *)CAN_MB09_TIMESTAMP) /* Mailbox 9 Time Stamp Value Register */ #define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) #define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) -#define pCAN_MB09_ID0 ((uint16_t volatile *)CAN_MB09_ID0) /* Mailbox 9 Identifier Low Register */ #define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) #define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) -#define pCAN_MB09_ID1 ((uint16_t volatile *)CAN_MB09_ID1) /* Mailbox 9 Identifier High Register */ #define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) #define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) -#define pCAN_MB10_DATA0 ((uint16_t volatile *)CAN_MB10_DATA0) /* Mailbox 10 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) #define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) -#define pCAN_MB10_DATA1 ((uint16_t volatile *)CAN_MB10_DATA1) /* Mailbox 10 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) #define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) -#define pCAN_MB10_DATA2 ((uint16_t volatile *)CAN_MB10_DATA2) /* Mailbox 10 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) #define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) -#define pCAN_MB10_DATA3 ((uint16_t volatile *)CAN_MB10_DATA3) /* Mailbox 10 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) #define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) -#define pCAN_MB10_LENGTH ((uint16_t volatile *)CAN_MB10_LENGTH) /* Mailbox 10 Data Length Code Register */ #define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) #define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) -#define pCAN_MB10_TIMESTAMP ((uint16_t volatile *)CAN_MB10_TIMESTAMP) /* Mailbox 10 Time Stamp Value Register */ #define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) #define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) -#define pCAN_MB10_ID0 ((uint16_t volatile *)CAN_MB10_ID0) /* Mailbox 10 Identifier Low Register */ #define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) #define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) -#define pCAN_MB10_ID1 ((uint16_t volatile *)CAN_MB10_ID1) /* Mailbox 10 Identifier High Register */ #define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) #define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) -#define pCAN_MB11_DATA0 ((uint16_t volatile *)CAN_MB11_DATA0) /* Mailbox 11 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) #define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) -#define pCAN_MB11_DATA1 ((uint16_t volatile *)CAN_MB11_DATA1) /* Mailbox 11 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) #define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) -#define pCAN_MB11_DATA2 ((uint16_t volatile *)CAN_MB11_DATA2) /* Mailbox 11 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) #define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) -#define pCAN_MB11_DATA3 ((uint16_t volatile *)CAN_MB11_DATA3) /* Mailbox 11 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) #define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) -#define pCAN_MB11_LENGTH ((uint16_t volatile *)CAN_MB11_LENGTH) /* Mailbox 11 Data Length Code Register */ #define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) #define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) -#define pCAN_MB11_TIMESTAMP ((uint16_t volatile *)CAN_MB11_TIMESTAMP) /* Mailbox 11 Time Stamp Value Register */ #define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) #define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) -#define pCAN_MB11_ID0 ((uint16_t volatile *)CAN_MB11_ID0) /* Mailbox 11 Identifier Low Register */ #define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) #define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) -#define pCAN_MB11_ID1 ((uint16_t volatile *)CAN_MB11_ID1) /* Mailbox 11 Identifier High Register */ #define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) #define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) -#define pCAN_MB12_DATA0 ((uint16_t volatile *)CAN_MB12_DATA0) /* Mailbox 12 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) #define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) -#define pCAN_MB12_DATA1 ((uint16_t volatile *)CAN_MB12_DATA1) /* Mailbox 12 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) #define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) -#define pCAN_MB12_DATA2 ((uint16_t volatile *)CAN_MB12_DATA2) /* Mailbox 12 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) #define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) -#define pCAN_MB12_DATA3 ((uint16_t volatile *)CAN_MB12_DATA3) /* Mailbox 12 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) #define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) -#define pCAN_MB12_LENGTH ((uint16_t volatile *)CAN_MB12_LENGTH) /* Mailbox 12 Data Length Code Register */ #define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) #define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) -#define pCAN_MB12_TIMESTAMP ((uint16_t volatile *)CAN_MB12_TIMESTAMP) /* Mailbox 12 Time Stamp Value Register */ #define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) #define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) -#define pCAN_MB12_ID0 ((uint16_t volatile *)CAN_MB12_ID0) /* Mailbox 12 Identifier Low Register */ #define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) #define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) -#define pCAN_MB12_ID1 ((uint16_t volatile *)CAN_MB12_ID1) /* Mailbox 12 Identifier High Register */ #define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) #define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) -#define pCAN_MB13_DATA0 ((uint16_t volatile *)CAN_MB13_DATA0) /* Mailbox 13 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) #define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) -#define pCAN_MB13_DATA1 ((uint16_t volatile *)CAN_MB13_DATA1) /* Mailbox 13 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) #define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) -#define pCAN_MB13_DATA2 ((uint16_t volatile *)CAN_MB13_DATA2) /* Mailbox 13 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) #define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) -#define pCAN_MB13_DATA3 ((uint16_t volatile *)CAN_MB13_DATA3) /* Mailbox 13 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) #define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) -#define pCAN_MB13_LENGTH ((uint16_t volatile *)CAN_MB13_LENGTH) /* Mailbox 13 Data Length Code Register */ #define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) #define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) -#define pCAN_MB13_TIMESTAMP ((uint16_t volatile *)CAN_MB13_TIMESTAMP) /* Mailbox 13 Time Stamp Value Register */ #define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) #define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) -#define pCAN_MB13_ID0 ((uint16_t volatile *)CAN_MB13_ID0) /* Mailbox 13 Identifier Low Register */ #define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) #define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) -#define pCAN_MB13_ID1 ((uint16_t volatile *)CAN_MB13_ID1) /* Mailbox 13 Identifier High Register */ #define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) #define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) -#define pCAN_MB14_DATA0 ((uint16_t volatile *)CAN_MB14_DATA0) /* Mailbox 14 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) #define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) -#define pCAN_MB14_DATA1 ((uint16_t volatile *)CAN_MB14_DATA1) /* Mailbox 14 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) #define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) -#define pCAN_MB14_DATA2 ((uint16_t volatile *)CAN_MB14_DATA2) /* Mailbox 14 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) #define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) -#define pCAN_MB14_DATA3 ((uint16_t volatile *)CAN_MB14_DATA3) /* Mailbox 14 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) #define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) -#define pCAN_MB14_LENGTH ((uint16_t volatile *)CAN_MB14_LENGTH) /* Mailbox 14 Data Length Code Register */ #define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) #define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) -#define pCAN_MB14_TIMESTAMP ((uint16_t volatile *)CAN_MB14_TIMESTAMP) /* Mailbox 14 Time Stamp Value Register */ #define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) #define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) -#define pCAN_MB14_ID0 ((uint16_t volatile *)CAN_MB14_ID0) /* Mailbox 14 Identifier Low Register */ #define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) #define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) -#define pCAN_MB14_ID1 ((uint16_t volatile *)CAN_MB14_ID1) /* Mailbox 14 Identifier High Register */ #define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) #define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) -#define pCAN_MB15_DATA0 ((uint16_t volatile *)CAN_MB15_DATA0) /* Mailbox 15 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) #define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) -#define pCAN_MB15_DATA1 ((uint16_t volatile *)CAN_MB15_DATA1) /* Mailbox 15 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) #define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) -#define pCAN_MB15_DATA2 ((uint16_t volatile *)CAN_MB15_DATA2) /* Mailbox 15 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) #define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) -#define pCAN_MB15_DATA3 ((uint16_t volatile *)CAN_MB15_DATA3) /* Mailbox 15 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) #define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) -#define pCAN_MB15_LENGTH ((uint16_t volatile *)CAN_MB15_LENGTH) /* Mailbox 15 Data Length Code Register */ #define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) #define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) -#define pCAN_MB15_TIMESTAMP ((uint16_t volatile *)CAN_MB15_TIMESTAMP) /* Mailbox 15 Time Stamp Value Register */ #define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) #define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) -#define pCAN_MB15_ID0 ((uint16_t volatile *)CAN_MB15_ID0) /* Mailbox 15 Identifier Low Register */ #define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) #define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) -#define pCAN_MB15_ID1 ((uint16_t volatile *)CAN_MB15_ID1) /* Mailbox 15 Identifier High Register */ #define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) #define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) -#define pCAN_MB16_DATA0 ((uint16_t volatile *)CAN_MB16_DATA0) /* Mailbox 16 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) #define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) -#define pCAN_MB16_DATA1 ((uint16_t volatile *)CAN_MB16_DATA1) /* Mailbox 16 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) #define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) -#define pCAN_MB16_DATA2 ((uint16_t volatile *)CAN_MB16_DATA2) /* Mailbox 16 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) #define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) -#define pCAN_MB16_DATA3 ((uint16_t volatile *)CAN_MB16_DATA3) /* Mailbox 16 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) #define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) -#define pCAN_MB16_LENGTH ((uint16_t volatile *)CAN_MB16_LENGTH) /* Mailbox 16 Data Length Code Register */ #define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) #define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) -#define pCAN_MB16_TIMESTAMP ((uint16_t volatile *)CAN_MB16_TIMESTAMP) /* Mailbox 16 Time Stamp Value Register */ #define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) #define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) -#define pCAN_MB16_ID0 ((uint16_t volatile *)CAN_MB16_ID0) /* Mailbox 16 Identifier Low Register */ #define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) #define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) -#define pCAN_MB16_ID1 ((uint16_t volatile *)CAN_MB16_ID1) /* Mailbox 16 Identifier High Register */ #define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) #define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) -#define pCAN_MB17_DATA0 ((uint16_t volatile *)CAN_MB17_DATA0) /* Mailbox 17 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) #define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) -#define pCAN_MB17_DATA1 ((uint16_t volatile *)CAN_MB17_DATA1) /* Mailbox 17 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) #define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) -#define pCAN_MB17_DATA2 ((uint16_t volatile *)CAN_MB17_DATA2) /* Mailbox 17 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) #define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) -#define pCAN_MB17_DATA3 ((uint16_t volatile *)CAN_MB17_DATA3) /* Mailbox 17 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) #define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) -#define pCAN_MB17_LENGTH ((uint16_t volatile *)CAN_MB17_LENGTH) /* Mailbox 17 Data Length Code Register */ #define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) #define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) -#define pCAN_MB17_TIMESTAMP ((uint16_t volatile *)CAN_MB17_TIMESTAMP) /* Mailbox 17 Time Stamp Value Register */ #define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) #define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) -#define pCAN_MB17_ID0 ((uint16_t volatile *)CAN_MB17_ID0) /* Mailbox 17 Identifier Low Register */ #define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) #define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) -#define pCAN_MB17_ID1 ((uint16_t volatile *)CAN_MB17_ID1) /* Mailbox 17 Identifier High Register */ #define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) #define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) -#define pCAN_MB18_DATA0 ((uint16_t volatile *)CAN_MB18_DATA0) /* Mailbox 18 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) #define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) -#define pCAN_MB18_DATA1 ((uint16_t volatile *)CAN_MB18_DATA1) /* Mailbox 18 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) #define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) -#define pCAN_MB18_DATA2 ((uint16_t volatile *)CAN_MB18_DATA2) /* Mailbox 18 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) #define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) -#define pCAN_MB18_DATA3 ((uint16_t volatile *)CAN_MB18_DATA3) /* Mailbox 18 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) #define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) -#define pCAN_MB18_LENGTH ((uint16_t volatile *)CAN_MB18_LENGTH) /* Mailbox 18 Data Length Code Register */ #define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) #define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) -#define pCAN_MB18_TIMESTAMP ((uint16_t volatile *)CAN_MB18_TIMESTAMP) /* Mailbox 18 Time Stamp Value Register */ #define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) #define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) -#define pCAN_MB18_ID0 ((uint16_t volatile *)CAN_MB18_ID0) /* Mailbox 18 Identifier Low Register */ #define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) #define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) -#define pCAN_MB18_ID1 ((uint16_t volatile *)CAN_MB18_ID1) /* Mailbox 18 Identifier High Register */ #define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) #define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) -#define pCAN_MB19_DATA0 ((uint16_t volatile *)CAN_MB19_DATA0) /* Mailbox 19 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) #define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) -#define pCAN_MB19_DATA1 ((uint16_t volatile *)CAN_MB19_DATA1) /* Mailbox 19 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) #define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) -#define pCAN_MB19_DATA2 ((uint16_t volatile *)CAN_MB19_DATA2) /* Mailbox 19 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) #define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) -#define pCAN_MB19_DATA3 ((uint16_t volatile *)CAN_MB19_DATA3) /* Mailbox 19 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) #define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) -#define pCAN_MB19_LENGTH ((uint16_t volatile *)CAN_MB19_LENGTH) /* Mailbox 19 Data Length Code Register */ #define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) #define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) -#define pCAN_MB19_TIMESTAMP ((uint16_t volatile *)CAN_MB19_TIMESTAMP) /* Mailbox 19 Time Stamp Value Register */ #define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) #define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) -#define pCAN_MB19_ID0 ((uint16_t volatile *)CAN_MB19_ID0) /* Mailbox 19 Identifier Low Register */ #define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) #define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) -#define pCAN_MB19_ID1 ((uint16_t volatile *)CAN_MB19_ID1) /* Mailbox 19 Identifier High Register */ #define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) #define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) -#define pCAN_MB20_DATA0 ((uint16_t volatile *)CAN_MB20_DATA0) /* Mailbox 20 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) #define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) -#define pCAN_MB20_DATA1 ((uint16_t volatile *)CAN_MB20_DATA1) /* Mailbox 20 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) #define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) -#define pCAN_MB20_DATA2 ((uint16_t volatile *)CAN_MB20_DATA2) /* Mailbox 20 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) #define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) -#define pCAN_MB20_DATA3 ((uint16_t volatile *)CAN_MB20_DATA3) /* Mailbox 20 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) #define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) -#define pCAN_MB20_LENGTH ((uint16_t volatile *)CAN_MB20_LENGTH) /* Mailbox 20 Data Length Code Register */ #define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) #define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) -#define pCAN_MB20_TIMESTAMP ((uint16_t volatile *)CAN_MB20_TIMESTAMP) /* Mailbox 20 Time Stamp Value Register */ #define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) #define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) -#define pCAN_MB20_ID0 ((uint16_t volatile *)CAN_MB20_ID0) /* Mailbox 20 Identifier Low Register */ #define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) #define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) -#define pCAN_MB20_ID1 ((uint16_t volatile *)CAN_MB20_ID1) /* Mailbox 20 Identifier High Register */ #define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) #define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) -#define pCAN_MB21_DATA0 ((uint16_t volatile *)CAN_MB21_DATA0) /* Mailbox 21 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) #define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) -#define pCAN_MB21_DATA1 ((uint16_t volatile *)CAN_MB21_DATA1) /* Mailbox 21 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) #define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) -#define pCAN_MB21_DATA2 ((uint16_t volatile *)CAN_MB21_DATA2) /* Mailbox 21 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) #define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) -#define pCAN_MB21_DATA3 ((uint16_t volatile *)CAN_MB21_DATA3) /* Mailbox 21 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) #define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) -#define pCAN_MB21_LENGTH ((uint16_t volatile *)CAN_MB21_LENGTH) /* Mailbox 21 Data Length Code Register */ #define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) #define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) -#define pCAN_MB21_TIMESTAMP ((uint16_t volatile *)CAN_MB21_TIMESTAMP) /* Mailbox 21 Time Stamp Value Register */ #define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) #define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) -#define pCAN_MB21_ID0 ((uint16_t volatile *)CAN_MB21_ID0) /* Mailbox 21 Identifier Low Register */ #define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) #define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) -#define pCAN_MB21_ID1 ((uint16_t volatile *)CAN_MB21_ID1) /* Mailbox 21 Identifier High Register */ #define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) #define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) -#define pCAN_MB22_DATA0 ((uint16_t volatile *)CAN_MB22_DATA0) /* Mailbox 22 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) #define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) -#define pCAN_MB22_DATA1 ((uint16_t volatile *)CAN_MB22_DATA1) /* Mailbox 22 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) #define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) -#define pCAN_MB22_DATA2 ((uint16_t volatile *)CAN_MB22_DATA2) /* Mailbox 22 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) #define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) -#define pCAN_MB22_DATA3 ((uint16_t volatile *)CAN_MB22_DATA3) /* Mailbox 22 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) #define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) -#define pCAN_MB22_LENGTH ((uint16_t volatile *)CAN_MB22_LENGTH) /* Mailbox 22 Data Length Code Register */ #define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) #define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) -#define pCAN_MB22_TIMESTAMP ((uint16_t volatile *)CAN_MB22_TIMESTAMP) /* Mailbox 22 Time Stamp Value Register */ #define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) #define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) -#define pCAN_MB22_ID0 ((uint16_t volatile *)CAN_MB22_ID0) /* Mailbox 22 Identifier Low Register */ #define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) #define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) -#define pCAN_MB22_ID1 ((uint16_t volatile *)CAN_MB22_ID1) /* Mailbox 22 Identifier High Register */ #define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) #define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) -#define pCAN_MB23_DATA0 ((uint16_t volatile *)CAN_MB23_DATA0) /* Mailbox 23 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) #define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) -#define pCAN_MB23_DATA1 ((uint16_t volatile *)CAN_MB23_DATA1) /* Mailbox 23 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) #define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) -#define pCAN_MB23_DATA2 ((uint16_t volatile *)CAN_MB23_DATA2) /* Mailbox 23 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) #define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) -#define pCAN_MB23_DATA3 ((uint16_t volatile *)CAN_MB23_DATA3) /* Mailbox 23 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) #define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) -#define pCAN_MB23_LENGTH ((uint16_t volatile *)CAN_MB23_LENGTH) /* Mailbox 23 Data Length Code Register */ #define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) #define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) -#define pCAN_MB23_TIMESTAMP ((uint16_t volatile *)CAN_MB23_TIMESTAMP) /* Mailbox 23 Time Stamp Value Register */ #define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) #define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) -#define pCAN_MB23_ID0 ((uint16_t volatile *)CAN_MB23_ID0) /* Mailbox 23 Identifier Low Register */ #define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) #define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) -#define pCAN_MB23_ID1 ((uint16_t volatile *)CAN_MB23_ID1) /* Mailbox 23 Identifier High Register */ #define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) #define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) -#define pCAN_MB24_DATA0 ((uint16_t volatile *)CAN_MB24_DATA0) /* Mailbox 24 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) #define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) -#define pCAN_MB24_DATA1 ((uint16_t volatile *)CAN_MB24_DATA1) /* Mailbox 24 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) #define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) -#define pCAN_MB24_DATA2 ((uint16_t volatile *)CAN_MB24_DATA2) /* Mailbox 24 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) #define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) -#define pCAN_MB24_DATA3 ((uint16_t volatile *)CAN_MB24_DATA3) /* Mailbox 24 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) #define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) -#define pCAN_MB24_LENGTH ((uint16_t volatile *)CAN_MB24_LENGTH) /* Mailbox 24 Data Length Code Register */ #define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) #define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) -#define pCAN_MB24_TIMESTAMP ((uint16_t volatile *)CAN_MB24_TIMESTAMP) /* Mailbox 24 Time Stamp Value Register */ #define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) #define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) -#define pCAN_MB24_ID0 ((uint16_t volatile *)CAN_MB24_ID0) /* Mailbox 24 Identifier Low Register */ #define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) #define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) -#define pCAN_MB24_ID1 ((uint16_t volatile *)CAN_MB24_ID1) /* Mailbox 24 Identifier High Register */ #define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) #define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) -#define pCAN_MB25_DATA0 ((uint16_t volatile *)CAN_MB25_DATA0) /* Mailbox 25 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) #define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) -#define pCAN_MB25_DATA1 ((uint16_t volatile *)CAN_MB25_DATA1) /* Mailbox 25 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) #define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) -#define pCAN_MB25_DATA2 ((uint16_t volatile *)CAN_MB25_DATA2) /* Mailbox 25 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) #define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) -#define pCAN_MB25_DATA3 ((uint16_t volatile *)CAN_MB25_DATA3) /* Mailbox 25 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) #define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) -#define pCAN_MB25_LENGTH ((uint16_t volatile *)CAN_MB25_LENGTH) /* Mailbox 25 Data Length Code Register */ #define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) #define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) -#define pCAN_MB25_TIMESTAMP ((uint16_t volatile *)CAN_MB25_TIMESTAMP) /* Mailbox 25 Time Stamp Value Register */ #define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) #define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) -#define pCAN_MB25_ID0 ((uint16_t volatile *)CAN_MB25_ID0) /* Mailbox 25 Identifier Low Register */ #define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) #define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) -#define pCAN_MB25_ID1 ((uint16_t volatile *)CAN_MB25_ID1) /* Mailbox 25 Identifier High Register */ #define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) #define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) -#define pCAN_MB26_DATA0 ((uint16_t volatile *)CAN_MB26_DATA0) /* Mailbox 26 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) #define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) -#define pCAN_MB26_DATA1 ((uint16_t volatile *)CAN_MB26_DATA1) /* Mailbox 26 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) #define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) -#define pCAN_MB26_DATA2 ((uint16_t volatile *)CAN_MB26_DATA2) /* Mailbox 26 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) #define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) -#define pCAN_MB26_DATA3 ((uint16_t volatile *)CAN_MB26_DATA3) /* Mailbox 26 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) #define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) -#define pCAN_MB26_LENGTH ((uint16_t volatile *)CAN_MB26_LENGTH) /* Mailbox 26 Data Length Code Register */ #define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) #define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) -#define pCAN_MB26_TIMESTAMP ((uint16_t volatile *)CAN_MB26_TIMESTAMP) /* Mailbox 26 Time Stamp Value Register */ #define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) #define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) -#define pCAN_MB26_ID0 ((uint16_t volatile *)CAN_MB26_ID0) /* Mailbox 26 Identifier Low Register */ #define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) #define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) -#define pCAN_MB26_ID1 ((uint16_t volatile *)CAN_MB26_ID1) /* Mailbox 26 Identifier High Register */ #define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) #define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) -#define pCAN_MB27_DATA0 ((uint16_t volatile *)CAN_MB27_DATA0) /* Mailbox 27 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) #define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) -#define pCAN_MB27_DATA1 ((uint16_t volatile *)CAN_MB27_DATA1) /* Mailbox 27 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) #define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) -#define pCAN_MB27_DATA2 ((uint16_t volatile *)CAN_MB27_DATA2) /* Mailbox 27 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) #define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) -#define pCAN_MB27_DATA3 ((uint16_t volatile *)CAN_MB27_DATA3) /* Mailbox 27 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) #define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) -#define pCAN_MB27_LENGTH ((uint16_t volatile *)CAN_MB27_LENGTH) /* Mailbox 27 Data Length Code Register */ #define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) #define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) -#define pCAN_MB27_TIMESTAMP ((uint16_t volatile *)CAN_MB27_TIMESTAMP) /* Mailbox 27 Time Stamp Value Register */ #define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) #define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) -#define pCAN_MB27_ID0 ((uint16_t volatile *)CAN_MB27_ID0) /* Mailbox 27 Identifier Low Register */ #define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) #define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) -#define pCAN_MB27_ID1 ((uint16_t volatile *)CAN_MB27_ID1) /* Mailbox 27 Identifier High Register */ #define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) #define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) -#define pCAN_MB28_DATA0 ((uint16_t volatile *)CAN_MB28_DATA0) /* Mailbox 28 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) #define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) -#define pCAN_MB28_DATA1 ((uint16_t volatile *)CAN_MB28_DATA1) /* Mailbox 28 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) #define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) -#define pCAN_MB28_DATA2 ((uint16_t volatile *)CAN_MB28_DATA2) /* Mailbox 28 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) #define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) -#define pCAN_MB28_DATA3 ((uint16_t volatile *)CAN_MB28_DATA3) /* Mailbox 28 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) #define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) -#define pCAN_MB28_LENGTH ((uint16_t volatile *)CAN_MB28_LENGTH) /* Mailbox 28 Data Length Code Register */ #define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) #define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) -#define pCAN_MB28_TIMESTAMP ((uint16_t volatile *)CAN_MB28_TIMESTAMP) /* Mailbox 28 Time Stamp Value Register */ #define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) #define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) -#define pCAN_MB28_ID0 ((uint16_t volatile *)CAN_MB28_ID0) /* Mailbox 28 Identifier Low Register */ #define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) #define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) -#define pCAN_MB28_ID1 ((uint16_t volatile *)CAN_MB28_ID1) /* Mailbox 28 Identifier High Register */ #define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) #define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) -#define pCAN_MB29_DATA0 ((uint16_t volatile *)CAN_MB29_DATA0) /* Mailbox 29 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) #define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) -#define pCAN_MB29_DATA1 ((uint16_t volatile *)CAN_MB29_DATA1) /* Mailbox 29 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) #define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) -#define pCAN_MB29_DATA2 ((uint16_t volatile *)CAN_MB29_DATA2) /* Mailbox 29 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) #define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) -#define pCAN_MB29_DATA3 ((uint16_t volatile *)CAN_MB29_DATA3) /* Mailbox 29 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) #define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) -#define pCAN_MB29_LENGTH ((uint16_t volatile *)CAN_MB29_LENGTH) /* Mailbox 29 Data Length Code Register */ #define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) #define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) -#define pCAN_MB29_TIMESTAMP ((uint16_t volatile *)CAN_MB29_TIMESTAMP) /* Mailbox 29 Time Stamp Value Register */ #define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) #define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) -#define pCAN_MB29_ID0 ((uint16_t volatile *)CAN_MB29_ID0) /* Mailbox 29 Identifier Low Register */ #define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) #define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) -#define pCAN_MB29_ID1 ((uint16_t volatile *)CAN_MB29_ID1) /* Mailbox 29 Identifier High Register */ #define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) #define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) -#define pCAN_MB30_DATA0 ((uint16_t volatile *)CAN_MB30_DATA0) /* Mailbox 30 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) #define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) -#define pCAN_MB30_DATA1 ((uint16_t volatile *)CAN_MB30_DATA1) /* Mailbox 30 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) #define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) -#define pCAN_MB30_DATA2 ((uint16_t volatile *)CAN_MB30_DATA2) /* Mailbox 30 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) #define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) -#define pCAN_MB30_DATA3 ((uint16_t volatile *)CAN_MB30_DATA3) /* Mailbox 30 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) #define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) -#define pCAN_MB30_LENGTH ((uint16_t volatile *)CAN_MB30_LENGTH) /* Mailbox 30 Data Length Code Register */ #define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) #define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) -#define pCAN_MB30_TIMESTAMP ((uint16_t volatile *)CAN_MB30_TIMESTAMP) /* Mailbox 30 Time Stamp Value Register */ #define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) #define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) -#define pCAN_MB30_ID0 ((uint16_t volatile *)CAN_MB30_ID0) /* Mailbox 30 Identifier Low Register */ #define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) #define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) -#define pCAN_MB30_ID1 ((uint16_t volatile *)CAN_MB30_ID1) /* Mailbox 30 Identifier High Register */ #define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) #define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) -#define pCAN_MB31_DATA0 ((uint16_t volatile *)CAN_MB31_DATA0) /* Mailbox 31 Data Word 0 [15:0] Register */ #define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) #define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) -#define pCAN_MB31_DATA1 ((uint16_t volatile *)CAN_MB31_DATA1) /* Mailbox 31 Data Word 1 [31:16] Register */ #define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) #define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) -#define pCAN_MB31_DATA2 ((uint16_t volatile *)CAN_MB31_DATA2) /* Mailbox 31 Data Word 2 [47:32] Register */ #define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) #define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) -#define pCAN_MB31_DATA3 ((uint16_t volatile *)CAN_MB31_DATA3) /* Mailbox 31 Data Word 3 [63:48] Register */ #define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) #define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) -#define pCAN_MB31_LENGTH ((uint16_t volatile *)CAN_MB31_LENGTH) /* Mailbox 31 Data Length Code Register */ #define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) #define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) -#define pCAN_MB31_TIMESTAMP ((uint16_t volatile *)CAN_MB31_TIMESTAMP) /* Mailbox 31 Time Stamp Value Register */ #define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) #define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) -#define pCAN_MB31_ID0 ((uint16_t volatile *)CAN_MB31_ID0) /* Mailbox 31 Identifier Low Register */ #define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) #define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) -#define pCAN_MB31_ID1 ((uint16_t volatile *)CAN_MB31_ID1) /* Mailbox 31 Identifier High Register */ #define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) #define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Port F Function Enable Register (Alternate/Flag*) */ #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Port G Function Enable Register (Alternate/Flag*) */ #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Port H Function Enable Register (Alternate/Flag*) */ #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORT_MUX ((uint16_t volatile *)PORT_MUX) /* Port Multiplexer Control Register */ #define bfin_read_PORT_MUX() bfin_read16(PORT_MUX) #define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* HMDMA0 Initial Edge Count Register */ #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* HMDMA0 Initial Block Count Register */ #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* HMDMA0 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* HMDMA0 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* HMDMA0 Current Edge Count Register */ #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* HMDMA0 Current Block Count Register */ #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* HMDMA1 Initial Edge Count Register */ #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* HMDMA1 Initial Block Count Register */ #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* HMDMA1 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* HMDMA1 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* HMDMA1 Current Edge Count Register */ #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* HMDMA1 Current Block Count Register */ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* L1 Data Memory Controller Register */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) #define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) #define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) #define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) #define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) diff --git a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h index 61ffa148e8..81b158e374 100644 --- a/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h +++ b/arch/blackfin/include/asm/mach-bf537/ADSP-EDN-BF534-extended_def.h @@ -6,6 +6,8 @@ #ifndef __BFIN_DEF_ADSP_EDN_BF534_extended__ #define __BFIN_DEF_ADSP_EDN_BF534_extended__ +#include "../mach-common/ADSP-EDN-core_def.h" + #define PLL_CTL 0xFFC00000 /* PLL Control Register */ #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ @@ -810,114 +812,7 @@ #define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */ -#define DCPLB_FAULT_ADDR 0xFFE0000C -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 -#define ICPLB_FAULT_ADDR 0xFFE0100C -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ #define CHIPID 0xFFC00014 -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 #define DMA_TC_CNT 0xFFC00B0C #define DMA_TC_PER 0xFFC00B10 diff --git a/arch/blackfin/include/asm/mach-bf537/BF534_def.h b/arch/blackfin/include/asm/mach-bf537/BF534_def.h index 5f0437b090..e04676c14a 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF534_def.h +++ b/arch/blackfin/include/asm/mach-bf537/BF534_def.h @@ -10,12 +10,14 @@ #include "ADSP-EDN-BF534-extended_def.h" +#if defined(__BFIN_DEF_ADSP_BF537_proc__) || !defined(__BFIN_DEF_ADSP_BF536_proc__) #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ #define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) #define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ #define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) #define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#endif #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ #define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h index d753b5e248..ccf57c8236 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h +++ b/arch/blackfin/include/asm/mach-bf537/BF536_cdef.h @@ -6,245 +6,164 @@ #ifndef __BFIN_CDEF_ADSP_BF536_proc__ #define __BFIN_CDEF_ADSP_BF536_proc__ -#include "../mach-common/ADSP-EDN-core_cdef.h" +#include "BF534_cdef.h" -#include "ADSP-EDN-BF534-extended_cdef.h" - -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ #define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) #define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ #define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) #define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ #define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) #define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ #define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) #define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ #define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) #define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ #define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) #define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ #define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) #define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ #define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) #define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ #define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) #define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ #define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) #define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ #define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) #define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) #define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) #define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) #define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ #define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) #define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ #define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) #define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ #define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) #define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ #define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) #define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ #define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) #define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ #define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ #define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) #define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ #define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) #define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ #define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) #define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ #define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) #define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ #define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) #define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ #define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) #define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ #define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) #define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ #define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) #define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ #define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) #define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ #define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) #define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ #define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) #define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ #define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) #define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ #define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) #define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ #define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) #define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ #define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) #define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ #define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) #define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ #define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) #define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ #define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) #define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ #define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) #define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ #define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) #define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ #define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) #define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ #define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) #define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ #define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) #define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ #define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) #define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ #define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) #define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ #define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) #define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ #define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) #define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ #define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) #define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ #define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) #define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ #define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) #define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ #define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) #define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ #define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) #define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ #define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) #define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ #define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) #define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ #define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) #define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ #define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) #define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ #define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) #define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ #define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) #define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ #define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) #define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ #define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) #define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ #define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) #define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ #define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) #define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ #define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) #define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ #define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) #define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ #define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) #define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ #define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) #define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ #define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) #define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ #define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) #define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ #define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) #define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ #define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) #define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ #define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) #define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ #define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) #define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ #define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) #define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ #define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) #define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ #define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) #define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ #define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) #define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ #define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) #define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ #define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) #define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) diff --git a/arch/blackfin/include/asm/mach-bf537/BF536_def.h b/arch/blackfin/include/asm/mach-bf537/BF536_def.h index 810fe91400..9d8d00a412 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF536_def.h +++ b/arch/blackfin/include/asm/mach-bf537/BF536_def.h @@ -6,9 +6,7 @@ #ifndef __BFIN_DEF_ADSP_BF536_proc__ #define __BFIN_DEF_ADSP_BF536_proc__ -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF534-extended_def.h" +#include "BF534_def.h" #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ #define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ @@ -89,14 +87,5 @@ #define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ #define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ #define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) #endif /* __BFIN_DEF_ADSP_BF536_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h index 5eff57d22d..958363bfcb 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h +++ b/arch/blackfin/include/asm/mach-bf537/BF537_cdef.h @@ -1,251 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF537_proc__ -#define __BFIN_CDEF_ADSP_BF537_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF534-extended_cdef.h" - -#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */ -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define pEMAC_ADDRLO ((uint32_t volatile *)EMAC_ADDRLO) /* Address Low (32 LSBs) Register */ -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define pEMAC_ADDRHI ((uint32_t volatile *)EMAC_ADDRHI) /* Address High (16 MSBs) Register */ -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define pEMAC_HASHLO ((uint32_t volatile *)EMAC_HASHLO) /* Multicast Hash Table Low (Bins 31-0) Register */ -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define pEMAC_HASHHI ((uint32_t volatile *)EMAC_HASHHI) /* Multicast Hash Table High (Bins 63-32) Register */ -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define pEMAC_STAADD ((uint32_t volatile *)EMAC_STAADD) /* Station Management Address Register */ -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define pEMAC_STADAT ((uint32_t volatile *)EMAC_STADAT) /* Station Management Data Register */ -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define pEMAC_FLC ((uint32_t volatile *)EMAC_FLC) /* Flow Control Register */ -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define pEMAC_VLAN1 ((uint32_t volatile *)EMAC_VLAN1) /* VLAN1 Tag Register */ -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define pEMAC_VLAN2 ((uint32_t volatile *)EMAC_VLAN2) /* VLAN2 Tag Register */ -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define pEMAC_WKUP_CTL ((uint32_t volatile *)EMAC_WKUP_CTL) /* Wake-Up Control/Status Register */ -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define pEMAC_WKUP_FFMSK0 ((uint32_t volatile *)EMAC_WKUP_FFMSK0) /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define pEMAC_WKUP_FFMSK1 ((uint32_t volatile *)EMAC_WKUP_FFMSK1) /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define pEMAC_WKUP_FFMSK2 ((uint32_t volatile *)EMAC_WKUP_FFMSK2) /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define pEMAC_WKUP_FFMSK3 ((uint32_t volatile *)EMAC_WKUP_FFMSK3) /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define pEMAC_WKUP_FFCMD ((uint32_t volatile *)EMAC_WKUP_FFCMD) /* Wake-Up Frame Filter Commands Register */ -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define pEMAC_WKUP_FFOFF ((uint32_t volatile *)EMAC_WKUP_FFOFF) /* Wake-Up Frame Filter Offsets Register */ -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define pEMAC_WKUP_FFCRC0 ((uint32_t volatile *)EMAC_WKUP_FFCRC0) /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define pEMAC_WKUP_FFCRC1 ((uint32_t volatile *)EMAC_WKUP_FFCRC1) /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) -#define pEMAC_SYSCTL ((uint32_t volatile *)EMAC_SYSCTL) /* EMAC System Control Register */ -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define pEMAC_SYSTAT ((uint32_t volatile *)EMAC_SYSTAT) /* EMAC System Status Register */ -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define pEMAC_RX_STAT ((uint32_t volatile *)EMAC_RX_STAT) /* RX Current Frame Status Register */ -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define pEMAC_RX_STKY ((uint32_t volatile *)EMAC_RX_STKY) /* RX Sticky Frame Status Register */ -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define pEMAC_RX_IRQE ((uint32_t volatile *)EMAC_RX_IRQE) /* RX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define pEMAC_TX_STAT ((uint32_t volatile *)EMAC_TX_STAT) /* TX Current Frame Status Register */ -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define pEMAC_TX_STKY ((uint32_t volatile *)EMAC_TX_STKY) /* TX Sticky Frame Status Register */ -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define pEMAC_TX_IRQE ((uint32_t volatile *)EMAC_TX_IRQE) /* TX Frame Status Interrupt Enables Register */ -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) -#define pEMAC_MMC_CTL ((uint32_t volatile *)EMAC_MMC_CTL) /* MMC Counter Control Register */ -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define pEMAC_MMC_RIRQS ((uint32_t volatile *)EMAC_MMC_RIRQS) /* MMC RX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define pEMAC_MMC_RIRQE ((uint32_t volatile *)EMAC_MMC_RIRQE) /* MMC RX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define pEMAC_MMC_TIRQS ((uint32_t volatile *)EMAC_MMC_TIRQS) /* MMC TX Interrupt Status Register */ -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define pEMAC_MMC_TIRQE ((uint32_t volatile *)EMAC_MMC_TIRQE) /* MMC TX Interrupt Enables Register */ -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) -#define pEMAC_RXC_OK ((uint32_t volatile *)EMAC_RXC_OK) /* RX Frame Successful Count */ -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define pEMAC_RXC_FCS ((uint32_t volatile *)EMAC_RXC_FCS) /* RX Frame FCS Failure Count */ -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define pEMAC_RXC_ALIGN ((uint32_t volatile *)EMAC_RXC_ALIGN) /* RX Alignment Error Count */ -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define pEMAC_RXC_OCTET ((uint32_t volatile *)EMAC_RXC_OCTET) /* RX Octets Successfully Received Count */ -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define pEMAC_RXC_DMAOVF ((uint32_t volatile *)EMAC_RXC_DMAOVF) /* Internal MAC Sublayer Error RX Frame Count */ -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define pEMAC_RXC_UNICST ((uint32_t volatile *)EMAC_RXC_UNICST) /* Unicast RX Frame Count */ -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define pEMAC_RXC_MULTI ((uint32_t volatile *)EMAC_RXC_MULTI) /* Multicast RX Frame Count */ -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define pEMAC_RXC_BROAD ((uint32_t volatile *)EMAC_RXC_BROAD) /* Broadcast RX Frame Count */ -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define pEMAC_RXC_LNERRI ((uint32_t volatile *)EMAC_RXC_LNERRI) /* RX Frame In Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define pEMAC_RXC_LNERRO ((uint32_t volatile *)EMAC_RXC_LNERRO) /* RX Frame Out Of Range Error Count */ -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define pEMAC_RXC_LONG ((uint32_t volatile *)EMAC_RXC_LONG) /* RX Frame Too Long Count */ -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define pEMAC_RXC_MACCTL ((uint32_t volatile *)EMAC_RXC_MACCTL) /* MAC Control RX Frame Count */ -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define pEMAC_RXC_OPCODE ((uint32_t volatile *)EMAC_RXC_OPCODE) /* Unsupported Op-Code RX Frame Count */ -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define pEMAC_RXC_PAUSE ((uint32_t volatile *)EMAC_RXC_PAUSE) /* MAC Control Pause RX Frame Count */ -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define pEMAC_RXC_ALLFRM ((uint32_t volatile *)EMAC_RXC_ALLFRM) /* Overall RX Frame Count */ -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define pEMAC_RXC_ALLOCT ((uint32_t volatile *)EMAC_RXC_ALLOCT) /* Overall RX Octet Count */ -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define pEMAC_RXC_TYPED ((uint32_t volatile *)EMAC_RXC_TYPED) /* Type/Length Consistent RX Frame Count */ -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define pEMAC_RXC_SHORT ((uint32_t volatile *)EMAC_RXC_SHORT) /* RX Frame Fragment Count - Byte Count x < 64 */ -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define pEMAC_RXC_EQ64 ((uint32_t volatile *)EMAC_RXC_EQ64) /* Good RX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define pEMAC_RXC_LT128 ((uint32_t volatile *)EMAC_RXC_LT128) /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define pEMAC_RXC_LT256 ((uint32_t volatile *)EMAC_RXC_LT256) /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define pEMAC_RXC_LT512 ((uint32_t volatile *)EMAC_RXC_LT512) /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define pEMAC_RXC_LT1024 ((uint32_t volatile *)EMAC_RXC_LT1024) /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define pEMAC_RXC_GE1024 ((uint32_t volatile *)EMAC_RXC_GE1024) /* Good RX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) -#define pEMAC_TXC_OK ((uint32_t volatile *)EMAC_TXC_OK) /* TX Frame Successful Count */ -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define pEMAC_TXC_1COL ((uint32_t volatile *)EMAC_TXC_1COL) /* TX Frames Successful After Single Collision Count */ -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define pEMAC_TXC_GT1COL ((uint32_t volatile *)EMAC_TXC_GT1COL) /* TX Frames Successful After Multiple Collisions Count */ -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define pEMAC_TXC_OCTET ((uint32_t volatile *)EMAC_TXC_OCTET) /* TX Octets Successfully Received Count */ -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define pEMAC_TXC_DEFER ((uint32_t volatile *)EMAC_TXC_DEFER) /* TX Frame Delayed Due To Busy Count */ -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define pEMAC_TXC_LATECL ((uint32_t volatile *)EMAC_TXC_LATECL) /* Late TX Collisions Count */ -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define pEMAC_TXC_XS_COL ((uint32_t volatile *)EMAC_TXC_XS_COL) /* TX Frame Failed Due To Excessive Collisions Count */ -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define pEMAC_TXC_DMAUND ((uint32_t volatile *)EMAC_TXC_DMAUND) /* Internal MAC Sublayer Error TX Frame Count */ -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define pEMAC_TXC_CRSERR ((uint32_t volatile *)EMAC_TXC_CRSERR) /* Carrier Sense Deasserted During TX Frame Count */ -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define pEMAC_TXC_UNICST ((uint32_t volatile *)EMAC_TXC_UNICST) /* Unicast TX Frame Count */ -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define pEMAC_TXC_MULTI ((uint32_t volatile *)EMAC_TXC_MULTI) /* Multicast TX Frame Count */ -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define pEMAC_TXC_BROAD ((uint32_t volatile *)EMAC_TXC_BROAD) /* Broadcast TX Frame Count */ -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define pEMAC_TXC_XS_DFR ((uint32_t volatile *)EMAC_TXC_XS_DFR) /* TX Frames With Excessive Deferral Count */ -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define pEMAC_TXC_MACCTL ((uint32_t volatile *)EMAC_TXC_MACCTL) /* MAC Control TX Frame Count */ -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define pEMAC_TXC_ALLFRM ((uint32_t volatile *)EMAC_TXC_ALLFRM) /* Overall TX Frame Count */ -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define pEMAC_TXC_ALLOCT ((uint32_t volatile *)EMAC_TXC_ALLOCT) /* Overall TX Octet Count */ -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define pEMAC_TXC_EQ64 ((uint32_t volatile *)EMAC_TXC_EQ64) /* Good TX Frame Count - Byte Count x = 64 */ -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define pEMAC_TXC_LT128 ((uint32_t volatile *)EMAC_TXC_LT128) /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define pEMAC_TXC_LT256 ((uint32_t volatile *)EMAC_TXC_LT256) /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define pEMAC_TXC_LT512 ((uint32_t volatile *)EMAC_TXC_LT512) /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define pEMAC_TXC_LT1024 ((uint32_t volatile *)EMAC_TXC_LT1024) /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define pEMAC_TXC_GE1024 ((uint32_t volatile *)EMAC_TXC_GE1024) /* Good TX Frame Count - Byte Count x >= 1024 */ -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define pEMAC_TXC_ABORT ((uint32_t volatile *)EMAC_TXC_ABORT) /* Total TX Frames Aborted Count */ -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) - -#endif /* __BFIN_CDEF_ADSP_BF537_proc__ */ +#include "BF536_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf537/BF537_def.h b/arch/blackfin/include/asm/mach-bf537/BF537_def.h index 030fa6461a..383d7a770b 100644 --- a/arch/blackfin/include/asm/mach-bf537/BF537_def.h +++ b/arch/blackfin/include/asm/mach-bf537/BF537_def.h @@ -1,108 +1 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF537_proc__ -#define __BFIN_DEF_ADSP_BF537_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF534-extended_def.h" - -#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ -#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ -#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ -#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ -#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ -#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ -#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ -#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ -#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ -#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ -#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ -#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ -#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ -#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ -#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ -#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ -#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ -#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ -#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ -#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ -#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ -#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ -#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ -#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ -#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ -#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ -#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ -#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ -#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ -#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ -#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ -#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ -#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ -#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ -#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ -#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ -#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ -#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ -#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ -#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ -#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ -#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ -#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ -#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ -#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ -#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ -#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ -#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ -#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ -#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ -#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ -#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ -#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ -#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ -#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ -#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ -#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ -#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ -#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ -#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ -#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ -#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ -#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ -#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ -#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ -#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ -#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ -#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ -#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */ -#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ -#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ -#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ -#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ -#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ -#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ -#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) -#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) -#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ -#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) -#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) -#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ -#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) -#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) -#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ -#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) -#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) -#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ -#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) -#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) - -#endif /* __BFIN_DEF_ADSP_BF537_proc__ */ +#include "BF536_def.h" diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h b/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h new file mode 100644 index 0000000000..42acdcc4f0 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/BF538_cdef.h @@ -0,0 +1,2014 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF538_proc__ +#define __BFIN_CDEF_ADSP_BF538_proc__ + +#include "../mach-common/ADSP-EDN-core_cdef.h" + +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define bfin_read_SYSCR() bfin_read16(SYSCR) +#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) +#define bfin_read_SIC_RVECT() bfin_readPTR(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_writePTR(SIC_RVECT, val) +#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) +#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) +#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) +#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) +#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) +#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) +#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) +#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) +#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) +#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) +#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) +#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) +#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) +#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) +#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) +#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) +#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) +#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) +#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) +#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define bfin_read_UART0_IER() bfin_read16(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) +#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) +#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) +#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define bfin_read_UART1_IER() bfin_read16(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) +#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) +#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) +#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) +#define bfin_read_UART2_THR() bfin_read16(UART2_THR) +#define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_IER() bfin_read16(UART2_IER) +#define bfin_write_UART2_IER(val) bfin_write16(UART2_IER, val) +#define bfin_read_UART2_IIR() bfin_read16(UART2_IIR) +#define bfin_write_UART2_IIR(val) bfin_write16(UART2_IIR, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) +#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) +#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) +#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) +#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) +#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) +#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) +#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) +#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) +#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) +#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) +#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) +#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) +#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) +#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) +#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) +#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) +#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) +#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) +#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) +#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) +#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) +#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) +#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) +#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) +#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) +#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) +#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) +#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) +#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) +#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) +#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) +#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) +#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) +#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) +#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) +#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) +#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) +#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) +#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) +#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) +#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) +#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) +#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) +#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) +#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) +#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) +#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) +#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) +#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) +#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) +#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) +#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) +#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) +#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) +#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) +#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) +#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) +#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) +#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) +#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) +#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) +#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) +#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) +#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) +#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) +#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) +#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) +#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) +#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) +#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) +#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) +#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) +#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) +#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) +#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) +#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) +#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) +#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) +#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) +#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) +#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) +#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) +#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) +#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) +#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) +#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) +#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) +#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) +#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) +#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) +#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) +#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) +#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) +#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) +#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) +#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) +#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) +#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) +#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) +#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) +#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) +#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) +#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) +#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) +#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) +#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) +#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) +#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) +#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) +#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) +#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) +#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) +#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) +#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) +#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) +#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) +#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) +#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) +#define bfin_read_PORTFIO() bfin_read16(PORTFIO) +#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val) +#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR) +#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val) +#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET) +#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val) +#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE) +#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val) +#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA) +#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val) +#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR) +#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val) +#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET) +#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val) +#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE) +#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val) +#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB) +#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val) +#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR) +#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val) +#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET) +#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val) +#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE) +#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val) +#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR) +#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val) +#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR) +#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val) +#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE) +#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val) +#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH) +#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val) +#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN) +#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val) +#define bfin_read_PORTCIO_FER() bfin_read16(PORTCIO_FER) +#define bfin_write_PORTCIO_FER(val) bfin_write16(PORTCIO_FER, val) +#define bfin_read_PORTCIO() bfin_read16(PORTCIO) +#define bfin_write_PORTCIO(val) bfin_write16(PORTCIO, val) +#define bfin_read_PORTCIO_CLEAR() bfin_read16(PORTCIO_CLEAR) +#define bfin_write_PORTCIO_CLEAR(val) bfin_write16(PORTCIO_CLEAR, val) +#define bfin_read_PORTCIO_SET() bfin_read16(PORTCIO_SET) +#define bfin_write_PORTCIO_SET(val) bfin_write16(PORTCIO_SET, val) +#define bfin_read_PORTCIO_TOGGLE() bfin_read16(PORTCIO_TOGGLE) +#define bfin_write_PORTCIO_TOGGLE(val) bfin_write16(PORTCIO_TOGGLE, val) +#define bfin_read_PORTCIO_DIR() bfin_read16(PORTCIO_DIR) +#define bfin_write_PORTCIO_DIR(val) bfin_write16(PORTCIO_DIR, val) +#define bfin_read_PORTCIO_INEN() bfin_read16(PORTCIO_INEN) +#define bfin_write_PORTCIO_INEN(val) bfin_write16(PORTCIO_INEN, val) +#define bfin_read_PORTDIO_FER() bfin_read16(PORTDIO_FER) +#define bfin_write_PORTDIO_FER(val) bfin_write16(PORTDIO_FER, val) +#define bfin_read_PORTDIO() bfin_read16(PORTDIO) +#define bfin_write_PORTDIO(val) bfin_write16(PORTDIO, val) +#define bfin_read_PORTDIO_CLEAR() bfin_read16(PORTDIO_CLEAR) +#define bfin_write_PORTDIO_CLEAR(val) bfin_write16(PORTDIO_CLEAR, val) +#define bfin_read_PORTDIO_SET() bfin_read16(PORTDIO_SET) +#define bfin_write_PORTDIO_SET(val) bfin_write16(PORTDIO_SET, val) +#define bfin_read_PORTDIO_TOGGLE() bfin_read16(PORTDIO_TOGGLE) +#define bfin_write_PORTDIO_TOGGLE(val) bfin_write16(PORTDIO_TOGGLE, val) +#define bfin_read_PORTDIO_DIR() bfin_read16(PORTDIO_DIR) +#define bfin_write_PORTDIO_DIR(val) bfin_write16(PORTDIO_DIR, val) +#define bfin_read_PORTDIO_INEN() bfin_read16(PORTDIO_INEN) +#define bfin_write_PORTDIO_INEN(val) bfin_write16(PORTDIO_INEN, val) +#define bfin_read_PORTEIO_FER() bfin_read16(PORTEIO_FER) +#define bfin_write_PORTEIO_FER(val) bfin_write16(PORTEIO_FER, val) +#define bfin_read_PORTEIO() bfin_read16(PORTEIO) +#define bfin_write_PORTEIO(val) bfin_write16(PORTEIO, val) +#define bfin_read_PORTEIO_CLEAR() bfin_read16(PORTEIO_CLEAR) +#define bfin_write_PORTEIO_CLEAR(val) bfin_write16(PORTEIO_CLEAR, val) +#define bfin_read_PORTEIO_SET() bfin_read16(PORTEIO_SET) +#define bfin_write_PORTEIO_SET(val) bfin_write16(PORTEIO_SET, val) +#define bfin_read_PORTEIO_TOGGLE() bfin_read16(PORTEIO_TOGGLE) +#define bfin_write_PORTEIO_TOGGLE(val) bfin_write16(PORTEIO_TOGGLE, val) +#define bfin_read_PORTEIO_DIR() bfin_read16(PORTEIO_DIR) +#define bfin_write_PORTEIO_DIR(val) bfin_write16(PORTEIO_DIR, val) +#define bfin_read_PORTEIO_INEN() bfin_read16(PORTEIO_INEN) +#define bfin_write_PORTEIO_INEN(val) bfin_write16(PORTEIO_INEN, val) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) +#define bfin_read_DMA0_TC_PER() bfin_read16(DMA0_TC_PER) +#define bfin_write_DMA0_TC_PER(val) bfin_write16(DMA0_TC_PER, val) +#define bfin_read_DMA0_TC_CNT() bfin_read16(DMA0_TC_CNT) +#define bfin_write_DMA0_TC_CNT(val) bfin_write16(DMA0_TC_CNT, val) +#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) +#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) +#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) +#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) +#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) +#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) +#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) +#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) +#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) +#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) +#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) +#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) +#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) +#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) +#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) +#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) +#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) +#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) +#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) +#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) +#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) +#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) +#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) +#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) +#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) +#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) +#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) +#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) +#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) +#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) +#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) +#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) +#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) +#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) +#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) +#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) +#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) +#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) +#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) +#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) +#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) +#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) +#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) +#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) +#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) +#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) +#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) +#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) +#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) +#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) +#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) +#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) +#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) +#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) +#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) +#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) +#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) +#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) +#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) +#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) +#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) +#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) +#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) +#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) +#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) +#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) +#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) +#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) +#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) +#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) +#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) +#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) +#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) +#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) +#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) +#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) +#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) +#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) +#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) +#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) +#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) +#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) +#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) +#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) +#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) +#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) +#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) +#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) +#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) +#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) +#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) +#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) +#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) +#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) +#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) +#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) +#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) +#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) +#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) +#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) +#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) +#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) +#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) +#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) +#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) +#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) +#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) +#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) +#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) +#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) +#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) +#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) +#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) +#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) +#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) +#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) +#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) +#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) +#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) +#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) +#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) +#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) +#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) +#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) +#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) +#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) +#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) +#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) +#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) +#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) +#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) +#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) +#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) +#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) +#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) +#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) +#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) +#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) +#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) +#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) +#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) +#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) +#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) +#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) +#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) +#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) +#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) +#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) +#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) +#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) +#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) +#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) +#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) +#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) +#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) +#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) +#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) +#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) +#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) +#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) +#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) +#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) +#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) +#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) +#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) +#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) +#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) +#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) +#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) +#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) +#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) +#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) +#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) +#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) +#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) +#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) +#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) +#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) +#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) +#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) +#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) +#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) +#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) +#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) +#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) +#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) +#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) +#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) +#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) +#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) +#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) +#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) +#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) +#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) +#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) +#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) +#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) +#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) +#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) +#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) +#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) +#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) +#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) +#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) +#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) +#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) +#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) +#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) +#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) +#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) +#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) +#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) +#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) +#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) +#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) +#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) +#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) +#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) +#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) +#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) +#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) +#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) +#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) +#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) +#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) +#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) +#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) +#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) +#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) +#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) +#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) +#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) +#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) +#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) +#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) +#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) +#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) +#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) +#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) +#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) +#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) +#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) +#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) +#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) +#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) +#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) +#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) +#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) +#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) +#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) +#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) +#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) +#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) +#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) +#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) +#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) +#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) +#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) +#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) +#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) +#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) +#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) +#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) +#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) +#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) +#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) +#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) +#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) +#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) +#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) +#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) +#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) +#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) +#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) +#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) +#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) +#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) +#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) +#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) +#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) +#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) +#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) +#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) +#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) +#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) +#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) +#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) +#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) +#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) +#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) +#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) +#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) +#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) +#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) +#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) +#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) +#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) +#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) +#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) +#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) +#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) +#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) +#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) +#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) +#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) +#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) +#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) +#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) +#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) +#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) +#define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) +#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) +#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) +#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) +#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) +#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) +#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) +#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) +#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) +#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) +#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) +#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) +#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) +#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) +#define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) +#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) +#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) +#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) +#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) +#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) +#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) +#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) +#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) +#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) +#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) +#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) +#define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) +#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) +#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) +#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) +#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) +#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) +#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) +#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) +#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) +#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) +#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) +#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) +#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) +#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) +#define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) +#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) +#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) +#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) +#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) +#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) +#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) +#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) +#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) +#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) +#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) +#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) +#define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) +#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) +#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) +#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) +#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) +#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) +#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) +#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) +#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) +#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) +#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) +#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) +#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) +#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) +#define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) +#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) +#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) +#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) +#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) +#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) +#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) +#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) +#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) +#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) +#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) +#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) +#define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) +#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) +#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) +#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) +#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) +#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) +#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) +#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) +#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) +#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) +#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) +#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) +#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) +#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) +#define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) +#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) +#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) +#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) +#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) +#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) +#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) +#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) +#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) +#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) +#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) +#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) +#define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) +#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) +#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) +#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) +#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) +#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) +#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) +#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) +#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) +#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) +#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) +#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) +#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) +#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) +#define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) +#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) +#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) +#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) +#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) +#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) +#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) +#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) +#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) +#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) +#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) +#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) +#define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) +#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) +#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) +#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) +#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) +#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) +#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) +#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) +#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) +#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) +#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) +#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) +#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) +#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) +#define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) +#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) +#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) +#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) +#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) +#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) +#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) +#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) +#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) +#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) +#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) +#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) +#define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) +#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) +#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) +#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) +#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) +#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) +#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) +#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) +#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) +#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) +#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) +#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) +#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) +#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) +#define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) +#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) +#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) +#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) +#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) +#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) +#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) +#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) +#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) +#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) +#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) +#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) +#define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) +#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) +#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) +#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) +#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) +#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) +#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) +#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) +#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) +#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) +#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) +#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) +#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) +#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) +#define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) +#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) +#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) +#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) +#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) +#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) +#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) +#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) +#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) +#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) +#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR) +#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val) +#define bfin_read_MDMA0_D0_CONFIG() bfin_read16(MDMA0_D0_CONFIG) +#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val) +#define bfin_read_MDMA0_D0_X_COUNT() bfin_read16(MDMA0_D0_X_COUNT) +#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val) +#define bfin_read_MDMA0_D0_X_MODIFY() bfin_read16(MDMA0_D0_X_MODIFY) +#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val) +#define bfin_read_MDMA0_D0_Y_COUNT() bfin_read16(MDMA0_D0_Y_COUNT) +#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val) +#define bfin_read_MDMA0_D0_Y_MODIFY() bfin_read16(MDMA0_D0_Y_MODIFY) +#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val) +#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR) +#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR) +#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val) +#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS) +#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val) +#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT) +#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT) +#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR) +#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val) +#define bfin_read_MDMA0_S0_CONFIG() bfin_read16(MDMA0_S0_CONFIG) +#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val) +#define bfin_read_MDMA0_S0_X_COUNT() bfin_read16(MDMA0_S0_X_COUNT) +#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val) +#define bfin_read_MDMA0_S0_X_MODIFY() bfin_read16(MDMA0_S0_X_MODIFY) +#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val) +#define bfin_read_MDMA0_S0_Y_COUNT() bfin_read16(MDMA0_S0_Y_COUNT) +#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val) +#define bfin_read_MDMA0_S0_Y_MODIFY() bfin_read16(MDMA0_S0_Y_MODIFY) +#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val) +#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR) +#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR) +#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val) +#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS) +#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val) +#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT) +#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT) +#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR) +#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val) +#define bfin_read_MDMA0_D1_CONFIG() bfin_read16(MDMA0_D1_CONFIG) +#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val) +#define bfin_read_MDMA0_D1_X_COUNT() bfin_read16(MDMA0_D1_X_COUNT) +#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val) +#define bfin_read_MDMA0_D1_X_MODIFY() bfin_read16(MDMA0_D1_X_MODIFY) +#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val) +#define bfin_read_MDMA0_D1_Y_COUNT() bfin_read16(MDMA0_D1_Y_COUNT) +#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val) +#define bfin_read_MDMA0_D1_Y_MODIFY() bfin_read16(MDMA0_D1_Y_MODIFY) +#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val) +#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR) +#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR) +#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val) +#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS) +#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val) +#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT) +#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT) +#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR) +#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val) +#define bfin_read_MDMA0_S1_CONFIG() bfin_read16(MDMA0_S1_CONFIG) +#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val) +#define bfin_read_MDMA0_S1_X_COUNT() bfin_read16(MDMA0_S1_X_COUNT) +#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val) +#define bfin_read_MDMA0_S1_X_MODIFY() bfin_read16(MDMA0_S1_X_MODIFY) +#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val) +#define bfin_read_MDMA0_S1_Y_COUNT() bfin_read16(MDMA0_S1_Y_COUNT) +#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val) +#define bfin_read_MDMA0_S1_Y_MODIFY() bfin_read16(MDMA0_S1_Y_MODIFY) +#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val) +#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR) +#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR) +#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val) +#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS) +#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val) +#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT) +#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT) +#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) +#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) +#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) +#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) +#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) +#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) +#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) +#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) +#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) +#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) +#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) +#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) +#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) +#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) +#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) +#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) +#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) +#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) +#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) +#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) +#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) +#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) +#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) +#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) +#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) +#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) +#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) +#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) +#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) +#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) +#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) +#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) +#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) +#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) +#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) +#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) +#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) +#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) +#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) +#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) +#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) +#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) +#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) +#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) +#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) +#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) +#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) +#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) +#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) +#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) +#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) +#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) +#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) +#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) +#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) +#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) +#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) +#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) +#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) +#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) +#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) +#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) +#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) +#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) +#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) +#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) +#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) +#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) +#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) +#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) +#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) +#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) +#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) +#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) +#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) +#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) +#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) +#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) +#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) +#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) +#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) +#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) +#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) +#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) +#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) +#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) +#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) +#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) +#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) +#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) +#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) +#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL) +#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val) +#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) +#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) +#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) +#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) +#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) +#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) +#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) +#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) +#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) +#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) +#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) +#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) +#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) +#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) +#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) +#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) +#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) +#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) +#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) +#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) +#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) +#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) +#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) +#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) +#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) +#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) +#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) +#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) +#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) +#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) +#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL) +#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val) +#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) +#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) +#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) +#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) +#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) +#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) +#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) +#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) +#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) +#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) +#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) +#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) +#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) +#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) +#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) +#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) +#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) +#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) +#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) +#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) +#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) +#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) +#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) +#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) +#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) +#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) +#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1) +#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val) +#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1) +#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val) +#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1) +#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val) +#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1) +#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val) +#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1) +#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val) +#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1) +#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val) +#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1) +#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val) +#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1) +#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val) +#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1) +#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val) +#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1) +#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val) +#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1) +#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val) +#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1) +#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val) +#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1) +#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val) +#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2) +#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val) +#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2) +#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val) +#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2) +#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val) +#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2) +#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val) +#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2) +#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val) +#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2) +#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val) +#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2) +#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val) +#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2) +#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val) +#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2) +#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val) +#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2) +#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val) +#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2) +#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val) +#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2) +#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val) +#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2) +#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val) +#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK) +#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val) +#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING) +#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val) +#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG) +#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val) +#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS) +#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val) +#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC) +#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val) +#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS) +#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val) +#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM) +#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val) +#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF) +#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val) +#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL) +#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val) +#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR) +#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val) +#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION) +#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val) +#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD) +#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val) +#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR) +#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val) +#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR) +#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val) +#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG) +#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val) +#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT) +#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val) +#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC) +#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val) +#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) +#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val) +#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2) +#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val) +#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) +#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val) +#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H) +#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val) +#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L) +#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val) +#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H) +#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val) +#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L) +#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val) +#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H) +#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val) +#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L) +#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val) +#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H) +#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val) +#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L) +#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val) +#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H) +#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val) +#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L) +#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val) +#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H) +#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val) +#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L) +#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val) +#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H) +#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val) +#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L) +#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val) +#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H) +#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val) +#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L) +#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val) +#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H) +#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val) +#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L) +#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val) +#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H) +#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val) +#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L) +#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val) +#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H) +#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val) +#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L) +#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val) +#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H) +#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val) +#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L) +#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val) +#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H) +#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val) +#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L) +#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val) +#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H) +#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val) +#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L) +#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val) +#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H) +#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val) +#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L) +#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val) +#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H) +#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val) +#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L) +#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val) +#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H) +#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val) +#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L) +#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val) +#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H) +#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val) +#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L) +#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val) +#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H) +#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val) +#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L) +#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val) +#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H) +#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val) +#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L) +#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val) +#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H) +#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val) +#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L) +#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val) +#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H) +#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val) +#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L) +#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val) +#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H) +#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val) +#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L) +#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val) +#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H) +#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val) +#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L) +#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val) +#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H) +#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val) +#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L) +#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val) +#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H) +#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val) +#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L) +#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val) +#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H) +#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val) +#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L) +#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val) +#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H) +#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val) +#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L) +#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val) +#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H) +#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val) +#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L) +#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val) +#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H) +#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val) +#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L) +#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val) +#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H) +#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val) +#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L) +#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val) +#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H) +#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val) +#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0) +#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val) +#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1) +#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val) +#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2) +#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val) +#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3) +#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val) +#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH) +#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val) +#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP) +#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val) +#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0) +#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val) +#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1) +#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val) +#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0) +#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val) +#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1) +#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val) +#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2) +#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val) +#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3) +#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val) +#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH) +#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val) +#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP) +#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val) +#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0) +#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val) +#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1) +#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val) +#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0) +#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val) +#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1) +#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val) +#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2) +#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val) +#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3) +#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val) +#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH) +#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val) +#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP) +#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val) +#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0) +#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val) +#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1) +#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val) +#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0) +#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val) +#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1) +#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val) +#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2) +#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val) +#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3) +#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val) +#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH) +#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val) +#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP) +#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val) +#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0) +#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val) +#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1) +#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val) +#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0) +#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val) +#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1) +#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val) +#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2) +#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val) +#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3) +#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val) +#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH) +#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val) +#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP) +#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val) +#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0) +#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val) +#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1) +#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val) +#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0) +#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val) +#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1) +#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val) +#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2) +#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val) +#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3) +#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val) +#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH) +#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val) +#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP) +#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val) +#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0) +#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val) +#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1) +#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val) +#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0) +#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val) +#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1) +#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val) +#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2) +#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val) +#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3) +#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val) +#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH) +#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val) +#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP) +#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val) +#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0) +#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val) +#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1) +#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val) +#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0) +#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val) +#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1) +#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val) +#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2) +#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val) +#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3) +#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val) +#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH) +#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val) +#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP) +#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val) +#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0) +#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val) +#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1) +#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val) +#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0) +#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val) +#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1) +#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val) +#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2) +#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val) +#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3) +#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val) +#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH) +#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val) +#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP) +#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val) +#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0) +#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val) +#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1) +#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val) +#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0) +#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val) +#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1) +#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val) +#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2) +#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val) +#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3) +#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val) +#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH) +#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val) +#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP) +#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val) +#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0) +#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val) +#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1) +#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val) +#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0) +#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val) +#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1) +#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val) +#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2) +#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val) +#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3) +#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val) +#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH) +#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val) +#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP) +#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val) +#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0) +#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val) +#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1) +#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val) +#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0) +#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val) +#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1) +#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val) +#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2) +#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val) +#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3) +#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val) +#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH) +#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val) +#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP) +#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val) +#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0) +#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val) +#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1) +#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val) +#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0) +#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val) +#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1) +#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val) +#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2) +#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val) +#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3) +#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val) +#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH) +#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val) +#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP) +#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val) +#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0) +#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val) +#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1) +#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val) +#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0) +#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val) +#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1) +#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val) +#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2) +#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val) +#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3) +#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val) +#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH) +#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val) +#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP) +#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val) +#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0) +#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val) +#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1) +#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val) +#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0) +#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val) +#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1) +#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val) +#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2) +#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val) +#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3) +#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val) +#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH) +#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val) +#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP) +#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val) +#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0) +#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val) +#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1) +#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val) +#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0) +#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val) +#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1) +#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val) +#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2) +#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val) +#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3) +#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val) +#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH) +#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val) +#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP) +#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val) +#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0) +#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val) +#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1) +#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val) +#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0) +#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val) +#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1) +#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val) +#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2) +#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val) +#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3) +#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val) +#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH) +#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val) +#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP) +#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val) +#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0) +#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val) +#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1) +#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val) +#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0) +#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val) +#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1) +#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val) +#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2) +#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val) +#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3) +#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val) +#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH) +#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val) +#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP) +#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val) +#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0) +#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val) +#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1) +#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val) +#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0) +#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val) +#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1) +#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val) +#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2) +#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val) +#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3) +#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val) +#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH) +#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val) +#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP) +#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val) +#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0) +#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val) +#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1) +#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val) +#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0) +#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val) +#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1) +#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val) +#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2) +#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val) +#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3) +#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val) +#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH) +#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val) +#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP) +#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val) +#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0) +#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val) +#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1) +#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val) +#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0) +#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val) +#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1) +#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val) +#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2) +#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val) +#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3) +#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val) +#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH) +#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val) +#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP) +#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val) +#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0) +#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val) +#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1) +#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val) +#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0) +#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val) +#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1) +#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val) +#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2) +#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val) +#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3) +#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val) +#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH) +#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val) +#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP) +#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val) +#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0) +#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val) +#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1) +#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val) +#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0) +#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val) +#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1) +#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val) +#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2) +#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val) +#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3) +#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val) +#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH) +#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val) +#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP) +#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val) +#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0) +#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val) +#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1) +#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val) +#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0) +#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val) +#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1) +#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val) +#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2) +#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val) +#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3) +#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val) +#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH) +#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val) +#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP) +#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val) +#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0) +#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val) +#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1) +#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val) +#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0) +#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val) +#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1) +#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val) +#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2) +#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val) +#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3) +#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val) +#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH) +#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val) +#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP) +#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val) +#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0) +#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val) +#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1) +#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val) +#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0) +#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val) +#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1) +#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val) +#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2) +#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val) +#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3) +#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val) +#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH) +#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val) +#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP) +#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val) +#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0) +#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val) +#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1) +#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val) +#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0) +#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val) +#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1) +#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val) +#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2) +#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val) +#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3) +#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val) +#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH) +#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val) +#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP) +#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val) +#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0) +#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val) +#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1) +#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val) +#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0) +#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val) +#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1) +#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val) +#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2) +#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val) +#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3) +#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val) +#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH) +#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val) +#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP) +#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val) +#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0) +#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val) +#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1) +#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val) +#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0) +#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val) +#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1) +#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val) +#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2) +#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val) +#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3) +#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val) +#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH) +#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val) +#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP) +#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val) +#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0) +#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val) +#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1) +#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val) +#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0) +#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val) +#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1) +#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val) +#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2) +#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val) +#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3) +#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val) +#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH) +#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val) +#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP) +#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val) +#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0) +#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val) +#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1) +#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val) +#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0) +#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val) +#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1) +#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val) +#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2) +#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val) +#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3) +#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val) +#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH) +#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val) +#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP) +#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val) +#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0) +#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val) +#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1) +#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val) +#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0) +#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val) +#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1) +#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val) +#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2) +#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val) +#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3) +#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val) +#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH) +#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val) +#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP) +#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val) +#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0) +#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val) +#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1) +#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val) + +#endif /* __BFIN_CDEF_ADSP_BF538_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf538/BF538_def.h b/arch/blackfin/include/asm/mach-bf538/BF538_def.h new file mode 100644 index 0000000000..eae8e8178e --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/BF538_def.h @@ -0,0 +1,1031 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF538_proc__ +#define __BFIN_DEF_ADSP_BF538_proc__ + +#include "../mach-common/ADSP-EDN-core_def.h" + +#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ +#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ +#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ +#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ +#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ +#define CHIPID 0xFFC00014 +#define SWRST 0xFFC00100 /* Software Reset Register */ +#define SYSCR 0xFFC00104 /* System Configuration register */ +#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register 0 */ +#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register 0 */ +#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register 0 */ +#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ +#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ +#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ +#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ +#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ +#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ +#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ +#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ +#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ +#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ +#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ +#define RTC_STAT 0xFFC00300 +#define RTC_ICTL 0xFFC00304 +#define RTC_ISTAT 0xFFC00308 +#define RTC_SWCNT 0xFFC0030C +#define RTC_ALARM 0xFFC00310 +#define RTC_PREN 0xFFC00314 +#define UART0_THR 0xFFC00400 +#define UART0_RBR 0xFFC00400 +#define UART0_DLL 0xFFC00400 +#define UART0_DLH 0xFFC00404 +#define UART0_IER 0xFFC00404 +#define UART0_IIR 0xFFC00408 +#define UART0_LCR 0xFFC0040C +#define UART0_MCR 0xFFC00410 +#define UART0_LSR 0xFFC00414 +#define UART0_SCR 0xFFC0041C +#define UART0_GCTL 0xFFC00424 +#define UART1_THR 0xFFC02000 +#define UART1_RBR 0xFFC02000 +#define UART1_DLL 0xFFC02000 +#define UART1_DLH 0xFFC02004 +#define UART1_IER 0xFFC02004 +#define UART1_IIR 0xFFC02008 +#define UART1_LCR 0xFFC0200C +#define UART1_MCR 0xFFC02010 +#define UART1_LSR 0xFFC02014 +#define UART1_SCR 0xFFC0201C +#define UART1_GCTL 0xFFC02024 +#define UART2_THR 0xFFC02100 +#define UART2_RBR 0xFFC02100 +#define UART2_DLL 0xFFC02100 +#define UART2_DLH 0xFFC02104 +#define UART2_IER 0xFFC02104 +#define UART2_IIR 0xFFC02108 +#define UART2_LCR 0xFFC0210C +#define UART2_MCR 0xFFC02110 +#define UART2_LSR 0xFFC02114 +#define UART2_SCR 0xFFC0211C +#define UART2_GCTL 0xFFC02124 +#define SPI0_CTL 0xFFC00500 +#define SPI0_FLG 0xFFC00504 +#define SPI0_STAT 0xFFC00508 +#define SPI0_TDBR 0xFFC0050C +#define SPI0_RDBR 0xFFC00510 +#define SPI0_BAUD 0xFFC00514 +#define SPI0_SHADOW 0xFFC00518 +#define SPI1_CTL 0xFFC02300 +#define SPI1_FLG 0xFFC02304 +#define SPI1_STAT 0xFFC02308 +#define SPI1_TDBR 0xFFC0230C +#define SPI1_RDBR 0xFFC02310 +#define SPI1_BAUD 0xFFC02314 +#define SPI1_SHADOW 0xFFC02318 +#define SPI2_CTL 0xFFC02400 +#define SPI2_FLG 0xFFC02404 +#define SPI2_STAT 0xFFC02408 +#define SPI2_TDBR 0xFFC0240C +#define SPI2_RDBR 0xFFC02410 +#define SPI2_BAUD 0xFFC02414 +#define SPI2_SHADOW 0xFFC02418 +#define TIMER0_CONFIG 0xFFC00600 +#define TIMER0_COUNTER 0xFFC00604 +#define TIMER0_PERIOD 0xFFC00608 +#define TIMER0_WIDTH 0xFFC0060C +#define TIMER1_CONFIG 0xFFC00610 +#define TIMER1_COUNTER 0xFFC00614 +#define TIMER1_PERIOD 0xFFC00618 +#define TIMER1_WIDTH 0xFFC0061C +#define TIMER2_CONFIG 0xFFC00620 +#define TIMER2_COUNTER 0xFFC00624 +#define TIMER2_PERIOD 0xFFC00628 +#define TIMER2_WIDTH 0xFFC0062C +#define TIMER_ENABLE 0xFFC00640 +#define TIMER_DISABLE 0xFFC00644 +#define TIMER_STATUS 0xFFC00648 +#define SPORT0_TCR1 0xFFC00800 +#define SPORT0_TCR2 0xFFC00804 +#define SPORT0_TCLKDIV 0xFFC00808 +#define SPORT0_TFSDIV 0xFFC0080C +#define SPORT0_TX 0xFFC00810 +#define SPORT0_RX 0xFFC00818 +#define SPORT0_RCR1 0xFFC00820 +#define SPORT0_RCR2 0xFFC00824 +#define SPORT0_RCLKDIV 0xFFC00828 +#define SPORT0_RFSDIV 0xFFC0082C +#define SPORT0_STAT 0xFFC00830 +#define SPORT0_CHNL 0xFFC00834 +#define SPORT0_MCMC1 0xFFC00838 +#define SPORT0_MCMC2 0xFFC0083C +#define SPORT0_MTCS0 0xFFC00840 +#define SPORT0_MTCS1 0xFFC00844 +#define SPORT0_MTCS2 0xFFC00848 +#define SPORT0_MTCS3 0xFFC0084C +#define SPORT0_MRCS0 0xFFC00850 +#define SPORT0_MRCS1 0xFFC00854 +#define SPORT0_MRCS2 0xFFC00858 +#define SPORT0_MRCS3 0xFFC0085C +#define SPORT1_TCR1 0xFFC00900 +#define SPORT1_TCR2 0xFFC00904 +#define SPORT1_TCLKDIV 0xFFC00908 +#define SPORT1_TFSDIV 0xFFC0090C +#define SPORT1_TX 0xFFC00910 +#define SPORT1_RX 0xFFC00918 +#define SPORT1_RCR1 0xFFC00920 +#define SPORT1_RCR2 0xFFC00924 +#define SPORT1_RCLKDIV 0xFFC00928 +#define SPORT1_RFSDIV 0xFFC0092C +#define SPORT1_STAT 0xFFC00930 +#define SPORT1_CHNL 0xFFC00934 +#define SPORT1_MCMC1 0xFFC00938 +#define SPORT1_MCMC2 0xFFC0093C +#define SPORT1_MTCS0 0xFFC00940 +#define SPORT1_MTCS1 0xFFC00944 +#define SPORT1_MTCS2 0xFFC00948 +#define SPORT1_MTCS3 0xFFC0094C +#define SPORT1_MRCS0 0xFFC00950 +#define SPORT1_MRCS1 0xFFC00954 +#define SPORT1_MRCS2 0xFFC00958 +#define SPORT1_MRCS3 0xFFC0095C +#define SPORT2_TCR1 0xFFC02500 +#define SPORT2_TCR2 0xFFC02504 +#define SPORT2_TCLKDIV 0xFFC02508 +#define SPORT2_TFSDIV 0xFFC0250C +#define SPORT2_TX 0xFFC02510 +#define SPORT2_RX 0xFFC02518 +#define SPORT2_RCR1 0xFFC02520 +#define SPORT2_RCR2 0xFFC02524 +#define SPORT2_RCLKDIV 0xFFC02528 +#define SPORT2_RFSDIV 0xFFC0252C +#define SPORT2_STAT 0xFFC02530 +#define SPORT2_CHNL 0xFFC02534 +#define SPORT2_MCMC1 0xFFC02538 +#define SPORT2_MCMC2 0xFFC0253C +#define SPORT2_MTCS0 0xFFC02540 +#define SPORT2_MTCS1 0xFFC02544 +#define SPORT2_MTCS2 0xFFC02548 +#define SPORT2_MTCS3 0xFFC0254C +#define SPORT2_MRCS0 0xFFC02550 +#define SPORT2_MRCS1 0xFFC02554 +#define SPORT2_MRCS2 0xFFC02558 +#define SPORT2_MRCS3 0xFFC0255C +#define SPORT3_TCR1 0xFFC02600 +#define SPORT3_TCR2 0xFFC02604 +#define SPORT3_TCLKDIV 0xFFC02608 +#define SPORT3_TFSDIV 0xFFC0260C +#define SPORT3_TX 0xFFC02610 +#define SPORT3_RX 0xFFC02618 +#define SPORT3_RCR1 0xFFC02620 +#define SPORT3_RCR2 0xFFC02624 +#define SPORT3_RCLKDIV 0xFFC02628 +#define SPORT3_RFSDIV 0xFFC0262C +#define SPORT3_STAT 0xFFC02630 +#define SPORT3_CHNL 0xFFC02634 +#define SPORT3_MCMC1 0xFFC02638 +#define SPORT3_MCMC2 0xFFC0263C +#define SPORT3_MTCS0 0xFFC02640 +#define SPORT3_MTCS1 0xFFC02644 +#define SPORT3_MTCS2 0xFFC02648 +#define SPORT3_MTCS3 0xFFC0264C +#define SPORT3_MRCS0 0xFFC02650 +#define SPORT3_MRCS1 0xFFC02654 +#define SPORT3_MRCS2 0xFFC02658 +#define SPORT3_MRCS3 0xFFC0265C +#define PORTFIO 0xFFC00700 +#define PORTFIO_CLEAR 0xFFC00704 +#define PORTFIO_SET 0xFFC00708 +#define PORTFIO_TOGGLE 0xFFC0070C +#define PORTFIO_MASKA 0xFFC00710 +#define PORTFIO_MASKA_CLEAR 0xFFC00714 +#define PORTFIO_MASKA_SET 0xFFC00718 +#define PORTFIO_MASKA_TOGGLE 0xFFC0071C +#define PORTFIO_MASKB 0xFFC00720 +#define PORTFIO_MASKB_CLEAR 0xFFC00724 +#define PORTFIO_MASKB_SET 0xFFC00728 +#define PORTFIO_MASKB_TOGGLE 0xFFC0072C +#define PORTFIO_DIR 0xFFC00730 +#define PORTFIO_POLAR 0xFFC00734 +#define PORTFIO_EDGE 0xFFC00738 +#define PORTFIO_BOTH 0xFFC0073C +#define PORTFIO_INEN 0xFFC00740 +#define PORTCIO_FER 0xFFC01500 +#define PORTCIO 0xFFC01510 +#define PORTCIO_CLEAR 0xFFC01520 +#define PORTCIO_SET 0xFFC01530 +#define PORTCIO_TOGGLE 0xFFC01540 +#define PORTCIO_DIR 0xFFC01550 +#define PORTCIO_INEN 0xFFC01560 +#define PORTDIO_FER 0xFFC01504 +#define PORTDIO 0xFFC01514 +#define PORTDIO_CLEAR 0xFFC01524 +#define PORTDIO_SET 0xFFC01534 +#define PORTDIO_TOGGLE 0xFFC01544 +#define PORTDIO_DIR 0xFFC01554 +#define PORTDIO_INEN 0xFFC01564 +#define PORTEIO_FER 0xFFC01508 +#define PORTEIO 0xFFC01518 +#define PORTEIO_CLEAR 0xFFC01528 +#define PORTEIO_SET 0xFFC01538 +#define PORTEIO_TOGGLE 0xFFC01548 +#define PORTEIO_DIR 0xFFC01558 +#define PORTEIO_INEN 0xFFC01568 +#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ +#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ +#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ +#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ +#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ +#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ +#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ +#define DMA0_TC_PER 0xFFC00B0C /* Traffic Control Periods */ +#define DMA0_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts */ +#define DMA0_NEXT_DESC_PTR 0xFFC00C00 +#define DMA0_START_ADDR 0xFFC00C04 +#define DMA0_CONFIG 0xFFC00C08 +#define DMA0_X_COUNT 0xFFC00C10 +#define DMA0_X_MODIFY 0xFFC00C14 +#define DMA0_Y_COUNT 0xFFC00C18 +#define DMA0_Y_MODIFY 0xFFC00C1C +#define DMA0_CURR_DESC_PTR 0xFFC00C20 +#define DMA0_CURR_ADDR 0xFFC00C24 +#define DMA0_IRQ_STATUS 0xFFC00C28 +#define DMA0_PERIPHERAL_MAP 0xFFC00C2C +#define DMA0_CURR_X_COUNT 0xFFC00C30 +#define DMA0_CURR_Y_COUNT 0xFFC00C38 +#define DMA1_NEXT_DESC_PTR 0xFFC00C40 +#define DMA1_START_ADDR 0xFFC00C44 +#define DMA1_CONFIG 0xFFC00C48 +#define DMA1_X_COUNT 0xFFC00C50 +#define DMA1_X_MODIFY 0xFFC00C54 +#define DMA1_Y_COUNT 0xFFC00C58 +#define DMA1_Y_MODIFY 0xFFC00C5C +#define DMA1_CURR_DESC_PTR 0xFFC00C60 +#define DMA1_CURR_ADDR 0xFFC00C64 +#define DMA1_IRQ_STATUS 0xFFC00C68 +#define DMA1_PERIPHERAL_MAP 0xFFC00C6C +#define DMA1_CURR_X_COUNT 0xFFC00C70 +#define DMA1_CURR_Y_COUNT 0xFFC00C78 +#define DMA2_NEXT_DESC_PTR 0xFFC00C80 +#define DMA2_START_ADDR 0xFFC00C84 +#define DMA2_CONFIG 0xFFC00C88 +#define DMA2_X_COUNT 0xFFC00C90 +#define DMA2_X_MODIFY 0xFFC00C94 +#define DMA2_Y_COUNT 0xFFC00C98 +#define DMA2_Y_MODIFY 0xFFC00C9C +#define DMA2_CURR_DESC_PTR 0xFFC00CA0 +#define DMA2_CURR_ADDR 0xFFC00CA4 +#define DMA2_IRQ_STATUS 0xFFC00CA8 +#define DMA2_PERIPHERAL_MAP 0xFFC00CAC +#define DMA2_CURR_X_COUNT 0xFFC00CB0 +#define DMA2_CURR_Y_COUNT 0xFFC00CB8 +#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 +#define DMA3_START_ADDR 0xFFC00CC4 +#define DMA3_CONFIG 0xFFC00CC8 +#define DMA3_X_COUNT 0xFFC00CD0 +#define DMA3_X_MODIFY 0xFFC00CD4 +#define DMA3_Y_COUNT 0xFFC00CD8 +#define DMA3_Y_MODIFY 0xFFC00CDC +#define DMA3_CURR_DESC_PTR 0xFFC00CE0 +#define DMA3_CURR_ADDR 0xFFC00CE4 +#define DMA3_IRQ_STATUS 0xFFC00CE8 +#define DMA3_PERIPHERAL_MAP 0xFFC00CEC +#define DMA3_CURR_X_COUNT 0xFFC00CF0 +#define DMA3_CURR_Y_COUNT 0xFFC00CF8 +#define DMA4_NEXT_DESC_PTR 0xFFC00D00 +#define DMA4_START_ADDR 0xFFC00D04 +#define DMA4_CONFIG 0xFFC00D08 +#define DMA4_X_COUNT 0xFFC00D10 +#define DMA4_X_MODIFY 0xFFC00D14 +#define DMA4_Y_COUNT 0xFFC00D18 +#define DMA4_Y_MODIFY 0xFFC00D1C +#define DMA4_CURR_DESC_PTR 0xFFC00D20 +#define DMA4_CURR_ADDR 0xFFC00D24 +#define DMA4_IRQ_STATUS 0xFFC00D28 +#define DMA4_PERIPHERAL_MAP 0xFFC00D2C +#define DMA4_CURR_X_COUNT 0xFFC00D30 +#define DMA4_CURR_Y_COUNT 0xFFC00D38 +#define DMA5_NEXT_DESC_PTR 0xFFC00D40 +#define DMA5_START_ADDR 0xFFC00D44 +#define DMA5_CONFIG 0xFFC00D48 +#define DMA5_X_COUNT 0xFFC00D50 +#define DMA5_X_MODIFY 0xFFC00D54 +#define DMA5_Y_COUNT 0xFFC00D58 +#define DMA5_Y_MODIFY 0xFFC00D5C +#define DMA5_CURR_DESC_PTR 0xFFC00D60 +#define DMA5_CURR_ADDR 0xFFC00D64 +#define DMA5_IRQ_STATUS 0xFFC00D68 +#define DMA5_PERIPHERAL_MAP 0xFFC00D6C +#define DMA5_CURR_X_COUNT 0xFFC00D70 +#define DMA5_CURR_Y_COUNT 0xFFC00D78 +#define DMA6_NEXT_DESC_PTR 0xFFC00D80 +#define DMA6_START_ADDR 0xFFC00D84 +#define DMA6_CONFIG 0xFFC00D88 +#define DMA6_X_COUNT 0xFFC00D90 +#define DMA6_X_MODIFY 0xFFC00D94 +#define DMA6_Y_COUNT 0xFFC00D98 +#define DMA6_Y_MODIFY 0xFFC00D9C +#define DMA6_CURR_DESC_PTR 0xFFC00DA0 +#define DMA6_CURR_ADDR 0xFFC00DA4 +#define DMA6_IRQ_STATUS 0xFFC00DA8 +#define DMA6_PERIPHERAL_MAP 0xFFC00DAC +#define DMA6_CURR_X_COUNT 0xFFC00DB0 +#define DMA6_CURR_Y_COUNT 0xFFC00DB8 +#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 +#define DMA7_START_ADDR 0xFFC00DC4 +#define DMA7_CONFIG 0xFFC00DC8 +#define DMA7_X_COUNT 0xFFC00DD0 +#define DMA7_X_MODIFY 0xFFC00DD4 +#define DMA7_Y_COUNT 0xFFC00DD8 +#define DMA7_Y_MODIFY 0xFFC00DDC +#define DMA7_CURR_DESC_PTR 0xFFC00DE0 +#define DMA7_CURR_ADDR 0xFFC00DE4 +#define DMA7_IRQ_STATUS 0xFFC00DE8 +#define DMA7_PERIPHERAL_MAP 0xFFC00DEC +#define DMA7_CURR_X_COUNT 0xFFC00DF0 +#define DMA7_CURR_Y_COUNT 0xFFC00DF8 +#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */ +#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ +#define DMA8_NEXT_DESC_PTR 0xFFC01C00 +#define DMA8_START_ADDR 0xFFC01C04 +#define DMA8_CONFIG 0xFFC01C08 +#define DMA8_X_COUNT 0xFFC01C10 +#define DMA8_X_MODIFY 0xFFC01C14 +#define DMA8_Y_COUNT 0xFFC01C18 +#define DMA8_Y_MODIFY 0xFFC01C1C +#define DMA8_CURR_DESC_PTR 0xFFC01C20 +#define DMA8_CURR_ADDR 0xFFC01C24 +#define DMA8_IRQ_STATUS 0xFFC01C28 +#define DMA8_PERIPHERAL_MAP 0xFFC01C2C +#define DMA8_CURR_X_COUNT 0xFFC01C30 +#define DMA8_CURR_Y_COUNT 0xFFC01C38 +#define DMA9_NEXT_DESC_PTR 0xFFC01C40 +#define DMA9_START_ADDR 0xFFC01C44 +#define DMA9_CONFIG 0xFFC01C48 +#define DMA9_X_COUNT 0xFFC01C50 +#define DMA9_X_MODIFY 0xFFC01C54 +#define DMA9_Y_COUNT 0xFFC01C58 +#define DMA9_Y_MODIFY 0xFFC01C5C +#define DMA9_CURR_DESC_PTR 0xFFC01C60 +#define DMA9_CURR_ADDR 0xFFC01C64 +#define DMA9_IRQ_STATUS 0xFFC01C68 +#define DMA9_PERIPHERAL_MAP 0xFFC01C6C +#define DMA9_CURR_X_COUNT 0xFFC01C70 +#define DMA9_CURR_Y_COUNT 0xFFC01C78 +#define DMA10_NEXT_DESC_PTR 0xFFC01C80 +#define DMA10_START_ADDR 0xFFC01C84 +#define DMA10_CONFIG 0xFFC01C88 +#define DMA10_X_COUNT 0xFFC01C90 +#define DMA10_X_MODIFY 0xFFC01C94 +#define DMA10_Y_COUNT 0xFFC01C98 +#define DMA10_Y_MODIFY 0xFFC01C9C +#define DMA10_CURR_DESC_PTR 0xFFC01CA0 +#define DMA10_CURR_ADDR 0xFFC01CA4 +#define DMA10_IRQ_STATUS 0xFFC01CA8 +#define DMA10_PERIPHERAL_MAP 0xFFC01CAC +#define DMA10_CURR_X_COUNT 0xFFC01CB0 +#define DMA10_CURR_Y_COUNT 0xFFC01CB8 +#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 +#define DMA11_START_ADDR 0xFFC01CC4 +#define DMA11_CONFIG 0xFFC01CC8 +#define DMA11_X_COUNT 0xFFC01CD0 +#define DMA11_X_MODIFY 0xFFC01CD4 +#define DMA11_Y_COUNT 0xFFC01CD8 +#define DMA11_Y_MODIFY 0xFFC01CDC +#define DMA11_CURR_DESC_PTR 0xFFC01CE0 +#define DMA11_CURR_ADDR 0xFFC01CE4 +#define DMA11_IRQ_STATUS 0xFFC01CE8 +#define DMA11_PERIPHERAL_MAP 0xFFC01CEC +#define DMA11_CURR_X_COUNT 0xFFC01CF0 +#define DMA11_CURR_Y_COUNT 0xFFC01CF8 +#define DMA12_NEXT_DESC_PTR 0xFFC01D00 +#define DMA12_START_ADDR 0xFFC01D04 +#define DMA12_CONFIG 0xFFC01D08 +#define DMA12_X_COUNT 0xFFC01D10 +#define DMA12_X_MODIFY 0xFFC01D14 +#define DMA12_Y_COUNT 0xFFC01D18 +#define DMA12_Y_MODIFY 0xFFC01D1C +#define DMA12_CURR_DESC_PTR 0xFFC01D20 +#define DMA12_CURR_ADDR 0xFFC01D24 +#define DMA12_IRQ_STATUS 0xFFC01D28 +#define DMA12_PERIPHERAL_MAP 0xFFC01D2C +#define DMA12_CURR_X_COUNT 0xFFC01D30 +#define DMA12_CURR_Y_COUNT 0xFFC01D38 +#define DMA13_NEXT_DESC_PTR 0xFFC01D40 +#define DMA13_START_ADDR 0xFFC01D44 +#define DMA13_CONFIG 0xFFC01D48 +#define DMA13_X_COUNT 0xFFC01D50 +#define DMA13_X_MODIFY 0xFFC01D54 +#define DMA13_Y_COUNT 0xFFC01D58 +#define DMA13_Y_MODIFY 0xFFC01D5C +#define DMA13_CURR_DESC_PTR 0xFFC01D60 +#define DMA13_CURR_ADDR 0xFFC01D64 +#define DMA13_IRQ_STATUS 0xFFC01D68 +#define DMA13_PERIPHERAL_MAP 0xFFC01D6C +#define DMA13_CURR_X_COUNT 0xFFC01D70 +#define DMA13_CURR_Y_COUNT 0xFFC01D78 +#define DMA14_NEXT_DESC_PTR 0xFFC01D80 +#define DMA14_START_ADDR 0xFFC01D84 +#define DMA14_CONFIG 0xFFC01D88 +#define DMA14_X_COUNT 0xFFC01D90 +#define DMA14_X_MODIFY 0xFFC01D94 +#define DMA14_Y_COUNT 0xFFC01D98 +#define DMA14_Y_MODIFY 0xFFC01D9C +#define DMA14_CURR_DESC_PTR 0xFFC01DA0 +#define DMA14_CURR_ADDR 0xFFC01DA4 +#define DMA14_IRQ_STATUS 0xFFC01DA8 +#define DMA14_PERIPHERAL_MAP 0xFFC01DAC +#define DMA14_CURR_X_COUNT 0xFFC01DB0 +#define DMA14_CURR_Y_COUNT 0xFFC01DB8 +#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 +#define DMA15_START_ADDR 0xFFC01DC4 +#define DMA15_CONFIG 0xFFC01DC8 +#define DMA15_X_COUNT 0xFFC01DD0 +#define DMA15_X_MODIFY 0xFFC01DD4 +#define DMA15_Y_COUNT 0xFFC01DD8 +#define DMA15_Y_MODIFY 0xFFC01DDC +#define DMA15_CURR_DESC_PTR 0xFFC01DE0 +#define DMA15_CURR_ADDR 0xFFC01DE4 +#define DMA15_IRQ_STATUS 0xFFC01DE8 +#define DMA15_PERIPHERAL_MAP 0xFFC01DEC +#define DMA15_CURR_X_COUNT 0xFFC01DF0 +#define DMA15_CURR_Y_COUNT 0xFFC01DF8 +#define DMA16_NEXT_DESC_PTR 0xFFC01E00 +#define DMA16_START_ADDR 0xFFC01E04 +#define DMA16_CONFIG 0xFFC01E08 +#define DMA16_X_COUNT 0xFFC01E10 +#define DMA16_X_MODIFY 0xFFC01E14 +#define DMA16_Y_COUNT 0xFFC01E18 +#define DMA16_Y_MODIFY 0xFFC01E1C +#define DMA16_CURR_DESC_PTR 0xFFC01E20 +#define DMA16_CURR_ADDR 0xFFC01E24 +#define DMA16_IRQ_STATUS 0xFFC01E28 +#define DMA16_PERIPHERAL_MAP 0xFFC01E2C +#define DMA16_CURR_X_COUNT 0xFFC01E30 +#define DMA16_CURR_Y_COUNT 0xFFC01E38 +#define DMA17_NEXT_DESC_PTR 0xFFC01E40 +#define DMA17_START_ADDR 0xFFC01E44 +#define DMA17_CONFIG 0xFFC01E48 +#define DMA17_X_COUNT 0xFFC01E50 +#define DMA17_X_MODIFY 0xFFC01E54 +#define DMA17_Y_COUNT 0xFFC01E58 +#define DMA17_Y_MODIFY 0xFFC01E5C +#define DMA17_CURR_DESC_PTR 0xFFC01E60 +#define DMA17_CURR_ADDR 0xFFC01E64 +#define DMA17_IRQ_STATUS 0xFFC01E68 +#define DMA17_PERIPHERAL_MAP 0xFFC01E6C +#define DMA17_CURR_X_COUNT 0xFFC01E70 +#define DMA17_CURR_Y_COUNT 0xFFC01E78 +#define DMA18_NEXT_DESC_PTR 0xFFC01E80 +#define DMA18_START_ADDR 0xFFC01E84 +#define DMA18_CONFIG 0xFFC01E88 +#define DMA18_X_COUNT 0xFFC01E90 +#define DMA18_X_MODIFY 0xFFC01E94 +#define DMA18_Y_COUNT 0xFFC01E98 +#define DMA18_Y_MODIFY 0xFFC01E9C +#define DMA18_CURR_DESC_PTR 0xFFC01EA0 +#define DMA18_CURR_ADDR 0xFFC01EA4 +#define DMA18_IRQ_STATUS 0xFFC01EA8 +#define DMA18_PERIPHERAL_MAP 0xFFC01EAC +#define DMA18_CURR_X_COUNT 0xFFC01EB0 +#define DMA18_CURR_Y_COUNT 0xFFC01EB8 +#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 +#define DMA19_START_ADDR 0xFFC01EC4 +#define DMA19_CONFIG 0xFFC01EC8 +#define DMA19_X_COUNT 0xFFC01ED0 +#define DMA19_X_MODIFY 0xFFC01ED4 +#define DMA19_Y_COUNT 0xFFC01ED8 +#define DMA19_Y_MODIFY 0xFFC01EDC +#define DMA19_CURR_DESC_PTR 0xFFC01EE0 +#define DMA19_CURR_ADDR 0xFFC01EE4 +#define DMA19_IRQ_STATUS 0xFFC01EE8 +#define DMA19_PERIPHERAL_MAP 0xFFC01EEC +#define DMA19_CURR_X_COUNT 0xFFC01EF0 +#define DMA19_CURR_Y_COUNT 0xFFC01EF8 +#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 +#define MDMA0_D0_START_ADDR 0xFFC00E04 +#define MDMA0_D0_CONFIG 0xFFC00E08 +#define MDMA0_D0_X_COUNT 0xFFC00E10 +#define MDMA0_D0_X_MODIFY 0xFFC00E14 +#define MDMA0_D0_Y_COUNT 0xFFC00E18 +#define MDMA0_D0_Y_MODIFY 0xFFC00E1C +#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 +#define MDMA0_D0_CURR_ADDR 0xFFC00E24 +#define MDMA0_D0_IRQ_STATUS 0xFFC00E28 +#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C +#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 +#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 +#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 +#define MDMA0_S0_START_ADDR 0xFFC00E44 +#define MDMA0_S0_CONFIG 0xFFC00E48 +#define MDMA0_S0_X_COUNT 0xFFC00E50 +#define MDMA0_S0_X_MODIFY 0xFFC00E54 +#define MDMA0_S0_Y_COUNT 0xFFC00E58 +#define MDMA0_S0_Y_MODIFY 0xFFC00E5C +#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 +#define MDMA0_S0_CURR_ADDR 0xFFC00E64 +#define MDMA0_S0_IRQ_STATUS 0xFFC00E68 +#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C +#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 +#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 +#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 +#define MDMA0_D1_START_ADDR 0xFFC00E84 +#define MDMA0_D1_CONFIG 0xFFC00E88 +#define MDMA0_D1_X_COUNT 0xFFC00E90 +#define MDMA0_D1_X_MODIFY 0xFFC00E94 +#define MDMA0_D1_Y_COUNT 0xFFC00E98 +#define MDMA0_D1_Y_MODIFY 0xFFC00E9C +#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 +#define MDMA0_D1_CURR_ADDR 0xFFC00EA4 +#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 +#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC +#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 +#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 +#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 +#define MDMA0_S1_START_ADDR 0xFFC00EC4 +#define MDMA0_S1_CONFIG 0xFFC00EC8 +#define MDMA0_S1_X_COUNT 0xFFC00ED0 +#define MDMA0_S1_X_MODIFY 0xFFC00ED4 +#define MDMA0_S1_Y_COUNT 0xFFC00ED8 +#define MDMA0_S1_Y_MODIFY 0xFFC00EDC +#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 +#define MDMA0_S1_CURR_ADDR 0xFFC00EE4 +#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 +#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC +#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 +#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 +#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 +#define MDMA1_D0_START_ADDR 0xFFC01F04 +#define MDMA1_D0_CONFIG 0xFFC01F08 +#define MDMA1_D0_X_COUNT 0xFFC01F10 +#define MDMA1_D0_X_MODIFY 0xFFC01F14 +#define MDMA1_D0_Y_COUNT 0xFFC01F18 +#define MDMA1_D0_Y_MODIFY 0xFFC01F1C +#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 +#define MDMA1_D0_CURR_ADDR 0xFFC01F24 +#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 +#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C +#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 +#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 +#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 +#define MDMA1_S0_START_ADDR 0xFFC01F44 +#define MDMA1_S0_CONFIG 0xFFC01F48 +#define MDMA1_S0_X_COUNT 0xFFC01F50 +#define MDMA1_S0_X_MODIFY 0xFFC01F54 +#define MDMA1_S0_Y_COUNT 0xFFC01F58 +#define MDMA1_S0_Y_MODIFY 0xFFC01F5C +#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 +#define MDMA1_S0_CURR_ADDR 0xFFC01F64 +#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 +#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C +#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 +#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 +#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 +#define MDMA1_D1_START_ADDR 0xFFC01F84 +#define MDMA1_D1_CONFIG 0xFFC01F88 +#define MDMA1_D1_X_COUNT 0xFFC01F90 +#define MDMA1_D1_X_MODIFY 0xFFC01F94 +#define MDMA1_D1_Y_COUNT 0xFFC01F98 +#define MDMA1_D1_Y_MODIFY 0xFFC01F9C +#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 +#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 +#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 +#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC +#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 +#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 +#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 +#define MDMA1_S1_START_ADDR 0xFFC01FC4 +#define MDMA1_S1_CONFIG 0xFFC01FC8 +#define MDMA1_S1_X_COUNT 0xFFC01FD0 +#define MDMA1_S1_X_MODIFY 0xFFC01FD4 +#define MDMA1_S1_Y_COUNT 0xFFC01FD8 +#define MDMA1_S1_Y_MODIFY 0xFFC01FDC +#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 +#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 +#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 +#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC +#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 +#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 +#define PPI_CONTROL 0xFFC01000 +#define PPI_STATUS 0xFFC01004 +#define PPI_DELAY 0xFFC0100C +#define PPI_COUNT 0xFFC01008 +#define PPI_FRAME 0xFFC01010 +#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ +#define TWI0_CONTROL 0xFFC01404 /* TWIO Master Internal Time Reference Register */ +#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */ +#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ +#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ +#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ +#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ +#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ +#define TWI0_INT_STAT 0xFFC01420 /* TWIO Master Interrupt Register */ +#define TWI0_INT_MASK 0xFFC01424 /* TWIO Master Interrupt Mask Register */ +#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ +#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ +#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ +#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ +#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ +#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ +#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ +#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ +#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ +#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ +#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ +#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ +#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ +#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ +#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ +#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ +#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ +#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ +#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ +#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ +#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ +#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ +#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ +#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ +#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ +#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ +#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ +#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ +#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ +#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ +#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ +#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ +#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ +#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ +#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ +#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ +#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ +#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ +#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ +#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ +#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ +#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ +#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ +#define CAN_DEBUG 0xFFC02A88 /* Config register */ +#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ +#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ +#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ +#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ +#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ +#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ +#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ +#define CAN_VERSION 0xFFC02AA8 /* Version Code Register */ +#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ +#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ +#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ +#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */ +#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ +#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */ +#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ +#define CAN_VERSION2 0xFFC02AD4 /* Version Code Register 2 */ +#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ +#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ +#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ +#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ +#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ +#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ +#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ +#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ +#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ +#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ +#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ +#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ +#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ +#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ +#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ +#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ +#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ +#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ +#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ +#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ +#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ +#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ +#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ +#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ +#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ +#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ +#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ +#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ +#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ +#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ +#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ +#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ +#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ +#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ +#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ +#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ +#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ +#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ +#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ +#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ +#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ +#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ +#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ +#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ +#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ +#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ +#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ +#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ +#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ +#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ +#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ +#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ +#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ +#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ +#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ +#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ +#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ +#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ +#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ +#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ +#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ +#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ +#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ +#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ +#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ +#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ +#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ +#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ +#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ +#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ +#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ +#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ +#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ +#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ +#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ +#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ +#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ +#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ +#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ +#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ +#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ +#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ +#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ +#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ +#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ +#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ +#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ +#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ +#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ +#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ +#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ +#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ +#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ +#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ +#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ +#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ +#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ +#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ +#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ +#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ +#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ +#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ +#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ +#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ +#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ +#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ +#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ +#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ +#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ +#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ +#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ +#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ +#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ +#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ +#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ +#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ +#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ +#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ +#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ +#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ +#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ +#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ +#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ +#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ +#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ +#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ +#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ +#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ +#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ +#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ +#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ +#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ +#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ +#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ +#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ +#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ +#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ +#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ +#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ +#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ +#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ +#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ +#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ +#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ +#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ +#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ +#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ +#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ +#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ +#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ +#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ +#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ +#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ +#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ +#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ +#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ +#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ +#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ +#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ +#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ +#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ +#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ +#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ +#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ +#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ +#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ +#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ +#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ +#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ +#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ +#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ +#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ +#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ +#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ +#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ +#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ +#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ +#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ +#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ +#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ +#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ +#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ +#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ +#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ +#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ +#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ +#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ +#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ +#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ +#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ +#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ +#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ +#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ +#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ +#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ +#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ +#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ +#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ +#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ +#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ +#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ +#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ +#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ +#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ +#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ +#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ +#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ +#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ +#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ +#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ +#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ +#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ +#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ +#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ +#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ +#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ +#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ +#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ +#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ +#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ +#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ +#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ +#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ +#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ +#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ +#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ +#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ +#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ +#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ +#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ +#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ +#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ +#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ +#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ +#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ +#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ +#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ +#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ +#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ +#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ +#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ +#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ +#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ +#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ +#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ +#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ +#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ +#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ +#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ +#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ +#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ +#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ +#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ +#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ +#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ +#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ +#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ +#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ +#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ +#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ +#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ +#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ +#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ +#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ +#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ +#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ +#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ +#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ +#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ +#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ +#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ +#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ +#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ +#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ +#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ +#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ +#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ +#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ +#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ +#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ +#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ +#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ +#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ +#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ +#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ +#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ +#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ +#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ +#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ +#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ +#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ +#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ +#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ +#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ +#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ +#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ +#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ +#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ +#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ +#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ +#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ +#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ +#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ +#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ +#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ +#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ +#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ +#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ +#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ +#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ +#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ +#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ +#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ +#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ +#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ +#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ +#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ +#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ +#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ +#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ + +#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ +#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) +#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) +#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ +#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) +#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) +#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ +#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) +#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ +#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) +#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) +#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ +#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) +#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) + +#endif /* __BFIN_DEF_ADSP_BF538_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h b/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h new file mode 100644 index 0000000000..7e785b45c9 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/BF539_cdef.h @@ -0,0 +1 @@ +#include "BF538_cdef.h" diff --git a/arch/blackfin/include/asm/mach-bf538/BF539_def.h b/arch/blackfin/include/asm/mach-bf538/BF539_def.h new file mode 100644 index 0000000000..5a2ed8d16c --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/BF539_def.h @@ -0,0 +1 @@ +#include "BF538_def.h" diff --git a/arch/blackfin/include/asm/mach-bf538/anomaly.h b/arch/blackfin/include/asm/mach-bf538/anomaly.h new file mode 100644 index 0000000000..e22d23c174 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/anomaly.h @@ -0,0 +1,196 @@ +/* + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE + * + * Copyright 2004-2010 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd + */ + +/* This file should be up to date with: + * - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List + * - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List + */ + +#ifndef _MACH_ANOMALY_H_ +#define _MACH_ANOMALY_H_ + +/* We do not support old silicon - sorry */ +#if __SILICON_REVISION__ < 4 +# error will not work on BF538/BF539 silicon version 0.0, 0.1, 0.2, or 0.3 +#endif + +#if defined(__ADSPBF538__) +# define ANOMALY_BF538 1 +#else +# define ANOMALY_BF538 0 +#endif +#if defined(__ADSPBF539__) +# define ANOMALY_BF539 1 +#else +# define ANOMALY_BF539 0 +#endif + +/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ +#define ANOMALY_05000074 (1) +/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ +#define ANOMALY_05000119 (1) +/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ +#define ANOMALY_05000122 (1) +/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ +#define ANOMALY_05000166 (1) +/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ +#define ANOMALY_05000179 (1) +/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ +#define ANOMALY_05000180 (1) +/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ +#define ANOMALY_05000193 (1) +/* Current DMA Address Shows Wrong Value During Carry Fix */ +#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) +/* NMI Event at Boot Time Results in Unpredictable State */ +#define ANOMALY_05000219 (1) +/* SPI Slave Boot Mode Modifies Registers from Reset Value */ +#define ANOMALY_05000229 (1) +/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ +#define ANOMALY_05000233 (1) +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) +/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ +#define ANOMALY_05000245 (1) +/* Maximum External Clock Speed for Timers */ +#define ANOMALY_05000253 (1) +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) +/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ +#define ANOMALY_05000270 (__SILICON_REVISION__ < 4) +/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ +#define ANOMALY_05000272 (1) +/* Writes to Synchronous SDRAM Memory May Be Lost */ +#define ANOMALY_05000273 (__SILICON_REVISION__ < 4) +/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ +#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) +/* Disabling Peripherals with DMA Running May Cause DMA System Instability */ +#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) +/* False Hardware Error Exception when ISR Context Is Not Restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) +/* Memory DMA Corruption with 32-Bit Data and Traffic Control */ +#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) +/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ +#define ANOMALY_05000283 (__SILICON_REVISION__ < 4) +/* SPORTs May Receive Bad Data If FIFOs Fill Up */ +#define ANOMALY_05000288 (__SILICON_REVISION__ < 4) +/* Reads from CAN Mailbox and Acceptance Mask Area Can Fail */ +#define ANOMALY_05000291 (__SILICON_REVISION__ < 4) +/* Hibernate Leakage Current Is Higher Than Specified */ +#define ANOMALY_05000293 (__SILICON_REVISION__ < 4) +/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */ +#define ANOMALY_05000294 (1) +/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ +#define ANOMALY_05000301 (__SILICON_REVISION__ < 4) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (__SILICON_REVISION__ < 4) +/* SCKELOW Bit Does Not Maintain State Through Hibernate */ +#define ANOMALY_05000307 (__SILICON_REVISION__ < 4) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (__SILICON_REVISION__ < 5) +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ +#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) +/* Killed System MMR Write Completes Erroneously on Next System MMR Access */ +#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) +/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ +#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (__SILICON_REVISION__ < 5) +/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ +#define ANOMALY_05000357 (__SILICON_REVISION__ < 5) +/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ +#define ANOMALY_05000366 (1) +/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ +#define ANOMALY_05000371 (__SILICON_REVISION__ < 5) +/* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */ +#define ANOMALY_05000374 (__SILICON_REVISION__ == 4) +/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ +#define ANOMALY_05000375 (__SILICON_REVISION__ < 4) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 3) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* Specific GPIO Pins May Change State when Entering Hibernate */ +#define ANOMALY_05000436 (__SILICON_REVISION__ > 3) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) +/* False Hardware Error when RETI Points to Invalid Memory */ +#define ANOMALY_05000461 (1) +/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ +#define ANOMALY_05000462 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Possible Lockup Condition whem Modifying PLL from External Memory */ +#define ANOMALY_05000475 (1) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) +/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ +#define ANOMALY_05000481 (1) + +/* Anomalies that don't exist on this proc */ +#define ANOMALY_05000099 (0) +#define ANOMALY_05000120 (0) +#define ANOMALY_05000125 (0) +#define ANOMALY_05000149 (0) +#define ANOMALY_05000158 (0) +#define ANOMALY_05000171 (0) +#define ANOMALY_05000182 (0) +#define ANOMALY_05000189 (0) +#define ANOMALY_05000198 (0) +#define ANOMALY_05000202 (0) +#define ANOMALY_05000215 (0) +#define ANOMALY_05000220 (0) +#define ANOMALY_05000227 (0) +#define ANOMALY_05000230 (0) +#define ANOMALY_05000231 (0) +#define ANOMALY_05000234 (0) +#define ANOMALY_05000242 (0) +#define ANOMALY_05000248 (0) +#define ANOMALY_05000250 (0) +#define ANOMALY_05000254 (0) +#define ANOMALY_05000257 (0) +#define ANOMALY_05000263 (0) +#define ANOMALY_05000266 (0) +#define ANOMALY_05000274 (0) +#define ANOMALY_05000287 (0) +#define ANOMALY_05000305 (0) +#define ANOMALY_05000311 (0) +#define ANOMALY_05000323 (0) +#define ANOMALY_05000353 (1) +#define ANOMALY_05000362 (1) +#define ANOMALY_05000363 (0) +#define ANOMALY_05000364 (0) +#define ANOMALY_05000380 (0) +#define ANOMALY_05000386 (1) +#define ANOMALY_05000389 (0) +#define ANOMALY_05000400 (0) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000430 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) +#define ANOMALY_05000447 (0) +#define ANOMALY_05000448 (0) +#define ANOMALY_05000456 (0) +#define ANOMALY_05000450 (0) +#define ANOMALY_05000465 (0) +#define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) +#define ANOMALY_05000485 (0) + +#endif diff --git a/arch/blackfin/include/asm/mach-bf538/def_local.h b/arch/blackfin/include/asm/mach-bf538/def_local.h new file mode 100644 index 0000000000..54d8e76151 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/def_local.h @@ -0,0 +1,5 @@ +#include "gpio.h" +#include "portmux.h" +#include "ports.h" + +#define BF538_FAMILY 1 /* Linux glue */ diff --git a/arch/blackfin/include/asm/mach-bf538/gpio.h b/arch/blackfin/include/asm/mach-bf538/gpio.h new file mode 100644 index 0000000000..bd9adb7183 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/gpio.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2008-2009 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + + +#ifndef _MACH_GPIO_H_ +#define _MACH_GPIO_H_ + +#define MAX_BLACKFIN_GPIOS 16 +#define BFIN_SPECIAL_GPIO_BANKS 3 + +#define GPIO_PF0 0 /* PF */ +#define GPIO_PF1 1 +#define GPIO_PF2 2 +#define GPIO_PF3 3 +#define GPIO_PF4 4 +#define GPIO_PF5 5 +#define GPIO_PF6 6 +#define GPIO_PF7 7 +#define GPIO_PF8 8 +#define GPIO_PF9 9 +#define GPIO_PF10 10 +#define GPIO_PF11 11 +#define GPIO_PF12 12 +#define GPIO_PF13 13 +#define GPIO_PF14 14 +#define GPIO_PF15 15 +#define GPIO_PC0 16 /* PC */ +#define GPIO_PC1 17 +#define GPIO_PC4 20 +#define GPIO_PC5 21 +#define GPIO_PC6 22 +#define GPIO_PC7 23 +#define GPIO_PC8 24 +#define GPIO_PC9 25 +#define GPIO_PD0 32 /* PD */ +#define GPIO_PD1 33 +#define GPIO_PD2 34 +#define GPIO_PD3 35 +#define GPIO_PD4 36 +#define GPIO_PD5 37 +#define GPIO_PD6 38 +#define GPIO_PD7 39 +#define GPIO_PD8 40 +#define GPIO_PD9 41 +#define GPIO_PD10 42 +#define GPIO_PD11 43 +#define GPIO_PD12 44 +#define GPIO_PD13 45 +#define GPIO_PE0 48 /* PE */ +#define GPIO_PE1 49 +#define GPIO_PE2 50 +#define GPIO_PE3 51 +#define GPIO_PE4 52 +#define GPIO_PE5 53 +#define GPIO_PE6 54 +#define GPIO_PE7 55 +#define GPIO_PE8 56 +#define GPIO_PE9 57 +#define GPIO_PE10 58 +#define GPIO_PE11 59 +#define GPIO_PE12 60 +#define GPIO_PE13 61 +#define GPIO_PE14 62 +#define GPIO_PE15 63 + +#define PORT_F GPIO_PF0 +#define PORT_C GPIO_PC0 +#define PORT_D GPIO_PD0 +#define PORT_E GPIO_PE0 + +#endif /* _MACH_GPIO_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf538/portmux.h b/arch/blackfin/include/asm/mach-bf538/portmux.h new file mode 100644 index 0000000000..b773c5fdbc --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/portmux.h @@ -0,0 +1,114 @@ +/* + * Copyright 2008-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _MACH_PORTMUX_H_ +#define _MACH_PORTMUX_H_ + +#define MAX_RESOURCES 64 + +#define P_TMR2 (P_DONTCARE) +#define P_TMR1 (P_DONTCARE) +#define P_TMR0 (P_DONTCARE) +#define P_TMRCLK (P_DONTCARE) +#define P_PPI0_CLK (P_DONTCARE) +#define P_PPI0_FS1 (P_DONTCARE) +#define P_PPI0_FS2 (P_DONTCARE) + +#define P_TWI0_SCL (P_DONTCARE) +#define P_TWI0_SDA (P_DONTCARE) +#define P_TWI1_SCL (P_DONTCARE) +#define P_TWI1_SDA (P_DONTCARE) + +#define P_SPORT1_TSCLK (P_DONTCARE) +#define P_SPORT1_RSCLK (P_DONTCARE) +#define P_SPORT0_TSCLK (P_DONTCARE) +#define P_SPORT0_RSCLK (P_DONTCARE) +#define P_SPORT1_DRSEC (P_DONTCARE) +#define P_SPORT1_RFS (P_DONTCARE) +#define P_SPORT1_DTPRI (P_DONTCARE) +#define P_SPORT1_DTSEC (P_DONTCARE) +#define P_SPORT1_TFS (P_DONTCARE) +#define P_SPORT1_DRPRI (P_DONTCARE) +#define P_SPORT0_DRSEC (P_DONTCARE) +#define P_SPORT0_RFS (P_DONTCARE) +#define P_SPORT0_DTPRI (P_DONTCARE) +#define P_SPORT0_DTSEC (P_DONTCARE) +#define P_SPORT0_TFS (P_DONTCARE) +#define P_SPORT0_DRPRI (P_DONTCARE) + +#define P_UART0_RX (P_DONTCARE) +#define P_UART0_TX (P_DONTCARE) + +#define P_SPI0_MOSI (P_DONTCARE) +#define P_SPI0_MISO (P_DONTCARE) +#define P_SPI0_SCK (P_DONTCARE) + +#define P_PPI0_D0 (P_DONTCARE) +#define P_PPI0_D1 (P_DONTCARE) +#define P_PPI0_D2 (P_DONTCARE) +#define P_PPI0_D3 (P_DONTCARE) + +#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PC0)) +#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PC1)) + +#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD0)) +#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD1)) +#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD2)) +#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD3)) +#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD4)) +#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PD5)) +#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PD6)) +#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PD7)) +#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PD8)) +#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD9)) +#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PD10)) +#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PD11)) +#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PD12)) +#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PD13)) + +#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PE0)) +#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PE1)) +#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PE2)) +#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PE3)) +#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PE4)) +#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PE5)) +#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PE6)) +#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PE7)) +#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PE8)) +#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PE9)) +#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PE10)) +#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PE11)) +#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PE12)) +#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PE13)) +#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PE14)) +#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PE15)) + +#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) +#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) +#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) +#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) + +#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) +#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) +#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) +#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) +#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) +#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) +#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) +#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) +#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) +#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) +#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) +#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) +#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 +#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 + +#endif /* _MACH_PORTMUX_H_ */ diff --git a/arch/blackfin/include/asm/mach-bf538/ports.h b/arch/blackfin/include/asm/mach-bf538/ports.h new file mode 100644 index 0000000000..4ae09f0582 --- /dev/null +++ b/arch/blackfin/include/asm/mach-bf538/ports.h @@ -0,0 +1,13 @@ +/* + * Port Masks + */ + +#ifndef __BFIN_PERIPHERAL_PORT__ +#define __BFIN_PERIPHERAL_PORT__ + +#include "../mach-common/bits/ports-c.h" +#include "../mach-common/bits/ports-d.h" +#include "../mach-common/bits/ports-e.h" +#include "../mach-common/bits/ports-f.h" + +#endif diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h index 51d9cf240a..84fa5d2dfb 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_cdef.h @@ -6,4372 +6,2907 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__ #define __BFIN_CDEF_ADSP_EDN_BF542_extended__ -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ #define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) #define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ #define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) #define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ #define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) #define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ #define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) #define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ #define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ #define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ #define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ #define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ #define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ #define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ #define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ #define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ #define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ #define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ #define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ #define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ #define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ #define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ #define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ #define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ #define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ #define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ #define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ #define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ #define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ #define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ #define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ #define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ #define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ #define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ #define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ #define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ #define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) #define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ #define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ #define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ #define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) #define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ #define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ #define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ #define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ #define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ #define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) #define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ #define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ #define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ #define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ #define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ #define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ #define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ #define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ #define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ #define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ #define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ #define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ #define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ #define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ #define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ #define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ #define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ #define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ #define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ #define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ #define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ #define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ #define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) #define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ #define bfin_read_PORTA() bfin_read16(PORTA) #define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ #define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) #define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) #define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) #define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) #define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ #define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) #define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ #define bfin_read_PORTB() bfin_read16(PORTB) #define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ #define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) #define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) #define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) #define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) #define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ #define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) #define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ #define bfin_read_PORTC() bfin_read16(PORTC) #define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ #define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) #define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) #define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) #define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) #define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ #define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) #define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ #define bfin_read_PORTD() bfin_read16(PORTD) #define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ #define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) #define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) #define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) #define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) #define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ #define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) #define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ #define bfin_read_PORTE() bfin_read16(PORTE) #define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ #define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) #define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) #define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) #define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) #define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ #define bfin_read_PORTF() bfin_read16(PORTF) #define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ #define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) #define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) #define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) #define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) #define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ #define bfin_read_PORTG() bfin_read16(PORTG) #define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ #define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) #define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) #define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) #define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) #define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ #define bfin_read_PORTH() bfin_read16(PORTH) #define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ #define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) #define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) #define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) #define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) #define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ #define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) #define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ #define bfin_read_PORTI() bfin_read16(PORTI) #define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ #define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) #define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) #define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) #define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) #define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ #define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) #define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ #define bfin_read_PORTJ() bfin_read16(PORTJ) #define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ #define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) #define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) #define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) #define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) #define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ #define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ #define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ #define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) #define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ #define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ #define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ #define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ #define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ #define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ #define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ #define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ #define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ #define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) #define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ #define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ #define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ #define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ #define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ #define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ #define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ #define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ #define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ #define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) #define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ #define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ #define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ #define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ #define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ #define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ #define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ #define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ #define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ #define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) #define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ #define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ #define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ #define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ #define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ #define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ #define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ #define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) #define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ #define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ #define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ #define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) #define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ #define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) #define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ #define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) #define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ #define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) #define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ #define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) #define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ #define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) #define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ #define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) #define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ #define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) #define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ #define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ #define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) #define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ #define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) #define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ #define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ #define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ #define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ #define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ #define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ #define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ #define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ #define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ #define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ #define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ #define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ #define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ #define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) #define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ #define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ #define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) #define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ #define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) #define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ #define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) #define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ #define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ #define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) #define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ #define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) #define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ #define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) #define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ #define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) #define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ #define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) #define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ #define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) #define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ #define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) #define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ #define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) #define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ #define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ #define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ #define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ #define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ #define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ #define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ #define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ #define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ #define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ #define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ #define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ #define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ #define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ #define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ #define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ #define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ #define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ #define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ #define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ #define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ #define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ #define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ #define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ #define bfin_read_NFC_RST() bfin_read16(NFC_RST) #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ #define bfin_read_NFC_READ() bfin_read16(NFC_READ) #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ #define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) #define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ #define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) #define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ #define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) #define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ #define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) #define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ #define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) #define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ #define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) #define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ #define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) #define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ #define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) #define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ #define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ #define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ #define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ #define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ #define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ #define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) #define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ #define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) #define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ #define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) #define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ #define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) #define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ #define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) #define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ #define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) #define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ #define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) #define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ #define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) #define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ #define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ #define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ #define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ #define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ #define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ #define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ #define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ #define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ #define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ #define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ #define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ #define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ #define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ #define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ #define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ #define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ #define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ #define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ #define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ #define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ #define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ #define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ #define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ #define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ #define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ #define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ #define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ #define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ #define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ #define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ #define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ #define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ #define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ #define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ #define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ #define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ #define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ #define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ #define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ #define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ #define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ #define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ #define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ #define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ #define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ #define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ #define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ #define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ #define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ #define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ #define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ #define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ #define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ #define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ #define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ #define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ #define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ #define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ #define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ #define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ #define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ #define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ #define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ #define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ #define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ #define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ #define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ #define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ #define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ #define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ #define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ #define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ #define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ #define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ #define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ #define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ #define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ #define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ #define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ #define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ #define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ #define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ #define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ #define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ #define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ #define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ #define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ #define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ #define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ #define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ #define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ #define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ #define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ #define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ #define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ #define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ #define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ #define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ #define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ #define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ #define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ #define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ #define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ #define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ #define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ #define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ #define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ #define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ #define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ #define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ #define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ #define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ #define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ #define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ #define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ #define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ #define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ #define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ #define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ #define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ #define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ #define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ #define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ #define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ #define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ #define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ #define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ #define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ #define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ #define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ #define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ #define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ #define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ #define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ #define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ #define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ #define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ #define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ #define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ #define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ #define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ #define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ #define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ #define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ #define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ #define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ #define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ #define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ #define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ #define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ #define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ #define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ #define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ #define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ #define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ #define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ #define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ #define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ #define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ #define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ #define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ #define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ #define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ #define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ #define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ #define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ #define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ #define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ #define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ #define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ #define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ #define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ #define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ #define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ #define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ #define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ #define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ #define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ #define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ #define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ #define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ #define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ #define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ #define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ #define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ #define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ #define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ #define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ #define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ #define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ #define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ #define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ #define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ #define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ #define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ #define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ #define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ #define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ #define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ #define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ #define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ #define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ #define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ #define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ #define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ #define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ #define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ #define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ #define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ #define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ #define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ #define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ #define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ #define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ #define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ #define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ #define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ #define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ #define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ #define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ #define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ #define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ #define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ #define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ #define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ #define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ #define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ #define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ #define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ #define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ #define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ #define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ #define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ #define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ #define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ #define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ #define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ #define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ #define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ #define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ #define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ #define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ #define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ #define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ #define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ #define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ #define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ #define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ #define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ #define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ #define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ #define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ #define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ #define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ #define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ #define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ #define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ #define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ #define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ #define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ #define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ #define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ #define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ #define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ #define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ #define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ #define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ #define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ #define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ #define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ #define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ #define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ #define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ #define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ #define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ #define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ #define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ #define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ #define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ #define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ #define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ #define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ #define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ #define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ #define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ #define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ #define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ #define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ #define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ #define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ #define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ #define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ #define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ #define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ #define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ #define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ #define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ #define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ #define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ #define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ #define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ #define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ #define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ #define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ #define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ #define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ #define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ #define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ #define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ #define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ #define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ #define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ #define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ #define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ #define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ #define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ #define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ #define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ #define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ #define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ #define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ #define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ #define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) #define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ #define bfin_read_UART1_THR() bfin_read16(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) #define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) #define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ #define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) #define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ #define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) #define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ #define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) #define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ #define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) #define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ #define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) #define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ #define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) #define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) #define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ #define bfin_read_UART3_THR() bfin_read16(UART3_THR) #define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ #define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) #define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ #define bfin_read_USB_POWER() bfin_read16(USB_POWER) #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ #define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ #define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ #define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ #define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ #define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ #define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ #define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ #define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h index f294a850ab..d94744d1e4 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF542-extended_def.h @@ -657,10 +657,6 @@ #define TIMER_ENABLE0 0xFFC01680 /* Timer Group of 8 Enable Register */ #define TIMER_DISABLE0 0xFFC01684 /* Timer Group of 8 Disable Register */ #define TIMER_STATUS0 0xFFC01688 /* Timer Group of 8 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h index 4c0fdf52bf..517e14309e 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h @@ -6,4966 +6,3303 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__ #define __BFIN_CDEF_ADSP_EDN_BF544_extended__ -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ #define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) #define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ #define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) #define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ #define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) #define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ #define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) #define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ #define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ #define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ #define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ #define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ #define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ #define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ #define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ #define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ #define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ #define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ #define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ #define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ #define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ #define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ #define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ #define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ #define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ #define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ #define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ #define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ #define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ #define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ #define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ #define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ #define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ #define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ #define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ #define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ #define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) #define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ #define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ #define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ #define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) #define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ #define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ #define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ #define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ #define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ #define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) #define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ #define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ #define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ #define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ #define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ #define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ #define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ #define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ #define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ #define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ #define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ #define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ #define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ #define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ #define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ #define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ #define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ #define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ #define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ #define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ #define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ #define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ #define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) #define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ #define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) #define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ #define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) #define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) #define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) #define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) #define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) #define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ #define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) #define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) #define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) #define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) #define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) #define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ #define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) #define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ #define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) #define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ #define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) #define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ #define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) #define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ #define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) #define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ #define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) #define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ #define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) #define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ #define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) #define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ #define bfin_read_PORTA() bfin_read16(PORTA) #define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ #define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) #define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) #define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) #define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) #define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ #define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) #define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ #define bfin_read_PORTB() bfin_read16(PORTB) #define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ #define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) #define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) #define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) #define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) #define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ #define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) #define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ #define bfin_read_PORTC() bfin_read16(PORTC) #define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ #define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) #define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) #define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) #define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) #define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ #define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) #define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ #define bfin_read_PORTD() bfin_read16(PORTD) #define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ #define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) #define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) #define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) #define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) #define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ #define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) #define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ #define bfin_read_PORTE() bfin_read16(PORTE) #define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ #define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) #define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) #define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) #define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) #define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ #define bfin_read_PORTF() bfin_read16(PORTF) #define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ #define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) #define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) #define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) #define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) #define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ #define bfin_read_PORTG() bfin_read16(PORTG) #define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ #define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) #define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) #define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) #define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) #define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ #define bfin_read_PORTH() bfin_read16(PORTH) #define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ #define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) #define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) #define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) #define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) #define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ #define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) #define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ #define bfin_read_PORTI() bfin_read16(PORTI) #define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ #define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) #define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) #define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) #define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) #define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ #define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) #define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ #define bfin_read_PORTJ() bfin_read16(PORTJ) #define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ #define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) #define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) #define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) #define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) #define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ #define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ #define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ #define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) #define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ #define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ #define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ #define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ #define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ #define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ #define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ #define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ #define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ #define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) #define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ #define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ #define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ #define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ #define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ #define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ #define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ #define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ #define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ #define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) #define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ #define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ #define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ #define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ #define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ #define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ #define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ #define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ #define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ #define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) #define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ #define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ #define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ #define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ #define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ #define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ #define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ #define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ #define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ #define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ #define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) #define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ #define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ #define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ #define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ #define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ #define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ #define bfin_read_NFC_RST() bfin_read16(NFC_RST) #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ #define bfin_read_NFC_READ() bfin_read16(NFC_READ) #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ #define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ #define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ #define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ #define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ #define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ #define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) #define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ #define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) #define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ #define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) #define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ #define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ #define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ #define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ #define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) #define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ #define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) #define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ #define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) #define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ #define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) #define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ #define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) #define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ #define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) #define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ #define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) #define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ #define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) #define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ #define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) #define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ #define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ #define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ #define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ #define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ #define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ #define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) #define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ #define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) #define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ #define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) #define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ #define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) #define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ #define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) #define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ #define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) #define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ #define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) #define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ #define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) #define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ #define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ #define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ #define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ #define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ #define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ #define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ #define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ #define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ #define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ #define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ #define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ #define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ #define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ #define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ #define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ #define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ #define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ #define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ #define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ #define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ #define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ #define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ #define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ #define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ #define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ #define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ #define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ #define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ #define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ #define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ #define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ #define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ #define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ #define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ #define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ #define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ #define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ #define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ #define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ #define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ #define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ #define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ #define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ #define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ #define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ #define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ #define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ #define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ #define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ #define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ #define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ #define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ #define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ #define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ #define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ #define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ #define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ #define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ #define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ #define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ #define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ #define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ #define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ #define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ #define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ #define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ #define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ #define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ #define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ #define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ #define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ #define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ #define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ #define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ #define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ #define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ #define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ #define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ #define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ #define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ #define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ #define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ #define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ #define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ #define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ #define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ #define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ #define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ #define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ #define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ #define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ #define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ #define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ #define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ #define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ #define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ #define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ #define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ #define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ #define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ #define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ #define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ #define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ #define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ #define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ #define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ #define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ #define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ #define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ #define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ #define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ #define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ #define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ #define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ #define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ #define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ #define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ #define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ #define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ #define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ #define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ #define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ #define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ #define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ #define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ #define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ #define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ #define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ #define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ #define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ #define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ #define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ #define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ #define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ #define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ #define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ #define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ #define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ #define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ #define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ #define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ #define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ #define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ #define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ #define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ #define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ #define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ #define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ #define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ #define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ #define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ #define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ #define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ #define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ #define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ #define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ #define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ #define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ #define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ #define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ #define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ #define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ #define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ #define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ #define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ #define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ #define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ #define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ #define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ #define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ #define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ #define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ #define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ #define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ #define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ #define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ #define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ #define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ #define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ #define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ #define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ #define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ #define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ #define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ #define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ #define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ #define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ #define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ #define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ #define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ #define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ #define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ #define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ #define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ #define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ #define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ #define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ #define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ #define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ #define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ #define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ #define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ #define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ #define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ #define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ #define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ #define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ #define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ #define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ #define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ #define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ #define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ #define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ #define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ #define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ #define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ #define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ #define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ #define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ #define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ #define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ #define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ #define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ #define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ #define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ #define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ #define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ #define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ #define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ #define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ #define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ #define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ #define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ #define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ #define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ #define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ #define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ #define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ #define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ #define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ #define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ #define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ #define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ #define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ #define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ #define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ #define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ #define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ #define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ #define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ #define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ #define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ #define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ #define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ #define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ #define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ #define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ #define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ #define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ #define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ #define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ #define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ #define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ #define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ #define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ #define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ #define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ #define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ #define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ #define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ #define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ #define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ #define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ #define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ #define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ #define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ #define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ #define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ #define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ #define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ #define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ #define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ #define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ #define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ #define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ #define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ #define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ #define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ #define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ #define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ #define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ #define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ #define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ #define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ #define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ #define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ #define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ #define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ #define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */ #define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */ #define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */ #define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */ #define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */ #define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */ #define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) #define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */ #define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) #define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */ #define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) #define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ #define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) #define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ #define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) #define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ #define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) #define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ #define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) #define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ #define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) #define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) -#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */ #define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) #define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */ #define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) #define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */ #define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) #define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */ #define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) #define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */ #define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) #define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */ #define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) #define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */ #define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) #define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */ #define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) #define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ #define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) #define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ #define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) #define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ #define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) #define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ #define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) #define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ #define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) #define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) -#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */ #define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) #define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */ #define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) #define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */ #define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) #define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */ #define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) #define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */ #define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) #define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */ #define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) #define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */ #define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) #define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */ #define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) #define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */ #define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) #define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */ #define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) #define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */ #define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) #define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */ #define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) #define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */ #define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) #define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */ #define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) #define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */ #define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) #define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */ #define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) #define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) -#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ #define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) #define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) #define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ #define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) #define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) #define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ #define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) #define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) #define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ #define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) #define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) #define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ #define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) #define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) #define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ #define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) #define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) #define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ #define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) #define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) #define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ #define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) #define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) #define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ #define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) #define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) #define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ #define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) #define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) #define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ #define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) #define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) #define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ #define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) #define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) #define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ #define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) #define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) #define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ #define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) #define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) #define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ #define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) #define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) #define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ #define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) #define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) #define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) -#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ #define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) #define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) #define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ #define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) #define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) #define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ #define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) #define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) #define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ #define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) #define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) #define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ #define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) #define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) #define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ #define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) #define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) #define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ #define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) #define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) #define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ #define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) #define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) #define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ #define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) #define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) #define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ #define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) #define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) #define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ #define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) #define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) #define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ #define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) #define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) #define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ #define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) #define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) #define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ #define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) #define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) #define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ #define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) #define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) #define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ #define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) #define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) #define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) -#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */ #define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */ #define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */ #define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */ #define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */ #define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */ #define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */ #define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) #define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */ #define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) #define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */ #define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */ #define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */ #define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */ #define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */ #define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */ #define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */ #define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) #define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */ #define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) #define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */ #define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */ #define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */ #define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */ #define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */ #define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */ #define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */ #define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) #define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */ #define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) #define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */ #define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */ #define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */ #define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */ #define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */ #define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */ #define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */ #define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) #define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */ #define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) #define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */ #define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */ #define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */ #define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */ #define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */ #define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */ #define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */ #define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) #define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */ #define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) #define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */ #define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */ #define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */ #define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */ #define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */ #define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */ #define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */ #define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) #define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */ #define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) #define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */ #define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */ #define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */ #define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */ #define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */ #define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */ #define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */ #define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) #define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */ #define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) #define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */ #define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */ #define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */ #define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */ #define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */ #define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */ #define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */ #define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) #define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */ #define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) #define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */ #define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */ #define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */ #define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */ #define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */ #define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */ #define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */ #define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) #define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */ #define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) #define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */ #define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */ #define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */ #define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */ #define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */ #define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */ #define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */ #define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) #define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */ #define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) #define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */ #define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */ #define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */ #define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */ #define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */ #define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */ #define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */ #define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) #define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */ #define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) #define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */ #define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */ #define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */ #define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */ #define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */ #define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */ #define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */ #define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) #define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */ #define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) #define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */ #define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */ #define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */ #define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */ #define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */ #define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */ #define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */ #define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) #define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */ #define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) #define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */ #define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */ #define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */ #define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */ #define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */ #define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */ #define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */ #define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) #define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */ #define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) #define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */ #define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */ #define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */ #define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */ #define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */ #define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */ #define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */ #define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) #define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */ #define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) #define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */ #define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */ #define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */ #define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */ #define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */ #define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */ #define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */ #define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) #define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */ #define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) #define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) -#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */ #define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */ #define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */ #define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */ #define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */ #define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */ #define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */ #define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) #define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */ #define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) #define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */ #define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */ #define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */ #define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */ #define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */ #define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */ #define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */ #define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) #define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */ #define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) #define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */ #define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */ #define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */ #define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */ #define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */ #define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */ #define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */ #define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) #define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */ #define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) #define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */ #define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */ #define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */ #define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */ #define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */ #define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */ #define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */ #define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) #define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */ #define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) #define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */ #define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */ #define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */ #define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */ #define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */ #define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */ #define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */ #define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) #define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */ #define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) #define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */ #define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */ #define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */ #define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */ #define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */ #define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */ #define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */ #define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) #define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */ #define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) #define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */ #define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */ #define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */ #define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */ #define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */ #define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */ #define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */ #define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) #define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */ #define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) #define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */ #define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */ #define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */ #define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */ #define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */ #define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */ #define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */ #define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) #define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */ #define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) #define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */ #define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */ #define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */ #define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */ #define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */ #define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */ #define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */ #define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) #define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */ #define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) #define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */ #define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */ #define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */ #define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */ #define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */ #define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */ #define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */ #define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) #define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */ #define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) #define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */ #define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */ #define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */ #define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */ #define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */ #define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */ #define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */ #define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) #define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */ #define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) #define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */ #define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */ #define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */ #define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */ #define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */ #define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */ #define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */ #define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) #define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */ #define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) #define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */ #define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */ #define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */ #define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */ #define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */ #define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */ #define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */ #define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) #define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */ #define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) #define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */ #define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */ #define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */ #define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */ #define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */ #define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */ #define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */ #define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) #define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */ #define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) #define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */ #define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */ #define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */ #define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */ #define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */ #define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */ #define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */ #define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) #define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */ #define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) #define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */ #define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */ #define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */ #define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */ #define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */ #define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */ #define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */ #define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) #define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */ #define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) #define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ #define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ #define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ #define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ #define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ #define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ #define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) #define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ #define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ #define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ #define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ #define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ #define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ #define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ #define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ #define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ #define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ #define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ #define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ #define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ #define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ #define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ #define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ #define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ #define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ #define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) #define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ #define bfin_read_UART1_THR() bfin_read16(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) #define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) #define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ #define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) #define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ #define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) #define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ #define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) #define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ #define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) #define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ #define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) #define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ #define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) #define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) #define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ #define bfin_read_UART3_THR() bfin_read16(UART3_THR) #define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ #define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) #define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h index 3c14d22d56..4b4f67d955 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_def.h @@ -694,10 +694,6 @@ #define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ #define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ #define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h index e0f76ae1ef..7e0c043b1c 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_cdef.h @@ -6,3609 +6,2398 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF547_extended__ #define __BFIN_CDEF_ADSP_EDN_BF547_extended__ -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ #define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) #define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ #define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) #define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ #define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) #define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ #define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) #define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ #define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ #define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ #define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ #define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ #define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ #define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ #define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ #define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ #define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ #define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ #define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ #define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ #define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ #define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ #define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ #define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ #define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ #define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ #define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ #define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ #define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ #define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ #define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ #define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ #define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ #define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ #define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ #define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ #define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) #define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ #define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ #define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ #define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) #define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ #define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ #define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ #define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ #define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ #define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) #define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ #define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ #define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ #define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ #define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ #define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ #define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ #define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ #define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ #define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ #define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ #define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ #define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ #define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ #define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ #define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ #define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ #define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ #define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ #define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ #define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ #define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ #define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) #define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ #define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) #define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ #define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) #define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) #define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) #define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) #define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) #define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ #define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) #define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) #define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) #define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) #define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) #define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ #define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) #define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ #define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) #define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ #define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) #define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ #define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) #define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ #define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) #define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ #define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) #define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ #define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) #define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ #define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) #define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ #define bfin_read_PORTA() bfin_read16(PORTA) #define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ #define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) #define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) #define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) #define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) #define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ #define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) #define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ #define bfin_read_PORTB() bfin_read16(PORTB) #define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ #define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) #define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) #define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) #define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) #define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ #define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) #define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ #define bfin_read_PORTC() bfin_read16(PORTC) #define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ #define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) #define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) #define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) #define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) #define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ #define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) #define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ #define bfin_read_PORTD() bfin_read16(PORTD) #define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ #define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) #define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) #define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) #define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) #define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ #define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) #define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ #define bfin_read_PORTE() bfin_read16(PORTE) #define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ #define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) #define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) #define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) #define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) #define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ #define bfin_read_PORTF() bfin_read16(PORTF) #define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ #define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) #define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) #define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) #define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) #define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ #define bfin_read_PORTG() bfin_read16(PORTG) #define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ #define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) #define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) #define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) #define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) #define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ #define bfin_read_PORTH() bfin_read16(PORTH) #define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ #define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) #define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) #define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) #define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) #define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ #define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) #define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ #define bfin_read_PORTI() bfin_read16(PORTI) #define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ #define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) #define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) #define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) #define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) #define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ #define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) #define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ #define bfin_read_PORTJ() bfin_read16(PORTJ) #define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ #define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) #define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) #define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) #define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) #define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ #define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ #define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ #define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) #define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ #define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ #define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ #define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ #define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ #define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ #define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ #define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ #define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ #define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) #define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ #define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ #define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ #define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ #define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ #define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ #define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ #define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ #define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ #define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) #define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ #define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ #define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ #define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ #define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ #define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ #define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ #define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ #define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ #define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) #define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ #define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ #define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ #define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ #define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ #define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ #define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ #define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ #define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ #define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ #define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) #define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ #define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ #define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ #define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ #define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ #define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ #define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) #define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ #define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) #define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ #define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) #define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ #define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) #define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ #define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) #define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ #define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) #define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ #define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) #define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ #define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) #define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ #define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ #define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) #define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ #define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) #define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ #define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ #define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ #define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ #define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ #define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ #define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ #define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ #define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ #define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ #define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ #define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ #define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ #define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) #define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ #define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ #define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) #define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ #define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) #define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ #define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) #define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ #define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ #define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) #define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ #define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) #define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ #define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) #define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ #define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) #define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ #define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) #define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ #define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) #define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ #define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) #define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ #define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) #define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ #define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ #define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ #define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ #define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ #define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ #define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ #define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ #define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ #define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ #define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ #define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ #define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ #define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ #define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ #define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ #define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ #define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ #define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ #define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ #define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ #define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ #define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ #define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ #define bfin_read_NFC_RST() bfin_read16(NFC_RST) #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ #define bfin_read_NFC_READ() bfin_read16(NFC_READ) #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ #define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ #define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ #define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ #define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ #define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ #define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) #define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ #define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) #define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ #define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) #define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ #define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ #define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ #define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ #define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) #define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ #define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) #define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ #define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) #define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ #define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) #define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ #define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) #define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ #define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) #define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ #define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) #define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ #define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) #define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ #define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) #define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ #define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ #define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ #define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ #define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ #define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ #define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) #define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ #define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) #define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ #define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) #define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ #define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) #define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ #define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) #define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ #define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) #define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ #define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) #define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ #define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) #define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ #define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ #define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ #define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ #define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ #define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ #define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ #define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ #define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ #define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ #define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ #define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) #define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */ #define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) #define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */ #define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) #define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */ #define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) #define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */ #define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) #define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */ #define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) #define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */ #define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) #define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) #define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */ #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */ #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */ #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */ #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */ #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ #define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ #define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ #define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ #define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ #define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ #define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ #define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ #define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ #define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ #define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ #define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ #define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ #define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ #define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ #define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ #define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ #define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ #define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) #define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ #define bfin_read_UART1_THR() bfin_read16(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) #define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) #define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */ #define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) #define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */ #define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) #define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */ #define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) #define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */ #define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) #define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */ #define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) #define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) -#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */ #define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) #define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) #define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) -#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) -#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */ #define bfin_read_UART2_THR() bfin_read16(UART2_THR) #define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) -#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */ #define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) #define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) #define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) #define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ #define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) #define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ #define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) #define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ #define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) #define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ #define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) #define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ #define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) #define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ #define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) #define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) #define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ #define bfin_read_UART3_THR() bfin_read16(UART3_THR) #define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ #define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) #define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ #define bfin_read_USB_POWER() bfin_read16(USB_POWER) #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ #define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ #define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ #define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ #define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ #define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ #define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ #define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ #define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h index 0e482792cf..ef9111fed4 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF547-extended_def.h @@ -694,10 +694,6 @@ #define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ #define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ #define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h index caf2f6fb6d..dfb32760be 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_cdef.h @@ -6,5781 +6,3846 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF548_extended__ #define __BFIN_CDEF_ADSP_EDN_BF548_extended__ -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ #define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) #define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ #define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) #define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ #define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) #define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ #define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) #define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ #define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ #define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ #define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ #define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ #define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ #define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ #define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ #define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ #define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ #define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ #define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ #define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ #define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ #define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ #define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ #define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ #define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ #define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ #define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ #define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ #define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ #define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ #define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ #define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ #define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ #define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ #define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ #define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ #define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) #define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ #define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ #define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ #define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) #define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ #define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ #define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ #define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ #define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ #define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) #define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ #define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ #define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ #define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ #define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ #define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ #define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ #define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ #define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ #define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ #define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ #define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ #define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ #define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ #define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ #define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ #define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ #define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ #define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ #define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ #define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ #define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ #define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) #define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ #define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) #define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ #define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) #define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) #define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) #define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) #define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) #define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ #define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) #define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) #define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) #define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) #define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) #define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ #define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) #define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ #define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) #define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ #define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) #define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ #define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) #define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ #define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) #define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ #define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) #define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ #define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) #define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ #define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) #define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ #define bfin_read_PORTA() bfin_read16(PORTA) #define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ #define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) #define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) #define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) #define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) #define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ #define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) #define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ #define bfin_read_PORTB() bfin_read16(PORTB) #define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ #define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) #define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) #define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) #define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) #define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ #define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) #define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ #define bfin_read_PORTC() bfin_read16(PORTC) #define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ #define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) #define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) #define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) #define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) #define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ #define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) #define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ #define bfin_read_PORTD() bfin_read16(PORTD) #define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ #define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) #define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) #define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) #define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) #define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ #define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) #define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ #define bfin_read_PORTE() bfin_read16(PORTE) #define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ #define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) #define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) #define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) #define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) #define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ #define bfin_read_PORTF() bfin_read16(PORTF) #define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ #define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) #define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) #define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) #define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) #define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ #define bfin_read_PORTG() bfin_read16(PORTG) #define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ #define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) #define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) #define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) #define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) #define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ #define bfin_read_PORTH() bfin_read16(PORTH) #define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ #define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) #define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) #define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) #define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) #define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ #define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) #define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ #define bfin_read_PORTI() bfin_read16(PORTI) #define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ #define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) #define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) #define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) #define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) #define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ #define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) #define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ #define bfin_read_PORTJ() bfin_read16(PORTJ) #define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ #define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) #define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) #define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) #define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) #define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ #define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ #define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ #define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) #define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ #define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ #define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ #define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ #define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ #define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ #define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ #define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ #define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ #define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) #define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ #define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ #define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ #define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ #define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ #define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ #define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ #define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ #define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ #define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) #define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ #define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ #define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ #define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ #define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ #define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ #define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ #define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ #define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ #define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) #define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ #define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ #define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ #define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ #define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ #define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ #define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ #define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ #define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ #define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ #define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) #define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ #define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ #define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ #define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ #define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ #define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ #define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) #define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ #define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) #define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ #define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) #define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ #define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) #define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ #define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) #define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ #define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) #define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ #define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) #define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ #define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) #define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ #define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ #define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) #define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ #define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) #define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ #define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ #define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ #define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ #define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ #define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ #define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ #define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ #define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ #define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ #define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ #define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ #define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ #define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) #define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ #define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ #define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) #define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ #define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) #define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ #define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) #define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ #define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ #define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) #define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ #define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) #define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ #define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) #define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ #define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) #define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ #define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) #define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ #define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) #define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ #define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) #define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ #define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) #define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ #define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ #define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ #define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ #define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ #define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ #define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ #define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ #define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ #define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ #define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ #define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ #define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ #define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ #define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ #define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ #define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ #define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ #define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ #define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ #define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ #define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ #define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ #define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ #define bfin_read_NFC_RST() bfin_read16(NFC_RST) #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ #define bfin_read_NFC_READ() bfin_read16(NFC_READ) #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ #define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ #define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ #define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ #define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ #define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ #define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) #define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ #define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) #define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ #define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) #define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ #define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ #define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ #define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ #define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) #define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ #define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) #define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ #define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) #define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ #define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) #define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ #define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) #define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ #define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) #define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ #define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) #define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ #define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) #define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ #define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) #define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ #define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ #define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ #define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ #define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ #define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ #define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) #define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ #define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) #define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ #define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) #define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ #define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) #define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ #define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) #define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ #define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) #define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ #define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) #define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ #define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) #define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ #define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ #define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ #define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ #define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ #define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ #define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ #define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ #define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ #define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ #define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ #define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ #define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ #define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ #define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ #define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ #define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ #define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ #define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ #define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ #define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ #define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ #define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ #define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ #define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ #define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ #define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ #define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ #define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ #define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ #define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ #define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ #define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ #define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ #define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ #define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ #define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ #define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ #define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ #define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ #define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ #define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ #define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ #define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ #define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ #define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ #define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ #define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ #define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ #define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ #define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ #define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ #define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ #define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ #define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ #define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ #define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ #define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ #define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ #define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ #define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ #define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ #define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ #define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ #define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ #define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ #define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ #define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ #define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ #define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ #define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ #define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ #define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ #define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ #define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ #define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ #define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ #define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ #define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ #define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ #define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ #define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ #define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ #define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ #define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ #define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ #define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ #define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ #define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ #define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ #define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ #define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ #define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ #define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ #define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ #define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ #define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ #define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ #define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ #define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ #define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ #define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ #define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ #define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ #define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ #define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ #define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ #define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ #define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ #define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ #define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ #define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ #define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ #define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ #define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ #define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ #define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ #define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ #define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ #define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ #define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ #define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ #define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ #define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ #define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ #define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ #define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ #define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ #define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ #define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ #define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ #define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ #define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ #define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ #define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ #define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ #define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ #define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ #define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ #define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ #define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ #define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ #define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ #define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ #define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ #define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ #define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ #define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ #define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ #define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ #define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ #define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ #define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ #define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ #define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ #define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ #define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ #define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ #define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ #define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ #define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ #define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ #define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ #define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ #define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ #define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ #define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ #define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ #define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ #define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ #define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ #define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ #define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ #define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ #define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ #define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ #define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ #define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ #define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ #define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ #define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ #define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ #define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ #define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ #define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ #define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ #define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ #define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ #define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ #define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ #define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ #define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ #define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ #define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ #define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ #define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ #define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ #define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ #define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ #define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ #define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ #define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ #define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ #define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ #define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ #define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ #define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ #define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ #define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ #define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ #define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ #define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ #define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ #define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ #define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ #define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ #define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ #define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ #define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ #define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ #define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ #define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ #define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ #define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ #define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ #define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ #define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ #define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ #define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ #define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ #define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ #define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ #define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ #define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ #define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ #define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ #define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ #define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ #define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ #define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ #define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ #define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ #define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ #define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ #define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ #define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ #define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ #define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ #define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ #define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ #define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ #define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ #define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ #define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ #define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ #define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ #define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ #define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ #define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ #define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ #define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ #define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ #define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ #define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ #define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ #define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ #define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ #define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ #define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ #define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ #define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ #define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ #define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ #define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ #define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ #define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ #define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ #define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ #define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ #define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ #define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ #define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ #define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ #define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ #define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ #define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ #define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ #define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ #define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ #define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ #define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ #define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ #define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ #define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ #define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ #define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ #define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ #define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ #define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ #define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */ #define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */ #define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */ #define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */ #define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */ #define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */ #define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) #define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */ #define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) #define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */ #define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) #define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ #define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) #define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ #define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) #define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ #define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) #define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ #define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) #define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ #define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) #define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) -#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */ #define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) #define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */ #define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) #define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */ #define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) #define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */ #define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) #define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */ #define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) #define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */ #define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) #define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */ #define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) #define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */ #define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) #define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ #define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) #define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ #define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) #define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ #define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) #define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ #define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) #define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ #define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) #define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) -#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */ #define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) #define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */ #define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) #define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */ #define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) #define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */ #define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) #define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */ #define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) #define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */ #define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) #define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */ #define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) #define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */ #define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) #define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */ #define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) #define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */ #define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) #define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */ #define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) #define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */ #define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) #define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */ #define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) #define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */ #define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) #define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */ #define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) #define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */ #define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) #define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) -#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ #define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) #define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) #define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ #define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) #define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) #define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ #define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) #define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) #define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ #define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) #define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) #define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ #define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) #define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) #define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ #define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) #define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) #define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ #define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) #define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) #define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ #define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) #define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) #define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ #define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) #define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) #define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ #define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) #define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) #define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ #define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) #define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) #define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ #define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) #define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) #define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ #define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) #define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) #define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ #define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) #define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) #define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ #define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) #define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) #define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ #define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) #define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) #define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) -#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ #define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) #define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) #define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ #define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) #define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) #define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ #define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) #define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) #define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ #define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) #define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) #define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ #define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) #define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) #define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ #define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) #define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) #define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ #define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) #define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) #define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ #define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) #define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) #define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ #define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) #define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) #define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ #define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) #define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) #define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ #define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) #define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) #define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ #define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) #define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) #define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ #define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) #define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) #define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ #define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) #define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) #define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ #define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) #define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) #define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ #define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) #define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) #define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) -#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */ #define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */ #define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */ #define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */ #define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */ #define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */ #define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */ #define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) #define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */ #define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) #define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */ #define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */ #define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */ #define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */ #define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */ #define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */ #define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */ #define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) #define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */ #define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) #define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */ #define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */ #define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */ #define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */ #define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */ #define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */ #define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */ #define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) #define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */ #define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) #define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */ #define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */ #define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */ #define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */ #define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */ #define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */ #define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */ #define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) #define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */ #define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) #define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */ #define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */ #define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */ #define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */ #define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */ #define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */ #define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */ #define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) #define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */ #define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) #define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */ #define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */ #define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */ #define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */ #define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */ #define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */ #define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */ #define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) #define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */ #define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) #define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */ #define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */ #define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */ #define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */ #define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */ #define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */ #define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */ #define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) #define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */ #define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) #define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */ #define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */ #define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */ #define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */ #define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */ #define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */ #define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */ #define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) #define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */ #define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) #define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */ #define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */ #define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */ #define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */ #define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */ #define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */ #define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */ #define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) #define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */ #define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) #define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */ #define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */ #define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */ #define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */ #define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */ #define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */ #define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */ #define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) #define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */ #define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) #define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */ #define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */ #define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */ #define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */ #define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */ #define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */ #define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */ #define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) #define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */ #define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) #define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */ #define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */ #define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */ #define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */ #define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */ #define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */ #define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */ #define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) #define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */ #define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) #define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */ #define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */ #define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */ #define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */ #define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */ #define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */ #define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */ #define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) #define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */ #define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) #define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */ #define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */ #define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */ #define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */ #define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */ #define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */ #define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */ #define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) #define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */ #define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) #define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */ #define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */ #define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */ #define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */ #define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */ #define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */ #define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */ #define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) #define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */ #define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) #define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */ #define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */ #define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */ #define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */ #define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */ #define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */ #define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */ #define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) #define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */ #define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) #define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) -#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */ #define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */ #define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */ #define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */ #define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */ #define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */ #define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */ #define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) #define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */ #define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) #define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */ #define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */ #define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */ #define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */ #define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */ #define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */ #define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */ #define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) #define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */ #define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) #define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */ #define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */ #define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */ #define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */ #define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */ #define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */ #define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */ #define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) #define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */ #define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) #define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */ #define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */ #define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */ #define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */ #define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */ #define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */ #define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */ #define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) #define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */ #define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) #define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */ #define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */ #define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */ #define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */ #define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */ #define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */ #define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */ #define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) #define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */ #define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) #define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */ #define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */ #define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */ #define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */ #define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */ #define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */ #define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */ #define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) #define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */ #define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) #define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */ #define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */ #define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */ #define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */ #define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */ #define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */ #define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */ #define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) #define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */ #define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) #define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */ #define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */ #define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */ #define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */ #define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */ #define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */ #define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */ #define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) #define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */ #define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) #define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */ #define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */ #define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */ #define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */ #define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */ #define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */ #define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */ #define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) #define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */ #define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) #define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */ #define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */ #define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */ #define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */ #define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */ #define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */ #define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */ #define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) #define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */ #define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) #define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */ #define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */ #define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */ #define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */ #define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */ #define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */ #define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */ #define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) #define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */ #define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) #define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */ #define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */ #define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */ #define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */ #define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */ #define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */ #define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */ #define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) #define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */ #define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) #define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */ #define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */ #define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */ #define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */ #define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */ #define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */ #define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */ #define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) #define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */ #define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) #define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */ #define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */ #define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */ #define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */ #define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */ #define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */ #define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */ #define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) #define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */ #define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) #define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */ #define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */ #define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */ #define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */ #define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */ #define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */ #define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */ #define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) #define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */ #define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) #define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */ #define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */ #define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */ #define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */ #define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */ #define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */ #define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */ #define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) #define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */ #define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) #define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ #define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ #define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ #define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ #define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ #define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ #define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) #define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */ #define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) #define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */ #define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) #define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */ #define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) #define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */ #define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) #define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */ #define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) #define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */ #define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) #define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) #define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */ #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */ #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */ #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */ #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */ #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ #define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ #define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ #define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ #define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ #define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ #define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ #define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ #define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ #define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ #define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ #define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ #define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ #define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ #define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ #define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ #define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ #define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ #define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) #define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ #define bfin_read_UART1_THR() bfin_read16(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) #define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) #define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */ #define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) #define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */ #define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) #define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */ #define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) #define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */ #define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) #define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */ #define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) #define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) -#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */ #define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) #define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) #define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) -#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) -#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */ #define bfin_read_UART2_THR() bfin_read16(UART2_THR) #define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) -#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */ #define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) #define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) #define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) #define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ #define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) #define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ #define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) #define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ #define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) #define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ #define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) #define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ #define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) #define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ #define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) #define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) #define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ #define bfin_read_UART3_THR() bfin_read16(UART3_THR) #define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ #define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) #define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ #define bfin_read_USB_POWER() bfin_read16(USB_POWER) #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the endpoint5 Tx FIFO */ #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ #define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ #define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ #define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ #define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ #define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ #define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ #define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ #define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h index a92479bc67..1be6688619 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF548-extended_def.h @@ -694,10 +694,6 @@ #define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ #define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ #define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h index af90e4c62e..970f13f5d0 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_cdef.h @@ -6,6129 +6,4078 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF549_extended__ #define __BFIN_CDEF_ADSP_EDN_BF549_extended__ -#define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */ #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) -#define pSIC_IMASK1 ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */ #define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1) #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) -#define pSIC_IMASK2 ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */ #define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) -#define pSIC_ISR0 ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */ #define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) -#define pSIC_ISR1 ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */ #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) -#define pSIC_ISR2 ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */ #define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) -#define pSIC_IWR0 ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */ #define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) -#define pSIC_IWR1 ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */ #define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val) -#define pSIC_IWR2 ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */ #define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2) #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */ #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */ #define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */ #define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */ #define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_IAR4 ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */ #define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4) #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val) -#define pSIC_IAR5 ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */ #define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5) #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val) -#define pSIC_IAR6 ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */ #define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6) #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val) -#define pSIC_IAR7 ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */ #define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7) #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val) -#define pSIC_IAR8 ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */ #define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8) #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val) -#define pSIC_IAR9 ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */ #define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9) #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val) -#define pSIC_IAR10 ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */ #define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10) #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val) -#define pSIC_IAR11 ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */ #define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11) #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val) -#define pDMAC0_TCPER ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */ #define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER) #define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val) -#define pDMAC0_TCCNT ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */ #define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT) #define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val) -#define pDMAC1_TCPER ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */ #define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER) #define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val) -#define pDMAC1_TCCNT ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */ #define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT) #define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val) -#define pDMAC1_PERIMUX ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */ #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) -#define pDMA0_NEXT_DESC_PTR ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */ #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR) #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */ #define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR) #define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ #define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) #define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */ #define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) #define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */ #define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) #define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */ #define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) #define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */ #define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) #define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */ #define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR) #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */ #define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR) #define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */ #define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) #define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */ #define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) #define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */ #define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) #define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */ #define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) #define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */ #define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR) #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */ #define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR) #define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ #define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) #define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */ #define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) #define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */ #define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) #define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */ #define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) #define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */ #define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) #define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */ #define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR) #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */ #define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR) #define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */ #define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) #define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */ #define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) #define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */ #define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) #define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */ #define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) #define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */ #define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR) #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */ #define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR) #define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ #define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) #define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */ #define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) #define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */ #define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) #define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */ #define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) #define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */ #define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) #define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */ #define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR) #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */ #define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR) #define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */ #define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) #define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */ #define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) #define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */ #define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) #define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */ #define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) #define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */ #define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR) #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */ #define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR) #define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ #define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) #define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */ #define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) #define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */ #define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) #define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */ #define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) #define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */ #define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) #define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */ #define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR) #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */ #define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR) #define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */ #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */ #define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) #define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */ #define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) #define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */ #define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) #define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */ #define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR) #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */ #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR) #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ #define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) #define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */ #define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) #define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */ #define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) #define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */ #define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) #define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */ #define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) #define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */ #define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR) #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */ #define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR) #define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */ #define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) #define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */ #define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) #define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */ #define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) #define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */ #define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) #define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */ #define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR) #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */ #define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR) #define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */ #define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) #define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */ #define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) #define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */ #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */ #define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) #define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */ #define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR) #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */ #define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR) #define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */ #define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) #define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */ #define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) #define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */ #define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) #define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */ #define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) #define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */ #define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR) #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */ #define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR) #define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ #define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) #define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */ #define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) #define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */ #define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) #define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */ #define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) #define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */ #define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) #define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */ #define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR) #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */ #define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR) #define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */ #define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) #define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */ #define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) #define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */ #define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) #define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */ #define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) #define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */ #define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR) #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */ #define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR) #define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ #define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) #define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */ #define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) #define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */ #define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) #define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */ #define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) #define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */ #define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) #define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */ #define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR) #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */ #define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR) #define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */ #define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) #define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */ #define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) #define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */ #define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */ #define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */ #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR) #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val) -#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */ #define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR) #define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val) -#define pDMA8_CONFIG ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */ #define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG) #define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val) -#define pDMA8_X_COUNT ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */ #define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT) #define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val) -#define pDMA8_X_MODIFY ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */ #define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY) #define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val) -#define pDMA8_Y_COUNT ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */ #define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT) #define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val) -#define pDMA8_Y_MODIFY ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */ #define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY) #define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val) -#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */ #define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR) #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val) -#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */ #define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR) #define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val) -#define pDMA8_IRQ_STATUS ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */ #define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS) #define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val) -#define pDMA8_PERIPHERAL_MAP ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */ #define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP) #define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val) -#define pDMA8_CURR_X_COUNT ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */ #define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT) #define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val) -#define pDMA8_CURR_Y_COUNT ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */ #define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT) #define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val) -#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */ #define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR) #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val) -#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */ #define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR) #define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val) -#define pDMA9_CONFIG ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */ #define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG) #define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val) -#define pDMA9_X_COUNT ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */ #define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT) #define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val) -#define pDMA9_X_MODIFY ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */ #define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY) #define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val) -#define pDMA9_Y_COUNT ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */ #define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT) #define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val) -#define pDMA9_Y_MODIFY ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */ #define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY) #define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val) -#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */ #define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR) #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val) -#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */ #define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR) #define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val) -#define pDMA9_IRQ_STATUS ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */ #define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS) #define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val) -#define pDMA9_PERIPHERAL_MAP ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */ #define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP) #define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val) -#define pDMA9_CURR_X_COUNT ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */ #define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT) #define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val) -#define pDMA9_CURR_Y_COUNT ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */ #define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT) #define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val) -#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */ #define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR) #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val) -#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */ #define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR) #define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val) -#define pDMA10_CONFIG ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */ #define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG) #define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val) -#define pDMA10_X_COUNT ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */ #define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT) #define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val) -#define pDMA10_X_MODIFY ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */ #define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY) #define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val) -#define pDMA10_Y_COUNT ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */ #define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT) #define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val) -#define pDMA10_Y_MODIFY ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */ #define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY) #define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val) -#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */ #define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR) #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val) -#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */ #define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR) #define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val) -#define pDMA10_IRQ_STATUS ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */ #define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS) #define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val) -#define pDMA10_PERIPHERAL_MAP ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */ #define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP) #define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val) -#define pDMA10_CURR_X_COUNT ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */ #define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT) #define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val) -#define pDMA10_CURR_Y_COUNT ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */ #define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT) #define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val) -#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */ #define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR) #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val) -#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */ #define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR) #define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val) -#define pDMA11_CONFIG ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */ #define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG) #define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val) -#define pDMA11_X_COUNT ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */ #define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT) #define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val) -#define pDMA11_X_MODIFY ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */ #define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY) #define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val) -#define pDMA11_Y_COUNT ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */ #define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT) #define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val) -#define pDMA11_Y_MODIFY ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */ #define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY) #define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val) -#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */ #define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR) #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val) -#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */ #define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR) #define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val) -#define pDMA11_IRQ_STATUS ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */ #define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS) #define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val) -#define pDMA11_PERIPHERAL_MAP ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */ #define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP) #define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val) -#define pDMA11_CURR_X_COUNT ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */ #define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT) #define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val) -#define pDMA11_CURR_Y_COUNT ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */ #define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT) #define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val) -#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */ #define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR) #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val) -#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */ #define bfin_read_DMA12_START_ADDR() bfin_readPTR(DMA12_START_ADDR) #define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val) -#define pDMA12_CONFIG ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */ #define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG) #define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val) -#define pDMA12_X_COUNT ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */ #define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT) #define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val) -#define pDMA12_X_MODIFY ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */ #define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY) #define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val) -#define pDMA12_Y_COUNT ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */ #define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT) #define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val) -#define pDMA12_Y_MODIFY ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */ #define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY) #define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val) -#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */ #define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR) #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val) -#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */ #define bfin_read_DMA12_CURR_ADDR() bfin_readPTR(DMA12_CURR_ADDR) #define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val) -#define pDMA12_IRQ_STATUS ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */ #define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS) #define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val) -#define pDMA12_PERIPHERAL_MAP ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */ #define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP) #define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val) -#define pDMA12_CURR_X_COUNT ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */ #define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT) #define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val) -#define pDMA12_CURR_Y_COUNT ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */ #define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT) #define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val) -#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */ #define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR) #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val) -#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */ #define bfin_read_DMA13_START_ADDR() bfin_readPTR(DMA13_START_ADDR) #define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val) -#define pDMA13_CONFIG ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */ #define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG) #define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val) -#define pDMA13_X_COUNT ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */ #define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT) #define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val) -#define pDMA13_X_MODIFY ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */ #define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY) #define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val) -#define pDMA13_Y_COUNT ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */ #define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT) #define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val) -#define pDMA13_Y_MODIFY ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */ #define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY) #define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val) -#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */ #define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR) #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val) -#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */ #define bfin_read_DMA13_CURR_ADDR() bfin_readPTR(DMA13_CURR_ADDR) #define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val) -#define pDMA13_IRQ_STATUS ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */ #define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS) #define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val) -#define pDMA13_PERIPHERAL_MAP ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */ #define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP) #define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val) -#define pDMA13_CURR_X_COUNT ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */ #define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT) #define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val) -#define pDMA13_CURR_Y_COUNT ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */ #define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT) #define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val) -#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */ #define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR) #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val) -#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */ #define bfin_read_DMA14_START_ADDR() bfin_readPTR(DMA14_START_ADDR) #define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val) -#define pDMA14_CONFIG ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */ #define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG) #define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val) -#define pDMA14_X_COUNT ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */ #define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT) #define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val) -#define pDMA14_X_MODIFY ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */ #define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY) #define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val) -#define pDMA14_Y_COUNT ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */ #define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT) #define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val) -#define pDMA14_Y_MODIFY ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */ #define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY) #define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val) -#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */ #define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR) #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val) -#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */ #define bfin_read_DMA14_CURR_ADDR() bfin_readPTR(DMA14_CURR_ADDR) #define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val) -#define pDMA14_IRQ_STATUS ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */ #define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS) #define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val) -#define pDMA14_PERIPHERAL_MAP ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */ #define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP) #define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val) -#define pDMA14_CURR_X_COUNT ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */ #define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT) #define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val) -#define pDMA14_CURR_Y_COUNT ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */ #define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT) #define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val) -#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */ #define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR) #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val) -#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */ #define bfin_read_DMA15_START_ADDR() bfin_readPTR(DMA15_START_ADDR) #define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val) -#define pDMA15_CONFIG ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */ #define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG) #define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val) -#define pDMA15_X_COUNT ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */ #define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT) #define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val) -#define pDMA15_X_MODIFY ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */ #define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY) #define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val) -#define pDMA15_Y_COUNT ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */ #define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT) #define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val) -#define pDMA15_Y_MODIFY ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */ #define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY) #define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val) -#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */ #define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR) #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val) -#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */ #define bfin_read_DMA15_CURR_ADDR() bfin_readPTR(DMA15_CURR_ADDR) #define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val) -#define pDMA15_IRQ_STATUS ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */ #define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS) #define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val) -#define pDMA15_PERIPHERAL_MAP ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */ #define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP) #define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val) -#define pDMA15_CURR_X_COUNT ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */ #define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT) #define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val) -#define pDMA15_CURR_Y_COUNT ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */ #define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT) #define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val) -#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */ #define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR) #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val) -#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */ #define bfin_read_DMA16_START_ADDR() bfin_readPTR(DMA16_START_ADDR) #define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val) -#define pDMA16_CONFIG ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */ #define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG) #define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val) -#define pDMA16_X_COUNT ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */ #define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT) #define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val) -#define pDMA16_X_MODIFY ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */ #define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY) #define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val) -#define pDMA16_Y_COUNT ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */ #define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT) #define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val) -#define pDMA16_Y_MODIFY ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */ #define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY) #define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val) -#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */ #define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR) #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val) -#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */ #define bfin_read_DMA16_CURR_ADDR() bfin_readPTR(DMA16_CURR_ADDR) #define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val) -#define pDMA16_IRQ_STATUS ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */ #define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS) #define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val) -#define pDMA16_PERIPHERAL_MAP ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */ #define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP) #define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val) -#define pDMA16_CURR_X_COUNT ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */ #define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT) #define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val) -#define pDMA16_CURR_Y_COUNT ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */ #define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT) #define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val) -#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */ #define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR) #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val) -#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */ #define bfin_read_DMA17_START_ADDR() bfin_readPTR(DMA17_START_ADDR) #define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val) -#define pDMA17_CONFIG ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */ #define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG) #define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val) -#define pDMA17_X_COUNT ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */ #define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT) #define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val) -#define pDMA17_X_MODIFY ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */ #define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY) #define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val) -#define pDMA17_Y_COUNT ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */ #define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT) #define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val) -#define pDMA17_Y_MODIFY ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */ #define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY) #define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val) -#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */ #define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR) #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val) -#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */ #define bfin_read_DMA17_CURR_ADDR() bfin_readPTR(DMA17_CURR_ADDR) #define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val) -#define pDMA17_IRQ_STATUS ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */ #define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS) #define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val) -#define pDMA17_PERIPHERAL_MAP ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */ #define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP) #define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val) -#define pDMA17_CURR_X_COUNT ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */ #define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT) #define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val) -#define pDMA17_CURR_Y_COUNT ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */ #define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT) #define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val) -#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */ #define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR) #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val) -#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */ #define bfin_read_DMA18_START_ADDR() bfin_readPTR(DMA18_START_ADDR) #define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val) -#define pDMA18_CONFIG ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */ #define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG) #define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val) -#define pDMA18_X_COUNT ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */ #define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT) #define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val) -#define pDMA18_X_MODIFY ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */ #define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY) #define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val) -#define pDMA18_Y_COUNT ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */ #define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT) #define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val) -#define pDMA18_Y_MODIFY ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */ #define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY) #define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val) -#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */ #define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR) #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val) -#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */ #define bfin_read_DMA18_CURR_ADDR() bfin_readPTR(DMA18_CURR_ADDR) #define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val) -#define pDMA18_IRQ_STATUS ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */ #define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS) #define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val) -#define pDMA18_PERIPHERAL_MAP ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */ #define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP) #define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val) -#define pDMA18_CURR_X_COUNT ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */ #define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT) #define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val) -#define pDMA18_CURR_Y_COUNT ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */ #define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT) #define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val) -#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */ #define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR) #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val) -#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */ #define bfin_read_DMA19_START_ADDR() bfin_readPTR(DMA19_START_ADDR) #define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val) -#define pDMA19_CONFIG ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */ #define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG) #define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val) -#define pDMA19_X_COUNT ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */ #define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT) #define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val) -#define pDMA19_X_MODIFY ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */ #define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY) #define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val) -#define pDMA19_Y_COUNT ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */ #define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT) #define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val) -#define pDMA19_Y_MODIFY ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */ #define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY) #define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val) -#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */ #define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR) #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val) -#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */ #define bfin_read_DMA19_CURR_ADDR() bfin_readPTR(DMA19_CURR_ADDR) #define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val) -#define pDMA19_IRQ_STATUS ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */ #define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS) #define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val) -#define pDMA19_PERIPHERAL_MAP ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */ #define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP) #define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val) -#define pDMA19_CURR_X_COUNT ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */ #define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT) #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val) -#define pDMA19_CURR_Y_COUNT ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */ #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT) #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val) -#define pDMA20_NEXT_DESC_PTR ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */ #define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR) #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val) -#define pDMA20_START_ADDR ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */ #define bfin_read_DMA20_START_ADDR() bfin_readPTR(DMA20_START_ADDR) #define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val) -#define pDMA20_CONFIG ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */ #define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG) #define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val) -#define pDMA20_X_COUNT ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */ #define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT) #define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val) -#define pDMA20_X_MODIFY ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */ #define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY) #define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val) -#define pDMA20_Y_COUNT ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */ #define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT) #define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val) -#define pDMA20_Y_MODIFY ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */ #define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY) #define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val) -#define pDMA20_CURR_DESC_PTR ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */ #define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR) #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val) -#define pDMA20_CURR_ADDR ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */ #define bfin_read_DMA20_CURR_ADDR() bfin_readPTR(DMA20_CURR_ADDR) #define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val) -#define pDMA20_IRQ_STATUS ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */ #define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS) #define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val) -#define pDMA20_PERIPHERAL_MAP ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */ #define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP) #define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val) -#define pDMA20_CURR_X_COUNT ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */ #define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT) #define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val) -#define pDMA20_CURR_Y_COUNT ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */ #define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT) #define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val) -#define pDMA21_NEXT_DESC_PTR ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */ #define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR) #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val) -#define pDMA21_START_ADDR ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */ #define bfin_read_DMA21_START_ADDR() bfin_readPTR(DMA21_START_ADDR) #define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val) -#define pDMA21_CONFIG ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */ #define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG) #define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val) -#define pDMA21_X_COUNT ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */ #define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT) #define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val) -#define pDMA21_X_MODIFY ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */ #define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY) #define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val) -#define pDMA21_Y_COUNT ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */ #define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT) #define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val) -#define pDMA21_Y_MODIFY ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */ #define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY) #define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val) -#define pDMA21_CURR_DESC_PTR ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */ #define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR) #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val) -#define pDMA21_CURR_ADDR ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */ #define bfin_read_DMA21_CURR_ADDR() bfin_readPTR(DMA21_CURR_ADDR) #define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val) -#define pDMA21_IRQ_STATUS ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */ #define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS) #define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val) -#define pDMA21_PERIPHERAL_MAP ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */ #define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP) #define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val) -#define pDMA21_CURR_X_COUNT ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */ #define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT) #define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val) -#define pDMA21_CURR_Y_COUNT ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */ #define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT) #define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val) -#define pDMA22_NEXT_DESC_PTR ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */ #define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR) #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val) -#define pDMA22_START_ADDR ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */ #define bfin_read_DMA22_START_ADDR() bfin_readPTR(DMA22_START_ADDR) #define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val) -#define pDMA22_CONFIG ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */ #define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG) #define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val) -#define pDMA22_X_COUNT ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */ #define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT) #define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val) -#define pDMA22_X_MODIFY ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */ #define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY) #define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val) -#define pDMA22_Y_COUNT ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */ #define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT) #define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val) -#define pDMA22_Y_MODIFY ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */ #define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY) #define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val) -#define pDMA22_CURR_DESC_PTR ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */ #define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR) #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val) -#define pDMA22_CURR_ADDR ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */ #define bfin_read_DMA22_CURR_ADDR() bfin_readPTR(DMA22_CURR_ADDR) #define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val) -#define pDMA22_IRQ_STATUS ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */ #define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS) #define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val) -#define pDMA22_PERIPHERAL_MAP ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */ #define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP) #define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val) -#define pDMA22_CURR_X_COUNT ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */ #define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT) #define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val) -#define pDMA22_CURR_Y_COUNT ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */ #define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT) #define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val) -#define pDMA23_NEXT_DESC_PTR ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */ #define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR) #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val) -#define pDMA23_START_ADDR ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */ #define bfin_read_DMA23_START_ADDR() bfin_readPTR(DMA23_START_ADDR) #define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val) -#define pDMA23_CONFIG ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */ #define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG) #define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val) -#define pDMA23_X_COUNT ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */ #define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT) #define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val) -#define pDMA23_X_MODIFY ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */ #define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY) #define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val) -#define pDMA23_Y_COUNT ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */ #define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT) #define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val) -#define pDMA23_Y_MODIFY ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */ #define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY) #define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val) -#define pDMA23_CURR_DESC_PTR ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */ #define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR) #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val) -#define pDMA23_CURR_ADDR ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */ #define bfin_read_DMA23_CURR_ADDR() bfin_readPTR(DMA23_CURR_ADDR) #define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val) -#define pDMA23_IRQ_STATUS ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */ #define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS) #define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val) -#define pDMA23_PERIPHERAL_MAP ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */ #define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP) #define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val) -#define pDMA23_CURR_X_COUNT ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */ #define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT) #define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val) -#define pDMA23_CURR_Y_COUNT ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */ #define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT) #define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR) #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */ #define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR) #define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */ #define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) #define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */ #define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) #define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */ #define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) #define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */ #define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) #define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */ #define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) #define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR) #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */ #define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR) #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) #define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */ #define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) #define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */ #define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) #define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */ #define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) #define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR) #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */ #define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR) #define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */ #define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) #define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */ #define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) #define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */ #define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) #define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */ #define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) #define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */ #define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) #define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR) #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */ #define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR) #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */ #define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) #define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */ #define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) #define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */ #define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) #define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */ #define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) #define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR) #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */ #define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR) #define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */ #define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) #define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */ #define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) #define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */ #define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) #define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */ #define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) #define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */ #define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) #define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR) #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */ #define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR) #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) #define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */ #define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) #define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */ #define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) #define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */ #define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) #define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR) #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */ #define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR) #define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */ #define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) #define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */ #define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) #define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */ #define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) #define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */ #define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) #define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */ #define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) #define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR) #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */ #define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR) #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */ #define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) #define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */ #define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) #define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */ #define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) #define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */ #define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) #define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pMDMA_D2_NEXT_DESC_PTR ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR) #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val) -#define pMDMA_D2_START_ADDR ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */ #define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR) #define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val) -#define pMDMA_D2_CONFIG ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */ #define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG) #define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val) -#define pMDMA_D2_X_COUNT ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */ #define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT) #define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val) -#define pMDMA_D2_X_MODIFY ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */ #define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY) #define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val) -#define pMDMA_D2_Y_COUNT ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */ #define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT) #define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val) -#define pMDMA_D2_Y_MODIFY ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */ #define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY) #define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val) -#define pMDMA_D2_CURR_DESC_PTR ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR) #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val) -#define pMDMA_D2_CURR_ADDR ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */ #define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR) #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val) -#define pMDMA_D2_IRQ_STATUS ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS) #define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val) -#define pMDMA_D2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */ #define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP) #define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val) -#define pMDMA_D2_CURR_X_COUNT ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */ #define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT) #define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val) -#define pMDMA_D2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */ #define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT) #define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val) -#define pMDMA_S2_NEXT_DESC_PTR ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR) #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val) -#define pMDMA_S2_START_ADDR ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */ #define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR) #define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val) -#define pMDMA_S2_CONFIG ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */ #define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG) #define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val) -#define pMDMA_S2_X_COUNT ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */ #define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT) #define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val) -#define pMDMA_S2_X_MODIFY ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */ #define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY) #define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val) -#define pMDMA_S2_Y_COUNT ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */ #define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT) #define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val) -#define pMDMA_S2_Y_MODIFY ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */ #define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY) #define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val) -#define pMDMA_S2_CURR_DESC_PTR ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR) #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val) -#define pMDMA_S2_CURR_ADDR ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */ #define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR) #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val) -#define pMDMA_S2_IRQ_STATUS ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */ #define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS) #define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val) -#define pMDMA_S2_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */ #define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP) #define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val) -#define pMDMA_S2_CURR_X_COUNT ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */ #define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT) #define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val) -#define pMDMA_S2_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */ #define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT) #define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val) -#define pMDMA_D3_NEXT_DESC_PTR ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */ #define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR) #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val) -#define pMDMA_D3_START_ADDR ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */ #define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR) #define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val) -#define pMDMA_D3_CONFIG ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */ #define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG) #define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val) -#define pMDMA_D3_X_COUNT ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */ #define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT) #define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val) -#define pMDMA_D3_X_MODIFY ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */ #define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY) #define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val) -#define pMDMA_D3_Y_COUNT ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */ #define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT) #define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val) -#define pMDMA_D3_Y_MODIFY ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */ #define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY) #define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val) -#define pMDMA_D3_CURR_DESC_PTR ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ #define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR) #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val) -#define pMDMA_D3_CURR_ADDR ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */ #define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR) #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val) -#define pMDMA_D3_IRQ_STATUS ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */ #define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS) #define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val) -#define pMDMA_D3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */ #define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP) #define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val) -#define pMDMA_D3_CURR_X_COUNT ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */ #define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT) #define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val) -#define pMDMA_D3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */ #define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT) #define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val) -#define pMDMA_S3_NEXT_DESC_PTR ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */ #define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR) #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val) -#define pMDMA_S3_START_ADDR ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */ #define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR) #define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val) -#define pMDMA_S3_CONFIG ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */ #define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG) #define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val) -#define pMDMA_S3_X_COUNT ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */ #define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT) #define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val) -#define pMDMA_S3_X_MODIFY ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */ #define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY) #define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val) -#define pMDMA_S3_Y_COUNT ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */ #define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT) #define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val) -#define pMDMA_S3_Y_MODIFY ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */ #define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY) #define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val) -#define pMDMA_S3_CURR_DESC_PTR ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ #define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR) #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val) -#define pMDMA_S3_CURR_ADDR ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */ #define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR) #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val) -#define pMDMA_S3_IRQ_STATUS ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */ #define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS) #define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val) -#define pMDMA_S3_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */ #define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP) #define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val) -#define pMDMA_S3_CURR_X_COUNT ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */ #define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT) #define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val) -#define pMDMA_S3_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */ #define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT) #define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val) -#define pHMDMA0_CONTROL ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */ #define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) #define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) -#define pHMDMA0_ECINIT ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */ #define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) #define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) -#define pHMDMA0_BCINIT ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */ #define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) #define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) -#define pHMDMA0_ECOUNT ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */ #define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) #define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) -#define pHMDMA0_BCOUNT ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */ #define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) #define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) -#define pHMDMA0_ECURGENT ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) #define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) -#define pHMDMA0_ECOVERFLOW ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) #define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) -#define pHMDMA1_CONTROL ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */ #define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) #define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) -#define pHMDMA1_ECINIT ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */ #define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) #define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) -#define pHMDMA1_BCINIT ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */ #define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) #define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) -#define pHMDMA1_ECURGENT ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */ #define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) #define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) -#define pHMDMA1_ECOVERFLOW ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ #define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) #define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) -#define pHMDMA1_ECOUNT ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */ #define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) #define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) -#define pHMDMA1_BCOUNT ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */ #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */ #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_MBSCTL ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */ #define bfin_read_EBIU_MBSCTL() bfin_read32(EBIU_MBSCTL) #define bfin_write_EBIU_MBSCTL(val) bfin_write32(EBIU_MBSCTL, val) -#define pEBIU_ARBSTAT ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */ #define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT) #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val) -#define pEBIU_MODE ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */ #define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE) #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val) -#define pEBIU_FCTL ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */ #define bfin_read_EBIU_FCTL() bfin_read32(EBIU_FCTL) #define bfin_write_EBIU_FCTL(val) bfin_write32(EBIU_FCTL, val) -#define pEBIU_DDRCTL0 ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */ #define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0) #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val) -#define pEBIU_DDRCTL1 ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */ #define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1) #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val) -#define pEBIU_DDRCTL2 ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */ #define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2) #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val) -#define pEBIU_DDRCTL3 ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */ #define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3) #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val) -#define pEBIU_DDRQUE ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */ #define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE) #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val) -#define pEBIU_ERRADD ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */ #define bfin_read_EBIU_ERRADD() bfin_readPTR(EBIU_ERRADD) #define bfin_write_EBIU_ERRADD(val) bfin_writePTR(EBIU_ERRADD, val) -#define pEBIU_ERRMST ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */ #define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST) #define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val) -#define pEBIU_RSTCTL ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */ #define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL) #define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val) -#define pEBIU_DDRBRC0 ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */ #define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0) #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val) -#define pEBIU_DDRBRC1 ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */ #define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1) #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val) -#define pEBIU_DDRBRC2 ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */ #define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2) #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val) -#define pEBIU_DDRBRC3 ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */ #define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3) #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val) -#define pEBIU_DDRBRC4 ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */ #define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4) #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val) -#define pEBIU_DDRBRC5 ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */ #define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5) #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val) -#define pEBIU_DDRBRC6 ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */ #define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6) #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val) -#define pEBIU_DDRBRC7 ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */ #define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7) #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val) -#define pEBIU_DDRBWC0 ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */ #define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0) #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val) -#define pEBIU_DDRBWC1 ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */ #define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1) #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val) -#define pEBIU_DDRBWC2 ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */ #define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2) #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val) -#define pEBIU_DDRBWC3 ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */ #define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3) #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val) -#define pEBIU_DDRBWC4 ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */ #define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4) #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val) -#define pEBIU_DDRBWC5 ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */ #define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5) #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val) -#define pEBIU_DDRBWC6 ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */ #define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6) #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val) -#define pEBIU_DDRBWC7 ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */ #define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7) #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val) -#define pEBIU_DDRACCT ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */ #define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT) #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val) -#define pEBIU_DDRTACT ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */ #define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT) #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val) -#define pEBIU_DDRARCT ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */ #define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT) #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val) -#define pEBIU_DDRGC0 ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */ #define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0) #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val) -#define pEBIU_DDRGC1 ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */ #define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1) #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val) -#define pEBIU_DDRGC2 ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */ #define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2) #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val) -#define pEBIU_DDRGC3 ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */ #define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3) #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val) -#define pEBIU_DDRMCEN ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */ #define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN) #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val) -#define pEBIU_DDRMCCL ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */ #define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL) #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val) -#define pPIXC_CTL ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ #define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) #define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) -#define pPIXC_PPL ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */ #define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) #define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) -#define pPIXC_LPF ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */ #define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) #define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) -#define pPIXC_AHSTART ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) #define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) -#define pPIXC_AHEND ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) #define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) -#define pPIXC_AVSTART ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) #define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) -#define pPIXC_AVEND ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */ #define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) #define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) -#define pPIXC_ATRANSP ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */ #define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) #define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) -#define pPIXC_BHSTART ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) #define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) -#define pPIXC_BHEND ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) #define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) -#define pPIXC_BVSTART ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) #define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) -#define pPIXC_BVEND ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */ #define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) #define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) -#define pPIXC_BTRANSP ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */ #define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) #define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) -#define pPIXC_INTRSTAT ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */ #define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) #define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) -#define pPIXC_RYCON ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ #define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) #define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) -#define pPIXC_GUCON ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */ #define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) #define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) -#define pPIXC_BVCON ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */ #define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) #define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) -#define pPIXC_CCBIAS ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */ #define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) #define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) -#define pPIXC_TC ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */ #define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) #define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) -#define pHOST_CONTROL ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */ #define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) #define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) -#define pHOST_STATUS ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */ #define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) #define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) -#define pHOST_TIMEOUT ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */ #define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) #define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) -#define pPORTA_FER ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */ #define bfin_read_PORTA_FER() bfin_read16(PORTA_FER) #define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val) -#define pPORTA ((uint16_t volatile *)PORTA) /* GPIO Data Register */ #define bfin_read_PORTA() bfin_read16(PORTA) #define bfin_write_PORTA(val) bfin_write16(PORTA, val) -#define pPORTA_SET ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */ #define bfin_read_PORTA_SET() bfin_read16(PORTA_SET) #define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val) -#define pPORTA_CLEAR ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR) #define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val) -#define pPORTA_DIR_SET ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET) #define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val) -#define pPORTA_DIR_CLEAR ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR) #define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val) -#define pPORTA_INEN ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN) #define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val) -#define pPORTA_MUX ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX) #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val) -#define pPORTB_FER ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */ #define bfin_read_PORTB_FER() bfin_read16(PORTB_FER) #define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val) -#define pPORTB ((uint16_t volatile *)PORTB) /* GPIO Data Register */ #define bfin_read_PORTB() bfin_read16(PORTB) #define bfin_write_PORTB(val) bfin_write16(PORTB, val) -#define pPORTB_SET ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */ #define bfin_read_PORTB_SET() bfin_read16(PORTB_SET) #define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val) -#define pPORTB_CLEAR ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR) #define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val) -#define pPORTB_DIR_SET ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET) #define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val) -#define pPORTB_DIR_CLEAR ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR) #define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val) -#define pPORTB_INEN ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN) #define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val) -#define pPORTB_MUX ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX) #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val) -#define pPORTC_FER ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */ #define bfin_read_PORTC_FER() bfin_read16(PORTC_FER) #define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val) -#define pPORTC ((uint16_t volatile *)PORTC) /* GPIO Data Register */ #define bfin_read_PORTC() bfin_read16(PORTC) #define bfin_write_PORTC(val) bfin_write16(PORTC, val) -#define pPORTC_SET ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */ #define bfin_read_PORTC_SET() bfin_read16(PORTC_SET) #define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val) -#define pPORTC_CLEAR ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR) #define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val) -#define pPORTC_DIR_SET ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET) #define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val) -#define pPORTC_DIR_CLEAR ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR) #define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val) -#define pPORTC_INEN ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN) #define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val) -#define pPORTC_MUX ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX) #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val) -#define pPORTD_FER ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */ #define bfin_read_PORTD_FER() bfin_read16(PORTD_FER) #define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val) -#define pPORTD ((uint16_t volatile *)PORTD) /* GPIO Data Register */ #define bfin_read_PORTD() bfin_read16(PORTD) #define bfin_write_PORTD(val) bfin_write16(PORTD, val) -#define pPORTD_SET ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */ #define bfin_read_PORTD_SET() bfin_read16(PORTD_SET) #define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val) -#define pPORTD_CLEAR ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR) #define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val) -#define pPORTD_DIR_SET ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET) #define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val) -#define pPORTD_DIR_CLEAR ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR) #define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val) -#define pPORTD_INEN ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN) #define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val) -#define pPORTD_MUX ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX) #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val) -#define pPORTE_FER ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */ #define bfin_read_PORTE_FER() bfin_read16(PORTE_FER) #define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val) -#define pPORTE ((uint16_t volatile *)PORTE) /* GPIO Data Register */ #define bfin_read_PORTE() bfin_read16(PORTE) #define bfin_write_PORTE(val) bfin_write16(PORTE, val) -#define pPORTE_SET ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */ #define bfin_read_PORTE_SET() bfin_read16(PORTE_SET) #define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val) -#define pPORTE_CLEAR ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR) #define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val) -#define pPORTE_DIR_SET ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET) #define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val) -#define pPORTE_DIR_CLEAR ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR) #define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val) -#define pPORTE_INEN ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN) #define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val) -#define pPORTE_MUX ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX) #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val) -#define pPORTF_FER ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */ #define bfin_read_PORTF_FER() bfin_read16(PORTF_FER) #define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val) -#define pPORTF ((uint16_t volatile *)PORTF) /* GPIO Data Register */ #define bfin_read_PORTF() bfin_read16(PORTF) #define bfin_write_PORTF(val) bfin_write16(PORTF, val) -#define pPORTF_SET ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */ #define bfin_read_PORTF_SET() bfin_read16(PORTF_SET) #define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val) -#define pPORTF_CLEAR ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR) #define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val) -#define pPORTF_DIR_SET ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET) #define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val) -#define pPORTF_DIR_CLEAR ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR) #define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val) -#define pPORTF_INEN ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN) #define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val) -#define pPORTF_MUX ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX) #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val) -#define pPORTG_FER ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */ #define bfin_read_PORTG_FER() bfin_read16(PORTG_FER) #define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val) -#define pPORTG ((uint16_t volatile *)PORTG) /* GPIO Data Register */ #define bfin_read_PORTG() bfin_read16(PORTG) #define bfin_write_PORTG(val) bfin_write16(PORTG, val) -#define pPORTG_SET ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */ #define bfin_read_PORTG_SET() bfin_read16(PORTG_SET) #define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val) -#define pPORTG_CLEAR ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR) #define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val) -#define pPORTG_DIR_SET ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET) #define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val) -#define pPORTG_DIR_CLEAR ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR) #define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val) -#define pPORTG_INEN ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN) #define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val) -#define pPORTG_MUX ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX) #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val) -#define pPORTH_FER ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */ #define bfin_read_PORTH_FER() bfin_read16(PORTH_FER) #define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val) -#define pPORTH ((uint16_t volatile *)PORTH) /* GPIO Data Register */ #define bfin_read_PORTH() bfin_read16(PORTH) #define bfin_write_PORTH(val) bfin_write16(PORTH, val) -#define pPORTH_SET ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */ #define bfin_read_PORTH_SET() bfin_read16(PORTH_SET) #define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val) -#define pPORTH_CLEAR ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR) #define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val) -#define pPORTH_DIR_SET ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET) #define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val) -#define pPORTH_DIR_CLEAR ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR) #define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val) -#define pPORTH_INEN ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN) #define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val) -#define pPORTH_MUX ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX) #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val) -#define pPORTI_FER ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */ #define bfin_read_PORTI_FER() bfin_read16(PORTI_FER) #define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val) -#define pPORTI ((uint16_t volatile *)PORTI) /* GPIO Data Register */ #define bfin_read_PORTI() bfin_read16(PORTI) #define bfin_write_PORTI(val) bfin_write16(PORTI, val) -#define pPORTI_SET ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */ #define bfin_read_PORTI_SET() bfin_read16(PORTI_SET) #define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val) -#define pPORTI_CLEAR ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR) #define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val) -#define pPORTI_DIR_SET ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET) #define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val) -#define pPORTI_DIR_CLEAR ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR) #define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val) -#define pPORTI_INEN ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN) #define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val) -#define pPORTI_MUX ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX) #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val) -#define pPORTJ_FER ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */ #define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER) #define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val) -#define pPORTJ ((uint16_t volatile *)PORTJ) /* GPIO Data Register */ #define bfin_read_PORTJ() bfin_read16(PORTJ) #define bfin_write_PORTJ(val) bfin_write16(PORTJ, val) -#define pPORTJ_SET ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */ #define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET) #define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val) -#define pPORTJ_CLEAR ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */ #define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR) #define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val) -#define pPORTJ_DIR_SET ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */ #define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET) #define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val) -#define pPORTJ_DIR_CLEAR ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */ #define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR) #define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val) -#define pPORTJ_INEN ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */ #define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN) #define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val) -#define pPORTJ_MUX ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */ #define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX) #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val) -#define pPINT0_MASK_SET ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */ #define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET) #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val) -#define pPINT0_MASK_CLEAR ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */ #define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR) #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val) -#define pPINT0_IRQ ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */ #define bfin_read_PINT0_IRQ() bfin_read32(PINT0_IRQ) #define bfin_write_PINT0_IRQ(val) bfin_write32(PINT0_IRQ, val) -#define pPINT0_ASSIGN ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */ #define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN) #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val) -#define pPINT0_EDGE_SET ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */ #define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET) #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val) -#define pPINT0_EDGE_CLEAR ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */ #define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR) #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val) -#define pPINT0_INVERT_SET ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */ #define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET) #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val) -#define pPINT0_INVERT_CLEAR ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */ #define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR) #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val) -#define pPINT0_PINSTATE ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */ #define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE) #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val) -#define pPINT0_LATCH ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */ #define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH) #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val) -#define pPINT1_MASK_SET ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */ #define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET) #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val) -#define pPINT1_MASK_CLEAR ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */ #define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR) #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val) -#define pPINT1_IRQ ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */ #define bfin_read_PINT1_IRQ() bfin_read32(PINT1_IRQ) #define bfin_write_PINT1_IRQ(val) bfin_write32(PINT1_IRQ, val) -#define pPINT1_ASSIGN ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */ #define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN) #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val) -#define pPINT1_EDGE_SET ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */ #define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET) #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val) -#define pPINT1_EDGE_CLEAR ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */ #define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR) #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val) -#define pPINT1_INVERT_SET ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */ #define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET) #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val) -#define pPINT1_INVERT_CLEAR ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */ #define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR) #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val) -#define pPINT1_PINSTATE ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */ #define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE) #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val) -#define pPINT1_LATCH ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */ #define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH) #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val) -#define pPINT2_MASK_SET ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */ #define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET) #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val) -#define pPINT2_MASK_CLEAR ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */ #define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR) #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val) -#define pPINT2_IRQ ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */ #define bfin_read_PINT2_IRQ() bfin_read32(PINT2_IRQ) #define bfin_write_PINT2_IRQ(val) bfin_write32(PINT2_IRQ, val) -#define pPINT2_ASSIGN ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */ #define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN) #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val) -#define pPINT2_EDGE_SET ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */ #define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET) #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val) -#define pPINT2_EDGE_CLEAR ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */ #define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR) #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val) -#define pPINT2_INVERT_SET ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */ #define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET) #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val) -#define pPINT2_INVERT_CLEAR ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */ #define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR) #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val) -#define pPINT2_PINSTATE ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */ #define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE) #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val) -#define pPINT2_LATCH ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */ #define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH) #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val) -#define pPINT3_MASK_SET ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */ #define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET) #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val) -#define pPINT3_MASK_CLEAR ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */ #define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR) #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val) -#define pPINT3_IRQ ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */ #define bfin_read_PINT3_IRQ() bfin_read32(PINT3_IRQ) #define bfin_write_PINT3_IRQ(val) bfin_write32(PINT3_IRQ, val) -#define pPINT3_ASSIGN ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */ #define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN) #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val) -#define pPINT3_EDGE_SET ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */ #define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET) #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val) -#define pPINT3_EDGE_CLEAR ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */ #define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR) #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val) -#define pPINT3_INVERT_SET ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */ #define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET) #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val) -#define pPINT3_INVERT_CLEAR ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */ #define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR) #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val) -#define pPINT3_PINSTATE ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */ #define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE) #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val) -#define pPINT3_LATCH ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */ #define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH) #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */ #define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */ #define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */ #define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */ #define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) #define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */ #define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */ #define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */ #define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */ #define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) #define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */ #define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */ #define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */ #define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */ #define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) #define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */ #define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */ #define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */ #define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */ #define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) #define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */ #define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */ #define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */ #define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */ #define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) #define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */ #define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */ #define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */ #define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */ #define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) #define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */ #define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */ #define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */ #define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */ #define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) #define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */ #define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */ #define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */ #define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */ #define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) #define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */ #define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) #define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */ #define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) #define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */ #define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) #define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */ #define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) #define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */ #define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) #define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */ #define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) #define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */ #define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) #define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */ #define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) #define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */ #define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) #define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */ #define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) #define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */ #define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) #define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER_ENABLE0 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */ #define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0) #define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val) -#define pTIMER_DISABLE0 ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */ #define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0) #define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val) -#define pTIMER_STATUS0 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */ #define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0) #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val) -#define pTIMER_ENABLE1 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */ #define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) #define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) -#define pTIMER_DISABLE1 ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */ #define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) #define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) -#define pTIMER_STATUS1 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */ #define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) #define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ #define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) #define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ #define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ #define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pCNT_CONFIG ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */ #define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG) #define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val) -#define pCNT_IMASK ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */ #define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK) #define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val) -#define pCNT_STATUS ((uint16_t volatile *)CNT_STATUS) /* Status Register */ #define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS) #define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val) -#define pCNT_COMMAND ((uint16_t volatile *)CNT_COMMAND) /* Command Register */ #define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND) #define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val) -#define pCNT_DEBOUNCE ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */ #define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE) #define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val) -#define pCNT_COUNTER ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */ #define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER) #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val) -#define pCNT_MAX ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */ #define bfin_read_CNT_MAX() bfin_read32(CNT_MAX) #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val) -#define pCNT_MIN ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */ #define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */ #define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) #define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */ #define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) #define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */ #define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) #define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */ #define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */ #define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) #define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pOTP_CONTROL ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */ #define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) #define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) -#define pOTP_BEN ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */ #define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) #define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) -#define pOTP_STATUS ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */ #define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) #define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) -#define pOTP_TIMING ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */ #define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) #define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) -#define pSECURE_SYSSWT ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val) -#define pSECURE_CONTROL ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */ #define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL) #define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val) -#define pSECURE_STATUS ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) -#define pOTP_DATA0 ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) #define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) -#define pOTP_DATA1 ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) #define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) -#define pOTP_DATA2 ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) #define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) -#define pOTP_DATA3 ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ #define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) #define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */ #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */ #define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) #define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */ #define bfin_read_VR_CTL() bfin_read16(VR_CTL) #define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */ #define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) #define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pMXVR_CONFIG ((uint16_t volatile *)MXVR_CONFIG) /* MXVR Configuration Register */ #define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG) #define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val) -#define pMXVR_STATE_0 ((uint32_t volatile *)MXVR_STATE_0) /* MXVR State Register 0 */ #define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0) #define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val) -#define pMXVR_STATE_1 ((uint32_t volatile *)MXVR_STATE_1) /* MXVR State Register 1 */ #define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1) #define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val) -#define pMXVR_INT_STAT_0 ((uint32_t volatile *)MXVR_INT_STAT_0) /* MXVR Interrupt Status Register 0 */ #define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0) #define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val) -#define pMXVR_INT_STAT_1 ((uint32_t volatile *)MXVR_INT_STAT_1) /* MXVR Interrupt Status Register 1 */ #define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1) #define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val) -#define pMXVR_INT_EN_0 ((uint32_t volatile *)MXVR_INT_EN_0) /* MXVR Interrupt Enable Register 0 */ #define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0) #define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val) -#define pMXVR_INT_EN_1 ((uint32_t volatile *)MXVR_INT_EN_1) /* MXVR Interrupt Enable Register 1 */ #define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1) #define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val) -#define pMXVR_POSITION ((uint16_t volatile *)MXVR_POSITION) /* MXVR Node Position Register */ #define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION) #define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val) -#define pMXVR_MAX_POSITION ((uint16_t volatile *)MXVR_MAX_POSITION) /* MXVR Maximum Node Position Register */ #define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION) #define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val) -#define pMXVR_DELAY ((uint16_t volatile *)MXVR_DELAY) /* MXVR Node Frame Delay Register */ #define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY) #define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val) -#define pMXVR_MAX_DELAY ((uint16_t volatile *)MXVR_MAX_DELAY) /* MXVR Maximum Node Frame Delay Register */ #define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY) #define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val) -#define pMXVR_LADDR ((uint32_t volatile *)MXVR_LADDR) /* MXVR Logical Address Register */ #define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR) #define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val) -#define pMXVR_GADDR ((uint16_t volatile *)MXVR_GADDR) /* MXVR Group Address Register */ #define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR) #define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val) -#define pMXVR_AADDR ((uint32_t volatile *)MXVR_AADDR) /* MXVR Alternate Address Register */ #define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR) #define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val) -#define pMXVR_ALLOC_0 ((uint32_t volatile *)MXVR_ALLOC_0) /* MXVR Allocation Table Register 0 */ #define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0) #define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val) -#define pMXVR_ALLOC_1 ((uint32_t volatile *)MXVR_ALLOC_1) /* MXVR Allocation Table Register 1 */ #define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1) #define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val) -#define pMXVR_ALLOC_2 ((uint32_t volatile *)MXVR_ALLOC_2) /* MXVR Allocation Table Register 2 */ #define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2) #define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val) -#define pMXVR_ALLOC_3 ((uint32_t volatile *)MXVR_ALLOC_3) /* MXVR Allocation Table Register 3 */ #define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3) #define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val) -#define pMXVR_ALLOC_4 ((uint32_t volatile *)MXVR_ALLOC_4) /* MXVR Allocation Table Register 4 */ #define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4) #define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val) -#define pMXVR_ALLOC_5 ((uint32_t volatile *)MXVR_ALLOC_5) /* MXVR Allocation Table Register 5 */ #define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5) #define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val) -#define pMXVR_ALLOC_6 ((uint32_t volatile *)MXVR_ALLOC_6) /* MXVR Allocation Table Register 6 */ #define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6) #define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val) -#define pMXVR_ALLOC_7 ((uint32_t volatile *)MXVR_ALLOC_7) /* MXVR Allocation Table Register 7 */ #define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7) #define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val) -#define pMXVR_ALLOC_8 ((uint32_t volatile *)MXVR_ALLOC_8) /* MXVR Allocation Table Register 8 */ #define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8) #define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val) -#define pMXVR_ALLOC_9 ((uint32_t volatile *)MXVR_ALLOC_9) /* MXVR Allocation Table Register 9 */ #define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9) #define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val) -#define pMXVR_ALLOC_10 ((uint32_t volatile *)MXVR_ALLOC_10) /* MXVR Allocation Table Register 10 */ #define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10) #define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val) -#define pMXVR_ALLOC_11 ((uint32_t volatile *)MXVR_ALLOC_11) /* MXVR Allocation Table Register 11 */ #define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11) #define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val) -#define pMXVR_ALLOC_12 ((uint32_t volatile *)MXVR_ALLOC_12) /* MXVR Allocation Table Register 12 */ #define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12) #define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val) -#define pMXVR_ALLOC_13 ((uint32_t volatile *)MXVR_ALLOC_13) /* MXVR Allocation Table Register 13 */ #define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13) #define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val) -#define pMXVR_ALLOC_14 ((uint32_t volatile *)MXVR_ALLOC_14) /* MXVR Allocation Table Register 14 */ #define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14) #define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val) -#define pMXVR_SYNC_LCHAN_0 ((uint32_t volatile *)MXVR_SYNC_LCHAN_0) /* MXVR Sync Data Logical Channel Assign Register 0 */ #define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0) #define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val) -#define pMXVR_SYNC_LCHAN_1 ((uint32_t volatile *)MXVR_SYNC_LCHAN_1) /* MXVR Sync Data Logical Channel Assign Register 1 */ #define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1) #define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val) -#define pMXVR_SYNC_LCHAN_2 ((uint32_t volatile *)MXVR_SYNC_LCHAN_2) /* MXVR Sync Data Logical Channel Assign Register 2 */ #define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2) #define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val) -#define pMXVR_SYNC_LCHAN_3 ((uint32_t volatile *)MXVR_SYNC_LCHAN_3) /* MXVR Sync Data Logical Channel Assign Register 3 */ #define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3) #define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val) -#define pMXVR_SYNC_LCHAN_4 ((uint32_t volatile *)MXVR_SYNC_LCHAN_4) /* MXVR Sync Data Logical Channel Assign Register 4 */ #define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4) #define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val) -#define pMXVR_SYNC_LCHAN_5 ((uint32_t volatile *)MXVR_SYNC_LCHAN_5) /* MXVR Sync Data Logical Channel Assign Register 5 */ #define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5) #define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val) -#define pMXVR_SYNC_LCHAN_6 ((uint32_t volatile *)MXVR_SYNC_LCHAN_6) /* MXVR Sync Data Logical Channel Assign Register 6 */ #define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6) #define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val) -#define pMXVR_SYNC_LCHAN_7 ((uint32_t volatile *)MXVR_SYNC_LCHAN_7) /* MXVR Sync Data Logical Channel Assign Register 7 */ #define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7) #define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val) -#define pMXVR_DMA0_CONFIG ((uint32_t volatile *)MXVR_DMA0_CONFIG) /* MXVR Sync Data DMA0 Config Register */ #define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG) #define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val) -#define pMXVR_DMA0_START_ADDR ((void * volatile *)MXVR_DMA0_START_ADDR) /* MXVR Sync Data DMA0 Start Address */ #define bfin_read_MXVR_DMA0_START_ADDR() bfin_readPTR(MXVR_DMA0_START_ADDR) #define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_writePTR(MXVR_DMA0_START_ADDR, val) -#define pMXVR_DMA0_COUNT ((uint16_t volatile *)MXVR_DMA0_COUNT) /* MXVR Sync Data DMA0 Loop Count Register */ #define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT) #define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val) -#define pMXVR_DMA0_CURR_ADDR ((void * volatile *)MXVR_DMA0_CURR_ADDR) /* MXVR Sync Data DMA0 Current Address */ #define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_readPTR(MXVR_DMA0_CURR_ADDR) #define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_writePTR(MXVR_DMA0_CURR_ADDR, val) -#define pMXVR_DMA0_CURR_COUNT ((uint16_t volatile *)MXVR_DMA0_CURR_COUNT) /* MXVR Sync Data DMA0 Current Loop Count */ #define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT) #define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val) -#define pMXVR_DMA1_CONFIG ((uint32_t volatile *)MXVR_DMA1_CONFIG) /* MXVR Sync Data DMA1 Config Register */ #define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG) #define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val) -#define pMXVR_DMA1_START_ADDR ((void * volatile *)MXVR_DMA1_START_ADDR) /* MXVR Sync Data DMA1 Start Address */ #define bfin_read_MXVR_DMA1_START_ADDR() bfin_readPTR(MXVR_DMA1_START_ADDR) #define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_writePTR(MXVR_DMA1_START_ADDR, val) -#define pMXVR_DMA1_COUNT ((uint16_t volatile *)MXVR_DMA1_COUNT) /* MXVR Sync Data DMA1 Loop Count Register */ #define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT) #define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val) -#define pMXVR_DMA1_CURR_ADDR ((void * volatile *)MXVR_DMA1_CURR_ADDR) /* MXVR Sync Data DMA1 Current Address */ #define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_readPTR(MXVR_DMA1_CURR_ADDR) #define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_writePTR(MXVR_DMA1_CURR_ADDR, val) -#define pMXVR_DMA1_CURR_COUNT ((uint16_t volatile *)MXVR_DMA1_CURR_COUNT) /* MXVR Sync Data DMA1 Current Loop Count */ #define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT) #define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val) -#define pMXVR_DMA2_CONFIG ((uint32_t volatile *)MXVR_DMA2_CONFIG) /* MXVR Sync Data DMA2 Config Register */ #define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG) #define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val) -#define pMXVR_DMA2_START_ADDR ((void * volatile *)MXVR_DMA2_START_ADDR) /* MXVR Sync Data DMA2 Start Address */ #define bfin_read_MXVR_DMA2_START_ADDR() bfin_readPTR(MXVR_DMA2_START_ADDR) #define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_writePTR(MXVR_DMA2_START_ADDR, val) -#define pMXVR_DMA2_COUNT ((uint16_t volatile *)MXVR_DMA2_COUNT) /* MXVR Sync Data DMA2 Loop Count Register */ #define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT) #define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val) -#define pMXVR_DMA2_CURR_ADDR ((void * volatile *)MXVR_DMA2_CURR_ADDR) /* MXVR Sync Data DMA2 Current Address */ #define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_readPTR(MXVR_DMA2_CURR_ADDR) #define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_writePTR(MXVR_DMA2_CURR_ADDR, val) -#define pMXVR_DMA2_CURR_COUNT ((uint16_t volatile *)MXVR_DMA2_CURR_COUNT) /* MXVR Sync Data DMA2 Current Loop Count */ #define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT) #define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val) -#define pMXVR_DMA3_CONFIG ((uint32_t volatile *)MXVR_DMA3_CONFIG) /* MXVR Sync Data DMA3 Config Register */ #define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG) #define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val) -#define pMXVR_DMA3_START_ADDR ((void * volatile *)MXVR_DMA3_START_ADDR) /* MXVR Sync Data DMA3 Start Address */ #define bfin_read_MXVR_DMA3_START_ADDR() bfin_readPTR(MXVR_DMA3_START_ADDR) #define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_writePTR(MXVR_DMA3_START_ADDR, val) -#define pMXVR_DMA3_COUNT ((uint16_t volatile *)MXVR_DMA3_COUNT) /* MXVR Sync Data DMA3 Loop Count Register */ #define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT) #define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val) -#define pMXVR_DMA3_CURR_ADDR ((void * volatile *)MXVR_DMA3_CURR_ADDR) /* MXVR Sync Data DMA3 Current Address */ #define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_readPTR(MXVR_DMA3_CURR_ADDR) #define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_writePTR(MXVR_DMA3_CURR_ADDR, val) -#define pMXVR_DMA3_CURR_COUNT ((uint16_t volatile *)MXVR_DMA3_CURR_COUNT) /* MXVR Sync Data DMA3 Current Loop Count */ #define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT) #define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val) -#define pMXVR_DMA4_CONFIG ((uint32_t volatile *)MXVR_DMA4_CONFIG) /* MXVR Sync Data DMA4 Config Register */ #define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG) #define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val) -#define pMXVR_DMA4_START_ADDR ((void * volatile *)MXVR_DMA4_START_ADDR) /* MXVR Sync Data DMA4 Start Address */ #define bfin_read_MXVR_DMA4_START_ADDR() bfin_readPTR(MXVR_DMA4_START_ADDR) #define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_writePTR(MXVR_DMA4_START_ADDR, val) -#define pMXVR_DMA4_COUNT ((uint16_t volatile *)MXVR_DMA4_COUNT) /* MXVR Sync Data DMA4 Loop Count Register */ #define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT) #define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val) -#define pMXVR_DMA4_CURR_ADDR ((void * volatile *)MXVR_DMA4_CURR_ADDR) /* MXVR Sync Data DMA4 Current Address */ #define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_readPTR(MXVR_DMA4_CURR_ADDR) #define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_writePTR(MXVR_DMA4_CURR_ADDR, val) -#define pMXVR_DMA4_CURR_COUNT ((uint16_t volatile *)MXVR_DMA4_CURR_COUNT) /* MXVR Sync Data DMA4 Current Loop Count */ #define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT) #define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val) -#define pMXVR_DMA5_CONFIG ((uint32_t volatile *)MXVR_DMA5_CONFIG) /* MXVR Sync Data DMA5 Config Register */ #define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG) #define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val) -#define pMXVR_DMA5_START_ADDR ((void * volatile *)MXVR_DMA5_START_ADDR) /* MXVR Sync Data DMA5 Start Address */ #define bfin_read_MXVR_DMA5_START_ADDR() bfin_readPTR(MXVR_DMA5_START_ADDR) #define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_writePTR(MXVR_DMA5_START_ADDR, val) -#define pMXVR_DMA5_COUNT ((uint16_t volatile *)MXVR_DMA5_COUNT) /* MXVR Sync Data DMA5 Loop Count Register */ #define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT) #define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val) -#define pMXVR_DMA5_CURR_ADDR ((void * volatile *)MXVR_DMA5_CURR_ADDR) /* MXVR Sync Data DMA5 Current Address */ #define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_readPTR(MXVR_DMA5_CURR_ADDR) #define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_writePTR(MXVR_DMA5_CURR_ADDR, val) -#define pMXVR_DMA5_CURR_COUNT ((uint16_t volatile *)MXVR_DMA5_CURR_COUNT) /* MXVR Sync Data DMA5 Current Loop Count */ #define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT) #define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val) -#define pMXVR_DMA6_CONFIG ((uint32_t volatile *)MXVR_DMA6_CONFIG) /* MXVR Sync Data DMA6 Config Register */ #define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG) #define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val) -#define pMXVR_DMA6_START_ADDR ((void * volatile *)MXVR_DMA6_START_ADDR) /* MXVR Sync Data DMA6 Start Address */ #define bfin_read_MXVR_DMA6_START_ADDR() bfin_readPTR(MXVR_DMA6_START_ADDR) #define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_writePTR(MXVR_DMA6_START_ADDR, val) -#define pMXVR_DMA6_COUNT ((uint16_t volatile *)MXVR_DMA6_COUNT) /* MXVR Sync Data DMA6 Loop Count Register */ #define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT) #define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val) -#define pMXVR_DMA6_CURR_ADDR ((void * volatile *)MXVR_DMA6_CURR_ADDR) /* MXVR Sync Data DMA6 Current Address */ #define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_readPTR(MXVR_DMA6_CURR_ADDR) #define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_writePTR(MXVR_DMA6_CURR_ADDR, val) -#define pMXVR_DMA6_CURR_COUNT ((uint16_t volatile *)MXVR_DMA6_CURR_COUNT) /* MXVR Sync Data DMA6 Current Loop Count */ #define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT) #define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val) -#define pMXVR_DMA7_CONFIG ((uint32_t volatile *)MXVR_DMA7_CONFIG) /* MXVR Sync Data DMA7 Config Register */ #define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG) #define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val) -#define pMXVR_DMA7_START_ADDR ((void * volatile *)MXVR_DMA7_START_ADDR) /* MXVR Sync Data DMA7 Start Address */ #define bfin_read_MXVR_DMA7_START_ADDR() bfin_readPTR(MXVR_DMA7_START_ADDR) #define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_writePTR(MXVR_DMA7_START_ADDR, val) -#define pMXVR_DMA7_COUNT ((uint16_t volatile *)MXVR_DMA7_COUNT) /* MXVR Sync Data DMA7 Loop Count Register */ #define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT) #define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val) -#define pMXVR_DMA7_CURR_ADDR ((void * volatile *)MXVR_DMA7_CURR_ADDR) /* MXVR Sync Data DMA7 Current Address */ #define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_readPTR(MXVR_DMA7_CURR_ADDR) #define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_writePTR(MXVR_DMA7_CURR_ADDR, val) -#define pMXVR_DMA7_CURR_COUNT ((uint16_t volatile *)MXVR_DMA7_CURR_COUNT) /* MXVR Sync Data DMA7 Current Loop Count */ #define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT) #define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val) -#define pMXVR_AP_CTL ((uint16_t volatile *)MXVR_AP_CTL) /* MXVR Async Packet Control Register */ #define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL) #define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val) -#define pMXVR_APRB_START_ADDR ((void * volatile *)MXVR_APRB_START_ADDR) /* MXVR Async Packet RX Buffer Start Addr Register */ #define bfin_read_MXVR_APRB_START_ADDR() bfin_readPTR(MXVR_APRB_START_ADDR) #define bfin_write_MXVR_APRB_START_ADDR(val) bfin_writePTR(MXVR_APRB_START_ADDR, val) -#define pMXVR_APRB_CURR_ADDR ((void * volatile *)MXVR_APRB_CURR_ADDR) /* MXVR Async Packet RX Buffer Current Addr Register */ #define bfin_read_MXVR_APRB_CURR_ADDR() bfin_readPTR(MXVR_APRB_CURR_ADDR) #define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_writePTR(MXVR_APRB_CURR_ADDR, val) -#define pMXVR_APTB_START_ADDR ((void * volatile *)MXVR_APTB_START_ADDR) /* MXVR Async Packet TX Buffer Start Addr Register */ #define bfin_read_MXVR_APTB_START_ADDR() bfin_readPTR(MXVR_APTB_START_ADDR) #define bfin_write_MXVR_APTB_START_ADDR(val) bfin_writePTR(MXVR_APTB_START_ADDR, val) -#define pMXVR_APTB_CURR_ADDR ((void * volatile *)MXVR_APTB_CURR_ADDR) /* MXVR Async Packet TX Buffer Current Addr Register */ #define bfin_read_MXVR_APTB_CURR_ADDR() bfin_readPTR(MXVR_APTB_CURR_ADDR) #define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_writePTR(MXVR_APTB_CURR_ADDR, val) -#define pMXVR_CM_CTL ((uint32_t volatile *)MXVR_CM_CTL) /* MXVR Control Message Control Register */ #define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL) #define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val) -#define pMXVR_CMRB_START_ADDR ((void * volatile *)MXVR_CMRB_START_ADDR) /* MXVR Control Message RX Buffer Start Addr Register */ #define bfin_read_MXVR_CMRB_START_ADDR() bfin_readPTR(MXVR_CMRB_START_ADDR) #define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_writePTR(MXVR_CMRB_START_ADDR, val) -#define pMXVR_CMRB_CURR_ADDR ((void * volatile *)MXVR_CMRB_CURR_ADDR) /* MXVR Control Message RX Buffer Current Address */ #define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_readPTR(MXVR_CMRB_CURR_ADDR) #define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_writePTR(MXVR_CMRB_CURR_ADDR, val) -#define pMXVR_CMTB_START_ADDR ((void * volatile *)MXVR_CMTB_START_ADDR) /* MXVR Control Message TX Buffer Start Addr Register */ #define bfin_read_MXVR_CMTB_START_ADDR() bfin_readPTR(MXVR_CMTB_START_ADDR) #define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_writePTR(MXVR_CMTB_START_ADDR, val) -#define pMXVR_CMTB_CURR_ADDR ((void * volatile *)MXVR_CMTB_CURR_ADDR) /* MXVR Control Message TX Buffer Current Address */ #define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_readPTR(MXVR_CMTB_CURR_ADDR) #define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_writePTR(MXVR_CMTB_CURR_ADDR, val) -#define pMXVR_RRDB_START_ADDR ((void * volatile *)MXVR_RRDB_START_ADDR) /* MXVR Remote Read Buffer Start Addr Register */ #define bfin_read_MXVR_RRDB_START_ADDR() bfin_readPTR(MXVR_RRDB_START_ADDR) #define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_writePTR(MXVR_RRDB_START_ADDR, val) -#define pMXVR_RRDB_CURR_ADDR ((void * volatile *)MXVR_RRDB_CURR_ADDR) /* MXVR Remote Read Buffer Current Addr Register */ #define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_readPTR(MXVR_RRDB_CURR_ADDR) #define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_writePTR(MXVR_RRDB_CURR_ADDR, val) -#define pMXVR_PAT_DATA_0 ((uint32_t volatile *)MXVR_PAT_DATA_0) /* MXVR Pattern Data Register 0 */ #define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0) #define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val) -#define pMXVR_PAT_EN_0 ((uint32_t volatile *)MXVR_PAT_EN_0) /* MXVR Pattern Enable Register 0 */ #define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0) #define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val) -#define pMXVR_PAT_DATA_1 ((uint32_t volatile *)MXVR_PAT_DATA_1) /* MXVR Pattern Data Register 1 */ #define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1) #define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val) -#define pMXVR_PAT_EN_1 ((uint32_t volatile *)MXVR_PAT_EN_1) /* MXVR Pattern Enable Register 1 */ #define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1) #define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val) -#define pMXVR_FRAME_CNT_0 ((uint16_t volatile *)MXVR_FRAME_CNT_0) /* MXVR Frame Counter 0 */ #define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0) #define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val) -#define pMXVR_FRAME_CNT_1 ((uint16_t volatile *)MXVR_FRAME_CNT_1) /* MXVR Frame Counter 1 */ #define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1) #define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val) -#define pMXVR_ROUTING_0 ((uint32_t volatile *)MXVR_ROUTING_0) /* MXVR Routing Table Register 0 */ #define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0) #define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val) -#define pMXVR_ROUTING_1 ((uint32_t volatile *)MXVR_ROUTING_1) /* MXVR Routing Table Register 1 */ #define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1) #define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val) -#define pMXVR_ROUTING_2 ((uint32_t volatile *)MXVR_ROUTING_2) /* MXVR Routing Table Register 2 */ #define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2) #define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val) -#define pMXVR_ROUTING_3 ((uint32_t volatile *)MXVR_ROUTING_3) /* MXVR Routing Table Register 3 */ #define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3) #define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val) -#define pMXVR_ROUTING_4 ((uint32_t volatile *)MXVR_ROUTING_4) /* MXVR Routing Table Register 4 */ #define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4) #define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val) -#define pMXVR_ROUTING_5 ((uint32_t volatile *)MXVR_ROUTING_5) /* MXVR Routing Table Register 5 */ #define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5) #define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val) -#define pMXVR_ROUTING_6 ((uint32_t volatile *)MXVR_ROUTING_6) /* MXVR Routing Table Register 6 */ #define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6) #define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val) -#define pMXVR_ROUTING_7 ((uint32_t volatile *)MXVR_ROUTING_7) /* MXVR Routing Table Register 7 */ #define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7) #define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val) -#define pMXVR_ROUTING_8 ((uint32_t volatile *)MXVR_ROUTING_8) /* MXVR Routing Table Register 8 */ #define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8) #define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val) -#define pMXVR_ROUTING_9 ((uint32_t volatile *)MXVR_ROUTING_9) /* MXVR Routing Table Register 9 */ #define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9) #define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val) -#define pMXVR_ROUTING_10 ((uint32_t volatile *)MXVR_ROUTING_10) /* MXVR Routing Table Register 10 */ #define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10) #define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val) -#define pMXVR_ROUTING_11 ((uint32_t volatile *)MXVR_ROUTING_11) /* MXVR Routing Table Register 11 */ #define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11) #define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val) -#define pMXVR_ROUTING_12 ((uint32_t volatile *)MXVR_ROUTING_12) /* MXVR Routing Table Register 12 */ #define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12) #define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val) -#define pMXVR_ROUTING_13 ((uint32_t volatile *)MXVR_ROUTING_13) /* MXVR Routing Table Register 13 */ #define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13) #define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val) -#define pMXVR_ROUTING_14 ((uint32_t volatile *)MXVR_ROUTING_14) /* MXVR Routing Table Register 14 */ #define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14) #define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val) -#define pMXVR_BLOCK_CNT ((uint16_t volatile *)MXVR_BLOCK_CNT) /* MXVR Block Counter */ #define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT) #define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val) -#define pMXVR_CLK_CTL ((uint32_t volatile *)MXVR_CLK_CTL) /* MXVR Clock Control Register */ #define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL) #define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val) -#define pMXVR_CDRPLL_CTL ((uint32_t volatile *)MXVR_CDRPLL_CTL) /* MXVR Clock/Data Recovery PLL Control Register */ #define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL) #define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val) -#define pMXVR_FMPLL_CTL ((uint32_t volatile *)MXVR_FMPLL_CTL) /* MXVR Frequency Multiply PLL Control Register */ #define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL) #define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val) -#define pMXVR_PIN_CTL ((uint16_t volatile *)MXVR_PIN_CTL) /* MXVR Pin Control Register */ #define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL) #define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val) -#define pMXVR_SCLK_CNT ((uint16_t volatile *)MXVR_SCLK_CNT) /* MXVR System Clock Counter Register */ #define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) #define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) -#define pKPAD_CTL ((uint16_t volatile *)KPAD_CTL) /* Controls keypad module enable and disable */ #define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) #define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) -#define pKPAD_PRESCALE ((uint16_t volatile *)KPAD_PRESCALE) /* Establish a time base for programing the KPAD_MSEL register */ #define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) #define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) -#define pKPAD_MSEL ((uint16_t volatile *)KPAD_MSEL) /* Selects delay parameters for keypad interface sensitivity */ #define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) #define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) -#define pKPAD_ROWCOL ((uint16_t volatile *)KPAD_ROWCOL) /* Captures the row and column output values of the keys pressed */ #define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) #define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) -#define pKPAD_STAT ((uint16_t volatile *)KPAD_STAT) /* Holds and clears the status of the keypad interface interrupt */ #define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) #define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) -#define pKPAD_SOFTEVAL ((uint16_t volatile *)KPAD_SOFTEVAL) /* Lets software force keypad interface to check for keys being pressed */ #define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) #define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) -#define pSDH_PWR_CTL ((uint16_t volatile *)SDH_PWR_CTL) /* SDH Power Control */ #define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) #define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) -#define pSDH_CLK_CTL ((uint16_t volatile *)SDH_CLK_CTL) /* SDH Clock Control */ #define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) #define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) -#define pSDH_ARGUMENT ((uint32_t volatile *)SDH_ARGUMENT) /* SDH Argument */ #define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) #define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) -#define pSDH_COMMAND ((uint16_t volatile *)SDH_COMMAND) /* SDH Command */ #define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) #define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) -#define pSDH_RESP_CMD ((uint16_t volatile *)SDH_RESP_CMD) /* SDH Response Command */ #define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) #define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) -#define pSDH_RESPONSE0 ((uint32_t volatile *)SDH_RESPONSE0) /* SDH Response0 */ #define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) #define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) -#define pSDH_RESPONSE1 ((uint32_t volatile *)SDH_RESPONSE1) /* SDH Response1 */ #define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) #define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) -#define pSDH_RESPONSE2 ((uint32_t volatile *)SDH_RESPONSE2) /* SDH Response2 */ #define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) #define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) -#define pSDH_RESPONSE3 ((uint32_t volatile *)SDH_RESPONSE3) /* SDH Response3 */ #define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) #define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) -#define pSDH_DATA_TIMER ((uint32_t volatile *)SDH_DATA_TIMER) /* SDH Data Timer */ #define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) #define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) -#define pSDH_DATA_LGTH ((uint16_t volatile *)SDH_DATA_LGTH) /* SDH Data Length */ #define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) #define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) -#define pSDH_DATA_CTL ((uint16_t volatile *)SDH_DATA_CTL) /* SDH Data Control */ #define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) #define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) -#define pSDH_DATA_CNT ((uint16_t volatile *)SDH_DATA_CNT) /* SDH Data Counter */ #define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) #define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) -#define pSDH_STATUS ((uint32_t volatile *)SDH_STATUS) /* SDH Status */ #define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) #define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) -#define pSDH_STATUS_CLR ((uint16_t volatile *)SDH_STATUS_CLR) /* SDH Status Clear */ #define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) #define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) -#define pSDH_MASK0 ((uint32_t volatile *)SDH_MASK0) /* SDH Interrupt0 Mask */ #define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) #define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) -#define pSDH_MASK1 ((uint32_t volatile *)SDH_MASK1) /* SDH Interrupt1 Mask */ #define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) #define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) -#define pSDH_FIFO_CNT ((uint16_t volatile *)SDH_FIFO_CNT) /* SDH FIFO Counter */ #define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) #define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) -#define pSDH_FIFO ((uint32_t volatile *)SDH_FIFO) /* SDH Data FIFO */ #define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) #define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) -#define pSDH_E_STATUS ((uint16_t volatile *)SDH_E_STATUS) /* SDH Exception Status */ #define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) #define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) -#define pSDH_E_MASK ((uint16_t volatile *)SDH_E_MASK) /* SDH Exception Mask */ #define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) #define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) -#define pSDH_CFG ((uint16_t volatile *)SDH_CFG) /* SDH Configuration */ #define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) #define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) -#define pSDH_RD_WAIT_EN ((uint16_t volatile *)SDH_RD_WAIT_EN) /* SDH Read Wait Enable */ #define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) #define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) -#define pSDH_PID0 ((uint16_t volatile *)SDH_PID0) /* SDH Peripheral Identification0 */ #define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) #define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) -#define pSDH_PID1 ((uint16_t volatile *)SDH_PID1) /* SDH Peripheral Identification1 */ #define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) #define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) -#define pSDH_PID2 ((uint16_t volatile *)SDH_PID2) /* SDH Peripheral Identification2 */ #define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) #define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) -#define pSDH_PID3 ((uint16_t volatile *)SDH_PID3) /* SDH Peripheral Identification3 */ #define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) #define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) -#define pSDH_PID4 ((uint16_t volatile *)SDH_PID4) /* SDH Peripheral Identification4 */ #define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) #define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) -#define pSDH_PID5 ((uint16_t volatile *)SDH_PID5) /* SDH Peripheral Identification5 */ #define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) #define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) -#define pSDH_PID6 ((uint16_t volatile *)SDH_PID6) /* SDH Peripheral Identification6 */ #define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) #define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) -#define pSDH_PID7 ((uint16_t volatile *)SDH_PID7) /* SDH Peripheral Identification7 */ #define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) #define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) -#define pATAPI_CONTROL ((uint16_t volatile *)ATAPI_CONTROL) /* ATAPI Control Register */ #define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) #define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) -#define pATAPI_STATUS ((uint16_t volatile *)ATAPI_STATUS) /* ATAPI Status Register */ #define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) #define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) -#define pATAPI_DEV_ADDR ((uint16_t volatile *)ATAPI_DEV_ADDR) /* ATAPI Device Register Address */ #define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) #define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) -#define pATAPI_DEV_TXBUF ((uint16_t volatile *)ATAPI_DEV_TXBUF) /* ATAPI Device Register Write Data */ #define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) #define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) -#define pATAPI_DEV_RXBUF ((uint16_t volatile *)ATAPI_DEV_RXBUF) /* ATAPI Device Register Read Data */ #define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) #define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) -#define pATAPI_INT_MASK ((uint16_t volatile *)ATAPI_INT_MASK) /* ATAPI Interrupt Mask Register */ #define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) #define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) -#define pATAPI_INT_STATUS ((uint16_t volatile *)ATAPI_INT_STATUS) /* ATAPI Interrupt Status Register */ #define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) #define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) -#define pATAPI_XFER_LEN ((uint16_t volatile *)ATAPI_XFER_LEN) /* ATAPI Length of Transfer */ #define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) #define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) -#define pATAPI_LINE_STATUS ((uint16_t volatile *)ATAPI_LINE_STATUS) /* ATAPI Line Status */ #define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) #define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) -#define pATAPI_SM_STATE ((uint16_t volatile *)ATAPI_SM_STATE) /* ATAPI State Machine Status */ #define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) #define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) -#define pATAPI_TERMINATE ((uint16_t volatile *)ATAPI_TERMINATE) /* ATAPI Host Terminate */ #define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) #define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) -#define pATAPI_PIO_TFRCNT ((uint16_t volatile *)ATAPI_PIO_TFRCNT) /* ATAPI PIO mode transfer count */ #define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) #define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) -#define pATAPI_DMA_TFRCNT ((uint16_t volatile *)ATAPI_DMA_TFRCNT) /* ATAPI DMA mode transfer count */ #define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) #define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) -#define pATAPI_UMAIN_TFRCNT ((uint16_t volatile *)ATAPI_UMAIN_TFRCNT) /* ATAPI UDMAIN transfer count */ #define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) #define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) -#define pATAPI_UDMAOUT_TFRCNT ((uint16_t volatile *)ATAPI_UDMAOUT_TFRCNT) /* ATAPI UDMAOUT transfer count */ #define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) #define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) -#define pATAPI_REG_TIM_0 ((uint16_t volatile *)ATAPI_REG_TIM_0) /* ATAPI Register Transfer Timing 0 */ #define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) #define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) -#define pATAPI_PIO_TIM_0 ((uint16_t volatile *)ATAPI_PIO_TIM_0) /* ATAPI PIO Timing 0 Register */ #define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) #define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) -#define pATAPI_PIO_TIM_1 ((uint16_t volatile *)ATAPI_PIO_TIM_1) /* ATAPI PIO Timing 1 Register */ #define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) #define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) -#define pATAPI_MULTI_TIM_0 ((uint16_t volatile *)ATAPI_MULTI_TIM_0) /* ATAPI Multi-DMA Timing 0 Register */ #define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) #define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) -#define pATAPI_MULTI_TIM_1 ((uint16_t volatile *)ATAPI_MULTI_TIM_1) /* ATAPI Multi-DMA Timing 1 Register */ #define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) #define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) -#define pATAPI_MULTI_TIM_2 ((uint16_t volatile *)ATAPI_MULTI_TIM_2) /* ATAPI Multi-DMA Timing 2 Register */ #define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) #define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) -#define pATAPI_ULTRA_TIM_0 ((uint16_t volatile *)ATAPI_ULTRA_TIM_0) /* ATAPI Ultra-DMA Timing 0 Register */ #define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) #define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) -#define pATAPI_ULTRA_TIM_1 ((uint16_t volatile *)ATAPI_ULTRA_TIM_1) /* ATAPI Ultra-DMA Timing 1 Register */ #define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) #define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) -#define pATAPI_ULTRA_TIM_2 ((uint16_t volatile *)ATAPI_ULTRA_TIM_2) /* ATAPI Ultra-DMA Timing 2 Register */ #define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) #define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) -#define pATAPI_ULTRA_TIM_3 ((uint16_t volatile *)ATAPI_ULTRA_TIM_3) /* ATAPI Ultra-DMA Timing 3 Register */ #define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) #define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) -#define pNFC_CTL ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) #define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) -#define pNFC_STAT ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */ #define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) #define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) -#define pNFC_IRQSTAT ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */ #define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) #define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) -#define pNFC_IRQMASK ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */ #define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) #define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) -#define pNFC_ECC0 ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */ #define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) #define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) -#define pNFC_ECC1 ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */ #define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) #define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) -#define pNFC_ECC2 ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */ #define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) #define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) -#define pNFC_ECC3 ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */ #define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) #define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) -#define pNFC_COUNT ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */ #define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) #define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) -#define pNFC_RST ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */ #define bfin_read_NFC_RST() bfin_read16(NFC_RST) #define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) -#define pNFC_PGCTL ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */ #define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) #define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) -#define pNFC_READ ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */ #define bfin_read_NFC_READ() bfin_read16(NFC_READ) #define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) -#define pNFC_ADDR ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */ #define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) #define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) -#define pNFC_CMD ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */ #define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) #define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) -#define pNFC_DATA_WR ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */ #define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) #define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) -#define pNFC_DATA_RD ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */ #define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) #define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) -#define pEPPI0_STATUS ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */ #define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) #define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) -#define pEPPI0_HCOUNT ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */ #define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) #define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) -#define pEPPI0_HDELAY ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */ #define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) #define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) -#define pEPPI0_VCOUNT ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */ #define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) #define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) -#define pEPPI0_VDELAY ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */ #define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) #define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) -#define pEPPI0_FRAME ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */ #define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) #define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) -#define pEPPI0_LINE ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */ #define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) #define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) -#define pEPPI0_CLKDIV ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */ #define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) #define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) -#define pEPPI0_CONTROL ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */ #define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) #define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) -#define pEPPI0_FS1W_HBL ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) #define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) -#define pEPPI0_FS1P_AVPL ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ #define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) #define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) -#define pEPPI0_FS2W_LVB ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ #define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) #define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) -#define pEPPI0_FS2P_LAVF ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ #define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) #define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) -#define pEPPI0_CLIP ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */ #define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) #define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) -#define pEPPI1_STATUS ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */ #define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS) #define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val) -#define pEPPI1_HCOUNT ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */ #define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT) #define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val) -#define pEPPI1_HDELAY ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */ #define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY) #define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val) -#define pEPPI1_VCOUNT ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */ #define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT) #define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val) -#define pEPPI1_VDELAY ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */ #define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY) #define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val) -#define pEPPI1_FRAME ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */ #define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME) #define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val) -#define pEPPI1_LINE ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */ #define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE) #define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val) -#define pEPPI1_CLKDIV ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */ #define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV) #define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val) -#define pEPPI1_CONTROL ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */ #define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL) #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val) -#define pEPPI1_FS1W_HBL ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL) #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val) -#define pEPPI1_FS1P_AVPL ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */ #define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL) #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val) -#define pEPPI1_FS2W_LVB ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */ #define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB) #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val) -#define pEPPI1_FS2P_LAVF ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */ #define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF) #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val) -#define pEPPI1_CLIP ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */ #define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP) #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val) -#define pEPPI2_STATUS ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */ #define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS) #define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val) -#define pEPPI2_HCOUNT ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */ #define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT) #define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val) -#define pEPPI2_HDELAY ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */ #define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY) #define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val) -#define pEPPI2_VCOUNT ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */ #define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT) #define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val) -#define pEPPI2_VDELAY ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */ #define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY) #define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val) -#define pEPPI2_FRAME ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */ #define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME) #define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val) -#define pEPPI2_LINE ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */ #define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE) #define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val) -#define pEPPI2_CLKDIV ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */ #define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV) #define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val) -#define pEPPI2_CONTROL ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */ #define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL) #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val) -#define pEPPI2_FS1W_HBL ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */ #define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL) #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val) -#define pEPPI2_FS1P_AVPL ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */ #define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL) #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val) -#define pEPPI2_FS2W_LVB ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */ #define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB) #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val) -#define pEPPI2_FS2P_LAVF ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */ #define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF) #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val) -#define pEPPI2_CLIP ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */ #define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP) #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val) -#define pCAN0_MC1 ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */ #define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1) #define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val) -#define pCAN0_MD1 ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */ #define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1) #define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val) -#define pCAN0_TRS1 ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */ #define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1) #define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val) -#define pCAN0_TRR1 ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */ #define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1) #define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val) -#define pCAN0_TA1 ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */ #define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1) #define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val) -#define pCAN0_AA1 ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */ #define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1) #define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val) -#define pCAN0_RMP1 ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */ #define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1) #define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val) -#define pCAN0_RML1 ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */ #define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1) #define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val) -#define pCAN0_MBTIF1 ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1) #define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val) -#define pCAN0_MBRIF1 ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */ #define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1) #define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val) -#define pCAN0_MBIM1 ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */ #define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1) #define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val) -#define pCAN0_RFH1 ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */ #define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1) #define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val) -#define pCAN0_OPSS1 ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */ #define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1) #define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val) -#define pCAN0_MC2 ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */ #define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2) #define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val) -#define pCAN0_MD2 ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */ #define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2) #define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val) -#define pCAN0_TRS2 ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */ #define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2) #define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val) -#define pCAN0_TRR2 ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */ #define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2) #define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val) -#define pCAN0_TA2 ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */ #define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2) #define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val) -#define pCAN0_AA2 ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */ #define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2) #define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val) -#define pCAN0_RMP2 ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */ #define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2) #define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val) -#define pCAN0_RML2 ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */ #define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2) #define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val) -#define pCAN0_MBTIF2 ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2) #define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val) -#define pCAN0_MBRIF2 ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */ #define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2) #define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val) -#define pCAN0_MBIM2 ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */ #define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2) #define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val) -#define pCAN0_RFH2 ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */ #define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2) #define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val) -#define pCAN0_OPSS2 ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */ #define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2) #define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val) -#define pCAN0_CLOCK ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */ #define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK) #define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val) -#define pCAN0_TIMING ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */ #define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING) #define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val) -#define pCAN0_DEBUG ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */ #define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG) #define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val) -#define pCAN0_STATUS ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */ #define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS) #define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val) -#define pCAN0_CEC ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */ #define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC) #define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val) -#define pCAN0_GIS ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */ #define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS) #define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val) -#define pCAN0_GIM ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */ #define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM) #define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val) -#define pCAN0_GIF ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */ #define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF) #define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val) -#define pCAN0_CONTROL ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */ #define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL) #define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val) -#define pCAN0_INTR ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */ #define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR) #define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val) -#define pCAN0_MBTD ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */ #define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD) #define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val) -#define pCAN0_EWR ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */ #define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR) #define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val) -#define pCAN0_ESR ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */ #define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR) #define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val) -#define pCAN0_UCCNT ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */ #define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT) #define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val) -#define pCAN0_UCRC ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */ #define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC) #define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val) -#define pCAN0_UCCNF ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */ #define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF) #define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val) -#define pCAN0_AM00L ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */ #define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L) #define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val) -#define pCAN0_AM00H ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H) #define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val) -#define pCAN0_AM01L ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */ #define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L) #define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val) -#define pCAN0_AM01H ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H) #define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val) -#define pCAN0_AM02L ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */ #define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L) #define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val) -#define pCAN0_AM02H ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H) #define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val) -#define pCAN0_AM03L ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */ #define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L) #define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val) -#define pCAN0_AM03H ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H) #define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val) -#define pCAN0_AM04L ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */ #define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L) #define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val) -#define pCAN0_AM04H ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H) #define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val) -#define pCAN0_AM05L ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */ #define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L) #define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val) -#define pCAN0_AM05H ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H) #define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val) -#define pCAN0_AM06L ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */ #define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L) #define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val) -#define pCAN0_AM06H ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H) #define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val) -#define pCAN0_AM07L ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */ #define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L) #define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val) -#define pCAN0_AM07H ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H) #define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val) -#define pCAN0_AM08L ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */ #define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L) #define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val) -#define pCAN0_AM08H ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H) #define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val) -#define pCAN0_AM09L ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */ #define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L) #define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val) -#define pCAN0_AM09H ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H) #define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val) -#define pCAN0_AM10L ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */ #define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L) #define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val) -#define pCAN0_AM10H ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H) #define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val) -#define pCAN0_AM11L ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */ #define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L) #define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val) -#define pCAN0_AM11H ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H) #define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val) -#define pCAN0_AM12L ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */ #define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L) #define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val) -#define pCAN0_AM12H ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H) #define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val) -#define pCAN0_AM13L ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */ #define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L) #define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val) -#define pCAN0_AM13H ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H) #define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val) -#define pCAN0_AM14L ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */ #define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L) #define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val) -#define pCAN0_AM14H ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H) #define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val) -#define pCAN0_AM15L ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */ #define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L) #define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val) -#define pCAN0_AM15H ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H) #define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val) -#define pCAN0_AM16L ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */ #define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L) #define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val) -#define pCAN0_AM16H ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H) #define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val) -#define pCAN0_AM17L ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */ #define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L) #define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val) -#define pCAN0_AM17H ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H) #define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val) -#define pCAN0_AM18L ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */ #define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L) #define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val) -#define pCAN0_AM18H ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H) #define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val) -#define pCAN0_AM19L ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */ #define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L) #define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val) -#define pCAN0_AM19H ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H) #define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val) -#define pCAN0_AM20L ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */ #define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L) #define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val) -#define pCAN0_AM20H ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H) #define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val) -#define pCAN0_AM21L ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */ #define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L) #define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val) -#define pCAN0_AM21H ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H) #define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val) -#define pCAN0_AM22L ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */ #define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L) #define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val) -#define pCAN0_AM22H ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H) #define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val) -#define pCAN0_AM23L ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */ #define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L) #define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val) -#define pCAN0_AM23H ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H) #define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val) -#define pCAN0_AM24L ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */ #define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L) #define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val) -#define pCAN0_AM24H ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H) #define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val) -#define pCAN0_AM25L ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */ #define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L) #define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val) -#define pCAN0_AM25H ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H) #define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val) -#define pCAN0_AM26L ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */ #define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L) #define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val) -#define pCAN0_AM26H ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H) #define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val) -#define pCAN0_AM27L ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */ #define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L) #define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val) -#define pCAN0_AM27H ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H) #define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val) -#define pCAN0_AM28L ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */ #define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L) #define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val) -#define pCAN0_AM28H ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H) #define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val) -#define pCAN0_AM29L ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */ #define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L) #define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val) -#define pCAN0_AM29H ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H) #define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val) -#define pCAN0_AM30L ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */ #define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L) #define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val) -#define pCAN0_AM30H ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H) #define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val) -#define pCAN0_AM31L ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */ #define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L) #define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val) -#define pCAN0_AM31H ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */ #define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H) #define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val) -#define pCAN0_MB00_DATA0 ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */ #define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0) #define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val) -#define pCAN0_MB00_DATA1 ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */ #define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1) #define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val) -#define pCAN0_MB00_DATA2 ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */ #define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2) #define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val) -#define pCAN0_MB00_DATA3 ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */ #define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3) #define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val) -#define pCAN0_MB00_LENGTH ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */ #define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH) #define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val) -#define pCAN0_MB00_TIMESTAMP ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */ #define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP) #define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val) -#define pCAN0_MB00_ID0 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */ #define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0) #define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val) -#define pCAN0_MB00_ID1 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */ #define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1) #define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val) -#define pCAN0_MB01_DATA0 ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */ #define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0) #define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val) -#define pCAN0_MB01_DATA1 ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */ #define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1) #define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val) -#define pCAN0_MB01_DATA2 ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */ #define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2) #define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val) -#define pCAN0_MB01_DATA3 ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */ #define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3) #define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val) -#define pCAN0_MB01_LENGTH ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */ #define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH) #define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val) -#define pCAN0_MB01_TIMESTAMP ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */ #define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP) #define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val) -#define pCAN0_MB01_ID0 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */ #define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0) #define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val) -#define pCAN0_MB01_ID1 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */ #define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1) #define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val) -#define pCAN0_MB02_DATA0 ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */ #define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0) #define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val) -#define pCAN0_MB02_DATA1 ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */ #define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1) #define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val) -#define pCAN0_MB02_DATA2 ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */ #define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2) #define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val) -#define pCAN0_MB02_DATA3 ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */ #define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3) #define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val) -#define pCAN0_MB02_LENGTH ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */ #define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH) #define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val) -#define pCAN0_MB02_TIMESTAMP ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */ #define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP) #define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val) -#define pCAN0_MB02_ID0 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */ #define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0) #define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val) -#define pCAN0_MB02_ID1 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */ #define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1) #define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val) -#define pCAN0_MB03_DATA0 ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */ #define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0) #define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val) -#define pCAN0_MB03_DATA1 ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */ #define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1) #define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val) -#define pCAN0_MB03_DATA2 ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */ #define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2) #define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val) -#define pCAN0_MB03_DATA3 ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */ #define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3) #define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val) -#define pCAN0_MB03_LENGTH ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */ #define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH) #define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val) -#define pCAN0_MB03_TIMESTAMP ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */ #define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP) #define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val) -#define pCAN0_MB03_ID0 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */ #define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0) #define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val) -#define pCAN0_MB03_ID1 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */ #define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1) #define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val) -#define pCAN0_MB04_DATA0 ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */ #define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0) #define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val) -#define pCAN0_MB04_DATA1 ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */ #define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1) #define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val) -#define pCAN0_MB04_DATA2 ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */ #define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2) #define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val) -#define pCAN0_MB04_DATA3 ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */ #define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3) #define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val) -#define pCAN0_MB04_LENGTH ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */ #define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH) #define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val) -#define pCAN0_MB04_TIMESTAMP ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */ #define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP) #define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val) -#define pCAN0_MB04_ID0 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */ #define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0) #define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val) -#define pCAN0_MB04_ID1 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */ #define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1) #define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val) -#define pCAN0_MB05_DATA0 ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */ #define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0) #define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val) -#define pCAN0_MB05_DATA1 ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */ #define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1) #define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val) -#define pCAN0_MB05_DATA2 ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */ #define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2) #define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val) -#define pCAN0_MB05_DATA3 ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */ #define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3) #define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val) -#define pCAN0_MB05_LENGTH ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */ #define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH) #define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val) -#define pCAN0_MB05_TIMESTAMP ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */ #define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP) #define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val) -#define pCAN0_MB05_ID0 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */ #define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0) #define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val) -#define pCAN0_MB05_ID1 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */ #define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1) #define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val) -#define pCAN0_MB06_DATA0 ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */ #define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0) #define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val) -#define pCAN0_MB06_DATA1 ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */ #define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1) #define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val) -#define pCAN0_MB06_DATA2 ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */ #define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2) #define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val) -#define pCAN0_MB06_DATA3 ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */ #define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3) #define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val) -#define pCAN0_MB06_LENGTH ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */ #define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH) #define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val) -#define pCAN0_MB06_TIMESTAMP ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */ #define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP) #define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val) -#define pCAN0_MB06_ID0 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */ #define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0) #define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val) -#define pCAN0_MB06_ID1 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */ #define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1) #define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val) -#define pCAN0_MB07_DATA0 ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */ #define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0) #define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val) -#define pCAN0_MB07_DATA1 ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */ #define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1) #define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val) -#define pCAN0_MB07_DATA2 ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */ #define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2) #define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val) -#define pCAN0_MB07_DATA3 ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */ #define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3) #define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val) -#define pCAN0_MB07_LENGTH ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */ #define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH) #define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val) -#define pCAN0_MB07_TIMESTAMP ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */ #define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP) #define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val) -#define pCAN0_MB07_ID0 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */ #define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0) #define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val) -#define pCAN0_MB07_ID1 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */ #define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1) #define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val) -#define pCAN0_MB08_DATA0 ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */ #define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0) #define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val) -#define pCAN0_MB08_DATA1 ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */ #define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1) #define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val) -#define pCAN0_MB08_DATA2 ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */ #define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2) #define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val) -#define pCAN0_MB08_DATA3 ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */ #define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3) #define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val) -#define pCAN0_MB08_LENGTH ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */ #define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH) #define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val) -#define pCAN0_MB08_TIMESTAMP ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */ #define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP) #define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val) -#define pCAN0_MB08_ID0 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */ #define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0) #define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val) -#define pCAN0_MB08_ID1 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */ #define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1) #define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val) -#define pCAN0_MB09_DATA0 ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */ #define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0) #define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val) -#define pCAN0_MB09_DATA1 ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */ #define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1) #define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val) -#define pCAN0_MB09_DATA2 ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */ #define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2) #define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val) -#define pCAN0_MB09_DATA3 ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */ #define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3) #define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val) -#define pCAN0_MB09_LENGTH ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */ #define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH) #define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val) -#define pCAN0_MB09_TIMESTAMP ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */ #define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP) #define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val) -#define pCAN0_MB09_ID0 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */ #define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0) #define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val) -#define pCAN0_MB09_ID1 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */ #define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1) #define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val) -#define pCAN0_MB10_DATA0 ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */ #define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0) #define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val) -#define pCAN0_MB10_DATA1 ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */ #define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1) #define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val) -#define pCAN0_MB10_DATA2 ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */ #define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2) #define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val) -#define pCAN0_MB10_DATA3 ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */ #define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3) #define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val) -#define pCAN0_MB10_LENGTH ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */ #define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH) #define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val) -#define pCAN0_MB10_TIMESTAMP ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */ #define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP) #define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val) -#define pCAN0_MB10_ID0 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */ #define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0) #define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val) -#define pCAN0_MB10_ID1 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */ #define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1) #define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val) -#define pCAN0_MB11_DATA0 ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */ #define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0) #define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val) -#define pCAN0_MB11_DATA1 ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */ #define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1) #define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val) -#define pCAN0_MB11_DATA2 ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */ #define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2) #define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val) -#define pCAN0_MB11_DATA3 ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */ #define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3) #define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val) -#define pCAN0_MB11_LENGTH ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */ #define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH) #define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val) -#define pCAN0_MB11_TIMESTAMP ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */ #define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP) #define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val) -#define pCAN0_MB11_ID0 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */ #define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0) #define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val) -#define pCAN0_MB11_ID1 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */ #define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1) #define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val) -#define pCAN0_MB12_DATA0 ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */ #define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0) #define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val) -#define pCAN0_MB12_DATA1 ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */ #define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1) #define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val) -#define pCAN0_MB12_DATA2 ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */ #define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2) #define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val) -#define pCAN0_MB12_DATA3 ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */ #define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3) #define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val) -#define pCAN0_MB12_LENGTH ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */ #define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH) #define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val) -#define pCAN0_MB12_TIMESTAMP ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */ #define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP) #define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val) -#define pCAN0_MB12_ID0 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */ #define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0) #define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val) -#define pCAN0_MB12_ID1 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */ #define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1) #define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val) -#define pCAN0_MB13_DATA0 ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */ #define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0) #define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val) -#define pCAN0_MB13_DATA1 ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */ #define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1) #define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val) -#define pCAN0_MB13_DATA2 ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */ #define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2) #define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val) -#define pCAN0_MB13_DATA3 ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */ #define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3) #define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val) -#define pCAN0_MB13_LENGTH ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */ #define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH) #define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val) -#define pCAN0_MB13_TIMESTAMP ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */ #define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP) #define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val) -#define pCAN0_MB13_ID0 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */ #define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0) #define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val) -#define pCAN0_MB13_ID1 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */ #define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1) #define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val) -#define pCAN0_MB14_DATA0 ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */ #define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0) #define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val) -#define pCAN0_MB14_DATA1 ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */ #define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1) #define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val) -#define pCAN0_MB14_DATA2 ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */ #define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2) #define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val) -#define pCAN0_MB14_DATA3 ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */ #define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3) #define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val) -#define pCAN0_MB14_LENGTH ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */ #define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH) #define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val) -#define pCAN0_MB14_TIMESTAMP ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */ #define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP) #define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val) -#define pCAN0_MB14_ID0 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */ #define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0) #define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val) -#define pCAN0_MB14_ID1 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */ #define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1) #define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val) -#define pCAN0_MB15_DATA0 ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */ #define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0) #define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val) -#define pCAN0_MB15_DATA1 ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */ #define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1) #define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val) -#define pCAN0_MB15_DATA2 ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */ #define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2) #define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val) -#define pCAN0_MB15_DATA3 ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */ #define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3) #define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val) -#define pCAN0_MB15_LENGTH ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */ #define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH) #define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val) -#define pCAN0_MB15_TIMESTAMP ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */ #define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP) #define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val) -#define pCAN0_MB15_ID0 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */ #define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0) #define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val) -#define pCAN0_MB15_ID1 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */ #define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1) #define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val) -#define pCAN0_MB16_DATA0 ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */ #define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0) #define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val) -#define pCAN0_MB16_DATA1 ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */ #define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1) #define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val) -#define pCAN0_MB16_DATA2 ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */ #define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2) #define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val) -#define pCAN0_MB16_DATA3 ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */ #define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3) #define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val) -#define pCAN0_MB16_LENGTH ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */ #define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH) #define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val) -#define pCAN0_MB16_TIMESTAMP ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */ #define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP) #define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val) -#define pCAN0_MB16_ID0 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */ #define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0) #define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val) -#define pCAN0_MB16_ID1 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */ #define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1) #define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val) -#define pCAN0_MB17_DATA0 ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */ #define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0) #define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val) -#define pCAN0_MB17_DATA1 ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */ #define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1) #define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val) -#define pCAN0_MB17_DATA2 ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */ #define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2) #define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val) -#define pCAN0_MB17_DATA3 ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */ #define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3) #define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val) -#define pCAN0_MB17_LENGTH ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */ #define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH) #define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val) -#define pCAN0_MB17_TIMESTAMP ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */ #define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP) #define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val) -#define pCAN0_MB17_ID0 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */ #define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0) #define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val) -#define pCAN0_MB17_ID1 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */ #define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1) #define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val) -#define pCAN0_MB18_DATA0 ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */ #define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0) #define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val) -#define pCAN0_MB18_DATA1 ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */ #define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1) #define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val) -#define pCAN0_MB18_DATA2 ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */ #define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2) #define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val) -#define pCAN0_MB18_DATA3 ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */ #define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3) #define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val) -#define pCAN0_MB18_LENGTH ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */ #define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH) #define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val) -#define pCAN0_MB18_TIMESTAMP ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */ #define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP) #define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val) -#define pCAN0_MB18_ID0 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */ #define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0) #define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val) -#define pCAN0_MB18_ID1 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */ #define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1) #define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val) -#define pCAN0_MB19_DATA0 ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */ #define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0) #define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val) -#define pCAN0_MB19_DATA1 ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */ #define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1) #define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val) -#define pCAN0_MB19_DATA2 ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */ #define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2) #define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val) -#define pCAN0_MB19_DATA3 ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */ #define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3) #define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val) -#define pCAN0_MB19_LENGTH ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */ #define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH) #define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val) -#define pCAN0_MB19_TIMESTAMP ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */ #define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP) #define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val) -#define pCAN0_MB19_ID0 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */ #define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0) #define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val) -#define pCAN0_MB19_ID1 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */ #define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1) #define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val) -#define pCAN0_MB20_DATA0 ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */ #define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0) #define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val) -#define pCAN0_MB20_DATA1 ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */ #define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1) #define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val) -#define pCAN0_MB20_DATA2 ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */ #define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2) #define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val) -#define pCAN0_MB20_DATA3 ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */ #define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3) #define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val) -#define pCAN0_MB20_LENGTH ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */ #define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH) #define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val) -#define pCAN0_MB20_TIMESTAMP ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */ #define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP) #define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val) -#define pCAN0_MB20_ID0 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */ #define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0) #define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val) -#define pCAN0_MB20_ID1 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */ #define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1) #define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val) -#define pCAN0_MB21_DATA0 ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */ #define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0) #define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val) -#define pCAN0_MB21_DATA1 ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */ #define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1) #define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val) -#define pCAN0_MB21_DATA2 ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */ #define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2) #define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val) -#define pCAN0_MB21_DATA3 ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */ #define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3) #define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val) -#define pCAN0_MB21_LENGTH ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */ #define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH) #define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val) -#define pCAN0_MB21_TIMESTAMP ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */ #define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP) #define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val) -#define pCAN0_MB21_ID0 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */ #define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0) #define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val) -#define pCAN0_MB21_ID1 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */ #define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1) #define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val) -#define pCAN0_MB22_DATA0 ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */ #define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0) #define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val) -#define pCAN0_MB22_DATA1 ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */ #define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1) #define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val) -#define pCAN0_MB22_DATA2 ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */ #define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2) #define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val) -#define pCAN0_MB22_DATA3 ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */ #define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3) #define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val) -#define pCAN0_MB22_LENGTH ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */ #define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH) #define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val) -#define pCAN0_MB22_TIMESTAMP ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */ #define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP) #define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val) -#define pCAN0_MB22_ID0 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */ #define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0) #define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val) -#define pCAN0_MB22_ID1 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */ #define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1) #define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val) -#define pCAN0_MB23_DATA0 ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */ #define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0) #define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val) -#define pCAN0_MB23_DATA1 ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */ #define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1) #define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val) -#define pCAN0_MB23_DATA2 ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */ #define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2) #define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val) -#define pCAN0_MB23_DATA3 ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */ #define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3) #define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val) -#define pCAN0_MB23_LENGTH ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */ #define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH) #define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val) -#define pCAN0_MB23_TIMESTAMP ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */ #define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP) #define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val) -#define pCAN0_MB23_ID0 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */ #define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0) #define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val) -#define pCAN0_MB23_ID1 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */ #define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1) #define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val) -#define pCAN0_MB24_DATA0 ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */ #define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0) #define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val) -#define pCAN0_MB24_DATA1 ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */ #define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1) #define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val) -#define pCAN0_MB24_DATA2 ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */ #define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2) #define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val) -#define pCAN0_MB24_DATA3 ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */ #define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3) #define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val) -#define pCAN0_MB24_LENGTH ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */ #define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH) #define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val) -#define pCAN0_MB24_TIMESTAMP ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */ #define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP) #define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val) -#define pCAN0_MB24_ID0 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */ #define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0) #define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val) -#define pCAN0_MB24_ID1 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */ #define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1) #define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val) -#define pCAN0_MB25_DATA0 ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */ #define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0) #define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val) -#define pCAN0_MB25_DATA1 ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */ #define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1) #define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val) -#define pCAN0_MB25_DATA2 ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */ #define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2) #define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val) -#define pCAN0_MB25_DATA3 ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */ #define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3) #define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val) -#define pCAN0_MB25_LENGTH ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */ #define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH) #define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val) -#define pCAN0_MB25_TIMESTAMP ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */ #define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP) #define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val) -#define pCAN0_MB25_ID0 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */ #define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0) #define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val) -#define pCAN0_MB25_ID1 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */ #define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1) #define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val) -#define pCAN0_MB26_DATA0 ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */ #define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0) #define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val) -#define pCAN0_MB26_DATA1 ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */ #define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1) #define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val) -#define pCAN0_MB26_DATA2 ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */ #define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2) #define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val) -#define pCAN0_MB26_DATA3 ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */ #define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3) #define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val) -#define pCAN0_MB26_LENGTH ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */ #define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH) #define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val) -#define pCAN0_MB26_TIMESTAMP ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */ #define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP) #define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val) -#define pCAN0_MB26_ID0 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */ #define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0) #define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val) -#define pCAN0_MB26_ID1 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */ #define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1) #define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val) -#define pCAN0_MB27_DATA0 ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */ #define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0) #define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val) -#define pCAN0_MB27_DATA1 ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */ #define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1) #define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val) -#define pCAN0_MB27_DATA2 ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */ #define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2) #define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val) -#define pCAN0_MB27_DATA3 ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */ #define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3) #define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val) -#define pCAN0_MB27_LENGTH ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */ #define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH) #define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val) -#define pCAN0_MB27_TIMESTAMP ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */ #define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP) #define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val) -#define pCAN0_MB27_ID0 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */ #define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0) #define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val) -#define pCAN0_MB27_ID1 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */ #define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1) #define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val) -#define pCAN0_MB28_DATA0 ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */ #define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0) #define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val) -#define pCAN0_MB28_DATA1 ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */ #define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1) #define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val) -#define pCAN0_MB28_DATA2 ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */ #define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2) #define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val) -#define pCAN0_MB28_DATA3 ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */ #define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3) #define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val) -#define pCAN0_MB28_LENGTH ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */ #define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH) #define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val) -#define pCAN0_MB28_TIMESTAMP ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */ #define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP) #define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val) -#define pCAN0_MB28_ID0 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */ #define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0) #define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val) -#define pCAN0_MB28_ID1 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */ #define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1) #define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val) -#define pCAN0_MB29_DATA0 ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */ #define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0) #define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val) -#define pCAN0_MB29_DATA1 ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */ #define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1) #define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val) -#define pCAN0_MB29_DATA2 ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */ #define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2) #define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val) -#define pCAN0_MB29_DATA3 ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */ #define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3) #define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val) -#define pCAN0_MB29_LENGTH ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */ #define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH) #define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val) -#define pCAN0_MB29_TIMESTAMP ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */ #define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP) #define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val) -#define pCAN0_MB29_ID0 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */ #define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0) #define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val) -#define pCAN0_MB29_ID1 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */ #define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1) #define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val) -#define pCAN0_MB30_DATA0 ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */ #define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0) #define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val) -#define pCAN0_MB30_DATA1 ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */ #define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1) #define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val) -#define pCAN0_MB30_DATA2 ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */ #define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2) #define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val) -#define pCAN0_MB30_DATA3 ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */ #define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3) #define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val) -#define pCAN0_MB30_LENGTH ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */ #define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH) #define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val) -#define pCAN0_MB30_TIMESTAMP ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */ #define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP) #define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val) -#define pCAN0_MB30_ID0 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */ #define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0) #define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val) -#define pCAN0_MB30_ID1 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */ #define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1) #define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val) -#define pCAN0_MB31_DATA0 ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */ #define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0) #define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val) -#define pCAN0_MB31_DATA1 ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */ #define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1) #define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val) -#define pCAN0_MB31_DATA2 ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */ #define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2) #define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val) -#define pCAN0_MB31_DATA3 ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */ #define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3) #define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val) -#define pCAN0_MB31_LENGTH ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */ #define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH) #define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val) -#define pCAN0_MB31_TIMESTAMP ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */ #define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP) #define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val) -#define pCAN0_MB31_ID0 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */ #define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0) #define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val) -#define pCAN0_MB31_ID1 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */ #define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1) #define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val) -#define pCAN1_MC1 ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */ #define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) #define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) -#define pCAN1_MD1 ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */ #define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) #define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) -#define pCAN1_TRS1 ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */ #define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) #define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) -#define pCAN1_TRR1 ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */ #define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) #define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) -#define pCAN1_TA1 ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */ #define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) #define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) -#define pCAN1_AA1 ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */ #define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) #define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) -#define pCAN1_RMP1 ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */ #define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) #define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) -#define pCAN1_RML1 ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */ #define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) #define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) -#define pCAN1_MBTIF1 ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ #define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) #define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) -#define pCAN1_MBRIF1 ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ #define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) #define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) -#define pCAN1_MBIM1 ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ #define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) #define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) -#define pCAN1_RFH1 ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ #define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) #define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) -#define pCAN1_OPSS1 ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ #define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) #define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) -#define pCAN1_MC2 ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */ #define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) #define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) -#define pCAN1_MD2 ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */ #define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) #define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) -#define pCAN1_TRS2 ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */ #define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) #define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) -#define pCAN1_TRR2 ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */ #define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) #define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) -#define pCAN1_TA2 ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */ #define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) #define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) -#define pCAN1_AA2 ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */ #define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) #define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) -#define pCAN1_RMP2 ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */ #define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) #define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) -#define pCAN1_RML2 ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */ #define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) #define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) -#define pCAN1_MBTIF2 ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ #define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) #define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) -#define pCAN1_MBRIF2 ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ #define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) #define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) -#define pCAN1_MBIM2 ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ #define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) #define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) -#define pCAN1_RFH2 ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ #define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) #define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) -#define pCAN1_OPSS2 ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ #define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) #define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) -#define pCAN1_CLOCK ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */ #define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) #define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) -#define pCAN1_TIMING ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */ #define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) #define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) -#define pCAN1_DEBUG ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */ #define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) #define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) -#define pCAN1_STATUS ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */ #define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) #define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) -#define pCAN1_CEC ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */ #define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) #define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) -#define pCAN1_GIS ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */ #define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) #define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) -#define pCAN1_GIM ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */ #define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) #define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) -#define pCAN1_GIF ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */ #define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) #define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) -#define pCAN1_CONTROL ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */ #define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) #define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) -#define pCAN1_INTR ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */ #define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) #define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) -#define pCAN1_MBTD ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */ #define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) #define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) -#define pCAN1_EWR ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */ #define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) #define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) -#define pCAN1_ESR ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */ #define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) #define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) -#define pCAN1_UCCNT ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */ #define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) #define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) -#define pCAN1_UCRC ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */ #define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) #define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) -#define pCAN1_UCCNF ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */ #define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) #define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) -#define pCAN1_AM00L ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ #define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) #define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) -#define pCAN1_AM00H ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) #define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) -#define pCAN1_AM01L ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ #define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) #define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) -#define pCAN1_AM01H ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) #define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) -#define pCAN1_AM02L ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ #define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) #define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) -#define pCAN1_AM02H ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) #define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) -#define pCAN1_AM03L ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ #define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) #define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) -#define pCAN1_AM03H ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) #define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) -#define pCAN1_AM04L ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ #define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) #define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) -#define pCAN1_AM04H ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) #define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) -#define pCAN1_AM05L ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ #define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) #define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) -#define pCAN1_AM05H ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) #define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) -#define pCAN1_AM06L ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ #define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) #define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) -#define pCAN1_AM06H ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) #define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) -#define pCAN1_AM07L ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ #define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) #define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) -#define pCAN1_AM07H ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) #define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) -#define pCAN1_AM08L ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ #define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) #define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) -#define pCAN1_AM08H ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) #define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) -#define pCAN1_AM09L ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ #define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) #define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) -#define pCAN1_AM09H ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) #define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) -#define pCAN1_AM10L ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ #define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) #define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) -#define pCAN1_AM10H ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) #define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) -#define pCAN1_AM11L ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ #define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) #define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) -#define pCAN1_AM11H ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) #define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) -#define pCAN1_AM12L ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ #define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) #define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) -#define pCAN1_AM12H ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) #define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) -#define pCAN1_AM13L ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ #define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) #define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) -#define pCAN1_AM13H ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) #define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) -#define pCAN1_AM14L ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ #define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) #define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) -#define pCAN1_AM14H ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) #define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) -#define pCAN1_AM15L ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ #define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) #define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) -#define pCAN1_AM15H ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) #define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) -#define pCAN1_AM16L ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ #define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) #define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) -#define pCAN1_AM16H ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) #define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) -#define pCAN1_AM17L ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ #define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) #define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) -#define pCAN1_AM17H ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) #define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) -#define pCAN1_AM18L ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ #define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) #define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) -#define pCAN1_AM18H ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) #define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) -#define pCAN1_AM19L ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ #define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) #define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) -#define pCAN1_AM19H ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) #define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) -#define pCAN1_AM20L ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ #define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) #define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) -#define pCAN1_AM20H ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) #define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) -#define pCAN1_AM21L ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ #define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) #define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) -#define pCAN1_AM21H ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) #define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) -#define pCAN1_AM22L ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ #define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) #define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) -#define pCAN1_AM22H ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) #define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) -#define pCAN1_AM23L ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ #define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) #define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) -#define pCAN1_AM23H ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) #define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) -#define pCAN1_AM24L ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ #define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) #define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) -#define pCAN1_AM24H ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) #define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) -#define pCAN1_AM25L ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ #define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) #define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) -#define pCAN1_AM25H ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) #define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) -#define pCAN1_AM26L ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ #define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) #define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) -#define pCAN1_AM26H ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) #define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) -#define pCAN1_AM27L ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ #define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) #define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) -#define pCAN1_AM27H ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) #define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) -#define pCAN1_AM28L ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ #define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) #define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) -#define pCAN1_AM28H ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) #define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) -#define pCAN1_AM29L ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ #define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) #define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) -#define pCAN1_AM29H ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) #define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) -#define pCAN1_AM30L ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ #define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) #define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) -#define pCAN1_AM30H ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) #define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) -#define pCAN1_AM31L ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ #define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) #define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) -#define pCAN1_AM31H ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ #define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) #define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) -#define pCAN1_MB00_DATA0 ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */ #define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) #define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) -#define pCAN1_MB00_DATA1 ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */ #define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) #define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) -#define pCAN1_MB00_DATA2 ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */ #define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) #define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) -#define pCAN1_MB00_DATA3 ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */ #define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) #define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) -#define pCAN1_MB00_LENGTH ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */ #define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) #define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) -#define pCAN1_MB00_TIMESTAMP ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */ #define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) #define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) -#define pCAN1_MB00_ID0 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */ #define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) #define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) -#define pCAN1_MB00_ID1 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */ #define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) #define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) -#define pCAN1_MB01_DATA0 ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */ #define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) #define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) -#define pCAN1_MB01_DATA1 ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */ #define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) #define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) -#define pCAN1_MB01_DATA2 ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */ #define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) #define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) -#define pCAN1_MB01_DATA3 ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */ #define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) #define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) -#define pCAN1_MB01_LENGTH ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */ #define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) #define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) -#define pCAN1_MB01_TIMESTAMP ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */ #define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) #define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) -#define pCAN1_MB01_ID0 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */ #define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) #define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) -#define pCAN1_MB01_ID1 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */ #define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) #define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) -#define pCAN1_MB02_DATA0 ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */ #define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) #define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) -#define pCAN1_MB02_DATA1 ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */ #define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) #define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) -#define pCAN1_MB02_DATA2 ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */ #define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) #define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) -#define pCAN1_MB02_DATA3 ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */ #define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) #define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) -#define pCAN1_MB02_LENGTH ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */ #define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) #define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) -#define pCAN1_MB02_TIMESTAMP ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */ #define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) #define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) -#define pCAN1_MB02_ID0 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */ #define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) #define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) -#define pCAN1_MB02_ID1 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */ #define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) #define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) -#define pCAN1_MB03_DATA0 ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */ #define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) #define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) -#define pCAN1_MB03_DATA1 ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */ #define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) #define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) -#define pCAN1_MB03_DATA2 ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */ #define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) #define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) -#define pCAN1_MB03_DATA3 ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */ #define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) #define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) -#define pCAN1_MB03_LENGTH ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */ #define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) #define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) -#define pCAN1_MB03_TIMESTAMP ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */ #define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) #define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) -#define pCAN1_MB03_ID0 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */ #define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) #define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) -#define pCAN1_MB03_ID1 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */ #define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) #define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) -#define pCAN1_MB04_DATA0 ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */ #define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) #define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) -#define pCAN1_MB04_DATA1 ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */ #define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) #define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) -#define pCAN1_MB04_DATA2 ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */ #define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) #define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) -#define pCAN1_MB04_DATA3 ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */ #define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) #define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) -#define pCAN1_MB04_LENGTH ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */ #define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) #define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) -#define pCAN1_MB04_TIMESTAMP ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */ #define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) #define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) -#define pCAN1_MB04_ID0 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */ #define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) #define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) -#define pCAN1_MB04_ID1 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */ #define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) #define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) -#define pCAN1_MB05_DATA0 ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */ #define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) #define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) -#define pCAN1_MB05_DATA1 ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */ #define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) #define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) -#define pCAN1_MB05_DATA2 ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */ #define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) #define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) -#define pCAN1_MB05_DATA3 ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */ #define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) #define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) -#define pCAN1_MB05_LENGTH ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */ #define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) #define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) -#define pCAN1_MB05_TIMESTAMP ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */ #define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) #define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) -#define pCAN1_MB05_ID0 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */ #define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) #define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) -#define pCAN1_MB05_ID1 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */ #define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) #define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) -#define pCAN1_MB06_DATA0 ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */ #define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) #define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) -#define pCAN1_MB06_DATA1 ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */ #define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) #define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) -#define pCAN1_MB06_DATA2 ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */ #define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) #define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) -#define pCAN1_MB06_DATA3 ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */ #define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) #define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) -#define pCAN1_MB06_LENGTH ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */ #define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) #define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) -#define pCAN1_MB06_TIMESTAMP ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */ #define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) #define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) -#define pCAN1_MB06_ID0 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */ #define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) #define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) -#define pCAN1_MB06_ID1 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */ #define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) #define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) -#define pCAN1_MB07_DATA0 ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */ #define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) #define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) -#define pCAN1_MB07_DATA1 ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */ #define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) #define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) -#define pCAN1_MB07_DATA2 ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */ #define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) #define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) -#define pCAN1_MB07_DATA3 ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */ #define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) #define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) -#define pCAN1_MB07_LENGTH ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */ #define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) #define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) -#define pCAN1_MB07_TIMESTAMP ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */ #define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) #define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) -#define pCAN1_MB07_ID0 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */ #define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) #define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) -#define pCAN1_MB07_ID1 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */ #define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) #define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) -#define pCAN1_MB08_DATA0 ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */ #define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) #define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) -#define pCAN1_MB08_DATA1 ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */ #define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) #define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) -#define pCAN1_MB08_DATA2 ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */ #define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) #define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) -#define pCAN1_MB08_DATA3 ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */ #define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) #define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) -#define pCAN1_MB08_LENGTH ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */ #define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) #define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) -#define pCAN1_MB08_TIMESTAMP ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */ #define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) #define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) -#define pCAN1_MB08_ID0 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */ #define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) #define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) -#define pCAN1_MB08_ID1 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */ #define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) #define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) -#define pCAN1_MB09_DATA0 ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */ #define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) #define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) -#define pCAN1_MB09_DATA1 ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */ #define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) #define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) -#define pCAN1_MB09_DATA2 ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */ #define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) #define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) -#define pCAN1_MB09_DATA3 ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */ #define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) #define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) -#define pCAN1_MB09_LENGTH ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */ #define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) #define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) -#define pCAN1_MB09_TIMESTAMP ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */ #define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) #define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) -#define pCAN1_MB09_ID0 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */ #define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) #define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) -#define pCAN1_MB09_ID1 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */ #define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) #define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) -#define pCAN1_MB10_DATA0 ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */ #define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) #define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) -#define pCAN1_MB10_DATA1 ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */ #define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) #define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) -#define pCAN1_MB10_DATA2 ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */ #define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) #define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) -#define pCAN1_MB10_DATA3 ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */ #define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) #define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) -#define pCAN1_MB10_LENGTH ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */ #define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) #define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) -#define pCAN1_MB10_TIMESTAMP ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */ #define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) #define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) -#define pCAN1_MB10_ID0 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */ #define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) #define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) -#define pCAN1_MB10_ID1 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */ #define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) #define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) -#define pCAN1_MB11_DATA0 ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */ #define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) #define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) -#define pCAN1_MB11_DATA1 ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */ #define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) #define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) -#define pCAN1_MB11_DATA2 ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */ #define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) #define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) -#define pCAN1_MB11_DATA3 ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */ #define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) #define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) -#define pCAN1_MB11_LENGTH ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */ #define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) #define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) -#define pCAN1_MB11_TIMESTAMP ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */ #define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) #define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) -#define pCAN1_MB11_ID0 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */ #define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) #define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) -#define pCAN1_MB11_ID1 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */ #define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) #define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) -#define pCAN1_MB12_DATA0 ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */ #define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) #define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) -#define pCAN1_MB12_DATA1 ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */ #define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) #define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) -#define pCAN1_MB12_DATA2 ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */ #define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) #define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) -#define pCAN1_MB12_DATA3 ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */ #define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) #define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) -#define pCAN1_MB12_LENGTH ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */ #define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) #define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) -#define pCAN1_MB12_TIMESTAMP ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */ #define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) #define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) -#define pCAN1_MB12_ID0 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */ #define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) #define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) -#define pCAN1_MB12_ID1 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */ #define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) #define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) -#define pCAN1_MB13_DATA0 ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */ #define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) #define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) -#define pCAN1_MB13_DATA1 ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */ #define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) #define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) -#define pCAN1_MB13_DATA2 ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */ #define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) #define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) -#define pCAN1_MB13_DATA3 ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */ #define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) #define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) -#define pCAN1_MB13_LENGTH ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */ #define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) #define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) -#define pCAN1_MB13_TIMESTAMP ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */ #define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) #define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) -#define pCAN1_MB13_ID0 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */ #define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) #define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) -#define pCAN1_MB13_ID1 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */ #define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) #define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) -#define pCAN1_MB14_DATA0 ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */ #define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) #define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) -#define pCAN1_MB14_DATA1 ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */ #define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) #define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) -#define pCAN1_MB14_DATA2 ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */ #define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) #define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) -#define pCAN1_MB14_DATA3 ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */ #define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) #define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) -#define pCAN1_MB14_LENGTH ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */ #define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) #define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) -#define pCAN1_MB14_TIMESTAMP ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */ #define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) #define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) -#define pCAN1_MB14_ID0 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */ #define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) #define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) -#define pCAN1_MB14_ID1 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */ #define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) #define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) -#define pCAN1_MB15_DATA0 ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */ #define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) #define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) -#define pCAN1_MB15_DATA1 ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */ #define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) #define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) -#define pCAN1_MB15_DATA2 ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */ #define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) #define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) -#define pCAN1_MB15_DATA3 ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */ #define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) #define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) -#define pCAN1_MB15_LENGTH ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */ #define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) #define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) -#define pCAN1_MB15_TIMESTAMP ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */ #define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) #define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) -#define pCAN1_MB15_ID0 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */ #define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) #define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) -#define pCAN1_MB15_ID1 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */ #define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) #define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) -#define pCAN1_MB16_DATA0 ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */ #define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) #define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) -#define pCAN1_MB16_DATA1 ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */ #define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) #define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) -#define pCAN1_MB16_DATA2 ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */ #define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) #define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) -#define pCAN1_MB16_DATA3 ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */ #define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) #define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) -#define pCAN1_MB16_LENGTH ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */ #define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) #define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) -#define pCAN1_MB16_TIMESTAMP ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */ #define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) #define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) -#define pCAN1_MB16_ID0 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */ #define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) #define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) -#define pCAN1_MB16_ID1 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */ #define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) #define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) -#define pCAN1_MB17_DATA0 ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */ #define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) #define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) -#define pCAN1_MB17_DATA1 ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */ #define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) #define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) -#define pCAN1_MB17_DATA2 ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */ #define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) #define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) -#define pCAN1_MB17_DATA3 ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */ #define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) #define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) -#define pCAN1_MB17_LENGTH ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */ #define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) #define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) -#define pCAN1_MB17_TIMESTAMP ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */ #define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) #define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) -#define pCAN1_MB17_ID0 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */ #define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) #define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) -#define pCAN1_MB17_ID1 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */ #define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) #define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) -#define pCAN1_MB18_DATA0 ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */ #define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) #define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) -#define pCAN1_MB18_DATA1 ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */ #define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) #define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) -#define pCAN1_MB18_DATA2 ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */ #define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) #define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) -#define pCAN1_MB18_DATA3 ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */ #define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) #define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) -#define pCAN1_MB18_LENGTH ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */ #define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) #define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) -#define pCAN1_MB18_TIMESTAMP ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */ #define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) #define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) -#define pCAN1_MB18_ID0 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */ #define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) #define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) -#define pCAN1_MB18_ID1 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */ #define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) #define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) -#define pCAN1_MB19_DATA0 ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */ #define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) #define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) -#define pCAN1_MB19_DATA1 ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */ #define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) #define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) -#define pCAN1_MB19_DATA2 ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */ #define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) #define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) -#define pCAN1_MB19_DATA3 ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */ #define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) #define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) -#define pCAN1_MB19_LENGTH ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */ #define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) #define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) -#define pCAN1_MB19_TIMESTAMP ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */ #define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) #define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) -#define pCAN1_MB19_ID0 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */ #define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) #define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) -#define pCAN1_MB19_ID1 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */ #define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) #define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) -#define pCAN1_MB20_DATA0 ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */ #define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) #define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) -#define pCAN1_MB20_DATA1 ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */ #define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) #define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) -#define pCAN1_MB20_DATA2 ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */ #define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) #define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) -#define pCAN1_MB20_DATA3 ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */ #define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) #define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) -#define pCAN1_MB20_LENGTH ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */ #define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) #define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) -#define pCAN1_MB20_TIMESTAMP ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */ #define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) #define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) -#define pCAN1_MB20_ID0 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */ #define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) #define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) -#define pCAN1_MB20_ID1 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */ #define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) #define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) -#define pCAN1_MB21_DATA0 ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */ #define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) #define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) -#define pCAN1_MB21_DATA1 ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */ #define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) #define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) -#define pCAN1_MB21_DATA2 ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */ #define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) #define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) -#define pCAN1_MB21_DATA3 ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */ #define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) #define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) -#define pCAN1_MB21_LENGTH ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */ #define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) #define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) -#define pCAN1_MB21_TIMESTAMP ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */ #define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) #define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) -#define pCAN1_MB21_ID0 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */ #define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) #define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) -#define pCAN1_MB21_ID1 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */ #define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) #define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) -#define pCAN1_MB22_DATA0 ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */ #define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) #define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) -#define pCAN1_MB22_DATA1 ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */ #define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) #define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) -#define pCAN1_MB22_DATA2 ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */ #define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) #define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) -#define pCAN1_MB22_DATA3 ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */ #define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) #define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) -#define pCAN1_MB22_LENGTH ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */ #define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) #define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) -#define pCAN1_MB22_TIMESTAMP ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */ #define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) #define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) -#define pCAN1_MB22_ID0 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */ #define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) #define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) -#define pCAN1_MB22_ID1 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */ #define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) #define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) -#define pCAN1_MB23_DATA0 ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */ #define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) #define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) -#define pCAN1_MB23_DATA1 ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */ #define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) #define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) -#define pCAN1_MB23_DATA2 ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */ #define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) #define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) -#define pCAN1_MB23_DATA3 ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */ #define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) #define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) -#define pCAN1_MB23_LENGTH ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */ #define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) #define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) -#define pCAN1_MB23_TIMESTAMP ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */ #define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) #define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) -#define pCAN1_MB23_ID0 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */ #define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) #define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) -#define pCAN1_MB23_ID1 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */ #define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) #define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) -#define pCAN1_MB24_DATA0 ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */ #define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) #define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) -#define pCAN1_MB24_DATA1 ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */ #define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) #define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) -#define pCAN1_MB24_DATA2 ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */ #define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) #define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) -#define pCAN1_MB24_DATA3 ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */ #define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) #define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) -#define pCAN1_MB24_LENGTH ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */ #define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) #define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) -#define pCAN1_MB24_TIMESTAMP ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */ #define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) #define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) -#define pCAN1_MB24_ID0 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */ #define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) #define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) -#define pCAN1_MB24_ID1 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */ #define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) #define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) -#define pCAN1_MB25_DATA0 ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */ #define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) #define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) -#define pCAN1_MB25_DATA1 ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */ #define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) #define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) -#define pCAN1_MB25_DATA2 ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */ #define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) #define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) -#define pCAN1_MB25_DATA3 ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */ #define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) #define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) -#define pCAN1_MB25_LENGTH ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */ #define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) #define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) -#define pCAN1_MB25_TIMESTAMP ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */ #define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) #define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) -#define pCAN1_MB25_ID0 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */ #define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) #define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) -#define pCAN1_MB25_ID1 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */ #define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) #define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) -#define pCAN1_MB26_DATA0 ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */ #define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) #define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) -#define pCAN1_MB26_DATA1 ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */ #define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) #define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) -#define pCAN1_MB26_DATA2 ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */ #define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) #define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) -#define pCAN1_MB26_DATA3 ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */ #define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) #define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) -#define pCAN1_MB26_LENGTH ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */ #define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) #define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) -#define pCAN1_MB26_TIMESTAMP ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */ #define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) #define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) -#define pCAN1_MB26_ID0 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */ #define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) #define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) -#define pCAN1_MB26_ID1 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */ #define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) #define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) -#define pCAN1_MB27_DATA0 ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */ #define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) #define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) -#define pCAN1_MB27_DATA1 ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */ #define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) #define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) -#define pCAN1_MB27_DATA2 ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */ #define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) #define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) -#define pCAN1_MB27_DATA3 ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */ #define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) #define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) -#define pCAN1_MB27_LENGTH ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */ #define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) #define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) -#define pCAN1_MB27_TIMESTAMP ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */ #define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) #define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) -#define pCAN1_MB27_ID0 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */ #define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) #define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) -#define pCAN1_MB27_ID1 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */ #define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) #define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) -#define pCAN1_MB28_DATA0 ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */ #define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) #define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) -#define pCAN1_MB28_DATA1 ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */ #define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) #define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) -#define pCAN1_MB28_DATA2 ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */ #define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) #define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) -#define pCAN1_MB28_DATA3 ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */ #define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) #define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) -#define pCAN1_MB28_LENGTH ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */ #define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) #define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) -#define pCAN1_MB28_TIMESTAMP ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */ #define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) #define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) -#define pCAN1_MB28_ID0 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */ #define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) #define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) -#define pCAN1_MB28_ID1 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */ #define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) #define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) -#define pCAN1_MB29_DATA0 ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */ #define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) #define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) -#define pCAN1_MB29_DATA1 ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */ #define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) #define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) -#define pCAN1_MB29_DATA2 ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */ #define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) #define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) -#define pCAN1_MB29_DATA3 ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */ #define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) #define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) -#define pCAN1_MB29_LENGTH ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */ #define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) #define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) -#define pCAN1_MB29_TIMESTAMP ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */ #define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) #define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) -#define pCAN1_MB29_ID0 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */ #define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) #define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) -#define pCAN1_MB29_ID1 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */ #define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) #define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) -#define pCAN1_MB30_DATA0 ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */ #define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) #define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) -#define pCAN1_MB30_DATA1 ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */ #define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) #define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) -#define pCAN1_MB30_DATA2 ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */ #define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) #define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) -#define pCAN1_MB30_DATA3 ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */ #define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) #define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) -#define pCAN1_MB30_LENGTH ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */ #define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) #define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) -#define pCAN1_MB30_TIMESTAMP ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */ #define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) #define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) -#define pCAN1_MB30_ID0 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */ #define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) #define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) -#define pCAN1_MB30_ID1 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */ #define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) #define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) -#define pCAN1_MB31_DATA0 ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */ #define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) #define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) -#define pCAN1_MB31_DATA1 ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */ #define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) #define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) -#define pCAN1_MB31_DATA2 ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */ #define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) #define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) -#define pCAN1_MB31_DATA3 ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */ #define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) #define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) -#define pCAN1_MB31_LENGTH ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */ #define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) #define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) -#define pCAN1_MB31_TIMESTAMP ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */ #define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) #define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) -#define pCAN1_MB31_ID0 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */ #define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) #define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) -#define pCAN1_MB31_ID1 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */ #define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) #define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) -#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */ #define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) #define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) -#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */ #define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) #define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) -#define pSPI0_STAT ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */ #define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT) #define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val) -#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */ #define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) #define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) -#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */ #define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) #define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) -#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */ #define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) #define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) -#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */ #define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) #define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) -#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */ #define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) #define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) -#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */ #define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) #define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) -#define pSPI1_STAT ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */ #define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT) #define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val) -#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */ #define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) #define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) -#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */ #define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) #define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) -#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */ #define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) #define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) -#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */ #define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) #define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) -#define pSPI2_CTL ((uint16_t volatile *)SPI2_CTL) /* SPI2 Control Register */ #define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) #define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) -#define pSPI2_FLG ((uint16_t volatile *)SPI2_FLG) /* SPI2 Flag Register */ #define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) #define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) -#define pSPI2_STAT ((uint16_t volatile *)SPI2_STAT) /* SPI2 Status Register */ #define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) #define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) -#define pSPI2_TDBR ((uint16_t volatile *)SPI2_TDBR) /* SPI2 Transmit Data Buffer Register */ #define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) #define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) -#define pSPI2_RDBR ((uint16_t volatile *)SPI2_RDBR) /* SPI2 Receive Data Buffer Register */ #define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) #define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) -#define pSPI2_BAUD ((uint16_t volatile *)SPI2_BAUD) /* SPI2 Baud Rate Register */ #define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) #define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) -#define pSPI2_SHADOW ((uint16_t volatile *)SPI2_SHADOW) /* SPI2 Receive Data Buffer Shadow Register */ #define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) #define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) -#define pTWI0_CLKDIV ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV) #define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val) -#define pTWI0_CONTROL ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */ #define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL) #define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val) -#define pTWI0_SLAVE_CTL ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI0_SLAVE_CTL() bfin_read16(TWI0_SLAVE_CTL) #define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val) -#define pTWI0_SLAVE_STAT ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT) #define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val) -#define pTWI0_SLAVE_ADDR ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR) #define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val) -#define pTWI0_MASTER_CTL ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL) #define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val) -#define pTWI0_MASTER_STAT ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT) #define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val) -#define pTWI0_MASTER_ADDR ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR) #define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val) -#define pTWI0_INT_STAT ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT) #define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val) -#define pTWI0_INT_MASK ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK) #define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val) -#define pTWI0_FIFO_CTL ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL) #define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val) -#define pTWI0_FIFO_STAT ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT) #define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val) -#define pTWI0_XMT_DATA8 ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8) #define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val) -#define pTWI0_XMT_DATA16 ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16) #define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val) -#define pTWI0_RCV_DATA8 ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8) #define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val) -#define pTWI0_RCV_DATA16 ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16) #define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val) -#define pTWI1_CLKDIV ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */ #define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV) #define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val) -#define pTWI1_CONTROL ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */ #define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL) #define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val) -#define pTWI1_SLAVE_CTL ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */ #define bfin_read_TWI1_SLAVE_CTL() bfin_read16(TWI1_SLAVE_CTL) #define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val) -#define pTWI1_SLAVE_STAT ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */ #define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT) #define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val) -#define pTWI1_SLAVE_ADDR ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */ #define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR) #define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val) -#define pTWI1_MASTER_CTL ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */ #define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL) #define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val) -#define pTWI1_MASTER_STAT ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */ #define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT) #define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val) -#define pTWI1_MASTER_ADDR ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */ #define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR) #define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val) -#define pTWI1_INT_STAT ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */ #define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT) #define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val) -#define pTWI1_INT_MASK ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */ #define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK) #define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val) -#define pTWI1_FIFO_CTL ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */ #define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL) #define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val) -#define pTWI1_FIFO_STAT ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */ #define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT) #define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val) -#define pTWI1_XMT_DATA8 ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */ #define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8) #define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val) -#define pTWI1_XMT_DATA16 ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */ #define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16) #define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val) -#define pTWI1_RCV_DATA8 ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */ #define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8) #define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val) -#define pTWI1_RCV_DATA16 ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */ #define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16) #define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ #define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) #define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) #define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 Transmit Data Register */ #define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Receive Configuration 1 Register */ #define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) #define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Receive Configuration 2 Register */ #define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) #define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Serial Clock Divider Register */ #define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) #define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider Register */ #define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) #define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 Receive Data Register */ #define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) #define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ #define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) #define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi channel Configuration Register 1 */ #define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) #define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi channel Configuration Register 2 */ #define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) #define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ #define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) #define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) /* SPORT0 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) #define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) /* SPORT0 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) #define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) /* SPORT0 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) #define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) /* SPORT0 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) /* SPORT0 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) #define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) /* SPORT0 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) #define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) /* SPORT0 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) #define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) /* SPORT0 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) #define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ #define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) #define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ #define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) #define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) #define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) #define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */ #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */ #define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) #define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */ #define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) #define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */ #define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) #define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */ #define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) #define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */ #define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ #define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) #define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */ #define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) #define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */ #define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) #define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ #define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) #define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT2_TCR1 ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */ #define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1) #define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val) -#define pSPORT2_TCR2 ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */ #define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2) #define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val) -#define pSPORT2_TCLKDIV ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV) #define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val) -#define pSPORT2_TFSDIV ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV) #define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val) -#define pSPORT2_TX ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */ #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val) -#define pSPORT2_RCR1 ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */ #define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1) #define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val) -#define pSPORT2_RCR2 ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */ #define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2) #define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val) -#define pSPORT2_RCLKDIV ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */ #define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV) #define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val) -#define pSPORT2_RFSDIV ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */ #define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV) #define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val) -#define pSPORT2_RX ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */ #define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX) #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val) -#define pSPORT2_STAT ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */ #define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT) #define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val) -#define pSPORT2_MCMC1 ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */ #define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1) #define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val) -#define pSPORT2_MCMC2 ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */ #define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2) #define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val) -#define pSPORT2_CHNL ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */ #define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL) #define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val) -#define pSPORT2_MRCS0 ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0) #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val) -#define pSPORT2_MRCS1 ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1) #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val) -#define pSPORT2_MRCS2 ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2) #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val) -#define pSPORT2_MRCS3 ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3) #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val) -#define pSPORT2_MTCS0 ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0) #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val) -#define pSPORT2_MTCS1 ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1) #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val) -#define pSPORT2_MTCS2 ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2) #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val) -#define pSPORT2_MTCS3 ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3) #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val) -#define pSPORT3_TCR1 ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */ #define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1) #define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val) -#define pSPORT3_TCR2 ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */ #define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2) #define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val) -#define pSPORT3_TCLKDIV ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */ #define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV) #define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val) -#define pSPORT3_TFSDIV ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */ #define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV) #define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val) -#define pSPORT3_TX ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */ #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val) -#define pSPORT3_RCR1 ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */ #define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1) #define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val) -#define pSPORT3_RCR2 ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */ #define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2) #define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val) -#define pSPORT3_RCLKDIV ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */ #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV) #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val) -#define pSPORT3_RFSDIV ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */ #define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV) #define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val) -#define pSPORT3_RX ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */ #define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX) #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val) -#define pSPORT3_STAT ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */ #define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT) #define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val) -#define pSPORT3_MCMC1 ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */ #define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1) #define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val) -#define pSPORT3_MCMC2 ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */ #define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2) #define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val) -#define pSPORT3_CHNL ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */ #define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL) #define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val) -#define pSPORT3_MRCS0 ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */ #define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0) #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val) -#define pSPORT3_MRCS1 ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */ #define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1) #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val) -#define pSPORT3_MRCS2 ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */ #define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2) #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val) -#define pSPORT3_MRCS3 ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */ #define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3) #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val) -#define pSPORT3_MTCS0 ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */ #define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0) #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val) -#define pSPORT3_MTCS1 ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */ #define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1) #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val) -#define pSPORT3_MTCS2 ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */ #define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2) #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val) -#define pSPORT3_MTCS3 ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */ #define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3) #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val) -#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) #define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) -#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) #define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) -#define pUART0_GCTL ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */ #define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL) #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) -#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control Register */ #define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) #define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) -#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */ #define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) #define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) -#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status Register */ #define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) #define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) -#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */ #define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) #define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) -#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* Scratch Register */ #define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) #define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) -#define pUART0_IER_SET ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET) #define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val) -#define pUART0_IER_CLEAR ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR) #define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val) -#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */ #define bfin_read_UART0_THR() bfin_read16(UART0_THR) #define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) -#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */ #define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) #define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) -#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) #define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) -#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) #define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) -#define pUART1_GCTL ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */ #define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL) #define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val) -#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control Register */ #define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) #define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) -#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */ #define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) #define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) -#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status Register */ #define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) #define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) -#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */ #define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) #define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) -#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* Scratch Register */ #define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) #define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) -#define pUART1_IER_SET ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET) #define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val) -#define pUART1_IER_CLEAR ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR) #define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val) -#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */ #define bfin_read_UART1_THR() bfin_read16(UART1_THR) #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) -#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */ #define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) #define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) -#define pUART2_DLL ((uint16_t volatile *)UART2_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) #define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) -#define pUART2_DLH ((uint16_t volatile *)UART2_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) #define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) -#define pUART2_GCTL ((uint16_t volatile *)UART2_GCTL) /* Global Control Register */ #define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) #define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) -#define pUART2_LCR ((uint16_t volatile *)UART2_LCR) /* Line Control Register */ #define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) #define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) -#define pUART2_MCR ((uint16_t volatile *)UART2_MCR) /* Modem Control Register */ #define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) #define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) -#define pUART2_LSR ((uint16_t volatile *)UART2_LSR) /* Line Status Register */ #define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) #define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) -#define pUART2_MSR ((uint16_t volatile *)UART2_MSR) /* Modem Status Register */ #define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) #define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) -#define pUART2_SCR ((uint16_t volatile *)UART2_SCR) /* Scratch Register */ #define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) #define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) -#define pUART2_IER_SET ((uint16_t volatile *)UART2_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) #define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) -#define pUART2_IER_CLEAR ((uint16_t volatile *)UART2_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) #define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) -#define pUART2_THR ((uint16_t volatile *)UART2_THR) /* Transmit Hold Register */ #define bfin_read_UART2_THR() bfin_read16(UART2_THR) #define bfin_write_UART2_THR(val) bfin_write16(UART2_THR, val) -#define pUART2_RBR ((uint16_t volatile *)UART2_RBR) /* Receive Buffer Register */ #define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) #define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) -#define pUART3_DLL ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */ #define bfin_read_UART3_DLL() bfin_read16(UART3_DLL) #define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val) -#define pUART3_DLH ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */ #define bfin_read_UART3_DLH() bfin_read16(UART3_DLH) #define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val) -#define pUART3_GCTL ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */ #define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL) #define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val) -#define pUART3_LCR ((uint16_t volatile *)UART3_LCR) /* Line Control Register */ #define bfin_read_UART3_LCR() bfin_read16(UART3_LCR) #define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val) -#define pUART3_MCR ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */ #define bfin_read_UART3_MCR() bfin_read16(UART3_MCR) #define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val) -#define pUART3_LSR ((uint16_t volatile *)UART3_LSR) /* Line Status Register */ #define bfin_read_UART3_LSR() bfin_read16(UART3_LSR) #define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val) -#define pUART3_MSR ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */ #define bfin_read_UART3_MSR() bfin_read16(UART3_MSR) #define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val) -#define pUART3_SCR ((uint16_t volatile *)UART3_SCR) /* Scratch Register */ #define bfin_read_UART3_SCR() bfin_read16(UART3_SCR) #define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val) -#define pUART3_IER_SET ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */ #define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET) #define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val) -#define pUART3_IER_CLEAR ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */ #define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR) #define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val) -#define pUART3_THR ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */ #define bfin_read_UART3_THR() bfin_read16(UART3_THR) #define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val) -#define pUART3_RBR ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */ #define bfin_read_UART3_RBR() bfin_read16(UART3_RBR) #define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val) -#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */ #define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) #define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) -#define pUSB_POWER ((uint16_t volatile *)USB_POWER) /* Power management register */ #define bfin_read_USB_POWER() bfin_read16(USB_POWER) #define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) -#define pUSB_INTRTX ((uint16_t volatile *)USB_INTRTX) /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ #define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) #define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) -#define pUSB_INTRRX ((uint16_t volatile *)USB_INTRRX) /* Interrupt register for Rx endpoints 1 to 7 */ #define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) #define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) -#define pUSB_INTRTXE ((uint16_t volatile *)USB_INTRTXE) /* Interrupt enable register for IntrTx */ #define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) #define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) -#define pUSB_INTRRXE ((uint16_t volatile *)USB_INTRRXE) /* Interrupt enable register for IntrRx */ #define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) #define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) -#define pUSB_INTRUSB ((uint16_t volatile *)USB_INTRUSB) /* Interrupt register for common USB interrupts */ #define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) #define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) -#define pUSB_INTRUSBE ((uint16_t volatile *)USB_INTRUSBE) /* Interrupt enable register for IntrUSB */ #define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) #define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) -#define pUSB_FRAME ((uint16_t volatile *)USB_FRAME) /* USB frame number */ #define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) #define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) -#define pUSB_INDEX ((uint16_t volatile *)USB_INDEX) /* Index register for selecting the indexed endpoint registers */ #define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) #define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) -#define pUSB_TESTMODE ((uint16_t volatile *)USB_TESTMODE) /* Enabled USB 20 test modes */ #define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) #define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) -#define pUSB_GLOBINTR ((uint16_t volatile *)USB_GLOBINTR) /* Global Interrupt Mask register and Wakeup Exception Interrupt */ #define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) #define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) -#define pUSB_GLOBAL_CTL ((uint16_t volatile *)USB_GLOBAL_CTL) /* Global Clock Control for the core */ #define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) #define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) -#define pUSB_TX_MAX_PACKET ((uint16_t volatile *)USB_TX_MAX_PACKET) /* Maximum packet size for Host Tx endpoint */ #define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) #define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) -#define pUSB_CSR0 ((uint16_t volatile *)USB_CSR0) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) #define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) -#define pUSB_TXCSR ((uint16_t volatile *)USB_TXCSR) /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ #define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) #define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) -#define pUSB_RX_MAX_PACKET ((uint16_t volatile *)USB_RX_MAX_PACKET) /* Maximum packet size for Host Rx endpoint */ #define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) #define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) -#define pUSB_RXCSR ((uint16_t volatile *)USB_RXCSR) /* Control Status register for Host Rx endpoint */ #define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) #define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) -#define pUSB_COUNT0 ((uint16_t volatile *)USB_COUNT0) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) #define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) -#define pUSB_RXCOUNT ((uint16_t volatile *)USB_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ #define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) #define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) -#define pUSB_TXTYPE ((uint16_t volatile *)USB_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ #define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) #define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) -#define pUSB_NAKLIMIT0 ((uint16_t volatile *)USB_NAKLIMIT0) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) #define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) -#define pUSB_TXINTERVAL ((uint16_t volatile *)USB_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ #define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) #define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) -#define pUSB_RXTYPE ((uint16_t volatile *)USB_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ #define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) #define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) -#define pUSB_RXINTERVAL ((uint16_t volatile *)USB_RXINTERVAL) /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ #define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) #define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) -#define pUSB_TXCOUNT ((uint16_t volatile *)USB_TXCOUNT) /* Number of bytes to be written to the selected endpoint Tx FIFO */ #define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) #define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) -#define pUSB_EP0_FIFO ((uint16_t volatile *)USB_EP0_FIFO) /* Endpoint 0 FIFO */ #define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) #define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) -#define pUSB_EP1_FIFO ((uint16_t volatile *)USB_EP1_FIFO) /* Endpoint 1 FIFO */ #define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) #define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) -#define pUSB_EP2_FIFO ((uint16_t volatile *)USB_EP2_FIFO) /* Endpoint 2 FIFO */ #define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) #define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) -#define pUSB_EP3_FIFO ((uint16_t volatile *)USB_EP3_FIFO) /* Endpoint 3 FIFO */ #define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) #define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) -#define pUSB_EP4_FIFO ((uint16_t volatile *)USB_EP4_FIFO) /* Endpoint 4 FIFO */ #define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) #define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) -#define pUSB_EP5_FIFO ((uint16_t volatile *)USB_EP5_FIFO) /* Endpoint 5 FIFO */ #define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) #define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) -#define pUSB_EP6_FIFO ((uint16_t volatile *)USB_EP6_FIFO) /* Endpoint 6 FIFO */ #define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) #define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) -#define pUSB_EP7_FIFO ((uint16_t volatile *)USB_EP7_FIFO) /* Endpoint 7 FIFO */ #define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) #define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) -#define pUSB_OTG_DEV_CTL ((uint16_t volatile *)USB_OTG_DEV_CTL) /* OTG Device Control Register */ #define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) #define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) -#define pUSB_OTG_VBUS_IRQ ((uint16_t volatile *)USB_OTG_VBUS_IRQ) /* OTG VBUS Control Interrupts */ #define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) #define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) -#define pUSB_OTG_VBUS_MASK ((uint16_t volatile *)USB_OTG_VBUS_MASK) /* VBUS Control Interrupt Enable */ #define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) #define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) -#define pUSB_LINKINFO ((uint16_t volatile *)USB_LINKINFO) /* Enables programming of some PHY-side delays */ #define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) #define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) -#define pUSB_VPLEN ((uint16_t volatile *)USB_VPLEN) /* Determines duration of VBUS pulse for VBUS charging */ #define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) #define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) -#define pUSB_HS_EOF1 ((uint16_t volatile *)USB_HS_EOF1) /* Time buffer for High-Speed transactions */ #define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) #define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) -#define pUSB_FS_EOF1 ((uint16_t volatile *)USB_FS_EOF1) /* Time buffer for Full-Speed transactions */ #define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) #define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) -#define pUSB_LS_EOF1 ((uint16_t volatile *)USB_LS_EOF1) /* Time buffer for Low-Speed transactions */ #define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) #define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) -#define pUSB_APHY_CNTRL ((uint16_t volatile *)USB_APHY_CNTRL) /* Register that increases visibility of Analog PHY */ #define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) #define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) -#define pUSB_APHY_CALIB ((uint16_t volatile *)USB_APHY_CALIB) /* Register used to set some calibration values */ #define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) #define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) -#define pUSB_APHY_CNTRL2 ((uint16_t volatile *)USB_APHY_CNTRL2) /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ #define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) #define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) -#define pUSB_PHY_TEST ((uint16_t volatile *)USB_PHY_TEST) /* Used for reducing simulation time and simplifies FIFO testability */ #define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) #define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) -#define pUSB_PLLOSC_CTRL ((uint16_t volatile *)USB_PLLOSC_CTRL) /* Used to program different parameters for USB PLL and Oscillator */ #define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) #define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) -#define pUSB_SRP_CLKDIV ((uint16_t volatile *)USB_SRP_CLKDIV) /* Used to program clock divide value for the clock fed to the SRP detection logic */ #define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) #define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) -#define pUSB_EP_NI0_TXMAXP ((uint16_t volatile *)USB_EP_NI0_TXMAXP) /* Maximum packet size for Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) #define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) -#define pUSB_EP_NI0_TXCSR ((uint16_t volatile *)USB_EP_NI0_TXCSR) /* Control Status register for endpoint 0 */ #define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) #define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) -#define pUSB_EP_NI0_RXMAXP ((uint16_t volatile *)USB_EP_NI0_RXMAXP) /* Maximum packet size for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) #define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) -#define pUSB_EP_NI0_RXCSR ((uint16_t volatile *)USB_EP_NI0_RXCSR) /* Control Status register for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) #define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) -#define pUSB_EP_NI0_RXCOUNT ((uint16_t volatile *)USB_EP_NI0_RXCOUNT) /* Number of bytes received in endpoint 0 FIFO */ #define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) #define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) -#define pUSB_EP_NI0_TXTYPE ((uint16_t volatile *)USB_EP_NI0_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ #define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) #define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) -#define pUSB_EP_NI0_TXINTERVAL ((uint16_t volatile *)USB_EP_NI0_TXINTERVAL) /* Sets the NAK response timeout on Endpoint 0 */ #define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) #define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) -#define pUSB_EP_NI0_RXTYPE ((uint16_t volatile *)USB_EP_NI0_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) #define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) -#define pUSB_EP_NI0_RXINTERVAL ((uint16_t volatile *)USB_EP_NI0_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ #define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) #define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) -#define pUSB_EP_NI0_TXCOUNT ((uint16_t volatile *)USB_EP_NI0_TXCOUNT) /* Number of bytes to be written to the endpoint0 Tx FIFO */ #define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) #define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) -#define pUSB_EP_NI1_TXMAXP ((uint16_t volatile *)USB_EP_NI1_TXMAXP) /* Maximum packet size for Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) #define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) -#define pUSB_EP_NI1_TXCSR ((uint16_t volatile *)USB_EP_NI1_TXCSR) /* Control Status register for endpoint1 */ #define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) #define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) -#define pUSB_EP_NI1_RXMAXP ((uint16_t volatile *)USB_EP_NI1_RXMAXP) /* Maximum packet size for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) #define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) -#define pUSB_EP_NI1_RXCSR ((uint16_t volatile *)USB_EP_NI1_RXCSR) /* Control Status register for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) #define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) -#define pUSB_EP_NI1_RXCOUNT ((uint16_t volatile *)USB_EP_NI1_RXCOUNT) /* Number of bytes received in endpoint1 FIFO */ #define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) #define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) -#define pUSB_EP_NI1_TXTYPE ((uint16_t volatile *)USB_EP_NI1_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ #define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) #define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) -#define pUSB_EP_NI1_TXINTERVAL ((uint16_t volatile *)USB_EP_NI1_TXINTERVAL) /* Sets the NAK response timeout on Endpoint1 */ #define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) #define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) -#define pUSB_EP_NI1_RXTYPE ((uint16_t volatile *)USB_EP_NI1_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) #define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) -#define pUSB_EP_NI1_RXINTERVAL ((uint16_t volatile *)USB_EP_NI1_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ #define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) #define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) -#define pUSB_EP_NI1_TXCOUNT ((uint16_t volatile *)USB_EP_NI1_TXCOUNT) /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ #define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) #define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) -#define pUSB_EP_NI2_TXMAXP ((uint16_t volatile *)USB_EP_NI2_TXMAXP) /* Maximum packet size for Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) #define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) -#define pUSB_EP_NI2_TXCSR ((uint16_t volatile *)USB_EP_NI2_TXCSR) /* Control Status register for endpoint2 */ #define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) #define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) -#define pUSB_EP_NI2_RXMAXP ((uint16_t volatile *)USB_EP_NI2_RXMAXP) /* Maximum packet size for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) #define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) -#define pUSB_EP_NI2_RXCSR ((uint16_t volatile *)USB_EP_NI2_RXCSR) /* Control Status register for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) #define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) -#define pUSB_EP_NI2_RXCOUNT ((uint16_t volatile *)USB_EP_NI2_RXCOUNT) /* Number of bytes received in endpoint2 FIFO */ #define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) #define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) -#define pUSB_EP_NI2_TXTYPE ((uint16_t volatile *)USB_EP_NI2_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ #define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) #define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) -#define pUSB_EP_NI2_TXINTERVAL ((uint16_t volatile *)USB_EP_NI2_TXINTERVAL) /* Sets the NAK response timeout on Endpoint2 */ #define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) #define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) -#define pUSB_EP_NI2_RXTYPE ((uint16_t volatile *)USB_EP_NI2_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) #define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) -#define pUSB_EP_NI2_RXINTERVAL ((uint16_t volatile *)USB_EP_NI2_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ #define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) #define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) -#define pUSB_EP_NI2_TXCOUNT ((uint16_t volatile *)USB_EP_NI2_TXCOUNT) /* Number of bytes to be written to the endpoint2 Tx FIFO */ #define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) #define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) -#define pUSB_EP_NI3_TXMAXP ((uint16_t volatile *)USB_EP_NI3_TXMAXP) /* Maximum packet size for Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) #define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) -#define pUSB_EP_NI3_TXCSR ((uint16_t volatile *)USB_EP_NI3_TXCSR) /* Control Status register for endpoint3 */ #define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) #define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) -#define pUSB_EP_NI3_RXMAXP ((uint16_t volatile *)USB_EP_NI3_RXMAXP) /* Maximum packet size for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) #define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) -#define pUSB_EP_NI3_RXCSR ((uint16_t volatile *)USB_EP_NI3_RXCSR) /* Control Status register for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) #define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) -#define pUSB_EP_NI3_RXCOUNT ((uint16_t volatile *)USB_EP_NI3_RXCOUNT) /* Number of bytes received in endpoint3 FIFO */ #define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) #define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) -#define pUSB_EP_NI3_TXTYPE ((uint16_t volatile *)USB_EP_NI3_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ #define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) #define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) -#define pUSB_EP_NI3_TXINTERVAL ((uint16_t volatile *)USB_EP_NI3_TXINTERVAL) /* Sets the NAK response timeout on Endpoint3 */ #define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) #define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) -#define pUSB_EP_NI3_RXTYPE ((uint16_t volatile *)USB_EP_NI3_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) #define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) -#define pUSB_EP_NI3_RXINTERVAL ((uint16_t volatile *)USB_EP_NI3_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ #define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) #define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) -#define pUSB_EP_NI3_TXCOUNT ((uint16_t volatile *)USB_EP_NI3_TXCOUNT) /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ #define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) #define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) -#define pUSB_EP_NI4_TXMAXP ((uint16_t volatile *)USB_EP_NI4_TXMAXP) /* Maximum packet size for Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) #define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) -#define pUSB_EP_NI4_TXCSR ((uint16_t volatile *)USB_EP_NI4_TXCSR) /* Control Status register for endpoint4 */ #define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) #define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) -#define pUSB_EP_NI4_RXMAXP ((uint16_t volatile *)USB_EP_NI4_RXMAXP) /* Maximum packet size for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) #define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) -#define pUSB_EP_NI4_RXCSR ((uint16_t volatile *)USB_EP_NI4_RXCSR) /* Control Status register for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) #define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) -#define pUSB_EP_NI4_RXCOUNT ((uint16_t volatile *)USB_EP_NI4_RXCOUNT) /* Number of bytes received in endpoint4 FIFO */ #define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) #define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) -#define pUSB_EP_NI4_TXTYPE ((uint16_t volatile *)USB_EP_NI4_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ #define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) #define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) -#define pUSB_EP_NI4_TXINTERVAL ((uint16_t volatile *)USB_EP_NI4_TXINTERVAL) /* Sets the NAK response timeout on Endpoint4 */ #define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) #define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) -#define pUSB_EP_NI4_RXTYPE ((uint16_t volatile *)USB_EP_NI4_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) #define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) -#define pUSB_EP_NI4_RXINTERVAL ((uint16_t volatile *)USB_EP_NI4_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ #define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) #define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) -#define pUSB_EP_NI4_TXCOUNT ((uint16_t volatile *)USB_EP_NI4_TXCOUNT) /* Number of bytes to be written to the endpoint4 Tx FIFO */ #define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) #define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) -#define pUSB_EP_NI5_TXMAXP ((uint16_t volatile *)USB_EP_NI5_TXMAXP) /* Maximum packet size for Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) #define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) -#define pUSB_EP_NI5_TXCSR ((uint16_t volatile *)USB_EP_NI5_TXCSR) /* Control Status register for endpoint5 */ #define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) #define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) -#define pUSB_EP_NI5_RXMAXP ((uint16_t volatile *)USB_EP_NI5_RXMAXP) /* Maximum packet size for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) #define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) -#define pUSB_EP_NI5_RXCSR ((uint16_t volatile *)USB_EP_NI5_RXCSR) /* Control Status register for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) #define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) -#define pUSB_EP_NI5_RXCOUNT ((uint16_t volatile *)USB_EP_NI5_RXCOUNT) /* Number of bytes received in endpoint5 FIFO */ #define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) #define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) -#define pUSB_EP_NI5_TXTYPE ((uint16_t volatile *)USB_EP_NI5_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ #define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) #define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) -#define pUSB_EP_NI5_TXINTERVAL ((uint16_t volatile *)USB_EP_NI5_TXINTERVAL) /* Sets the NAK response timeout on Endpoint5 */ #define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) #define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) -#define pUSB_EP_NI5_RXTYPE ((uint16_t volatile *)USB_EP_NI5_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) #define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) -#define pUSB_EP_NI5_RXINTERVAL ((uint16_t volatile *)USB_EP_NI5_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ #define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) #define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) -#define pUSB_EP_NI5_TXCOUNT ((uint16_t volatile *)USB_EP_NI5_TXCOUNT) /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ #define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) #define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) -#define pUSB_EP_NI6_TXMAXP ((uint16_t volatile *)USB_EP_NI6_TXMAXP) /* Maximum packet size for Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) #define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) -#define pUSB_EP_NI6_TXCSR ((uint16_t volatile *)USB_EP_NI6_TXCSR) /* Control Status register for endpoint6 */ #define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) #define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) -#define pUSB_EP_NI6_RXMAXP ((uint16_t volatile *)USB_EP_NI6_RXMAXP) /* Maximum packet size for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) #define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) -#define pUSB_EP_NI6_RXCSR ((uint16_t volatile *)USB_EP_NI6_RXCSR) /* Control Status register for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) #define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) -#define pUSB_EP_NI6_RXCOUNT ((uint16_t volatile *)USB_EP_NI6_RXCOUNT) /* Number of bytes received in endpoint6 FIFO */ #define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) #define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) -#define pUSB_EP_NI6_TXTYPE ((uint16_t volatile *)USB_EP_NI6_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ #define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) #define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) -#define pUSB_EP_NI6_TXINTERVAL ((uint16_t volatile *)USB_EP_NI6_TXINTERVAL) /* Sets the NAK response timeout on Endpoint6 */ #define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) #define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) -#define pUSB_EP_NI6_RXTYPE ((uint16_t volatile *)USB_EP_NI6_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) #define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) -#define pUSB_EP_NI6_RXINTERVAL ((uint16_t volatile *)USB_EP_NI6_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ #define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) #define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) -#define pUSB_EP_NI6_TXCOUNT ((uint16_t volatile *)USB_EP_NI6_TXCOUNT) /* Number of bytes to be written to the endpoint6 Tx FIFO */ #define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) #define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) -#define pUSB_EP_NI7_TXMAXP ((uint16_t volatile *)USB_EP_NI7_TXMAXP) /* Maximum packet size for Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) #define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) -#define pUSB_EP_NI7_TXCSR ((uint16_t volatile *)USB_EP_NI7_TXCSR) /* Control Status register for endpoint7 */ #define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) #define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) -#define pUSB_EP_NI7_RXMAXP ((uint16_t volatile *)USB_EP_NI7_RXMAXP) /* Maximum packet size for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) #define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) -#define pUSB_EP_NI7_RXCSR ((uint16_t volatile *)USB_EP_NI7_RXCSR) /* Control Status register for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) #define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) -#define pUSB_EP_NI7_RXCOUNT ((uint16_t volatile *)USB_EP_NI7_RXCOUNT) /* Number of bytes received in endpoint7 FIFO */ #define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) #define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) -#define pUSB_EP_NI7_TXTYPE ((uint16_t volatile *)USB_EP_NI7_TXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ #define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) #define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) -#define pUSB_EP_NI7_TXINTERVAL ((uint16_t volatile *)USB_EP_NI7_TXINTERVAL) /* Sets the NAK response timeout on Endpoint7 */ #define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) #define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) -#define pUSB_EP_NI7_RXTYPE ((uint16_t volatile *)USB_EP_NI7_RXTYPE) /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) #define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) -#define pUSB_EP_NI7_RXINTERVAL ((uint16_t volatile *)USB_EP_NI7_RXINTERVAL) /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ #define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) #define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) -#define pUSB_EP_NI7_TXCOUNT ((uint16_t volatile *)USB_EP_NI7_TXCOUNT) /* Number of bytes to be written to the endpoint7 Tx FIFO */ #define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) #define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) -#define pUSB_DMA_INTERRUPT ((uint16_t volatile *)USB_DMA_INTERRUPT) /* Indicates pending interrupts for the DMA channels */ #define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) #define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) -#define pUSB_DMA0_CONTROL ((uint16_t volatile *)USB_DMA0_CONTROL) /* DMA master channel 0 configuration */ #define bfin_read_USB_DMA0_CONTROL() bfin_read16(USB_DMA0_CONTROL) #define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val) -#define pUSB_DMA0_ADDRLOW ((uint16_t volatile *)USB_DMA0_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRLOW() bfin_read16(USB_DMA0_ADDRLOW) #define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val) -#define pUSB_DMA0_ADDRHIGH ((uint16_t volatile *)USB_DMA0_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ #define bfin_read_USB_DMA0_ADDRHIGH() bfin_read16(USB_DMA0_ADDRHIGH) #define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val) -#define pUSB_DMA0_COUNTLOW ((uint16_t volatile *)USB_DMA0_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTLOW() bfin_read16(USB_DMA0_COUNTLOW) #define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val) -#define pUSB_DMA0_COUNTHIGH ((uint16_t volatile *)USB_DMA0_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ #define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH) #define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val) -#define pUSB_DMA1_CONTROL ((uint16_t volatile *)USB_DMA1_CONTROL) /* DMA master channel 1 configuration */ #define bfin_read_USB_DMA1_CONTROL() bfin_read16(USB_DMA1_CONTROL) #define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val) -#define pUSB_DMA1_ADDRLOW ((uint16_t volatile *)USB_DMA1_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRLOW() bfin_read16(USB_DMA1_ADDRLOW) #define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val) -#define pUSB_DMA1_ADDRHIGH ((uint16_t volatile *)USB_DMA1_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ #define bfin_read_USB_DMA1_ADDRHIGH() bfin_read16(USB_DMA1_ADDRHIGH) #define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val) -#define pUSB_DMA1_COUNTLOW ((uint16_t volatile *)USB_DMA1_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTLOW() bfin_read16(USB_DMA1_COUNTLOW) #define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val) -#define pUSB_DMA1_COUNTHIGH ((uint16_t volatile *)USB_DMA1_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ #define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH) #define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val) -#define pUSB_DMA2_CONTROL ((uint16_t volatile *)USB_DMA2_CONTROL) /* DMA master channel 2 configuration */ #define bfin_read_USB_DMA2_CONTROL() bfin_read16(USB_DMA2_CONTROL) #define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val) -#define pUSB_DMA2_ADDRLOW ((uint16_t volatile *)USB_DMA2_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRLOW() bfin_read16(USB_DMA2_ADDRLOW) #define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val) -#define pUSB_DMA2_ADDRHIGH ((uint16_t volatile *)USB_DMA2_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ #define bfin_read_USB_DMA2_ADDRHIGH() bfin_read16(USB_DMA2_ADDRHIGH) #define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val) -#define pUSB_DMA2_COUNTLOW ((uint16_t volatile *)USB_DMA2_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTLOW() bfin_read16(USB_DMA2_COUNTLOW) #define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val) -#define pUSB_DMA2_COUNTHIGH ((uint16_t volatile *)USB_DMA2_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ #define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH) #define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val) -#define pUSB_DMA3_CONTROL ((uint16_t volatile *)USB_DMA3_CONTROL) /* DMA master channel 3 configuration */ #define bfin_read_USB_DMA3_CONTROL() bfin_read16(USB_DMA3_CONTROL) #define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val) -#define pUSB_DMA3_ADDRLOW ((uint16_t volatile *)USB_DMA3_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRLOW() bfin_read16(USB_DMA3_ADDRLOW) #define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val) -#define pUSB_DMA3_ADDRHIGH ((uint16_t volatile *)USB_DMA3_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ #define bfin_read_USB_DMA3_ADDRHIGH() bfin_read16(USB_DMA3_ADDRHIGH) #define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val) -#define pUSB_DMA3_COUNTLOW ((uint16_t volatile *)USB_DMA3_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTLOW() bfin_read16(USB_DMA3_COUNTLOW) #define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val) -#define pUSB_DMA3_COUNTHIGH ((uint16_t volatile *)USB_DMA3_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ #define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH) #define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val) -#define pUSB_DMA4_CONTROL ((uint16_t volatile *)USB_DMA4_CONTROL) /* DMA master channel 4 configuration */ #define bfin_read_USB_DMA4_CONTROL() bfin_read16(USB_DMA4_CONTROL) #define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val) -#define pUSB_DMA4_ADDRLOW ((uint16_t volatile *)USB_DMA4_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRLOW() bfin_read16(USB_DMA4_ADDRLOW) #define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val) -#define pUSB_DMA4_ADDRHIGH ((uint16_t volatile *)USB_DMA4_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ #define bfin_read_USB_DMA4_ADDRHIGH() bfin_read16(USB_DMA4_ADDRHIGH) #define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val) -#define pUSB_DMA4_COUNTLOW ((uint16_t volatile *)USB_DMA4_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTLOW() bfin_read16(USB_DMA4_COUNTLOW) #define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val) -#define pUSB_DMA4_COUNTHIGH ((uint16_t volatile *)USB_DMA4_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ #define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH) #define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val) -#define pUSB_DMA5_CONTROL ((uint16_t volatile *)USB_DMA5_CONTROL) /* DMA master channel 5 configuration */ #define bfin_read_USB_DMA5_CONTROL() bfin_read16(USB_DMA5_CONTROL) #define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val) -#define pUSB_DMA5_ADDRLOW ((uint16_t volatile *)USB_DMA5_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRLOW() bfin_read16(USB_DMA5_ADDRLOW) #define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val) -#define pUSB_DMA5_ADDRHIGH ((uint16_t volatile *)USB_DMA5_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ #define bfin_read_USB_DMA5_ADDRHIGH() bfin_read16(USB_DMA5_ADDRHIGH) #define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val) -#define pUSB_DMA5_COUNTLOW ((uint16_t volatile *)USB_DMA5_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTLOW() bfin_read16(USB_DMA5_COUNTLOW) #define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val) -#define pUSB_DMA5_COUNTHIGH ((uint16_t volatile *)USB_DMA5_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ #define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH) #define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val) -#define pUSB_DMA6_CONTROL ((uint16_t volatile *)USB_DMA6_CONTROL) /* DMA master channel 6 configuration */ #define bfin_read_USB_DMA6_CONTROL() bfin_read16(USB_DMA6_CONTROL) #define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val) -#define pUSB_DMA6_ADDRLOW ((uint16_t volatile *)USB_DMA6_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRLOW() bfin_read16(USB_DMA6_ADDRLOW) #define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val) -#define pUSB_DMA6_ADDRHIGH ((uint16_t volatile *)USB_DMA6_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ #define bfin_read_USB_DMA6_ADDRHIGH() bfin_read16(USB_DMA6_ADDRHIGH) #define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val) -#define pUSB_DMA6_COUNTLOW ((uint16_t volatile *)USB_DMA6_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTLOW() bfin_read16(USB_DMA6_COUNTLOW) #define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val) -#define pUSB_DMA6_COUNTHIGH ((uint16_t volatile *)USB_DMA6_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ #define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH) #define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val) -#define pUSB_DMA7_CONTROL ((uint16_t volatile *)USB_DMA7_CONTROL) /* DMA master channel 7 configuration */ #define bfin_read_USB_DMA7_CONTROL() bfin_read16(USB_DMA7_CONTROL) #define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val) -#define pUSB_DMA7_ADDRLOW ((uint16_t volatile *)USB_DMA7_ADDRLOW) /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRLOW() bfin_read16(USB_DMA7_ADDRLOW) #define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val) -#define pUSB_DMA7_ADDRHIGH ((uint16_t volatile *)USB_DMA7_ADDRHIGH) /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ #define bfin_read_USB_DMA7_ADDRHIGH() bfin_read16(USB_DMA7_ADDRHIGH) #define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val) -#define pUSB_DMA7_COUNTLOW ((uint16_t volatile *)USB_DMA7_COUNTLOW) /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTLOW() bfin_read16(USB_DMA7_COUNTLOW) #define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val) -#define pUSB_DMA7_COUNTHIGH ((uint16_t volatile *)USB_DMA7_COUNTHIGH) /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ #define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH) #define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val) diff --git a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h index 6163eb276f..33c82b427d 100644 --- a/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h +++ b/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF549-extended_def.h @@ -694,10 +694,6 @@ #define TIMER_ENABLE1 0xFFC00640 /* Timer Group of 3 Enable Register */ #define TIMER_DISABLE1 0xFFC00644 /* Timer Group of 3 Disable Register */ #define TIMER_STATUS1 0xFFC00648 /* Timer Group of 3 Status Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h deleted file mode 100644 index 1b8c79b59d..0000000000 --- a/arch/blackfin/include/asm/mach-bf548/BF541_cdef.h +++ /dev/null @@ -1,323 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_BF541_proc__ -#define __BFIN_CDEF_ADSP_BF541_proc__ - -#include "../mach-common/ADSP-EDN-core_cdef.h" - -#include "ADSP-EDN-BF542-extended_cdef.h" - -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) - -#endif /* __BFIN_CDEF_ADSP_BF541_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF541_def.h b/arch/blackfin/include/asm/mach-bf548/BF541_def.h deleted file mode 100644 index 1469ac2db7..0000000000 --- a/arch/blackfin/include/asm/mach-bf548/BF541_def.h +++ /dev/null @@ -1,117 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_BF541_proc__ -#define __BFIN_DEF_ADSP_BF541_proc__ - -#include "../mach-common/ADSP-EDN-core_def.h" - -#include "ADSP-EDN-BF542-extended_def.h" - -#define CHIPID 0xFFC00014 -#define SWRST 0xFFC00100 /* Software Reset Register */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ - -#endif /* __BFIN_DEF_ADSP_BF541_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h index 306b5f117f..fbd309210f 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/BF542_cdef.h @@ -10,314 +10,11 @@ #include "ADSP-EDN-BF542-extended_cdef.h" -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) #endif /* __BFIN_CDEF_ADSP_BF542_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF542_def.h b/arch/blackfin/include/asm/mach-bf548/BF542_def.h index 1324a136fd..38452ffee0 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF542_def.h +++ b/arch/blackfin/include/asm/mach-bf548/BF542_def.h @@ -13,105 +13,5 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ #endif /* __BFIN_DEF_ADSP_BF542_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h index 47ef6e17b5..ef26af33d0 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/BF544_cdef.h @@ -10,314 +10,11 @@ #include "ADSP-EDN-BF544-extended_cdef.h" -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) #endif /* __BFIN_CDEF_ADSP_BF544_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF544_def.h b/arch/blackfin/include/asm/mach-bf548/BF544_def.h index aef6e4858d..c12e9befb5 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF544_def.h +++ b/arch/blackfin/include/asm/mach-bf548/BF544_def.h @@ -13,105 +13,5 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ #endif /* __BFIN_DEF_ADSP_BF544_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h index 42d041a741..3f1ff8b4f2 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/BF547_cdef.h @@ -10,314 +10,11 @@ #include "ADSP-EDN-BF547-extended_cdef.h" -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) #endif /* __BFIN_CDEF_ADSP_BF547_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF547_def.h b/arch/blackfin/include/asm/mach-bf548/BF547_def.h index ce7c8804c0..e1f666b1c9 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF547_def.h +++ b/arch/blackfin/include/asm/mach-bf548/BF547_def.h @@ -13,105 +13,5 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ #endif /* __BFIN_DEF_ADSP_BF547_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h index cf02834e98..c8be3afa09 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/BF548_cdef.h @@ -10,314 +10,11 @@ #include "ADSP-EDN-BF548-extended_cdef.h" -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) #endif /* __BFIN_CDEF_ADSP_BF548_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF548_def.h b/arch/blackfin/include/asm/mach-bf548/BF548_def.h index e02e843e57..48b257c7f5 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF548_def.h +++ b/arch/blackfin/include/asm/mach-bf548/BF548_def.h @@ -13,105 +13,5 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ #endif /* __BFIN_DEF_ADSP_BF548_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h index 3514ceff4d..212d54e27a 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h +++ b/arch/blackfin/include/asm/mach-bf548/BF549_cdef.h @@ -10,314 +10,11 @@ #include "ADSP-EDN-BF549-extended_cdef.h" -#define pCHIPID ((uint32_t volatile *)CHIPID) #define bfin_read_CHIPID() bfin_read32(CHIPID) #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register */ #define bfin_read_SWRST() bfin_read16(SWRST) #define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) #endif /* __BFIN_CDEF_ADSP_BF549_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf548/BF549_def.h b/arch/blackfin/include/asm/mach-bf548/BF549_def.h index a16ff5aaf6..22f4a88b61 100644 --- a/arch/blackfin/include/asm/mach-bf548/BF549_def.h +++ b/arch/blackfin/include/asm/mach-bf548/BF549_def.h @@ -13,105 +13,5 @@ #define CHIPID 0xFFC00014 #define SWRST 0xFFC00100 /* Software Reset Register */ #define SYSCR 0xFFC00104 /* System Configuration register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ -#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ -#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ #endif /* __BFIN_DEF_ADSP_BF549_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h index e2c165ace3..211ba884ed 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_cdef.h @@ -8,456 +8,1402 @@ #include "../mach-common/ADSP-EDN-core_cdef.h" -#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h" - -#define pSRAM_BASE_ADDR ((uint32_t volatile *)SRAM_BASE_ADDR) -#define bfin_read_SRAM_BASE_ADDR() bfin_read32(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) -#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) -#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) -#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR) -#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((uint32_t volatile *)DCPLB_ADDR0) -#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((uint32_t volatile *)DCPLB_ADDR1) -#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((uint32_t volatile *)DCPLB_ADDR2) -#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((uint32_t volatile *)DCPLB_ADDR3) -#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((uint32_t volatile *)DCPLB_ADDR4) -#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((uint32_t volatile *)DCPLB_ADDR5) -#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((uint32_t volatile *)DCPLB_ADDR6) -#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((uint32_t volatile *)DCPLB_ADDR7) -#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((uint32_t volatile *)DCPLB_ADDR8) -#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((uint32_t volatile *)DCPLB_ADDR9) -#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((uint32_t volatile *)DCPLB_ADDR10) -#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((uint32_t volatile *)DCPLB_ADDR11) -#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((uint32_t volatile *)DCPLB_ADDR12) -#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((uint32_t volatile *)DCPLB_ADDR13) -#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((uint32_t volatile *)DCPLB_ADDR14) -#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((uint32_t volatile *)DCPLB_ADDR15) -#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) -#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) -#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) -#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR) -#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((uint32_t volatile *)ICPLB_ADDR0) -#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((uint32_t volatile *)ICPLB_ADDR1) -#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((uint32_t volatile *)ICPLB_ADDR2) -#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((uint32_t volatile *)ICPLB_ADDR3) -#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((uint32_t volatile *)ICPLB_ADDR4) -#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((uint32_t volatile *)ICPLB_ADDR5) -#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((uint32_t volatile *)ICPLB_ADDR6) -#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((uint32_t volatile *)ICPLB_ADDR7) -#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((uint32_t volatile *)ICPLB_ADDR8) -#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((uint32_t volatile *)ICPLB_ADDR9) -#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((uint32_t volatile *)ICPLB_ADDR10) -#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((uint32_t volatile *)ICPLB_ADDR11) -#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((uint32_t volatile *)ICPLB_ADDR12) -#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((uint32_t volatile *)ICPLB_ADDR13) -#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((uint32_t volatile *)ICPLB_ADDR14) -#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((uint32_t volatile *)ICPLB_ADDR15) -#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST) +#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) +#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) +#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) +#define bfin_read_VR_CTL() bfin_read16(VR_CTL) +#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) +#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) +#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) +#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL) +#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val) +#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT) +#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val) +#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT) +#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val) +#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL) +#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val) +#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT) +#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val) +#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT) +#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val) +#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) +#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) +#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) +#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) +#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) +#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val) +#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR) +#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR) +#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val) +#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT) +#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val) +#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT) +#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val) +#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY) +#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val) +#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY) +#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val) +#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR) +#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val) +#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR) +#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val) +#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT) +#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val) +#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT) +#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val) +#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS) +#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val) +#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP) +#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG) +#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val) +#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR) +#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR) +#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val) +#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT) +#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val) +#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT) +#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val) +#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY) +#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val) +#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY) +#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val) +#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR) +#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val) +#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR) +#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val) +#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT) +#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val) +#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT) +#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val) +#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS) +#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val) +#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP) +#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG) +#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val) +#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR) +#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR) +#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val) +#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT) +#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val) +#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT) +#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val) +#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY) +#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val) +#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY) +#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val) +#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR) +#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val) +#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR) +#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val) +#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT) +#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val) +#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT) +#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val) +#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS) +#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val) +#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP) +#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG) +#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val) +#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR) +#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR) +#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val) +#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT) +#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val) +#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT) +#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val) +#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY) +#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val) +#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY) +#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val) +#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR) +#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val) +#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR) +#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val) +#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT) +#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val) +#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT) +#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val) +#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS) +#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val) +#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP) +#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG) +#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val) +#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR) +#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR) +#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val) +#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT) +#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val) +#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT) +#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val) +#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY) +#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val) +#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY) +#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val) +#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR) +#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val) +#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR) +#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val) +#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT) +#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val) +#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT) +#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val) +#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS) +#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val) +#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP) +#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG) +#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val) +#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR) +#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR) +#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val) +#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT) +#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val) +#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT) +#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val) +#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY) +#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val) +#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY) +#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val) +#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR) +#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val) +#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR) +#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val) +#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT) +#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val) +#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT) +#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val) +#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS) +#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val) +#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP) +#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG) +#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val) +#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR) +#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR) +#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val) +#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT) +#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val) +#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT) +#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val) +#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY) +#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val) +#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY) +#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val) +#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR) +#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val) +#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR) +#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val) +#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT) +#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val) +#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT) +#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val) +#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS) +#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val) +#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP) +#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG) +#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val) +#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR) +#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR) +#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val) +#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT) +#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val) +#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT) +#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val) +#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY) +#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val) +#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY) +#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val) +#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR) +#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val) +#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR) +#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val) +#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT) +#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val) +#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT) +#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val) +#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS) +#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val) +#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP) +#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG) +#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val) +#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR) +#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR) +#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val) +#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT) +#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val) +#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT) +#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val) +#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY) +#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val) +#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY) +#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val) +#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR) +#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val) +#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR) +#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val) +#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT) +#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val) +#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT) +#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val) +#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS) +#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val) +#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP) +#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG) +#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val) +#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR) +#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR) +#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val) +#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT) +#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val) +#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT) +#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val) +#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY) +#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val) +#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY) +#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val) +#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR) +#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val) +#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR) +#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val) +#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT) +#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val) +#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT) +#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val) +#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS) +#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val) +#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP) +#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG) +#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val) +#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR) +#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR) +#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val) +#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT) +#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val) +#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT) +#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val) +#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY) +#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val) +#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY) +#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val) +#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR) +#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val) +#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR) +#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val) +#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT) +#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val) +#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT) +#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val) +#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS) +#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val) +#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP) +#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val) +#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG) +#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val) +#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR) +#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val) +#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR) +#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val) +#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT) +#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val) +#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT) +#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val) +#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY) +#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val) +#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY) +#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val) +#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR) +#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val) +#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR) +#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val) +#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT) +#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val) +#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT) +#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val) +#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS) +#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val) +#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) +#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) +#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val) +#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) +#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val) +#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) +#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val) +#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR) +#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR) +#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val) +#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT) +#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val) +#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT) +#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val) +#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY) +#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val) +#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY) +#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val) +#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR) +#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val) +#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR) +#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val) +#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT) +#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val) +#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT) +#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val) +#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS) +#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val) +#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP) +#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG) +#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val) +#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR) +#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR) +#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val) +#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT) +#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val) +#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT) +#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val) +#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY) +#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val) +#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY) +#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val) +#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR) +#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val) +#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR) +#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val) +#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT) +#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val) +#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT) +#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val) +#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS) +#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val) +#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP) +#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG) +#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val) +#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR) +#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR) +#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val) +#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT) +#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val) +#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT) +#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val) +#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY) +#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val) +#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY) +#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val) +#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR) +#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val) +#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR) +#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val) +#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT) +#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val) +#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT) +#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val) +#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS) +#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val) +#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP) +#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG) +#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val) +#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR) +#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR) +#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val) +#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT) +#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val) +#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT) +#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val) +#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY) +#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val) +#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY) +#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val) +#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR) +#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val) +#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR) +#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val) +#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT) +#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val) +#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT) +#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val) +#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS) +#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val) +#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP) +#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG) +#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val) +#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR) +#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR) +#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val) +#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT) +#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val) +#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT) +#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val) +#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY) +#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val) +#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY) +#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val) +#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR) +#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val) +#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR) +#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val) +#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT) +#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val) +#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT) +#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val) +#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS) +#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val) +#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP) +#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG) +#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val) +#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR) +#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR) +#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val) +#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT) +#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val) +#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT) +#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val) +#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY) +#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val) +#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY) +#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val) +#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR) +#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val) +#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR) +#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val) +#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT) +#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val) +#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT) +#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val) +#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS) +#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val) +#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP) +#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG) +#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val) +#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR) +#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR) +#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val) +#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT) +#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val) +#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT) +#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val) +#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY) +#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val) +#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY) +#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val) +#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR) +#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val) +#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR) +#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val) +#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT) +#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val) +#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT) +#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val) +#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS) +#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val) +#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP) +#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG) +#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val) +#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR) +#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR) +#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val) +#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT) +#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val) +#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT) +#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val) +#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY) +#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val) +#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY) +#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val) +#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR) +#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val) +#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR) +#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val) +#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT) +#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val) +#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT) +#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val) +#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS) +#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val) +#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP) +#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG) +#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val) +#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR) +#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR) +#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val) +#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT) +#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val) +#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT) +#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val) +#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY) +#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val) +#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY) +#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val) +#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR) +#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val) +#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR) +#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val) +#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT) +#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val) +#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT) +#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val) +#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS) +#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val) +#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP) +#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG) +#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val) +#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR) +#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR) +#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val) +#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT) +#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val) +#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT) +#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val) +#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY) +#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val) +#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY) +#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val) +#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR) +#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val) +#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR) +#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val) +#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT) +#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val) +#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT) +#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val) +#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS) +#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val) +#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP) +#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG) +#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val) +#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR) +#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR) +#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val) +#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT) +#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val) +#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT) +#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val) +#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY) +#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val) +#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY) +#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val) +#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR) +#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val) +#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR) +#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val) +#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT) +#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val) +#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT) +#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val) +#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS) +#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val) +#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP) +#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val) +#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG) +#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val) +#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR) +#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val) +#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR) +#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val) +#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT) +#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val) +#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT) +#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val) +#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY) +#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val) +#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY) +#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val) +#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR) +#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val) +#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR) +#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val) +#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT) +#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val) +#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT) +#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val) +#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS) +#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val) +#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) +#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val) +#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG) +#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val) +#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR) +#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val) +#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR) +#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val) +#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT) +#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val) +#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT) +#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val) +#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY) +#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val) +#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY) +#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val) +#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR) +#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val) +#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR) +#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val) +#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT) +#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val) +#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT) +#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val) +#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS) +#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val) +#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) +#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val) +#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR) +#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val) +#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR) +#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val) +#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT) +#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val) +#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT) +#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val) +#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY) +#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val) +#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY) +#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val) +#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR) +#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val) +#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR) +#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val) +#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT) +#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val) +#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT) +#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val) +#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS) +#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val) +#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG) +#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val) +#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR) +#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val) +#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR) +#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val) +#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT) +#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val) +#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT) +#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val) +#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY) +#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val) +#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY) +#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val) +#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR) +#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val) +#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR) +#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val) +#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT) +#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val) +#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT) +#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val) +#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) +#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val) +#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG) +#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val) +#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR) +#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val) +#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR) +#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val) +#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT) +#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val) +#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT) +#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val) +#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY) +#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val) +#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY) +#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val) +#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR) +#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val) +#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR) +#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val) +#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT) +#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val) +#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT) +#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val) +#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS) +#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val) +#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) +#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) +#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) +#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) +#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) +#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) +#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) +#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) +#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) +#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) +#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) +#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) +#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) +#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) +#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) +#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) +#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) +#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) +#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) +#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) +#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) +#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) +#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) +#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) +#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) +#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) +#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) +#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) +#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) +#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) +#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) +#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) +#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) +#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) +#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) +#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) +#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) +#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) +#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) +#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) +#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) +#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) +#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) +#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) +#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) +#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) +#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) +#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) +#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) +#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) +#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) +#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) +#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) +#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) +#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) +#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) +#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) +#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) +#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) +#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) +#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) +#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) +#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) +#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) +#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) +#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) +#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) +#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) +#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) +#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) +#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) +#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) +#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) +#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) +#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) +#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) +#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) +#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val) +#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR) +#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR) +#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val) +#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) +#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val) +#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) +#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val) +#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) +#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val) +#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) +#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val) +#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR) +#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val) +#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR) +#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val) +#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) +#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val) +#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) +#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val) +#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) +#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val) +#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) +#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) +#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val) +#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR) +#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val) +#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR) +#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val) +#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) +#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val) +#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) +#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val) +#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) +#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val) +#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) +#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val) +#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR) +#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val) +#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR) +#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val) +#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) +#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val) +#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) +#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val) +#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) +#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val) +#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) +#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val) +#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) +#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val) +#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR) +#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR) +#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val) +#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) +#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val) +#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) +#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val) +#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) +#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val) +#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) +#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val) +#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR) +#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val) +#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR) +#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val) +#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) +#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val) +#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) +#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val) +#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) +#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val) +#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) +#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val) +#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) +#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val) +#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR) +#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val) +#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR) +#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val) +#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) +#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val) +#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) +#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val) +#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) +#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val) +#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) +#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val) +#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR) +#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val) +#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR) +#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val) +#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) +#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val) +#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) +#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val) +#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) +#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val) +#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) +#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) +#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) +#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) +#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) +#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) +#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) +#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) +#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) +#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) +#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) +#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) +#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) +#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) +#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) +#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) +#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) +#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) +#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) +#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) +#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) +#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) +#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) +#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) +#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) +#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) +#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) +#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) +#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) +#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) +#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) +#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) +#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) +#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) +#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) +#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) +#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) +#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) +#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) +#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) +#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) +#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) +#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) +#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) +#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) +#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) +#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) +#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) +#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) +#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) +#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) +#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) +#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) +#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) +#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) +#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) +#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) +#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG) +#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val) +#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER) +#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val) +#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD) +#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val) +#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH) +#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val) +#define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE) +#define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val) +#define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE) +#define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val) +#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS) +#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val) +#define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE) +#define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val) +#define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE) +#define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val) +#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS) +#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val) +#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D) +#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val) +#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C) +#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val) +#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S) +#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val) +#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T) +#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val) +#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D) +#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val) +#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C) +#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val) +#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S) +#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val) +#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T) +#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val) +#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D) +#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val) +#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C) +#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val) +#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S) +#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val) +#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T) +#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val) +#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR) +#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val) +#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR) +#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val) +#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE) +#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val) +#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH) +#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val) +#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN) +#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val) +#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D) +#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val) +#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C) +#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val) +#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S) +#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val) +#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T) +#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val) +#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D) +#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val) +#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C) +#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val) +#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S) +#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val) +#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T) +#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val) +#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D) +#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val) +#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C) +#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val) +#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S) +#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val) +#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T) +#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val) +#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR) +#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val) +#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR) +#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val) +#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE) +#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val) +#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH) +#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val) +#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN) +#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val) +#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D) +#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val) +#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C) +#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val) +#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S) +#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val) +#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T) +#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val) +#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D) +#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val) +#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C) +#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val) +#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S) +#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val) +#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T) +#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val) +#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D) +#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val) +#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C) +#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val) +#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S) +#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val) +#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T) +#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val) +#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR) +#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val) +#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR) +#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val) +#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE) +#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val) +#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH) +#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val) +#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN) +#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val) +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) +#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) +#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) +#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) +#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) +#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) +#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) +#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) +#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) +#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) +#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) +#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) +#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) +#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) +#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) +#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) +#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) +#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) +#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) +#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) +#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) +#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) #define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) #define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val) -#define pSICA_SYSCR ((uint16_t volatile *)SICA_SYSCR) #define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR) #define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR, val) -#define pSICA_RVECT ((uint16_t volatile *)SICA_RVECT) #define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT) #define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT, val) -#define pSICA_IMASK0 ((uint32_t volatile *)SICA_IMASK0) #define bfin_read_SICA_IMASK0() bfin_read32(SICA_IMASK0) #define bfin_write_SICA_IMASK0(val) bfin_write32(SICA_IMASK0, val) -#define pSICA_IMASK1 ((uint32_t volatile *)SICA_IMASK1) #define bfin_read_SICA_IMASK1() bfin_read32(SICA_IMASK1) #define bfin_write_SICA_IMASK1(val) bfin_write32(SICA_IMASK1, val) -#define pSICA_ISR0 ((uint32_t volatile *)SICA_ISR0) #define bfin_read_SICA_ISR0() bfin_read32(SICA_ISR0) #define bfin_write_SICA_ISR0(val) bfin_write32(SICA_ISR0, val) -#define pSICA_ISR1 ((uint32_t volatile *)SICA_ISR1) #define bfin_read_SICA_ISR1() bfin_read32(SICA_ISR1) #define bfin_write_SICA_ISR1(val) bfin_write32(SICA_ISR1, val) -#define pSICA_IWR0 ((uint32_t volatile *)SICA_IWR0) #define bfin_read_SICA_IWR0() bfin_read32(SICA_IWR0) #define bfin_write_SICA_IWR0(val) bfin_write32(SICA_IWR0, val) -#define pSICA_IWR1 ((uint32_t volatile *)SICA_IWR1) #define bfin_read_SICA_IWR1() bfin_read32(SICA_IWR1) #define bfin_write_SICA_IWR1(val) bfin_write32(SICA_IWR1, val) -#define pSICA_IAR0 ((uint32_t volatile *)SICA_IAR0) #define bfin_read_SICA_IAR0() bfin_read32(SICA_IAR0) #define bfin_write_SICA_IAR0(val) bfin_write32(SICA_IAR0, val) -#define pSICA_IAR1 ((uint32_t volatile *)SICA_IAR1) #define bfin_read_SICA_IAR1() bfin_read32(SICA_IAR1) #define bfin_write_SICA_IAR1(val) bfin_write32(SICA_IAR1, val) -#define pSICA_IAR2 ((uint32_t volatile *)SICA_IAR2) #define bfin_read_SICA_IAR2() bfin_read32(SICA_IAR2) #define bfin_write_SICA_IAR2(val) bfin_write32(SICA_IAR2, val) -#define pSICA_IAR3 ((uint32_t volatile *)SICA_IAR3) #define bfin_read_SICA_IAR3() bfin_read32(SICA_IAR3) #define bfin_write_SICA_IAR3(val) bfin_write32(SICA_IAR3, val) -#define pSICA_IAR4 ((uint32_t volatile *)SICA_IAR4) #define bfin_read_SICA_IAR4() bfin_read32(SICA_IAR4) #define bfin_write_SICA_IAR4(val) bfin_write32(SICA_IAR4, val) -#define pSICA_IAR5 ((uint32_t volatile *)SICA_IAR5) #define bfin_read_SICA_IAR5() bfin_read32(SICA_IAR5) #define bfin_write_SICA_IAR5(val) bfin_write32(SICA_IAR5, val) -#define pSICA_IAR6 ((uint32_t volatile *)SICA_IAR6) #define bfin_read_SICA_IAR6() bfin_read32(SICA_IAR6) #define bfin_write_SICA_IAR6(val) bfin_write32(SICA_IAR6, val) -#define pSICA_IAR7 ((uint32_t volatile *)SICA_IAR7) #define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) #define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val) -#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST) #define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) #define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val) -#define pSICB_SYSCR ((uint16_t volatile *)SICB_SYSCR) #define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR) #define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR, val) -#define pSICB_RVECT ((uint16_t volatile *)SICB_RVECT) #define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT) #define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT, val) -#define pSICB_IMASK0 ((uint32_t volatile *)SICB_IMASK0) #define bfin_read_SICB_IMASK0() bfin_read32(SICB_IMASK0) #define bfin_write_SICB_IMASK0(val) bfin_write32(SICB_IMASK0, val) -#define pSICB_IMASK1 ((uint32_t volatile *)SICB_IMASK1) #define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1) #define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1, val) -#define pSICB_ISR0 ((uint32_t volatile *)SICB_ISR0) #define bfin_read_SICB_ISR0() bfin_read32(SICB_ISR0) #define bfin_write_SICB_ISR0(val) bfin_write32(SICB_ISR0, val) -#define pSICB_ISR1 ((uint32_t volatile *)SICB_ISR1) #define bfin_read_SICB_ISR1() bfin_read32(SICB_ISR1) #define bfin_write_SICB_ISR1(val) bfin_write32(SICB_ISR1, val) -#define pSICB_IWR0 ((uint32_t volatile *)SICB_IWR0) #define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0) #define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0, val) -#define pSICB_IWR1 ((uint32_t volatile *)SICB_IWR1) #define bfin_read_SICB_IWR1() bfin_read32(SICB_IWR1) #define bfin_write_SICB_IWR1(val) bfin_write32(SICB_IWR1, val) -#define pSICB_IAR0 ((uint32_t volatile *)SICB_IAR0) #define bfin_read_SICB_IAR0() bfin_read32(SICB_IAR0) #define bfin_write_SICB_IAR0(val) bfin_write32(SICB_IAR0, val) -#define pSICB_IAR1 ((uint32_t volatile *)SICB_IAR1) #define bfin_read_SICB_IAR1() bfin_read32(SICB_IAR1) #define bfin_write_SICB_IAR1(val) bfin_write32(SICB_IAR1, val) -#define pSICB_IAR2 ((uint32_t volatile *)SICB_IAR2) #define bfin_read_SICB_IAR2() bfin_read32(SICB_IAR2) #define bfin_write_SICB_IAR2(val) bfin_write32(SICB_IAR2, val) -#define pSICB_IAR3 ((uint32_t volatile *)SICB_IAR3) #define bfin_read_SICB_IAR3() bfin_read32(SICB_IAR3) #define bfin_write_SICB_IAR3(val) bfin_write32(SICB_IAR3, val) -#define pSICB_IAR4 ((uint32_t volatile *)SICB_IAR4) #define bfin_read_SICB_IAR4() bfin_read32(SICB_IAR4) #define bfin_write_SICB_IAR4(val) bfin_write32(SICB_IAR4, val) -#define pSICB_IAR5 ((uint32_t volatile *)SICB_IAR5) #define bfin_read_SICB_IAR5() bfin_read32(SICB_IAR5) #define bfin_write_SICB_IAR5(val) bfin_write32(SICB_IAR5, val) -#define pSICB_IAR6 ((uint32_t volatile *)SICB_IAR6) #define bfin_read_SICB_IAR6() bfin_read32(SICB_IAR6) #define bfin_write_SICB_IAR6(val) bfin_write32(SICB_IAR6, val) -#define pSICB_IAR7 ((uint32_t volatile *)SICB_IAR7) #define bfin_read_SICB_IAR7() bfin_read32(SICB_IAR7) #define bfin_write_SICB_IAR7(val) bfin_write32(SICB_IAR7, val) -#define pPPI0_CONTROL ((uint16_t volatile *)PPI0_CONTROL) #define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL) #define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL, val) -#define pPPI0_STATUS ((uint16_t volatile *)PPI0_STATUS) #define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS) #define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS, val) -#define pPPI0_DELAY ((uint16_t volatile *)PPI0_DELAY) #define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY) #define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY, val) -#define pPPI0_COUNT ((uint16_t volatile *)PPI0_COUNT) #define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT) #define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT, val) -#define pPPI0_FRAME ((uint16_t volatile *)PPI0_FRAME) #define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME) #define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME, val) -#define pPPI1_CONTROL ((uint16_t volatile *)PPI1_CONTROL) #define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL) #define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL, val) -#define pPPI1_STATUS ((uint16_t volatile *)PPI1_STATUS) #define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS) #define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS, val) -#define pPPI1_DELAY ((uint16_t volatile *)PPI1_DELAY) #define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY) #define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY, val) -#define pPPI1_COUNT ((uint16_t volatile *)PPI1_COUNT) #define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT) #define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT, val) -#define pPPI1_FRAME ((uint16_t volatile *)PPI1_FRAME) #define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME) #define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((uint32_t volatile *)TBUF) -#define bfin_read_TBUF() bfin_read32(TBUF) -#define bfin_write_TBUF(val) bfin_write32(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pSRAM_BASE_ADDR_CORE_A ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_A) -#define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A) -#define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val) -#define pSRAM_BASE_ADDR_CORE_B ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_B) -#define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B) -#define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val) -#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE) -#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) -#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) -#define pUART_THR ((uint16_t volatile *)UART_THR) #define bfin_read_UART_THR() bfin_read16(UART_THR) #define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) -#define pUART_RBR ((uint16_t volatile *)UART_RBR) #define bfin_read_UART_RBR() bfin_read16(UART_RBR) #define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val) -#define pUART_DLL ((uint16_t volatile *)UART_DLL) #define bfin_read_UART_DLL() bfin_read16(UART_DLL) #define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val) -#define pUART_DLH ((uint16_t volatile *)UART_DLH) #define bfin_read_UART_DLH() bfin_read16(UART_DLH) #define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val) -#define pUART_IER ((uint16_t volatile *)UART_IER) #define bfin_read_UART_IER() bfin_read16(UART_IER) #define bfin_write_UART_IER(val) bfin_write16(UART_IER, val) -#define pUART_IIR ((uint16_t volatile *)UART_IIR) #define bfin_read_UART_IIR() bfin_read16(UART_IIR) #define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val) -#define pUART_LCR ((uint16_t volatile *)UART_LCR) #define bfin_read_UART_LCR() bfin_read16(UART_LCR) #define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val) -#define pUART_MCR ((uint16_t volatile *)UART_MCR) #define bfin_read_UART_MCR() bfin_read16(UART_MCR) #define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val) -#define pUART_LSR ((uint16_t volatile *)UART_LSR) #define bfin_read_UART_LSR() bfin_read16(UART_LSR) #define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val) -#define pUART_MSR ((uint16_t volatile *)UART_MSR) #define bfin_read_UART_MSR() bfin_read16(UART_MSR) #define bfin_write_UART_MSR(val) bfin_write16(UART_MSR, val) -#define pUART_SCR ((uint16_t volatile *)UART_SCR) #define bfin_read_UART_SCR() bfin_read16(UART_SCR) #define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val) -#define pUART_GCTL ((uint16_t volatile *)UART_GCTL) #define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) #define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val) -#define pUART_GBL ((uint16_t volatile *)UART_GBL) #define bfin_read_UART_GBL() bfin_read16(UART_GBL) #define bfin_write_UART_GBL(val) bfin_write16(UART_GBL, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) #define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) #define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) #define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) #define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint32_t volatile *)EBIU_SDBCTL) #define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) #define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) #define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) #define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h index 8534962326..1aae565fe7 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h @@ -8,85 +8,642 @@ #include "../mach-common/ADSP-EDN-core_def.h" -#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h" - -#define SRAM_BASE_ADDR 0xFFE00000 -#define DMEM_CONTROL 0xFFE00004 -#define DCPLB_STATUS 0xFFE00008 -#define DCPLB_FAULT_ADDR 0xFFE0000C -#define DCPLB_ADDR0 0xFFE00100 -#define DCPLB_ADDR1 0xFFE00104 -#define DCPLB_ADDR2 0xFFE00108 -#define DCPLB_ADDR3 0xFFE0010C -#define DCPLB_ADDR4 0xFFE00110 -#define DCPLB_ADDR5 0xFFE00114 -#define DCPLB_ADDR6 0xFFE00118 -#define DCPLB_ADDR7 0xFFE0011C -#define DCPLB_ADDR8 0xFFE00120 -#define DCPLB_ADDR9 0xFFE00124 -#define DCPLB_ADDR10 0xFFE00128 -#define DCPLB_ADDR11 0xFFE0012C -#define DCPLB_ADDR12 0xFFE00130 -#define DCPLB_ADDR13 0xFFE00134 -#define DCPLB_ADDR14 0xFFE00138 -#define DCPLB_ADDR15 0xFFE0013C -#define DCPLB_DATA0 0xFFE00200 -#define DCPLB_DATA1 0xFFE00204 -#define DCPLB_DATA2 0xFFE00208 -#define DCPLB_DATA3 0xFFE0020C -#define DCPLB_DATA4 0xFFE00210 -#define DCPLB_DATA5 0xFFE00214 -#define DCPLB_DATA6 0xFFE00218 -#define DCPLB_DATA7 0xFFE0021C -#define DCPLB_DATA8 0xFFE00220 -#define DCPLB_DATA9 0xFFE00224 -#define DCPLB_DATA10 0xFFE00228 -#define DCPLB_DATA11 0xFFE0022C -#define DCPLB_DATA12 0xFFE00230 -#define DCPLB_DATA13 0xFFE00234 -#define DCPLB_DATA14 0xFFE00238 -#define DCPLB_DATA15 0xFFE0023C -#define DTEST_COMMAND 0xFFE00300 -#define DTEST_DATA0 0xFFE00400 -#define DTEST_DATA1 0xFFE00404 -#define IMEM_CONTROL 0xFFE01004 -#define ICPLB_STATUS 0xFFE01008 -#define ICPLB_FAULT_ADDR 0xFFE0100C -#define ICPLB_ADDR0 0xFFE01100 -#define ICPLB_ADDR1 0xFFE01104 -#define ICPLB_ADDR2 0xFFE01108 -#define ICPLB_ADDR3 0xFFE0110C -#define ICPLB_ADDR4 0xFFE01110 -#define ICPLB_ADDR5 0xFFE01114 -#define ICPLB_ADDR6 0xFFE01118 -#define ICPLB_ADDR7 0xFFE0111C -#define ICPLB_ADDR8 0xFFE01120 -#define ICPLB_ADDR9 0xFFE01124 -#define ICPLB_ADDR10 0xFFE01128 -#define ICPLB_ADDR11 0xFFE0112C -#define ICPLB_ADDR12 0xFFE01130 -#define ICPLB_ADDR13 0xFFE01134 -#define ICPLB_ADDR14 0xFFE01138 -#define ICPLB_ADDR15 0xFFE0113C -#define ICPLB_DATA0 0xFFE01200 -#define ICPLB_DATA1 0xFFE01204 -#define ICPLB_DATA2 0xFFE01208 -#define ICPLB_DATA3 0xFFE0120C -#define ICPLB_DATA4 0xFFE01210 -#define ICPLB_DATA5 0xFFE01214 -#define ICPLB_DATA6 0xFFE01218 -#define ICPLB_DATA7 0xFFE0121C -#define ICPLB_DATA8 0xFFE01220 -#define ICPLB_DATA9 0xFFE01224 -#define ICPLB_DATA10 0xFFE01228 -#define ICPLB_DATA11 0xFFE0122C -#define ICPLB_DATA12 0xFFE01230 -#define ICPLB_DATA13 0xFFE01234 -#define ICPLB_DATA14 0xFFE01238 -#define ICPLB_DATA15 0xFFE0123C -#define ITEST_COMMAND 0xFFE01300 -#define ITEST_DATA0 0xFFE01400 -#define ITEST_DATA1 0xFFE01404 +#define PLL_CTL 0xFFC00000 +#define PLL_DIV 0xFFC00004 +#define VR_CTL 0xFFC00008 +#define PLL_STAT 0xFFC0000C +#define PLL_LOCKCNT 0xFFC00010 +#define CHIPID 0xFFC00014 +#define SPI_CTL 0xFFC00500 +#define SPI_FLG 0xFFC00504 +#define SPI_STAT 0xFFC00508 +#define SPI_TDBR 0xFFC0050C +#define SPI_RDBR 0xFFC00510 +#define SPI_BAUD 0xFFC00514 +#define SPI_SHADOW 0xFFC00518 +#define WDOGA_CTL 0xFFC00200 +#define WDOGA_CNT 0xFFC00204 +#define WDOGA_STAT 0xFFC00208 +#define WDOGB_CTL 0xFFC01200 +#define WDOGB_CNT 0xFFC01204 +#define WDOGB_STAT 0xFFC01208 +#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */ +#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ +#define DMA1_0_CONFIG 0xFFC01C08 +#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 +#define DMA1_0_START_ADDR 0xFFC01C04 +#define DMA1_0_X_COUNT 0xFFC01C10 +#define DMA1_0_Y_COUNT 0xFFC01C18 +#define DMA1_0_X_MODIFY 0xFFC01C14 +#define DMA1_0_Y_MODIFY 0xFFC01C1C +#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 +#define DMA1_0_CURR_ADDR 0xFFC01C24 +#define DMA1_0_CURR_X_COUNT 0xFFC01C30 +#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 +#define DMA1_0_IRQ_STATUS 0xFFC01C28 +#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C +#define DMA1_1_CONFIG 0xFFC01C48 +#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 +#define DMA1_1_START_ADDR 0xFFC01C44 +#define DMA1_1_X_COUNT 0xFFC01C50 +#define DMA1_1_Y_COUNT 0xFFC01C58 +#define DMA1_1_X_MODIFY 0xFFC01C54 +#define DMA1_1_Y_MODIFY 0xFFC01C5C +#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 +#define DMA1_1_CURR_ADDR 0xFFC01C64 +#define DMA1_1_CURR_X_COUNT 0xFFC01C70 +#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 +#define DMA1_1_IRQ_STATUS 0xFFC01C68 +#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C +#define DMA1_2_CONFIG 0xFFC01C88 +#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 +#define DMA1_2_START_ADDR 0xFFC01C84 +#define DMA1_2_X_COUNT 0xFFC01C90 +#define DMA1_2_Y_COUNT 0xFFC01C98 +#define DMA1_2_X_MODIFY 0xFFC01C94 +#define DMA1_2_Y_MODIFY 0xFFC01C9C +#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 +#define DMA1_2_CURR_ADDR 0xFFC01CA4 +#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 +#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 +#define DMA1_2_IRQ_STATUS 0xFFC01CA8 +#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC +#define DMA1_3_CONFIG 0xFFC01CC8 +#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 +#define DMA1_3_START_ADDR 0xFFC01CC4 +#define DMA1_3_X_COUNT 0xFFC01CD0 +#define DMA1_3_Y_COUNT 0xFFC01CD8 +#define DMA1_3_X_MODIFY 0xFFC01CD4 +#define DMA1_3_Y_MODIFY 0xFFC01CDC +#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 +#define DMA1_3_CURR_ADDR 0xFFC01CE4 +#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 +#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 +#define DMA1_3_IRQ_STATUS 0xFFC01CE8 +#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC +#define DMA1_4_CONFIG 0xFFC01D08 +#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 +#define DMA1_4_START_ADDR 0xFFC01D04 +#define DMA1_4_X_COUNT 0xFFC01D10 +#define DMA1_4_Y_COUNT 0xFFC01D18 +#define DMA1_4_X_MODIFY 0xFFC01D14 +#define DMA1_4_Y_MODIFY 0xFFC01D1C +#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 +#define DMA1_4_CURR_ADDR 0xFFC01D24 +#define DMA1_4_CURR_X_COUNT 0xFFC01D30 +#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 +#define DMA1_4_IRQ_STATUS 0xFFC01D28 +#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C +#define DMA1_5_CONFIG 0xFFC01D48 +#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 +#define DMA1_5_START_ADDR 0xFFC01D44 +#define DMA1_5_X_COUNT 0xFFC01D50 +#define DMA1_5_Y_COUNT 0xFFC01D58 +#define DMA1_5_X_MODIFY 0xFFC01D54 +#define DMA1_5_Y_MODIFY 0xFFC01D5C +#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 +#define DMA1_5_CURR_ADDR 0xFFC01D64 +#define DMA1_5_CURR_X_COUNT 0xFFC01D70 +#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 +#define DMA1_5_IRQ_STATUS 0xFFC01D68 +#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C +#define DMA1_6_CONFIG 0xFFC01D88 +#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 +#define DMA1_6_START_ADDR 0xFFC01D84 +#define DMA1_6_X_COUNT 0xFFC01D90 +#define DMA1_6_Y_COUNT 0xFFC01D98 +#define DMA1_6_X_MODIFY 0xFFC01D94 +#define DMA1_6_Y_MODIFY 0xFFC01D9C +#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 +#define DMA1_6_CURR_ADDR 0xFFC01DA4 +#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 +#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 +#define DMA1_6_IRQ_STATUS 0xFFC01DA8 +#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC +#define DMA1_7_CONFIG 0xFFC01DC8 +#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 +#define DMA1_7_START_ADDR 0xFFC01DC4 +#define DMA1_7_X_COUNT 0xFFC01DD0 +#define DMA1_7_Y_COUNT 0xFFC01DD8 +#define DMA1_7_X_MODIFY 0xFFC01DD4 +#define DMA1_7_Y_MODIFY 0xFFC01DDC +#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 +#define DMA1_7_CURR_ADDR 0xFFC01DE4 +#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 +#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 +#define DMA1_7_IRQ_STATUS 0xFFC01DE8 +#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC +#define DMA1_8_CONFIG 0xFFC01E08 +#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 +#define DMA1_8_START_ADDR 0xFFC01E04 +#define DMA1_8_X_COUNT 0xFFC01E10 +#define DMA1_8_Y_COUNT 0xFFC01E18 +#define DMA1_8_X_MODIFY 0xFFC01E14 +#define DMA1_8_Y_MODIFY 0xFFC01E1C +#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 +#define DMA1_8_CURR_ADDR 0xFFC01E24 +#define DMA1_8_CURR_X_COUNT 0xFFC01E30 +#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 +#define DMA1_8_IRQ_STATUS 0xFFC01E28 +#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C +#define DMA1_9_CONFIG 0xFFC01E48 +#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 +#define DMA1_9_START_ADDR 0xFFC01E44 +#define DMA1_9_X_COUNT 0xFFC01E50 +#define DMA1_9_Y_COUNT 0xFFC01E58 +#define DMA1_9_X_MODIFY 0xFFC01E54 +#define DMA1_9_Y_MODIFY 0xFFC01E5C +#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 +#define DMA1_9_CURR_ADDR 0xFFC01E64 +#define DMA1_9_CURR_X_COUNT 0xFFC01E70 +#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 +#define DMA1_9_IRQ_STATUS 0xFFC01E68 +#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C +#define DMA1_10_CONFIG 0xFFC01E88 +#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 +#define DMA1_10_START_ADDR 0xFFC01E84 +#define DMA1_10_X_COUNT 0xFFC01E90 +#define DMA1_10_Y_COUNT 0xFFC01E98 +#define DMA1_10_X_MODIFY 0xFFC01E94 +#define DMA1_10_Y_MODIFY 0xFFC01E9C +#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 +#define DMA1_10_CURR_ADDR 0xFFC01EA4 +#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 +#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 +#define DMA1_10_IRQ_STATUS 0xFFC01EA8 +#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC +#define DMA1_11_CONFIG 0xFFC01EC8 +#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 +#define DMA1_11_START_ADDR 0xFFC01EC4 +#define DMA1_11_X_COUNT 0xFFC01ED0 +#define DMA1_11_Y_COUNT 0xFFC01ED8 +#define DMA1_11_X_MODIFY 0xFFC01ED4 +#define DMA1_11_Y_MODIFY 0xFFC01EDC +#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 +#define DMA1_11_CURR_ADDR 0xFFC01EE4 +#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 +#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 +#define DMA1_11_IRQ_STATUS 0xFFC01EE8 +#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC +#define DMA2_TC_PER 0xFFC00B0C +#define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ +#define DMA2_0_CONFIG 0xFFC00C08 +#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 +#define DMA2_0_START_ADDR 0xFFC00C04 +#define DMA2_0_X_COUNT 0xFFC00C10 +#define DMA2_0_Y_COUNT 0xFFC00C18 +#define DMA2_0_X_MODIFY 0xFFC00C14 +#define DMA2_0_Y_MODIFY 0xFFC00C1C +#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 +#define DMA2_0_CURR_ADDR 0xFFC00C24 +#define DMA2_0_CURR_X_COUNT 0xFFC00C30 +#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 +#define DMA2_0_IRQ_STATUS 0xFFC00C28 +#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C +#define DMA2_1_CONFIG 0xFFC00C48 +#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 +#define DMA2_1_START_ADDR 0xFFC00C44 +#define DMA2_1_X_COUNT 0xFFC00C50 +#define DMA2_1_Y_COUNT 0xFFC00C58 +#define DMA2_1_X_MODIFY 0xFFC00C54 +#define DMA2_1_Y_MODIFY 0xFFC00C5C +#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 +#define DMA2_1_CURR_ADDR 0xFFC00C64 +#define DMA2_1_CURR_X_COUNT 0xFFC00C70 +#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 +#define DMA2_1_IRQ_STATUS 0xFFC00C68 +#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C +#define DMA2_2_CONFIG 0xFFC00C88 +#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 +#define DMA2_2_START_ADDR 0xFFC00C84 +#define DMA2_2_X_COUNT 0xFFC00C90 +#define DMA2_2_Y_COUNT 0xFFC00C98 +#define DMA2_2_X_MODIFY 0xFFC00C94 +#define DMA2_2_Y_MODIFY 0xFFC00C9C +#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 +#define DMA2_2_CURR_ADDR 0xFFC00CA4 +#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 +#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 +#define DMA2_2_IRQ_STATUS 0xFFC00CA8 +#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC +#define DMA2_3_CONFIG 0xFFC00CC8 +#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 +#define DMA2_3_START_ADDR 0xFFC00CC4 +#define DMA2_3_X_COUNT 0xFFC00CD0 +#define DMA2_3_Y_COUNT 0xFFC00CD8 +#define DMA2_3_X_MODIFY 0xFFC00CD4 +#define DMA2_3_Y_MODIFY 0xFFC00CDC +#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 +#define DMA2_3_CURR_ADDR 0xFFC00CE4 +#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 +#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 +#define DMA2_3_IRQ_STATUS 0xFFC00CE8 +#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC +#define DMA2_4_CONFIG 0xFFC00D08 +#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 +#define DMA2_4_START_ADDR 0xFFC00D04 +#define DMA2_4_X_COUNT 0xFFC00D10 +#define DMA2_4_Y_COUNT 0xFFC00D18 +#define DMA2_4_X_MODIFY 0xFFC00D14 +#define DMA2_4_Y_MODIFY 0xFFC00D1C +#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 +#define DMA2_4_CURR_ADDR 0xFFC00D24 +#define DMA2_4_CURR_X_COUNT 0xFFC00D30 +#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 +#define DMA2_4_IRQ_STATUS 0xFFC00D28 +#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C +#define DMA2_5_CONFIG 0xFFC00D48 +#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 +#define DMA2_5_START_ADDR 0xFFC00D44 +#define DMA2_5_X_COUNT 0xFFC00D50 +#define DMA2_5_Y_COUNT 0xFFC00D58 +#define DMA2_5_X_MODIFY 0xFFC00D54 +#define DMA2_5_Y_MODIFY 0xFFC00D5C +#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 +#define DMA2_5_CURR_ADDR 0xFFC00D64 +#define DMA2_5_CURR_X_COUNT 0xFFC00D70 +#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 +#define DMA2_5_IRQ_STATUS 0xFFC00D68 +#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C +#define DMA2_6_CONFIG 0xFFC00D88 +#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 +#define DMA2_6_START_ADDR 0xFFC00D84 +#define DMA2_6_X_COUNT 0xFFC00D90 +#define DMA2_6_Y_COUNT 0xFFC00D98 +#define DMA2_6_X_MODIFY 0xFFC00D94 +#define DMA2_6_Y_MODIFY 0xFFC00D9C +#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 +#define DMA2_6_CURR_ADDR 0xFFC00DA4 +#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 +#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 +#define DMA2_6_IRQ_STATUS 0xFFC00DA8 +#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC +#define DMA2_7_CONFIG 0xFFC00DC8 +#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 +#define DMA2_7_START_ADDR 0xFFC00DC4 +#define DMA2_7_X_COUNT 0xFFC00DD0 +#define DMA2_7_Y_COUNT 0xFFC00DD8 +#define DMA2_7_X_MODIFY 0xFFC00DD4 +#define DMA2_7_Y_MODIFY 0xFFC00DDC +#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 +#define DMA2_7_CURR_ADDR 0xFFC00DE4 +#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 +#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 +#define DMA2_7_IRQ_STATUS 0xFFC00DE8 +#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC +#define DMA2_8_CONFIG 0xFFC00E08 +#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 +#define DMA2_8_START_ADDR 0xFFC00E04 +#define DMA2_8_X_COUNT 0xFFC00E10 +#define DMA2_8_Y_COUNT 0xFFC00E18 +#define DMA2_8_X_MODIFY 0xFFC00E14 +#define DMA2_8_Y_MODIFY 0xFFC00E1C +#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 +#define DMA2_8_CURR_ADDR 0xFFC00E24 +#define DMA2_8_CURR_X_COUNT 0xFFC00E30 +#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 +#define DMA2_8_IRQ_STATUS 0xFFC00E28 +#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C +#define DMA2_9_CONFIG 0xFFC00E48 +#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 +#define DMA2_9_START_ADDR 0xFFC00E44 +#define DMA2_9_X_COUNT 0xFFC00E50 +#define DMA2_9_Y_COUNT 0xFFC00E58 +#define DMA2_9_X_MODIFY 0xFFC00E54 +#define DMA2_9_Y_MODIFY 0xFFC00E5C +#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 +#define DMA2_9_CURR_ADDR 0xFFC00E64 +#define DMA2_9_CURR_X_COUNT 0xFFC00E70 +#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 +#define DMA2_9_IRQ_STATUS 0xFFC00E68 +#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C +#define DMA2_10_CONFIG 0xFFC00E88 +#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 +#define DMA2_10_START_ADDR 0xFFC00E84 +#define DMA2_10_X_COUNT 0xFFC00E90 +#define DMA2_10_Y_COUNT 0xFFC00E98 +#define DMA2_10_X_MODIFY 0xFFC00E94 +#define DMA2_10_Y_MODIFY 0xFFC00E9C +#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 +#define DMA2_10_CURR_ADDR 0xFFC00EA4 +#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 +#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 +#define DMA2_10_IRQ_STATUS 0xFFC00EA8 +#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC +#define DMA2_11_CONFIG 0xFFC00EC8 +#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 +#define DMA2_11_START_ADDR 0xFFC00EC4 +#define DMA2_11_X_COUNT 0xFFC00ED0 +#define DMA2_11_Y_COUNT 0xFFC00ED8 +#define DMA2_11_X_MODIFY 0xFFC00ED4 +#define DMA2_11_Y_MODIFY 0xFFC00EDC +#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 +#define DMA2_11_CURR_ADDR 0xFFC00EE4 +#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 +#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 +#define DMA2_11_IRQ_STATUS 0xFFC00EE8 +#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC +#define IMDMA_S0_CONFIG 0xFFC01848 +#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 +#define IMDMA_S0_START_ADDR 0xFFC01844 +#define IMDMA_S0_X_COUNT 0xFFC01850 +#define IMDMA_S0_Y_COUNT 0xFFC01858 +#define IMDMA_S0_X_MODIFY 0xFFC01854 +#define IMDMA_S0_Y_MODIFY 0xFFC0185C +#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 +#define IMDMA_S0_CURR_ADDR 0xFFC01864 +#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 +#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 +#define IMDMA_S0_IRQ_STATUS 0xFFC01868 +#define IMDMA_D0_CONFIG 0xFFC01808 +#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 +#define IMDMA_D0_START_ADDR 0xFFC01804 +#define IMDMA_D0_X_COUNT 0xFFC01810 +#define IMDMA_D0_Y_COUNT 0xFFC01818 +#define IMDMA_D0_X_MODIFY 0xFFC01814 +#define IMDMA_D0_Y_MODIFY 0xFFC0181C +#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 +#define IMDMA_D0_CURR_ADDR 0xFFC01824 +#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 +#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 +#define IMDMA_D0_IRQ_STATUS 0xFFC01828 +#define IMDMA_S1_CONFIG 0xFFC018C8 +#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 +#define IMDMA_S1_START_ADDR 0xFFC018C4 +#define IMDMA_S1_X_COUNT 0xFFC018D0 +#define IMDMA_S1_Y_COUNT 0xFFC018D8 +#define IMDMA_S1_X_MODIFY 0xFFC018D4 +#define IMDMA_S1_Y_MODIFY 0xFFC018DC +#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 +#define IMDMA_S1_CURR_ADDR 0xFFC018E4 +#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 +#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 +#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 +#define IMDMA_D1_CONFIG 0xFFC01888 +#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 +#define IMDMA_D1_START_ADDR 0xFFC01884 +#define IMDMA_D1_X_COUNT 0xFFC01890 +#define IMDMA_D1_Y_COUNT 0xFFC01898 +#define IMDMA_D1_X_MODIFY 0xFFC01894 +#define IMDMA_D1_Y_MODIFY 0xFFC0189C +#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 +#define IMDMA_D1_CURR_ADDR 0xFFC018A4 +#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 +#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 +#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 +#define MDMA1_S0_CONFIG 0xFFC01F48 +#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 +#define MDMA1_S0_START_ADDR 0xFFC01F44 +#define MDMA1_S0_X_COUNT 0xFFC01F50 +#define MDMA1_S0_Y_COUNT 0xFFC01F58 +#define MDMA1_S0_X_MODIFY 0xFFC01F54 +#define MDMA1_S0_Y_MODIFY 0xFFC01F5C +#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 +#define MDMA1_S0_CURR_ADDR 0xFFC01F64 +#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 +#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 +#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 +#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C +#define MDMA1_D0_CONFIG 0xFFC01F08 +#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 +#define MDMA1_D0_START_ADDR 0xFFC01F04 +#define MDMA1_D0_X_COUNT 0xFFC01F10 +#define MDMA1_D0_Y_COUNT 0xFFC01F18 +#define MDMA1_D0_X_MODIFY 0xFFC01F14 +#define MDMA1_D0_Y_MODIFY 0xFFC01F1C +#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 +#define MDMA1_D0_CURR_ADDR 0xFFC01F24 +#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 +#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 +#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 +#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C +#define MDMA1_S1_CONFIG 0xFFC01FC8 +#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 +#define MDMA1_S1_START_ADDR 0xFFC01FC4 +#define MDMA1_S1_X_COUNT 0xFFC01FD0 +#define MDMA1_S1_Y_COUNT 0xFFC01FD8 +#define MDMA1_S1_X_MODIFY 0xFFC01FD4 +#define MDMA1_S1_Y_MODIFY 0xFFC01FDC +#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 +#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 +#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 +#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 +#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 +#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC +#define MDMA1_D1_CONFIG 0xFFC01F88 +#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 +#define MDMA1_D1_START_ADDR 0xFFC01F84 +#define MDMA1_D1_X_COUNT 0xFFC01F90 +#define MDMA1_D1_Y_COUNT 0xFFC01F98 +#define MDMA1_D1_X_MODIFY 0xFFC01F94 +#define MDMA1_D1_Y_MODIFY 0xFFC01F9C +#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 +#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 +#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 +#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 +#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 +#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC +#define MDMA2_S0_CONFIG 0xFFC00F48 +#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 +#define MDMA2_S0_START_ADDR 0xFFC00F44 +#define MDMA2_S0_X_COUNT 0xFFC00F50 +#define MDMA2_S0_Y_COUNT 0xFFC00F58 +#define MDMA2_S0_X_MODIFY 0xFFC00F54 +#define MDMA2_S0_Y_MODIFY 0xFFC00F5C +#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 +#define MDMA2_S0_CURR_ADDR 0xFFC00F64 +#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 +#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 +#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 +#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C +#define MDMA2_D0_CONFIG 0xFFC00F08 +#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 +#define MDMA2_D0_START_ADDR 0xFFC00F04 +#define MDMA2_D0_X_COUNT 0xFFC00F10 +#define MDMA2_D0_Y_COUNT 0xFFC00F18 +#define MDMA2_D0_X_MODIFY 0xFFC00F14 +#define MDMA2_D0_Y_MODIFY 0xFFC00F1C +#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 +#define MDMA2_D0_CURR_ADDR 0xFFC00F24 +#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 +#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 +#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 +#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C +#define MDMA2_S1_CONFIG 0xFFC00FC8 +#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 +#define MDMA2_S1_START_ADDR 0xFFC00FC4 +#define MDMA2_S1_X_COUNT 0xFFC00FD0 +#define MDMA2_S1_Y_COUNT 0xFFC00FD8 +#define MDMA2_S1_X_MODIFY 0xFFC00FD4 +#define MDMA2_S1_Y_MODIFY 0xFFC00FDC +#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 +#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 +#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 +#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 +#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 +#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC +#define MDMA2_D1_CONFIG 0xFFC00F88 +#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 +#define MDMA2_D1_START_ADDR 0xFFC00F84 +#define MDMA2_D1_X_COUNT 0xFFC00F90 +#define MDMA2_D1_Y_COUNT 0xFFC00F98 +#define MDMA2_D1_X_MODIFY 0xFFC00F94 +#define MDMA2_D1_Y_MODIFY 0xFFC00F9C +#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 +#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 +#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 +#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 +#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 +#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC +#define TIMER0_CONFIG 0xFFC00600 +#define TIMER0_COUNTER 0xFFC00604 +#define TIMER0_PERIOD 0xFFC00608 +#define TIMER0_WIDTH 0xFFC0060C +#define TIMER1_CONFIG 0xFFC00610 +#define TIMER1_COUNTER 0xFFC00614 +#define TIMER1_PERIOD 0xFFC00618 +#define TIMER1_WIDTH 0xFFC0061C +#define TIMER2_CONFIG 0xFFC00620 +#define TIMER2_COUNTER 0xFFC00624 +#define TIMER2_PERIOD 0xFFC00628 +#define TIMER2_WIDTH 0xFFC0062C +#define TIMER3_CONFIG 0xFFC00630 +#define TIMER3_COUNTER 0xFFC00634 +#define TIMER3_PERIOD 0xFFC00638 +#define TIMER3_WIDTH 0xFFC0063C +#define TIMER4_CONFIG 0xFFC00640 +#define TIMER4_COUNTER 0xFFC00644 +#define TIMER4_PERIOD 0xFFC00648 +#define TIMER4_WIDTH 0xFFC0064C +#define TIMER5_CONFIG 0xFFC00650 +#define TIMER5_COUNTER 0xFFC00654 +#define TIMER5_PERIOD 0xFFC00658 +#define TIMER5_WIDTH 0xFFC0065C +#define TIMER6_CONFIG 0xFFC00660 +#define TIMER6_COUNTER 0xFFC00664 +#define TIMER6_PERIOD 0xFFC00668 +#define TIMER6_WIDTH 0xFFC0066C +#define TIMER7_CONFIG 0xFFC00670 +#define TIMER7_COUNTER 0xFFC00674 +#define TIMER7_PERIOD 0xFFC00678 +#define TIMER7_WIDTH 0xFFC0067C +#define TIMER8_CONFIG 0xFFC01600 +#define TIMER8_COUNTER 0xFFC01604 +#define TIMER8_PERIOD 0xFFC01608 +#define TIMER8_WIDTH 0xFFC0160C +#define TIMER9_CONFIG 0xFFC01610 +#define TIMER9_COUNTER 0xFFC01614 +#define TIMER9_PERIOD 0xFFC01618 +#define TIMER9_WIDTH 0xFFC0161C +#define TIMER10_CONFIG 0xFFC01620 +#define TIMER10_COUNTER 0xFFC01624 +#define TIMER10_PERIOD 0xFFC01628 +#define TIMER10_WIDTH 0xFFC0162C +#define TIMER11_CONFIG 0xFFC01630 +#define TIMER11_COUNTER 0xFFC01634 +#define TIMER11_PERIOD 0xFFC01638 +#define TIMER11_WIDTH 0xFFC0163C +#define TMRS4_ENABLE 0xFFC01640 +#define TMRS4_DISABLE 0xFFC01644 +#define TMRS4_STATUS 0xFFC01648 +#define TMRS8_ENABLE 0xFFC00680 +#define TMRS8_DISABLE 0xFFC00684 +#define TMRS8_STATUS 0xFFC00688 +#define FIO0_FLAG_D 0xFFC00700 +#define FIO0_FLAG_C 0xFFC00704 +#define FIO0_FLAG_S 0xFFC00708 +#define FIO0_FLAG_T 0xFFC0070C +#define FIO0_MASKA_D 0xFFC00710 +#define FIO0_MASKA_C 0xFFC00714 +#define FIO0_MASKA_S 0xFFC00718 +#define FIO0_MASKA_T 0xFFC0071C +#define FIO0_MASKB_D 0xFFC00720 +#define FIO0_MASKB_C 0xFFC00724 +#define FIO0_MASKB_S 0xFFC00728 +#define FIO0_MASKB_T 0xFFC0072C +#define FIO0_DIR 0xFFC00730 +#define FIO0_POLAR 0xFFC00734 +#define FIO0_EDGE 0xFFC00738 +#define FIO0_BOTH 0xFFC0073C +#define FIO0_INEN 0xFFC00740 +#define FIO1_FLAG_D 0xFFC01500 +#define FIO1_FLAG_C 0xFFC01504 +#define FIO1_FLAG_S 0xFFC01508 +#define FIO1_FLAG_T 0xFFC0150C +#define FIO1_MASKA_D 0xFFC01510 +#define FIO1_MASKA_C 0xFFC01514 +#define FIO1_MASKA_S 0xFFC01518 +#define FIO1_MASKA_T 0xFFC0151C +#define FIO1_MASKB_D 0xFFC01520 +#define FIO1_MASKB_C 0xFFC01524 +#define FIO1_MASKB_S 0xFFC01528 +#define FIO1_MASKB_T 0xFFC0152C +#define FIO1_DIR 0xFFC01530 +#define FIO1_POLAR 0xFFC01534 +#define FIO1_EDGE 0xFFC01538 +#define FIO1_BOTH 0xFFC0153C +#define FIO1_INEN 0xFFC01540 +#define FIO2_FLAG_D 0xFFC01700 +#define FIO2_FLAG_C 0xFFC01704 +#define FIO2_FLAG_S 0xFFC01708 +#define FIO2_FLAG_T 0xFFC0170C +#define FIO2_MASKA_D 0xFFC01710 +#define FIO2_MASKA_C 0xFFC01714 +#define FIO2_MASKA_S 0xFFC01718 +#define FIO2_MASKA_T 0xFFC0171C +#define FIO2_MASKB_D 0xFFC01720 +#define FIO2_MASKB_C 0xFFC01724 +#define FIO2_MASKB_S 0xFFC01728 +#define FIO2_MASKB_T 0xFFC0172C +#define FIO2_DIR 0xFFC01730 +#define FIO2_POLAR 0xFFC01734 +#define FIO2_EDGE 0xFFC01738 +#define FIO2_BOTH 0xFFC0173C +#define FIO2_INEN 0xFFC01740 +#define SPORT0_TCR1 0xFFC00800 +#define SPORT0_TCR2 0xFFC00804 +#define SPORT0_TCLKDIV 0xFFC00808 +#define SPORT0_TFSDIV 0xFFC0080C +#define SPORT0_TX 0xFFC00810 +#define SPORT0_RX 0xFFC00818 +#define SPORT0_RCR1 0xFFC00820 +#define SPORT0_RCR2 0xFFC00824 +#define SPORT0_RCLKDIV 0xFFC00828 +#define SPORT0_RFSDIV 0xFFC0082C +#define SPORT0_STAT 0xFFC00830 +#define SPORT0_CHNL 0xFFC00834 +#define SPORT0_MCMC1 0xFFC00838 +#define SPORT0_MCMC2 0xFFC0083C +#define SPORT0_MTCS0 0xFFC00840 +#define SPORT0_MTCS1 0xFFC00844 +#define SPORT0_MTCS2 0xFFC00848 +#define SPORT0_MTCS3 0xFFC0084C +#define SPORT0_MRCS0 0xFFC00850 +#define SPORT0_MRCS1 0xFFC00854 +#define SPORT0_MRCS2 0xFFC00858 +#define SPORT0_MRCS3 0xFFC0085C +#define SPORT1_TCR1 0xFFC00900 +#define SPORT1_TCR2 0xFFC00904 +#define SPORT1_TCLKDIV 0xFFC00908 +#define SPORT1_TFSDIV 0xFFC0090C +#define SPORT1_TX 0xFFC00910 +#define SPORT1_RX 0xFFC00918 +#define SPORT1_RCR1 0xFFC00920 +#define SPORT1_RCR2 0xFFC00924 +#define SPORT1_RCLKDIV 0xFFC00928 +#define SPORT1_RFSDIV 0xFFC0092C +#define SPORT1_STAT 0xFFC00930 +#define SPORT1_CHNL 0xFFC00934 +#define SPORT1_MCMC1 0xFFC00938 +#define SPORT1_MCMC2 0xFFC0093C +#define SPORT1_MTCS0 0xFFC00940 +#define SPORT1_MTCS1 0xFFC00944 +#define SPORT1_MTCS2 0xFFC00948 +#define SPORT1_MTCS3 0xFFC0094C +#define SPORT1_MRCS0 0xFFC00950 +#define SPORT1_MRCS1 0xFFC00954 +#define SPORT1_MRCS2 0xFFC00958 +#define SPORT1_MRCS3 0xFFC0095C #define SICA_SWRST 0xFFC00100 #define SICA_SYSCR 0xFFC00104 #define SICA_RVECT 0xFFC00108 @@ -131,15 +688,6 @@ #define PPI1_DELAY 0xFFC0130C #define PPI1_COUNT 0xFFC01308 #define PPI1_FRAME 0xFFC01310 -#define TBUFCTL 0xFFE06000 -#define TBUFSTAT 0xFFE06004 -#define TBUF 0xFFE06100 -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 -#define SRAM_BASE_ADDR_CORE_A 0xFFE00000 -#define SRAM_BASE_ADDR_CORE_B 0xFFE00000 -#define EVT_OVERRIDE 0xFFE02100 #define UART_THR 0xFFC00400 #define UART_RBR 0xFFC00400 #define UART_DLL 0xFFC00400 diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h deleted file mode 100644 index 43f385021d..0000000000 --- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h +++ /dev/null @@ -1,1988 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ -#define __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ - -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pWDOGA_CTL ((uint16_t volatile *)WDOGA_CTL) -#define bfin_read_WDOGA_CTL() bfin_read16(WDOGA_CTL) -#define bfin_write_WDOGA_CTL(val) bfin_write16(WDOGA_CTL, val) -#define pWDOGA_CNT ((uint32_t volatile *)WDOGA_CNT) -#define bfin_read_WDOGA_CNT() bfin_read32(WDOGA_CNT) -#define bfin_write_WDOGA_CNT(val) bfin_write32(WDOGA_CNT, val) -#define pWDOGA_STAT ((uint32_t volatile *)WDOGA_STAT) -#define bfin_read_WDOGA_STAT() bfin_read32(WDOGA_STAT) -#define bfin_write_WDOGA_STAT(val) bfin_write32(WDOGA_STAT, val) -#define pWDOGB_CTL ((uint16_t volatile *)WDOGB_CTL) -#define bfin_read_WDOGB_CTL() bfin_read16(WDOGB_CTL) -#define bfin_write_WDOGB_CTL(val) bfin_write16(WDOGB_CTL, val) -#define pWDOGB_CNT ((uint32_t volatile *)WDOGB_CNT) -#define bfin_read_WDOGB_CNT() bfin_read32(WDOGB_CNT) -#define bfin_write_WDOGB_CNT(val) bfin_write32(WDOGB_CNT, val) -#define pWDOGB_STAT ((uint32_t volatile *)WDOGB_STAT) -#define bfin_read_WDOGB_STAT() bfin_read32(WDOGB_STAT) -#define bfin_write_WDOGB_STAT(val) bfin_write32(WDOGB_STAT, val) -#define pDMA1_TC_PER ((uint16_t volatile *)DMA1_TC_PER) /* Traffic Control Periods */ -#define bfin_read_DMA1_TC_PER() bfin_read16(DMA1_TC_PER) -#define bfin_write_DMA1_TC_PER(val) bfin_write16(DMA1_TC_PER, val) -#define pDMA1_TC_CNT ((uint16_t volatile *)DMA1_TC_CNT) /* Traffic Control Current Counts */ -#define bfin_read_DMA1_TC_CNT() bfin_read16(DMA1_TC_CNT) -#define bfin_write_DMA1_TC_CNT(val) bfin_write16(DMA1_TC_CNT, val) -#define pDMA1_0_CONFIG ((uint16_t volatile *)DMA1_0_CONFIG) -#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG) -#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG, val) -#define pDMA1_0_NEXT_DESC_PTR ((void * volatile *)DMA1_0_NEXT_DESC_PTR) -#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_readPTR(DMA1_0_NEXT_DESC_PTR) -#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_0_NEXT_DESC_PTR, val) -#define pDMA1_0_START_ADDR ((void * volatile *)DMA1_0_START_ADDR) -#define bfin_read_DMA1_0_START_ADDR() bfin_readPTR(DMA1_0_START_ADDR) -#define bfin_write_DMA1_0_START_ADDR(val) bfin_writePTR(DMA1_0_START_ADDR, val) -#define pDMA1_0_X_COUNT ((uint16_t volatile *)DMA1_0_X_COUNT) -#define bfin_read_DMA1_0_X_COUNT() bfin_read16(DMA1_0_X_COUNT) -#define bfin_write_DMA1_0_X_COUNT(val) bfin_write16(DMA1_0_X_COUNT, val) -#define pDMA1_0_Y_COUNT ((uint16_t volatile *)DMA1_0_Y_COUNT) -#define bfin_read_DMA1_0_Y_COUNT() bfin_read16(DMA1_0_Y_COUNT) -#define bfin_write_DMA1_0_Y_COUNT(val) bfin_write16(DMA1_0_Y_COUNT, val) -#define pDMA1_0_X_MODIFY ((uint16_t volatile *)DMA1_0_X_MODIFY) -#define bfin_read_DMA1_0_X_MODIFY() bfin_read16(DMA1_0_X_MODIFY) -#define bfin_write_DMA1_0_X_MODIFY(val) bfin_write16(DMA1_0_X_MODIFY, val) -#define pDMA1_0_Y_MODIFY ((uint16_t volatile *)DMA1_0_Y_MODIFY) -#define bfin_read_DMA1_0_Y_MODIFY() bfin_read16(DMA1_0_Y_MODIFY) -#define bfin_write_DMA1_0_Y_MODIFY(val) bfin_write16(DMA1_0_Y_MODIFY, val) -#define pDMA1_0_CURR_DESC_PTR ((void * volatile *)DMA1_0_CURR_DESC_PTR) -#define bfin_read_DMA1_0_CURR_DESC_PTR() bfin_readPTR(DMA1_0_CURR_DESC_PTR) -#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_writePTR(DMA1_0_CURR_DESC_PTR, val) -#define pDMA1_0_CURR_ADDR ((void * volatile *)DMA1_0_CURR_ADDR) -#define bfin_read_DMA1_0_CURR_ADDR() bfin_readPTR(DMA1_0_CURR_ADDR) -#define bfin_write_DMA1_0_CURR_ADDR(val) bfin_writePTR(DMA1_0_CURR_ADDR, val) -#define pDMA1_0_CURR_X_COUNT ((uint16_t volatile *)DMA1_0_CURR_X_COUNT) -#define bfin_read_DMA1_0_CURR_X_COUNT() bfin_read16(DMA1_0_CURR_X_COUNT) -#define bfin_write_DMA1_0_CURR_X_COUNT(val) bfin_write16(DMA1_0_CURR_X_COUNT, val) -#define pDMA1_0_CURR_Y_COUNT ((uint16_t volatile *)DMA1_0_CURR_Y_COUNT) -#define bfin_read_DMA1_0_CURR_Y_COUNT() bfin_read16(DMA1_0_CURR_Y_COUNT) -#define bfin_write_DMA1_0_CURR_Y_COUNT(val) bfin_write16(DMA1_0_CURR_Y_COUNT, val) -#define pDMA1_0_IRQ_STATUS ((uint16_t volatile *)DMA1_0_IRQ_STATUS) -#define bfin_read_DMA1_0_IRQ_STATUS() bfin_read16(DMA1_0_IRQ_STATUS) -#define bfin_write_DMA1_0_IRQ_STATUS(val) bfin_write16(DMA1_0_IRQ_STATUS, val) -#define pDMA1_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_0_PERIPHERAL_MAP) -#define bfin_read_DMA1_0_PERIPHERAL_MAP() bfin_read16(DMA1_0_PERIPHERAL_MAP) -#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP, val) -#define pDMA1_1_CONFIG ((uint16_t volatile *)DMA1_1_CONFIG) -#define bfin_read_DMA1_1_CONFIG() bfin_read16(DMA1_1_CONFIG) -#define bfin_write_DMA1_1_CONFIG(val) bfin_write16(DMA1_1_CONFIG, val) -#define pDMA1_1_NEXT_DESC_PTR ((void * volatile *)DMA1_1_NEXT_DESC_PTR) -#define bfin_read_DMA1_1_NEXT_DESC_PTR() bfin_readPTR(DMA1_1_NEXT_DESC_PTR) -#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_1_NEXT_DESC_PTR, val) -#define pDMA1_1_START_ADDR ((void * volatile *)DMA1_1_START_ADDR) -#define bfin_read_DMA1_1_START_ADDR() bfin_readPTR(DMA1_1_START_ADDR) -#define bfin_write_DMA1_1_START_ADDR(val) bfin_writePTR(DMA1_1_START_ADDR, val) -#define pDMA1_1_X_COUNT ((uint16_t volatile *)DMA1_1_X_COUNT) -#define bfin_read_DMA1_1_X_COUNT() bfin_read16(DMA1_1_X_COUNT) -#define bfin_write_DMA1_1_X_COUNT(val) bfin_write16(DMA1_1_X_COUNT, val) -#define pDMA1_1_Y_COUNT ((uint16_t volatile *)DMA1_1_Y_COUNT) -#define bfin_read_DMA1_1_Y_COUNT() bfin_read16(DMA1_1_Y_COUNT) -#define bfin_write_DMA1_1_Y_COUNT(val) bfin_write16(DMA1_1_Y_COUNT, val) -#define pDMA1_1_X_MODIFY ((uint16_t volatile *)DMA1_1_X_MODIFY) -#define bfin_read_DMA1_1_X_MODIFY() bfin_read16(DMA1_1_X_MODIFY) -#define bfin_write_DMA1_1_X_MODIFY(val) bfin_write16(DMA1_1_X_MODIFY, val) -#define pDMA1_1_Y_MODIFY ((uint16_t volatile *)DMA1_1_Y_MODIFY) -#define bfin_read_DMA1_1_Y_MODIFY() bfin_read16(DMA1_1_Y_MODIFY) -#define bfin_write_DMA1_1_Y_MODIFY(val) bfin_write16(DMA1_1_Y_MODIFY, val) -#define pDMA1_1_CURR_DESC_PTR ((void * volatile *)DMA1_1_CURR_DESC_PTR) -#define bfin_read_DMA1_1_CURR_DESC_PTR() bfin_readPTR(DMA1_1_CURR_DESC_PTR) -#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_1_CURR_DESC_PTR, val) -#define pDMA1_1_CURR_ADDR ((void * volatile *)DMA1_1_CURR_ADDR) -#define bfin_read_DMA1_1_CURR_ADDR() bfin_readPTR(DMA1_1_CURR_ADDR) -#define bfin_write_DMA1_1_CURR_ADDR(val) bfin_writePTR(DMA1_1_CURR_ADDR, val) -#define pDMA1_1_CURR_X_COUNT ((uint16_t volatile *)DMA1_1_CURR_X_COUNT) -#define bfin_read_DMA1_1_CURR_X_COUNT() bfin_read16(DMA1_1_CURR_X_COUNT) -#define bfin_write_DMA1_1_CURR_X_COUNT(val) bfin_write16(DMA1_1_CURR_X_COUNT, val) -#define pDMA1_1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_1_CURR_Y_COUNT) -#define bfin_read_DMA1_1_CURR_Y_COUNT() bfin_read16(DMA1_1_CURR_Y_COUNT) -#define bfin_write_DMA1_1_CURR_Y_COUNT(val) bfin_write16(DMA1_1_CURR_Y_COUNT, val) -#define pDMA1_1_IRQ_STATUS ((uint16_t volatile *)DMA1_1_IRQ_STATUS) -#define bfin_read_DMA1_1_IRQ_STATUS() bfin_read16(DMA1_1_IRQ_STATUS) -#define bfin_write_DMA1_1_IRQ_STATUS(val) bfin_write16(DMA1_1_IRQ_STATUS, val) -#define pDMA1_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_1_PERIPHERAL_MAP) -#define bfin_read_DMA1_1_PERIPHERAL_MAP() bfin_read16(DMA1_1_PERIPHERAL_MAP) -#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP, val) -#define pDMA1_2_CONFIG ((uint16_t volatile *)DMA1_2_CONFIG) -#define bfin_read_DMA1_2_CONFIG() bfin_read16(DMA1_2_CONFIG) -#define bfin_write_DMA1_2_CONFIG(val) bfin_write16(DMA1_2_CONFIG, val) -#define pDMA1_2_NEXT_DESC_PTR ((void * volatile *)DMA1_2_NEXT_DESC_PTR) -#define bfin_read_DMA1_2_NEXT_DESC_PTR() bfin_readPTR(DMA1_2_NEXT_DESC_PTR) -#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_2_NEXT_DESC_PTR, val) -#define pDMA1_2_START_ADDR ((void * volatile *)DMA1_2_START_ADDR) -#define bfin_read_DMA1_2_START_ADDR() bfin_readPTR(DMA1_2_START_ADDR) -#define bfin_write_DMA1_2_START_ADDR(val) bfin_writePTR(DMA1_2_START_ADDR, val) -#define pDMA1_2_X_COUNT ((uint16_t volatile *)DMA1_2_X_COUNT) -#define bfin_read_DMA1_2_X_COUNT() bfin_read16(DMA1_2_X_COUNT) -#define bfin_write_DMA1_2_X_COUNT(val) bfin_write16(DMA1_2_X_COUNT, val) -#define pDMA1_2_Y_COUNT ((uint16_t volatile *)DMA1_2_Y_COUNT) -#define bfin_read_DMA1_2_Y_COUNT() bfin_read16(DMA1_2_Y_COUNT) -#define bfin_write_DMA1_2_Y_COUNT(val) bfin_write16(DMA1_2_Y_COUNT, val) -#define pDMA1_2_X_MODIFY ((uint16_t volatile *)DMA1_2_X_MODIFY) -#define bfin_read_DMA1_2_X_MODIFY() bfin_read16(DMA1_2_X_MODIFY) -#define bfin_write_DMA1_2_X_MODIFY(val) bfin_write16(DMA1_2_X_MODIFY, val) -#define pDMA1_2_Y_MODIFY ((uint16_t volatile *)DMA1_2_Y_MODIFY) -#define bfin_read_DMA1_2_Y_MODIFY() bfin_read16(DMA1_2_Y_MODIFY) -#define bfin_write_DMA1_2_Y_MODIFY(val) bfin_write16(DMA1_2_Y_MODIFY, val) -#define pDMA1_2_CURR_DESC_PTR ((void * volatile *)DMA1_2_CURR_DESC_PTR) -#define bfin_read_DMA1_2_CURR_DESC_PTR() bfin_readPTR(DMA1_2_CURR_DESC_PTR) -#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_writePTR(DMA1_2_CURR_DESC_PTR, val) -#define pDMA1_2_CURR_ADDR ((void * volatile *)DMA1_2_CURR_ADDR) -#define bfin_read_DMA1_2_CURR_ADDR() bfin_readPTR(DMA1_2_CURR_ADDR) -#define bfin_write_DMA1_2_CURR_ADDR(val) bfin_writePTR(DMA1_2_CURR_ADDR, val) -#define pDMA1_2_CURR_X_COUNT ((uint16_t volatile *)DMA1_2_CURR_X_COUNT) -#define bfin_read_DMA1_2_CURR_X_COUNT() bfin_read16(DMA1_2_CURR_X_COUNT) -#define bfin_write_DMA1_2_CURR_X_COUNT(val) bfin_write16(DMA1_2_CURR_X_COUNT, val) -#define pDMA1_2_CURR_Y_COUNT ((uint16_t volatile *)DMA1_2_CURR_Y_COUNT) -#define bfin_read_DMA1_2_CURR_Y_COUNT() bfin_read16(DMA1_2_CURR_Y_COUNT) -#define bfin_write_DMA1_2_CURR_Y_COUNT(val) bfin_write16(DMA1_2_CURR_Y_COUNT, val) -#define pDMA1_2_IRQ_STATUS ((uint16_t volatile *)DMA1_2_IRQ_STATUS) -#define bfin_read_DMA1_2_IRQ_STATUS() bfin_read16(DMA1_2_IRQ_STATUS) -#define bfin_write_DMA1_2_IRQ_STATUS(val) bfin_write16(DMA1_2_IRQ_STATUS, val) -#define pDMA1_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_2_PERIPHERAL_MAP) -#define bfin_read_DMA1_2_PERIPHERAL_MAP() bfin_read16(DMA1_2_PERIPHERAL_MAP) -#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP, val) -#define pDMA1_3_CONFIG ((uint16_t volatile *)DMA1_3_CONFIG) -#define bfin_read_DMA1_3_CONFIG() bfin_read16(DMA1_3_CONFIG) -#define bfin_write_DMA1_3_CONFIG(val) bfin_write16(DMA1_3_CONFIG, val) -#define pDMA1_3_NEXT_DESC_PTR ((void * volatile *)DMA1_3_NEXT_DESC_PTR) -#define bfin_read_DMA1_3_NEXT_DESC_PTR() bfin_readPTR(DMA1_3_NEXT_DESC_PTR) -#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_3_NEXT_DESC_PTR, val) -#define pDMA1_3_START_ADDR ((void * volatile *)DMA1_3_START_ADDR) -#define bfin_read_DMA1_3_START_ADDR() bfin_readPTR(DMA1_3_START_ADDR) -#define bfin_write_DMA1_3_START_ADDR(val) bfin_writePTR(DMA1_3_START_ADDR, val) -#define pDMA1_3_X_COUNT ((uint16_t volatile *)DMA1_3_X_COUNT) -#define bfin_read_DMA1_3_X_COUNT() bfin_read16(DMA1_3_X_COUNT) -#define bfin_write_DMA1_3_X_COUNT(val) bfin_write16(DMA1_3_X_COUNT, val) -#define pDMA1_3_Y_COUNT ((uint16_t volatile *)DMA1_3_Y_COUNT) -#define bfin_read_DMA1_3_Y_COUNT() bfin_read16(DMA1_3_Y_COUNT) -#define bfin_write_DMA1_3_Y_COUNT(val) bfin_write16(DMA1_3_Y_COUNT, val) -#define pDMA1_3_X_MODIFY ((uint16_t volatile *)DMA1_3_X_MODIFY) -#define bfin_read_DMA1_3_X_MODIFY() bfin_read16(DMA1_3_X_MODIFY) -#define bfin_write_DMA1_3_X_MODIFY(val) bfin_write16(DMA1_3_X_MODIFY, val) -#define pDMA1_3_Y_MODIFY ((uint16_t volatile *)DMA1_3_Y_MODIFY) -#define bfin_read_DMA1_3_Y_MODIFY() bfin_read16(DMA1_3_Y_MODIFY) -#define bfin_write_DMA1_3_Y_MODIFY(val) bfin_write16(DMA1_3_Y_MODIFY, val) -#define pDMA1_3_CURR_DESC_PTR ((void * volatile *)DMA1_3_CURR_DESC_PTR) -#define bfin_read_DMA1_3_CURR_DESC_PTR() bfin_readPTR(DMA1_3_CURR_DESC_PTR) -#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_writePTR(DMA1_3_CURR_DESC_PTR, val) -#define pDMA1_3_CURR_ADDR ((void * volatile *)DMA1_3_CURR_ADDR) -#define bfin_read_DMA1_3_CURR_ADDR() bfin_readPTR(DMA1_3_CURR_ADDR) -#define bfin_write_DMA1_3_CURR_ADDR(val) bfin_writePTR(DMA1_3_CURR_ADDR, val) -#define pDMA1_3_CURR_X_COUNT ((uint16_t volatile *)DMA1_3_CURR_X_COUNT) -#define bfin_read_DMA1_3_CURR_X_COUNT() bfin_read16(DMA1_3_CURR_X_COUNT) -#define bfin_write_DMA1_3_CURR_X_COUNT(val) bfin_write16(DMA1_3_CURR_X_COUNT, val) -#define pDMA1_3_CURR_Y_COUNT ((uint16_t volatile *)DMA1_3_CURR_Y_COUNT) -#define bfin_read_DMA1_3_CURR_Y_COUNT() bfin_read16(DMA1_3_CURR_Y_COUNT) -#define bfin_write_DMA1_3_CURR_Y_COUNT(val) bfin_write16(DMA1_3_CURR_Y_COUNT, val) -#define pDMA1_3_IRQ_STATUS ((uint16_t volatile *)DMA1_3_IRQ_STATUS) -#define bfin_read_DMA1_3_IRQ_STATUS() bfin_read16(DMA1_3_IRQ_STATUS) -#define bfin_write_DMA1_3_IRQ_STATUS(val) bfin_write16(DMA1_3_IRQ_STATUS, val) -#define pDMA1_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_3_PERIPHERAL_MAP) -#define bfin_read_DMA1_3_PERIPHERAL_MAP() bfin_read16(DMA1_3_PERIPHERAL_MAP) -#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP, val) -#define pDMA1_4_CONFIG ((uint16_t volatile *)DMA1_4_CONFIG) -#define bfin_read_DMA1_4_CONFIG() bfin_read16(DMA1_4_CONFIG) -#define bfin_write_DMA1_4_CONFIG(val) bfin_write16(DMA1_4_CONFIG, val) -#define pDMA1_4_NEXT_DESC_PTR ((void * volatile *)DMA1_4_NEXT_DESC_PTR) -#define bfin_read_DMA1_4_NEXT_DESC_PTR() bfin_readPTR(DMA1_4_NEXT_DESC_PTR) -#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_4_NEXT_DESC_PTR, val) -#define pDMA1_4_START_ADDR ((void * volatile *)DMA1_4_START_ADDR) -#define bfin_read_DMA1_4_START_ADDR() bfin_readPTR(DMA1_4_START_ADDR) -#define bfin_write_DMA1_4_START_ADDR(val) bfin_writePTR(DMA1_4_START_ADDR, val) -#define pDMA1_4_X_COUNT ((uint16_t volatile *)DMA1_4_X_COUNT) -#define bfin_read_DMA1_4_X_COUNT() bfin_read16(DMA1_4_X_COUNT) -#define bfin_write_DMA1_4_X_COUNT(val) bfin_write16(DMA1_4_X_COUNT, val) -#define pDMA1_4_Y_COUNT ((uint16_t volatile *)DMA1_4_Y_COUNT) -#define bfin_read_DMA1_4_Y_COUNT() bfin_read16(DMA1_4_Y_COUNT) -#define bfin_write_DMA1_4_Y_COUNT(val) bfin_write16(DMA1_4_Y_COUNT, val) -#define pDMA1_4_X_MODIFY ((uint16_t volatile *)DMA1_4_X_MODIFY) -#define bfin_read_DMA1_4_X_MODIFY() bfin_read16(DMA1_4_X_MODIFY) -#define bfin_write_DMA1_4_X_MODIFY(val) bfin_write16(DMA1_4_X_MODIFY, val) -#define pDMA1_4_Y_MODIFY ((uint16_t volatile *)DMA1_4_Y_MODIFY) -#define bfin_read_DMA1_4_Y_MODIFY() bfin_read16(DMA1_4_Y_MODIFY) -#define bfin_write_DMA1_4_Y_MODIFY(val) bfin_write16(DMA1_4_Y_MODIFY, val) -#define pDMA1_4_CURR_DESC_PTR ((void * volatile *)DMA1_4_CURR_DESC_PTR) -#define bfin_read_DMA1_4_CURR_DESC_PTR() bfin_readPTR(DMA1_4_CURR_DESC_PTR) -#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_writePTR(DMA1_4_CURR_DESC_PTR, val) -#define pDMA1_4_CURR_ADDR ((void * volatile *)DMA1_4_CURR_ADDR) -#define bfin_read_DMA1_4_CURR_ADDR() bfin_readPTR(DMA1_4_CURR_ADDR) -#define bfin_write_DMA1_4_CURR_ADDR(val) bfin_writePTR(DMA1_4_CURR_ADDR, val) -#define pDMA1_4_CURR_X_COUNT ((uint16_t volatile *)DMA1_4_CURR_X_COUNT) -#define bfin_read_DMA1_4_CURR_X_COUNT() bfin_read16(DMA1_4_CURR_X_COUNT) -#define bfin_write_DMA1_4_CURR_X_COUNT(val) bfin_write16(DMA1_4_CURR_X_COUNT, val) -#define pDMA1_4_CURR_Y_COUNT ((uint16_t volatile *)DMA1_4_CURR_Y_COUNT) -#define bfin_read_DMA1_4_CURR_Y_COUNT() bfin_read16(DMA1_4_CURR_Y_COUNT) -#define bfin_write_DMA1_4_CURR_Y_COUNT(val) bfin_write16(DMA1_4_CURR_Y_COUNT, val) -#define pDMA1_4_IRQ_STATUS ((uint16_t volatile *)DMA1_4_IRQ_STATUS) -#define bfin_read_DMA1_4_IRQ_STATUS() bfin_read16(DMA1_4_IRQ_STATUS) -#define bfin_write_DMA1_4_IRQ_STATUS(val) bfin_write16(DMA1_4_IRQ_STATUS, val) -#define pDMA1_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_4_PERIPHERAL_MAP) -#define bfin_read_DMA1_4_PERIPHERAL_MAP() bfin_read16(DMA1_4_PERIPHERAL_MAP) -#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP, val) -#define pDMA1_5_CONFIG ((uint16_t volatile *)DMA1_5_CONFIG) -#define bfin_read_DMA1_5_CONFIG() bfin_read16(DMA1_5_CONFIG) -#define bfin_write_DMA1_5_CONFIG(val) bfin_write16(DMA1_5_CONFIG, val) -#define pDMA1_5_NEXT_DESC_PTR ((void * volatile *)DMA1_5_NEXT_DESC_PTR) -#define bfin_read_DMA1_5_NEXT_DESC_PTR() bfin_readPTR(DMA1_5_NEXT_DESC_PTR) -#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_5_NEXT_DESC_PTR, val) -#define pDMA1_5_START_ADDR ((void * volatile *)DMA1_5_START_ADDR) -#define bfin_read_DMA1_5_START_ADDR() bfin_readPTR(DMA1_5_START_ADDR) -#define bfin_write_DMA1_5_START_ADDR(val) bfin_writePTR(DMA1_5_START_ADDR, val) -#define pDMA1_5_X_COUNT ((uint16_t volatile *)DMA1_5_X_COUNT) -#define bfin_read_DMA1_5_X_COUNT() bfin_read16(DMA1_5_X_COUNT) -#define bfin_write_DMA1_5_X_COUNT(val) bfin_write16(DMA1_5_X_COUNT, val) -#define pDMA1_5_Y_COUNT ((uint16_t volatile *)DMA1_5_Y_COUNT) -#define bfin_read_DMA1_5_Y_COUNT() bfin_read16(DMA1_5_Y_COUNT) -#define bfin_write_DMA1_5_Y_COUNT(val) bfin_write16(DMA1_5_Y_COUNT, val) -#define pDMA1_5_X_MODIFY ((uint16_t volatile *)DMA1_5_X_MODIFY) -#define bfin_read_DMA1_5_X_MODIFY() bfin_read16(DMA1_5_X_MODIFY) -#define bfin_write_DMA1_5_X_MODIFY(val) bfin_write16(DMA1_5_X_MODIFY, val) -#define pDMA1_5_Y_MODIFY ((uint16_t volatile *)DMA1_5_Y_MODIFY) -#define bfin_read_DMA1_5_Y_MODIFY() bfin_read16(DMA1_5_Y_MODIFY) -#define bfin_write_DMA1_5_Y_MODIFY(val) bfin_write16(DMA1_5_Y_MODIFY, val) -#define pDMA1_5_CURR_DESC_PTR ((void * volatile *)DMA1_5_CURR_DESC_PTR) -#define bfin_read_DMA1_5_CURR_DESC_PTR() bfin_readPTR(DMA1_5_CURR_DESC_PTR) -#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_writePTR(DMA1_5_CURR_DESC_PTR, val) -#define pDMA1_5_CURR_ADDR ((void * volatile *)DMA1_5_CURR_ADDR) -#define bfin_read_DMA1_5_CURR_ADDR() bfin_readPTR(DMA1_5_CURR_ADDR) -#define bfin_write_DMA1_5_CURR_ADDR(val) bfin_writePTR(DMA1_5_CURR_ADDR, val) -#define pDMA1_5_CURR_X_COUNT ((uint16_t volatile *)DMA1_5_CURR_X_COUNT) -#define bfin_read_DMA1_5_CURR_X_COUNT() bfin_read16(DMA1_5_CURR_X_COUNT) -#define bfin_write_DMA1_5_CURR_X_COUNT(val) bfin_write16(DMA1_5_CURR_X_COUNT, val) -#define pDMA1_5_CURR_Y_COUNT ((uint16_t volatile *)DMA1_5_CURR_Y_COUNT) -#define bfin_read_DMA1_5_CURR_Y_COUNT() bfin_read16(DMA1_5_CURR_Y_COUNT) -#define bfin_write_DMA1_5_CURR_Y_COUNT(val) bfin_write16(DMA1_5_CURR_Y_COUNT, val) -#define pDMA1_5_IRQ_STATUS ((uint16_t volatile *)DMA1_5_IRQ_STATUS) -#define bfin_read_DMA1_5_IRQ_STATUS() bfin_read16(DMA1_5_IRQ_STATUS) -#define bfin_write_DMA1_5_IRQ_STATUS(val) bfin_write16(DMA1_5_IRQ_STATUS, val) -#define pDMA1_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_5_PERIPHERAL_MAP) -#define bfin_read_DMA1_5_PERIPHERAL_MAP() bfin_read16(DMA1_5_PERIPHERAL_MAP) -#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP, val) -#define pDMA1_6_CONFIG ((uint16_t volatile *)DMA1_6_CONFIG) -#define bfin_read_DMA1_6_CONFIG() bfin_read16(DMA1_6_CONFIG) -#define bfin_write_DMA1_6_CONFIG(val) bfin_write16(DMA1_6_CONFIG, val) -#define pDMA1_6_NEXT_DESC_PTR ((void * volatile *)DMA1_6_NEXT_DESC_PTR) -#define bfin_read_DMA1_6_NEXT_DESC_PTR() bfin_readPTR(DMA1_6_NEXT_DESC_PTR) -#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_6_NEXT_DESC_PTR, val) -#define pDMA1_6_START_ADDR ((void * volatile *)DMA1_6_START_ADDR) -#define bfin_read_DMA1_6_START_ADDR() bfin_readPTR(DMA1_6_START_ADDR) -#define bfin_write_DMA1_6_START_ADDR(val) bfin_writePTR(DMA1_6_START_ADDR, val) -#define pDMA1_6_X_COUNT ((uint16_t volatile *)DMA1_6_X_COUNT) -#define bfin_read_DMA1_6_X_COUNT() bfin_read16(DMA1_6_X_COUNT) -#define bfin_write_DMA1_6_X_COUNT(val) bfin_write16(DMA1_6_X_COUNT, val) -#define pDMA1_6_Y_COUNT ((uint16_t volatile *)DMA1_6_Y_COUNT) -#define bfin_read_DMA1_6_Y_COUNT() bfin_read16(DMA1_6_Y_COUNT) -#define bfin_write_DMA1_6_Y_COUNT(val) bfin_write16(DMA1_6_Y_COUNT, val) -#define pDMA1_6_X_MODIFY ((uint16_t volatile *)DMA1_6_X_MODIFY) -#define bfin_read_DMA1_6_X_MODIFY() bfin_read16(DMA1_6_X_MODIFY) -#define bfin_write_DMA1_6_X_MODIFY(val) bfin_write16(DMA1_6_X_MODIFY, val) -#define pDMA1_6_Y_MODIFY ((uint16_t volatile *)DMA1_6_Y_MODIFY) -#define bfin_read_DMA1_6_Y_MODIFY() bfin_read16(DMA1_6_Y_MODIFY) -#define bfin_write_DMA1_6_Y_MODIFY(val) bfin_write16(DMA1_6_Y_MODIFY, val) -#define pDMA1_6_CURR_DESC_PTR ((void * volatile *)DMA1_6_CURR_DESC_PTR) -#define bfin_read_DMA1_6_CURR_DESC_PTR() bfin_readPTR(DMA1_6_CURR_DESC_PTR) -#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_writePTR(DMA1_6_CURR_DESC_PTR, val) -#define pDMA1_6_CURR_ADDR ((void * volatile *)DMA1_6_CURR_ADDR) -#define bfin_read_DMA1_6_CURR_ADDR() bfin_readPTR(DMA1_6_CURR_ADDR) -#define bfin_write_DMA1_6_CURR_ADDR(val) bfin_writePTR(DMA1_6_CURR_ADDR, val) -#define pDMA1_6_CURR_X_COUNT ((uint16_t volatile *)DMA1_6_CURR_X_COUNT) -#define bfin_read_DMA1_6_CURR_X_COUNT() bfin_read16(DMA1_6_CURR_X_COUNT) -#define bfin_write_DMA1_6_CURR_X_COUNT(val) bfin_write16(DMA1_6_CURR_X_COUNT, val) -#define pDMA1_6_CURR_Y_COUNT ((uint16_t volatile *)DMA1_6_CURR_Y_COUNT) -#define bfin_read_DMA1_6_CURR_Y_COUNT() bfin_read16(DMA1_6_CURR_Y_COUNT) -#define bfin_write_DMA1_6_CURR_Y_COUNT(val) bfin_write16(DMA1_6_CURR_Y_COUNT, val) -#define pDMA1_6_IRQ_STATUS ((uint16_t volatile *)DMA1_6_IRQ_STATUS) -#define bfin_read_DMA1_6_IRQ_STATUS() bfin_read16(DMA1_6_IRQ_STATUS) -#define bfin_write_DMA1_6_IRQ_STATUS(val) bfin_write16(DMA1_6_IRQ_STATUS, val) -#define pDMA1_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_6_PERIPHERAL_MAP) -#define bfin_read_DMA1_6_PERIPHERAL_MAP() bfin_read16(DMA1_6_PERIPHERAL_MAP) -#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP, val) -#define pDMA1_7_CONFIG ((uint16_t volatile *)DMA1_7_CONFIG) -#define bfin_read_DMA1_7_CONFIG() bfin_read16(DMA1_7_CONFIG) -#define bfin_write_DMA1_7_CONFIG(val) bfin_write16(DMA1_7_CONFIG, val) -#define pDMA1_7_NEXT_DESC_PTR ((void * volatile *)DMA1_7_NEXT_DESC_PTR) -#define bfin_read_DMA1_7_NEXT_DESC_PTR() bfin_readPTR(DMA1_7_NEXT_DESC_PTR) -#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_7_NEXT_DESC_PTR, val) -#define pDMA1_7_START_ADDR ((void * volatile *)DMA1_7_START_ADDR) -#define bfin_read_DMA1_7_START_ADDR() bfin_readPTR(DMA1_7_START_ADDR) -#define bfin_write_DMA1_7_START_ADDR(val) bfin_writePTR(DMA1_7_START_ADDR, val) -#define pDMA1_7_X_COUNT ((uint16_t volatile *)DMA1_7_X_COUNT) -#define bfin_read_DMA1_7_X_COUNT() bfin_read16(DMA1_7_X_COUNT) -#define bfin_write_DMA1_7_X_COUNT(val) bfin_write16(DMA1_7_X_COUNT, val) -#define pDMA1_7_Y_COUNT ((uint16_t volatile *)DMA1_7_Y_COUNT) -#define bfin_read_DMA1_7_Y_COUNT() bfin_read16(DMA1_7_Y_COUNT) -#define bfin_write_DMA1_7_Y_COUNT(val) bfin_write16(DMA1_7_Y_COUNT, val) -#define pDMA1_7_X_MODIFY ((uint16_t volatile *)DMA1_7_X_MODIFY) -#define bfin_read_DMA1_7_X_MODIFY() bfin_read16(DMA1_7_X_MODIFY) -#define bfin_write_DMA1_7_X_MODIFY(val) bfin_write16(DMA1_7_X_MODIFY, val) -#define pDMA1_7_Y_MODIFY ((uint16_t volatile *)DMA1_7_Y_MODIFY) -#define bfin_read_DMA1_7_Y_MODIFY() bfin_read16(DMA1_7_Y_MODIFY) -#define bfin_write_DMA1_7_Y_MODIFY(val) bfin_write16(DMA1_7_Y_MODIFY, val) -#define pDMA1_7_CURR_DESC_PTR ((void * volatile *)DMA1_7_CURR_DESC_PTR) -#define bfin_read_DMA1_7_CURR_DESC_PTR() bfin_readPTR(DMA1_7_CURR_DESC_PTR) -#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_writePTR(DMA1_7_CURR_DESC_PTR, val) -#define pDMA1_7_CURR_ADDR ((void * volatile *)DMA1_7_CURR_ADDR) -#define bfin_read_DMA1_7_CURR_ADDR() bfin_readPTR(DMA1_7_CURR_ADDR) -#define bfin_write_DMA1_7_CURR_ADDR(val) bfin_writePTR(DMA1_7_CURR_ADDR, val) -#define pDMA1_7_CURR_X_COUNT ((uint16_t volatile *)DMA1_7_CURR_X_COUNT) -#define bfin_read_DMA1_7_CURR_X_COUNT() bfin_read16(DMA1_7_CURR_X_COUNT) -#define bfin_write_DMA1_7_CURR_X_COUNT(val) bfin_write16(DMA1_7_CURR_X_COUNT, val) -#define pDMA1_7_CURR_Y_COUNT ((uint16_t volatile *)DMA1_7_CURR_Y_COUNT) -#define bfin_read_DMA1_7_CURR_Y_COUNT() bfin_read16(DMA1_7_CURR_Y_COUNT) -#define bfin_write_DMA1_7_CURR_Y_COUNT(val) bfin_write16(DMA1_7_CURR_Y_COUNT, val) -#define pDMA1_7_IRQ_STATUS ((uint16_t volatile *)DMA1_7_IRQ_STATUS) -#define bfin_read_DMA1_7_IRQ_STATUS() bfin_read16(DMA1_7_IRQ_STATUS) -#define bfin_write_DMA1_7_IRQ_STATUS(val) bfin_write16(DMA1_7_IRQ_STATUS, val) -#define pDMA1_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_7_PERIPHERAL_MAP) -#define bfin_read_DMA1_7_PERIPHERAL_MAP() bfin_read16(DMA1_7_PERIPHERAL_MAP) -#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP, val) -#define pDMA1_8_CONFIG ((uint16_t volatile *)DMA1_8_CONFIG) -#define bfin_read_DMA1_8_CONFIG() bfin_read16(DMA1_8_CONFIG) -#define bfin_write_DMA1_8_CONFIG(val) bfin_write16(DMA1_8_CONFIG, val) -#define pDMA1_8_NEXT_DESC_PTR ((void * volatile *)DMA1_8_NEXT_DESC_PTR) -#define bfin_read_DMA1_8_NEXT_DESC_PTR() bfin_readPTR(DMA1_8_NEXT_DESC_PTR) -#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_8_NEXT_DESC_PTR, val) -#define pDMA1_8_START_ADDR ((void * volatile *)DMA1_8_START_ADDR) -#define bfin_read_DMA1_8_START_ADDR() bfin_readPTR(DMA1_8_START_ADDR) -#define bfin_write_DMA1_8_START_ADDR(val) bfin_writePTR(DMA1_8_START_ADDR, val) -#define pDMA1_8_X_COUNT ((uint16_t volatile *)DMA1_8_X_COUNT) -#define bfin_read_DMA1_8_X_COUNT() bfin_read16(DMA1_8_X_COUNT) -#define bfin_write_DMA1_8_X_COUNT(val) bfin_write16(DMA1_8_X_COUNT, val) -#define pDMA1_8_Y_COUNT ((uint16_t volatile *)DMA1_8_Y_COUNT) -#define bfin_read_DMA1_8_Y_COUNT() bfin_read16(DMA1_8_Y_COUNT) -#define bfin_write_DMA1_8_Y_COUNT(val) bfin_write16(DMA1_8_Y_COUNT, val) -#define pDMA1_8_X_MODIFY ((uint16_t volatile *)DMA1_8_X_MODIFY) -#define bfin_read_DMA1_8_X_MODIFY() bfin_read16(DMA1_8_X_MODIFY) -#define bfin_write_DMA1_8_X_MODIFY(val) bfin_write16(DMA1_8_X_MODIFY, val) -#define pDMA1_8_Y_MODIFY ((uint16_t volatile *)DMA1_8_Y_MODIFY) -#define bfin_read_DMA1_8_Y_MODIFY() bfin_read16(DMA1_8_Y_MODIFY) -#define bfin_write_DMA1_8_Y_MODIFY(val) bfin_write16(DMA1_8_Y_MODIFY, val) -#define pDMA1_8_CURR_DESC_PTR ((void * volatile *)DMA1_8_CURR_DESC_PTR) -#define bfin_read_DMA1_8_CURR_DESC_PTR() bfin_readPTR(DMA1_8_CURR_DESC_PTR) -#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_writePTR(DMA1_8_CURR_DESC_PTR, val) -#define pDMA1_8_CURR_ADDR ((void * volatile *)DMA1_8_CURR_ADDR) -#define bfin_read_DMA1_8_CURR_ADDR() bfin_readPTR(DMA1_8_CURR_ADDR) -#define bfin_write_DMA1_8_CURR_ADDR(val) bfin_writePTR(DMA1_8_CURR_ADDR, val) -#define pDMA1_8_CURR_X_COUNT ((uint16_t volatile *)DMA1_8_CURR_X_COUNT) -#define bfin_read_DMA1_8_CURR_X_COUNT() bfin_read16(DMA1_8_CURR_X_COUNT) -#define bfin_write_DMA1_8_CURR_X_COUNT(val) bfin_write16(DMA1_8_CURR_X_COUNT, val) -#define pDMA1_8_CURR_Y_COUNT ((uint16_t volatile *)DMA1_8_CURR_Y_COUNT) -#define bfin_read_DMA1_8_CURR_Y_COUNT() bfin_read16(DMA1_8_CURR_Y_COUNT) -#define bfin_write_DMA1_8_CURR_Y_COUNT(val) bfin_write16(DMA1_8_CURR_Y_COUNT, val) -#define pDMA1_8_IRQ_STATUS ((uint16_t volatile *)DMA1_8_IRQ_STATUS) -#define bfin_read_DMA1_8_IRQ_STATUS() bfin_read16(DMA1_8_IRQ_STATUS) -#define bfin_write_DMA1_8_IRQ_STATUS(val) bfin_write16(DMA1_8_IRQ_STATUS, val) -#define pDMA1_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_8_PERIPHERAL_MAP) -#define bfin_read_DMA1_8_PERIPHERAL_MAP() bfin_read16(DMA1_8_PERIPHERAL_MAP) -#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP, val) -#define pDMA1_9_CONFIG ((uint16_t volatile *)DMA1_9_CONFIG) -#define bfin_read_DMA1_9_CONFIG() bfin_read16(DMA1_9_CONFIG) -#define bfin_write_DMA1_9_CONFIG(val) bfin_write16(DMA1_9_CONFIG, val) -#define pDMA1_9_NEXT_DESC_PTR ((void * volatile *)DMA1_9_NEXT_DESC_PTR) -#define bfin_read_DMA1_9_NEXT_DESC_PTR() bfin_readPTR(DMA1_9_NEXT_DESC_PTR) -#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_9_NEXT_DESC_PTR, val) -#define pDMA1_9_START_ADDR ((void * volatile *)DMA1_9_START_ADDR) -#define bfin_read_DMA1_9_START_ADDR() bfin_readPTR(DMA1_9_START_ADDR) -#define bfin_write_DMA1_9_START_ADDR(val) bfin_writePTR(DMA1_9_START_ADDR, val) -#define pDMA1_9_X_COUNT ((uint16_t volatile *)DMA1_9_X_COUNT) -#define bfin_read_DMA1_9_X_COUNT() bfin_read16(DMA1_9_X_COUNT) -#define bfin_write_DMA1_9_X_COUNT(val) bfin_write16(DMA1_9_X_COUNT, val) -#define pDMA1_9_Y_COUNT ((uint16_t volatile *)DMA1_9_Y_COUNT) -#define bfin_read_DMA1_9_Y_COUNT() bfin_read16(DMA1_9_Y_COUNT) -#define bfin_write_DMA1_9_Y_COUNT(val) bfin_write16(DMA1_9_Y_COUNT, val) -#define pDMA1_9_X_MODIFY ((uint16_t volatile *)DMA1_9_X_MODIFY) -#define bfin_read_DMA1_9_X_MODIFY() bfin_read16(DMA1_9_X_MODIFY) -#define bfin_write_DMA1_9_X_MODIFY(val) bfin_write16(DMA1_9_X_MODIFY, val) -#define pDMA1_9_Y_MODIFY ((uint16_t volatile *)DMA1_9_Y_MODIFY) -#define bfin_read_DMA1_9_Y_MODIFY() bfin_read16(DMA1_9_Y_MODIFY) -#define bfin_write_DMA1_9_Y_MODIFY(val) bfin_write16(DMA1_9_Y_MODIFY, val) -#define pDMA1_9_CURR_DESC_PTR ((void * volatile *)DMA1_9_CURR_DESC_PTR) -#define bfin_read_DMA1_9_CURR_DESC_PTR() bfin_readPTR(DMA1_9_CURR_DESC_PTR) -#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_writePTR(DMA1_9_CURR_DESC_PTR, val) -#define pDMA1_9_CURR_ADDR ((void * volatile *)DMA1_9_CURR_ADDR) -#define bfin_read_DMA1_9_CURR_ADDR() bfin_readPTR(DMA1_9_CURR_ADDR) -#define bfin_write_DMA1_9_CURR_ADDR(val) bfin_writePTR(DMA1_9_CURR_ADDR, val) -#define pDMA1_9_CURR_X_COUNT ((uint16_t volatile *)DMA1_9_CURR_X_COUNT) -#define bfin_read_DMA1_9_CURR_X_COUNT() bfin_read16(DMA1_9_CURR_X_COUNT) -#define bfin_write_DMA1_9_CURR_X_COUNT(val) bfin_write16(DMA1_9_CURR_X_COUNT, val) -#define pDMA1_9_CURR_Y_COUNT ((uint16_t volatile *)DMA1_9_CURR_Y_COUNT) -#define bfin_read_DMA1_9_CURR_Y_COUNT() bfin_read16(DMA1_9_CURR_Y_COUNT) -#define bfin_write_DMA1_9_CURR_Y_COUNT(val) bfin_write16(DMA1_9_CURR_Y_COUNT, val) -#define pDMA1_9_IRQ_STATUS ((uint16_t volatile *)DMA1_9_IRQ_STATUS) -#define bfin_read_DMA1_9_IRQ_STATUS() bfin_read16(DMA1_9_IRQ_STATUS) -#define bfin_write_DMA1_9_IRQ_STATUS(val) bfin_write16(DMA1_9_IRQ_STATUS, val) -#define pDMA1_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_9_PERIPHERAL_MAP) -#define bfin_read_DMA1_9_PERIPHERAL_MAP() bfin_read16(DMA1_9_PERIPHERAL_MAP) -#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP, val) -#define pDMA1_10_CONFIG ((uint16_t volatile *)DMA1_10_CONFIG) -#define bfin_read_DMA1_10_CONFIG() bfin_read16(DMA1_10_CONFIG) -#define bfin_write_DMA1_10_CONFIG(val) bfin_write16(DMA1_10_CONFIG, val) -#define pDMA1_10_NEXT_DESC_PTR ((void * volatile *)DMA1_10_NEXT_DESC_PTR) -#define bfin_read_DMA1_10_NEXT_DESC_PTR() bfin_readPTR(DMA1_10_NEXT_DESC_PTR) -#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_10_NEXT_DESC_PTR, val) -#define pDMA1_10_START_ADDR ((void * volatile *)DMA1_10_START_ADDR) -#define bfin_read_DMA1_10_START_ADDR() bfin_readPTR(DMA1_10_START_ADDR) -#define bfin_write_DMA1_10_START_ADDR(val) bfin_writePTR(DMA1_10_START_ADDR, val) -#define pDMA1_10_X_COUNT ((uint16_t volatile *)DMA1_10_X_COUNT) -#define bfin_read_DMA1_10_X_COUNT() bfin_read16(DMA1_10_X_COUNT) -#define bfin_write_DMA1_10_X_COUNT(val) bfin_write16(DMA1_10_X_COUNT, val) -#define pDMA1_10_Y_COUNT ((uint16_t volatile *)DMA1_10_Y_COUNT) -#define bfin_read_DMA1_10_Y_COUNT() bfin_read16(DMA1_10_Y_COUNT) -#define bfin_write_DMA1_10_Y_COUNT(val) bfin_write16(DMA1_10_Y_COUNT, val) -#define pDMA1_10_X_MODIFY ((uint16_t volatile *)DMA1_10_X_MODIFY) -#define bfin_read_DMA1_10_X_MODIFY() bfin_read16(DMA1_10_X_MODIFY) -#define bfin_write_DMA1_10_X_MODIFY(val) bfin_write16(DMA1_10_X_MODIFY, val) -#define pDMA1_10_Y_MODIFY ((uint16_t volatile *)DMA1_10_Y_MODIFY) -#define bfin_read_DMA1_10_Y_MODIFY() bfin_read16(DMA1_10_Y_MODIFY) -#define bfin_write_DMA1_10_Y_MODIFY(val) bfin_write16(DMA1_10_Y_MODIFY, val) -#define pDMA1_10_CURR_DESC_PTR ((void * volatile *)DMA1_10_CURR_DESC_PTR) -#define bfin_read_DMA1_10_CURR_DESC_PTR() bfin_readPTR(DMA1_10_CURR_DESC_PTR) -#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_writePTR(DMA1_10_CURR_DESC_PTR, val) -#define pDMA1_10_CURR_ADDR ((void * volatile *)DMA1_10_CURR_ADDR) -#define bfin_read_DMA1_10_CURR_ADDR() bfin_readPTR(DMA1_10_CURR_ADDR) -#define bfin_write_DMA1_10_CURR_ADDR(val) bfin_writePTR(DMA1_10_CURR_ADDR, val) -#define pDMA1_10_CURR_X_COUNT ((uint16_t volatile *)DMA1_10_CURR_X_COUNT) -#define bfin_read_DMA1_10_CURR_X_COUNT() bfin_read16(DMA1_10_CURR_X_COUNT) -#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT, val) -#define pDMA1_10_CURR_Y_COUNT ((uint16_t volatile *)DMA1_10_CURR_Y_COUNT) -#define bfin_read_DMA1_10_CURR_Y_COUNT() bfin_read16(DMA1_10_CURR_Y_COUNT) -#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT, val) -#define pDMA1_10_IRQ_STATUS ((uint16_t volatile *)DMA1_10_IRQ_STATUS) -#define bfin_read_DMA1_10_IRQ_STATUS() bfin_read16(DMA1_10_IRQ_STATUS) -#define bfin_write_DMA1_10_IRQ_STATUS(val) bfin_write16(DMA1_10_IRQ_STATUS, val) -#define pDMA1_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_10_PERIPHERAL_MAP) -#define bfin_read_DMA1_10_PERIPHERAL_MAP() bfin_read16(DMA1_10_PERIPHERAL_MAP) -#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP, val) -#define pDMA1_11_CONFIG ((uint16_t volatile *)DMA1_11_CONFIG) -#define bfin_read_DMA1_11_CONFIG() bfin_read16(DMA1_11_CONFIG) -#define bfin_write_DMA1_11_CONFIG(val) bfin_write16(DMA1_11_CONFIG, val) -#define pDMA1_11_NEXT_DESC_PTR ((void * volatile *)DMA1_11_NEXT_DESC_PTR) -#define bfin_read_DMA1_11_NEXT_DESC_PTR() bfin_readPTR(DMA1_11_NEXT_DESC_PTR) -#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_11_NEXT_DESC_PTR, val) -#define pDMA1_11_START_ADDR ((void * volatile *)DMA1_11_START_ADDR) -#define bfin_read_DMA1_11_START_ADDR() bfin_readPTR(DMA1_11_START_ADDR) -#define bfin_write_DMA1_11_START_ADDR(val) bfin_writePTR(DMA1_11_START_ADDR, val) -#define pDMA1_11_X_COUNT ((uint16_t volatile *)DMA1_11_X_COUNT) -#define bfin_read_DMA1_11_X_COUNT() bfin_read16(DMA1_11_X_COUNT) -#define bfin_write_DMA1_11_X_COUNT(val) bfin_write16(DMA1_11_X_COUNT, val) -#define pDMA1_11_Y_COUNT ((uint16_t volatile *)DMA1_11_Y_COUNT) -#define bfin_read_DMA1_11_Y_COUNT() bfin_read16(DMA1_11_Y_COUNT) -#define bfin_write_DMA1_11_Y_COUNT(val) bfin_write16(DMA1_11_Y_COUNT, val) -#define pDMA1_11_X_MODIFY ((uint16_t volatile *)DMA1_11_X_MODIFY) -#define bfin_read_DMA1_11_X_MODIFY() bfin_read16(DMA1_11_X_MODIFY) -#define bfin_write_DMA1_11_X_MODIFY(val) bfin_write16(DMA1_11_X_MODIFY, val) -#define pDMA1_11_Y_MODIFY ((uint16_t volatile *)DMA1_11_Y_MODIFY) -#define bfin_read_DMA1_11_Y_MODIFY() bfin_read16(DMA1_11_Y_MODIFY) -#define bfin_write_DMA1_11_Y_MODIFY(val) bfin_write16(DMA1_11_Y_MODIFY, val) -#define pDMA1_11_CURR_DESC_PTR ((void * volatile *)DMA1_11_CURR_DESC_PTR) -#define bfin_read_DMA1_11_CURR_DESC_PTR() bfin_readPTR(DMA1_11_CURR_DESC_PTR) -#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_writePTR(DMA1_11_CURR_DESC_PTR, val) -#define pDMA1_11_CURR_ADDR ((void * volatile *)DMA1_11_CURR_ADDR) -#define bfin_read_DMA1_11_CURR_ADDR() bfin_readPTR(DMA1_11_CURR_ADDR) -#define bfin_write_DMA1_11_CURR_ADDR(val) bfin_writePTR(DMA1_11_CURR_ADDR, val) -#define pDMA1_11_CURR_X_COUNT ((uint16_t volatile *)DMA1_11_CURR_X_COUNT) -#define bfin_read_DMA1_11_CURR_X_COUNT() bfin_read16(DMA1_11_CURR_X_COUNT) -#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT, val) -#define pDMA1_11_CURR_Y_COUNT ((uint16_t volatile *)DMA1_11_CURR_Y_COUNT) -#define bfin_read_DMA1_11_CURR_Y_COUNT() bfin_read16(DMA1_11_CURR_Y_COUNT) -#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT, val) -#define pDMA1_11_IRQ_STATUS ((uint16_t volatile *)DMA1_11_IRQ_STATUS) -#define bfin_read_DMA1_11_IRQ_STATUS() bfin_read16(DMA1_11_IRQ_STATUS) -#define bfin_write_DMA1_11_IRQ_STATUS(val) bfin_write16(DMA1_11_IRQ_STATUS, val) -#define pDMA1_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_11_PERIPHERAL_MAP) -#define bfin_read_DMA1_11_PERIPHERAL_MAP() bfin_read16(DMA1_11_PERIPHERAL_MAP) -#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP, val) -#define pDMA2_TC_PER ((uint16_t volatile *)DMA2_TC_PER) -#define bfin_read_DMA2_TC_PER() bfin_read16(DMA2_TC_PER) -#define bfin_write_DMA2_TC_PER(val) bfin_write16(DMA2_TC_PER, val) -#define pDMA2_TC_CNT ((uint16_t volatile *)DMA2_TC_CNT) /* Traffic Control Current Counts */ -#define bfin_read_DMA2_TC_CNT() bfin_read16(DMA2_TC_CNT) -#define bfin_write_DMA2_TC_CNT(val) bfin_write16(DMA2_TC_CNT, val) -#define pDMA2_0_CONFIG ((uint16_t volatile *)DMA2_0_CONFIG) -#define bfin_read_DMA2_0_CONFIG() bfin_read16(DMA2_0_CONFIG) -#define bfin_write_DMA2_0_CONFIG(val) bfin_write16(DMA2_0_CONFIG, val) -#define pDMA2_0_NEXT_DESC_PTR ((void * volatile *)DMA2_0_NEXT_DESC_PTR) -#define bfin_read_DMA2_0_NEXT_DESC_PTR() bfin_readPTR(DMA2_0_NEXT_DESC_PTR) -#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_0_NEXT_DESC_PTR, val) -#define pDMA2_0_START_ADDR ((void * volatile *)DMA2_0_START_ADDR) -#define bfin_read_DMA2_0_START_ADDR() bfin_readPTR(DMA2_0_START_ADDR) -#define bfin_write_DMA2_0_START_ADDR(val) bfin_writePTR(DMA2_0_START_ADDR, val) -#define pDMA2_0_X_COUNT ((uint16_t volatile *)DMA2_0_X_COUNT) -#define bfin_read_DMA2_0_X_COUNT() bfin_read16(DMA2_0_X_COUNT) -#define bfin_write_DMA2_0_X_COUNT(val) bfin_write16(DMA2_0_X_COUNT, val) -#define pDMA2_0_Y_COUNT ((uint16_t volatile *)DMA2_0_Y_COUNT) -#define bfin_read_DMA2_0_Y_COUNT() bfin_read16(DMA2_0_Y_COUNT) -#define bfin_write_DMA2_0_Y_COUNT(val) bfin_write16(DMA2_0_Y_COUNT, val) -#define pDMA2_0_X_MODIFY ((uint16_t volatile *)DMA2_0_X_MODIFY) -#define bfin_read_DMA2_0_X_MODIFY() bfin_read16(DMA2_0_X_MODIFY) -#define bfin_write_DMA2_0_X_MODIFY(val) bfin_write16(DMA2_0_X_MODIFY, val) -#define pDMA2_0_Y_MODIFY ((uint16_t volatile *)DMA2_0_Y_MODIFY) -#define bfin_read_DMA2_0_Y_MODIFY() bfin_read16(DMA2_0_Y_MODIFY) -#define bfin_write_DMA2_0_Y_MODIFY(val) bfin_write16(DMA2_0_Y_MODIFY, val) -#define pDMA2_0_CURR_DESC_PTR ((void * volatile *)DMA2_0_CURR_DESC_PTR) -#define bfin_read_DMA2_0_CURR_DESC_PTR() bfin_readPTR(DMA2_0_CURR_DESC_PTR) -#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_writePTR(DMA2_0_CURR_DESC_PTR, val) -#define pDMA2_0_CURR_ADDR ((void * volatile *)DMA2_0_CURR_ADDR) -#define bfin_read_DMA2_0_CURR_ADDR() bfin_readPTR(DMA2_0_CURR_ADDR) -#define bfin_write_DMA2_0_CURR_ADDR(val) bfin_writePTR(DMA2_0_CURR_ADDR, val) -#define pDMA2_0_CURR_X_COUNT ((uint16_t volatile *)DMA2_0_CURR_X_COUNT) -#define bfin_read_DMA2_0_CURR_X_COUNT() bfin_read16(DMA2_0_CURR_X_COUNT) -#define bfin_write_DMA2_0_CURR_X_COUNT(val) bfin_write16(DMA2_0_CURR_X_COUNT, val) -#define pDMA2_0_CURR_Y_COUNT ((uint16_t volatile *)DMA2_0_CURR_Y_COUNT) -#define bfin_read_DMA2_0_CURR_Y_COUNT() bfin_read16(DMA2_0_CURR_Y_COUNT) -#define bfin_write_DMA2_0_CURR_Y_COUNT(val) bfin_write16(DMA2_0_CURR_Y_COUNT, val) -#define pDMA2_0_IRQ_STATUS ((uint16_t volatile *)DMA2_0_IRQ_STATUS) -#define bfin_read_DMA2_0_IRQ_STATUS() bfin_read16(DMA2_0_IRQ_STATUS) -#define bfin_write_DMA2_0_IRQ_STATUS(val) bfin_write16(DMA2_0_IRQ_STATUS, val) -#define pDMA2_0_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_0_PERIPHERAL_MAP) -#define bfin_read_DMA2_0_PERIPHERAL_MAP() bfin_read16(DMA2_0_PERIPHERAL_MAP) -#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP, val) -#define pDMA2_1_CONFIG ((uint16_t volatile *)DMA2_1_CONFIG) -#define bfin_read_DMA2_1_CONFIG() bfin_read16(DMA2_1_CONFIG) -#define bfin_write_DMA2_1_CONFIG(val) bfin_write16(DMA2_1_CONFIG, val) -#define pDMA2_1_NEXT_DESC_PTR ((void * volatile *)DMA2_1_NEXT_DESC_PTR) -#define bfin_read_DMA2_1_NEXT_DESC_PTR() bfin_readPTR(DMA2_1_NEXT_DESC_PTR) -#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_1_NEXT_DESC_PTR, val) -#define pDMA2_1_START_ADDR ((void * volatile *)DMA2_1_START_ADDR) -#define bfin_read_DMA2_1_START_ADDR() bfin_readPTR(DMA2_1_START_ADDR) -#define bfin_write_DMA2_1_START_ADDR(val) bfin_writePTR(DMA2_1_START_ADDR, val) -#define pDMA2_1_X_COUNT ((uint16_t volatile *)DMA2_1_X_COUNT) -#define bfin_read_DMA2_1_X_COUNT() bfin_read16(DMA2_1_X_COUNT) -#define bfin_write_DMA2_1_X_COUNT(val) bfin_write16(DMA2_1_X_COUNT, val) -#define pDMA2_1_Y_COUNT ((uint16_t volatile *)DMA2_1_Y_COUNT) -#define bfin_read_DMA2_1_Y_COUNT() bfin_read16(DMA2_1_Y_COUNT) -#define bfin_write_DMA2_1_Y_COUNT(val) bfin_write16(DMA2_1_Y_COUNT, val) -#define pDMA2_1_X_MODIFY ((uint16_t volatile *)DMA2_1_X_MODIFY) -#define bfin_read_DMA2_1_X_MODIFY() bfin_read16(DMA2_1_X_MODIFY) -#define bfin_write_DMA2_1_X_MODIFY(val) bfin_write16(DMA2_1_X_MODIFY, val) -#define pDMA2_1_Y_MODIFY ((uint16_t volatile *)DMA2_1_Y_MODIFY) -#define bfin_read_DMA2_1_Y_MODIFY() bfin_read16(DMA2_1_Y_MODIFY) -#define bfin_write_DMA2_1_Y_MODIFY(val) bfin_write16(DMA2_1_Y_MODIFY, val) -#define pDMA2_1_CURR_DESC_PTR ((void * volatile *)DMA2_1_CURR_DESC_PTR) -#define bfin_read_DMA2_1_CURR_DESC_PTR() bfin_readPTR(DMA2_1_CURR_DESC_PTR) -#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_writePTR(DMA2_1_CURR_DESC_PTR, val) -#define pDMA2_1_CURR_ADDR ((void * volatile *)DMA2_1_CURR_ADDR) -#define bfin_read_DMA2_1_CURR_ADDR() bfin_readPTR(DMA2_1_CURR_ADDR) -#define bfin_write_DMA2_1_CURR_ADDR(val) bfin_writePTR(DMA2_1_CURR_ADDR, val) -#define pDMA2_1_CURR_X_COUNT ((uint16_t volatile *)DMA2_1_CURR_X_COUNT) -#define bfin_read_DMA2_1_CURR_X_COUNT() bfin_read16(DMA2_1_CURR_X_COUNT) -#define bfin_write_DMA2_1_CURR_X_COUNT(val) bfin_write16(DMA2_1_CURR_X_COUNT, val) -#define pDMA2_1_CURR_Y_COUNT ((uint16_t volatile *)DMA2_1_CURR_Y_COUNT) -#define bfin_read_DMA2_1_CURR_Y_COUNT() bfin_read16(DMA2_1_CURR_Y_COUNT) -#define bfin_write_DMA2_1_CURR_Y_COUNT(val) bfin_write16(DMA2_1_CURR_Y_COUNT, val) -#define pDMA2_1_IRQ_STATUS ((uint16_t volatile *)DMA2_1_IRQ_STATUS) -#define bfin_read_DMA2_1_IRQ_STATUS() bfin_read16(DMA2_1_IRQ_STATUS) -#define bfin_write_DMA2_1_IRQ_STATUS(val) bfin_write16(DMA2_1_IRQ_STATUS, val) -#define pDMA2_1_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_1_PERIPHERAL_MAP) -#define bfin_read_DMA2_1_PERIPHERAL_MAP() bfin_read16(DMA2_1_PERIPHERAL_MAP) -#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP, val) -#define pDMA2_2_CONFIG ((uint16_t volatile *)DMA2_2_CONFIG) -#define bfin_read_DMA2_2_CONFIG() bfin_read16(DMA2_2_CONFIG) -#define bfin_write_DMA2_2_CONFIG(val) bfin_write16(DMA2_2_CONFIG, val) -#define pDMA2_2_NEXT_DESC_PTR ((void * volatile *)DMA2_2_NEXT_DESC_PTR) -#define bfin_read_DMA2_2_NEXT_DESC_PTR() bfin_readPTR(DMA2_2_NEXT_DESC_PTR) -#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_2_NEXT_DESC_PTR, val) -#define pDMA2_2_START_ADDR ((void * volatile *)DMA2_2_START_ADDR) -#define bfin_read_DMA2_2_START_ADDR() bfin_readPTR(DMA2_2_START_ADDR) -#define bfin_write_DMA2_2_START_ADDR(val) bfin_writePTR(DMA2_2_START_ADDR, val) -#define pDMA2_2_X_COUNT ((uint16_t volatile *)DMA2_2_X_COUNT) -#define bfin_read_DMA2_2_X_COUNT() bfin_read16(DMA2_2_X_COUNT) -#define bfin_write_DMA2_2_X_COUNT(val) bfin_write16(DMA2_2_X_COUNT, val) -#define pDMA2_2_Y_COUNT ((uint16_t volatile *)DMA2_2_Y_COUNT) -#define bfin_read_DMA2_2_Y_COUNT() bfin_read16(DMA2_2_Y_COUNT) -#define bfin_write_DMA2_2_Y_COUNT(val) bfin_write16(DMA2_2_Y_COUNT, val) -#define pDMA2_2_X_MODIFY ((uint16_t volatile *)DMA2_2_X_MODIFY) -#define bfin_read_DMA2_2_X_MODIFY() bfin_read16(DMA2_2_X_MODIFY) -#define bfin_write_DMA2_2_X_MODIFY(val) bfin_write16(DMA2_2_X_MODIFY, val) -#define pDMA2_2_Y_MODIFY ((uint16_t volatile *)DMA2_2_Y_MODIFY) -#define bfin_read_DMA2_2_Y_MODIFY() bfin_read16(DMA2_2_Y_MODIFY) -#define bfin_write_DMA2_2_Y_MODIFY(val) bfin_write16(DMA2_2_Y_MODIFY, val) -#define pDMA2_2_CURR_DESC_PTR ((void * volatile *)DMA2_2_CURR_DESC_PTR) -#define bfin_read_DMA2_2_CURR_DESC_PTR() bfin_readPTR(DMA2_2_CURR_DESC_PTR) -#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_2_CURR_DESC_PTR, val) -#define pDMA2_2_CURR_ADDR ((void * volatile *)DMA2_2_CURR_ADDR) -#define bfin_read_DMA2_2_CURR_ADDR() bfin_readPTR(DMA2_2_CURR_ADDR) -#define bfin_write_DMA2_2_CURR_ADDR(val) bfin_writePTR(DMA2_2_CURR_ADDR, val) -#define pDMA2_2_CURR_X_COUNT ((uint16_t volatile *)DMA2_2_CURR_X_COUNT) -#define bfin_read_DMA2_2_CURR_X_COUNT() bfin_read16(DMA2_2_CURR_X_COUNT) -#define bfin_write_DMA2_2_CURR_X_COUNT(val) bfin_write16(DMA2_2_CURR_X_COUNT, val) -#define pDMA2_2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_2_CURR_Y_COUNT) -#define bfin_read_DMA2_2_CURR_Y_COUNT() bfin_read16(DMA2_2_CURR_Y_COUNT) -#define bfin_write_DMA2_2_CURR_Y_COUNT(val) bfin_write16(DMA2_2_CURR_Y_COUNT, val) -#define pDMA2_2_IRQ_STATUS ((uint16_t volatile *)DMA2_2_IRQ_STATUS) -#define bfin_read_DMA2_2_IRQ_STATUS() bfin_read16(DMA2_2_IRQ_STATUS) -#define bfin_write_DMA2_2_IRQ_STATUS(val) bfin_write16(DMA2_2_IRQ_STATUS, val) -#define pDMA2_2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_2_PERIPHERAL_MAP) -#define bfin_read_DMA2_2_PERIPHERAL_MAP() bfin_read16(DMA2_2_PERIPHERAL_MAP) -#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP, val) -#define pDMA2_3_CONFIG ((uint16_t volatile *)DMA2_3_CONFIG) -#define bfin_read_DMA2_3_CONFIG() bfin_read16(DMA2_3_CONFIG) -#define bfin_write_DMA2_3_CONFIG(val) bfin_write16(DMA2_3_CONFIG, val) -#define pDMA2_3_NEXT_DESC_PTR ((void * volatile *)DMA2_3_NEXT_DESC_PTR) -#define bfin_read_DMA2_3_NEXT_DESC_PTR() bfin_readPTR(DMA2_3_NEXT_DESC_PTR) -#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_3_NEXT_DESC_PTR, val) -#define pDMA2_3_START_ADDR ((void * volatile *)DMA2_3_START_ADDR) -#define bfin_read_DMA2_3_START_ADDR() bfin_readPTR(DMA2_3_START_ADDR) -#define bfin_write_DMA2_3_START_ADDR(val) bfin_writePTR(DMA2_3_START_ADDR, val) -#define pDMA2_3_X_COUNT ((uint16_t volatile *)DMA2_3_X_COUNT) -#define bfin_read_DMA2_3_X_COUNT() bfin_read16(DMA2_3_X_COUNT) -#define bfin_write_DMA2_3_X_COUNT(val) bfin_write16(DMA2_3_X_COUNT, val) -#define pDMA2_3_Y_COUNT ((uint16_t volatile *)DMA2_3_Y_COUNT) -#define bfin_read_DMA2_3_Y_COUNT() bfin_read16(DMA2_3_Y_COUNT) -#define bfin_write_DMA2_3_Y_COUNT(val) bfin_write16(DMA2_3_Y_COUNT, val) -#define pDMA2_3_X_MODIFY ((uint16_t volatile *)DMA2_3_X_MODIFY) -#define bfin_read_DMA2_3_X_MODIFY() bfin_read16(DMA2_3_X_MODIFY) -#define bfin_write_DMA2_3_X_MODIFY(val) bfin_write16(DMA2_3_X_MODIFY, val) -#define pDMA2_3_Y_MODIFY ((uint16_t volatile *)DMA2_3_Y_MODIFY) -#define bfin_read_DMA2_3_Y_MODIFY() bfin_read16(DMA2_3_Y_MODIFY) -#define bfin_write_DMA2_3_Y_MODIFY(val) bfin_write16(DMA2_3_Y_MODIFY, val) -#define pDMA2_3_CURR_DESC_PTR ((void * volatile *)DMA2_3_CURR_DESC_PTR) -#define bfin_read_DMA2_3_CURR_DESC_PTR() bfin_readPTR(DMA2_3_CURR_DESC_PTR) -#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_writePTR(DMA2_3_CURR_DESC_PTR, val) -#define pDMA2_3_CURR_ADDR ((void * volatile *)DMA2_3_CURR_ADDR) -#define bfin_read_DMA2_3_CURR_ADDR() bfin_readPTR(DMA2_3_CURR_ADDR) -#define bfin_write_DMA2_3_CURR_ADDR(val) bfin_writePTR(DMA2_3_CURR_ADDR, val) -#define pDMA2_3_CURR_X_COUNT ((uint16_t volatile *)DMA2_3_CURR_X_COUNT) -#define bfin_read_DMA2_3_CURR_X_COUNT() bfin_read16(DMA2_3_CURR_X_COUNT) -#define bfin_write_DMA2_3_CURR_X_COUNT(val) bfin_write16(DMA2_3_CURR_X_COUNT, val) -#define pDMA2_3_CURR_Y_COUNT ((uint16_t volatile *)DMA2_3_CURR_Y_COUNT) -#define bfin_read_DMA2_3_CURR_Y_COUNT() bfin_read16(DMA2_3_CURR_Y_COUNT) -#define bfin_write_DMA2_3_CURR_Y_COUNT(val) bfin_write16(DMA2_3_CURR_Y_COUNT, val) -#define pDMA2_3_IRQ_STATUS ((uint16_t volatile *)DMA2_3_IRQ_STATUS) -#define bfin_read_DMA2_3_IRQ_STATUS() bfin_read16(DMA2_3_IRQ_STATUS) -#define bfin_write_DMA2_3_IRQ_STATUS(val) bfin_write16(DMA2_3_IRQ_STATUS, val) -#define pDMA2_3_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_3_PERIPHERAL_MAP) -#define bfin_read_DMA2_3_PERIPHERAL_MAP() bfin_read16(DMA2_3_PERIPHERAL_MAP) -#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP, val) -#define pDMA2_4_CONFIG ((uint16_t volatile *)DMA2_4_CONFIG) -#define bfin_read_DMA2_4_CONFIG() bfin_read16(DMA2_4_CONFIG) -#define bfin_write_DMA2_4_CONFIG(val) bfin_write16(DMA2_4_CONFIG, val) -#define pDMA2_4_NEXT_DESC_PTR ((void * volatile *)DMA2_4_NEXT_DESC_PTR) -#define bfin_read_DMA2_4_NEXT_DESC_PTR() bfin_readPTR(DMA2_4_NEXT_DESC_PTR) -#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_4_NEXT_DESC_PTR, val) -#define pDMA2_4_START_ADDR ((void * volatile *)DMA2_4_START_ADDR) -#define bfin_read_DMA2_4_START_ADDR() bfin_readPTR(DMA2_4_START_ADDR) -#define bfin_write_DMA2_4_START_ADDR(val) bfin_writePTR(DMA2_4_START_ADDR, val) -#define pDMA2_4_X_COUNT ((uint16_t volatile *)DMA2_4_X_COUNT) -#define bfin_read_DMA2_4_X_COUNT() bfin_read16(DMA2_4_X_COUNT) -#define bfin_write_DMA2_4_X_COUNT(val) bfin_write16(DMA2_4_X_COUNT, val) -#define pDMA2_4_Y_COUNT ((uint16_t volatile *)DMA2_4_Y_COUNT) -#define bfin_read_DMA2_4_Y_COUNT() bfin_read16(DMA2_4_Y_COUNT) -#define bfin_write_DMA2_4_Y_COUNT(val) bfin_write16(DMA2_4_Y_COUNT, val) -#define pDMA2_4_X_MODIFY ((uint16_t volatile *)DMA2_4_X_MODIFY) -#define bfin_read_DMA2_4_X_MODIFY() bfin_read16(DMA2_4_X_MODIFY) -#define bfin_write_DMA2_4_X_MODIFY(val) bfin_write16(DMA2_4_X_MODIFY, val) -#define pDMA2_4_Y_MODIFY ((uint16_t volatile *)DMA2_4_Y_MODIFY) -#define bfin_read_DMA2_4_Y_MODIFY() bfin_read16(DMA2_4_Y_MODIFY) -#define bfin_write_DMA2_4_Y_MODIFY(val) bfin_write16(DMA2_4_Y_MODIFY, val) -#define pDMA2_4_CURR_DESC_PTR ((void * volatile *)DMA2_4_CURR_DESC_PTR) -#define bfin_read_DMA2_4_CURR_DESC_PTR() bfin_readPTR(DMA2_4_CURR_DESC_PTR) -#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_writePTR(DMA2_4_CURR_DESC_PTR, val) -#define pDMA2_4_CURR_ADDR ((void * volatile *)DMA2_4_CURR_ADDR) -#define bfin_read_DMA2_4_CURR_ADDR() bfin_readPTR(DMA2_4_CURR_ADDR) -#define bfin_write_DMA2_4_CURR_ADDR(val) bfin_writePTR(DMA2_4_CURR_ADDR, val) -#define pDMA2_4_CURR_X_COUNT ((uint16_t volatile *)DMA2_4_CURR_X_COUNT) -#define bfin_read_DMA2_4_CURR_X_COUNT() bfin_read16(DMA2_4_CURR_X_COUNT) -#define bfin_write_DMA2_4_CURR_X_COUNT(val) bfin_write16(DMA2_4_CURR_X_COUNT, val) -#define pDMA2_4_CURR_Y_COUNT ((uint16_t volatile *)DMA2_4_CURR_Y_COUNT) -#define bfin_read_DMA2_4_CURR_Y_COUNT() bfin_read16(DMA2_4_CURR_Y_COUNT) -#define bfin_write_DMA2_4_CURR_Y_COUNT(val) bfin_write16(DMA2_4_CURR_Y_COUNT, val) -#define pDMA2_4_IRQ_STATUS ((uint16_t volatile *)DMA2_4_IRQ_STATUS) -#define bfin_read_DMA2_4_IRQ_STATUS() bfin_read16(DMA2_4_IRQ_STATUS) -#define bfin_write_DMA2_4_IRQ_STATUS(val) bfin_write16(DMA2_4_IRQ_STATUS, val) -#define pDMA2_4_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_4_PERIPHERAL_MAP) -#define bfin_read_DMA2_4_PERIPHERAL_MAP() bfin_read16(DMA2_4_PERIPHERAL_MAP) -#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP, val) -#define pDMA2_5_CONFIG ((uint16_t volatile *)DMA2_5_CONFIG) -#define bfin_read_DMA2_5_CONFIG() bfin_read16(DMA2_5_CONFIG) -#define bfin_write_DMA2_5_CONFIG(val) bfin_write16(DMA2_5_CONFIG, val) -#define pDMA2_5_NEXT_DESC_PTR ((void * volatile *)DMA2_5_NEXT_DESC_PTR) -#define bfin_read_DMA2_5_NEXT_DESC_PTR() bfin_readPTR(DMA2_5_NEXT_DESC_PTR) -#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_5_NEXT_DESC_PTR, val) -#define pDMA2_5_START_ADDR ((void * volatile *)DMA2_5_START_ADDR) -#define bfin_read_DMA2_5_START_ADDR() bfin_readPTR(DMA2_5_START_ADDR) -#define bfin_write_DMA2_5_START_ADDR(val) bfin_writePTR(DMA2_5_START_ADDR, val) -#define pDMA2_5_X_COUNT ((uint16_t volatile *)DMA2_5_X_COUNT) -#define bfin_read_DMA2_5_X_COUNT() bfin_read16(DMA2_5_X_COUNT) -#define bfin_write_DMA2_5_X_COUNT(val) bfin_write16(DMA2_5_X_COUNT, val) -#define pDMA2_5_Y_COUNT ((uint16_t volatile *)DMA2_5_Y_COUNT) -#define bfin_read_DMA2_5_Y_COUNT() bfin_read16(DMA2_5_Y_COUNT) -#define bfin_write_DMA2_5_Y_COUNT(val) bfin_write16(DMA2_5_Y_COUNT, val) -#define pDMA2_5_X_MODIFY ((uint16_t volatile *)DMA2_5_X_MODIFY) -#define bfin_read_DMA2_5_X_MODIFY() bfin_read16(DMA2_5_X_MODIFY) -#define bfin_write_DMA2_5_X_MODIFY(val) bfin_write16(DMA2_5_X_MODIFY, val) -#define pDMA2_5_Y_MODIFY ((uint16_t volatile *)DMA2_5_Y_MODIFY) -#define bfin_read_DMA2_5_Y_MODIFY() bfin_read16(DMA2_5_Y_MODIFY) -#define bfin_write_DMA2_5_Y_MODIFY(val) bfin_write16(DMA2_5_Y_MODIFY, val) -#define pDMA2_5_CURR_DESC_PTR ((void * volatile *)DMA2_5_CURR_DESC_PTR) -#define bfin_read_DMA2_5_CURR_DESC_PTR() bfin_readPTR(DMA2_5_CURR_DESC_PTR) -#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_writePTR(DMA2_5_CURR_DESC_PTR, val) -#define pDMA2_5_CURR_ADDR ((void * volatile *)DMA2_5_CURR_ADDR) -#define bfin_read_DMA2_5_CURR_ADDR() bfin_readPTR(DMA2_5_CURR_ADDR) -#define bfin_write_DMA2_5_CURR_ADDR(val) bfin_writePTR(DMA2_5_CURR_ADDR, val) -#define pDMA2_5_CURR_X_COUNT ((uint16_t volatile *)DMA2_5_CURR_X_COUNT) -#define bfin_read_DMA2_5_CURR_X_COUNT() bfin_read16(DMA2_5_CURR_X_COUNT) -#define bfin_write_DMA2_5_CURR_X_COUNT(val) bfin_write16(DMA2_5_CURR_X_COUNT, val) -#define pDMA2_5_CURR_Y_COUNT ((uint16_t volatile *)DMA2_5_CURR_Y_COUNT) -#define bfin_read_DMA2_5_CURR_Y_COUNT() bfin_read16(DMA2_5_CURR_Y_COUNT) -#define bfin_write_DMA2_5_CURR_Y_COUNT(val) bfin_write16(DMA2_5_CURR_Y_COUNT, val) -#define pDMA2_5_IRQ_STATUS ((uint16_t volatile *)DMA2_5_IRQ_STATUS) -#define bfin_read_DMA2_5_IRQ_STATUS() bfin_read16(DMA2_5_IRQ_STATUS) -#define bfin_write_DMA2_5_IRQ_STATUS(val) bfin_write16(DMA2_5_IRQ_STATUS, val) -#define pDMA2_5_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_5_PERIPHERAL_MAP) -#define bfin_read_DMA2_5_PERIPHERAL_MAP() bfin_read16(DMA2_5_PERIPHERAL_MAP) -#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP, val) -#define pDMA2_6_CONFIG ((uint16_t volatile *)DMA2_6_CONFIG) -#define bfin_read_DMA2_6_CONFIG() bfin_read16(DMA2_6_CONFIG) -#define bfin_write_DMA2_6_CONFIG(val) bfin_write16(DMA2_6_CONFIG, val) -#define pDMA2_6_NEXT_DESC_PTR ((void * volatile *)DMA2_6_NEXT_DESC_PTR) -#define bfin_read_DMA2_6_NEXT_DESC_PTR() bfin_readPTR(DMA2_6_NEXT_DESC_PTR) -#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_6_NEXT_DESC_PTR, val) -#define pDMA2_6_START_ADDR ((void * volatile *)DMA2_6_START_ADDR) -#define bfin_read_DMA2_6_START_ADDR() bfin_readPTR(DMA2_6_START_ADDR) -#define bfin_write_DMA2_6_START_ADDR(val) bfin_writePTR(DMA2_6_START_ADDR, val) -#define pDMA2_6_X_COUNT ((uint16_t volatile *)DMA2_6_X_COUNT) -#define bfin_read_DMA2_6_X_COUNT() bfin_read16(DMA2_6_X_COUNT) -#define bfin_write_DMA2_6_X_COUNT(val) bfin_write16(DMA2_6_X_COUNT, val) -#define pDMA2_6_Y_COUNT ((uint16_t volatile *)DMA2_6_Y_COUNT) -#define bfin_read_DMA2_6_Y_COUNT() bfin_read16(DMA2_6_Y_COUNT) -#define bfin_write_DMA2_6_Y_COUNT(val) bfin_write16(DMA2_6_Y_COUNT, val) -#define pDMA2_6_X_MODIFY ((uint16_t volatile *)DMA2_6_X_MODIFY) -#define bfin_read_DMA2_6_X_MODIFY() bfin_read16(DMA2_6_X_MODIFY) -#define bfin_write_DMA2_6_X_MODIFY(val) bfin_write16(DMA2_6_X_MODIFY, val) -#define pDMA2_6_Y_MODIFY ((uint16_t volatile *)DMA2_6_Y_MODIFY) -#define bfin_read_DMA2_6_Y_MODIFY() bfin_read16(DMA2_6_Y_MODIFY) -#define bfin_write_DMA2_6_Y_MODIFY(val) bfin_write16(DMA2_6_Y_MODIFY, val) -#define pDMA2_6_CURR_DESC_PTR ((void * volatile *)DMA2_6_CURR_DESC_PTR) -#define bfin_read_DMA2_6_CURR_DESC_PTR() bfin_readPTR(DMA2_6_CURR_DESC_PTR) -#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_writePTR(DMA2_6_CURR_DESC_PTR, val) -#define pDMA2_6_CURR_ADDR ((void * volatile *)DMA2_6_CURR_ADDR) -#define bfin_read_DMA2_6_CURR_ADDR() bfin_readPTR(DMA2_6_CURR_ADDR) -#define bfin_write_DMA2_6_CURR_ADDR(val) bfin_writePTR(DMA2_6_CURR_ADDR, val) -#define pDMA2_6_CURR_X_COUNT ((uint16_t volatile *)DMA2_6_CURR_X_COUNT) -#define bfin_read_DMA2_6_CURR_X_COUNT() bfin_read16(DMA2_6_CURR_X_COUNT) -#define bfin_write_DMA2_6_CURR_X_COUNT(val) bfin_write16(DMA2_6_CURR_X_COUNT, val) -#define pDMA2_6_CURR_Y_COUNT ((uint16_t volatile *)DMA2_6_CURR_Y_COUNT) -#define bfin_read_DMA2_6_CURR_Y_COUNT() bfin_read16(DMA2_6_CURR_Y_COUNT) -#define bfin_write_DMA2_6_CURR_Y_COUNT(val) bfin_write16(DMA2_6_CURR_Y_COUNT, val) -#define pDMA2_6_IRQ_STATUS ((uint16_t volatile *)DMA2_6_IRQ_STATUS) -#define bfin_read_DMA2_6_IRQ_STATUS() bfin_read16(DMA2_6_IRQ_STATUS) -#define bfin_write_DMA2_6_IRQ_STATUS(val) bfin_write16(DMA2_6_IRQ_STATUS, val) -#define pDMA2_6_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_6_PERIPHERAL_MAP) -#define bfin_read_DMA2_6_PERIPHERAL_MAP() bfin_read16(DMA2_6_PERIPHERAL_MAP) -#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP, val) -#define pDMA2_7_CONFIG ((uint16_t volatile *)DMA2_7_CONFIG) -#define bfin_read_DMA2_7_CONFIG() bfin_read16(DMA2_7_CONFIG) -#define bfin_write_DMA2_7_CONFIG(val) bfin_write16(DMA2_7_CONFIG, val) -#define pDMA2_7_NEXT_DESC_PTR ((void * volatile *)DMA2_7_NEXT_DESC_PTR) -#define bfin_read_DMA2_7_NEXT_DESC_PTR() bfin_readPTR(DMA2_7_NEXT_DESC_PTR) -#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_7_NEXT_DESC_PTR, val) -#define pDMA2_7_START_ADDR ((void * volatile *)DMA2_7_START_ADDR) -#define bfin_read_DMA2_7_START_ADDR() bfin_readPTR(DMA2_7_START_ADDR) -#define bfin_write_DMA2_7_START_ADDR(val) bfin_writePTR(DMA2_7_START_ADDR, val) -#define pDMA2_7_X_COUNT ((uint16_t volatile *)DMA2_7_X_COUNT) -#define bfin_read_DMA2_7_X_COUNT() bfin_read16(DMA2_7_X_COUNT) -#define bfin_write_DMA2_7_X_COUNT(val) bfin_write16(DMA2_7_X_COUNT, val) -#define pDMA2_7_Y_COUNT ((uint16_t volatile *)DMA2_7_Y_COUNT) -#define bfin_read_DMA2_7_Y_COUNT() bfin_read16(DMA2_7_Y_COUNT) -#define bfin_write_DMA2_7_Y_COUNT(val) bfin_write16(DMA2_7_Y_COUNT, val) -#define pDMA2_7_X_MODIFY ((uint16_t volatile *)DMA2_7_X_MODIFY) -#define bfin_read_DMA2_7_X_MODIFY() bfin_read16(DMA2_7_X_MODIFY) -#define bfin_write_DMA2_7_X_MODIFY(val) bfin_write16(DMA2_7_X_MODIFY, val) -#define pDMA2_7_Y_MODIFY ((uint16_t volatile *)DMA2_7_Y_MODIFY) -#define bfin_read_DMA2_7_Y_MODIFY() bfin_read16(DMA2_7_Y_MODIFY) -#define bfin_write_DMA2_7_Y_MODIFY(val) bfin_write16(DMA2_7_Y_MODIFY, val) -#define pDMA2_7_CURR_DESC_PTR ((void * volatile *)DMA2_7_CURR_DESC_PTR) -#define bfin_read_DMA2_7_CURR_DESC_PTR() bfin_readPTR(DMA2_7_CURR_DESC_PTR) -#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_writePTR(DMA2_7_CURR_DESC_PTR, val) -#define pDMA2_7_CURR_ADDR ((void * volatile *)DMA2_7_CURR_ADDR) -#define bfin_read_DMA2_7_CURR_ADDR() bfin_readPTR(DMA2_7_CURR_ADDR) -#define bfin_write_DMA2_7_CURR_ADDR(val) bfin_writePTR(DMA2_7_CURR_ADDR, val) -#define pDMA2_7_CURR_X_COUNT ((uint16_t volatile *)DMA2_7_CURR_X_COUNT) -#define bfin_read_DMA2_7_CURR_X_COUNT() bfin_read16(DMA2_7_CURR_X_COUNT) -#define bfin_write_DMA2_7_CURR_X_COUNT(val) bfin_write16(DMA2_7_CURR_X_COUNT, val) -#define pDMA2_7_CURR_Y_COUNT ((uint16_t volatile *)DMA2_7_CURR_Y_COUNT) -#define bfin_read_DMA2_7_CURR_Y_COUNT() bfin_read16(DMA2_7_CURR_Y_COUNT) -#define bfin_write_DMA2_7_CURR_Y_COUNT(val) bfin_write16(DMA2_7_CURR_Y_COUNT, val) -#define pDMA2_7_IRQ_STATUS ((uint16_t volatile *)DMA2_7_IRQ_STATUS) -#define bfin_read_DMA2_7_IRQ_STATUS() bfin_read16(DMA2_7_IRQ_STATUS) -#define bfin_write_DMA2_7_IRQ_STATUS(val) bfin_write16(DMA2_7_IRQ_STATUS, val) -#define pDMA2_7_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_7_PERIPHERAL_MAP) -#define bfin_read_DMA2_7_PERIPHERAL_MAP() bfin_read16(DMA2_7_PERIPHERAL_MAP) -#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP, val) -#define pDMA2_8_CONFIG ((uint16_t volatile *)DMA2_8_CONFIG) -#define bfin_read_DMA2_8_CONFIG() bfin_read16(DMA2_8_CONFIG) -#define bfin_write_DMA2_8_CONFIG(val) bfin_write16(DMA2_8_CONFIG, val) -#define pDMA2_8_NEXT_DESC_PTR ((void * volatile *)DMA2_8_NEXT_DESC_PTR) -#define bfin_read_DMA2_8_NEXT_DESC_PTR() bfin_readPTR(DMA2_8_NEXT_DESC_PTR) -#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_8_NEXT_DESC_PTR, val) -#define pDMA2_8_START_ADDR ((void * volatile *)DMA2_8_START_ADDR) -#define bfin_read_DMA2_8_START_ADDR() bfin_readPTR(DMA2_8_START_ADDR) -#define bfin_write_DMA2_8_START_ADDR(val) bfin_writePTR(DMA2_8_START_ADDR, val) -#define pDMA2_8_X_COUNT ((uint16_t volatile *)DMA2_8_X_COUNT) -#define bfin_read_DMA2_8_X_COUNT() bfin_read16(DMA2_8_X_COUNT) -#define bfin_write_DMA2_8_X_COUNT(val) bfin_write16(DMA2_8_X_COUNT, val) -#define pDMA2_8_Y_COUNT ((uint16_t volatile *)DMA2_8_Y_COUNT) -#define bfin_read_DMA2_8_Y_COUNT() bfin_read16(DMA2_8_Y_COUNT) -#define bfin_write_DMA2_8_Y_COUNT(val) bfin_write16(DMA2_8_Y_COUNT, val) -#define pDMA2_8_X_MODIFY ((uint16_t volatile *)DMA2_8_X_MODIFY) -#define bfin_read_DMA2_8_X_MODIFY() bfin_read16(DMA2_8_X_MODIFY) -#define bfin_write_DMA2_8_X_MODIFY(val) bfin_write16(DMA2_8_X_MODIFY, val) -#define pDMA2_8_Y_MODIFY ((uint16_t volatile *)DMA2_8_Y_MODIFY) -#define bfin_read_DMA2_8_Y_MODIFY() bfin_read16(DMA2_8_Y_MODIFY) -#define bfin_write_DMA2_8_Y_MODIFY(val) bfin_write16(DMA2_8_Y_MODIFY, val) -#define pDMA2_8_CURR_DESC_PTR ((void * volatile *)DMA2_8_CURR_DESC_PTR) -#define bfin_read_DMA2_8_CURR_DESC_PTR() bfin_readPTR(DMA2_8_CURR_DESC_PTR) -#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_writePTR(DMA2_8_CURR_DESC_PTR, val) -#define pDMA2_8_CURR_ADDR ((void * volatile *)DMA2_8_CURR_ADDR) -#define bfin_read_DMA2_8_CURR_ADDR() bfin_readPTR(DMA2_8_CURR_ADDR) -#define bfin_write_DMA2_8_CURR_ADDR(val) bfin_writePTR(DMA2_8_CURR_ADDR, val) -#define pDMA2_8_CURR_X_COUNT ((uint16_t volatile *)DMA2_8_CURR_X_COUNT) -#define bfin_read_DMA2_8_CURR_X_COUNT() bfin_read16(DMA2_8_CURR_X_COUNT) -#define bfin_write_DMA2_8_CURR_X_COUNT(val) bfin_write16(DMA2_8_CURR_X_COUNT, val) -#define pDMA2_8_CURR_Y_COUNT ((uint16_t volatile *)DMA2_8_CURR_Y_COUNT) -#define bfin_read_DMA2_8_CURR_Y_COUNT() bfin_read16(DMA2_8_CURR_Y_COUNT) -#define bfin_write_DMA2_8_CURR_Y_COUNT(val) bfin_write16(DMA2_8_CURR_Y_COUNT, val) -#define pDMA2_8_IRQ_STATUS ((uint16_t volatile *)DMA2_8_IRQ_STATUS) -#define bfin_read_DMA2_8_IRQ_STATUS() bfin_read16(DMA2_8_IRQ_STATUS) -#define bfin_write_DMA2_8_IRQ_STATUS(val) bfin_write16(DMA2_8_IRQ_STATUS, val) -#define pDMA2_8_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_8_PERIPHERAL_MAP) -#define bfin_read_DMA2_8_PERIPHERAL_MAP() bfin_read16(DMA2_8_PERIPHERAL_MAP) -#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP, val) -#define pDMA2_9_CONFIG ((uint16_t volatile *)DMA2_9_CONFIG) -#define bfin_read_DMA2_9_CONFIG() bfin_read16(DMA2_9_CONFIG) -#define bfin_write_DMA2_9_CONFIG(val) bfin_write16(DMA2_9_CONFIG, val) -#define pDMA2_9_NEXT_DESC_PTR ((void * volatile *)DMA2_9_NEXT_DESC_PTR) -#define bfin_read_DMA2_9_NEXT_DESC_PTR() bfin_readPTR(DMA2_9_NEXT_DESC_PTR) -#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_9_NEXT_DESC_PTR, val) -#define pDMA2_9_START_ADDR ((void * volatile *)DMA2_9_START_ADDR) -#define bfin_read_DMA2_9_START_ADDR() bfin_readPTR(DMA2_9_START_ADDR) -#define bfin_write_DMA2_9_START_ADDR(val) bfin_writePTR(DMA2_9_START_ADDR, val) -#define pDMA2_9_X_COUNT ((uint16_t volatile *)DMA2_9_X_COUNT) -#define bfin_read_DMA2_9_X_COUNT() bfin_read16(DMA2_9_X_COUNT) -#define bfin_write_DMA2_9_X_COUNT(val) bfin_write16(DMA2_9_X_COUNT, val) -#define pDMA2_9_Y_COUNT ((uint16_t volatile *)DMA2_9_Y_COUNT) -#define bfin_read_DMA2_9_Y_COUNT() bfin_read16(DMA2_9_Y_COUNT) -#define bfin_write_DMA2_9_Y_COUNT(val) bfin_write16(DMA2_9_Y_COUNT, val) -#define pDMA2_9_X_MODIFY ((uint16_t volatile *)DMA2_9_X_MODIFY) -#define bfin_read_DMA2_9_X_MODIFY() bfin_read16(DMA2_9_X_MODIFY) -#define bfin_write_DMA2_9_X_MODIFY(val) bfin_write16(DMA2_9_X_MODIFY, val) -#define pDMA2_9_Y_MODIFY ((uint16_t volatile *)DMA2_9_Y_MODIFY) -#define bfin_read_DMA2_9_Y_MODIFY() bfin_read16(DMA2_9_Y_MODIFY) -#define bfin_write_DMA2_9_Y_MODIFY(val) bfin_write16(DMA2_9_Y_MODIFY, val) -#define pDMA2_9_CURR_DESC_PTR ((void * volatile *)DMA2_9_CURR_DESC_PTR) -#define bfin_read_DMA2_9_CURR_DESC_PTR() bfin_readPTR(DMA2_9_CURR_DESC_PTR) -#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_writePTR(DMA2_9_CURR_DESC_PTR, val) -#define pDMA2_9_CURR_ADDR ((void * volatile *)DMA2_9_CURR_ADDR) -#define bfin_read_DMA2_9_CURR_ADDR() bfin_readPTR(DMA2_9_CURR_ADDR) -#define bfin_write_DMA2_9_CURR_ADDR(val) bfin_writePTR(DMA2_9_CURR_ADDR, val) -#define pDMA2_9_CURR_X_COUNT ((uint16_t volatile *)DMA2_9_CURR_X_COUNT) -#define bfin_read_DMA2_9_CURR_X_COUNT() bfin_read16(DMA2_9_CURR_X_COUNT) -#define bfin_write_DMA2_9_CURR_X_COUNT(val) bfin_write16(DMA2_9_CURR_X_COUNT, val) -#define pDMA2_9_CURR_Y_COUNT ((uint16_t volatile *)DMA2_9_CURR_Y_COUNT) -#define bfin_read_DMA2_9_CURR_Y_COUNT() bfin_read16(DMA2_9_CURR_Y_COUNT) -#define bfin_write_DMA2_9_CURR_Y_COUNT(val) bfin_write16(DMA2_9_CURR_Y_COUNT, val) -#define pDMA2_9_IRQ_STATUS ((uint16_t volatile *)DMA2_9_IRQ_STATUS) -#define bfin_read_DMA2_9_IRQ_STATUS() bfin_read16(DMA2_9_IRQ_STATUS) -#define bfin_write_DMA2_9_IRQ_STATUS(val) bfin_write16(DMA2_9_IRQ_STATUS, val) -#define pDMA2_9_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_9_PERIPHERAL_MAP) -#define bfin_read_DMA2_9_PERIPHERAL_MAP() bfin_read16(DMA2_9_PERIPHERAL_MAP) -#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP, val) -#define pDMA2_10_CONFIG ((uint16_t volatile *)DMA2_10_CONFIG) -#define bfin_read_DMA2_10_CONFIG() bfin_read16(DMA2_10_CONFIG) -#define bfin_write_DMA2_10_CONFIG(val) bfin_write16(DMA2_10_CONFIG, val) -#define pDMA2_10_NEXT_DESC_PTR ((void * volatile *)DMA2_10_NEXT_DESC_PTR) -#define bfin_read_DMA2_10_NEXT_DESC_PTR() bfin_readPTR(DMA2_10_NEXT_DESC_PTR) -#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_10_NEXT_DESC_PTR, val) -#define pDMA2_10_START_ADDR ((void * volatile *)DMA2_10_START_ADDR) -#define bfin_read_DMA2_10_START_ADDR() bfin_readPTR(DMA2_10_START_ADDR) -#define bfin_write_DMA2_10_START_ADDR(val) bfin_writePTR(DMA2_10_START_ADDR, val) -#define pDMA2_10_X_COUNT ((uint16_t volatile *)DMA2_10_X_COUNT) -#define bfin_read_DMA2_10_X_COUNT() bfin_read16(DMA2_10_X_COUNT) -#define bfin_write_DMA2_10_X_COUNT(val) bfin_write16(DMA2_10_X_COUNT, val) -#define pDMA2_10_Y_COUNT ((uint16_t volatile *)DMA2_10_Y_COUNT) -#define bfin_read_DMA2_10_Y_COUNT() bfin_read16(DMA2_10_Y_COUNT) -#define bfin_write_DMA2_10_Y_COUNT(val) bfin_write16(DMA2_10_Y_COUNT, val) -#define pDMA2_10_X_MODIFY ((uint16_t volatile *)DMA2_10_X_MODIFY) -#define bfin_read_DMA2_10_X_MODIFY() bfin_read16(DMA2_10_X_MODIFY) -#define bfin_write_DMA2_10_X_MODIFY(val) bfin_write16(DMA2_10_X_MODIFY, val) -#define pDMA2_10_Y_MODIFY ((uint16_t volatile *)DMA2_10_Y_MODIFY) -#define bfin_read_DMA2_10_Y_MODIFY() bfin_read16(DMA2_10_Y_MODIFY) -#define bfin_write_DMA2_10_Y_MODIFY(val) bfin_write16(DMA2_10_Y_MODIFY, val) -#define pDMA2_10_CURR_DESC_PTR ((void * volatile *)DMA2_10_CURR_DESC_PTR) -#define bfin_read_DMA2_10_CURR_DESC_PTR() bfin_readPTR(DMA2_10_CURR_DESC_PTR) -#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_writePTR(DMA2_10_CURR_DESC_PTR, val) -#define pDMA2_10_CURR_ADDR ((void * volatile *)DMA2_10_CURR_ADDR) -#define bfin_read_DMA2_10_CURR_ADDR() bfin_readPTR(DMA2_10_CURR_ADDR) -#define bfin_write_DMA2_10_CURR_ADDR(val) bfin_writePTR(DMA2_10_CURR_ADDR, val) -#define pDMA2_10_CURR_X_COUNT ((uint16_t volatile *)DMA2_10_CURR_X_COUNT) -#define bfin_read_DMA2_10_CURR_X_COUNT() bfin_read16(DMA2_10_CURR_X_COUNT) -#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT, val) -#define pDMA2_10_CURR_Y_COUNT ((uint16_t volatile *)DMA2_10_CURR_Y_COUNT) -#define bfin_read_DMA2_10_CURR_Y_COUNT() bfin_read16(DMA2_10_CURR_Y_COUNT) -#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT, val) -#define pDMA2_10_IRQ_STATUS ((uint16_t volatile *)DMA2_10_IRQ_STATUS) -#define bfin_read_DMA2_10_IRQ_STATUS() bfin_read16(DMA2_10_IRQ_STATUS) -#define bfin_write_DMA2_10_IRQ_STATUS(val) bfin_write16(DMA2_10_IRQ_STATUS, val) -#define pDMA2_10_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_10_PERIPHERAL_MAP) -#define bfin_read_DMA2_10_PERIPHERAL_MAP() bfin_read16(DMA2_10_PERIPHERAL_MAP) -#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP, val) -#define pDMA2_11_CONFIG ((uint16_t volatile *)DMA2_11_CONFIG) -#define bfin_read_DMA2_11_CONFIG() bfin_read16(DMA2_11_CONFIG) -#define bfin_write_DMA2_11_CONFIG(val) bfin_write16(DMA2_11_CONFIG, val) -#define pDMA2_11_NEXT_DESC_PTR ((void * volatile *)DMA2_11_NEXT_DESC_PTR) -#define bfin_read_DMA2_11_NEXT_DESC_PTR() bfin_readPTR(DMA2_11_NEXT_DESC_PTR) -#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_11_NEXT_DESC_PTR, val) -#define pDMA2_11_START_ADDR ((void * volatile *)DMA2_11_START_ADDR) -#define bfin_read_DMA2_11_START_ADDR() bfin_readPTR(DMA2_11_START_ADDR) -#define bfin_write_DMA2_11_START_ADDR(val) bfin_writePTR(DMA2_11_START_ADDR, val) -#define pDMA2_11_X_COUNT ((uint16_t volatile *)DMA2_11_X_COUNT) -#define bfin_read_DMA2_11_X_COUNT() bfin_read16(DMA2_11_X_COUNT) -#define bfin_write_DMA2_11_X_COUNT(val) bfin_write16(DMA2_11_X_COUNT, val) -#define pDMA2_11_Y_COUNT ((uint16_t volatile *)DMA2_11_Y_COUNT) -#define bfin_read_DMA2_11_Y_COUNT() bfin_read16(DMA2_11_Y_COUNT) -#define bfin_write_DMA2_11_Y_COUNT(val) bfin_write16(DMA2_11_Y_COUNT, val) -#define pDMA2_11_X_MODIFY ((uint16_t volatile *)DMA2_11_X_MODIFY) -#define bfin_read_DMA2_11_X_MODIFY() bfin_read16(DMA2_11_X_MODIFY) -#define bfin_write_DMA2_11_X_MODIFY(val) bfin_write16(DMA2_11_X_MODIFY, val) -#define pDMA2_11_Y_MODIFY ((uint16_t volatile *)DMA2_11_Y_MODIFY) -#define bfin_read_DMA2_11_Y_MODIFY() bfin_read16(DMA2_11_Y_MODIFY) -#define bfin_write_DMA2_11_Y_MODIFY(val) bfin_write16(DMA2_11_Y_MODIFY, val) -#define pDMA2_11_CURR_DESC_PTR ((void * volatile *)DMA2_11_CURR_DESC_PTR) -#define bfin_read_DMA2_11_CURR_DESC_PTR() bfin_readPTR(DMA2_11_CURR_DESC_PTR) -#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_writePTR(DMA2_11_CURR_DESC_PTR, val) -#define pDMA2_11_CURR_ADDR ((void * volatile *)DMA2_11_CURR_ADDR) -#define bfin_read_DMA2_11_CURR_ADDR() bfin_readPTR(DMA2_11_CURR_ADDR) -#define bfin_write_DMA2_11_CURR_ADDR(val) bfin_writePTR(DMA2_11_CURR_ADDR, val) -#define pDMA2_11_CURR_X_COUNT ((uint16_t volatile *)DMA2_11_CURR_X_COUNT) -#define bfin_read_DMA2_11_CURR_X_COUNT() bfin_read16(DMA2_11_CURR_X_COUNT) -#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT, val) -#define pDMA2_11_CURR_Y_COUNT ((uint16_t volatile *)DMA2_11_CURR_Y_COUNT) -#define bfin_read_DMA2_11_CURR_Y_COUNT() bfin_read16(DMA2_11_CURR_Y_COUNT) -#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT, val) -#define pDMA2_11_IRQ_STATUS ((uint16_t volatile *)DMA2_11_IRQ_STATUS) -#define bfin_read_DMA2_11_IRQ_STATUS() bfin_read16(DMA2_11_IRQ_STATUS) -#define bfin_write_DMA2_11_IRQ_STATUS(val) bfin_write16(DMA2_11_IRQ_STATUS, val) -#define pDMA2_11_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_11_PERIPHERAL_MAP) -#define bfin_read_DMA2_11_PERIPHERAL_MAP() bfin_read16(DMA2_11_PERIPHERAL_MAP) -#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP, val) -#define pIMDMA_S0_CONFIG ((uint16_t volatile *)IMDMA_S0_CONFIG) -#define bfin_read_IMDMA_S0_CONFIG() bfin_read16(IMDMA_S0_CONFIG) -#define bfin_write_IMDMA_S0_CONFIG(val) bfin_write16(IMDMA_S0_CONFIG, val) -#define pIMDMA_S0_NEXT_DESC_PTR ((void * volatile *)IMDMA_S0_NEXT_DESC_PTR) -#define bfin_read_IMDMA_S0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S0_NEXT_DESC_PTR) -#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S0_NEXT_DESC_PTR, val) -#define pIMDMA_S0_START_ADDR ((void * volatile *)IMDMA_S0_START_ADDR) -#define bfin_read_IMDMA_S0_START_ADDR() bfin_readPTR(IMDMA_S0_START_ADDR) -#define bfin_write_IMDMA_S0_START_ADDR(val) bfin_writePTR(IMDMA_S0_START_ADDR, val) -#define pIMDMA_S0_X_COUNT ((uint16_t volatile *)IMDMA_S0_X_COUNT) -#define bfin_read_IMDMA_S0_X_COUNT() bfin_read16(IMDMA_S0_X_COUNT) -#define bfin_write_IMDMA_S0_X_COUNT(val) bfin_write16(IMDMA_S0_X_COUNT, val) -#define pIMDMA_S0_Y_COUNT ((uint16_t volatile *)IMDMA_S0_Y_COUNT) -#define bfin_read_IMDMA_S0_Y_COUNT() bfin_read16(IMDMA_S0_Y_COUNT) -#define bfin_write_IMDMA_S0_Y_COUNT(val) bfin_write16(IMDMA_S0_Y_COUNT, val) -#define pIMDMA_S0_X_MODIFY ((uint16_t volatile *)IMDMA_S0_X_MODIFY) -#define bfin_read_IMDMA_S0_X_MODIFY() bfin_read16(IMDMA_S0_X_MODIFY) -#define bfin_write_IMDMA_S0_X_MODIFY(val) bfin_write16(IMDMA_S0_X_MODIFY, val) -#define pIMDMA_S0_Y_MODIFY ((uint16_t volatile *)IMDMA_S0_Y_MODIFY) -#define bfin_read_IMDMA_S0_Y_MODIFY() bfin_read16(IMDMA_S0_Y_MODIFY) -#define bfin_write_IMDMA_S0_Y_MODIFY(val) bfin_write16(IMDMA_S0_Y_MODIFY, val) -#define pIMDMA_S0_CURR_DESC_PTR ((void * volatile *)IMDMA_S0_CURR_DESC_PTR) -#define bfin_read_IMDMA_S0_CURR_DESC_PTR() bfin_readPTR(IMDMA_S0_CURR_DESC_PTR) -#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S0_CURR_DESC_PTR, val) -#define pIMDMA_S0_CURR_ADDR ((void * volatile *)IMDMA_S0_CURR_ADDR) -#define bfin_read_IMDMA_S0_CURR_ADDR() bfin_readPTR(IMDMA_S0_CURR_ADDR) -#define bfin_write_IMDMA_S0_CURR_ADDR(val) bfin_writePTR(IMDMA_S0_CURR_ADDR, val) -#define pIMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_X_COUNT) -#define bfin_read_IMDMA_S0_CURR_X_COUNT() bfin_read16(IMDMA_S0_CURR_X_COUNT) -#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT, val) -#define pIMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S0_CURR_Y_COUNT) -#define bfin_read_IMDMA_S0_CURR_Y_COUNT() bfin_read16(IMDMA_S0_CURR_Y_COUNT) -#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT, val) -#define pIMDMA_S0_IRQ_STATUS ((uint16_t volatile *)IMDMA_S0_IRQ_STATUS) -#define bfin_read_IMDMA_S0_IRQ_STATUS() bfin_read16(IMDMA_S0_IRQ_STATUS) -#define bfin_write_IMDMA_S0_IRQ_STATUS(val) bfin_write16(IMDMA_S0_IRQ_STATUS, val) -#define pIMDMA_D0_CONFIG ((uint16_t volatile *)IMDMA_D0_CONFIG) -#define bfin_read_IMDMA_D0_CONFIG() bfin_read16(IMDMA_D0_CONFIG) -#define bfin_write_IMDMA_D0_CONFIG(val) bfin_write16(IMDMA_D0_CONFIG, val) -#define pIMDMA_D0_NEXT_DESC_PTR ((void * volatile *)IMDMA_D0_NEXT_DESC_PTR) -#define bfin_read_IMDMA_D0_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D0_NEXT_DESC_PTR) -#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D0_NEXT_DESC_PTR, val) -#define pIMDMA_D0_START_ADDR ((void * volatile *)IMDMA_D0_START_ADDR) -#define bfin_read_IMDMA_D0_START_ADDR() bfin_readPTR(IMDMA_D0_START_ADDR) -#define bfin_write_IMDMA_D0_START_ADDR(val) bfin_writePTR(IMDMA_D0_START_ADDR, val) -#define pIMDMA_D0_X_COUNT ((uint16_t volatile *)IMDMA_D0_X_COUNT) -#define bfin_read_IMDMA_D0_X_COUNT() bfin_read16(IMDMA_D0_X_COUNT) -#define bfin_write_IMDMA_D0_X_COUNT(val) bfin_write16(IMDMA_D0_X_COUNT, val) -#define pIMDMA_D0_Y_COUNT ((uint16_t volatile *)IMDMA_D0_Y_COUNT) -#define bfin_read_IMDMA_D0_Y_COUNT() bfin_read16(IMDMA_D0_Y_COUNT) -#define bfin_write_IMDMA_D0_Y_COUNT(val) bfin_write16(IMDMA_D0_Y_COUNT, val) -#define pIMDMA_D0_X_MODIFY ((uint16_t volatile *)IMDMA_D0_X_MODIFY) -#define bfin_read_IMDMA_D0_X_MODIFY() bfin_read16(IMDMA_D0_X_MODIFY) -#define bfin_write_IMDMA_D0_X_MODIFY(val) bfin_write16(IMDMA_D0_X_MODIFY, val) -#define pIMDMA_D0_Y_MODIFY ((uint16_t volatile *)IMDMA_D0_Y_MODIFY) -#define bfin_read_IMDMA_D0_Y_MODIFY() bfin_read16(IMDMA_D0_Y_MODIFY) -#define bfin_write_IMDMA_D0_Y_MODIFY(val) bfin_write16(IMDMA_D0_Y_MODIFY, val) -#define pIMDMA_D0_CURR_DESC_PTR ((void * volatile *)IMDMA_D0_CURR_DESC_PTR) -#define bfin_read_IMDMA_D0_CURR_DESC_PTR() bfin_readPTR(IMDMA_D0_CURR_DESC_PTR) -#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D0_CURR_DESC_PTR, val) -#define pIMDMA_D0_CURR_ADDR ((void * volatile *)IMDMA_D0_CURR_ADDR) -#define bfin_read_IMDMA_D0_CURR_ADDR() bfin_readPTR(IMDMA_D0_CURR_ADDR) -#define bfin_write_IMDMA_D0_CURR_ADDR(val) bfin_writePTR(IMDMA_D0_CURR_ADDR, val) -#define pIMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_X_COUNT) -#define bfin_read_IMDMA_D0_CURR_X_COUNT() bfin_read16(IMDMA_D0_CURR_X_COUNT) -#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT, val) -#define pIMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D0_CURR_Y_COUNT) -#define bfin_read_IMDMA_D0_CURR_Y_COUNT() bfin_read16(IMDMA_D0_CURR_Y_COUNT) -#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT, val) -#define pIMDMA_D0_IRQ_STATUS ((uint16_t volatile *)IMDMA_D0_IRQ_STATUS) -#define bfin_read_IMDMA_D0_IRQ_STATUS() bfin_read16(IMDMA_D0_IRQ_STATUS) -#define bfin_write_IMDMA_D0_IRQ_STATUS(val) bfin_write16(IMDMA_D0_IRQ_STATUS, val) -#define pIMDMA_S1_CONFIG ((uint16_t volatile *)IMDMA_S1_CONFIG) -#define bfin_read_IMDMA_S1_CONFIG() bfin_read16(IMDMA_S1_CONFIG) -#define bfin_write_IMDMA_S1_CONFIG(val) bfin_write16(IMDMA_S1_CONFIG, val) -#define pIMDMA_S1_NEXT_DESC_PTR ((void * volatile *)IMDMA_S1_NEXT_DESC_PTR) -#define bfin_read_IMDMA_S1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_S1_NEXT_DESC_PTR) -#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_S1_NEXT_DESC_PTR, val) -#define pIMDMA_S1_START_ADDR ((void * volatile *)IMDMA_S1_START_ADDR) -#define bfin_read_IMDMA_S1_START_ADDR() bfin_readPTR(IMDMA_S1_START_ADDR) -#define bfin_write_IMDMA_S1_START_ADDR(val) bfin_writePTR(IMDMA_S1_START_ADDR, val) -#define pIMDMA_S1_X_COUNT ((uint16_t volatile *)IMDMA_S1_X_COUNT) -#define bfin_read_IMDMA_S1_X_COUNT() bfin_read16(IMDMA_S1_X_COUNT) -#define bfin_write_IMDMA_S1_X_COUNT(val) bfin_write16(IMDMA_S1_X_COUNT, val) -#define pIMDMA_S1_Y_COUNT ((uint16_t volatile *)IMDMA_S1_Y_COUNT) -#define bfin_read_IMDMA_S1_Y_COUNT() bfin_read16(IMDMA_S1_Y_COUNT) -#define bfin_write_IMDMA_S1_Y_COUNT(val) bfin_write16(IMDMA_S1_Y_COUNT, val) -#define pIMDMA_S1_X_MODIFY ((uint16_t volatile *)IMDMA_S1_X_MODIFY) -#define bfin_read_IMDMA_S1_X_MODIFY() bfin_read16(IMDMA_S1_X_MODIFY) -#define bfin_write_IMDMA_S1_X_MODIFY(val) bfin_write16(IMDMA_S1_X_MODIFY, val) -#define pIMDMA_S1_Y_MODIFY ((uint16_t volatile *)IMDMA_S1_Y_MODIFY) -#define bfin_read_IMDMA_S1_Y_MODIFY() bfin_read16(IMDMA_S1_Y_MODIFY) -#define bfin_write_IMDMA_S1_Y_MODIFY(val) bfin_write16(IMDMA_S1_Y_MODIFY, val) -#define pIMDMA_S1_CURR_DESC_PTR ((void * volatile *)IMDMA_S1_CURR_DESC_PTR) -#define bfin_read_IMDMA_S1_CURR_DESC_PTR() bfin_readPTR(IMDMA_S1_CURR_DESC_PTR) -#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_S1_CURR_DESC_PTR, val) -#define pIMDMA_S1_CURR_ADDR ((void * volatile *)IMDMA_S1_CURR_ADDR) -#define bfin_read_IMDMA_S1_CURR_ADDR() bfin_readPTR(IMDMA_S1_CURR_ADDR) -#define bfin_write_IMDMA_S1_CURR_ADDR(val) bfin_writePTR(IMDMA_S1_CURR_ADDR, val) -#define pIMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_X_COUNT) -#define bfin_read_IMDMA_S1_CURR_X_COUNT() bfin_read16(IMDMA_S1_CURR_X_COUNT) -#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT, val) -#define pIMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_S1_CURR_Y_COUNT) -#define bfin_read_IMDMA_S1_CURR_Y_COUNT() bfin_read16(IMDMA_S1_CURR_Y_COUNT) -#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT, val) -#define pIMDMA_S1_IRQ_STATUS ((uint16_t volatile *)IMDMA_S1_IRQ_STATUS) -#define bfin_read_IMDMA_S1_IRQ_STATUS() bfin_read16(IMDMA_S1_IRQ_STATUS) -#define bfin_write_IMDMA_S1_IRQ_STATUS(val) bfin_write16(IMDMA_S1_IRQ_STATUS, val) -#define pIMDMA_D1_CONFIG ((uint16_t volatile *)IMDMA_D1_CONFIG) -#define bfin_read_IMDMA_D1_CONFIG() bfin_read16(IMDMA_D1_CONFIG) -#define bfin_write_IMDMA_D1_CONFIG(val) bfin_write16(IMDMA_D1_CONFIG, val) -#define pIMDMA_D1_NEXT_DESC_PTR ((void * volatile *)IMDMA_D1_NEXT_DESC_PTR) -#define bfin_read_IMDMA_D1_NEXT_DESC_PTR() bfin_readPTR(IMDMA_D1_NEXT_DESC_PTR) -#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(IMDMA_D1_NEXT_DESC_PTR, val) -#define pIMDMA_D1_START_ADDR ((void * volatile *)IMDMA_D1_START_ADDR) -#define bfin_read_IMDMA_D1_START_ADDR() bfin_readPTR(IMDMA_D1_START_ADDR) -#define bfin_write_IMDMA_D1_START_ADDR(val) bfin_writePTR(IMDMA_D1_START_ADDR, val) -#define pIMDMA_D1_X_COUNT ((uint16_t volatile *)IMDMA_D1_X_COUNT) -#define bfin_read_IMDMA_D1_X_COUNT() bfin_read16(IMDMA_D1_X_COUNT) -#define bfin_write_IMDMA_D1_X_COUNT(val) bfin_write16(IMDMA_D1_X_COUNT, val) -#define pIMDMA_D1_Y_COUNT ((uint16_t volatile *)IMDMA_D1_Y_COUNT) -#define bfin_read_IMDMA_D1_Y_COUNT() bfin_read16(IMDMA_D1_Y_COUNT) -#define bfin_write_IMDMA_D1_Y_COUNT(val) bfin_write16(IMDMA_D1_Y_COUNT, val) -#define pIMDMA_D1_X_MODIFY ((uint16_t volatile *)IMDMA_D1_X_MODIFY) -#define bfin_read_IMDMA_D1_X_MODIFY() bfin_read16(IMDMA_D1_X_MODIFY) -#define bfin_write_IMDMA_D1_X_MODIFY(val) bfin_write16(IMDMA_D1_X_MODIFY, val) -#define pIMDMA_D1_Y_MODIFY ((uint16_t volatile *)IMDMA_D1_Y_MODIFY) -#define bfin_read_IMDMA_D1_Y_MODIFY() bfin_read16(IMDMA_D1_Y_MODIFY) -#define bfin_write_IMDMA_D1_Y_MODIFY(val) bfin_write16(IMDMA_D1_Y_MODIFY, val) -#define pIMDMA_D1_CURR_DESC_PTR ((void * volatile *)IMDMA_D1_CURR_DESC_PTR) -#define bfin_read_IMDMA_D1_CURR_DESC_PTR() bfin_readPTR(IMDMA_D1_CURR_DESC_PTR) -#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(IMDMA_D1_CURR_DESC_PTR, val) -#define pIMDMA_D1_CURR_ADDR ((void * volatile *)IMDMA_D1_CURR_ADDR) -#define bfin_read_IMDMA_D1_CURR_ADDR() bfin_readPTR(IMDMA_D1_CURR_ADDR) -#define bfin_write_IMDMA_D1_CURR_ADDR(val) bfin_writePTR(IMDMA_D1_CURR_ADDR, val) -#define pIMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_X_COUNT) -#define bfin_read_IMDMA_D1_CURR_X_COUNT() bfin_read16(IMDMA_D1_CURR_X_COUNT) -#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT, val) -#define pIMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)IMDMA_D1_CURR_Y_COUNT) -#define bfin_read_IMDMA_D1_CURR_Y_COUNT() bfin_read16(IMDMA_D1_CURR_Y_COUNT) -#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT, val) -#define pIMDMA_D1_IRQ_STATUS ((uint16_t volatile *)IMDMA_D1_IRQ_STATUS) -#define bfin_read_IMDMA_D1_IRQ_STATUS() bfin_read16(IMDMA_D1_IRQ_STATUS) -#define bfin_write_IMDMA_D1_IRQ_STATUS(val) bfin_write16(IMDMA_D1_IRQ_STATUS, val) -#define pMDMA1_S0_CONFIG ((uint16_t volatile *)MDMA1_S0_CONFIG) -#define bfin_read_MDMA1_S0_CONFIG() bfin_read16(MDMA1_S0_CONFIG) -#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val) -#define pMDMA1_S0_NEXT_DESC_PTR ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR) -#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val) -#define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR) -#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR) -#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val) -#define pMDMA1_S0_X_COUNT ((uint16_t volatile *)MDMA1_S0_X_COUNT) -#define bfin_read_MDMA1_S0_X_COUNT() bfin_read16(MDMA1_S0_X_COUNT) -#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val) -#define pMDMA1_S0_Y_COUNT ((uint16_t volatile *)MDMA1_S0_Y_COUNT) -#define bfin_read_MDMA1_S0_Y_COUNT() bfin_read16(MDMA1_S0_Y_COUNT) -#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val) -#define pMDMA1_S0_X_MODIFY ((uint16_t volatile *)MDMA1_S0_X_MODIFY) -#define bfin_read_MDMA1_S0_X_MODIFY() bfin_read16(MDMA1_S0_X_MODIFY) -#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val) -#define pMDMA1_S0_Y_MODIFY ((uint16_t volatile *)MDMA1_S0_Y_MODIFY) -#define bfin_read_MDMA1_S0_Y_MODIFY() bfin_read16(MDMA1_S0_Y_MODIFY) -#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val) -#define pMDMA1_S0_CURR_DESC_PTR ((void * volatile *)MDMA1_S0_CURR_DESC_PTR) -#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR) -#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val) -#define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR) -#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR) -#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val) -#define pMDMA1_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_X_COUNT) -#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT) -#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val) -#define pMDMA1_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S0_CURR_Y_COUNT) -#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT) -#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val) -#define pMDMA1_S0_IRQ_STATUS ((uint16_t volatile *)MDMA1_S0_IRQ_STATUS) -#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS) -#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val) -#define pMDMA1_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S0_PERIPHERAL_MAP) -#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val) -#define pMDMA1_D0_CONFIG ((uint16_t volatile *)MDMA1_D0_CONFIG) -#define bfin_read_MDMA1_D0_CONFIG() bfin_read16(MDMA1_D0_CONFIG) -#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val) -#define pMDMA1_D0_NEXT_DESC_PTR ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR) -#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val) -#define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR) -#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR) -#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val) -#define pMDMA1_D0_X_COUNT ((uint16_t volatile *)MDMA1_D0_X_COUNT) -#define bfin_read_MDMA1_D0_X_COUNT() bfin_read16(MDMA1_D0_X_COUNT) -#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val) -#define pMDMA1_D0_Y_COUNT ((uint16_t volatile *)MDMA1_D0_Y_COUNT) -#define bfin_read_MDMA1_D0_Y_COUNT() bfin_read16(MDMA1_D0_Y_COUNT) -#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val) -#define pMDMA1_D0_X_MODIFY ((uint16_t volatile *)MDMA1_D0_X_MODIFY) -#define bfin_read_MDMA1_D0_X_MODIFY() bfin_read16(MDMA1_D0_X_MODIFY) -#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val) -#define pMDMA1_D0_Y_MODIFY ((uint16_t volatile *)MDMA1_D0_Y_MODIFY) -#define bfin_read_MDMA1_D0_Y_MODIFY() bfin_read16(MDMA1_D0_Y_MODIFY) -#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val) -#define pMDMA1_D0_CURR_DESC_PTR ((void * volatile *)MDMA1_D0_CURR_DESC_PTR) -#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR) -#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val) -#define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR) -#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR) -#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val) -#define pMDMA1_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_X_COUNT) -#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT) -#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val) -#define pMDMA1_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D0_CURR_Y_COUNT) -#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT) -#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val) -#define pMDMA1_D0_IRQ_STATUS ((uint16_t volatile *)MDMA1_D0_IRQ_STATUS) -#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS) -#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val) -#define pMDMA1_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D0_PERIPHERAL_MAP) -#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val) -#define pMDMA1_S1_CONFIG ((uint16_t volatile *)MDMA1_S1_CONFIG) -#define bfin_read_MDMA1_S1_CONFIG() bfin_read16(MDMA1_S1_CONFIG) -#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val) -#define pMDMA1_S1_NEXT_DESC_PTR ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR) -#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val) -#define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR) -#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR) -#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val) -#define pMDMA1_S1_X_COUNT ((uint16_t volatile *)MDMA1_S1_X_COUNT) -#define bfin_read_MDMA1_S1_X_COUNT() bfin_read16(MDMA1_S1_X_COUNT) -#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val) -#define pMDMA1_S1_Y_COUNT ((uint16_t volatile *)MDMA1_S1_Y_COUNT) -#define bfin_read_MDMA1_S1_Y_COUNT() bfin_read16(MDMA1_S1_Y_COUNT) -#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val) -#define pMDMA1_S1_X_MODIFY ((uint16_t volatile *)MDMA1_S1_X_MODIFY) -#define bfin_read_MDMA1_S1_X_MODIFY() bfin_read16(MDMA1_S1_X_MODIFY) -#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val) -#define pMDMA1_S1_Y_MODIFY ((uint16_t volatile *)MDMA1_S1_Y_MODIFY) -#define bfin_read_MDMA1_S1_Y_MODIFY() bfin_read16(MDMA1_S1_Y_MODIFY) -#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val) -#define pMDMA1_S1_CURR_DESC_PTR ((void * volatile *)MDMA1_S1_CURR_DESC_PTR) -#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR) -#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val) -#define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR) -#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR) -#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val) -#define pMDMA1_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_X_COUNT) -#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT) -#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val) -#define pMDMA1_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_S1_CURR_Y_COUNT) -#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT) -#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val) -#define pMDMA1_S1_IRQ_STATUS ((uint16_t volatile *)MDMA1_S1_IRQ_STATUS) -#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS) -#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val) -#define pMDMA1_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_S1_PERIPHERAL_MAP) -#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val) -#define pMDMA1_D1_CONFIG ((uint16_t volatile *)MDMA1_D1_CONFIG) -#define bfin_read_MDMA1_D1_CONFIG() bfin_read16(MDMA1_D1_CONFIG) -#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val) -#define pMDMA1_D1_NEXT_DESC_PTR ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR) -#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val) -#define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR) -#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR) -#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val) -#define pMDMA1_D1_X_COUNT ((uint16_t volatile *)MDMA1_D1_X_COUNT) -#define bfin_read_MDMA1_D1_X_COUNT() bfin_read16(MDMA1_D1_X_COUNT) -#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val) -#define pMDMA1_D1_Y_COUNT ((uint16_t volatile *)MDMA1_D1_Y_COUNT) -#define bfin_read_MDMA1_D1_Y_COUNT() bfin_read16(MDMA1_D1_Y_COUNT) -#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val) -#define pMDMA1_D1_X_MODIFY ((uint16_t volatile *)MDMA1_D1_X_MODIFY) -#define bfin_read_MDMA1_D1_X_MODIFY() bfin_read16(MDMA1_D1_X_MODIFY) -#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val) -#define pMDMA1_D1_Y_MODIFY ((uint16_t volatile *)MDMA1_D1_Y_MODIFY) -#define bfin_read_MDMA1_D1_Y_MODIFY() bfin_read16(MDMA1_D1_Y_MODIFY) -#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val) -#define pMDMA1_D1_CURR_DESC_PTR ((void * volatile *)MDMA1_D1_CURR_DESC_PTR) -#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR) -#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val) -#define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR) -#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR) -#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val) -#define pMDMA1_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_X_COUNT) -#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT) -#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val) -#define pMDMA1_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA1_D1_CURR_Y_COUNT) -#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT) -#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val) -#define pMDMA1_D1_IRQ_STATUS ((uint16_t volatile *)MDMA1_D1_IRQ_STATUS) -#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS) -#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val) -#define pMDMA1_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA1_D1_PERIPHERAL_MAP) -#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val) -#define pMDMA2_S0_CONFIG ((uint16_t volatile *)MDMA2_S0_CONFIG) -#define bfin_read_MDMA2_S0_CONFIG() bfin_read16(MDMA2_S0_CONFIG) -#define bfin_write_MDMA2_S0_CONFIG(val) bfin_write16(MDMA2_S0_CONFIG, val) -#define pMDMA2_S0_NEXT_DESC_PTR ((void * volatile *)MDMA2_S0_NEXT_DESC_PTR) -#define bfin_read_MDMA2_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S0_NEXT_DESC_PTR, val) -#define pMDMA2_S0_START_ADDR ((void * volatile *)MDMA2_S0_START_ADDR) -#define bfin_read_MDMA2_S0_START_ADDR() bfin_readPTR(MDMA2_S0_START_ADDR) -#define bfin_write_MDMA2_S0_START_ADDR(val) bfin_writePTR(MDMA2_S0_START_ADDR, val) -#define pMDMA2_S0_X_COUNT ((uint16_t volatile *)MDMA2_S0_X_COUNT) -#define bfin_read_MDMA2_S0_X_COUNT() bfin_read16(MDMA2_S0_X_COUNT) -#define bfin_write_MDMA2_S0_X_COUNT(val) bfin_write16(MDMA2_S0_X_COUNT, val) -#define pMDMA2_S0_Y_COUNT ((uint16_t volatile *)MDMA2_S0_Y_COUNT) -#define bfin_read_MDMA2_S0_Y_COUNT() bfin_read16(MDMA2_S0_Y_COUNT) -#define bfin_write_MDMA2_S0_Y_COUNT(val) bfin_write16(MDMA2_S0_Y_COUNT, val) -#define pMDMA2_S0_X_MODIFY ((uint16_t volatile *)MDMA2_S0_X_MODIFY) -#define bfin_read_MDMA2_S0_X_MODIFY() bfin_read16(MDMA2_S0_X_MODIFY) -#define bfin_write_MDMA2_S0_X_MODIFY(val) bfin_write16(MDMA2_S0_X_MODIFY, val) -#define pMDMA2_S0_Y_MODIFY ((uint16_t volatile *)MDMA2_S0_Y_MODIFY) -#define bfin_read_MDMA2_S0_Y_MODIFY() bfin_read16(MDMA2_S0_Y_MODIFY) -#define bfin_write_MDMA2_S0_Y_MODIFY(val) bfin_write16(MDMA2_S0_Y_MODIFY, val) -#define pMDMA2_S0_CURR_DESC_PTR ((void * volatile *)MDMA2_S0_CURR_DESC_PTR) -#define bfin_read_MDMA2_S0_CURR_DESC_PTR() bfin_readPTR(MDMA2_S0_CURR_DESC_PTR) -#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S0_CURR_DESC_PTR, val) -#define pMDMA2_S0_CURR_ADDR ((void * volatile *)MDMA2_S0_CURR_ADDR) -#define bfin_read_MDMA2_S0_CURR_ADDR() bfin_readPTR(MDMA2_S0_CURR_ADDR) -#define bfin_write_MDMA2_S0_CURR_ADDR(val) bfin_writePTR(MDMA2_S0_CURR_ADDR, val) -#define pMDMA2_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_X_COUNT) -#define bfin_read_MDMA2_S0_CURR_X_COUNT() bfin_read16(MDMA2_S0_CURR_X_COUNT) -#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT, val) -#define pMDMA2_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S0_CURR_Y_COUNT) -#define bfin_read_MDMA2_S0_CURR_Y_COUNT() bfin_read16(MDMA2_S0_CURR_Y_COUNT) -#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT, val) -#define pMDMA2_S0_IRQ_STATUS ((uint16_t volatile *)MDMA2_S0_IRQ_STATUS) -#define bfin_read_MDMA2_S0_IRQ_STATUS() bfin_read16(MDMA2_S0_IRQ_STATUS) -#define bfin_write_MDMA2_S0_IRQ_STATUS(val) bfin_write16(MDMA2_S0_IRQ_STATUS, val) -#define pMDMA2_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S0_PERIPHERAL_MAP) -#define bfin_read_MDMA2_S0_PERIPHERAL_MAP() bfin_read16(MDMA2_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP, val) -#define pMDMA2_D0_CONFIG ((uint16_t volatile *)MDMA2_D0_CONFIG) -#define bfin_read_MDMA2_D0_CONFIG() bfin_read16(MDMA2_D0_CONFIG) -#define bfin_write_MDMA2_D0_CONFIG(val) bfin_write16(MDMA2_D0_CONFIG, val) -#define pMDMA2_D0_NEXT_DESC_PTR ((void * volatile *)MDMA2_D0_NEXT_DESC_PTR) -#define bfin_read_MDMA2_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D0_NEXT_DESC_PTR, val) -#define pMDMA2_D0_START_ADDR ((void * volatile *)MDMA2_D0_START_ADDR) -#define bfin_read_MDMA2_D0_START_ADDR() bfin_readPTR(MDMA2_D0_START_ADDR) -#define bfin_write_MDMA2_D0_START_ADDR(val) bfin_writePTR(MDMA2_D0_START_ADDR, val) -#define pMDMA2_D0_X_COUNT ((uint16_t volatile *)MDMA2_D0_X_COUNT) -#define bfin_read_MDMA2_D0_X_COUNT() bfin_read16(MDMA2_D0_X_COUNT) -#define bfin_write_MDMA2_D0_X_COUNT(val) bfin_write16(MDMA2_D0_X_COUNT, val) -#define pMDMA2_D0_Y_COUNT ((uint16_t volatile *)MDMA2_D0_Y_COUNT) -#define bfin_read_MDMA2_D0_Y_COUNT() bfin_read16(MDMA2_D0_Y_COUNT) -#define bfin_write_MDMA2_D0_Y_COUNT(val) bfin_write16(MDMA2_D0_Y_COUNT, val) -#define pMDMA2_D0_X_MODIFY ((uint16_t volatile *)MDMA2_D0_X_MODIFY) -#define bfin_read_MDMA2_D0_X_MODIFY() bfin_read16(MDMA2_D0_X_MODIFY) -#define bfin_write_MDMA2_D0_X_MODIFY(val) bfin_write16(MDMA2_D0_X_MODIFY, val) -#define pMDMA2_D0_Y_MODIFY ((uint16_t volatile *)MDMA2_D0_Y_MODIFY) -#define bfin_read_MDMA2_D0_Y_MODIFY() bfin_read16(MDMA2_D0_Y_MODIFY) -#define bfin_write_MDMA2_D0_Y_MODIFY(val) bfin_write16(MDMA2_D0_Y_MODIFY, val) -#define pMDMA2_D0_CURR_DESC_PTR ((void * volatile *)MDMA2_D0_CURR_DESC_PTR) -#define bfin_read_MDMA2_D0_CURR_DESC_PTR() bfin_readPTR(MDMA2_D0_CURR_DESC_PTR) -#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D0_CURR_DESC_PTR, val) -#define pMDMA2_D0_CURR_ADDR ((void * volatile *)MDMA2_D0_CURR_ADDR) -#define bfin_read_MDMA2_D0_CURR_ADDR() bfin_readPTR(MDMA2_D0_CURR_ADDR) -#define bfin_write_MDMA2_D0_CURR_ADDR(val) bfin_writePTR(MDMA2_D0_CURR_ADDR, val) -#define pMDMA2_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_X_COUNT) -#define bfin_read_MDMA2_D0_CURR_X_COUNT() bfin_read16(MDMA2_D0_CURR_X_COUNT) -#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT, val) -#define pMDMA2_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D0_CURR_Y_COUNT) -#define bfin_read_MDMA2_D0_CURR_Y_COUNT() bfin_read16(MDMA2_D0_CURR_Y_COUNT) -#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT, val) -#define pMDMA2_D0_IRQ_STATUS ((uint16_t volatile *)MDMA2_D0_IRQ_STATUS) -#define bfin_read_MDMA2_D0_IRQ_STATUS() bfin_read16(MDMA2_D0_IRQ_STATUS) -#define bfin_write_MDMA2_D0_IRQ_STATUS(val) bfin_write16(MDMA2_D0_IRQ_STATUS, val) -#define pMDMA2_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D0_PERIPHERAL_MAP) -#define bfin_read_MDMA2_D0_PERIPHERAL_MAP() bfin_read16(MDMA2_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP, val) -#define pMDMA2_S1_CONFIG ((uint16_t volatile *)MDMA2_S1_CONFIG) -#define bfin_read_MDMA2_S1_CONFIG() bfin_read16(MDMA2_S1_CONFIG) -#define bfin_write_MDMA2_S1_CONFIG(val) bfin_write16(MDMA2_S1_CONFIG, val) -#define pMDMA2_S1_NEXT_DESC_PTR ((void * volatile *)MDMA2_S1_NEXT_DESC_PTR) -#define bfin_read_MDMA2_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_S1_NEXT_DESC_PTR, val) -#define pMDMA2_S1_START_ADDR ((void * volatile *)MDMA2_S1_START_ADDR) -#define bfin_read_MDMA2_S1_START_ADDR() bfin_readPTR(MDMA2_S1_START_ADDR) -#define bfin_write_MDMA2_S1_START_ADDR(val) bfin_writePTR(MDMA2_S1_START_ADDR, val) -#define pMDMA2_S1_X_COUNT ((uint16_t volatile *)MDMA2_S1_X_COUNT) -#define bfin_read_MDMA2_S1_X_COUNT() bfin_read16(MDMA2_S1_X_COUNT) -#define bfin_write_MDMA2_S1_X_COUNT(val) bfin_write16(MDMA2_S1_X_COUNT, val) -#define pMDMA2_S1_Y_COUNT ((uint16_t volatile *)MDMA2_S1_Y_COUNT) -#define bfin_read_MDMA2_S1_Y_COUNT() bfin_read16(MDMA2_S1_Y_COUNT) -#define bfin_write_MDMA2_S1_Y_COUNT(val) bfin_write16(MDMA2_S1_Y_COUNT, val) -#define pMDMA2_S1_X_MODIFY ((uint16_t volatile *)MDMA2_S1_X_MODIFY) -#define bfin_read_MDMA2_S1_X_MODIFY() bfin_read16(MDMA2_S1_X_MODIFY) -#define bfin_write_MDMA2_S1_X_MODIFY(val) bfin_write16(MDMA2_S1_X_MODIFY, val) -#define pMDMA2_S1_Y_MODIFY ((uint16_t volatile *)MDMA2_S1_Y_MODIFY) -#define bfin_read_MDMA2_S1_Y_MODIFY() bfin_read16(MDMA2_S1_Y_MODIFY) -#define bfin_write_MDMA2_S1_Y_MODIFY(val) bfin_write16(MDMA2_S1_Y_MODIFY, val) -#define pMDMA2_S1_CURR_DESC_PTR ((void * volatile *)MDMA2_S1_CURR_DESC_PTR) -#define bfin_read_MDMA2_S1_CURR_DESC_PTR() bfin_readPTR(MDMA2_S1_CURR_DESC_PTR) -#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_S1_CURR_DESC_PTR, val) -#define pMDMA2_S1_CURR_ADDR ((void * volatile *)MDMA2_S1_CURR_ADDR) -#define bfin_read_MDMA2_S1_CURR_ADDR() bfin_readPTR(MDMA2_S1_CURR_ADDR) -#define bfin_write_MDMA2_S1_CURR_ADDR(val) bfin_writePTR(MDMA2_S1_CURR_ADDR, val) -#define pMDMA2_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_X_COUNT) -#define bfin_read_MDMA2_S1_CURR_X_COUNT() bfin_read16(MDMA2_S1_CURR_X_COUNT) -#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT, val) -#define pMDMA2_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_S1_CURR_Y_COUNT) -#define bfin_read_MDMA2_S1_CURR_Y_COUNT() bfin_read16(MDMA2_S1_CURR_Y_COUNT) -#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT, val) -#define pMDMA2_S1_IRQ_STATUS ((uint16_t volatile *)MDMA2_S1_IRQ_STATUS) -#define bfin_read_MDMA2_S1_IRQ_STATUS() bfin_read16(MDMA2_S1_IRQ_STATUS) -#define bfin_write_MDMA2_S1_IRQ_STATUS(val) bfin_write16(MDMA2_S1_IRQ_STATUS, val) -#define pMDMA2_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_S1_PERIPHERAL_MAP) -#define bfin_read_MDMA2_S1_PERIPHERAL_MAP() bfin_read16(MDMA2_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP, val) -#define pMDMA2_D1_CONFIG ((uint16_t volatile *)MDMA2_D1_CONFIG) -#define bfin_read_MDMA2_D1_CONFIG() bfin_read16(MDMA2_D1_CONFIG) -#define bfin_write_MDMA2_D1_CONFIG(val) bfin_write16(MDMA2_D1_CONFIG, val) -#define pMDMA2_D1_NEXT_DESC_PTR ((void * volatile *)MDMA2_D1_NEXT_DESC_PTR) -#define bfin_read_MDMA2_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA2_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA2_D1_NEXT_DESC_PTR, val) -#define pMDMA2_D1_START_ADDR ((void * volatile *)MDMA2_D1_START_ADDR) -#define bfin_read_MDMA2_D1_START_ADDR() bfin_readPTR(MDMA2_D1_START_ADDR) -#define bfin_write_MDMA2_D1_START_ADDR(val) bfin_writePTR(MDMA2_D1_START_ADDR, val) -#define pMDMA2_D1_X_COUNT ((uint16_t volatile *)MDMA2_D1_X_COUNT) -#define bfin_read_MDMA2_D1_X_COUNT() bfin_read16(MDMA2_D1_X_COUNT) -#define bfin_write_MDMA2_D1_X_COUNT(val) bfin_write16(MDMA2_D1_X_COUNT, val) -#define pMDMA2_D1_Y_COUNT ((uint16_t volatile *)MDMA2_D1_Y_COUNT) -#define bfin_read_MDMA2_D1_Y_COUNT() bfin_read16(MDMA2_D1_Y_COUNT) -#define bfin_write_MDMA2_D1_Y_COUNT(val) bfin_write16(MDMA2_D1_Y_COUNT, val) -#define pMDMA2_D1_X_MODIFY ((uint16_t volatile *)MDMA2_D1_X_MODIFY) -#define bfin_read_MDMA2_D1_X_MODIFY() bfin_read16(MDMA2_D1_X_MODIFY) -#define bfin_write_MDMA2_D1_X_MODIFY(val) bfin_write16(MDMA2_D1_X_MODIFY, val) -#define pMDMA2_D1_Y_MODIFY ((uint16_t volatile *)MDMA2_D1_Y_MODIFY) -#define bfin_read_MDMA2_D1_Y_MODIFY() bfin_read16(MDMA2_D1_Y_MODIFY) -#define bfin_write_MDMA2_D1_Y_MODIFY(val) bfin_write16(MDMA2_D1_Y_MODIFY, val) -#define pMDMA2_D1_CURR_DESC_PTR ((void * volatile *)MDMA2_D1_CURR_DESC_PTR) -#define bfin_read_MDMA2_D1_CURR_DESC_PTR() bfin_readPTR(MDMA2_D1_CURR_DESC_PTR) -#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA2_D1_CURR_DESC_PTR, val) -#define pMDMA2_D1_CURR_ADDR ((void * volatile *)MDMA2_D1_CURR_ADDR) -#define bfin_read_MDMA2_D1_CURR_ADDR() bfin_readPTR(MDMA2_D1_CURR_ADDR) -#define bfin_write_MDMA2_D1_CURR_ADDR(val) bfin_writePTR(MDMA2_D1_CURR_ADDR, val) -#define pMDMA2_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_X_COUNT) -#define bfin_read_MDMA2_D1_CURR_X_COUNT() bfin_read16(MDMA2_D1_CURR_X_COUNT) -#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT, val) -#define pMDMA2_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA2_D1_CURR_Y_COUNT) -#define bfin_read_MDMA2_D1_CURR_Y_COUNT() bfin_read16(MDMA2_D1_CURR_Y_COUNT) -#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT, val) -#define pMDMA2_D1_IRQ_STATUS ((uint16_t volatile *)MDMA2_D1_IRQ_STATUS) -#define bfin_read_MDMA2_D1_IRQ_STATUS() bfin_read16(MDMA2_D1_IRQ_STATUS) -#define bfin_write_MDMA2_D1_IRQ_STATUS(val) bfin_write16(MDMA2_D1_IRQ_STATUS, val) -#define pMDMA2_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA2_D1_PERIPHERAL_MAP) -#define bfin_read_MDMA2_D1_PERIPHERAL_MAP() bfin_read16(MDMA2_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER3_CONFIG ((uint16_t volatile *)TIMER3_CONFIG) -#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG) -#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val) -#define pTIMER3_COUNTER ((uint32_t volatile *)TIMER3_COUNTER) -#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER) -#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val) -#define pTIMER3_PERIOD ((uint32_t volatile *)TIMER3_PERIOD) -#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD) -#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val) -#define pTIMER3_WIDTH ((uint32_t volatile *)TIMER3_WIDTH) -#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH) -#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val) -#define pTIMER4_CONFIG ((uint16_t volatile *)TIMER4_CONFIG) -#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG) -#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val) -#define pTIMER4_COUNTER ((uint32_t volatile *)TIMER4_COUNTER) -#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER) -#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val) -#define pTIMER4_PERIOD ((uint32_t volatile *)TIMER4_PERIOD) -#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD) -#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val) -#define pTIMER4_WIDTH ((uint32_t volatile *)TIMER4_WIDTH) -#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH) -#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val) -#define pTIMER5_CONFIG ((uint16_t volatile *)TIMER5_CONFIG) -#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG) -#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val) -#define pTIMER5_COUNTER ((uint32_t volatile *)TIMER5_COUNTER) -#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER) -#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val) -#define pTIMER5_PERIOD ((uint32_t volatile *)TIMER5_PERIOD) -#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD) -#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val) -#define pTIMER5_WIDTH ((uint32_t volatile *)TIMER5_WIDTH) -#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH) -#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val) -#define pTIMER6_CONFIG ((uint16_t volatile *)TIMER6_CONFIG) -#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG) -#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val) -#define pTIMER6_COUNTER ((uint32_t volatile *)TIMER6_COUNTER) -#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER) -#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val) -#define pTIMER6_PERIOD ((uint32_t volatile *)TIMER6_PERIOD) -#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD) -#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val) -#define pTIMER6_WIDTH ((uint32_t volatile *)TIMER6_WIDTH) -#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH) -#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val) -#define pTIMER7_CONFIG ((uint16_t volatile *)TIMER7_CONFIG) -#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG) -#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val) -#define pTIMER7_COUNTER ((uint32_t volatile *)TIMER7_COUNTER) -#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER) -#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val) -#define pTIMER7_PERIOD ((uint32_t volatile *)TIMER7_PERIOD) -#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD) -#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val) -#define pTIMER7_WIDTH ((uint32_t volatile *)TIMER7_WIDTH) -#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH) -#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val) -#define pTIMER8_CONFIG ((uint16_t volatile *)TIMER8_CONFIG) -#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) -#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) -#define pTIMER8_COUNTER ((uint32_t volatile *)TIMER8_COUNTER) -#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) -#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) -#define pTIMER8_PERIOD ((uint32_t volatile *)TIMER8_PERIOD) -#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) -#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) -#define pTIMER8_WIDTH ((uint32_t volatile *)TIMER8_WIDTH) -#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) -#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) -#define pTIMER9_CONFIG ((uint16_t volatile *)TIMER9_CONFIG) -#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) -#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) -#define pTIMER9_COUNTER ((uint32_t volatile *)TIMER9_COUNTER) -#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) -#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) -#define pTIMER9_PERIOD ((uint32_t volatile *)TIMER9_PERIOD) -#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) -#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) -#define pTIMER9_WIDTH ((uint32_t volatile *)TIMER9_WIDTH) -#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) -#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) -#define pTIMER10_CONFIG ((uint16_t volatile *)TIMER10_CONFIG) -#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) -#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) -#define pTIMER10_COUNTER ((uint32_t volatile *)TIMER10_COUNTER) -#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) -#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) -#define pTIMER10_PERIOD ((uint32_t volatile *)TIMER10_PERIOD) -#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) -#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) -#define pTIMER10_WIDTH ((uint32_t volatile *)TIMER10_WIDTH) -#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) -#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) -#define pTIMER11_CONFIG ((uint16_t volatile *)TIMER11_CONFIG) -#define bfin_read_TIMER11_CONFIG() bfin_read16(TIMER11_CONFIG) -#define bfin_write_TIMER11_CONFIG(val) bfin_write16(TIMER11_CONFIG, val) -#define pTIMER11_COUNTER ((uint32_t volatile *)TIMER11_COUNTER) -#define bfin_read_TIMER11_COUNTER() bfin_read32(TIMER11_COUNTER) -#define bfin_write_TIMER11_COUNTER(val) bfin_write32(TIMER11_COUNTER, val) -#define pTIMER11_PERIOD ((uint32_t volatile *)TIMER11_PERIOD) -#define bfin_read_TIMER11_PERIOD() bfin_read32(TIMER11_PERIOD) -#define bfin_write_TIMER11_PERIOD(val) bfin_write32(TIMER11_PERIOD, val) -#define pTIMER11_WIDTH ((uint32_t volatile *)TIMER11_WIDTH) -#define bfin_read_TIMER11_WIDTH() bfin_read32(TIMER11_WIDTH) -#define bfin_write_TIMER11_WIDTH(val) bfin_write32(TIMER11_WIDTH, val) -#define pTMRS4_ENABLE ((uint32_t volatile *)TMRS4_ENABLE) -#define bfin_read_TMRS4_ENABLE() bfin_read32(TMRS4_ENABLE) -#define bfin_write_TMRS4_ENABLE(val) bfin_write32(TMRS4_ENABLE, val) -#define pTMRS4_DISABLE ((uint32_t volatile *)TMRS4_DISABLE) -#define bfin_read_TMRS4_DISABLE() bfin_read32(TMRS4_DISABLE) -#define bfin_write_TMRS4_DISABLE(val) bfin_write32(TMRS4_DISABLE, val) -#define pTMRS4_STATUS ((uint32_t volatile *)TMRS4_STATUS) -#define bfin_read_TMRS4_STATUS() bfin_read32(TMRS4_STATUS) -#define bfin_write_TMRS4_STATUS(val) bfin_write32(TMRS4_STATUS, val) -#define pTMRS8_ENABLE ((uint32_t volatile *)TMRS8_ENABLE) -#define bfin_read_TMRS8_ENABLE() bfin_read32(TMRS8_ENABLE) -#define bfin_write_TMRS8_ENABLE(val) bfin_write32(TMRS8_ENABLE, val) -#define pTMRS8_DISABLE ((uint32_t volatile *)TMRS8_DISABLE) -#define bfin_read_TMRS8_DISABLE() bfin_read32(TMRS8_DISABLE) -#define bfin_write_TMRS8_DISABLE(val) bfin_write32(TMRS8_DISABLE, val) -#define pTMRS8_STATUS ((uint32_t volatile *)TMRS8_STATUS) -#define bfin_read_TMRS8_STATUS() bfin_read32(TMRS8_STATUS) -#define bfin_write_TMRS8_STATUS(val) bfin_write32(TMRS8_STATUS, val) -#define pFIO0_FLAG_D ((uint16_t volatile *)FIO0_FLAG_D) -#define bfin_read_FIO0_FLAG_D() bfin_read16(FIO0_FLAG_D) -#define bfin_write_FIO0_FLAG_D(val) bfin_write16(FIO0_FLAG_D, val) -#define pFIO0_FLAG_C ((uint16_t volatile *)FIO0_FLAG_C) -#define bfin_read_FIO0_FLAG_C() bfin_read16(FIO0_FLAG_C) -#define bfin_write_FIO0_FLAG_C(val) bfin_write16(FIO0_FLAG_C, val) -#define pFIO0_FLAG_S ((uint16_t volatile *)FIO0_FLAG_S) -#define bfin_read_FIO0_FLAG_S() bfin_read16(FIO0_FLAG_S) -#define bfin_write_FIO0_FLAG_S(val) bfin_write16(FIO0_FLAG_S, val) -#define pFIO0_FLAG_T ((uint16_t volatile *)FIO0_FLAG_T) -#define bfin_read_FIO0_FLAG_T() bfin_read16(FIO0_FLAG_T) -#define bfin_write_FIO0_FLAG_T(val) bfin_write16(FIO0_FLAG_T, val) -#define pFIO0_MASKA_D ((uint16_t volatile *)FIO0_MASKA_D) -#define bfin_read_FIO0_MASKA_D() bfin_read16(FIO0_MASKA_D) -#define bfin_write_FIO0_MASKA_D(val) bfin_write16(FIO0_MASKA_D, val) -#define pFIO0_MASKA_C ((uint16_t volatile *)FIO0_MASKA_C) -#define bfin_read_FIO0_MASKA_C() bfin_read16(FIO0_MASKA_C) -#define bfin_write_FIO0_MASKA_C(val) bfin_write16(FIO0_MASKA_C, val) -#define pFIO0_MASKA_S ((uint16_t volatile *)FIO0_MASKA_S) -#define bfin_read_FIO0_MASKA_S() bfin_read16(FIO0_MASKA_S) -#define bfin_write_FIO0_MASKA_S(val) bfin_write16(FIO0_MASKA_S, val) -#define pFIO0_MASKA_T ((uint16_t volatile *)FIO0_MASKA_T) -#define bfin_read_FIO0_MASKA_T() bfin_read16(FIO0_MASKA_T) -#define bfin_write_FIO0_MASKA_T(val) bfin_write16(FIO0_MASKA_T, val) -#define pFIO0_MASKB_D ((uint16_t volatile *)FIO0_MASKB_D) -#define bfin_read_FIO0_MASKB_D() bfin_read16(FIO0_MASKB_D) -#define bfin_write_FIO0_MASKB_D(val) bfin_write16(FIO0_MASKB_D, val) -#define pFIO0_MASKB_C ((uint16_t volatile *)FIO0_MASKB_C) -#define bfin_read_FIO0_MASKB_C() bfin_read16(FIO0_MASKB_C) -#define bfin_write_FIO0_MASKB_C(val) bfin_write16(FIO0_MASKB_C, val) -#define pFIO0_MASKB_S ((uint16_t volatile *)FIO0_MASKB_S) -#define bfin_read_FIO0_MASKB_S() bfin_read16(FIO0_MASKB_S) -#define bfin_write_FIO0_MASKB_S(val) bfin_write16(FIO0_MASKB_S, val) -#define pFIO0_MASKB_T ((uint16_t volatile *)FIO0_MASKB_T) -#define bfin_read_FIO0_MASKB_T() bfin_read16(FIO0_MASKB_T) -#define bfin_write_FIO0_MASKB_T(val) bfin_write16(FIO0_MASKB_T, val) -#define pFIO0_DIR ((uint16_t volatile *)FIO0_DIR) -#define bfin_read_FIO0_DIR() bfin_read16(FIO0_DIR) -#define bfin_write_FIO0_DIR(val) bfin_write16(FIO0_DIR, val) -#define pFIO0_POLAR ((uint16_t volatile *)FIO0_POLAR) -#define bfin_read_FIO0_POLAR() bfin_read16(FIO0_POLAR) -#define bfin_write_FIO0_POLAR(val) bfin_write16(FIO0_POLAR, val) -#define pFIO0_EDGE ((uint16_t volatile *)FIO0_EDGE) -#define bfin_read_FIO0_EDGE() bfin_read16(FIO0_EDGE) -#define bfin_write_FIO0_EDGE(val) bfin_write16(FIO0_EDGE, val) -#define pFIO0_BOTH ((uint16_t volatile *)FIO0_BOTH) -#define bfin_read_FIO0_BOTH() bfin_read16(FIO0_BOTH) -#define bfin_write_FIO0_BOTH(val) bfin_write16(FIO0_BOTH, val) -#define pFIO0_INEN ((uint16_t volatile *)FIO0_INEN) -#define bfin_read_FIO0_INEN() bfin_read16(FIO0_INEN) -#define bfin_write_FIO0_INEN(val) bfin_write16(FIO0_INEN, val) -#define pFIO1_FLAG_D ((uint16_t volatile *)FIO1_FLAG_D) -#define bfin_read_FIO1_FLAG_D() bfin_read16(FIO1_FLAG_D) -#define bfin_write_FIO1_FLAG_D(val) bfin_write16(FIO1_FLAG_D, val) -#define pFIO1_FLAG_C ((uint16_t volatile *)FIO1_FLAG_C) -#define bfin_read_FIO1_FLAG_C() bfin_read16(FIO1_FLAG_C) -#define bfin_write_FIO1_FLAG_C(val) bfin_write16(FIO1_FLAG_C, val) -#define pFIO1_FLAG_S ((uint16_t volatile *)FIO1_FLAG_S) -#define bfin_read_FIO1_FLAG_S() bfin_read16(FIO1_FLAG_S) -#define bfin_write_FIO1_FLAG_S(val) bfin_write16(FIO1_FLAG_S, val) -#define pFIO1_FLAG_T ((uint16_t volatile *)FIO1_FLAG_T) -#define bfin_read_FIO1_FLAG_T() bfin_read16(FIO1_FLAG_T) -#define bfin_write_FIO1_FLAG_T(val) bfin_write16(FIO1_FLAG_T, val) -#define pFIO1_MASKA_D ((uint16_t volatile *)FIO1_MASKA_D) -#define bfin_read_FIO1_MASKA_D() bfin_read16(FIO1_MASKA_D) -#define bfin_write_FIO1_MASKA_D(val) bfin_write16(FIO1_MASKA_D, val) -#define pFIO1_MASKA_C ((uint16_t volatile *)FIO1_MASKA_C) -#define bfin_read_FIO1_MASKA_C() bfin_read16(FIO1_MASKA_C) -#define bfin_write_FIO1_MASKA_C(val) bfin_write16(FIO1_MASKA_C, val) -#define pFIO1_MASKA_S ((uint16_t volatile *)FIO1_MASKA_S) -#define bfin_read_FIO1_MASKA_S() bfin_read16(FIO1_MASKA_S) -#define bfin_write_FIO1_MASKA_S(val) bfin_write16(FIO1_MASKA_S, val) -#define pFIO1_MASKA_T ((uint16_t volatile *)FIO1_MASKA_T) -#define bfin_read_FIO1_MASKA_T() bfin_read16(FIO1_MASKA_T) -#define bfin_write_FIO1_MASKA_T(val) bfin_write16(FIO1_MASKA_T, val) -#define pFIO1_MASKB_D ((uint16_t volatile *)FIO1_MASKB_D) -#define bfin_read_FIO1_MASKB_D() bfin_read16(FIO1_MASKB_D) -#define bfin_write_FIO1_MASKB_D(val) bfin_write16(FIO1_MASKB_D, val) -#define pFIO1_MASKB_C ((uint16_t volatile *)FIO1_MASKB_C) -#define bfin_read_FIO1_MASKB_C() bfin_read16(FIO1_MASKB_C) -#define bfin_write_FIO1_MASKB_C(val) bfin_write16(FIO1_MASKB_C, val) -#define pFIO1_MASKB_S ((uint16_t volatile *)FIO1_MASKB_S) -#define bfin_read_FIO1_MASKB_S() bfin_read16(FIO1_MASKB_S) -#define bfin_write_FIO1_MASKB_S(val) bfin_write16(FIO1_MASKB_S, val) -#define pFIO1_MASKB_T ((uint16_t volatile *)FIO1_MASKB_T) -#define bfin_read_FIO1_MASKB_T() bfin_read16(FIO1_MASKB_T) -#define bfin_write_FIO1_MASKB_T(val) bfin_write16(FIO1_MASKB_T, val) -#define pFIO1_DIR ((uint16_t volatile *)FIO1_DIR) -#define bfin_read_FIO1_DIR() bfin_read16(FIO1_DIR) -#define bfin_write_FIO1_DIR(val) bfin_write16(FIO1_DIR, val) -#define pFIO1_POLAR ((uint16_t volatile *)FIO1_POLAR) -#define bfin_read_FIO1_POLAR() bfin_read16(FIO1_POLAR) -#define bfin_write_FIO1_POLAR(val) bfin_write16(FIO1_POLAR, val) -#define pFIO1_EDGE ((uint16_t volatile *)FIO1_EDGE) -#define bfin_read_FIO1_EDGE() bfin_read16(FIO1_EDGE) -#define bfin_write_FIO1_EDGE(val) bfin_write16(FIO1_EDGE, val) -#define pFIO1_BOTH ((uint16_t volatile *)FIO1_BOTH) -#define bfin_read_FIO1_BOTH() bfin_read16(FIO1_BOTH) -#define bfin_write_FIO1_BOTH(val) bfin_write16(FIO1_BOTH, val) -#define pFIO1_INEN ((uint16_t volatile *)FIO1_INEN) -#define bfin_read_FIO1_INEN() bfin_read16(FIO1_INEN) -#define bfin_write_FIO1_INEN(val) bfin_write16(FIO1_INEN, val) -#define pFIO2_FLAG_D ((uint16_t volatile *)FIO2_FLAG_D) -#define bfin_read_FIO2_FLAG_D() bfin_read16(FIO2_FLAG_D) -#define bfin_write_FIO2_FLAG_D(val) bfin_write16(FIO2_FLAG_D, val) -#define pFIO2_FLAG_C ((uint16_t volatile *)FIO2_FLAG_C) -#define bfin_read_FIO2_FLAG_C() bfin_read16(FIO2_FLAG_C) -#define bfin_write_FIO2_FLAG_C(val) bfin_write16(FIO2_FLAG_C, val) -#define pFIO2_FLAG_S ((uint16_t volatile *)FIO2_FLAG_S) -#define bfin_read_FIO2_FLAG_S() bfin_read16(FIO2_FLAG_S) -#define bfin_write_FIO2_FLAG_S(val) bfin_write16(FIO2_FLAG_S, val) -#define pFIO2_FLAG_T ((uint16_t volatile *)FIO2_FLAG_T) -#define bfin_read_FIO2_FLAG_T() bfin_read16(FIO2_FLAG_T) -#define bfin_write_FIO2_FLAG_T(val) bfin_write16(FIO2_FLAG_T, val) -#define pFIO2_MASKA_D ((uint16_t volatile *)FIO2_MASKA_D) -#define bfin_read_FIO2_MASKA_D() bfin_read16(FIO2_MASKA_D) -#define bfin_write_FIO2_MASKA_D(val) bfin_write16(FIO2_MASKA_D, val) -#define pFIO2_MASKA_C ((uint16_t volatile *)FIO2_MASKA_C) -#define bfin_read_FIO2_MASKA_C() bfin_read16(FIO2_MASKA_C) -#define bfin_write_FIO2_MASKA_C(val) bfin_write16(FIO2_MASKA_C, val) -#define pFIO2_MASKA_S ((uint16_t volatile *)FIO2_MASKA_S) -#define bfin_read_FIO2_MASKA_S() bfin_read16(FIO2_MASKA_S) -#define bfin_write_FIO2_MASKA_S(val) bfin_write16(FIO2_MASKA_S, val) -#define pFIO2_MASKA_T ((uint16_t volatile *)FIO2_MASKA_T) -#define bfin_read_FIO2_MASKA_T() bfin_read16(FIO2_MASKA_T) -#define bfin_write_FIO2_MASKA_T(val) bfin_write16(FIO2_MASKA_T, val) -#define pFIO2_MASKB_D ((uint16_t volatile *)FIO2_MASKB_D) -#define bfin_read_FIO2_MASKB_D() bfin_read16(FIO2_MASKB_D) -#define bfin_write_FIO2_MASKB_D(val) bfin_write16(FIO2_MASKB_D, val) -#define pFIO2_MASKB_C ((uint16_t volatile *)FIO2_MASKB_C) -#define bfin_read_FIO2_MASKB_C() bfin_read16(FIO2_MASKB_C) -#define bfin_write_FIO2_MASKB_C(val) bfin_write16(FIO2_MASKB_C, val) -#define pFIO2_MASKB_S ((uint16_t volatile *)FIO2_MASKB_S) -#define bfin_read_FIO2_MASKB_S() bfin_read16(FIO2_MASKB_S) -#define bfin_write_FIO2_MASKB_S(val) bfin_write16(FIO2_MASKB_S, val) -#define pFIO2_MASKB_T ((uint16_t volatile *)FIO2_MASKB_T) -#define bfin_read_FIO2_MASKB_T() bfin_read16(FIO2_MASKB_T) -#define bfin_write_FIO2_MASKB_T(val) bfin_write16(FIO2_MASKB_T, val) -#define pFIO2_DIR ((uint16_t volatile *)FIO2_DIR) -#define bfin_read_FIO2_DIR() bfin_read16(FIO2_DIR) -#define bfin_write_FIO2_DIR(val) bfin_write16(FIO2_DIR, val) -#define pFIO2_POLAR ((uint16_t volatile *)FIO2_POLAR) -#define bfin_read_FIO2_POLAR() bfin_read16(FIO2_POLAR) -#define bfin_write_FIO2_POLAR(val) bfin_write16(FIO2_POLAR, val) -#define pFIO2_EDGE ((uint16_t volatile *)FIO2_EDGE) -#define bfin_read_FIO2_EDGE() bfin_read16(FIO2_EDGE) -#define bfin_write_FIO2_EDGE(val) bfin_write16(FIO2_EDGE, val) -#define pFIO2_BOTH ((uint16_t volatile *)FIO2_BOTH) -#define bfin_read_FIO2_BOTH() bfin_read16(FIO2_BOTH) -#define bfin_write_FIO2_BOTH(val) bfin_write16(FIO2_BOTH, val) -#define pFIO2_INEN ((uint16_t volatile *)FIO2_INEN) -#define bfin_read_FIO2_INEN() bfin_read16(FIO2_INEN) -#define bfin_write_FIO2_INEN(val) bfin_write16(FIO2_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) -#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT0_MTCS0 ((uint32_t volatile *)SPORT0_MTCS0) -#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) -#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) -#define pSPORT0_MTCS1 ((uint32_t volatile *)SPORT0_MTCS1) -#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) -#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) -#define pSPORT0_MTCS2 ((uint32_t volatile *)SPORT0_MTCS2) -#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) -#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) -#define pSPORT0_MTCS3 ((uint32_t volatile *)SPORT0_MTCS3) -#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) -#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) -#define pSPORT0_MRCS0 ((uint32_t volatile *)SPORT0_MRCS0) -#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) -#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) -#define pSPORT0_MRCS1 ((uint32_t volatile *)SPORT0_MRCS1) -#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) -#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) -#define pSPORT0_MRCS2 ((uint32_t volatile *)SPORT0_MRCS2) -#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) -#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) -#define pSPORT0_MRCS3 ((uint32_t volatile *)SPORT0_MRCS3) -#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) -#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pSPORT1_MTCS0 ((uint32_t volatile *)SPORT1_MTCS0) -#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0) -#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val) -#define pSPORT1_MTCS1 ((uint32_t volatile *)SPORT1_MTCS1) -#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1) -#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val) -#define pSPORT1_MTCS2 ((uint32_t volatile *)SPORT1_MTCS2) -#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2) -#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val) -#define pSPORT1_MTCS3 ((uint32_t volatile *)SPORT1_MTCS3) -#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3) -#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val) -#define pSPORT1_MRCS0 ((uint32_t volatile *)SPORT1_MRCS0) -#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0) -#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val) -#define pSPORT1_MRCS1 ((uint32_t volatile *)SPORT1_MRCS1) -#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1) -#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val) -#define pSPORT1_MRCS2 ((uint32_t volatile *)SPORT1_MRCS2) -#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2) -#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val) -#define pSPORT1_MRCS3 ((uint32_t volatile *)SPORT1_MRCS3) -#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3) -#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val) -#define pEVT0 ((void * volatile *)EVT0) -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_DUAL_CORE_extended__ */ diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h deleted file mode 100644 index b4857c3b02..0000000000 --- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-DUAL-CORE-extended_def.h +++ /dev/null @@ -1,670 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ -#define __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ - -#define PLL_CTL 0xFFC00000 -#define PLL_DIV 0xFFC00004 -#define VR_CTL 0xFFC00008 -#define PLL_STAT 0xFFC0000C -#define PLL_LOCKCNT 0xFFC00010 -#define CHIPID 0xFFC00014 -#define SPI_CTL 0xFFC00500 -#define SPI_FLG 0xFFC00504 -#define SPI_STAT 0xFFC00508 -#define SPI_TDBR 0xFFC0050C -#define SPI_RDBR 0xFFC00510 -#define SPI_BAUD 0xFFC00514 -#define SPI_SHADOW 0xFFC00518 -#define WDOGA_CTL 0xFFC00200 -#define WDOGA_CNT 0xFFC00204 -#define WDOGA_STAT 0xFFC00208 -#define WDOGB_CTL 0xFFC01200 -#define WDOGB_CNT 0xFFC01204 -#define WDOGB_STAT 0xFFC01208 -#define DMA1_TC_PER 0xFFC01B0C /* Traffic Control Periods */ -#define DMA1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ -#define DMA1_0_CONFIG 0xFFC01C08 -#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 -#define DMA1_0_START_ADDR 0xFFC01C04 -#define DMA1_0_X_COUNT 0xFFC01C10 -#define DMA1_0_Y_COUNT 0xFFC01C18 -#define DMA1_0_X_MODIFY 0xFFC01C14 -#define DMA1_0_Y_MODIFY 0xFFC01C1C -#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 -#define DMA1_0_CURR_ADDR 0xFFC01C24 -#define DMA1_0_CURR_X_COUNT 0xFFC01C30 -#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 -#define DMA1_0_IRQ_STATUS 0xFFC01C28 -#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C -#define DMA1_1_CONFIG 0xFFC01C48 -#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 -#define DMA1_1_START_ADDR 0xFFC01C44 -#define DMA1_1_X_COUNT 0xFFC01C50 -#define DMA1_1_Y_COUNT 0xFFC01C58 -#define DMA1_1_X_MODIFY 0xFFC01C54 -#define DMA1_1_Y_MODIFY 0xFFC01C5C -#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 -#define DMA1_1_CURR_ADDR 0xFFC01C64 -#define DMA1_1_CURR_X_COUNT 0xFFC01C70 -#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 -#define DMA1_1_IRQ_STATUS 0xFFC01C68 -#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C -#define DMA1_2_CONFIG 0xFFC01C88 -#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 -#define DMA1_2_START_ADDR 0xFFC01C84 -#define DMA1_2_X_COUNT 0xFFC01C90 -#define DMA1_2_Y_COUNT 0xFFC01C98 -#define DMA1_2_X_MODIFY 0xFFC01C94 -#define DMA1_2_Y_MODIFY 0xFFC01C9C -#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 -#define DMA1_2_CURR_ADDR 0xFFC01CA4 -#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 -#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 -#define DMA1_2_IRQ_STATUS 0xFFC01CA8 -#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC -#define DMA1_3_CONFIG 0xFFC01CC8 -#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 -#define DMA1_3_START_ADDR 0xFFC01CC4 -#define DMA1_3_X_COUNT 0xFFC01CD0 -#define DMA1_3_Y_COUNT 0xFFC01CD8 -#define DMA1_3_X_MODIFY 0xFFC01CD4 -#define DMA1_3_Y_MODIFY 0xFFC01CDC -#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 -#define DMA1_3_CURR_ADDR 0xFFC01CE4 -#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 -#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 -#define DMA1_3_IRQ_STATUS 0xFFC01CE8 -#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC -#define DMA1_4_CONFIG 0xFFC01D08 -#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 -#define DMA1_4_START_ADDR 0xFFC01D04 -#define DMA1_4_X_COUNT 0xFFC01D10 -#define DMA1_4_Y_COUNT 0xFFC01D18 -#define DMA1_4_X_MODIFY 0xFFC01D14 -#define DMA1_4_Y_MODIFY 0xFFC01D1C -#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 -#define DMA1_4_CURR_ADDR 0xFFC01D24 -#define DMA1_4_CURR_X_COUNT 0xFFC01D30 -#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 -#define DMA1_4_IRQ_STATUS 0xFFC01D28 -#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C -#define DMA1_5_CONFIG 0xFFC01D48 -#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 -#define DMA1_5_START_ADDR 0xFFC01D44 -#define DMA1_5_X_COUNT 0xFFC01D50 -#define DMA1_5_Y_COUNT 0xFFC01D58 -#define DMA1_5_X_MODIFY 0xFFC01D54 -#define DMA1_5_Y_MODIFY 0xFFC01D5C -#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 -#define DMA1_5_CURR_ADDR 0xFFC01D64 -#define DMA1_5_CURR_X_COUNT 0xFFC01D70 -#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 -#define DMA1_5_IRQ_STATUS 0xFFC01D68 -#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C -#define DMA1_6_CONFIG 0xFFC01D88 -#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 -#define DMA1_6_START_ADDR 0xFFC01D84 -#define DMA1_6_X_COUNT 0xFFC01D90 -#define DMA1_6_Y_COUNT 0xFFC01D98 -#define DMA1_6_X_MODIFY 0xFFC01D94 -#define DMA1_6_Y_MODIFY 0xFFC01D9C -#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 -#define DMA1_6_CURR_ADDR 0xFFC01DA4 -#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 -#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 -#define DMA1_6_IRQ_STATUS 0xFFC01DA8 -#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC -#define DMA1_7_CONFIG 0xFFC01DC8 -#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 -#define DMA1_7_START_ADDR 0xFFC01DC4 -#define DMA1_7_X_COUNT 0xFFC01DD0 -#define DMA1_7_Y_COUNT 0xFFC01DD8 -#define DMA1_7_X_MODIFY 0xFFC01DD4 -#define DMA1_7_Y_MODIFY 0xFFC01DDC -#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 -#define DMA1_7_CURR_ADDR 0xFFC01DE4 -#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 -#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 -#define DMA1_7_IRQ_STATUS 0xFFC01DE8 -#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC -#define DMA1_8_CONFIG 0xFFC01E08 -#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 -#define DMA1_8_START_ADDR 0xFFC01E04 -#define DMA1_8_X_COUNT 0xFFC01E10 -#define DMA1_8_Y_COUNT 0xFFC01E18 -#define DMA1_8_X_MODIFY 0xFFC01E14 -#define DMA1_8_Y_MODIFY 0xFFC01E1C -#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 -#define DMA1_8_CURR_ADDR 0xFFC01E24 -#define DMA1_8_CURR_X_COUNT 0xFFC01E30 -#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 -#define DMA1_8_IRQ_STATUS 0xFFC01E28 -#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C -#define DMA1_9_CONFIG 0xFFC01E48 -#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 -#define DMA1_9_START_ADDR 0xFFC01E44 -#define DMA1_9_X_COUNT 0xFFC01E50 -#define DMA1_9_Y_COUNT 0xFFC01E58 -#define DMA1_9_X_MODIFY 0xFFC01E54 -#define DMA1_9_Y_MODIFY 0xFFC01E5C -#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 -#define DMA1_9_CURR_ADDR 0xFFC01E64 -#define DMA1_9_CURR_X_COUNT 0xFFC01E70 -#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 -#define DMA1_9_IRQ_STATUS 0xFFC01E68 -#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C -#define DMA1_10_CONFIG 0xFFC01E88 -#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 -#define DMA1_10_START_ADDR 0xFFC01E84 -#define DMA1_10_X_COUNT 0xFFC01E90 -#define DMA1_10_Y_COUNT 0xFFC01E98 -#define DMA1_10_X_MODIFY 0xFFC01E94 -#define DMA1_10_Y_MODIFY 0xFFC01E9C -#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 -#define DMA1_10_CURR_ADDR 0xFFC01EA4 -#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 -#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 -#define DMA1_10_IRQ_STATUS 0xFFC01EA8 -#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC -#define DMA1_11_CONFIG 0xFFC01EC8 -#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 -#define DMA1_11_START_ADDR 0xFFC01EC4 -#define DMA1_11_X_COUNT 0xFFC01ED0 -#define DMA1_11_Y_COUNT 0xFFC01ED8 -#define DMA1_11_X_MODIFY 0xFFC01ED4 -#define DMA1_11_Y_MODIFY 0xFFC01EDC -#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 -#define DMA1_11_CURR_ADDR 0xFFC01EE4 -#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 -#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 -#define DMA1_11_IRQ_STATUS 0xFFC01EE8 -#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC -#define DMA2_TC_PER 0xFFC00B0C -#define DMA2_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts */ -#define DMA2_0_CONFIG 0xFFC00C08 -#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 -#define DMA2_0_START_ADDR 0xFFC00C04 -#define DMA2_0_X_COUNT 0xFFC00C10 -#define DMA2_0_Y_COUNT 0xFFC00C18 -#define DMA2_0_X_MODIFY 0xFFC00C14 -#define DMA2_0_Y_MODIFY 0xFFC00C1C -#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 -#define DMA2_0_CURR_ADDR 0xFFC00C24 -#define DMA2_0_CURR_X_COUNT 0xFFC00C30 -#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 -#define DMA2_0_IRQ_STATUS 0xFFC00C28 -#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C -#define DMA2_1_CONFIG 0xFFC00C48 -#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 -#define DMA2_1_START_ADDR 0xFFC00C44 -#define DMA2_1_X_COUNT 0xFFC00C50 -#define DMA2_1_Y_COUNT 0xFFC00C58 -#define DMA2_1_X_MODIFY 0xFFC00C54 -#define DMA2_1_Y_MODIFY 0xFFC00C5C -#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 -#define DMA2_1_CURR_ADDR 0xFFC00C64 -#define DMA2_1_CURR_X_COUNT 0xFFC00C70 -#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 -#define DMA2_1_IRQ_STATUS 0xFFC00C68 -#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C -#define DMA2_2_CONFIG 0xFFC00C88 -#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 -#define DMA2_2_START_ADDR 0xFFC00C84 -#define DMA2_2_X_COUNT 0xFFC00C90 -#define DMA2_2_Y_COUNT 0xFFC00C98 -#define DMA2_2_X_MODIFY 0xFFC00C94 -#define DMA2_2_Y_MODIFY 0xFFC00C9C -#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 -#define DMA2_2_CURR_ADDR 0xFFC00CA4 -#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 -#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 -#define DMA2_2_IRQ_STATUS 0xFFC00CA8 -#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC -#define DMA2_3_CONFIG 0xFFC00CC8 -#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 -#define DMA2_3_START_ADDR 0xFFC00CC4 -#define DMA2_3_X_COUNT 0xFFC00CD0 -#define DMA2_3_Y_COUNT 0xFFC00CD8 -#define DMA2_3_X_MODIFY 0xFFC00CD4 -#define DMA2_3_Y_MODIFY 0xFFC00CDC -#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 -#define DMA2_3_CURR_ADDR 0xFFC00CE4 -#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 -#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 -#define DMA2_3_IRQ_STATUS 0xFFC00CE8 -#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC -#define DMA2_4_CONFIG 0xFFC00D08 -#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 -#define DMA2_4_START_ADDR 0xFFC00D04 -#define DMA2_4_X_COUNT 0xFFC00D10 -#define DMA2_4_Y_COUNT 0xFFC00D18 -#define DMA2_4_X_MODIFY 0xFFC00D14 -#define DMA2_4_Y_MODIFY 0xFFC00D1C -#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 -#define DMA2_4_CURR_ADDR 0xFFC00D24 -#define DMA2_4_CURR_X_COUNT 0xFFC00D30 -#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 -#define DMA2_4_IRQ_STATUS 0xFFC00D28 -#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C -#define DMA2_5_CONFIG 0xFFC00D48 -#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 -#define DMA2_5_START_ADDR 0xFFC00D44 -#define DMA2_5_X_COUNT 0xFFC00D50 -#define DMA2_5_Y_COUNT 0xFFC00D58 -#define DMA2_5_X_MODIFY 0xFFC00D54 -#define DMA2_5_Y_MODIFY 0xFFC00D5C -#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 -#define DMA2_5_CURR_ADDR 0xFFC00D64 -#define DMA2_5_CURR_X_COUNT 0xFFC00D70 -#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 -#define DMA2_5_IRQ_STATUS 0xFFC00D68 -#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C -#define DMA2_6_CONFIG 0xFFC00D88 -#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 -#define DMA2_6_START_ADDR 0xFFC00D84 -#define DMA2_6_X_COUNT 0xFFC00D90 -#define DMA2_6_Y_COUNT 0xFFC00D98 -#define DMA2_6_X_MODIFY 0xFFC00D94 -#define DMA2_6_Y_MODIFY 0xFFC00D9C -#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 -#define DMA2_6_CURR_ADDR 0xFFC00DA4 -#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 -#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 -#define DMA2_6_IRQ_STATUS 0xFFC00DA8 -#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC -#define DMA2_7_CONFIG 0xFFC00DC8 -#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 -#define DMA2_7_START_ADDR 0xFFC00DC4 -#define DMA2_7_X_COUNT 0xFFC00DD0 -#define DMA2_7_Y_COUNT 0xFFC00DD8 -#define DMA2_7_X_MODIFY 0xFFC00DD4 -#define DMA2_7_Y_MODIFY 0xFFC00DDC -#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 -#define DMA2_7_CURR_ADDR 0xFFC00DE4 -#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 -#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 -#define DMA2_7_IRQ_STATUS 0xFFC00DE8 -#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC -#define DMA2_8_CONFIG 0xFFC00E08 -#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 -#define DMA2_8_START_ADDR 0xFFC00E04 -#define DMA2_8_X_COUNT 0xFFC00E10 -#define DMA2_8_Y_COUNT 0xFFC00E18 -#define DMA2_8_X_MODIFY 0xFFC00E14 -#define DMA2_8_Y_MODIFY 0xFFC00E1C -#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 -#define DMA2_8_CURR_ADDR 0xFFC00E24 -#define DMA2_8_CURR_X_COUNT 0xFFC00E30 -#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 -#define DMA2_8_IRQ_STATUS 0xFFC00E28 -#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C -#define DMA2_9_CONFIG 0xFFC00E48 -#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 -#define DMA2_9_START_ADDR 0xFFC00E44 -#define DMA2_9_X_COUNT 0xFFC00E50 -#define DMA2_9_Y_COUNT 0xFFC00E58 -#define DMA2_9_X_MODIFY 0xFFC00E54 -#define DMA2_9_Y_MODIFY 0xFFC00E5C -#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 -#define DMA2_9_CURR_ADDR 0xFFC00E64 -#define DMA2_9_CURR_X_COUNT 0xFFC00E70 -#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 -#define DMA2_9_IRQ_STATUS 0xFFC00E68 -#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C -#define DMA2_10_CONFIG 0xFFC00E88 -#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 -#define DMA2_10_START_ADDR 0xFFC00E84 -#define DMA2_10_X_COUNT 0xFFC00E90 -#define DMA2_10_Y_COUNT 0xFFC00E98 -#define DMA2_10_X_MODIFY 0xFFC00E94 -#define DMA2_10_Y_MODIFY 0xFFC00E9C -#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 -#define DMA2_10_CURR_ADDR 0xFFC00EA4 -#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 -#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 -#define DMA2_10_IRQ_STATUS 0xFFC00EA8 -#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC -#define DMA2_11_CONFIG 0xFFC00EC8 -#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 -#define DMA2_11_START_ADDR 0xFFC00EC4 -#define DMA2_11_X_COUNT 0xFFC00ED0 -#define DMA2_11_Y_COUNT 0xFFC00ED8 -#define DMA2_11_X_MODIFY 0xFFC00ED4 -#define DMA2_11_Y_MODIFY 0xFFC00EDC -#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 -#define DMA2_11_CURR_ADDR 0xFFC00EE4 -#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 -#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 -#define DMA2_11_IRQ_STATUS 0xFFC00EE8 -#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC -#define IMDMA_S0_CONFIG 0xFFC01848 -#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 -#define IMDMA_S0_START_ADDR 0xFFC01844 -#define IMDMA_S0_X_COUNT 0xFFC01850 -#define IMDMA_S0_Y_COUNT 0xFFC01858 -#define IMDMA_S0_X_MODIFY 0xFFC01854 -#define IMDMA_S0_Y_MODIFY 0xFFC0185C -#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 -#define IMDMA_S0_CURR_ADDR 0xFFC01864 -#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 -#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 -#define IMDMA_S0_IRQ_STATUS 0xFFC01868 -#define IMDMA_D0_CONFIG 0xFFC01808 -#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 -#define IMDMA_D0_START_ADDR 0xFFC01804 -#define IMDMA_D0_X_COUNT 0xFFC01810 -#define IMDMA_D0_Y_COUNT 0xFFC01818 -#define IMDMA_D0_X_MODIFY 0xFFC01814 -#define IMDMA_D0_Y_MODIFY 0xFFC0181C -#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 -#define IMDMA_D0_CURR_ADDR 0xFFC01824 -#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 -#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 -#define IMDMA_D0_IRQ_STATUS 0xFFC01828 -#define IMDMA_S1_CONFIG 0xFFC018C8 -#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 -#define IMDMA_S1_START_ADDR 0xFFC018C4 -#define IMDMA_S1_X_COUNT 0xFFC018D0 -#define IMDMA_S1_Y_COUNT 0xFFC018D8 -#define IMDMA_S1_X_MODIFY 0xFFC018D4 -#define IMDMA_S1_Y_MODIFY 0xFFC018DC -#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 -#define IMDMA_S1_CURR_ADDR 0xFFC018E4 -#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 -#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 -#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 -#define IMDMA_D1_CONFIG 0xFFC01888 -#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 -#define IMDMA_D1_START_ADDR 0xFFC01884 -#define IMDMA_D1_X_COUNT 0xFFC01890 -#define IMDMA_D1_Y_COUNT 0xFFC01898 -#define IMDMA_D1_X_MODIFY 0xFFC01894 -#define IMDMA_D1_Y_MODIFY 0xFFC0189C -#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 -#define IMDMA_D1_CURR_ADDR 0xFFC018A4 -#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 -#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 -#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 -#define MDMA1_S0_CONFIG 0xFFC01F48 -#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 -#define MDMA1_S0_START_ADDR 0xFFC01F44 -#define MDMA1_S0_X_COUNT 0xFFC01F50 -#define MDMA1_S0_Y_COUNT 0xFFC01F58 -#define MDMA1_S0_X_MODIFY 0xFFC01F54 -#define MDMA1_S0_Y_MODIFY 0xFFC01F5C -#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 -#define MDMA1_S0_CURR_ADDR 0xFFC01F64 -#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 -#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 -#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 -#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C -#define MDMA1_D0_CONFIG 0xFFC01F08 -#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 -#define MDMA1_D0_START_ADDR 0xFFC01F04 -#define MDMA1_D0_X_COUNT 0xFFC01F10 -#define MDMA1_D0_Y_COUNT 0xFFC01F18 -#define MDMA1_D0_X_MODIFY 0xFFC01F14 -#define MDMA1_D0_Y_MODIFY 0xFFC01F1C -#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 -#define MDMA1_D0_CURR_ADDR 0xFFC01F24 -#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 -#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 -#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 -#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C -#define MDMA1_S1_CONFIG 0xFFC01FC8 -#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 -#define MDMA1_S1_START_ADDR 0xFFC01FC4 -#define MDMA1_S1_X_COUNT 0xFFC01FD0 -#define MDMA1_S1_Y_COUNT 0xFFC01FD8 -#define MDMA1_S1_X_MODIFY 0xFFC01FD4 -#define MDMA1_S1_Y_MODIFY 0xFFC01FDC -#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 -#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 -#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 -#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 -#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 -#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC -#define MDMA1_D1_CONFIG 0xFFC01F88 -#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 -#define MDMA1_D1_START_ADDR 0xFFC01F84 -#define MDMA1_D1_X_COUNT 0xFFC01F90 -#define MDMA1_D1_Y_COUNT 0xFFC01F98 -#define MDMA1_D1_X_MODIFY 0xFFC01F94 -#define MDMA1_D1_Y_MODIFY 0xFFC01F9C -#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 -#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 -#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 -#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 -#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 -#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC -#define MDMA2_S0_CONFIG 0xFFC00F48 -#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 -#define MDMA2_S0_START_ADDR 0xFFC00F44 -#define MDMA2_S0_X_COUNT 0xFFC00F50 -#define MDMA2_S0_Y_COUNT 0xFFC00F58 -#define MDMA2_S0_X_MODIFY 0xFFC00F54 -#define MDMA2_S0_Y_MODIFY 0xFFC00F5C -#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 -#define MDMA2_S0_CURR_ADDR 0xFFC00F64 -#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 -#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 -#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 -#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C -#define MDMA2_D0_CONFIG 0xFFC00F08 -#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 -#define MDMA2_D0_START_ADDR 0xFFC00F04 -#define MDMA2_D0_X_COUNT 0xFFC00F10 -#define MDMA2_D0_Y_COUNT 0xFFC00F18 -#define MDMA2_D0_X_MODIFY 0xFFC00F14 -#define MDMA2_D0_Y_MODIFY 0xFFC00F1C -#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 -#define MDMA2_D0_CURR_ADDR 0xFFC00F24 -#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 -#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 -#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 -#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C -#define MDMA2_S1_CONFIG 0xFFC00FC8 -#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 -#define MDMA2_S1_START_ADDR 0xFFC00FC4 -#define MDMA2_S1_X_COUNT 0xFFC00FD0 -#define MDMA2_S1_Y_COUNT 0xFFC00FD8 -#define MDMA2_S1_X_MODIFY 0xFFC00FD4 -#define MDMA2_S1_Y_MODIFY 0xFFC00FDC -#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 -#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 -#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 -#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 -#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 -#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC -#define MDMA2_D1_CONFIG 0xFFC00F88 -#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 -#define MDMA2_D1_START_ADDR 0xFFC00F84 -#define MDMA2_D1_X_COUNT 0xFFC00F90 -#define MDMA2_D1_Y_COUNT 0xFFC00F98 -#define MDMA2_D1_X_MODIFY 0xFFC00F94 -#define MDMA2_D1_Y_MODIFY 0xFFC00F9C -#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 -#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 -#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 -#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 -#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 -#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC -#define TIMER0_CONFIG 0xFFC00600 -#define TIMER0_COUNTER 0xFFC00604 -#define TIMER0_PERIOD 0xFFC00608 -#define TIMER0_WIDTH 0xFFC0060C -#define TIMER1_CONFIG 0xFFC00610 -#define TIMER1_COUNTER 0xFFC00614 -#define TIMER1_PERIOD 0xFFC00618 -#define TIMER1_WIDTH 0xFFC0061C -#define TIMER2_CONFIG 0xFFC00620 -#define TIMER2_COUNTER 0xFFC00624 -#define TIMER2_PERIOD 0xFFC00628 -#define TIMER2_WIDTH 0xFFC0062C -#define TIMER3_CONFIG 0xFFC00630 -#define TIMER3_COUNTER 0xFFC00634 -#define TIMER3_PERIOD 0xFFC00638 -#define TIMER3_WIDTH 0xFFC0063C -#define TIMER4_CONFIG 0xFFC00640 -#define TIMER4_COUNTER 0xFFC00644 -#define TIMER4_PERIOD 0xFFC00648 -#define TIMER4_WIDTH 0xFFC0064C -#define TIMER5_CONFIG 0xFFC00650 -#define TIMER5_COUNTER 0xFFC00654 -#define TIMER5_PERIOD 0xFFC00658 -#define TIMER5_WIDTH 0xFFC0065C -#define TIMER6_CONFIG 0xFFC00660 -#define TIMER6_COUNTER 0xFFC00664 -#define TIMER6_PERIOD 0xFFC00668 -#define TIMER6_WIDTH 0xFFC0066C -#define TIMER7_CONFIG 0xFFC00670 -#define TIMER7_COUNTER 0xFFC00674 -#define TIMER7_PERIOD 0xFFC00678 -#define TIMER7_WIDTH 0xFFC0067C -#define TIMER8_CONFIG 0xFFC01600 -#define TIMER8_COUNTER 0xFFC01604 -#define TIMER8_PERIOD 0xFFC01608 -#define TIMER8_WIDTH 0xFFC0160C -#define TIMER9_CONFIG 0xFFC01610 -#define TIMER9_COUNTER 0xFFC01614 -#define TIMER9_PERIOD 0xFFC01618 -#define TIMER9_WIDTH 0xFFC0161C -#define TIMER10_CONFIG 0xFFC01620 -#define TIMER10_COUNTER 0xFFC01624 -#define TIMER10_PERIOD 0xFFC01628 -#define TIMER10_WIDTH 0xFFC0162C -#define TIMER11_CONFIG 0xFFC01630 -#define TIMER11_COUNTER 0xFFC01634 -#define TIMER11_PERIOD 0xFFC01638 -#define TIMER11_WIDTH 0xFFC0163C -#define TMRS4_ENABLE 0xFFC01640 -#define TMRS4_DISABLE 0xFFC01644 -#define TMRS4_STATUS 0xFFC01648 -#define TMRS8_ENABLE 0xFFC00680 -#define TMRS8_DISABLE 0xFFC00684 -#define TMRS8_STATUS 0xFFC00688 -#define FIO0_FLAG_D 0xFFC00700 -#define FIO0_FLAG_C 0xFFC00704 -#define FIO0_FLAG_S 0xFFC00708 -#define FIO0_FLAG_T 0xFFC0070C -#define FIO0_MASKA_D 0xFFC00710 -#define FIO0_MASKA_C 0xFFC00714 -#define FIO0_MASKA_S 0xFFC00718 -#define FIO0_MASKA_T 0xFFC0071C -#define FIO0_MASKB_D 0xFFC00720 -#define FIO0_MASKB_C 0xFFC00724 -#define FIO0_MASKB_S 0xFFC00728 -#define FIO0_MASKB_T 0xFFC0072C -#define FIO0_DIR 0xFFC00730 -#define FIO0_POLAR 0xFFC00734 -#define FIO0_EDGE 0xFFC00738 -#define FIO0_BOTH 0xFFC0073C -#define FIO0_INEN 0xFFC00740 -#define FIO1_FLAG_D 0xFFC01500 -#define FIO1_FLAG_C 0xFFC01504 -#define FIO1_FLAG_S 0xFFC01508 -#define FIO1_FLAG_T 0xFFC0150C -#define FIO1_MASKA_D 0xFFC01510 -#define FIO1_MASKA_C 0xFFC01514 -#define FIO1_MASKA_S 0xFFC01518 -#define FIO1_MASKA_T 0xFFC0151C -#define FIO1_MASKB_D 0xFFC01520 -#define FIO1_MASKB_C 0xFFC01524 -#define FIO1_MASKB_S 0xFFC01528 -#define FIO1_MASKB_T 0xFFC0152C -#define FIO1_DIR 0xFFC01530 -#define FIO1_POLAR 0xFFC01534 -#define FIO1_EDGE 0xFFC01538 -#define FIO1_BOTH 0xFFC0153C -#define FIO1_INEN 0xFFC01540 -#define FIO2_FLAG_D 0xFFC01700 -#define FIO2_FLAG_C 0xFFC01704 -#define FIO2_FLAG_S 0xFFC01708 -#define FIO2_FLAG_T 0xFFC0170C -#define FIO2_MASKA_D 0xFFC01710 -#define FIO2_MASKA_C 0xFFC01714 -#define FIO2_MASKA_S 0xFFC01718 -#define FIO2_MASKA_T 0xFFC0171C -#define FIO2_MASKB_D 0xFFC01720 -#define FIO2_MASKB_C 0xFFC01724 -#define FIO2_MASKB_S 0xFFC01728 -#define FIO2_MASKB_T 0xFFC0172C -#define FIO2_DIR 0xFFC01730 -#define FIO2_POLAR 0xFFC01734 -#define FIO2_EDGE 0xFFC01738 -#define FIO2_BOTH 0xFFC0173C -#define FIO2_INEN 0xFFC01740 -#define SPORT0_TCR1 0xFFC00800 -#define SPORT0_TCR2 0xFFC00804 -#define SPORT0_TCLKDIV 0xFFC00808 -#define SPORT0_TFSDIV 0xFFC0080C -#define SPORT0_TX 0xFFC00810 -#define SPORT0_RX 0xFFC00818 -#define SPORT0_RCR1 0xFFC00820 -#define SPORT0_RCR2 0xFFC00824 -#define SPORT0_RCLKDIV 0xFFC00828 -#define SPORT0_RFSDIV 0xFFC0082C -#define SPORT0_STAT 0xFFC00830 -#define SPORT0_CHNL 0xFFC00834 -#define SPORT0_MCMC1 0xFFC00838 -#define SPORT0_MCMC2 0xFFC0083C -#define SPORT0_MTCS0 0xFFC00840 -#define SPORT0_MTCS1 0xFFC00844 -#define SPORT0_MTCS2 0xFFC00848 -#define SPORT0_MTCS3 0xFFC0084C -#define SPORT0_MRCS0 0xFFC00850 -#define SPORT0_MRCS1 0xFFC00854 -#define SPORT0_MRCS2 0xFFC00858 -#define SPORT0_MRCS3 0xFFC0085C -#define SPORT1_TCR1 0xFFC00900 -#define SPORT1_TCR2 0xFFC00904 -#define SPORT1_TCLKDIV 0xFFC00908 -#define SPORT1_TFSDIV 0xFFC0090C -#define SPORT1_TX 0xFFC00910 -#define SPORT1_RX 0xFFC00918 -#define SPORT1_RCR1 0xFFC00920 -#define SPORT1_RCR2 0xFFC00924 -#define SPORT1_RCLKDIV 0xFFC00928 -#define SPORT1_RFSDIV 0xFFC0092C -#define SPORT1_STAT 0xFFC00930 -#define SPORT1_CHNL 0xFFC00934 -#define SPORT1_MCMC1 0xFFC00938 -#define SPORT1_MCMC2 0xFFC0093C -#define SPORT1_MTCS0 0xFFC00940 -#define SPORT1_MTCS1 0xFFC00944 -#define SPORT1_MTCS2 0xFFC00948 -#define SPORT1_MTCS3 0xFFC0094C -#define SPORT1_MRCS0 0xFFC00950 -#define SPORT1_MRCS1 0xFFC00954 -#define SPORT1_MRCS2 0xFFC00958 -#define SPORT1_MRCS3 0xFFC0095C -#define EVT0 0xFFE02000 -#define EVT1 0xFFE02004 -#define EVT2 0xFFE02008 -#define EVT3 0xFFE0200C -#define EVT4 0xFFE02010 -#define EVT5 0xFFE02014 -#define EVT6 0xFFE02018 -#define EVT7 0xFFE0201C -#define EVT8 0xFFE02020 -#define EVT9 0xFFE02024 -#define EVT10 0xFFE02028 -#define EVT11 0xFFE0202C -#define EVT12 0xFFE02030 -#define EVT13 0xFFE02034 -#define EVT14 0xFFE02038 -#define EVT15 0xFFE0203C -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 -#define TPERIOD 0xFFE03004 -#define TSCALE 0xFFE03008 -#define TCOUNT 0xFFE0300C - -#endif /* __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__ */ diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h index af17813db8..3acf94b0bf 100644 --- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h +++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_cdef.h @@ -6,68 +6,271 @@ #ifndef __BFIN_CDEF_ADSP_EDN_core__ #define __BFIN_CDEF_ADSP_EDN_core__ -#define pWPIACTL ((uint32_t volatile *)WPIACTL) +#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) +#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) +#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) +#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) +#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS) +#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val) +#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR) +#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val) +#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) +#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) +#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) +#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) +#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) +#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) +#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) +#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) +#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) +#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) +#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) +#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) +#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) +#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) +#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) +#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) +#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) +#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) +#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) +#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) +#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) +#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) +#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) +#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) +#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) +#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) +#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) +#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) +#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) +#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) +#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) +#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) +#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) +#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) +#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) +#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) +#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) +#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) +#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) +#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) +#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) +#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) +#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) +#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) +#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) +#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) +#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) +#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) +#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) +#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) +#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) +#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) +#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) +#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) +#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) +#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) +#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) +#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) +#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) +#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) +#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) +#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) +#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) +#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) +#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) +#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) +#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) +#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) +#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) +#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) + +#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) +#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) +#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) +#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) +#define bfin_read_ICPLB_FAULT_ADDR() bfin_readPTR(ICPLB_FAULT_ADDR) +#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val) +#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) +#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) +#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) +#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) +#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) +#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) +#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) +#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) +#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) +#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) +#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) +#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) +#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) +#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) +#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) +#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) +#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) +#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) +#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) +#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) +#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) +#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) +#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) +#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) +#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) +#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) +#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) +#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) +#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) +#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) +#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) +#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) +#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) +#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) +#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) +#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) +#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) +#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) +#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) +#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) +#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) +#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) +#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) +#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) +#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) +#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) +#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) +#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) +#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) +#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) +#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) +#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) +#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) +#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) +#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) +#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) +#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) +#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) +#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) +#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) +#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) +#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) +#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) +#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) +#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) +#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) +#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) +#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) +#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) +#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) + +#define bfin_read_EVT0() bfin_readPTR(EVT0) +#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) +#define bfin_read_EVT1() bfin_readPTR(EVT1) +#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) +#define bfin_read_EVT2() bfin_readPTR(EVT2) +#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) +#define bfin_read_EVT3() bfin_readPTR(EVT3) +#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) +#define bfin_read_EVT4() bfin_readPTR(EVT4) +#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) +#define bfin_read_EVT5() bfin_readPTR(EVT5) +#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) +#define bfin_read_EVT6() bfin_readPTR(EVT6) +#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) +#define bfin_read_EVT7() bfin_readPTR(EVT7) +#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) +#define bfin_read_EVT8() bfin_readPTR(EVT8) +#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) +#define bfin_read_EVT9() bfin_readPTR(EVT9) +#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) +#define bfin_read_EVT10() bfin_readPTR(EVT10) +#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) +#define bfin_read_EVT11() bfin_readPTR(EVT11) +#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) +#define bfin_read_EVT12() bfin_readPTR(EVT12) +#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) +#define bfin_read_EVT13() bfin_readPTR(EVT13) +#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) +#define bfin_read_EVT14() bfin_readPTR(EVT14) +#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) +#define bfin_read_EVT15() bfin_readPTR(EVT15) +#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) + +#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) +#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) +#define bfin_read_ILAT() bfin_read32(ILAT) +#define bfin_write_ILAT(val) bfin_write32(ILAT, val) +#define bfin_read_IMASK() bfin_read32(IMASK) +#define bfin_write_IMASK(val) bfin_write32(IMASK, val) +#define bfin_read_IPEND() bfin_read32(IPEND) +#define bfin_write_IPEND(val) bfin_write32(IPEND, val) +#define bfin_read_IPRIO() bfin_read32(IPRIO) +#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) + +#define bfin_read_TCNTL() bfin_read32(TCNTL) +#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) +#define bfin_read_TPERIOD() bfin_read32(TPERIOD) +#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) +#define bfin_read_TSCALE() bfin_read32(TSCALE) +#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) +#define bfin_read_TCOUNT() bfin_read32(TCOUNT) +#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) + +#define bfin_read_DSPID() bfin_read32(DSPID) +#define bfin_write_DSPID(val) bfin_write32(DSPID, val) +#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT) +#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val) + +#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) +#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) +#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) +#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) +#define bfin_read_TBUF() bfin_readPTR(TBUF) +#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) + #define bfin_read_WPIACTL() bfin_read32(WPIACTL) #define bfin_write_WPIACTL(val) bfin_write32(WPIACTL, val) -#define pWPIA0 ((void * volatile *)WPIA0) #define bfin_read_WPIA0() bfin_readPTR(WPIA0) #define bfin_write_WPIA0(val) bfin_writePTR(WPIA0, val) -#define pWPIA1 ((void * volatile *)WPIA1) #define bfin_read_WPIA1() bfin_readPTR(WPIA1) #define bfin_write_WPIA1(val) bfin_writePTR(WPIA1, val) -#define pWPIA2 ((void * volatile *)WPIA2) #define bfin_read_WPIA2() bfin_readPTR(WPIA2) #define bfin_write_WPIA2(val) bfin_writePTR(WPIA2, val) -#define pWPIA3 ((void * volatile *)WPIA3) #define bfin_read_WPIA3() bfin_readPTR(WPIA3) #define bfin_write_WPIA3(val) bfin_writePTR(WPIA3, val) -#define pWPIA4 ((void * volatile *)WPIA4) #define bfin_read_WPIA4() bfin_readPTR(WPIA4) #define bfin_write_WPIA4(val) bfin_writePTR(WPIA4, val) -#define pWPIA5 ((void * volatile *)WPIA5) #define bfin_read_WPIA5() bfin_readPTR(WPIA5) #define bfin_write_WPIA5(val) bfin_writePTR(WPIA5, val) -#define pWPIACNT0 ((uint32_t volatile *)WPIACNT0) #define bfin_read_WPIACNT0() bfin_read32(WPIACNT0) #define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0, val) -#define pWPIACNT1 ((uint32_t volatile *)WPIACNT1) #define bfin_read_WPIACNT1() bfin_read32(WPIACNT1) #define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1, val) -#define pWPIACNT2 ((uint32_t volatile *)WPIACNT2) #define bfin_read_WPIACNT2() bfin_read32(WPIACNT2) #define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2, val) -#define pWPIACNT3 ((uint32_t volatile *)WPIACNT3) #define bfin_read_WPIACNT3() bfin_read32(WPIACNT3) #define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3, val) -#define pWPIACNT4 ((uint32_t volatile *)WPIACNT4) #define bfin_read_WPIACNT4() bfin_read32(WPIACNT4) #define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4, val) -#define pWPIACNT5 ((uint32_t volatile *)WPIACNT5) #define bfin_read_WPIACNT5() bfin_read32(WPIACNT5) #define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5, val) -#define pWPDACTL ((uint32_t volatile *)WPDACTL) #define bfin_read_WPDACTL() bfin_read32(WPDACTL) #define bfin_write_WPDACTL(val) bfin_write32(WPDACTL, val) -#define pWPDA0 ((void * volatile *)WPDA0) #define bfin_read_WPDA0() bfin_readPTR(WPDA0) #define bfin_write_WPDA0(val) bfin_writePTR(WPDA0, val) -#define pWPDA1 ((void * volatile *)WPDA1) #define bfin_read_WPDA1() bfin_readPTR(WPDA1) #define bfin_write_WPDA1(val) bfin_writePTR(WPDA1, val) -#define pWPDACNT0 ((uint32_t volatile *)WPDACNT0) #define bfin_read_WPDACNT0() bfin_read32(WPDACNT0) #define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0, val) -#define pWPDACNT1 ((uint32_t volatile *)WPDACNT1) #define bfin_read_WPDACNT1() bfin_read32(WPDACNT1) #define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1, val) -#define pWPSTAT ((uint32_t volatile *)WPSTAT) #define bfin_read_WPSTAT() bfin_read32(WPSTAT) #define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val) -#define pDSPID ((uint32_t volatile *)DSPID) -#define bfin_read_DSPID() bfin_read32(DSPID) -#define bfin_write_DSPID(val) bfin_write32(DSPID, val) -#define pDBGSTAT ((uint32_t volatile *)DBGSTAT) -#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT) -#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val) + +#define bfin_read_PFCTL() bfin_read32(PFCTL) +#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) +#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) +#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) +#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) +#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) #endif /* __BFIN_CDEF_ADSP_EDN_core__ */ diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h index 74f5d309c0..cf28b8ea27 100644 --- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h +++ b/arch/blackfin/include/asm/mach-common/ADSP-EDN-core_def.h @@ -6,6 +6,120 @@ #ifndef __BFIN_DEF_ADSP_EDN_core__ #define __BFIN_DEF_ADSP_EDN_core__ +#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ +#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ +#define DCPLB_FAULT_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ +#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ +#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ +#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ +#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ +#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ +#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ +#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ +#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ +#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ +#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ +#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ +#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ +#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ +#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ +#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ +#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ +#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ +#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ +#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ +#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ +#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ +#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ +#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ +#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ +#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ +#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ +#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ +#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ +#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ +#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ +#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ +#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ +#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ +#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ +#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ +#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ + +#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ +#define ICPLB_FAULT_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ +#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ +#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ +#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ +#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ +#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ +#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ +#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ +#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ +#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ +#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ +#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ +#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ +#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ +#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ +#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ +#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ +#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ +#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ +#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ +#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ +#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ +#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ +#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ +#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ +#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ +#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ +#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ +#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ +#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ +#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ +#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ +#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ +#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ +#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ +#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ +#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ + +#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ +#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ +#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ +#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ +#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ +#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ +#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ +#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ +#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ +#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ +#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ +#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ +#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ +#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ +#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ +#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ + +#define EVT_OVERRIDE 0xFFE02100 +#define ILAT 0xFFE0210C /* Interrupt Latch Register */ +#define IMASK 0xFFE02104 /* Interrupt Mask Register */ +#define IPEND 0xFFE02108 /* Interrupt Pending Register */ +#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ + +#define TCNTL 0xFFE03000 /* Core Timer Control Register */ +#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ +#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ +#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ + +#define DSPID 0xFFE05000 +#define DBGSTAT 0xFFE05008 + +#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ +#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ +#define TBUF 0xFFE06100 /* Trace Buffer */ + #define WPIACTL 0xFFE07000 #define WPIA0 0xFFE07040 #define WPIA1 0xFFE07044 @@ -25,7 +139,9 @@ #define WPDACNT0 0xFFE07180 #define WPDACNT1 0xFFE07184 #define WPSTAT 0xFFE07200 -#define DSPID 0xFFE05000 -#define DBGSTAT 0xFFE05008 + +#define PFCTL 0xFFE08000 +#define PFCNTR0 0xFFE08100 +#define PFCNTR1 0xFFE08104 #endif /* __BFIN_DEF_ADSP_EDN_core__ */ diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h deleted file mode 100644 index 2e61b5faae..0000000000 --- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_cdef.h +++ /dev/null @@ -1,1607 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-cdef-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_CDEF_ADSP_EDN_extended__ -#define __BFIN_CDEF_ADSP_EDN_extended__ - -#define pILAT ((uint32_t volatile *)ILAT) /* Interrupt Latch Register */ -#define bfin_read_ILAT() bfin_read32(ILAT) -#define bfin_write_ILAT(val) bfin_write32(ILAT, val) -#define pIMASK ((uint32_t volatile *)IMASK) /* Interrupt Mask Register */ -#define bfin_read_IMASK() bfin_read32(IMASK) -#define bfin_write_IMASK(val) bfin_write32(IMASK, val) -#define pIPEND ((uint32_t volatile *)IPEND) /* Interrupt Pending Register */ -#define bfin_read_IPEND() bfin_read32(IPEND) -#define bfin_write_IPEND(val) bfin_write32(IPEND, val) -#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */ -#define bfin_read_IPRIO() bfin_read32(IPRIO) -#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val) -#define pTCNTL ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */ -#define bfin_read_TCNTL() bfin_read32(TCNTL) -#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) -#define pTPERIOD ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */ -#define bfin_read_TPERIOD() bfin_read32(TPERIOD) -#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) -#define pTSCALE ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */ -#define bfin_read_TSCALE() bfin_read32(TSCALE) -#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) -#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */ -#define bfin_read_TCOUNT() bfin_read32(TCOUNT) -#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) -#define pSRAM_BASE_ADDR ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */ -#define bfin_read_SRAM_BASE_ADDR() bfin_readPTR(SRAM_BASE_ADDR) -#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val) -#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */ -#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) -#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) -#define pDCPLB_FAULT_STATUS ((uint32_t volatile *)DCPLB_FAULT_STATUS) /* L1 Data Memory Controller Register */ -#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS) -#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val) -#define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR) -#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) -#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val) -#define pDCPLB_ADDR0 ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */ -#define bfin_read_DCPLB_ADDR0() bfin_readPTR(DCPLB_ADDR0) -#define bfin_write_DCPLB_ADDR0(val) bfin_writePTR(DCPLB_ADDR0, val) -#define pDCPLB_ADDR1 ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */ -#define bfin_read_DCPLB_ADDR1() bfin_readPTR(DCPLB_ADDR1) -#define bfin_write_DCPLB_ADDR1(val) bfin_writePTR(DCPLB_ADDR1, val) -#define pDCPLB_ADDR2 ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */ -#define bfin_read_DCPLB_ADDR2() bfin_readPTR(DCPLB_ADDR2) -#define bfin_write_DCPLB_ADDR2(val) bfin_writePTR(DCPLB_ADDR2, val) -#define pDCPLB_ADDR3 ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */ -#define bfin_read_DCPLB_ADDR3() bfin_readPTR(DCPLB_ADDR3) -#define bfin_write_DCPLB_ADDR3(val) bfin_writePTR(DCPLB_ADDR3, val) -#define pDCPLB_ADDR4 ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */ -#define bfin_read_DCPLB_ADDR4() bfin_readPTR(DCPLB_ADDR4) -#define bfin_write_DCPLB_ADDR4(val) bfin_writePTR(DCPLB_ADDR4, val) -#define pDCPLB_ADDR5 ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */ -#define bfin_read_DCPLB_ADDR5() bfin_readPTR(DCPLB_ADDR5) -#define bfin_write_DCPLB_ADDR5(val) bfin_writePTR(DCPLB_ADDR5, val) -#define pDCPLB_ADDR6 ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */ -#define bfin_read_DCPLB_ADDR6() bfin_readPTR(DCPLB_ADDR6) -#define bfin_write_DCPLB_ADDR6(val) bfin_writePTR(DCPLB_ADDR6, val) -#define pDCPLB_ADDR7 ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */ -#define bfin_read_DCPLB_ADDR7() bfin_readPTR(DCPLB_ADDR7) -#define bfin_write_DCPLB_ADDR7(val) bfin_writePTR(DCPLB_ADDR7, val) -#define pDCPLB_ADDR8 ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */ -#define bfin_read_DCPLB_ADDR8() bfin_readPTR(DCPLB_ADDR8) -#define bfin_write_DCPLB_ADDR8(val) bfin_writePTR(DCPLB_ADDR8, val) -#define pDCPLB_ADDR9 ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */ -#define bfin_read_DCPLB_ADDR9() bfin_readPTR(DCPLB_ADDR9) -#define bfin_write_DCPLB_ADDR9(val) bfin_writePTR(DCPLB_ADDR9, val) -#define pDCPLB_ADDR10 ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */ -#define bfin_read_DCPLB_ADDR10() bfin_readPTR(DCPLB_ADDR10) -#define bfin_write_DCPLB_ADDR10(val) bfin_writePTR(DCPLB_ADDR10, val) -#define pDCPLB_ADDR11 ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */ -#define bfin_read_DCPLB_ADDR11() bfin_readPTR(DCPLB_ADDR11) -#define bfin_write_DCPLB_ADDR11(val) bfin_writePTR(DCPLB_ADDR11, val) -#define pDCPLB_ADDR12 ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */ -#define bfin_read_DCPLB_ADDR12() bfin_readPTR(DCPLB_ADDR12) -#define bfin_write_DCPLB_ADDR12(val) bfin_writePTR(DCPLB_ADDR12, val) -#define pDCPLB_ADDR13 ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */ -#define bfin_read_DCPLB_ADDR13() bfin_readPTR(DCPLB_ADDR13) -#define bfin_write_DCPLB_ADDR13(val) bfin_writePTR(DCPLB_ADDR13, val) -#define pDCPLB_ADDR14 ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */ -#define bfin_read_DCPLB_ADDR14() bfin_readPTR(DCPLB_ADDR14) -#define bfin_write_DCPLB_ADDR14(val) bfin_writePTR(DCPLB_ADDR14, val) -#define pDCPLB_ADDR15 ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */ -#define bfin_read_DCPLB_ADDR15() bfin_readPTR(DCPLB_ADDR15) -#define bfin_write_DCPLB_ADDR15(val) bfin_writePTR(DCPLB_ADDR15, val) -#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */ -#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) -#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) -#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */ -#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) -#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) -#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */ -#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) -#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) -#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */ -#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) -#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) -#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */ -#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) -#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) -#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */ -#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) -#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) -#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */ -#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) -#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) -#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */ -#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) -#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) -#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */ -#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) -#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) -#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */ -#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) -#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) -#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */ -#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) -#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) -#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */ -#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) -#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) -#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */ -#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) -#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) -#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */ -#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) -#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) -#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */ -#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) -#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) -#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */ -#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) -#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) -#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */ -#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) -#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) -#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) -#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) -#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */ -#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) -#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) -#define pEVT0 ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */ -#define bfin_read_EVT0() bfin_readPTR(EVT0) -#define bfin_write_EVT0(val) bfin_writePTR(EVT0, val) -#define pEVT1 ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */ -#define bfin_read_EVT1() bfin_readPTR(EVT1) -#define bfin_write_EVT1(val) bfin_writePTR(EVT1, val) -#define pEVT2 ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */ -#define bfin_read_EVT2() bfin_readPTR(EVT2) -#define bfin_write_EVT2(val) bfin_writePTR(EVT2, val) -#define pEVT3 ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */ -#define bfin_read_EVT3() bfin_readPTR(EVT3) -#define bfin_write_EVT3(val) bfin_writePTR(EVT3, val) -#define pEVT4 ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */ -#define bfin_read_EVT4() bfin_readPTR(EVT4) -#define bfin_write_EVT4(val) bfin_writePTR(EVT4, val) -#define pEVT5 ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */ -#define bfin_read_EVT5() bfin_readPTR(EVT5) -#define bfin_write_EVT5(val) bfin_writePTR(EVT5, val) -#define pEVT6 ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */ -#define bfin_read_EVT6() bfin_readPTR(EVT6) -#define bfin_write_EVT6(val) bfin_writePTR(EVT6, val) -#define pEVT7 ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */ -#define bfin_read_EVT7() bfin_readPTR(EVT7) -#define bfin_write_EVT7(val) bfin_writePTR(EVT7, val) -#define pEVT8 ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */ -#define bfin_read_EVT8() bfin_readPTR(EVT8) -#define bfin_write_EVT8(val) bfin_writePTR(EVT8, val) -#define pEVT9 ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */ -#define bfin_read_EVT9() bfin_readPTR(EVT9) -#define bfin_write_EVT9(val) bfin_writePTR(EVT9, val) -#define pEVT10 ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */ -#define bfin_read_EVT10() bfin_readPTR(EVT10) -#define bfin_write_EVT10(val) bfin_writePTR(EVT10, val) -#define pEVT11 ((void * volatile *)EVT11) /* Event Vector 11 ESR Address */ -#define bfin_read_EVT11() bfin_readPTR(EVT11) -#define bfin_write_EVT11(val) bfin_writePTR(EVT11, val) -#define pEVT12 ((void * volatile *)EVT12) /* Event Vector 12 ESR Address */ -#define bfin_read_EVT12() bfin_readPTR(EVT12) -#define bfin_write_EVT12(val) bfin_writePTR(EVT12, val) -#define pEVT13 ((void * volatile *)EVT13) /* Event Vector 13 ESR Address */ -#define bfin_read_EVT13() bfin_readPTR(EVT13) -#define bfin_write_EVT13(val) bfin_writePTR(EVT13, val) -#define pEVT14 ((void * volatile *)EVT14) /* Event Vector 14 ESR Address */ -#define bfin_read_EVT14() bfin_readPTR(EVT14) -#define bfin_write_EVT14(val) bfin_writePTR(EVT14, val) -#define pEVT15 ((void * volatile *)EVT15) /* Event Vector 15 ESR Address */ -#define bfin_read_EVT15() bfin_readPTR(EVT15) -#define bfin_write_EVT15(val) bfin_writePTR(EVT15, val) -#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */ -#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) -#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) -#define pICPLB_FAULT_STATUS ((uint32_t volatile *)ICPLB_FAULT_STATUS) -#define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS) -#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val) -#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR) -#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) -#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val) -#define pICPLB_ADDR0 ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define bfin_read_ICPLB_ADDR0() bfin_readPTR(ICPLB_ADDR0) -#define bfin_write_ICPLB_ADDR0(val) bfin_writePTR(ICPLB_ADDR0, val) -#define pICPLB_ADDR1 ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define bfin_read_ICPLB_ADDR1() bfin_readPTR(ICPLB_ADDR1) -#define bfin_write_ICPLB_ADDR1(val) bfin_writePTR(ICPLB_ADDR1, val) -#define pICPLB_ADDR2 ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define bfin_read_ICPLB_ADDR2() bfin_readPTR(ICPLB_ADDR2) -#define bfin_write_ICPLB_ADDR2(val) bfin_writePTR(ICPLB_ADDR2, val) -#define pICPLB_ADDR3 ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define bfin_read_ICPLB_ADDR3() bfin_readPTR(ICPLB_ADDR3) -#define bfin_write_ICPLB_ADDR3(val) bfin_writePTR(ICPLB_ADDR3, val) -#define pICPLB_ADDR4 ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define bfin_read_ICPLB_ADDR4() bfin_readPTR(ICPLB_ADDR4) -#define bfin_write_ICPLB_ADDR4(val) bfin_writePTR(ICPLB_ADDR4, val) -#define pICPLB_ADDR5 ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define bfin_read_ICPLB_ADDR5() bfin_readPTR(ICPLB_ADDR5) -#define bfin_write_ICPLB_ADDR5(val) bfin_writePTR(ICPLB_ADDR5, val) -#define pICPLB_ADDR6 ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define bfin_read_ICPLB_ADDR6() bfin_readPTR(ICPLB_ADDR6) -#define bfin_write_ICPLB_ADDR6(val) bfin_writePTR(ICPLB_ADDR6, val) -#define pICPLB_ADDR7 ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define bfin_read_ICPLB_ADDR7() bfin_readPTR(ICPLB_ADDR7) -#define bfin_write_ICPLB_ADDR7(val) bfin_writePTR(ICPLB_ADDR7, val) -#define pICPLB_ADDR8 ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define bfin_read_ICPLB_ADDR8() bfin_readPTR(ICPLB_ADDR8) -#define bfin_write_ICPLB_ADDR8(val) bfin_writePTR(ICPLB_ADDR8, val) -#define pICPLB_ADDR9 ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define bfin_read_ICPLB_ADDR9() bfin_readPTR(ICPLB_ADDR9) -#define bfin_write_ICPLB_ADDR9(val) bfin_writePTR(ICPLB_ADDR9, val) -#define pICPLB_ADDR10 ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define bfin_read_ICPLB_ADDR10() bfin_readPTR(ICPLB_ADDR10) -#define bfin_write_ICPLB_ADDR10(val) bfin_writePTR(ICPLB_ADDR10, val) -#define pICPLB_ADDR11 ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define bfin_read_ICPLB_ADDR11() bfin_readPTR(ICPLB_ADDR11) -#define bfin_write_ICPLB_ADDR11(val) bfin_writePTR(ICPLB_ADDR11, val) -#define pICPLB_ADDR12 ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define bfin_read_ICPLB_ADDR12() bfin_readPTR(ICPLB_ADDR12) -#define bfin_write_ICPLB_ADDR12(val) bfin_writePTR(ICPLB_ADDR12, val) -#define pICPLB_ADDR13 ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define bfin_read_ICPLB_ADDR13() bfin_readPTR(ICPLB_ADDR13) -#define bfin_write_ICPLB_ADDR13(val) bfin_writePTR(ICPLB_ADDR13, val) -#define pICPLB_ADDR14 ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define bfin_read_ICPLB_ADDR14() bfin_readPTR(ICPLB_ADDR14) -#define bfin_write_ICPLB_ADDR14(val) bfin_writePTR(ICPLB_ADDR14, val) -#define pICPLB_ADDR15 ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define bfin_read_ICPLB_ADDR15() bfin_readPTR(ICPLB_ADDR15) -#define bfin_write_ICPLB_ADDR15(val) bfin_writePTR(ICPLB_ADDR15, val) -#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */ -#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) -#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) -#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */ -#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) -#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) -#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */ -#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) -#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) -#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */ -#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) -#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) -#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */ -#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) -#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) -#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */ -#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) -#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) -#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */ -#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) -#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) -#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */ -#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) -#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) -#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */ -#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) -#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) -#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */ -#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) -#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) -#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */ -#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) -#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) -#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */ -#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) -#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) -#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */ -#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) -#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) -#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */ -#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) -#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) -#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */ -#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) -#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) -#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */ -#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) -#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) -#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */ -#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) -#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) -#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) -#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) -#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */ -#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) -#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pMDMAFLX0_DMACNFG_D ((uint16_t volatile *)MDMAFLX0_DMACNFG_D) -#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D) -#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val) -#define pMDMAFLX0_XCOUNT_D ((uint16_t volatile *)MDMAFLX0_XCOUNT_D) -#define bfin_read_MDMAFLX0_XCOUNT_D() bfin_read16(MDMAFLX0_XCOUNT_D) -#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val) -#define pMDMAFLX0_XMODIFY_D ((uint16_t volatile *)MDMAFLX0_XMODIFY_D) -#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D) -#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val) -#define pMDMAFLX0_YCOUNT_D ((uint16_t volatile *)MDMAFLX0_YCOUNT_D) -#define bfin_read_MDMAFLX0_YCOUNT_D() bfin_read16(MDMAFLX0_YCOUNT_D) -#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val) -#define pMDMAFLX0_YMODIFY_D ((uint16_t volatile *)MDMAFLX0_YMODIFY_D) -#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D) -#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val) -#define pMDMAFLX0_IRQSTAT_D ((uint16_t volatile *)MDMAFLX0_IRQSTAT_D) -#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D) -#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val) -#define pMDMAFLX0_PMAP_D ((uint16_t volatile *)MDMAFLX0_PMAP_D) -#define bfin_read_MDMAFLX0_PMAP_D() bfin_read16(MDMAFLX0_PMAP_D) -#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val) -#define pMDMAFLX0_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_D) -#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D) -#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val) -#define pMDMAFLX0_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_D) -#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D) -#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val) -#define pMDMAFLX0_DMACNFG_S ((uint16_t volatile *)MDMAFLX0_DMACNFG_S) -#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S) -#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val) -#define pMDMAFLX0_XCOUNT_S ((uint16_t volatile *)MDMAFLX0_XCOUNT_S) -#define bfin_read_MDMAFLX0_XCOUNT_S() bfin_read16(MDMAFLX0_XCOUNT_S) -#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val) -#define pMDMAFLX0_XMODIFY_S ((uint16_t volatile *)MDMAFLX0_XMODIFY_S) -#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S) -#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val) -#define pMDMAFLX0_YCOUNT_S ((uint16_t volatile *)MDMAFLX0_YCOUNT_S) -#define bfin_read_MDMAFLX0_YCOUNT_S() bfin_read16(MDMAFLX0_YCOUNT_S) -#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val) -#define pMDMAFLX0_YMODIFY_S ((uint16_t volatile *)MDMAFLX0_YMODIFY_S) -#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S) -#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val) -#define pMDMAFLX0_IRQSTAT_S ((uint16_t volatile *)MDMAFLX0_IRQSTAT_S) -#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S) -#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val) -#define pMDMAFLX0_PMAP_S ((uint16_t volatile *)MDMAFLX0_PMAP_S) -#define bfin_read_MDMAFLX0_PMAP_S() bfin_read16(MDMAFLX0_PMAP_S) -#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val) -#define pMDMAFLX0_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURXCOUNT_S) -#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S) -#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val) -#define pMDMAFLX0_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX0_CURYCOUNT_S) -#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S) -#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val) -#define pMDMAFLX1_DMACNFG_D ((uint16_t volatile *)MDMAFLX1_DMACNFG_D) -#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D) -#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val) -#define pMDMAFLX1_XCOUNT_D ((uint16_t volatile *)MDMAFLX1_XCOUNT_D) -#define bfin_read_MDMAFLX1_XCOUNT_D() bfin_read16(MDMAFLX1_XCOUNT_D) -#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val) -#define pMDMAFLX1_XMODIFY_D ((uint16_t volatile *)MDMAFLX1_XMODIFY_D) -#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D) -#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val) -#define pMDMAFLX1_YCOUNT_D ((uint16_t volatile *)MDMAFLX1_YCOUNT_D) -#define bfin_read_MDMAFLX1_YCOUNT_D() bfin_read16(MDMAFLX1_YCOUNT_D) -#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val) -#define pMDMAFLX1_YMODIFY_D ((uint16_t volatile *)MDMAFLX1_YMODIFY_D) -#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D) -#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val) -#define pMDMAFLX1_IRQSTAT_D ((uint16_t volatile *)MDMAFLX1_IRQSTAT_D) -#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D) -#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val) -#define pMDMAFLX1_PMAP_D ((uint16_t volatile *)MDMAFLX1_PMAP_D) -#define bfin_read_MDMAFLX1_PMAP_D() bfin_read16(MDMAFLX1_PMAP_D) -#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val) -#define pMDMAFLX1_CURXCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_D) -#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D) -#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val) -#define pMDMAFLX1_CURYCOUNT_D ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_D) -#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D) -#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val) -#define pMDMAFLX1_DMACNFG_S ((uint16_t volatile *)MDMAFLX1_DMACNFG_S) -#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S) -#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val) -#define pMDMAFLX1_XCOUNT_S ((uint16_t volatile *)MDMAFLX1_XCOUNT_S) -#define bfin_read_MDMAFLX1_XCOUNT_S() bfin_read16(MDMAFLX1_XCOUNT_S) -#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val) -#define pMDMAFLX1_XMODIFY_S ((uint16_t volatile *)MDMAFLX1_XMODIFY_S) -#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S) -#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val) -#define pMDMAFLX1_YCOUNT_S ((uint16_t volatile *)MDMAFLX1_YCOUNT_S) -#define bfin_read_MDMAFLX1_YCOUNT_S() bfin_read16(MDMAFLX1_YCOUNT_S) -#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val) -#define pMDMAFLX1_YMODIFY_S ((uint16_t volatile *)MDMAFLX1_YMODIFY_S) -#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S) -#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val) -#define pMDMAFLX1_IRQSTAT_S ((uint16_t volatile *)MDMAFLX1_IRQSTAT_S) -#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S) -#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val) -#define pMDMAFLX1_PMAP_S ((uint16_t volatile *)MDMAFLX1_PMAP_S) -#define bfin_read_MDMAFLX1_PMAP_S() bfin_read16(MDMAFLX1_PMAP_S) -#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val) -#define pMDMAFLX1_CURXCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURXCOUNT_S) -#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S) -#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val) -#define pMDMAFLX1_CURYCOUNT_S ((uint16_t volatile *)MDMAFLX1_CURYCOUNT_S) -#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S) -#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val) -#define pDMAFLX0_DMACNFG ((uint16_t volatile *)DMAFLX0_DMACNFG) -#define bfin_read_DMAFLX0_DMACNFG() bfin_read16(DMAFLX0_DMACNFG) -#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val) -#define pDMAFLX0_XCOUNT ((uint16_t volatile *)DMAFLX0_XCOUNT) -#define bfin_read_DMAFLX0_XCOUNT() bfin_read16(DMAFLX0_XCOUNT) -#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val) -#define pDMAFLX0_XMODIFY ((uint16_t volatile *)DMAFLX0_XMODIFY) -#define bfin_read_DMAFLX0_XMODIFY() bfin_read16(DMAFLX0_XMODIFY) -#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val) -#define pDMAFLX0_YCOUNT ((uint16_t volatile *)DMAFLX0_YCOUNT) -#define bfin_read_DMAFLX0_YCOUNT() bfin_read16(DMAFLX0_YCOUNT) -#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val) -#define pDMAFLX0_YMODIFY ((uint16_t volatile *)DMAFLX0_YMODIFY) -#define bfin_read_DMAFLX0_YMODIFY() bfin_read16(DMAFLX0_YMODIFY) -#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val) -#define pDMAFLX0_IRQSTAT ((uint16_t volatile *)DMAFLX0_IRQSTAT) -#define bfin_read_DMAFLX0_IRQSTAT() bfin_read16(DMAFLX0_IRQSTAT) -#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val) -#define pDMAFLX0_PMAP ((uint16_t volatile *)DMAFLX0_PMAP) -#define bfin_read_DMAFLX0_PMAP() bfin_read16(DMAFLX0_PMAP) -#define bfin_write_DMAFLX0_PMAP(val) bfin_write16(DMAFLX0_PMAP, val) -#define pDMAFLX0_CURXCOUNT ((uint16_t volatile *)DMAFLX0_CURXCOUNT) -#define bfin_read_DMAFLX0_CURXCOUNT() bfin_read16(DMAFLX0_CURXCOUNT) -#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val) -#define pDMAFLX0_CURYCOUNT ((uint16_t volatile *)DMAFLX0_CURYCOUNT) -#define bfin_read_DMAFLX0_CURYCOUNT() bfin_read16(DMAFLX0_CURYCOUNT) -#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val) -#define pDMAFLX1_DMACNFG ((uint16_t volatile *)DMAFLX1_DMACNFG) -#define bfin_read_DMAFLX1_DMACNFG() bfin_read16(DMAFLX1_DMACNFG) -#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val) -#define pDMAFLX1_XCOUNT ((uint16_t volatile *)DMAFLX1_XCOUNT) -#define bfin_read_DMAFLX1_XCOUNT() bfin_read16(DMAFLX1_XCOUNT) -#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val) -#define pDMAFLX1_XMODIFY ((uint16_t volatile *)DMAFLX1_XMODIFY) -#define bfin_read_DMAFLX1_XMODIFY() bfin_read16(DMAFLX1_XMODIFY) -#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val) -#define pDMAFLX1_YCOUNT ((uint16_t volatile *)DMAFLX1_YCOUNT) -#define bfin_read_DMAFLX1_YCOUNT() bfin_read16(DMAFLX1_YCOUNT) -#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val) -#define pDMAFLX1_YMODIFY ((uint16_t volatile *)DMAFLX1_YMODIFY) -#define bfin_read_DMAFLX1_YMODIFY() bfin_read16(DMAFLX1_YMODIFY) -#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val) -#define pDMAFLX1_IRQSTAT ((uint16_t volatile *)DMAFLX1_IRQSTAT) -#define bfin_read_DMAFLX1_IRQSTAT() bfin_read16(DMAFLX1_IRQSTAT) -#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val) -#define pDMAFLX1_PMAP ((uint16_t volatile *)DMAFLX1_PMAP) -#define bfin_read_DMAFLX1_PMAP() bfin_read16(DMAFLX1_PMAP) -#define bfin_write_DMAFLX1_PMAP(val) bfin_write16(DMAFLX1_PMAP, val) -#define pDMAFLX1_CURXCOUNT ((uint16_t volatile *)DMAFLX1_CURXCOUNT) -#define bfin_read_DMAFLX1_CURXCOUNT() bfin_read16(DMAFLX1_CURXCOUNT) -#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val) -#define pDMAFLX1_CURYCOUNT ((uint16_t volatile *)DMAFLX1_CURYCOUNT) -#define bfin_read_DMAFLX1_CURYCOUNT() bfin_read16(DMAFLX1_CURYCOUNT) -#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val) -#define pDMAFLX2_DMACNFG ((uint16_t volatile *)DMAFLX2_DMACNFG) -#define bfin_read_DMAFLX2_DMACNFG() bfin_read16(DMAFLX2_DMACNFG) -#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val) -#define pDMAFLX2_XCOUNT ((uint16_t volatile *)DMAFLX2_XCOUNT) -#define bfin_read_DMAFLX2_XCOUNT() bfin_read16(DMAFLX2_XCOUNT) -#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val) -#define pDMAFLX2_XMODIFY ((uint16_t volatile *)DMAFLX2_XMODIFY) -#define bfin_read_DMAFLX2_XMODIFY() bfin_read16(DMAFLX2_XMODIFY) -#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val) -#define pDMAFLX2_YCOUNT ((uint16_t volatile *)DMAFLX2_YCOUNT) -#define bfin_read_DMAFLX2_YCOUNT() bfin_read16(DMAFLX2_YCOUNT) -#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val) -#define pDMAFLX2_YMODIFY ((uint16_t volatile *)DMAFLX2_YMODIFY) -#define bfin_read_DMAFLX2_YMODIFY() bfin_read16(DMAFLX2_YMODIFY) -#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val) -#define pDMAFLX2_IRQSTAT ((uint16_t volatile *)DMAFLX2_IRQSTAT) -#define bfin_read_DMAFLX2_IRQSTAT() bfin_read16(DMAFLX2_IRQSTAT) -#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val) -#define pDMAFLX2_PMAP ((uint16_t volatile *)DMAFLX2_PMAP) -#define bfin_read_DMAFLX2_PMAP() bfin_read16(DMAFLX2_PMAP) -#define bfin_write_DMAFLX2_PMAP(val) bfin_write16(DMAFLX2_PMAP, val) -#define pDMAFLX2_CURXCOUNT ((uint16_t volatile *)DMAFLX2_CURXCOUNT) -#define bfin_read_DMAFLX2_CURXCOUNT() bfin_read16(DMAFLX2_CURXCOUNT) -#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val) -#define pDMAFLX2_CURYCOUNT ((uint16_t volatile *)DMAFLX2_CURYCOUNT) -#define bfin_read_DMAFLX2_CURYCOUNT() bfin_read16(DMAFLX2_CURYCOUNT) -#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val) -#define pDMAFLX3_DMACNFG ((uint16_t volatile *)DMAFLX3_DMACNFG) -#define bfin_read_DMAFLX3_DMACNFG() bfin_read16(DMAFLX3_DMACNFG) -#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val) -#define pDMAFLX3_XCOUNT ((uint16_t volatile *)DMAFLX3_XCOUNT) -#define bfin_read_DMAFLX3_XCOUNT() bfin_read16(DMAFLX3_XCOUNT) -#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val) -#define pDMAFLX3_XMODIFY ((uint16_t volatile *)DMAFLX3_XMODIFY) -#define bfin_read_DMAFLX3_XMODIFY() bfin_read16(DMAFLX3_XMODIFY) -#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val) -#define pDMAFLX3_YCOUNT ((uint16_t volatile *)DMAFLX3_YCOUNT) -#define bfin_read_DMAFLX3_YCOUNT() bfin_read16(DMAFLX3_YCOUNT) -#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val) -#define pDMAFLX3_YMODIFY ((uint16_t volatile *)DMAFLX3_YMODIFY) -#define bfin_read_DMAFLX3_YMODIFY() bfin_read16(DMAFLX3_YMODIFY) -#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val) -#define pDMAFLX3_IRQSTAT ((uint16_t volatile *)DMAFLX3_IRQSTAT) -#define bfin_read_DMAFLX3_IRQSTAT() bfin_read16(DMAFLX3_IRQSTAT) -#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val) -#define pDMAFLX3_PMAP ((uint16_t volatile *)DMAFLX3_PMAP) -#define bfin_read_DMAFLX3_PMAP() bfin_read16(DMAFLX3_PMAP) -#define bfin_write_DMAFLX3_PMAP(val) bfin_write16(DMAFLX3_PMAP, val) -#define pDMAFLX3_CURXCOUNT ((uint16_t volatile *)DMAFLX3_CURXCOUNT) -#define bfin_read_DMAFLX3_CURXCOUNT() bfin_read16(DMAFLX3_CURXCOUNT) -#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val) -#define pDMAFLX3_CURYCOUNT ((uint16_t volatile *)DMAFLX3_CURYCOUNT) -#define bfin_read_DMAFLX3_CURYCOUNT() bfin_read16(DMAFLX3_CURYCOUNT) -#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val) -#define pDMAFLX4_DMACNFG ((uint16_t volatile *)DMAFLX4_DMACNFG) -#define bfin_read_DMAFLX4_DMACNFG() bfin_read16(DMAFLX4_DMACNFG) -#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val) -#define pDMAFLX4_XCOUNT ((uint16_t volatile *)DMAFLX4_XCOUNT) -#define bfin_read_DMAFLX4_XCOUNT() bfin_read16(DMAFLX4_XCOUNT) -#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val) -#define pDMAFLX4_XMODIFY ((uint16_t volatile *)DMAFLX4_XMODIFY) -#define bfin_read_DMAFLX4_XMODIFY() bfin_read16(DMAFLX4_XMODIFY) -#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val) -#define pDMAFLX4_YCOUNT ((uint16_t volatile *)DMAFLX4_YCOUNT) -#define bfin_read_DMAFLX4_YCOUNT() bfin_read16(DMAFLX4_YCOUNT) -#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val) -#define pDMAFLX4_YMODIFY ((uint16_t volatile *)DMAFLX4_YMODIFY) -#define bfin_read_DMAFLX4_YMODIFY() bfin_read16(DMAFLX4_YMODIFY) -#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val) -#define pDMAFLX4_IRQSTAT ((uint16_t volatile *)DMAFLX4_IRQSTAT) -#define bfin_read_DMAFLX4_IRQSTAT() bfin_read16(DMAFLX4_IRQSTAT) -#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val) -#define pDMAFLX4_PMAP ((uint16_t volatile *)DMAFLX4_PMAP) -#define bfin_read_DMAFLX4_PMAP() bfin_read16(DMAFLX4_PMAP) -#define bfin_write_DMAFLX4_PMAP(val) bfin_write16(DMAFLX4_PMAP, val) -#define pDMAFLX4_CURXCOUNT ((uint16_t volatile *)DMAFLX4_CURXCOUNT) -#define bfin_read_DMAFLX4_CURXCOUNT() bfin_read16(DMAFLX4_CURXCOUNT) -#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val) -#define pDMAFLX4_CURYCOUNT ((uint16_t volatile *)DMAFLX4_CURYCOUNT) -#define bfin_read_DMAFLX4_CURYCOUNT() bfin_read16(DMAFLX4_CURYCOUNT) -#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val) -#define pDMAFLX5_DMACNFG ((uint16_t volatile *)DMAFLX5_DMACNFG) -#define bfin_read_DMAFLX5_DMACNFG() bfin_read16(DMAFLX5_DMACNFG) -#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val) -#define pDMAFLX5_XCOUNT ((uint16_t volatile *)DMAFLX5_XCOUNT) -#define bfin_read_DMAFLX5_XCOUNT() bfin_read16(DMAFLX5_XCOUNT) -#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val) -#define pDMAFLX5_XMODIFY ((uint16_t volatile *)DMAFLX5_XMODIFY) -#define bfin_read_DMAFLX5_XMODIFY() bfin_read16(DMAFLX5_XMODIFY) -#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val) -#define pDMAFLX5_YCOUNT ((uint16_t volatile *)DMAFLX5_YCOUNT) -#define bfin_read_DMAFLX5_YCOUNT() bfin_read16(DMAFLX5_YCOUNT) -#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val) -#define pDMAFLX5_YMODIFY ((uint16_t volatile *)DMAFLX5_YMODIFY) -#define bfin_read_DMAFLX5_YMODIFY() bfin_read16(DMAFLX5_YMODIFY) -#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val) -#define pDMAFLX5_IRQSTAT ((uint16_t volatile *)DMAFLX5_IRQSTAT) -#define bfin_read_DMAFLX5_IRQSTAT() bfin_read16(DMAFLX5_IRQSTAT) -#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val) -#define pDMAFLX5_PMAP ((uint16_t volatile *)DMAFLX5_PMAP) -#define bfin_read_DMAFLX5_PMAP() bfin_read16(DMAFLX5_PMAP) -#define bfin_write_DMAFLX5_PMAP(val) bfin_write16(DMAFLX5_PMAP, val) -#define pDMAFLX5_CURXCOUNT ((uint16_t volatile *)DMAFLX5_CURXCOUNT) -#define bfin_read_DMAFLX5_CURXCOUNT() bfin_read16(DMAFLX5_CURXCOUNT) -#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val) -#define pDMAFLX5_CURYCOUNT ((uint16_t volatile *)DMAFLX5_CURYCOUNT) -#define bfin_read_DMAFLX5_CURYCOUNT() bfin_read16(DMAFLX5_CURYCOUNT) -#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val) -#define pDMAFLX6_DMACNFG ((uint16_t volatile *)DMAFLX6_DMACNFG) -#define bfin_read_DMAFLX6_DMACNFG() bfin_read16(DMAFLX6_DMACNFG) -#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val) -#define pDMAFLX6_XCOUNT ((uint16_t volatile *)DMAFLX6_XCOUNT) -#define bfin_read_DMAFLX6_XCOUNT() bfin_read16(DMAFLX6_XCOUNT) -#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val) -#define pDMAFLX6_XMODIFY ((uint16_t volatile *)DMAFLX6_XMODIFY) -#define bfin_read_DMAFLX6_XMODIFY() bfin_read16(DMAFLX6_XMODIFY) -#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val) -#define pDMAFLX6_YCOUNT ((uint16_t volatile *)DMAFLX6_YCOUNT) -#define bfin_read_DMAFLX6_YCOUNT() bfin_read16(DMAFLX6_YCOUNT) -#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val) -#define pDMAFLX6_YMODIFY ((uint16_t volatile *)DMAFLX6_YMODIFY) -#define bfin_read_DMAFLX6_YMODIFY() bfin_read16(DMAFLX6_YMODIFY) -#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val) -#define pDMAFLX6_IRQSTAT ((uint16_t volatile *)DMAFLX6_IRQSTAT) -#define bfin_read_DMAFLX6_IRQSTAT() bfin_read16(DMAFLX6_IRQSTAT) -#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val) -#define pDMAFLX6_PMAP ((uint16_t volatile *)DMAFLX6_PMAP) -#define bfin_read_DMAFLX6_PMAP() bfin_read16(DMAFLX6_PMAP) -#define bfin_write_DMAFLX6_PMAP(val) bfin_write16(DMAFLX6_PMAP, val) -#define pDMAFLX6_CURXCOUNT ((uint16_t volatile *)DMAFLX6_CURXCOUNT) -#define bfin_read_DMAFLX6_CURXCOUNT() bfin_read16(DMAFLX6_CURXCOUNT) -#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val) -#define pDMAFLX6_CURYCOUNT ((uint16_t volatile *)DMAFLX6_CURYCOUNT) -#define bfin_read_DMAFLX6_CURYCOUNT() bfin_read16(DMAFLX6_CURYCOUNT) -#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val) -#define pDMAFLX7_DMACNFG ((uint16_t volatile *)DMAFLX7_DMACNFG) -#define bfin_read_DMAFLX7_DMACNFG() bfin_read16(DMAFLX7_DMACNFG) -#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val) -#define pDMAFLX7_XCOUNT ((uint16_t volatile *)DMAFLX7_XCOUNT) -#define bfin_read_DMAFLX7_XCOUNT() bfin_read16(DMAFLX7_XCOUNT) -#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val) -#define pDMAFLX7_XMODIFY ((uint16_t volatile *)DMAFLX7_XMODIFY) -#define bfin_read_DMAFLX7_XMODIFY() bfin_read16(DMAFLX7_XMODIFY) -#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val) -#define pDMAFLX7_YCOUNT ((uint16_t volatile *)DMAFLX7_YCOUNT) -#define bfin_read_DMAFLX7_YCOUNT() bfin_read16(DMAFLX7_YCOUNT) -#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val) -#define pDMAFLX7_YMODIFY ((uint16_t volatile *)DMAFLX7_YMODIFY) -#define bfin_read_DMAFLX7_YMODIFY() bfin_read16(DMAFLX7_YMODIFY) -#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val) -#define pDMAFLX7_IRQSTAT ((uint16_t volatile *)DMAFLX7_IRQSTAT) -#define bfin_read_DMAFLX7_IRQSTAT() bfin_read16(DMAFLX7_IRQSTAT) -#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val) -#define pDMAFLX7_PMAP ((uint16_t volatile *)DMAFLX7_PMAP) -#define bfin_read_DMAFLX7_PMAP() bfin_read16(DMAFLX7_PMAP) -#define bfin_write_DMAFLX7_PMAP(val) bfin_write16(DMAFLX7_PMAP, val) -#define pDMAFLX7_CURXCOUNT ((uint16_t volatile *)DMAFLX7_CURXCOUNT) -#define bfin_read_DMAFLX7_CURXCOUNT() bfin_read16(DMAFLX7_CURXCOUNT) -#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val) -#define pDMAFLX7_CURYCOUNT ((uint16_t volatile *)DMAFLX7_CURYCOUNT) -#define bfin_read_DMAFLX7_CURYCOUNT() bfin_read16(DMAFLX7_CURYCOUNT) -#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val) -#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) -#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) -#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) -#define pTIMER0_COUNTER ((uint32_t volatile *)TIMER0_COUNTER) -#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER) -#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val) -#define pTIMER0_PERIOD ((uint32_t volatile *)TIMER0_PERIOD) -#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD) -#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val) -#define pTIMER0_WIDTH ((uint32_t volatile *)TIMER0_WIDTH) -#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH) -#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val) -#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) -#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) -#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) -#define pTIMER1_COUNTER ((uint32_t volatile *)TIMER1_COUNTER) -#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER) -#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val) -#define pTIMER1_PERIOD ((uint32_t volatile *)TIMER1_PERIOD) -#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD) -#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val) -#define pTIMER1_WIDTH ((uint32_t volatile *)TIMER1_WIDTH) -#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH) -#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val) -#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) -#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) -#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) -#define pTIMER2_COUNTER ((uint32_t volatile *)TIMER2_COUNTER) -#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER) -#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val) -#define pTIMER2_PERIOD ((uint32_t volatile *)TIMER2_PERIOD) -#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD) -#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val) -#define pTIMER2_WIDTH ((uint32_t volatile *)TIMER2_WIDTH) -#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH) -#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val) -#define pTIMER_ENABLE ((uint16_t volatile *)TIMER_ENABLE) -#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE) -#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val) -#define pTIMER_DISABLE ((uint16_t volatile *)TIMER_DISABLE) -#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE) -#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val) -#define pTIMER_STATUS ((uint16_t volatile *)TIMER_STATUS) -#define bfin_read_TIMER_STATUS() bfin_read16(TIMER_STATUS) -#define bfin_write_TIMER_STATUS(val) bfin_write16(TIMER_STATUS, val) -#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ -#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) -#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */ -#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) -#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) -#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */ -#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) -#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) -#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */ -#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) -#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) -#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */ -#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) -#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) -#define pSIC_IAR3 ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */ -#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3) -#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val) -#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) /* Interrupt Status Register */ -#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) -#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) -#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) /* Interrupt Wakeup Register */ -#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) -#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) -#define pUART_THR ((uint16_t volatile *)UART_THR) /* Transmit Holding */ -#define bfin_read_UART_THR() bfin_read16(UART_THR) -#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val) -#define pUART_DLL ((uint16_t volatile *)UART_DLL) /* Divisor Latch Low Byte */ -#define bfin_read_UART_DLL() bfin_read16(UART_DLL) -#define bfin_write_UART_DLL(val) bfin_write16(UART_DLL, val) -#define pUART_DLH ((uint16_t volatile *)UART_DLH) /* Divisor Latch High Byte */ -#define bfin_read_UART_DLH() bfin_read16(UART_DLH) -#define bfin_write_UART_DLH(val) bfin_write16(UART_DLH, val) -#define pUART_IER ((uint16_t volatile *)UART_IER) -#define bfin_read_UART_IER() bfin_read16(UART_IER) -#define bfin_write_UART_IER(val) bfin_write16(UART_IER, val) -#define pUART_IIR ((uint16_t volatile *)UART_IIR) -#define bfin_read_UART_IIR() bfin_read16(UART_IIR) -#define bfin_write_UART_IIR(val) bfin_write16(UART_IIR, val) -#define pUART_LCR ((uint16_t volatile *)UART_LCR) -#define bfin_read_UART_LCR() bfin_read16(UART_LCR) -#define bfin_write_UART_LCR(val) bfin_write16(UART_LCR, val) -#define pUART_MCR ((uint16_t volatile *)UART_MCR) -#define bfin_read_UART_MCR() bfin_read16(UART_MCR) -#define bfin_write_UART_MCR(val) bfin_write16(UART_MCR, val) -#define pUART_LSR ((uint16_t volatile *)UART_LSR) -#define bfin_read_UART_LSR() bfin_read16(UART_LSR) -#define bfin_write_UART_LSR(val) bfin_write16(UART_LSR, val) -#define pUART_SCR ((uint16_t volatile *)UART_SCR) -#define bfin_read_UART_SCR() bfin_read16(UART_SCR) -#define bfin_write_UART_SCR(val) bfin_write16(UART_SCR, val) -#define pUART_RBR ((uint16_t volatile *)UART_RBR) /* Receive Buffer */ -#define bfin_read_UART_RBR() bfin_read16(UART_RBR) -#define bfin_write_UART_RBR(val) bfin_write16(UART_RBR, val) -#define pUART_GCTL ((uint16_t volatile *)UART_GCTL) -#define bfin_read_UART_GCTL() bfin_read16(UART_GCTL) -#define bfin_write_UART_GCTL(val) bfin_write16(UART_GCTL, val) -#define pSPT0_TX_CONFIG0 ((uint16_t volatile *)SPT0_TX_CONFIG0) -#define bfin_read_SPT0_TX_CONFIG0() bfin_read16(SPT0_TX_CONFIG0) -#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val) -#define pSPT0_TX_CONFIG1 ((uint16_t volatile *)SPT0_TX_CONFIG1) -#define bfin_read_SPT0_TX_CONFIG1() bfin_read16(SPT0_TX_CONFIG1) -#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val) -#define pSPT0_RX_CONFIG0 ((uint16_t volatile *)SPT0_RX_CONFIG0) -#define bfin_read_SPT0_RX_CONFIG0() bfin_read16(SPT0_RX_CONFIG0) -#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val) -#define pSPT0_RX_CONFIG1 ((uint16_t volatile *)SPT0_RX_CONFIG1) -#define bfin_read_SPT0_RX_CONFIG1() bfin_read16(SPT0_RX_CONFIG1) -#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val) -#define pSPT0_TX ((uint32_t volatile *)SPT0_TX) -#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX) -#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val) -#define pSPT0_RX ((uint32_t volatile *)SPT0_RX) -#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX) -#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val) -#define pSPT0_TSCLKDIV ((uint16_t volatile *)SPT0_TSCLKDIV) -#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV) -#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val) -#define pSPT0_RSCLKDIV ((uint16_t volatile *)SPT0_RSCLKDIV) -#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV) -#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val) -#define pSPT0_TFSDIV ((uint16_t volatile *)SPT0_TFSDIV) -#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV) -#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val) -#define pSPT0_RFSDIV ((uint16_t volatile *)SPT0_RFSDIV) -#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV) -#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val) -#define pSPT0_STAT ((uint16_t volatile *)SPT0_STAT) -#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT) -#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val) -#define pSPT0_MTCS0 ((uint32_t volatile *)SPT0_MTCS0) -#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0) -#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val) -#define pSPT0_MTCS1 ((uint32_t volatile *)SPT0_MTCS1) -#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1) -#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val) -#define pSPT0_MTCS2 ((uint32_t volatile *)SPT0_MTCS2) -#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2) -#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val) -#define pSPT0_MTCS3 ((uint32_t volatile *)SPT0_MTCS3) -#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3) -#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val) -#define pSPT0_MRCS0 ((uint32_t volatile *)SPT0_MRCS0) -#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0) -#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val) -#define pSPT0_MRCS1 ((uint32_t volatile *)SPT0_MRCS1) -#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1) -#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val) -#define pSPT0_MRCS2 ((uint32_t volatile *)SPT0_MRCS2) -#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2) -#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val) -#define pSPT0_MRCS3 ((uint32_t volatile *)SPT0_MRCS3) -#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3) -#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val) -#define pSPT0_MCMC1 ((uint16_t volatile *)SPT0_MCMC1) -#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1) -#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val) -#define pSPT0_MCMC2 ((uint16_t volatile *)SPT0_MCMC2) -#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2) -#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val) -#define pSPT0_CHNL ((uint16_t volatile *)SPT0_CHNL) -#define bfin_read_SPT0_CHNL() bfin_read16(SPT0_CHNL) -#define bfin_write_SPT0_CHNL(val) bfin_write16(SPT0_CHNL, val) -#define pSPT1_TX_CONFIG0 ((uint16_t volatile *)SPT1_TX_CONFIG0) -#define bfin_read_SPT1_TX_CONFIG0() bfin_read16(SPT1_TX_CONFIG0) -#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val) -#define pSPT1_TX_CONFIG1 ((uint16_t volatile *)SPT1_TX_CONFIG1) -#define bfin_read_SPT1_TX_CONFIG1() bfin_read16(SPT1_TX_CONFIG1) -#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val) -#define pSPT1_RX_CONFIG0 ((uint16_t volatile *)SPT1_RX_CONFIG0) -#define bfin_read_SPT1_RX_CONFIG0() bfin_read16(SPT1_RX_CONFIG0) -#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val) -#define pSPT1_RX_CONFIG1 ((uint16_t volatile *)SPT1_RX_CONFIG1) -#define bfin_read_SPT1_RX_CONFIG1() bfin_read16(SPT1_RX_CONFIG1) -#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val) -#define pSPT1_TX ((uint16_t volatile *)SPT1_TX) -#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX) -#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val) -#define pSPT1_RX ((uint16_t volatile *)SPT1_RX) -#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX) -#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val) -#define pSPT1_TSCLKDIV ((uint16_t volatile *)SPT1_TSCLKDIV) -#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV) -#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val) -#define pSPT1_RSCLKDIV ((uint16_t volatile *)SPT1_RSCLKDIV) -#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV) -#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val) -#define pSPT1_TFSDIV ((uint16_t volatile *)SPT1_TFSDIV) -#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV) -#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val) -#define pSPT1_RFSDIV ((uint16_t volatile *)SPT1_RFSDIV) -#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV) -#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val) -#define pSPT1_STAT ((uint16_t volatile *)SPT1_STAT) -#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT) -#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val) -#define pSPT1_MTCS0 ((uint32_t volatile *)SPT1_MTCS0) -#define bfin_read_SPT1_MTCS0() bfin_read32(SPT1_MTCS0) -#define bfin_write_SPT1_MTCS0(val) bfin_write32(SPT1_MTCS0, val) -#define pSPT1_MTCS1 ((uint32_t volatile *)SPT1_MTCS1) -#define bfin_read_SPT1_MTCS1() bfin_read32(SPT1_MTCS1) -#define bfin_write_SPT1_MTCS1(val) bfin_write32(SPT1_MTCS1, val) -#define pSPT1_MTCS2 ((uint32_t volatile *)SPT1_MTCS2) -#define bfin_read_SPT1_MTCS2() bfin_read32(SPT1_MTCS2) -#define bfin_write_SPT1_MTCS2(val) bfin_write32(SPT1_MTCS2, val) -#define pSPT1_MTCS3 ((uint32_t volatile *)SPT1_MTCS3) -#define bfin_read_SPT1_MTCS3() bfin_read32(SPT1_MTCS3) -#define bfin_write_SPT1_MTCS3(val) bfin_write32(SPT1_MTCS3, val) -#define pSPT1_MRCS0 ((uint32_t volatile *)SPT1_MRCS0) -#define bfin_read_SPT1_MRCS0() bfin_read32(SPT1_MRCS0) -#define bfin_write_SPT1_MRCS0(val) bfin_write32(SPT1_MRCS0, val) -#define pSPT1_MRCS1 ((uint32_t volatile *)SPT1_MRCS1) -#define bfin_read_SPT1_MRCS1() bfin_read32(SPT1_MRCS1) -#define bfin_write_SPT1_MRCS1(val) bfin_write32(SPT1_MRCS1, val) -#define pSPT1_MRCS2 ((uint32_t volatile *)SPT1_MRCS2) -#define bfin_read_SPT1_MRCS2() bfin_read32(SPT1_MRCS2) -#define bfin_write_SPT1_MRCS2(val) bfin_write32(SPT1_MRCS2, val) -#define pSPT1_MRCS3 ((uint32_t volatile *)SPT1_MRCS3) -#define bfin_read_SPT1_MRCS3() bfin_read32(SPT1_MRCS3) -#define bfin_write_SPT1_MRCS3(val) bfin_write32(SPT1_MRCS3, val) -#define pSPT1_MCMC1 ((uint16_t volatile *)SPT1_MCMC1) -#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1) -#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val) -#define pSPT1_MCMC2 ((uint16_t volatile *)SPT1_MCMC2) -#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2) -#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val) -#define pSPT1_CHNL ((uint16_t volatile *)SPT1_CHNL) -#define bfin_read_SPT1_CHNL() bfin_read16(SPT1_CHNL) -#define bfin_write_SPT1_CHNL(val) bfin_write16(SPT1_CHNL, val) -#define pPPI_CONTROL ((uint16_t volatile *)PPI_CONTROL) -#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL) -#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) -#define pPPI_STATUS ((uint16_t volatile *)PPI_STATUS) -#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) -#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define pPPI_DELAY ((uint16_t volatile *)PPI_DELAY) -#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) -#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) -#define pPPI_COUNT ((uint16_t volatile *)PPI_COUNT) -#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) -#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val) -#define pPPI_FRAME ((uint16_t volatile *)PPI_FRAME) -#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME) -#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val) -#define pPLL_CTL ((uint16_t volatile *)PLL_CTL) /* PLL Control register (16-bit) */ -#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL) -#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val) -#define pPLL_DIV ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register (16-bit) */ -#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) -#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) -#define pVR_CTL ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register (16-bit) */ -#define bfin_read_VR_CTL() bfin_read16(VR_CTL) -#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) -#define pPLL_STAT ((uint16_t volatile *)PLL_STAT) /* PLL Status register (16-bit) */ -#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) -#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) -#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */ -#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) -#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */ -#define bfin_read_SWRST() bfin_read16(SWRST) -#define bfin_write_SWRST(val) bfin_write16(SWRST, val) -#define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration register */ -#define bfin_read_SYSCR() bfin_read16(SYSCR) -#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE) -#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE) -#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val) -#define pCHIPID ((uint32_t volatile *)CHIPID) -#define bfin_read_CHIPID() bfin_read32(CHIPID) -#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) -#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */ -#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) -#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) -#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) /* Trace Buffer Status Register */ -#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) -#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) -#define pTBUF ((void * volatile *)TBUF) /* Trace Buffer */ -#define bfin_read_TBUF() bfin_readPTR(TBUF) -#define bfin_write_TBUF(val) bfin_writePTR(TBUF, val) -#define pPFCTL ((uint32_t volatile *)PFCTL) -#define bfin_read_PFCTL() bfin_read32(PFCTL) -#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) -#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) -#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) -#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) -#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) -#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) -#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) -#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */ -#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) -#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) -#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */ -#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) -#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) -#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */ -#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) -#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) -#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) -#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) -#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) -#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) -#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) -#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) -#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) -#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) -#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) -#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) -#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) -#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) -#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) -#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) -#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) -#define pRTC_PREN ((uint16_t volatile *)RTC_PREN) -#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) -#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val) -#define pSPI_CTL ((uint16_t volatile *)SPI_CTL) -#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) -#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) -#define pSPI_FLG ((uint16_t volatile *)SPI_FLG) -#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) -#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) -#define pSPI_STAT ((uint16_t volatile *)SPI_STAT) -#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) -#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) -#define pSPI_TDBR ((uint16_t volatile *)SPI_TDBR) -#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) -#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) -#define pSPI_RDBR ((uint16_t volatile *)SPI_RDBR) -#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) -#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) -#define pSPI_BAUD ((uint16_t volatile *)SPI_BAUD) -#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) -#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) -#define pSPI_SHADOW ((uint16_t volatile *)SPI_SHADOW) -#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) -#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) -#define pFIO_FLAG_D ((uint16_t volatile *)FIO_FLAG_D) -#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D) -#define bfin_write_FIO_FLAG_D(val) bfin_write16(FIO_FLAG_D, val) -#define pFIO_FLAG_C ((uint16_t volatile *)FIO_FLAG_C) -#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) -#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) -#define pFIO_FLAG_S ((uint16_t volatile *)FIO_FLAG_S) -#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) -#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) -#define pFIO_FLAG_T ((uint16_t volatile *)FIO_FLAG_T) -#define bfin_read_FIO_FLAG_T() bfin_read16(FIO_FLAG_T) -#define bfin_write_FIO_FLAG_T(val) bfin_write16(FIO_FLAG_T, val) -#define pFIO_MASKA_D ((uint16_t volatile *)FIO_MASKA_D) -#define bfin_read_FIO_MASKA_D() bfin_read16(FIO_MASKA_D) -#define bfin_write_FIO_MASKA_D(val) bfin_write16(FIO_MASKA_D, val) -#define pFIO_MASKA_C ((uint16_t volatile *)FIO_MASKA_C) -#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) -#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val) -#define pFIO_MASKA_S ((uint16_t volatile *)FIO_MASKA_S) -#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) -#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val) -#define pFIO_MASKA_T ((uint16_t volatile *)FIO_MASKA_T) -#define bfin_read_FIO_MASKA_T() bfin_read16(FIO_MASKA_T) -#define bfin_write_FIO_MASKA_T(val) bfin_write16(FIO_MASKA_T, val) -#define pFIO_MASKB_D ((uint16_t volatile *)FIO_MASKB_D) -#define bfin_read_FIO_MASKB_D() bfin_read16(FIO_MASKB_D) -#define bfin_write_FIO_MASKB_D(val) bfin_write16(FIO_MASKB_D, val) -#define pFIO_MASKB_C ((uint16_t volatile *)FIO_MASKB_C) -#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) -#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val) -#define pFIO_MASKB_S ((uint16_t volatile *)FIO_MASKB_S) -#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) -#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val) -#define pFIO_MASKB_T ((uint16_t volatile *)FIO_MASKB_T) -#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) -#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T, val) -#define pFIO_DIR ((uint16_t volatile *)FIO_DIR) -#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) -#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val) -#define pFIO_POLAR ((uint16_t volatile *)FIO_POLAR) -#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) -#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val) -#define pFIO_EDGE ((uint16_t volatile *)FIO_EDGE) -#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) -#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val) -#define pFIO_BOTH ((uint16_t volatile *)FIO_BOTH) -#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) -#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val) -#define pFIO_INEN ((uint16_t volatile *)FIO_INEN) -#define bfin_read_FIO_INEN() bfin_read16(FIO_INEN) -#define bfin_write_FIO_INEN(val) bfin_write16(FIO_INEN, val) -#define pSPORT0_TCR1 ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) -#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) -#define pSPORT0_TCR2 ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) -#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) -#define pSPORT0_TCLKDIV ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */ -#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) -#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) -#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */ -#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) -#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) -#define pSPORT0_TX ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */ -#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) -#define pSPORT0_RX ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */ -#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) -#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) -#define pSPORT0_RCR1 ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */ -#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) -#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) -#define pSPORT0_RCR2 ((uint16_t volatile *)SPORT0_RCR2) /* SPORT0 Transmit Configuration 2 Register */ -#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) -#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) -#define pSPORT0_RCLKDIV ((uint16_t volatile *)SPORT0_RCLKDIV) /* SPORT0 Receive Clock Divider */ -#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) -#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) -#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) /* SPORT0 Receive Frame Sync Divider */ -#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) -#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) -#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) /* SPORT0 Status Register */ -#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) -#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) -#define pSPORT0_CHNL ((uint16_t volatile *)SPORT0_CHNL) /* SPORT0 Current Channel Register */ -#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) -#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) -#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) /* SPORT0 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) -#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) -#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) /* SPORT0 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) -#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) -#define pSPORT1_TCR1 ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1) -#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val) -#define pSPORT1_TCR2 ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2) -#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val) -#define pSPORT1_TCLKDIV ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Clock Divider */ -#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV) -#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val) -#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider */ -#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) -#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) -#define pSPORT1_TX ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */ -#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val) -#define pSPORT1_RX ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */ -#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX) -#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val) -#define pSPORT1_RCR1 ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Transmit Configuration 1 Register */ -#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1) -#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val) -#define pSPORT1_RCR2 ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Transmit Configuration 2 Register */ -#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2) -#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val) -#define pSPORT1_RCLKDIV ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Clock Divider */ -#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV) -#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val) -#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider */ -#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) -#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) -#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */ -#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) -#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) -#define pSPORT1_CHNL ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */ -#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL) -#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val) -#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi-Channel Configuration Register 1 */ -#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) -#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) -#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi-Channel Configuration Register 2 */ -#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) -#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) -#define pDMA0_NEXT_DESC_PTR ((uint32_t volatile *)DMA0_NEXT_DESC_PTR) -#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR) -#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val) -#define pDMA0_START_ADDR ((uint32_t volatile *)DMA0_START_ADDR) -#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR) -#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val) -#define pDMA0_CONFIG ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */ -#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) -#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val) -#define pDMA0_X_COUNT ((uint16_t volatile *)DMA0_X_COUNT) -#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT) -#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val) -#define pDMA0_X_MODIFY ((uint16_t volatile *)DMA0_X_MODIFY) -#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY) -#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val) -#define pDMA0_Y_COUNT ((uint16_t volatile *)DMA0_Y_COUNT) -#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT) -#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val) -#define pDMA0_Y_MODIFY ((uint16_t volatile *)DMA0_Y_MODIFY) -#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY) -#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val) -#define pDMA0_CURR_DESC_PTR ((uint32_t volatile *)DMA0_CURR_DESC_PTR) -#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR) -#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val) -#define pDMA0_CURR_ADDR ((uint32_t volatile *)DMA0_CURR_ADDR) -#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR) -#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val) -#define pDMA0_IRQ_STATUS ((uint16_t volatile *)DMA0_IRQ_STATUS) -#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS) -#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val) -#define pDMA0_PERIPHERAL_MAP ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) -#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP) -#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val) -#define pDMA0_CURR_X_COUNT ((uint16_t volatile *)DMA0_CURR_X_COUNT) -#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT) -#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val) -#define pDMA0_CURR_Y_COUNT ((uint16_t volatile *)DMA0_CURR_Y_COUNT) -#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT) -#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val) -#define pDMA1_NEXT_DESC_PTR ((uint32_t volatile *)DMA1_NEXT_DESC_PTR) -#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR) -#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val) -#define pDMA1_START_ADDR ((uint32_t volatile *)DMA1_START_ADDR) -#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR) -#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val) -#define pDMA1_CONFIG ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */ -#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG) -#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val) -#define pDMA1_X_COUNT ((uint16_t volatile *)DMA1_X_COUNT) -#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT) -#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val) -#define pDMA1_X_MODIFY ((uint16_t volatile *)DMA1_X_MODIFY) -#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY) -#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val) -#define pDMA1_Y_COUNT ((uint16_t volatile *)DMA1_Y_COUNT) -#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT) -#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val) -#define pDMA1_Y_MODIFY ((uint16_t volatile *)DMA1_Y_MODIFY) -#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY) -#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val) -#define pDMA1_CURR_DESC_PTR ((uint32_t volatile *)DMA1_CURR_DESC_PTR) -#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR) -#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val) -#define pDMA1_CURR_ADDR ((uint32_t volatile *)DMA1_CURR_ADDR) -#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR) -#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val) -#define pDMA1_IRQ_STATUS ((uint16_t volatile *)DMA1_IRQ_STATUS) -#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS) -#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val) -#define pDMA1_PERIPHERAL_MAP ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) -#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP) -#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val) -#define pDMA1_CURR_X_COUNT ((uint16_t volatile *)DMA1_CURR_X_COUNT) -#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT) -#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val) -#define pDMA1_CURR_Y_COUNT ((uint16_t volatile *)DMA1_CURR_Y_COUNT) -#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT) -#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val) -#define pDMA2_NEXT_DESC_PTR ((uint32_t volatile *)DMA2_NEXT_DESC_PTR) -#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR) -#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val) -#define pDMA2_START_ADDR ((uint32_t volatile *)DMA2_START_ADDR) -#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR) -#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val) -#define pDMA2_CONFIG ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */ -#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG) -#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val) -#define pDMA2_X_COUNT ((uint16_t volatile *)DMA2_X_COUNT) -#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT) -#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val) -#define pDMA2_X_MODIFY ((uint16_t volatile *)DMA2_X_MODIFY) -#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY) -#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val) -#define pDMA2_Y_COUNT ((uint16_t volatile *)DMA2_Y_COUNT) -#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT) -#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val) -#define pDMA2_Y_MODIFY ((uint16_t volatile *)DMA2_Y_MODIFY) -#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY) -#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val) -#define pDMA2_CURR_DESC_PTR ((uint32_t volatile *)DMA2_CURR_DESC_PTR) -#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR) -#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val) -#define pDMA2_CURR_ADDR ((uint32_t volatile *)DMA2_CURR_ADDR) -#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR) -#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val) -#define pDMA2_IRQ_STATUS ((uint16_t volatile *)DMA2_IRQ_STATUS) -#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS) -#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val) -#define pDMA2_PERIPHERAL_MAP ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) -#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP) -#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val) -#define pDMA2_CURR_X_COUNT ((uint16_t volatile *)DMA2_CURR_X_COUNT) -#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT) -#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val) -#define pDMA2_CURR_Y_COUNT ((uint16_t volatile *)DMA2_CURR_Y_COUNT) -#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT) -#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val) -#define pDMA3_NEXT_DESC_PTR ((uint32_t volatile *)DMA3_NEXT_DESC_PTR) -#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR) -#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val) -#define pDMA3_START_ADDR ((uint32_t volatile *)DMA3_START_ADDR) -#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR) -#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val) -#define pDMA3_CONFIG ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */ -#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG) -#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val) -#define pDMA3_X_COUNT ((uint16_t volatile *)DMA3_X_COUNT) -#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT) -#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val) -#define pDMA3_X_MODIFY ((uint16_t volatile *)DMA3_X_MODIFY) -#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY) -#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val) -#define pDMA3_Y_COUNT ((uint16_t volatile *)DMA3_Y_COUNT) -#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT) -#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val) -#define pDMA3_Y_MODIFY ((uint16_t volatile *)DMA3_Y_MODIFY) -#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY) -#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val) -#define pDMA3_CURR_DESC_PTR ((uint32_t volatile *)DMA3_CURR_DESC_PTR) -#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR) -#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val) -#define pDMA3_CURR_ADDR ((uint32_t volatile *)DMA3_CURR_ADDR) -#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR) -#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val) -#define pDMA3_IRQ_STATUS ((uint16_t volatile *)DMA3_IRQ_STATUS) -#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS) -#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val) -#define pDMA3_PERIPHERAL_MAP ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) -#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP) -#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val) -#define pDMA3_CURR_X_COUNT ((uint16_t volatile *)DMA3_CURR_X_COUNT) -#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT) -#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val) -#define pDMA3_CURR_Y_COUNT ((uint16_t volatile *)DMA3_CURR_Y_COUNT) -#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT) -#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val) -#define pDMA4_NEXT_DESC_PTR ((uint32_t volatile *)DMA4_NEXT_DESC_PTR) -#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR) -#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val) -#define pDMA4_START_ADDR ((uint32_t volatile *)DMA4_START_ADDR) -#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR) -#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val) -#define pDMA4_CONFIG ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */ -#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG) -#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val) -#define pDMA4_X_COUNT ((uint16_t volatile *)DMA4_X_COUNT) -#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT) -#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val) -#define pDMA4_X_MODIFY ((uint16_t volatile *)DMA4_X_MODIFY) -#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY) -#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val) -#define pDMA4_Y_COUNT ((uint16_t volatile *)DMA4_Y_COUNT) -#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT) -#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val) -#define pDMA4_Y_MODIFY ((uint16_t volatile *)DMA4_Y_MODIFY) -#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY) -#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val) -#define pDMA4_CURR_DESC_PTR ((uint32_t volatile *)DMA4_CURR_DESC_PTR) -#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR) -#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val) -#define pDMA4_CURR_ADDR ((uint32_t volatile *)DMA4_CURR_ADDR) -#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR) -#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val) -#define pDMA4_IRQ_STATUS ((uint16_t volatile *)DMA4_IRQ_STATUS) -#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS) -#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val) -#define pDMA4_PERIPHERAL_MAP ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) -#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP) -#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val) -#define pDMA4_CURR_X_COUNT ((uint16_t volatile *)DMA4_CURR_X_COUNT) -#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT) -#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val) -#define pDMA4_CURR_Y_COUNT ((uint16_t volatile *)DMA4_CURR_Y_COUNT) -#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT) -#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val) -#define pDMA5_NEXT_DESC_PTR ((uint32_t volatile *)DMA5_NEXT_DESC_PTR) -#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR) -#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val) -#define pDMA5_START_ADDR ((uint32_t volatile *)DMA5_START_ADDR) -#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR) -#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val) -#define pDMA5_CONFIG ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */ -#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG) -#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val) -#define pDMA5_X_COUNT ((uint16_t volatile *)DMA5_X_COUNT) -#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT) -#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val) -#define pDMA5_X_MODIFY ((uint16_t volatile *)DMA5_X_MODIFY) -#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY) -#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val) -#define pDMA5_Y_COUNT ((uint16_t volatile *)DMA5_Y_COUNT) -#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) -#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val) -#define pDMA5_Y_MODIFY ((uint16_t volatile *)DMA5_Y_MODIFY) -#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY) -#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val) -#define pDMA5_CURR_DESC_PTR ((uint32_t volatile *)DMA5_CURR_DESC_PTR) -#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR) -#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val) -#define pDMA5_CURR_ADDR ((uint32_t volatile *)DMA5_CURR_ADDR) -#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR) -#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val) -#define pDMA5_IRQ_STATUS ((uint16_t volatile *)DMA5_IRQ_STATUS) -#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS) -#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val) -#define pDMA5_PERIPHERAL_MAP ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) -#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP) -#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val) -#define pDMA5_CURR_X_COUNT ((uint16_t volatile *)DMA5_CURR_X_COUNT) -#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT) -#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val) -#define pDMA5_CURR_Y_COUNT ((uint16_t volatile *)DMA5_CURR_Y_COUNT) -#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT) -#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val) -#define pDMA6_NEXT_DESC_PTR ((uint32_t volatile *)DMA6_NEXT_DESC_PTR) -#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR) -#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val) -#define pDMA6_START_ADDR ((uint32_t volatile *)DMA6_START_ADDR) -#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR) -#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val) -#define pDMA6_CONFIG ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */ -#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG) -#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val) -#define pDMA6_X_COUNT ((uint16_t volatile *)DMA6_X_COUNT) -#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT) -#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val) -#define pDMA6_X_MODIFY ((uint16_t volatile *)DMA6_X_MODIFY) -#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY) -#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val) -#define pDMA6_Y_COUNT ((uint16_t volatile *)DMA6_Y_COUNT) -#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT) -#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val) -#define pDMA6_Y_MODIFY ((uint16_t volatile *)DMA6_Y_MODIFY) -#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY) -#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val) -#define pDMA6_CURR_DESC_PTR ((uint32_t volatile *)DMA6_CURR_DESC_PTR) -#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR) -#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val) -#define pDMA6_CURR_ADDR ((uint32_t volatile *)DMA6_CURR_ADDR) -#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR) -#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val) -#define pDMA6_IRQ_STATUS ((uint16_t volatile *)DMA6_IRQ_STATUS) -#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS) -#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val) -#define pDMA6_PERIPHERAL_MAP ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) -#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP) -#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val) -#define pDMA6_CURR_X_COUNT ((uint16_t volatile *)DMA6_CURR_X_COUNT) -#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT) -#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val) -#define pDMA6_CURR_Y_COUNT ((uint16_t volatile *)DMA6_CURR_Y_COUNT) -#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT) -#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val) -#define pDMA7_NEXT_DESC_PTR ((uint32_t volatile *)DMA7_NEXT_DESC_PTR) -#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR) -#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val) -#define pDMA7_START_ADDR ((uint32_t volatile *)DMA7_START_ADDR) -#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR) -#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val) -#define pDMA7_CONFIG ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */ -#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG) -#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val) -#define pDMA7_X_COUNT ((uint16_t volatile *)DMA7_X_COUNT) -#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT) -#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val) -#define pDMA7_X_MODIFY ((uint16_t volatile *)DMA7_X_MODIFY) -#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY) -#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val) -#define pDMA7_Y_COUNT ((uint16_t volatile *)DMA7_Y_COUNT) -#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT) -#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val) -#define pDMA7_Y_MODIFY ((uint16_t volatile *)DMA7_Y_MODIFY) -#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY) -#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val) -#define pDMA7_CURR_DESC_PTR ((uint32_t volatile *)DMA7_CURR_DESC_PTR) -#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR) -#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val) -#define pDMA7_CURR_ADDR ((uint32_t volatile *)DMA7_CURR_ADDR) -#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR) -#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val) -#define pDMA7_IRQ_STATUS ((uint16_t volatile *)DMA7_IRQ_STATUS) -#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS) -#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val) -#define pDMA7_PERIPHERAL_MAP ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) -#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP) -#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val) -#define pDMA7_CURR_X_COUNT ((uint16_t volatile *)DMA7_CURR_X_COUNT) -#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT) -#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val) -#define pDMA7_CURR_Y_COUNT ((uint16_t volatile *)DMA7_CURR_Y_COUNT) -#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT) -#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val) -#define pMDMA_D0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D0_NEXT_DESC_PTR) -#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) -#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val) -#define pMDMA_D0_START_ADDR ((uint32_t volatile *)MDMA_D0_START_ADDR) -#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) -#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val) -#define pMDMA_D0_CONFIG ((uint16_t volatile *)MDMA_D0_CONFIG) -#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) -#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) -#define pMDMA_D0_X_COUNT ((uint16_t volatile *)MDMA_D0_X_COUNT) -#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) -#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) -#define pMDMA_D0_X_MODIFY ((uint16_t volatile *)MDMA_D0_X_MODIFY) -#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) -#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val) -#define pMDMA_D0_Y_COUNT ((uint16_t volatile *)MDMA_D0_Y_COUNT) -#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) -#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) -#define pMDMA_D0_Y_MODIFY ((uint16_t volatile *)MDMA_D0_Y_MODIFY) -#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) -#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val) -#define pMDMA_D0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D0_CURR_DESC_PTR) -#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) -#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val) -#define pMDMA_D0_CURR_ADDR ((uint32_t volatile *)MDMA_D0_CURR_ADDR) -#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) -#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val) -#define pMDMA_D0_IRQ_STATUS ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) -#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) -#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) -#define pMDMA_D0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) -#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) -#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val) -#define pMDMA_D0_CURR_X_COUNT ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) -#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT) -#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val) -#define pMDMA_D0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) -#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) -#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) -#define pMDMA_S0_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S0_NEXT_DESC_PTR) -#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) -#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val) -#define pMDMA_S0_START_ADDR ((uint32_t volatile *)MDMA_S0_START_ADDR) -#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) -#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val) -#define pMDMA_S0_CONFIG ((uint16_t volatile *)MDMA_S0_CONFIG) -#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) -#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) -#define pMDMA_S0_X_COUNT ((uint16_t volatile *)MDMA_S0_X_COUNT) -#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) -#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) -#define pMDMA_S0_X_MODIFY ((uint16_t volatile *)MDMA_S0_X_MODIFY) -#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) -#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val) -#define pMDMA_S0_Y_COUNT ((uint16_t volatile *)MDMA_S0_Y_COUNT) -#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) -#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) -#define pMDMA_S0_Y_MODIFY ((uint16_t volatile *)MDMA_S0_Y_MODIFY) -#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) -#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val) -#define pMDMA_S0_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S0_CURR_DESC_PTR) -#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) -#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val) -#define pMDMA_S0_CURR_ADDR ((uint32_t volatile *)MDMA_S0_CURR_ADDR) -#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) -#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val) -#define pMDMA_S0_IRQ_STATUS ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) -#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) -#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) -#define pMDMA_S0_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) -#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) -#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val) -#define pMDMA_S0_CURR_X_COUNT ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) -#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT) -#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val) -#define pMDMA_S0_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) -#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT) -#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val) -#define pMDMA_D1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_D1_NEXT_DESC_PTR) -#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) -#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val) -#define pMDMA_D1_START_ADDR ((uint32_t volatile *)MDMA_D1_START_ADDR) -#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) -#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val) -#define pMDMA_D1_CONFIG ((uint16_t volatile *)MDMA_D1_CONFIG) /* MemDMA Stream 1 Destination Configuration Register */ -#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) -#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) -#define pMDMA_D1_X_COUNT ((uint16_t volatile *)MDMA_D1_X_COUNT) -#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) -#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val) -#define pMDMA_D1_X_MODIFY ((uint16_t volatile *)MDMA_D1_X_MODIFY) -#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY) -#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val) -#define pMDMA_D1_Y_COUNT ((uint16_t volatile *)MDMA_D1_Y_COUNT) -#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT) -#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val) -#define pMDMA_D1_Y_MODIFY ((uint16_t volatile *)MDMA_D1_Y_MODIFY) -#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) -#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val) -#define pMDMA_D1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_D1_CURR_DESC_PTR) -#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) -#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val) -#define pMDMA_D1_CURR_ADDR ((uint32_t volatile *)MDMA_D1_CURR_ADDR) -#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) -#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val) -#define pMDMA_D1_IRQ_STATUS ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) -#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) -#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) -#define pMDMA_D1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) -#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) -#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val) -#define pMDMA_D1_CURR_X_COUNT ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) -#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT) -#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val) -#define pMDMA_D1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) -#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) -#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) -#define pMDMA_S1_NEXT_DESC_PTR ((uint32_t volatile *)MDMA_S1_NEXT_DESC_PTR) -#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) -#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val) -#define pMDMA_S1_START_ADDR ((uint32_t volatile *)MDMA_S1_START_ADDR) -#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) -#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val) -#define pMDMA_S1_CONFIG ((uint16_t volatile *)MDMA_S1_CONFIG) -#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) -#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) -#define pMDMA_S1_X_COUNT ((uint16_t volatile *)MDMA_S1_X_COUNT) -#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) -#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val) -#define pMDMA_S1_X_MODIFY ((uint16_t volatile *)MDMA_S1_X_MODIFY) -#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY) -#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val) -#define pMDMA_S1_Y_COUNT ((uint16_t volatile *)MDMA_S1_Y_COUNT) -#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT) -#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val) -#define pMDMA_S1_Y_MODIFY ((uint16_t volatile *)MDMA_S1_Y_MODIFY) -#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) -#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val) -#define pMDMA_S1_CURR_DESC_PTR ((uint32_t volatile *)MDMA_S1_CURR_DESC_PTR) -#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) -#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val) -#define pMDMA_S1_CURR_ADDR ((uint32_t volatile *)MDMA_S1_CURR_ADDR) -#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) -#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val) -#define pMDMA_S1_IRQ_STATUS ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) -#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) -#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) -#define pMDMA_S1_PERIPHERAL_MAP ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) -#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) -#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val) -#define pMDMA_S1_CURR_X_COUNT ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) -#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT) -#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val) -#define pMDMA_S1_CURR_Y_COUNT ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) -#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT) -#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val) -#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) -#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) -#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) -#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) -#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) -#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) -#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) -#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) -#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) -#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) -#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) -#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) -#define pEBIU_SDBCTL ((uint16_t volatile *)EBIU_SDBCTL) -#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL) -#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val) -#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) -#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) -#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) -#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) -#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) -#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) -#define pDMA_TC_CNT ((uint16_t volatile *)DMA_TC_CNT) -#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT) -#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val) -#define pDMA_TC_PER ((uint16_t volatile *)DMA_TC_PER) -#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER) -#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val) - -#endif /* __BFIN_CDEF_ADSP_EDN_extended__ */ diff --git a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h b/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h deleted file mode 100644 index 24b56b3876..0000000000 --- a/arch/blackfin/include/asm/mach-common/ADSP-EDN-extended_def.h +++ /dev/null @@ -1,543 +0,0 @@ -/* DO NOT EDIT THIS FILE - * Automatically generated by generate-def-headers.xsl - * DO NOT EDIT THIS FILE - */ - -#ifndef __BFIN_DEF_ADSP_EDN_extended__ -#define __BFIN_DEF_ADSP_EDN_extended__ - -#define ILAT 0xFFE0210C /* Interrupt Latch Register */ -#define IMASK 0xFFE02104 /* Interrupt Mask Register */ -#define IPEND 0xFFE02108 /* Interrupt Pending Register */ -#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ -#define TCNTL 0xFFE03000 /* Core Timer Control Register */ -#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ -#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ -#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ -#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ -#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ -#define DCPLB_FAULT_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */ -#define DCPLB_FAULT_ADDR 0xFFE0000C -#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ -#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ -#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ -#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ -#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ -#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ -#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ -#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ -#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ -#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ -#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ -#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ -#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ -#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ -#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ -#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ -#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ -#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ -#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ -#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ -#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ -#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ -#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ -#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ -#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ -#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ -#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ -#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ -#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ -#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ -#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ -#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ -#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ -#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ -#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ -#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ -#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ -#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ -#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ -#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ -#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ -#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ -#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ -#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ -#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ -#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ -#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ -#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ -#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ -#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ -#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ -#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ -#define ICPLB_FAULT_STATUS 0xFFE01008 -#define ICPLB_FAULT_ADDR 0xFFE0100C -#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ -#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ -#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ -#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ -#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ -#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ -#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ -#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ -#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ -#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ -#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ -#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ -#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ -#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ -#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ -#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ -#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ -#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ -#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ -#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ -#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ -#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ -#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ -#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ -#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ -#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ -#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ -#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ -#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ -#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ -#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ -#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ -#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ -#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ -#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ -#define MDMAFLX0_DMACNFG_D 0xFFC00E08 -#define MDMAFLX0_XCOUNT_D 0xFFC00E10 -#define MDMAFLX0_XMODIFY_D 0xFFC00E14 -#define MDMAFLX0_YCOUNT_D 0xFFC00E18 -#define MDMAFLX0_YMODIFY_D 0xFFC00E1C -#define MDMAFLX0_IRQSTAT_D 0xFFC00E28 -#define MDMAFLX0_PMAP_D 0xFFC00E2C -#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30 -#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38 -#define MDMAFLX0_DMACNFG_S 0xFFC00E48 -#define MDMAFLX0_XCOUNT_S 0xFFC00E50 -#define MDMAFLX0_XMODIFY_S 0xFFC00E54 -#define MDMAFLX0_YCOUNT_S 0xFFC00E58 -#define MDMAFLX0_YMODIFY_S 0xFFC00E5C -#define MDMAFLX0_IRQSTAT_S 0xFFC00E68 -#define MDMAFLX0_PMAP_S 0xFFC00E6C -#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70 -#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78 -#define MDMAFLX1_DMACNFG_D 0xFFC00E88 -#define MDMAFLX1_XCOUNT_D 0xFFC00E90 -#define MDMAFLX1_XMODIFY_D 0xFFC00E94 -#define MDMAFLX1_YCOUNT_D 0xFFC00E98 -#define MDMAFLX1_YMODIFY_D 0xFFC00E9C -#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8 -#define MDMAFLX1_PMAP_D 0xFFC00EAC -#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0 -#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8 -#define MDMAFLX1_DMACNFG_S 0xFFC00EC8 -#define MDMAFLX1_XCOUNT_S 0xFFC00ED0 -#define MDMAFLX1_XMODIFY_S 0xFFC00ED4 -#define MDMAFLX1_YCOUNT_S 0xFFC00ED8 -#define MDMAFLX1_YMODIFY_S 0xFFC00EDC -#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8 -#define MDMAFLX1_PMAP_S 0xFFC00EEC -#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0 -#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8 -#define DMAFLX0_DMACNFG 0xFFC00C08 -#define DMAFLX0_XCOUNT 0xFFC00C10 -#define DMAFLX0_XMODIFY 0xFFC00C14 -#define DMAFLX0_YCOUNT 0xFFC00C18 -#define DMAFLX0_YMODIFY 0xFFC00C1C -#define DMAFLX0_IRQSTAT 0xFFC00C28 -#define DMAFLX0_PMAP 0xFFC00C2C -#define DMAFLX0_CURXCOUNT 0xFFC00C30 -#define DMAFLX0_CURYCOUNT 0xFFC00C38 -#define DMAFLX1_DMACNFG 0xFFC00C48 -#define DMAFLX1_XCOUNT 0xFFC00C50 -#define DMAFLX1_XMODIFY 0xFFC00C54 -#define DMAFLX1_YCOUNT 0xFFC00C58 -#define DMAFLX1_YMODIFY 0xFFC00C5C -#define DMAFLX1_IRQSTAT 0xFFC00C68 -#define DMAFLX1_PMAP 0xFFC00C6C -#define DMAFLX1_CURXCOUNT 0xFFC00C70 -#define DMAFLX1_CURYCOUNT 0xFFC00C78 -#define DMAFLX2_DMACNFG 0xFFC00C88 -#define DMAFLX2_XCOUNT 0xFFC00C90 -#define DMAFLX2_XMODIFY 0xFFC00C94 -#define DMAFLX2_YCOUNT 0xFFC00C98 -#define DMAFLX2_YMODIFY 0xFFC00C9C -#define DMAFLX2_IRQSTAT 0xFFC00CA8 -#define DMAFLX2_PMAP 0xFFC00CAC -#define DMAFLX2_CURXCOUNT 0xFFC00CB0 -#define DMAFLX2_CURYCOUNT 0xFFC00CB8 -#define DMAFLX3_DMACNFG 0xFFC00CC8 -#define DMAFLX3_XCOUNT 0xFFC00CD0 -#define DMAFLX3_XMODIFY 0xFFC00CD4 -#define DMAFLX3_YCOUNT 0xFFC00CD8 -#define DMAFLX3_YMODIFY 0xFFC00CDC -#define DMAFLX3_IRQSTAT 0xFFC00CE8 -#define DMAFLX3_PMAP 0xFFC00CEC -#define DMAFLX3_CURXCOUNT 0xFFC00CF0 -#define DMAFLX3_CURYCOUNT 0xFFC00CF8 -#define DMAFLX4_DMACNFG 0xFFC00D08 -#define DMAFLX4_XCOUNT 0xFFC00D10 -#define DMAFLX4_XMODIFY 0xFFC00D14 -#define DMAFLX4_YCOUNT 0xFFC00D18 -#define DMAFLX4_YMODIFY 0xFFC00D1C -#define DMAFLX4_IRQSTAT 0xFFC00D28 -#define DMAFLX4_PMAP 0xFFC00D2C -#define DMAFLX4_CURXCOUNT 0xFFC00D30 -#define DMAFLX4_CURYCOUNT 0xFFC00D38 -#define DMAFLX5_DMACNFG 0xFFC00D48 -#define DMAFLX5_XCOUNT 0xFFC00D50 -#define DMAFLX5_XMODIFY 0xFFC00D54 -#define DMAFLX5_YCOUNT 0xFFC00D58 -#define DMAFLX5_YMODIFY 0xFFC00D5C -#define DMAFLX5_IRQSTAT 0xFFC00D68 -#define DMAFLX5_PMAP 0xFFC00D6C -#define DMAFLX5_CURXCOUNT 0xFFC00D70 -#define DMAFLX5_CURYCOUNT 0xFFC00D78 -#define DMAFLX6_DMACNFG 0xFFC00D88 -#define DMAFLX6_XCOUNT 0xFFC00D90 -#define DMAFLX6_XMODIFY 0xFFC00D94 -#define DMAFLX6_YCOUNT 0xFFC00D98 -#define DMAFLX6_YMODIFY 0xFFC00D9C -#define DMAFLX6_IRQSTAT 0xFFC00DA8 -#define DMAFLX6_PMAP 0xFFC00DAC -#define DMAFLX6_CURXCOUNT 0xFFC00DB0 -#define DMAFLX6_CURYCOUNT 0xFFC00DB8 -#define DMAFLX7_DMACNFG 0xFFC00DC8 -#define DMAFLX7_XCOUNT 0xFFC00DD0 -#define DMAFLX7_XMODIFY 0xFFC00DD4 -#define DMAFLX7_YCOUNT 0xFFC00DD8 -#define DMAFLX7_YMODIFY 0xFFC00DDC -#define DMAFLX7_IRQSTAT 0xFFC00DE8 -#define DMAFLX7_PMAP 0xFFC00DEC -#define DMAFLX7_CURXCOUNT 0xFFC00DF0 -#define DMAFLX7_CURYCOUNT 0xFFC00DF8 -#define TIMER0_CONFIG 0xFFC00600 -#define TIMER0_COUNTER 0xFFC00604 -#define TIMER0_PERIOD 0xFFC00608 -#define TIMER0_WIDTH 0xFFC0060C -#define TIMER1_CONFIG 0xFFC00610 -#define TIMER1_COUNTER 0xFFC00614 -#define TIMER1_PERIOD 0xFFC00618 -#define TIMER1_WIDTH 0xFFC0061C -#define TIMER2_CONFIG 0xFFC00620 -#define TIMER2_COUNTER 0xFFC00624 -#define TIMER2_PERIOD 0xFFC00628 -#define TIMER2_WIDTH 0xFFC0062C -#define TIMER_ENABLE 0xFFC00640 -#define TIMER_DISABLE 0xFFC00644 -#define TIMER_STATUS 0xFFC00648 -#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ -#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ -#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ -#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ -#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ -#define UART_THR 0xFFC00400 /* Transmit Holding */ -#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */ -#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */ -#define UART_IER 0xFFC00404 -#define UART_IIR 0xFFC00408 -#define UART_LCR 0xFFC0040C -#define UART_MCR 0xFFC00410 -#define UART_LSR 0xFFC00414 -#define UART_SCR 0xFFC0041C -#define UART_RBR 0xFFC00400 /* Receive Buffer */ -#define UART_GCTL 0xFFC00424 -#define SPT0_TX_CONFIG0 0xFFC00800 -#define SPT0_TX_CONFIG1 0xFFC00804 -#define SPT0_RX_CONFIG0 0xFFC00820 -#define SPT0_RX_CONFIG1 0xFFC00824 -#define SPT0_TX 0xFFC00810 -#define SPT0_RX 0xFFC00818 -#define SPT0_TSCLKDIV 0xFFC00808 -#define SPT0_RSCLKDIV 0xFFC00828 -#define SPT0_TFSDIV 0xFFC0080C -#define SPT0_RFSDIV 0xFFC0082C -#define SPT0_STAT 0xFFC00830 -#define SPT0_MTCS0 0xFFC00840 -#define SPT0_MTCS1 0xFFC00844 -#define SPT0_MTCS2 0xFFC00848 -#define SPT0_MTCS3 0xFFC0084C -#define SPT0_MRCS0 0xFFC00850 -#define SPT0_MRCS1 0xFFC00854 -#define SPT0_MRCS2 0xFFC00858 -#define SPT0_MRCS3 0xFFC0085C -#define SPT0_MCMC1 0xFFC00838 -#define SPT0_MCMC2 0xFFC0083C -#define SPT0_CHNL 0xFFC00834 -#define SPT1_TX_CONFIG0 0xFFC00900 -#define SPT1_TX_CONFIG1 0xFFC00904 -#define SPT1_RX_CONFIG0 0xFFC00920 -#define SPT1_RX_CONFIG1 0xFFC00924 -#define SPT1_TX 0xFFC00910 -#define SPT1_RX 0xFFC00918 -#define SPT1_TSCLKDIV 0xFFC00908 -#define SPT1_RSCLKDIV 0xFFC00928 -#define SPT1_TFSDIV 0xFFC0090C -#define SPT1_RFSDIV 0xFFC0092C -#define SPT1_STAT 0xFFC00930 -#define SPT1_MTCS0 0xFFC00940 -#define SPT1_MTCS1 0xFFC00944 -#define SPT1_MTCS2 0xFFC00948 -#define SPT1_MTCS3 0xFFC0094C -#define SPT1_MRCS0 0xFFC00950 -#define SPT1_MRCS1 0xFFC00954 -#define SPT1_MRCS2 0xFFC00958 -#define SPT1_MRCS3 0xFFC0095C -#define SPT1_MCMC1 0xFFC00938 -#define SPT1_MCMC2 0xFFC0093C -#define SPT1_CHNL 0xFFC00934 -#define PPI_CONTROL 0xFFC01000 -#define PPI_STATUS 0xFFC01004 -#define PPI_DELAY 0xFFC0100C -#define PPI_COUNT 0xFFC01008 -#define PPI_FRAME 0xFFC01010 -#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ -#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ -#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ -#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ -#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ -#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ -#define SYSCR 0xFFC00104 /* System Configuration register */ -#define EVT_OVERRIDE 0xFFE02100 -#define CHIPID 0xFFC00014 -#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ -#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ -#define TBUF 0xFFE06100 /* Trace Buffer */ -#define PFCTL 0xFFE08000 -#define PFCNTR0 0xFFE08100 -#define PFCNTR1 0xFFE08104 -#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ -#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ -#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ -#define RTC_STAT 0xFFC00300 -#define RTC_ICTL 0xFFC00304 -#define RTC_ISTAT 0xFFC00308 -#define RTC_SWCNT 0xFFC0030C -#define RTC_ALARM 0xFFC00310 -#define RTC_PREN 0xFFC00314 -#define SPI_CTL 0xFFC00500 -#define SPI_FLG 0xFFC00504 -#define SPI_STAT 0xFFC00508 -#define SPI_TDBR 0xFFC0050C -#define SPI_RDBR 0xFFC00510 -#define SPI_BAUD 0xFFC00514 -#define SPI_SHADOW 0xFFC00518 -#define FIO_FLAG_D 0xFFC00700 -#define FIO_FLAG_C 0xFFC00704 -#define FIO_FLAG_S 0xFFC00708 -#define FIO_FLAG_T 0xFFC0070C -#define FIO_MASKA_D 0xFFC00710 -#define FIO_MASKA_C 0xFFC00714 -#define FIO_MASKA_S 0xFFC00718 -#define FIO_MASKA_T 0xFFC0071C -#define FIO_MASKB_D 0xFFC00720 -#define FIO_MASKB_C 0xFFC00724 -#define FIO_MASKB_S 0xFFC00728 -#define FIO_MASKB_T 0xFFC0072C -#define FIO_DIR 0xFFC00730 -#define FIO_POLAR 0xFFC00734 -#define FIO_EDGE 0xFFC00738 -#define FIO_BOTH 0xFFC0073C -#define FIO_INEN 0xFFC00740 -#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ -#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ -#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ -#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ -#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ -#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ -#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ -#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ -#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ -#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ -#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ -#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ -#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ -#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ -#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ -#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ -#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ -#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ -#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ -#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ -#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ -#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ -#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ -#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ -#define DMA0_NEXT_DESC_PTR 0xFFC00C00 -#define DMA0_START_ADDR 0xFFC00C04 -#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ -#define DMA0_X_COUNT 0xFFC00C10 -#define DMA0_X_MODIFY 0xFFC00C14 -#define DMA0_Y_COUNT 0xFFC00C18 -#define DMA0_Y_MODIFY 0xFFC00C1C -#define DMA0_CURR_DESC_PTR 0xFFC00C20 -#define DMA0_CURR_ADDR 0xFFC00C24 -#define DMA0_IRQ_STATUS 0xFFC00C28 -#define DMA0_PERIPHERAL_MAP 0xFFC00C2C -#define DMA0_CURR_X_COUNT 0xFFC00C30 -#define DMA0_CURR_Y_COUNT 0xFFC00C38 -#define DMA1_NEXT_DESC_PTR 0xFFC00C40 -#define DMA1_START_ADDR 0xFFC00C44 -#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ -#define DMA1_X_COUNT 0xFFC00C50 -#define DMA1_X_MODIFY 0xFFC00C54 -#define DMA1_Y_COUNT 0xFFC00C58 -#define DMA1_Y_MODIFY 0xFFC00C5C -#define DMA1_CURR_DESC_PTR 0xFFC00C60 -#define DMA1_CURR_ADDR 0xFFC00C64 -#define DMA1_IRQ_STATUS 0xFFC00C68 -#define DMA1_PERIPHERAL_MAP 0xFFC00C6C -#define DMA1_CURR_X_COUNT 0xFFC00C70 -#define DMA1_CURR_Y_COUNT 0xFFC00C78 -#define DMA2_NEXT_DESC_PTR 0xFFC00C80 -#define DMA2_START_ADDR 0xFFC00C84 -#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ -#define DMA2_X_COUNT 0xFFC00C90 -#define DMA2_X_MODIFY 0xFFC00C94 -#define DMA2_Y_COUNT 0xFFC00C98 -#define DMA2_Y_MODIFY 0xFFC00C9C -#define DMA2_CURR_DESC_PTR 0xFFC00CA0 -#define DMA2_CURR_ADDR 0xFFC00CA4 -#define DMA2_IRQ_STATUS 0xFFC00CA8 -#define DMA2_PERIPHERAL_MAP 0xFFC00CAC -#define DMA2_CURR_X_COUNT 0xFFC00CB0 -#define DMA2_CURR_Y_COUNT 0xFFC00CB8 -#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 -#define DMA3_START_ADDR 0xFFC00CC4 -#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ -#define DMA3_X_COUNT 0xFFC00CD0 -#define DMA3_X_MODIFY 0xFFC00CD4 -#define DMA3_Y_COUNT 0xFFC00CD8 -#define DMA3_Y_MODIFY 0xFFC00CDC -#define DMA3_CURR_DESC_PTR 0xFFC00CE0 -#define DMA3_CURR_ADDR 0xFFC00CE4 -#define DMA3_IRQ_STATUS 0xFFC00CE8 -#define DMA3_PERIPHERAL_MAP 0xFFC00CEC -#define DMA3_CURR_X_COUNT 0xFFC00CF0 -#define DMA3_CURR_Y_COUNT 0xFFC00CF8 -#define DMA4_NEXT_DESC_PTR 0xFFC00D00 -#define DMA4_START_ADDR 0xFFC00D04 -#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ -#define DMA4_X_COUNT 0xFFC00D10 -#define DMA4_X_MODIFY 0xFFC00D14 -#define DMA4_Y_COUNT 0xFFC00D18 -#define DMA4_Y_MODIFY 0xFFC00D1C -#define DMA4_CURR_DESC_PTR 0xFFC00D20 -#define DMA4_CURR_ADDR 0xFFC00D24 -#define DMA4_IRQ_STATUS 0xFFC00D28 -#define DMA4_PERIPHERAL_MAP 0xFFC00D2C -#define DMA4_CURR_X_COUNT 0xFFC00D30 -#define DMA4_CURR_Y_COUNT 0xFFC00D38 -#define DMA5_NEXT_DESC_PTR 0xFFC00D40 -#define DMA5_START_ADDR 0xFFC00D44 -#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ -#define DMA5_X_COUNT 0xFFC00D50 -#define DMA5_X_MODIFY 0xFFC00D54 -#define DMA5_Y_COUNT 0xFFC00D58 -#define DMA5_Y_MODIFY 0xFFC00D5C -#define DMA5_CURR_DESC_PTR 0xFFC00D60 -#define DMA5_CURR_ADDR 0xFFC00D64 -#define DMA5_IRQ_STATUS 0xFFC00D68 -#define DMA5_PERIPHERAL_MAP 0xFFC00D6C -#define DMA5_CURR_X_COUNT 0xFFC00D70 -#define DMA5_CURR_Y_COUNT 0xFFC00D78 -#define DMA6_NEXT_DESC_PTR 0xFFC00D80 -#define DMA6_START_ADDR 0xFFC00D84 -#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ -#define DMA6_X_COUNT 0xFFC00D90 -#define DMA6_X_MODIFY 0xFFC00D94 -#define DMA6_Y_COUNT 0xFFC00D98 -#define DMA6_Y_MODIFY 0xFFC00D9C -#define DMA6_CURR_DESC_PTR 0xFFC00DA0 -#define DMA6_CURR_ADDR 0xFFC00DA4 -#define DMA6_IRQ_STATUS 0xFFC00DA8 -#define DMA6_PERIPHERAL_MAP 0xFFC00DAC -#define DMA6_CURR_X_COUNT 0xFFC00DB0 -#define DMA6_CURR_Y_COUNT 0xFFC00DB8 -#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 -#define DMA7_START_ADDR 0xFFC00DC4 -#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ -#define DMA7_X_COUNT 0xFFC00DD0 -#define DMA7_X_MODIFY 0xFFC00DD4 -#define DMA7_Y_COUNT 0xFFC00DD8 -#define DMA7_Y_MODIFY 0xFFC00DDC -#define DMA7_CURR_DESC_PTR 0xFFC00DE0 -#define DMA7_CURR_ADDR 0xFFC00DE4 -#define DMA7_IRQ_STATUS 0xFFC00DE8 -#define DMA7_PERIPHERAL_MAP 0xFFC00DEC -#define DMA7_CURR_X_COUNT 0xFFC00DF0 -#define DMA7_CURR_Y_COUNT 0xFFC00DF8 -#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 -#define MDMA_D0_START_ADDR 0xFFC00E04 -#define MDMA_D0_CONFIG 0xFFC00E08 -#define MDMA_D0_X_COUNT 0xFFC00E10 -#define MDMA_D0_X_MODIFY 0xFFC00E14 -#define MDMA_D0_Y_COUNT 0xFFC00E18 -#define MDMA_D0_Y_MODIFY 0xFFC00E1C -#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 -#define MDMA_D0_CURR_ADDR 0xFFC00E24 -#define MDMA_D0_IRQ_STATUS 0xFFC00E28 -#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C -#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 -#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 -#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 -#define MDMA_S0_START_ADDR 0xFFC00E44 -#define MDMA_S0_CONFIG 0xFFC00E48 -#define MDMA_S0_X_COUNT 0xFFC00E50 -#define MDMA_S0_X_MODIFY 0xFFC00E54 -#define MDMA_S0_Y_COUNT 0xFFC00E58 -#define MDMA_S0_Y_MODIFY 0xFFC00E5C -#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 -#define MDMA_S0_CURR_ADDR 0xFFC00E64 -#define MDMA_S0_IRQ_STATUS 0xFFC00E68 -#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C -#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 -#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 -#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 -#define MDMA_D1_START_ADDR 0xFFC00E84 -#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ -#define MDMA_D1_X_COUNT 0xFFC00E90 -#define MDMA_D1_X_MODIFY 0xFFC00E94 -#define MDMA_D1_Y_COUNT 0xFFC00E98 -#define MDMA_D1_Y_MODIFY 0xFFC00E9C -#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 -#define MDMA_D1_CURR_ADDR 0xFFC00EA4 -#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 -#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC -#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 -#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 -#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 -#define MDMA_S1_START_ADDR 0xFFC00EC4 -#define MDMA_S1_CONFIG 0xFFC00EC8 -#define MDMA_S1_X_COUNT 0xFFC00ED0 -#define MDMA_S1_X_MODIFY 0xFFC00ED4 -#define MDMA_S1_Y_COUNT 0xFFC00ED8 -#define MDMA_S1_Y_MODIFY 0xFFC00EDC -#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 -#define MDMA_S1_CURR_ADDR 0xFFC00EE4 -#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 -#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC -#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 -#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 -#define EBIU_AMGCTL 0xFFC00A00 -#define EBIU_AMBCTL0 0xFFC00A04 -#define EBIU_AMBCTL1 0xFFC00A08 -#define EBIU_SDGCTL 0xFFC00A10 -#define EBIU_SDBCTL 0xFFC00A14 -#define EBIU_SDRRC 0xFFC00A18 -#define EBIU_SDSTAT 0xFFC00A1C -#define DMA_TC_CNT 0xFFC00B0C -#define DMA_TC_PER 0xFFC00B10 - -#endif /* __BFIN_DEF_ADSP_EDN_extended__ */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 7643250da3..fcfd1746a5 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -254,7 +254,7 @@ void board_init_f(ulong bootflag) memset((void *)bd, 0, sizeof(bd_t)); bd->bi_r_version = version_string; - bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU); + bd->bi_cpu = BFIN_CPU; bd->bi_board_name = BFIN_BOARD_NAME; bd->bi_vco = get_vco(); bd->bi_cclk = get_cclk(); @@ -351,7 +351,7 @@ void board_init_r(gd_t * id, ulong dest_addr) #endif #ifdef CONFIG_GENERIC_MMC - puts("MMC: "); + puts("MMC: "); mmc_initialize(bd); #endif diff --git a/arch/i386/config.mk b/arch/i386/config.mk index 4b990e04ef..8743f1a663 100644 --- a/arch/i386/config.mk +++ b/arch/i386/config.mk @@ -25,4 +25,15 @@ CROSS_COMPILE ?= i386-linux- STANDALONE_LOAD_ADDR = 0x40000 +PLATFORM_CPPFLAGS += -fno-strict-aliasing +PLATFORM_CPPFLAGS += -Wstrict-prototypes +PLATFORM_CPPFLAGS += -mregparm=3 +PLATFORM_CPPFLAGS += -fomit-frame-pointer +PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding) +PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time)) +PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) +PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ + +LDFLAGS += --cref --gc-sections +PLATFORM_RELFLAGS += -ffunction-sections diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index bd6aced873..ae40384f09 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -37,6 +37,61 @@ #include <command.h> #include <asm/interrupt.h> +/* Constructor for a conventional segment GDT (or LDT) entry */ +/* This is a macro so it can be used in initializers */ +#define GDT_ENTRY(flags, base, limit) \ + ((((base) & 0xff000000ULL) << (56-24)) | \ + (((flags) & 0x0000f0ffULL) << 40) | \ + (((limit) & 0x000f0000ULL) << (48-16)) | \ + (((base) & 0x00ffffffULL) << 16) | \ + (((limit) & 0x0000ffffULL))) + +/* Simple and small GDT entries for booting only */ + +#define GDT_ENTRY_32BIT_CS 2 +#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1) +#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1) +#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1) + +/* + * Set up the GDT + */ + +struct gdt_ptr { + u16 len; + u32 ptr; +} __attribute__((packed)); + +static void reload_gdt(void) +{ + /* There are machines which are known to not boot with the GDT + being 8-byte unaligned. Intel recommends 16 byte alignment. */ + static const u64 boot_gdt[] __attribute__((aligned(16))) = { + /* CS: code, read/execute, 4 GB, base 0 */ + [GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff), + /* DS: data, read/write, 4 GB, base 0 */ + [GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff), + /* 16-bit CS: code, read/execute, 64 kB, base 0 */ + [GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff), + /* 16-bit DS: data, read/write, 64 kB, base 0 */ + [GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff), + }; + static struct gdt_ptr gdt; + + gdt.len = sizeof(boot_gdt)-1; + gdt.ptr = (u32)&boot_gdt; + + asm volatile("lgdtl %0\n" \ + "movl $((2+1)*8), %%ecx\n" \ + "movl %%ecx, %%ds\n" \ + "movl %%ecx, %%es\n" \ + "movl %%ecx, %%fs\n" \ + "movl %%ecx, %%gs\n" \ + "movl %%ecx, %%ss" \ + : : "m" (gdt) : "ecx"); +} + + int cpu_init_f(void) { /* initialize FPU, reset EM, set MP and NE */ @@ -51,6 +106,8 @@ int cpu_init_f(void) int cpu_init_r(void) { + reload_gdt(); + /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts (); return 0; diff --git a/arch/i386/cpu/interrupts.c b/arch/i386/cpu/interrupts.c index 51023f3a86..e4d0868cde 100644 --- a/arch/i386/cpu/interrupts.c +++ b/arch/i386/cpu/interrupts.c @@ -104,7 +104,7 @@ static inline unsigned long get_debugreg(int regno) return val; } -void dump_regs(struct pt_regs *regs) +void dump_regs(struct irq_regs *regs) { unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L; unsigned long d0, d1, d2, d3, d6, d7; @@ -225,7 +225,7 @@ int disable_interrupts(void) } /* IRQ Low-Level Service Routine */ -__isr__ irq_llsr(struct pt_regs *regs) +void irq_llsr(struct irq_regs *regs) { /* * For detailed description of each exception, refer to: @@ -234,7 +234,7 @@ __isr__ irq_llsr(struct pt_regs *regs) * Order Number: 253665-029US, November 2008 * Table 6-1. Exceptions and Interrupts */ - switch (regs->orig_eax) { + switch (regs->irq_id) { case 0x00: printf("Divide Error (Division by zero)\n"); dump_regs(regs); @@ -340,7 +340,7 @@ __isr__ irq_llsr(struct pt_regs *regs) default: /* Hardware or User IRQ */ - do_irq(regs->orig_eax); + do_irq(regs->irq_id); } } @@ -352,17 +352,30 @@ __isr__ irq_llsr(struct pt_regs *regs) * Interrupt entries are now very small (a push and a jump) but they are * now slower (all registers pushed on stack which provides complete * crash dumps in the low level handlers + * + * Interrupt Entry Point: + * - Interrupt has caused eflags, CS and EIP to be pushed + * - Interrupt Vector Handler has pushed orig_eax + * - pt_regs.esp needs to be adjusted by 40 bytes: + * 12 bytes pushed by CPU (EFLAGSF, CS, EIP) + * 4 bytes pushed by vector handler (irq_id) + * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX) + * NOTE: Only longs are pushed on/popped off the stack! */ asm(".globl irq_common_entry\n" \ ".hidden irq_common_entry\n" \ ".type irq_common_entry, @function\n" \ "irq_common_entry:\n" \ "cld\n" \ + "pushl %ss\n" \ "pushl %gs\n" \ "pushl %fs\n" \ "pushl %es\n" \ "pushl %ds\n" \ "pushl %eax\n" \ + "movl %esp, %eax\n" \ + "addl $40, %eax\n" \ + "pushl %eax\n" \ "pushl %ebp\n" \ "pushl %edi\n" \ "pushl %esi\n" \ @@ -370,12 +383,7 @@ asm(".globl irq_common_entry\n" \ "pushl %ecx\n" \ "pushl %ebx\n" \ "mov %esp, %eax\n" \ - "pushl %ebp\n" \ - "movl %esp,%ebp\n" \ - "pushl %eax\n" \ "call irq_llsr\n" \ - "popl %eax\n" \ - "leave\n"\ "popl %ebx\n" \ "popl %ecx\n" \ "popl %edx\n" \ @@ -383,10 +391,12 @@ asm(".globl irq_common_entry\n" \ "popl %edi\n" \ "popl %ebp\n" \ "popl %eax\n" \ + "popl %eax\n" \ "popl %ds\n" \ "popl %es\n" \ "popl %fs\n" \ "popl %gs\n" \ + "popl %ss\n" \ "add $4, %esp\n" \ "iret\n" \ DECLARE_INTERRUPT(0) \ diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 519bfd8b0c..7acd471d96 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -41,7 +41,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000; void init_sc520(void) { - /* Set the UARTxCTL register at it's slower, + /* + * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference */ writeb(0x07, &sc520_mmcr->uart1ctl); @@ -50,25 +51,30 @@ void init_sc520(void) /* first set the timer pin mapping */ writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */ - /* enable PCI bus arbitrer */ - writeb(0x02, &sc520_mmcr->sysarbctl); /* enable concurrent mode */ + /* enable PCI bus arbiter (concurrent mode) */ + writeb(0x02, &sc520_mmcr->sysarbctl); - writeb(0x1f, &sc520_mmcr->sysarbmenb); /* enable external grants */ - writeb(0x04, &sc520_mmcr->hbctl); /* enable posted-writes */ + /* enable external grants */ + writeb(0x1f, &sc520_mmcr->sysarbmenb); + + /* enable posted-writes */ + writeb(0x04, &sc520_mmcr->hbctl); if (CONFIG_SYS_SC520_HIGH_SPEED) { - writeb(0x02, &sc520_mmcr->cpuctl); /* set it to 133 MHz and write back */ + /* set it to 133 MHz and write back */ + writeb(0x02, &sc520_mmcr->cpuctl); gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); } else { - writeb(0x01, &sc520_mmcr->cpuctl); /* set it to 100 MHz and write back */ + /* set it to 100 MHz and write back */ + writeb(0x01, &sc520_mmcr->cpuctl); printf("## CPU Speed set to 100MHz\n"); gd->cpu_clk = 100000000; } /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" + asm("movl $0x2000, %%ecx\n" "0: pushl %%ecx\n" "popl %%ecx\n" "loop 0b\n": : : "ecx"); @@ -107,15 +113,15 @@ unsigned long init_sc520_dram(void) /* set SDRAM speed here */ - refresh_rate/=78; - if (refresh_rate<=1) { - val = 0; /* 7.8us */ - } else if (refresh_rate==2) { - val = 1; /* 15.6us */ - } else if (refresh_rate==3 || refresh_rate==4) { - val = 2; /* 31.2us */ + refresh_rate /= 78; + if (refresh_rate <= 1) { + val = 0; /* 7.8us */ + } else if (refresh_rate == 2) { + val = 1; /* 15.6us */ + } else if (refresh_rate == 3 || refresh_rate == 4) { + val = 2; /* 31.2us */ } else { - val = 3; /* 62.4us */ + val = 3; /* 62.4us */ } tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4); @@ -124,9 +130,9 @@ unsigned long init_sc520_dram(void) val = readb(&sc520_mmcr->drctmctl) & 0xf0; if (cas_precharge_delay==3) { - val |= 0x04; /* 3T */ + val |= 0x04; /* 3T */ } else if (cas_precharge_delay==4) { - val |= 0x08; /* 4T */ + val |= 0x08; /* 4T */ } else if (cas_precharge_delay>4) { val |= 0x0c; } @@ -139,8 +145,10 @@ unsigned long init_sc520_dram(void) writeb(val, &c520_mmcr->drctmctl); #endif - /* We read-back the configuration of the dram - * controller that the assembly code wrote */ + /* + * We read-back the configuration of the dram + * controller that the assembly code wrote + */ dram_ctrl = readl(&sc520_mmcr->drcbendadr); bd->bi_dram[0].start = 0; @@ -148,7 +156,6 @@ unsigned long init_sc520_dram(void) /* bank 0 enabled */ dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22; bd->bi_dram[0].size = bd->bi_dram[1].start; - } else { bd->bi_dram[0].size = 0; bd->bi_dram[1].start = bd->bi_dram[0].start; @@ -179,11 +186,6 @@ unsigned long init_sc520_dram(void) } else { bd->bi_dram[3].size = 0; } - - -#if 0 - printf("Configured %d bytes of dram\n", dram_present); -#endif gd->ram_size = dram_present; return dram_present; diff --git a/arch/i386/cpu/sc520/sc520_asm.S b/arch/i386/cpu/sc520/sc520_asm.S index fff56c00b4..63c14b7eb0 100644 --- a/arch/i386/cpu/sc520/sc520_asm.S +++ b/arch/i386/cpu/sc520/sc520_asm.S @@ -172,396 +172,373 @@ .equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */ .equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */ - - /* - * initialize dram controller registers - */ .globl mem_init mem_init: - xorw %ax,%ax - movl $DBCTL, %edi - movb %al, (%edi) /* disable write buffer */ + /* Preserve Boot Flags */ + movl %ebx, %ebp - movl $ECCCTL, %edi - movb %al, (%edi) /* disable ECC */ + /* initialize dram controller registers */ + xorw %ax, %ax + movl $DBCTL, %edi + movb %al, (%edi) /* disable write buffer */ - movl $DRCTMCTL, %edi - movb $0x1E,%al /* Set SDRAM timing for slowest */ - movb %al, (%edi) + movl $ECCCTL, %edi + movb %al, (%edi) /* disable ECC */ - /* - * setup loop to do 4 external banks starting with bank 3 - */ - movl $0xff000000,%eax /* enable last bank and setup */ - movl $DRCBENDADR, %edi /* ending address register */ - movl %eax, (%edi) + movl $DRCTMCTL, %edi + movb $0x1e, %al /* Set SDRAM timing for slowest */ + movb %al, (%edi) - movl $DRCCFG, %edi /* setup */ - movw $0xbbbb,%ax /* dram config register for */ - movw %ax, (%edi) + /* setup loop to do 4 external banks starting with bank 3 */ + movl $0xff000000, %eax /* enable last bank and setup */ + movl $DRCBENDADR, %edi /* ending address register */ + movl %eax, (%edi) - /* - * issue a NOP to all DRAMs - */ - movl $DRCCTL, %edi /* setup DRAM control register with */ - movb $0x1,%al /* Disable refresh,disable write buffer */ - movb %al, (%edi) - movl $CACHELINESZ, %esi /* just a dummy address to write for */ - movw %ax, (%esi) - /* - * delay for 100 usec? 200? - * ******this is a cludge for now ************* - */ - movw $100,%cx -sizdelay: - loop sizdelay /* we need 100 usec here */ - /***********************************************/ + movl $DRCCFG, %edi /* setup */ + movw $0xbbbb, %ax /* dram config register for */ + movw %ax, (%edi) - /* - * issue all banks precharge - */ - movb $0x2,%al /* All banks precharge */ - movb %al, (%edi) - movw %ax, (%esi) + /* issue a NOP to all DRAMs */ + movl $DRCCTL, %edi /* setup DRAM control register with */ + movb $0x01, %al /* Disable refresh,disable write buffer */ + movb %al, (%edi) + movl $CACHELINESZ, %esi /* just a dummy address to write for */ + movw %ax, (%esi) - /* - * issue 2 auto refreshes to all banks - */ - movb $0x4,%al /* Auto refresh cmd */ - movb %al, (%edi) - movw $2,%cx -refresh1: - movw %ax, (%esi) - loop refresh1 + /* delay for 100 usec? */ + movw $100, %cx +sizdelay: + loop sizdelay - /* - * issue LOAD MODE REGISTER command - */ - movb $0x3,%al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) + /* issue all banks precharge */ + movb $0x02, %al + movb %al, (%edi) + movw %ax, (%esi) - /* - * issue 8 more auto refreshes to all banks - */ - movb $0x4,%al /* Auto refresh cmd */ - movb %al, (%edi) - movw $8,%cx + /* issue 2 auto refreshes to all banks */ + movb $0x04, %al /* Auto refresh cmd */ + movb %al, (%edi) + movw $0x02, %cx +refresh1: + movw %ax, (%esi) + loop refresh1 + + /* issue LOAD MODE REGISTER command */ + movb $0x03, %al /* Load mode register cmd */ + movb %al, (%edi) + movw %ax, (%esi) + + /* issue 8 more auto refreshes to all banks */ + movb $0x04, %al /* Auto refresh cmd */ + movb %al, (%edi) + movw $0x0008, %cx refresh2: - movw %ax, (%esi) - loop refresh2 + movw %ax, (%esi) + loop refresh2 - /* - * set control register to NORMAL mode - */ - movb $0x0,%al /* Normal mode value */ - movb %al, (%edi) + /* set control register to NORMAL mode */ + movb $0x00, %al /* Normal mode value */ + movb %al, (%edi) - /* - * size dram starting with external bank 3 moving to external bank 0 - */ - movl $0x3,%ecx /* start with external bank 3 */ + /* + * size dram starting with external bank 3 + * moving to external bank 0 + */ + movl $0x3, %ecx /* start with external bank 3 */ nextbank: - /* - * write col 11 wrap adr - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ - movl %eax, (%esi) /* write max col pattern at max col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 10 wrap adr - */ + /* write col 11 wrap adr */ + movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ + movl $COL11_DATA, %eax /* pattern for max supported columns(11) */ + movl %eax, (%esi) /* write max col pattern at max col adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write col 10 wrap adr */ + movl $COL10_ADR, %esi /* set address to 10 col wrap address */ + movl $COL10_DATA, %eax /* pattern for 10 col wrap */ + movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write col 9 wrap adr */ + movl $COL09_ADR, %esi /* set address to 9 col wrap address */ + movl $COL09_DATA, %eax /* pattern for 9 col wrap */ + movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write col 8 wrap adr */ + movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ + movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ + movl %eax, (%esi) /* write min col pattern @ min col adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 14 wrap adr */ + movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ + movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ + movl %eax, (%esi) /* write max row pattern at max row adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 13 wrap adr */ + movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ + movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ + movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 12 wrap adr */ + movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ + movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ + movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ + movl (%esi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* write row 11 wrap adr */ + movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ + movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ + movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ + movl (%edi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ - movl $COL10_ADR, %esi /* set address to 10 col wrap address */ - movl $COL10_DATA, %eax /* pattern for 10 col wrap */ - movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 9 wrap adr - */ - movl $COL09_ADR, %esi /* set address to 9 col wrap address */ - movl $COL09_DATA, %eax /* pattern for 9 col wrap */ - movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write col 8 wrap adr - */ - movl $COL08_ADR, %esi /* set address to min(8) col wrap address */ - movl $COL08_DATA, %eax /* pattern for min (8) col wrap */ - movl %eax, (%esi) /* write min col pattern @ min col adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 14 wrap adr - */ - movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */ - movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */ - movl %eax, (%esi) /* write max row pattern at max row adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 13 wrap adr - */ - movl $ROW13_ADR, %esi /* set address to 13 row wrap address */ - movl $ROW13_DATA, %eax /* pattern for 13 row wrap */ - movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 12 wrap adr - */ - movl $ROW12_ADR, %esi /* set address to 12 row wrap address */ - movl $ROW12_DATA, %eax /* pattern for 12 row wrap */ - movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */ - movl (%esi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 11 wrap adr - */ - movl $ROW11_ADR, %edi /* set address to 11 row wrap address */ - movl $ROW11_DATA, %eax /* pattern for 11 row wrap */ - movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * write row 10 wrap adr --- this write is really to determine number of banks - */ - movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ - movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ - movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ - movl (%edi), %ebx /* optional read */ - cmpl %ebx,%eax /* to verify write */ - jnz bad_ram /* this ram is bad */ - /* - * read data @ row 12 wrap adr to determine * banks, - * and read data @ row 14 wrap adr to determine * rows. - * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. - * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 - * if data @ row 12 wrap == 11 or 12, we have 4 banks, - */ - xorw %di,%di /* value for 2 banks in DI */ - movl (%esi), %ebx /* read from 12 row wrap to check banks - * (esi is setup from the write to row 12 wrap) */ - cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */ - jz only2 /* if pattern == AA, we only have 2 banks */ + /* + * write row 10 wrap adr --- this write is really to determine + * number of banks + */ + movl $ROW10_ADR, %edi /* set address to 10 row wrap address */ + movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */ + movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */ + movl (%edi), %ebx /* optional read */ + cmpl %ebx, %eax /* to verify write */ + jnz bad_ram /* this ram is bad */ + + /* + * read data @ row 12 wrap adr to determine * banks, + * and read data @ row 14 wrap adr to determine * rows. + * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM. + * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 + * if data @ row 12 wrap == 11 or 12, we have 4 banks, + */ + xorw %di, %di /* value for 2 banks in DI */ + movl (%esi), %ebx /* read from 12 row wrap to check banks */ + /* (esi is setup from the write to row 12 wrap) */ + cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */ + jz only2 /* if pattern == AA, we only have 2 banks */ /* 4 banks */ - movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */ - cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ - jz only2 - cmpl $ROW12_DATA, %ebx /* and 12 */ - jnz bad_ram /* its bad if not 11 or 12! */ + movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */ + cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */ + jz only2 + cmpl $ROW12_DATA, %ebx /* and 12 */ + jnz bad_ram /* its bad if not 11 or 12! */ /* fall through */ only2: /* * validate row mask */ - movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ - movl (%esi), %eax /* read actual number of rows @ row14 adr */ + movl $ROW14_ADR, %esi /* set address back to max row wrap addr */ + movl (%esi), %eax /* read actual number of rows @ row14 adr */ - cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ - jb bad_ram + cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */ + jb bad_ram - cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ - ja bad_ram + cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */ + ja bad_ram + + cmpb %ah, %al /* verify all 4 bytes of dword same */ + jnz bad_ram + movl %eax, %ebx + shrl $16, %ebx + cmpw %bx, %ax + jnz bad_ram + + /* + * read col 11 wrap adr for real column data value + */ + movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ + movl (%esi), %eax /* read real col number at max col adr */ + + /* + * validate column data + */ + cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ + jb bad_ram + + cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ + ja bad_ram + + subl $COL08_DATA, %eax /* normalize column data to zero */ + jc bad_ram + cmpb %ah, %al /* verify all 4 bytes of dword equal */ + jnz bad_ram + movl %eax, %edx + shrl $16, %edx + cmpw %dx, %ax + jnz bad_ram + + /* + * merge bank and col data together + */ + addw %di, %dx /* merge of bank and col info in dl */ + + /* + * fix ending addr mask based upon col info + */ + movb $0x03, %al + subb %dh, %al /* dh contains the overflow from the bank/col merge */ + movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ + xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ + shrb %cl, %dh + incb %dh /* ending addr is 1 greater than real end */ + xchgw %cx, %ax /* cx is bank number again */ - cmpb %ah,%al /* verify all 4 bytes of dword same */ - jnz bad_ram - movl %eax,%ebx - shrl $16,%ebx - cmpw %bx,%ax - jnz bad_ram - /* - * read col 11 wrap adr for real column data value - */ - movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */ - movl (%esi), %eax /* read real col number at max col adr */ - /* - * validate column data - */ - cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */ - jb bad_ram - - cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */ - ja bad_ram - - subl $COL08_DATA, %eax /* normalize column data to zero */ - jc bad_ram - cmpb %ah,%al /* verify all 4 bytes of dword equal */ - jnz bad_ram - movl %eax,%edx - shrl $16,%edx - cmpw %dx,%ax - jnz bad_ram - /* - * merge bank and col data together - */ - addw %di,%dx /* merge of bank and col info in dl */ - /* - * fix ending addr mask based upon col info - */ - movb $3,%al - subb %dh,%al /* dh contains the overflow from the bank/col merge */ - movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */ - xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */ - shrb %cl,%dh /* */ - incb %dh /* ending addr is 1 greater than real end */ - xchgw %cx,%ax /* cx is bank number again */ - /* - * issue all banks precharge - */ bad_reint: - movl $DRCCTL, %esi /* setup DRAM control register with */ - movb $0x2,%al /* All banks precharge */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) + /* + * issue all banks precharge + */ + movl $DRCCTL, %esi /* setup DRAM control register with */ + movb $0x02, %al /* All banks precharge */ + movb %al, (%esi) + movl $CACHELINESZ, %esi /* address to init read buffer */ + movw %ax, (%esi) - /* - * update ENDING ADDRESS REGISTER - */ - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movl %ecx,%ebx + /* + * update ENDING ADDRESS REGISTER + */ + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl %ecx, %ebx addl %ebx, %edi - movb %dh, (%edi) - /* - * update CONFIG REGISTER - */ - xorb %dh,%dh - movw $0x00f,%bx - movw %cx,%ax - shlw $2,%ax - xchgw %cx,%ax - shlw %cl,%dx - shlw %cl,%bx - notw %bx - xchgw %cx,%ax - movl $DRCCFG, %edi - mov (%edi), %ax - andw %bx,%ax - orw %dx,%ax - movw %ax, (%edi) - jcxz cleanup - - decw %cx - movl %ecx,%ebx - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movb $0xff,%al + movb %dh, (%edi) + + /* + * update CONFIG REGISTER + */ + xorb %dh, %dh + movw $0x000f, %bx + movw %cx, %ax + shlw $2, %ax + xchgw %cx, %ax + shlw %cl, %dx + shlw %cl, %bx + notw %bx + xchgw %cx, %ax + movl $DRCCFG, %edi + movw (%edi), %ax + andw %bx, %ax + orw %dx, %ax + movw %ax, (%edi) + jcxz cleanup + + decw %cx + movl %ecx, %ebx + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movb $0xff, %al addl %ebx, %edi - movb %al, (%edi) - /* - * set control register to NORMAL mode - */ - movl $DRCCTL, %esi /* setup DRAM control register with */ - movb $0x0,%al /* Normal mode value */ - movb %al, (%esi) - movl $CACHELINESZ, %esi /* address to init read buffer */ - movw %ax, (%esi) - jmp nextbank + movb %al, (%edi) + + /* + * set control register to NORMAL mode + */ + movl $DRCCTL, %esi /* setup DRAM control register with */ + movb $0x00, %al /* Normal mode value */ + movb %al, (%esi) + movl $CACHELINESZ, %esi /* address to init read buffer */ + movw %ax, (%esi) + jmp nextbank cleanup: - movl $DRCBENDADR, %edi /* DRAM ending address register */ - movw $4,%cx - xorw %ax,%ax + movl $DRCBENDADR, %edi /* DRAM ending address register */ + movw $0x04, %cx + xorw %ax, %ax cleanuplp: - movb (%edi), %al - orb %al,%al - jz emptybank + movb (%edi), %al + orb %al, %al + jz emptybank - addb %ah,%al - jns nottoomuch + addb %ah, %al + jns nottoomuch - movb $0x7f,%al + movb $0x7f, %al nottoomuch: - movb %al,%ah - orb $0x80,%al - movb %al, (%edi) + movb %al, %ah + orb $0x80, %al + movb %al, (%edi) emptybank: - incl %edi - loop cleanuplp + incl %edi + loop cleanuplp #if defined CONFIG_SYS_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $DRCTMCTL, %edi - movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al - movb %al, (%edi) + movl $DRCTMCTL, %edi + movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al + movb %al, (%edi) #else #if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T) - /* set the CAS latency now since it is hard to do - * when we run from the RAM */ - movl $DRCTMCTL, %edi /* DRAM timing register */ - movb (%edi), %al + /* + * Set the CAS latency now since it is hard to do + * when we run from the RAM + */ + movl $DRCTMCTL, %edi /* DRAM timing register */ + movb (%edi), %al #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T - andb $0xef, %al + andb $0xef, %al #endif #ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T - orb $0x10, %al + orb $0x10, %al #endif - movb %al, (%edi) + movb %al, (%edi) #endif #endif - movl $DRCCTL, %edi /* DRAM Control register */ - movb $0x3,%al /* Load mode register cmd */ - movb %al, (%edi) - movw %ax, (%esi) + movl $DRCCTL, %edi /* DRAM Control register */ + movb $0x03, %al /* Load mode register cmd */ + movb %al, (%edi) + movw %ax, (%esi) - movl $DRCCTL, %edi /* DRAM Control register */ - movb $0x18,%al /* Enable refresh and NORMAL mode */ - movb %al, (%edi) + movl $DRCCTL, %edi /* DRAM Control register */ + movb $0x18, %al /* Enable refresh and NORMAL mode */ + movb %al, (%edi) - jmp dram_done + jmp dram_done bad_ram: - xorl %edx,%edx - xorl %edi,%edi - jmp bad_reint + xorl %edx, %edx + xorl %edi, %edi + jmp bad_reint dram_done: + /* Restore Boot Flags */ + movl %ebx, %ebp + jmp mem_init_ret #if CONFIG_SYS_SDRAM_ECC_ENABLE - /* - * We are in the middle of an existing 'call' - Need to store the - * existing return address before making another 'call' - */ - movl %ebp, %ebx - - /* Get the memory size */ - movl $init_ecc, %ebp - jmpl get_mem_size - +.globl init_ecc init_ecc: - /* Restore the orignal return address */ - movl %ebx, %ebp - /* A nominal memory test: just a byte at each address line */ - movl %eax, %ecx - shrl $0x1, %ecx + movl %eax, %ecx + shrl $0x1, %ecx movl $0x1, %edi memtest0: movb $0xa5, (%edi) - cmpb $0xa5, (%edi) + cmpb $0xa5, (%edi) jne out - shrl $1, %ecx - andl %ecx,%ecx + shrl $0x1, %ecx + andl %ecx, %ecx jz set_ecc - shll $1, %edi + shll $0x1, %edi jmp memtest0 set_ecc: @@ -570,25 +547,28 @@ set_ecc: xorl %esi, %esi xorl %edi, %edi xorl %eax, %eax - shrl $2, %ecx + shrl $0x2, %ecx cld rep stosl - /* enable read, write buffers */ - movb $0x11, %al - movl $DBCTL, %edi - movb %al, (%edi) - /* enable NMI mapping for ECC */ - movl $ECCINT, %edi - mov $0x10, %al - movb %al, (%edi) - /* Turn on ECC */ - movl $ECCCTL, %edi - mov $0x05, %al - movb %al, (%edi) -#endif + + /* enable read, write buffers */ + movb $0x11, %al + movl $DBCTL, %edi + movb %al, (%edi) + + /* enable NMI mapping for ECC */ + movl $ECCINT, %edi + movb $0x10, %al + movb %al, (%edi) + + /* Turn on ECC */ + movl $ECCCTL, %edi + movb $0x05, %al + movb %al,(%edi) out: - jmp *%ebp + jmp init_ecc_ret +#endif /* * Read and decode the sc520 DRCBENDADR MMCR and return the number of @@ -596,7 +576,7 @@ out: */ .globl get_mem_size get_mem_size: - movl $DRCBENDADR, %edi /* DRAM ending address register */ + movl $DRCBENDADR, %edi /* DRAM ending address register */ bank0: movl (%edi), %eax movl %eax, %ecx @@ -604,7 +584,7 @@ bank0: movl (%edi), %eax jz bank1 andl $0x0000007f, %eax shll $22, %eax - movl %eax, %ebx + movl %eax, %edx bank1: movl (%edi), %eax movl %eax, %ecx @@ -612,7 +592,7 @@ bank1: movl (%edi), %eax jz bank2 andl $0x00007f00, %eax shll $14, %eax - movl %eax, %ebx + movl %eax, %edx bank2: movl (%edi), %eax movl %eax, %ecx @@ -620,7 +600,7 @@ bank2: movl (%edi), %eax jz bank3 andl $0x007f0000, %eax shll $6, %eax - movl %eax, %ebx + movl %eax, %edx bank3: movl (%edi), %eax movl %eax, %ecx @@ -628,8 +608,8 @@ bank3: movl (%edi), %eax jz done andl $0x7f000000, %eax shrl $2, %eax - movl %eax, %ebx + movl %eax, %edx done: - movl %ebx, %eax - jmp *%ebp + movl %edx, %eax + jmp get_mem_size_ret diff --git a/arch/i386/cpu/start.S b/arch/i386/cpu/start.S index 7def8def8b..829468fe7e 100644 --- a/arch/i386/cpu/start.S +++ b/arch/i386/cpu/start.S @@ -1,7 +1,7 @@ /* * U-boot - i386 Startup Code * - * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se> + * Copyright (c) 2002 Omicron Ceti AB, Daniel Engstr�m <denaiel@omicron.se> * * See file CREDITS for list of people who contributed to this * project. @@ -25,6 +25,7 @@ #include <config.h> #include <version.h> +#include <asm/global_data.h> .section .text @@ -45,175 +46,98 @@ _i386boot_start: /* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000,%eax + orl $0x60000000, %eax movl %eax, %cr0 wbinvd /* Tell 32-bit code it is being entered from an in-RAM copy */ - movw $0x0000, %bx + movw $GD_FLG_WARM_BOOT, %bx _start: /* This is the 32-bit cold-reset entry point */ - movl $0x18,%eax /* Load our segement registes, the + movl $0x18, %eax /* Load our segement registes, the * gdt have already been loaded by start16.S */ - movw %ax,%fs - movw %ax,%ds - movw %ax,%gs - movw %ax,%es - movw %ax,%ss + movw %ax, %fs + movw %ax, %ds + movw %ax, %gs + movw %ax, %es + movw %ax, %ss /* Clear the interupt vectors */ lidt blank_idt_ptr - /* - * Skip low-level board and memory initialization if not starting - * from cold-reset. This allows us to do a fail safe boot-strap - * into a new build of U-Boot from a known-good boot flash - */ - movw $0x0001, %ax - cmpw %ax, %bx - jne mem_init_ret - - /* We call a few functions in the board support package - * since we have no stack yet we'll have to use %ebp - * to store the return address */ + /* Skip low-level initialization if not starting from cold-reset */ + movl %ebx, %ecx + andl $GD_FLG_COLD_BOOT, %ecx + jz skip_mem_init /* Early platform init (setup gpio, etc ) */ - mov $early_board_init_ret, %ebp jmp early_board_init +.globl early_board_init_ret early_board_init_ret: - /* The __port80 entry-point should be usabe by now */ - /* so we try to indicate progress */ - movw $0x01, %ax - movl $.progress0, %ebp - jmp show_boot_progress_asm -.progress0: - /* size memory */ - mov $mem_init_ret, %ebp - jmp mem_init + jmp mem_init +.globl mem_init_ret mem_init_ret: +skip_mem_init: /* fetch memory size (into %eax) */ - mov $get_mem_size_ret, %ebp - jmp get_mem_size + jmp get_mem_size +.globl get_mem_size_ret get_mem_size_ret: - /* - * We are now in 'Flat Protected Mode' and we know how much memory - * the board has. The (temporary) Global Descriptor Table is not - * in a 'Safe' place (it is either in Flash which can be erased or - * reprogrammed or in a fail-safe boot-strap image which could be - * over-written). - * - * Move the final gdt to a safe place (top of RAM) and load it. - * This is not a trivial excercise - the lgdt instruction does not - * have a register operand (memory only) and we may well be - * running from Flash, so self modifying code will not work here. - * To overcome this, we copy a stub into upper memory along with - * the GDT. - */ +#if CONFIG_SYS_SDRAM_ECC_ENABLE + /* Skip ECC initialization if not starting from cold-reset */ + movl %ebx, %ecx + andl $GD_FLG_COLD_BOOT, %ecx + jz init_ecc_ret + jmp init_ecc - /* Reduce upper memory limit by (Stub + GDT Pointer + GDT) */ - subl $(end_gdt_setup - start_gdt_setup), %eax - - /* Copy the GDT and Stub */ - movl $start_gdt_setup, %esi - movl %eax, %edi - movl $(end_gdt_setup - start_gdt_setup), %ecx - shrl $2, %ecx - cld - rep movsl +.globl init_ecc_ret +init_ecc_ret: +#endif - /* write the lgdt 'parameter' */ - subl $(jmp_instr - start_gdt_setup - 4), %ebp - addl %eax, %ebp - movl $(gdt_ptr - start_gdt_setup), %ebx - addl %eax, %ebx - movl %ebx, (%ebp) - - /* write the gdt address into the pointer */ - movl $(gdt_addr - start_gdt_setup), %ebp - addl %eax, %ebp - movl $(gdt - start_gdt_setup), %ebx - addl %eax, %ebx - movl %ebx, (%ebp) - - /* Save the return address */ - movl $load_gdt_ret, %ebp - - /* Load the new (safe) Global Descriptor Table */ - jmp *%eax - -load_gdt_ret: /* Check we have enough memory for stack */ movl $CONFIG_SYS_STACK_SIZE, %ecx cmpl %ecx, %eax - jae mem_ok - - /* indicate (lack of) progress */ - movw $0x81, %ax - movl $.progress0a, %ebp - jmp show_boot_progress_asm -.progress0a: - jmp die + jb die mem_ok: /* Set stack pointer to upper memory limit*/ - movl %eax, %esp - - /* indicate progress */ - movw $0x02, %ax - movl $.progress1, %ebp - jmp show_boot_progress_asm -.progress1: + movl %eax, %esp /* Test the stack */ pushl $0 - popl %eax - cmpl $0, %eax - jne no_stack + popl %ecx + cmpl $0, %ecx + jne die push $0x55aa55aa - popl %ebx - cmpl $0x55aa55aa, %ebx - je stack_ok - -no_stack: - /* indicate (lack of) progress */ - movw $0x82, %ax - movl $.progress1a, %ebp - jmp show_boot_progress_asm -.progress1a: - jmp die + popl %ecx + cmpl $0x55aa55aa, %ecx + jne die + wbinvd -stack_ok: - /* indicate progress */ - movw $0x03, %ax - movl $.progress2, %ebp - jmp show_boot_progress_asm -.progress2: + /* Determine our load offset */ + call 1f +1: popl %ecx + subl $1b, %ecx - wbinvd + /* Set the upper memory limit parameter */ + subl $CONFIG_SYS_STACK_SIZE, %eax - /* Get upper memory limit */ - movl %esp, %ecx - subl $CONFIG_SYS_STACK_SIZE, %ecx + /* Reserve space for global data */ + subl $(GD_SIZE * 4), %eax - /* Create a Stack Frame */ - pushl %ebp - movl %esp, %ebp + /* %eax points to the global data structure */ + movl %esp, (GD_RAM_SIZE * 4)(%eax) + movl %ebx, (GD_FLAGS * 4)(%eax) + movl %ecx, (GD_LOAD_OFF * 4)(%eax) - /* stack_limit parameter */ - pushl %ecx call board_init_f /* Enter, U-boot! */ /* indicate (lack of) progress */ movw $0x85, %ax - movl $.progress4a, %ebp - jmp show_boot_progress_asm -.progress4a: - die: hlt jmp die hlt @@ -221,52 +145,3 @@ die: hlt blank_idt_ptr: .word 0 /* limit */ .long 0 /* base */ - -.align 4 -start_gdt_setup: - lgdt gdt_ptr -jmp_instr: - jmp *%ebp - -.align 4 -gdt_ptr: - .word 0x30 /* limit (48 bytes = 6 GDT entries) */ -gdt_addr: - .long gdt /* base */ - - /* The GDT table ... - * - * Selector Type - * 0x00 NULL - * 0x08 Unused - * 0x10 32bit code - * 0x18 32bit data/stack - * 0x20 16bit code - * 0x28 16bit data/stack - */ - -.align 4 -gdt: - .word 0, 0, 0, 0 /* NULL */ - .word 0, 0, 0, 0 /* unused */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0 /* base address = 0 */ - .word 0x9B00 /* code read/exec */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 4Gb - (0x100000*0x1000 = 4Gb) */ - .word 0x0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9b00 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ - - .word 0xFFFF /* 64kb */ - .word 0 /* base address = 0 */ - .word 0x9300 /* data read/write */ - .word 0x0010 /* granularity = 1 (+5th nibble of limit) */ -end_gdt_setup: diff --git a/arch/i386/cpu/start16.S b/arch/i386/cpu/start16.S index ebe5835841..0a5823d3c2 100644 --- a/arch/i386/cpu/start16.S +++ b/arch/i386/cpu/start16.S @@ -22,6 +22,7 @@ * MA 02111-1307 USA */ +#include <asm/global_data.h> #define BOOT_SEG 0xffff0000 /* linear segment of boot code */ #define a32 .byte 0x67; @@ -31,16 +32,20 @@ .code16 .globl start16 start16: - /* First we let the BSP do some early initialization + /* Set the Cold Boot / Hard Reset flag */ + movl $GD_FLG_COLD_BOOT, %ebx + + /* + * First we let the BSP do some early initialization * this code have to map the flash to its final position */ - mov $board_init16_ret, %bp jmp board_init16 +.globl board_init16_ret board_init16_ret: /* Turn of cache (this might require a 486-class CPU) */ movl %cr0, %eax - orl $0x60000000,%eax + orl $0x60000000, %eax movl %eax, %cr0 wbinvd @@ -50,18 +55,15 @@ o32 cs lgdt gdt_ptr /* Now, we enter protected mode */ movl %cr0, %eax - orl $1,%eax + orl $1, %eax movl %eax, %cr0 /* Flush the prefetch queue */ jmp ff ff: - /* Tell 32-bit code it is being entered from hard-reset */ - movw $0x0001, %bx - /* Finally jump to the 32bit initialization code */ movw $code32start, %ax - movw %ax,%bp + movw %ax, %bp o32 cs ljmp *(%bp) /* 48-bit far pointer */ diff --git a/arch/i386/include/asm/config.h b/arch/i386/include/asm/config.h index 049c44eaf8..1952de79f8 100644 --- a/arch/i386/include/asm/config.h +++ b/arch/i386/include/asm/config.h @@ -21,4 +21,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index 3a9adc9c66..597112318f 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -33,12 +33,15 @@ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t) */ +#ifndef __ASSEMBLY__ + typedef struct { bd_t *bd; unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ unsigned long reloc_off; /* Relocation Offset */ + unsigned long load_off; /* Load Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long cpu_clk; /* CPU clock in Hz! */ @@ -49,6 +52,27 @@ typedef struct { char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; +extern gd_t *gd; + +#endif + +/* Word Offsets into Global Data - MUST match struct gd_t */ +#define GD_BD 0 +#define GD_FLAGS 1 +#define GD_BAUDRATE 2 +#define GD_HAVE_CONSOLE 3 +#define GD_RELOC_OFF 4 +#define GD_LOAD_OFF 5 +#define GD_ENV_ADDR 6 +#define GD_ENV_VALID 7 +#define GD_CPU_CLK 8 +#define GD_BUS_CLK 9 +#define GD_RAM_SIZE 10 +#define GD_RESET_STATUS 11 +#define GD_JT 12 + +#define GD_SIZE 13 + /* * Global Data Flags */ @@ -60,8 +84,9 @@ typedef struct { #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ #define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ +#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ +#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ -extern gd_t *gd; #define DECLARE_GLOBAL_DATA_PTR diff --git a/arch/i386/include/asm/interrupt.h b/arch/i386/include/asm/interrupt.h index 07426fe6a7..d32ef8b190 100644 --- a/arch/i386/include/asm/interrupt.h +++ b/arch/i386/include/asm/interrupt.h @@ -27,6 +27,8 @@ #ifndef __ASM_INTERRUPT_H_ #define __ASM_INTERRUPT_H_ 1 +#include <asm/types.h> + /* arch/i386/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); @@ -41,6 +43,4 @@ void specific_eoi(int irq); extern char exception_stack[]; -#define __isr__ void __attribute__ ((regparm(0))) - #endif diff --git a/arch/i386/include/asm/ptrace.h b/arch/i386/include/asm/ptrace.h index 750e40d030..a727dbfb05 100644 --- a/arch/i386/include/asm/ptrace.h +++ b/arch/i386/include/asm/ptrace.h @@ -1,6 +1,8 @@ #ifndef _I386_PTRACE_H #define _I386_PTRACE_H +#include <asm/types.h> + #define EBX 0 #define ECX 1 #define EDX 2 @@ -43,6 +45,28 @@ struct pt_regs { int xss; } __attribute__ ((packed)); +struct irq_regs { + /* Pushed by irq_common_entry */ + long ebx; + long ecx; + long edx; + long esi; + long edi; + long ebp; + long esp; + long eax; + long xds; + long xes; + long xfs; + long xgs; + long xss; + /* Pushed by vector handler (irq_<num>) */ + long irq_id; + /* Pushed by cpu in response to interrupt */ + long eip; + long xcs; + long eflags; +} __attribute__ ((packed)); /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ #define PTRACE_GETREGS 12 diff --git a/arch/i386/lib/bios_setup.c b/arch/i386/lib/bios_setup.c index a92b77ea23..75407c173c 100644 --- a/arch/i386/lib/bios_setup.c +++ b/arch/i386/lib/bios_setup.c @@ -45,8 +45,8 @@ DECLARE_GLOBAL_DATA_PTR; #define BIOS_BASE ((char*)0xf0000) #define BIOS_CS 0xf000 -extern ulong _i386boot_bios; -extern ulong _i386boot_bios_size; +extern ulong __bios_start; +extern ulong __bios_size; /* these are defined in a 16bit segment and needs * to be accessed with the RELOC_16_xxxx() macros below @@ -141,8 +141,8 @@ static void setvector(int vector, u16 segment, void *handler) int bios_setup(void) { - ulong i386boot_bios = (ulong)&_i386boot_bios + gd->reloc_off; - ulong i386boot_bios_size = (ulong)&_i386boot_bios_size; + ulong bios_start = (ulong)&__bios_start + gd->reloc_off; + ulong bios_size = (ulong)&__bios_size; static int done=0; int vector; @@ -154,13 +154,13 @@ int bios_setup(void) } done = 1; - if (i386boot_bios_size > 65536) { + if (bios_size > 65536) { printf("BIOS too large (%ld bytes, max is 65536)\n", - i386boot_bios_size); + bios_size); return -1; } - memcpy(BIOS_BASE, (void*)i386boot_bios, i386boot_bios_size); + memcpy(BIOS_BASE, (void*)bios_start, bios_size); /* clear bda */ memset(BIOS_DATA, 0, BIOS_DATA_SIZE); diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 5002203ec8..1129918fe2 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -48,13 +48,12 @@ DECLARE_GLOBAL_DATA_PTR; /* Exports from the Linker Script */ -extern ulong _i386boot_text_start; -extern ulong _i386boot_rel_dyn_start; -extern ulong _i386boot_rel_dyn_end; -extern ulong _i386boot_bss_start; -extern ulong _i386boot_bss_size; - -void ram_bootstrap (void *, ulong); +extern ulong __text_start; +extern ulong __data_end; +extern ulong __rel_dyn_start; +extern ulong __rel_dyn_end; +extern ulong __bss_start; +extern ulong __bss_end; const char version_string[] = U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; @@ -164,85 +163,77 @@ init_fnc_t *init_sequence[] = { NULL, }; -static gd_t gd_data; gd_t *gd; /* * Load U-Boot into RAM, initialize BSS, perform relocation adjustments */ -void board_init_f (ulong stack_limit) +void board_init_f (ulong gdp) { - void *text_start = &_i386boot_text_start; - void *u_boot_cmd_end = &__u_boot_cmd_end; - Elf32_Rel *rel_dyn_start = (Elf32_Rel *)&_i386boot_rel_dyn_start; - Elf32_Rel *rel_dyn_end = (Elf32_Rel *)&_i386boot_rel_dyn_end; - void *bss_start = &_i386boot_bss_start; - ulong bss_size = (ulong)&_i386boot_bss_size; - - ulong uboot_size; + void *text_start = &__text_start; + void *data_end = &__data_end; + void *rel_dyn_start = &__rel_dyn_start; + void *rel_dyn_end = &__rel_dyn_end; + void *bss_start = &__bss_start; + void *bss_end = &__bss_end; + + ulong *dst_addr; + ulong *src_addr; + ulong *end_addr; + void *dest_addr; ulong rel_offset; - Elf32_Rel *re; + Elf32_Rel *re_src; + Elf32_Rel *re_end; - void (*start_func)(void *, ulong); - - uboot_size = (ulong)u_boot_cmd_end - (ulong)text_start; - dest_addr = (void *)stack_limit - (uboot_size + (ulong)bss_size); + /* Calculate destination RAM Address and relocation offset */ + dest_addr = (void *)gdp - (bss_end - text_start); rel_offset = text_start - dest_addr; - start_func = ram_bootstrap - rel_offset; - /* First stage CPU initialization */ - if (cpu_init_f() != 0) - hang(); + /* Perform low-level initialization only when cold booted */ + if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) { + /* First stage CPU initialization */ + if (cpu_init_f() != 0) + hang(); - /* First stage Board initialization */ - if (board_early_init_f() != 0) - hang(); + /* First stage Board initialization */ + if (board_early_init_f() != 0) + hang(); + } /* Copy U-Boot into RAM */ - memcpy(dest_addr, text_start, uboot_size); + dst_addr = (ulong *)dest_addr; + src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off); + end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off); + + while (src_addr < end_addr) + *dst_addr++ = *src_addr++; /* Clear BSS */ - memset(bss_start - rel_offset, 0, bss_size); + dst_addr = (ulong *)(bss_start - rel_offset); + end_addr = (ulong *)(bss_end - rel_offset); + + while (dst_addr < end_addr) + *dst_addr++ = 0x00000000; /* Perform relocation adjustments */ - for (re = rel_dyn_start; re < rel_dyn_end; re++) - { - if (re->r_offset >= TEXT_BASE) - if (*(ulong *)re->r_offset >= TEXT_BASE) - *(ulong *)(re->r_offset - rel_offset) -= (Elf32_Addr)rel_offset; - } + re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off); + re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off); - /* Enter the relocated U-Boot! */ - start_func(dest_addr, rel_offset); - /* NOTREACHED - board_init_f() does not return */ - while(1); -} + do { + if (re_src->r_offset >= TEXT_BASE) + if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >= TEXT_BASE) + *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset; + } while (re_src++ < re_end); -/* - * We cannot initialize gd_data in board_init_f() because we would be - * attempting to write to flash (I have even tried using manual relocation - * adjustments on pointers but it just won't work) and board_init_r() does - * not have enough arguments to allow us to pass the relocation offset - * straight up. This bootstrap function (which runs in RAM) is used to - * setup gd_data in order to pass the relocation offset to the rest of - * U-Boot. - * - * TODO: The compiler optimization barrier is intended to stop GCC from - * optimizing this function into board_init_f(). It seems to work without - * it, but I've left it in to be sure. I think also that the barrier in - * board_init_r() is no longer needed, but left it in 'just in case' - */ -void ram_bootstrap (void *dest_addr, ulong rel_offset) -{ - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); + ((gd_t *)gdp)->reloc_off = rel_offset; + ((gd_t *)gdp)->flags |= GD_FLG_RELOC; - /* tell others: relocation done */ - gd_data.reloc_off = rel_offset; - gd_data.flags |= GD_FLG_RELOC; + /* Enter the relocated U-Boot! */ + (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr); - board_init_r(&gd_data, (ulong)dest_addr); + /* NOTREACHED - board_init_f() does not return */ + while(1); } void board_init_r(gd_t *id, ulong dest_addr) diff --git a/arch/i386/lib/realmode.c b/arch/i386/lib/realmode.c index b3f51230a5..60fe1816a1 100644 --- a/arch/i386/lib/realmode.c +++ b/arch/i386/lib/realmode.c @@ -31,23 +31,23 @@ #define REALMODE_MAILBOX ((char*)0xe00) -extern ulong _i386boot_realmode; -extern ulong _i386boot_realmode_size; +extern ulong __realmode_start; +extern ulong __realmode_size; extern char realmode_enter; int realmode_setup(void) { - ulong i386boot_realmode = (ulong)&_i386boot_realmode + gd->reloc_off; - ulong i386boot_realmode_size = (ulong)&_i386boot_realmode_size; + ulong realmode_start = (ulong)&__realmode_start + gd->reloc_off; + ulong realmode_size = (ulong)&__realmode_size; /* copy the realmode switch code */ - if (i386boot_realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { + if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) { printf("realmode switch too large (%ld bytes, max is %d)\n", - i386boot_realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); + realmode_size, (REALMODE_MAILBOX-REALMODE_BASE)); return -1; } - memcpy(REALMODE_BASE, (void*)i386boot_realmode, i386boot_realmode_size); + memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size); asm("wbinvd\n"); return 0; diff --git a/arch/i386/lib/zimage.c b/arch/i386/lib/zimage.c index 89fe015e6e..0c42072691 100644 --- a/arch/i386/lib/zimage.c +++ b/arch/i386/lib/zimage.c @@ -248,7 +248,8 @@ void boot_zimage(void *setup_base) int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { void *base_ptr; - void *bzImage_addr; + void *bzImage_addr = NULL; + char *s; ulong bzImage_size = 0; disable_interrupts(); @@ -256,10 +257,17 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Setup board for maximum PC/AT Compatibility */ setup_pcat_compatibility(); - /* argv[1] holds the address of the bzImage */ - bzImage_addr = (void *)simple_strtoul(argv[1], NULL, 16); + if (argc >= 2) + /* argv[1] holds the address of the bzImage */ + s = argv[1]; + else + s = getenv("fileaddr"); + + if (s) + bzImage_addr = (void *)simple_strtoul(s, NULL, 16); - if (argc == 3) + if (argc >= 3) + /* argv[2] holds the size of the bzImage */ bzImage_size = simple_strtoul(argv[2], NULL, 16); /* Lets look for*/ @@ -282,7 +290,7 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - zboot, 3, 0, do_zboot, + zboot, 2, 0, do_zboot, "Boot bzImage", "" ); diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index c29f5775bb..eba2435a59 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -73,10 +73,6 @@ DECLARE_GLOBAL_DATA_PTR; static char *failed = "*** failed ***\n"; -#ifdef CONFIG_PCU_E -extern flash_info_t flash_info[]; -#endif - #include <environment.h> extern ulong __init_end; diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c index fa4a0bc971..c4108af336 100644 --- a/arch/powerpc/cpu/mpc512x/diu.c +++ b/arch/powerpc/cpu/mpc512x/diu.c @@ -27,17 +27,10 @@ #include <command.h> #include <asm/io.h> -#include "../../../../board/freescale/common/fsl_diu_fb.h" - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) -#include <stdio_dev.h> -#include <video_fb.h> -#endif +#include <fsl_diu_fb.h> DECLARE_GLOBAL_DATA_PTR; -static int xres, yres; - void diu_set_pixel_clock(unsigned int pixclock) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; @@ -58,61 +51,20 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); } -int mpc5121_diu_init(void) +int platform_diu_init(unsigned int *xres, unsigned int *yres) { unsigned int pixel_format; #if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES) - xres = CONFIG_VIDEO_XRES; - yres = CONFIG_VIDEO_YRES; + *xres = CONFIG_VIDEO_XRES; + *yres = CONFIG_VIDEO_YRES; #else - xres = 1024; - yres = 768; + *xres = 1024; + *yres = 768; #endif pixel_format = 0x88883316; debug("mpc5121_diu_init\n"); - return fsl_diu_init(xres, pixel_format, 0); + return fsl_diu_init(*xres, pixel_format, 0); } - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - -/* - * The Graphic Device - */ -GraphicDevice ctfb; -void *video_hw_init(void) -{ - GraphicDevice *pGD = (GraphicDevice *) &ctfb; - struct fb_info *info; - - if (mpc5121_diu_init() < 0) - return NULL; - - /* fill in Graphic device struct */ - sprintf(pGD->modeIdent, "%dx%dx%d %dkHz %dHz", - xres, yres, 32, 64, 60); - - pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); - pGD->winSizeX = xres; - pGD->winSizeY = yres; - pGD->plnSizeX = pGD->winSizeX; - pGD->plnSizeY = pGD->winSizeY; - - pGD->gdfBytesPP = 4; - pGD->gdfIndex = GDF_32BIT_X888RGB; - - pGD->isaBase = 0; - pGD->pciBase = 0; - pGD->memSize = info->screen_size; - - /* Cursor Start Address */ - pGD->dprBase = 0; - pGD->vprBase = 0; - pGD->cprBase = 0; - - return (void *)pGD; -} - -#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index a6cfaa5971..df2504802a 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -81,10 +81,16 @@ struct liodn_id_table fman2_liodn_tbl[] = { #endif struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 146, 154), - SET_SEC_JR_LIODN_ENTRY(1, 147, 155), - SET_SEC_JR_LIODN_ENTRY(2, 178, 186), - SET_SEC_JR_LIODN_ENTRY(3, 179, 187), + /* + * We assume currently that all JR are in the same partition + * and as such they need to represent the same LIODN due to + * a 4080 rev.2 h/w requirement that DECOs sharing from themselves + * or from another DECO have the two Non-SEQ LIODN values equal + */ + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), /* (0, 146, 154), */ + SET_SEC_JR_LIODN_ENTRY(1, 146, 154), /* (1, 147, 155), */ + SET_SEC_JR_LIODN_ENTRY(2, 146, 154), /* (2, 178, 186), */ + SET_SEC_JR_LIODN_ENTRY(3, 146, 154), /* (3, 179, 187), */ SET_SEC_RTIC_LIODN_ENTRY(a, 144), SET_SEC_RTIC_LIODN_ENTRY(b, 145), SET_SEC_RTIC_LIODN_ENTRY(c, 176), diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index e97ae68c49..49b354d1ab 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -156,7 +156,6 @@ void cpu_init_f (volatile immap_t * immr) defined(CONFIG_IVMS8) || \ defined(CONFIG_LWMON) || \ defined(CONFIG_MHPC) || \ - defined(CONFIG_PCU_E) || \ defined(CONFIG_R360MPI) || \ defined(CONFIG_RMU) || \ defined(CONFIG_RPXCLASSIC) || \ diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 6009b0ce04..67f1fff7ef 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -250,6 +250,20 @@ static char *bootstrap_str[] = { }; static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; #endif +#if defined(CONFIG_APM821XX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "RESERVED", + "RESERVED", + "RESERVED", + "NAND (8 bits)", + "NOR (8 bits)", + "NOR (8 bits) w/PLL Bypassed", + "I2C (Addr 0x54)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' }; +#endif #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) @@ -590,6 +604,11 @@ int checkcpu (void) strcpy(addstr, "No Security support"); break; + case PVR_APM821XX_RA: + puts("APM821XX Rev. A"); + strcpy(addstr, "Security support"); + break; + case PVR_VIRTEX5: puts("440x5 VIRTEX5"); break; diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index d54b30e26f..2a727b1df3 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -237,7 +237,8 @@ cpu_init_f (void) reconfigure_pll(CONFIG_SYS_PLL_RECONFIG); -#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CONFIG_SYS_4xx_GPIO_TABLE) +#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \ + !defined(CONFIG_APM821XX) &&!defined(CONFIG_SYS_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -393,7 +394,7 @@ cpu_init_f (void) #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index abd4e910d2..09d6671d0d 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -189,7 +189,7 @@ ulong get_PCI_freq (void) #elif defined(CONFIG_440) #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) static u8 pll_fwdv_multi_bits[] = { /* values for: 1 - 16 */ 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c, @@ -250,6 +250,78 @@ u32 get_cpr0_fbdv(unsigned long cpr_reg_fbdv) return 0; } +#if defined(CONFIG_APM821XX) + +void get_sys_info(sys_info_t *sysInfo) +{ + unsigned long plld; + unsigned long temp; + unsigned long mul; + unsigned long cpudv; + unsigned long plb2dv; + unsigned long ddr2dv; + + /* Calculate Forward divisor A and Feeback divisor */ + mfcpr(CPR0_PLLD, plld); + + temp = CPR0_PLLD_FWDVA(plld); + sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); + + temp = CPR0_PLLD_FDV(plld); + sysInfo->pllFbkDiv = get_cpr0_fbdv(temp); + + /* Calculate OPB clock divisor */ + mfcpr(CPR0_OPBD, temp); + temp = CPR0_OPBD_OPBDV(temp); + sysInfo->pllOpbDiv = temp ? temp : 4; + + /* Calculate Peripheral clock divisor */ + mfcpr(CPR0_PERD, temp); + temp = CPR0_PERD_PERDV(temp); + sysInfo->pllExtBusDiv = temp ? temp : 4; + + /* Calculate CPU clock divisor */ + mfcpr(CPR0_CPUD, temp); + temp = CPR0_CPUD_CPUDV(temp); + cpudv = temp ? temp : 8; + + /* Calculate PLB2 clock divisor */ + mfcpr(CPR0_PLB2D, temp); + temp = CPR0_PLB2D_PLB2DV(temp); + plb2dv = temp ? temp : 4; + + /* Calculate DDR2 clock divisor */ + mfcpr(CPR0_DDR2D, temp); + temp = CPR0_DDR2D_DDR2DV(temp); + ddr2dv = temp ? temp : 4; + + /* Calculate 'M' based on feedback source */ + mfcpr(CPR0_PLLC, temp); + temp = CPR0_PLLC_SEL(temp); + if (temp == 0) { + /* PLL internal feedback */ + mul = sysInfo->pllFbkDiv; + } else { + /* PLL PerClk feedback */ + mul = sysInfo->pllFwdDivA * sysInfo->pllFbkDiv * cpudv + * plb2dv * 2 * sysInfo->pllOpbDiv * + sysInfo->pllExtBusDiv; + } + + /* Now calculate the individual clocks */ + sysInfo->freqVCOMhz = (mul * CONFIG_SYS_CLK_FREQ) + (mul >> 1); + sysInfo->freqProcessor = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv; + sysInfo->freqPLB = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / plb2dv / 2; + sysInfo->freqOPB = sysInfo->freqPLB / sysInfo->pllOpbDiv; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqDDR = sysInfo->freqVCOMhz / + sysInfo->pllFwdDivA / cpudv / ddr2dv / 2; + sysInfo->freqUART = sysInfo->freqPLB; +} + +#else /* * AMCC_TODO: verify this routine against latest EAS, cause stuff changed * with latest EAS @@ -307,6 +379,7 @@ void get_sys_info (sys_info_t * sysInfo) return; } +#endif #elif defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 7a65d9fcc6..c2d52bfb9f 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -703,7 +703,8 @@ _start: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r1, 0x0000 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ mtdcr L2_CACHE_CFG,r1 @@ -731,7 +732,8 @@ _start: lis r1, 0x8003 ori r1,r1, 0x0980 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ + defined(CONFIG_460GT) || defined(CONFIG_APM821XX) lis r1,0x0000 /* BAS = X_0000_0000 */ ori r1,r1,0x0984 /* first 64k */ mtdcr ISRAM0_SB0CR,r1 @@ -744,7 +746,8 @@ _start: lis r1, 0x0003 ori r1,r1, 0x0984 /* fourth 64k */ mtdcr ISRAM0_SB3CR,r1 -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) lis r2,0x7fff ori r2,r2,0xffff mfdcr r1,ISRAM1_DPC @@ -755,7 +758,7 @@ _start: mtdcr ISRAM1_PMEG,r1 lis r1,0x0004 /* BAS = 4_0004_0000 */ - ori r1,r1,0x0984 /* 64k */ + ori r1,r1,ISRAM1_SIZE /* ocm size */ mtdcr ISRAM1_SB0CR,r1 #endif #elif defined(CONFIG_460SX) diff --git a/arch/powerpc/include/asm/apm821xx.h b/arch/powerpc/include/asm/apm821xx.h new file mode 100644 index 0000000000..8841bc9386 --- /dev/null +++ b/arch/powerpc/include/asm/apm821xx.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _APM821XX_H_ +#define _APM821XX_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +/* Memory mapped registers */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +#define SDR0_SRST0_DMC 0x00200000 +#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ + +/* AHB config. */ +#define AHB_TOP 0xA4 +#define AHB_BOT 0xA5 + +/* clk divisors */ +#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ +#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ +#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ +#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ +#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ +#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/ +#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ + +/* + + * Clocking Controller + + */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24) +#define CPR0_PLLD 0x0060 +#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24) +#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16) +#define CPR0_CPUD 0x0080 +#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24) +#define CPR0_PLB2D 0x00a0 +#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25) +#define CPR0_OPBD 0x00c0 +#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24) +#define CPR0_PERD 0x00e0 +#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24) +#define CPR0_DDR2D 0x0100 +#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25) +#define CLK_ICFG 0x0140 + +#endif /* _APM821XX_H_ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3dd2b7f53a..30c64ebb17 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1589,7 +1589,9 @@ typedef struct cpc_corenet { u32 cpcerreaddr; /* error extended address */ u32 cpcerraddr; /* error address */ u32 cpcerrctl; /* error control */ - u32 res9[105]; /* pad out to 4k */ + u32 res9[41]; /* pad out to 4k */ + u32 cpchdbcr0; /* hardware debug control register 0 */ + u32 res10[63]; /* pad out to 4k */ } cpc_corenet_t; #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ @@ -1616,6 +1618,7 @@ typedef struct cpc_corenet { #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a #define CPC_SRCR0_SRAMEN 0x00000001 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h index 252f35bdc6..6c214726bb 100644 --- a/arch/powerpc/include/asm/ppc440epx_grx.h +++ b/arch/powerpc/include/asm/ppc440epx_grx.h @@ -36,6 +36,8 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) diff --git a/arch/powerpc/include/asm/ppc4xx-ebc.h b/arch/powerpc/include/asm/ppc4xx-ebc.h index 9c17e46252..75af13000e 100644 --- a/arch/powerpc/include/asm/ppc4xx-ebc.h +++ b/arch/powerpc/include/asm/ppc4xx-ebc.h @@ -69,7 +69,8 @@ #define EBC_NUM_BANKS 6 #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_APM821XX) #define EBC_NUM_BANKS 3 #endif diff --git a/arch/powerpc/include/asm/ppc4xx-isram.h b/arch/powerpc/include/asm/ppc4xx-isram.h index d6d17ac961..32e1297d01 100644 --- a/arch/powerpc/include/asm/ppc4xx-isram.h +++ b/arch/powerpc/include/asm/ppc4xx-isram.h @@ -25,7 +25,8 @@ /* * Internal SRAM */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_APM821XX) #define ISRAM0_DCR_BASE 0x380 #else #define ISRAM0_DCR_BASE 0x020 @@ -42,7 +43,8 @@ #define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */ #define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) #define ISRAM1_DCR_BASE 0x0B0 #define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/ #define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */ @@ -54,13 +56,19 @@ #define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */ #endif /* CONFIG_460EX || CONFIG_460GT */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define ISRAM1_SIZE 0x0984 /* OCM size 64k */ +#elif defined(CONFIG_APM821XX) +#define ISRAM1_SIZE 0x0784 /* OCM size 32k */ +#endif + /* * L2 Cache */ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define L2_CACHE_BASE 0x030 #define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index ac150c268d..d570d7915e 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -292,7 +292,7 @@ */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -365,7 +365,7 @@ /* * Memory controller registers */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -375,9 +375,9 @@ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#else /* CONFIG_405EX */ +#else /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCSTAT 0x14 /* memory controller status */ -#endif /* CONFIG_405EX */ +#endif /* CONFIG_405EX || CONFIG_APM821XX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ @@ -423,12 +423,12 @@ #define SDRAM_MEMODE 0x89 /* memory extended mode */ #define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ -#ifndef CONFIG_405EX +#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX) #define SDRAM_RID 0xA8 /* revision ID */ #endif #define SDRAM_FCSR 0xB0 /* feedback calibration status */ #define SDRAM_RTSR 0xB1 /* run time status tracking */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX) #define SDRAM_RID 0xF8 /* revision ID */ #endif diff --git a/arch/powerpc/include/asm/ppc4xx-uic.h b/arch/powerpc/include/asm/ppc4xx-uic.h index 782d0454b7..3714a0a4f1 100644 --- a/arch/powerpc/include/asm/ppc4xx-uic.h +++ b/arch/powerpc/include/asm/ppc4xx-uic.h @@ -31,7 +31,7 @@ */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) + defined(CONFIG_460SX) || defined(CONFIG_APM821XX) #define UIC_MAX 4 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_405EX) @@ -252,7 +252,8 @@ #define VECNUM_ETH0 (32 + 28) #endif /* CONFIG_440SPE */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_APM821XX) /* UIC 0 */ #define VECNUM_UIC2NCI 10 #define VECNUM_UIC2CI 11 diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h index 87a16ec986..633f793c9b 100644 --- a/arch/powerpc/include/asm/ppc4xx.h +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -79,10 +79,13 @@ #include <asm/ppc460sx.h> #endif +#if defined(CONFIG_APM821XX) +#include <asm/apm821xx.h> +#endif + /* * Configure which SDRAM/DDR/DDR2 controller is equipped */ -// test-only: what to do with these??? #if defined(CONFIG_AP1000) || defined(CONFIG_ML2) #define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ #endif @@ -202,22 +205,6 @@ #define GPT0_DCT0 0x00000110 #define GPT0_DCIS 0x0000011C -#if 0 // test-only -/* - * All PPC4xx share the same NS16550 UART(s). Only base addresses - * may differ. We define here the integration of the common NS16550 - * driver for all PPC4xx SoC's. The board config header must specify - * on which UART the console should be located via CONFIG_CONS_INDEX. - */ -#if 0 /* test-only */ -#define CONFIG_SERIAL_MULTI -#endif -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#endif - #if defined(CONFIG_440) #include <asm/ppc440.h> #else diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 84a1e2ec0d..9cafe85f19 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -916,6 +916,7 @@ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ +#define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 8f6a7c9d43..bfdfa86249 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -107,7 +107,7 @@ void doc_init (void); static char *failed = "*** failed ***\n"; -#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU) +#if defined(CONFIG_OXC) || defined(CONFIG_RMU) extern flash_info_t flash_info[]; #endif @@ -681,11 +681,10 @@ void board_init_r (gd_t *id, ulong dest_addr) unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ #endif -#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) /* - * Do PCI configuration on BAB7xx and CPC45 _before_ the flash - * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus - * bridge there. + * Do early PCI configuration _before_ the flash gets initialised, + * because PCU ressources are crucial for flash access on some boards. */ pci_init (); #endif @@ -735,7 +734,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif -# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU) +# if defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = TEXT_BASE + flash_size; # elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE @@ -856,7 +855,7 @@ void board_init_r (gd_t *id, ulong dest_addr) WATCHDOG_RESET (); -#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45) +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) /* * Do pci configuration */ diff --git a/board/siemens/CCM/Makefile b/board/amcc/bluestone/Makefile index c5695f98cb..41751c870b 100644 --- a/board/siemens/CCM/Makefile +++ b/board/amcc/bluestone/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri@apm.com> # # See file CREDITS for list of people who contributed to this # project. @@ -23,22 +23,18 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqc/tqm8xx) -endif - LIB = $(obj)lib$(BOARD).a -COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \ - ../../tqc/tqm8xx/load_sernum_ethaddr.o +COBJS-y := $(BOARD).o +SOBJS := init.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c new file mode 100644 index 0000000000..fe8929c389 --- /dev/null +++ b/board/amcc/bluestone/bluestone.c @@ -0,0 +1,111 @@ +/* + * Bluestone board support + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/apm821xx.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <asm/ppc4xx-gpio.h> + +int board_early_init_f(void) +{ + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + mtdcr(UIC0ER, 0x00000000); /* disable all */ + mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC0SR, 0xffffffff); /* clear all */ + + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + mtdcr(UIC1ER, 0x00000000); /* disable all */ + mtdcr(UIC1CR, 0x00000000); /* all non-critical */ + mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC1SR, 0xffffffff); /* clear all */ + + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + mtdcr(UIC2ER, 0x00000000); /* disable all */ + mtdcr(UIC2CR, 0x00000000); /* all non-critical */ + mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC2SR, 0xffffffff); /* clear all */ + + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + mtdcr(UIC3ER, 0x00000000); /* disable all */ + mtdcr(UIC3CR, 0x00000000); /* all non-critical */ + mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */ + mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */ + mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(UIC3SR, 0xffffffff); /* clear all */ + + /* + * Configure PFC (Pin Function Control) registers + * UART0: 2 pins + */ + mtsdr(SDR0_PFC1, 0x0000000); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: Bluestone Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +int misc_init_r(void) +{ + u32 sdr0_srst1 = 0; + + /* Setup PLB4-AHB bridge based on the system address map */ + mtdcr(AHB_TOP, 0x8000004B); + mtdcr(AHB_BOT, 0x8000004B); + + /* + * The AHB Bridge core is held in reset after power-on or reset + * so enable it now + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_AHB; + mtsdr(SDR0_SRST1, sdr0_srst1); + + return 0; +} diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk new file mode 100644 index 0000000000..e2194e4e00 --- /dev/null +++ b/board/amcc/bluestone/config.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2010, Applied Micro Circuits Corporation +# Author: Tirumala R Marri <tmarri@apm.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Applied Micro APM821XX Evaluation board. +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S new file mode 100644 index 0000000000..e969fcfd90 --- /dev/null +++ b/board/amcc/bluestone/init.S @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm/mmu.h> +#include <asm/ppc4xx.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* TLB 0 */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, + 4, AC_RWX | SA_G) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_RWX | SA_G) + + /* TLB-entry for OCM */ + tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4, + AC_RWX | SA_I) + + /* TLB-entry for Local Configuration registers => peripherals */ + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, + CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG) + tlbtab_end diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index b26cadb6bb..faa3720df3 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -34,16 +34,16 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch DECLARE_GLOBAL_DATA_PTR; - struct board_bcsr { - u8 board_id; - u8 cpld_rev; - u8 led_user; - u8 board_status; - u8 reset_ctrl; - u8 flash_ctrl; - u8 eth_ctrl; - u8 usb_ctrl; - u8 irq_ctrl; +struct board_bcsr { + u8 board_id; + u8 cpld_rev; + u8 led_user; + u8 board_status; + u8 reset_ctrl; + u8 flash_ctrl; + u8 eth_ctrl; + u8 usb_ctrl; + u8 irq_ctrl; }; #define BOARD_CANYONLANDS_PCIE 1 @@ -195,16 +195,6 @@ int board_early_init_f(void) mtdcr(AHB_TOP, 0x8000004B); mtdcr(AHB_BOT, 0x8000004B); - if (pvr_460ex()) { - /* - * Configure USB-STP pins as alternate and not GPIO - * It seems to be neccessary to configure the STP pins as GPIO - * input at powerup (perhaps while USB reset is asserted). So - * we configure those pins to their "real" function now. - */ - gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); - } #endif return 0; @@ -222,6 +212,15 @@ int usb_board_init(void) val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); out_8(&bcsr_data->usb_ctrl, val); + /* + * Configure USB-STP pins as alternate and not GPIO + * It seems to be neccessary to configure the STP pins as GPIO + * input at powerup (perhaps while USB reset is asserted). So + * we configure those pins to their "real" function now. + */ + gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); + return 0; } @@ -236,6 +235,10 @@ int usb_board_stop(void) val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST); out_8(&bcsr_data->usb_ctrl, val); + /* Reconfigure USB-STP pins as input */ + gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0); + gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0); + return 0; } diff --git a/board/bct-brettl2/Makefile b/board/bct-brettl2/Makefile new file mode 100644 index 0000000000..cf99d29f1c --- /dev/null +++ b/board/bct-brettl2/Makefile @@ -0,0 +1,51 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o gpio_cfi_flash.o cled.o +COBJS-$(CONFIG_BFIN_MAC) += smsc9303.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c new file mode 100644 index 0000000000..de5b9ff0e7 --- /dev/null +++ b/board/bct-brettl2/bct-brettl2.c @@ -0,0 +1,123 @@ +/* + * U-boot - main board file for BCT brettl2 + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <command.h> +#include <asm/blackfin.h> +#include <asm/portmux.h> +#include <asm/gpio.h> +#include <asm/net.h> +#include <net.h> +#include <netdev.h> +#include <miiphy.h> + +#include "../cm-bf537e/gpio_cfi_flash.h" +#include "smsc9303.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: bct-brettl2 board\n"); + printf(" Support: http://www.bct-electronic.com/\n"); + return 0; +} + +#ifdef CONFIG_BFIN_MAC +static void board_init_enetaddr(uchar *mac_addr) +{ + puts("Warning: Generating 'random' MAC address\n"); + bfin_gen_rand_mac(mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +int board_eth_init(bd_t *bis) +{ + int retry = 3; + int ret; + + ret = bfin_EMAC_initialize(bis); + + uchar enetaddr[6]; + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + printf("setting MAC %pM\n", enetaddr); + } + puts(" "); + + puts("initialize SMSC LAN9303i ethernet switch\n"); + + while (retry-- > 0) { + if (init_smsc9303i_mii()) + return ret; + } + + return ret; +} +#endif + +static void init_tlv320aic31(void) +{ + puts("Audio: setup TIMER0 to enable 16.384 MHz clock for tlv320aic31\n"); + peripheral_request(P_TMR0, "tlv320aic31 clock"); + bfin_write_TIMER0_CONFIG(0x020d); + bfin_write_TIMER0_PERIOD(0x0008); + bfin_write_TIMER0_WIDTH(0x0008/2); + bfin_write_TIMER_ENABLE(bfin_read_TIMER_ENABLE() | 1); + SSYNC(); + udelay(10000); + + puts(" resetting tlv320aic31\n"); + + gpio_request(GPIO_PF2, "tlv320aic31"); + gpio_direction_output(GPIO_PF2, 0); + udelay(10000); + gpio_direction_output(GPIO_PF2, 1); + udelay(10000); + gpio_free(GPIO_PF2); +} + +static void init_mute_pin(void) +{ + printf(" unmute class D amplifier\n"); + + gpio_request(GPIO_PF5, "mute"); + gpio_direction_output(GPIO_PF5, 1); + gpio_free(GPIO_PF5); +} + +/* sometimes LEDs (speech, status) are still on after reboot, turn 'em off */ +static void turn_leds_off(void) +{ + printf(" turn LEDs off\n"); + + gpio_request(GPIO_PF6, "led"); + gpio_direction_output(GPIO_PF6, 0); + gpio_free(GPIO_PF6); + + gpio_request(GPIO_PF15, "led"); + gpio_direction_output(GPIO_PF15, 0); + gpio_free(GPIO_PF15); +} + +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ +#ifdef CONFIG_BFIN_MAC + uchar enetaddr[6]; + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + board_init_enetaddr(enetaddr); +#endif + + gpio_cfi_flash_init(); + init_tlv320aic31(); + init_mute_pin(); + turn_leds_off(); + + return 0; +} diff --git a/board/bct-brettl2/cled.c b/board/bct-brettl2/cled.c new file mode 100644 index 0000000000..9e73c57b87 --- /dev/null +++ b/board/bct-brettl2/cled.c @@ -0,0 +1,32 @@ +/* + * cled.c - control color led + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <command.h> +#include <asm/blackfin.h> +#include <asm/io.h> + +int do_cled(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr = 0x20000000 + 0x200000; // AMS2 + uchar data; + + if (argc < 2) + return cmd_usage(cmdtp); + + data = simple_strtoul(argv[1], NULL, 10); + outb(data, addr); + + printf("cled, write %02x\n", data); + + return 0; +} + +U_BOOT_CMD(cled, 2, 0, do_cled, + "set/clear color LED", + ""); diff --git a/board/siemens/CCM/config.mk b/board/bct-brettl2/config.mk index 9c72c79d3b..dfd94569e1 100644 --- a/board/siemens/CCM/config.mk +++ b/board/bct-brettl2/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -21,8 +23,13 @@ # MA 02111-1307 USA # -# -# TQM8xxL boards -# +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf536-0.3 + +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 -TEXT_BASE = 0x40000000 +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bct-brettl2/gpio_cfi_flash.c b/board/bct-brettl2/gpio_cfi_flash.c new file mode 100644 index 0000000000..b385c7fc0e --- /dev/null +++ b/board/bct-brettl2/gpio_cfi_flash.c @@ -0,0 +1,4 @@ +#define GPIO_PIN_1 GPIO_PG5 +#define GPIO_PIN_2 GPIO_PG6 +#define GPIO_PIN_3 GPIO_PG7 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/bct-brettl2/smsc9303.c b/board/bct-brettl2/smsc9303.c new file mode 100644 index 0000000000..15eea7a484 --- /dev/null +++ b/board/bct-brettl2/smsc9303.c @@ -0,0 +1,176 @@ +/* + * smsc9303.c - routines to initialize SMSC 9303 switch + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <config.h> +#include <miiphy.h> + +#include <asm/blackfin.h> +#include <asm/gpio.h> + +static int smc9303i_write_mii(unsigned char addr, unsigned char reg, unsigned short data) +{ + const char *devname = miiphy_get_current_dev(); + + if (!devname) + return 0; + + if (miiphy_write(devname, addr, reg, data) != 0) + return 0; + + return 1; +} + +static int smc9303i_write_reg(unsigned short reg, unsigned int data) +{ + const char *devname = miiphy_get_current_dev(); + unsigned char mii_addr = 0x10 | (reg >> 6); + unsigned char mii_reg = (reg & 0x3c) >> 1; + + if (!devname) + return 0; + + if (miiphy_write(devname, mii_addr, mii_reg|0, data & 0xffff) != 0) + return 0; + + if (miiphy_write(devname, mii_addr, mii_reg|1, data >> 16) != 0) + return 0; + + return 1; +} + +static int smc9303i_read_reg(unsigned short reg, unsigned int *data) +{ + const char *devname = miiphy_get_current_dev(); + unsigned char mii_addr = 0x10 | (reg >> 6); + unsigned char mii_reg = (reg & 0x3c) >> 1; + unsigned short tmp1, tmp2; + + if (!devname) + return 0; + + if (miiphy_read(devname, mii_addr, mii_reg|0, &tmp1) != 0) + return 0; + + if (miiphy_read(devname, mii_addr, mii_reg|1, &tmp2) != 0) + return 0; + + *data = (tmp2 << 16) | tmp1; + + return 1; +} + +#if 0 +static int smc9303i_read_mii(unsigned char addr, unsigned char reg, unsigned short *data) +{ + const char *devname = miiphy_get_current_dev(); + + if (!devname) + return 0; + + if (miiphy_read(devname, addr, reg, data) != 0) + return 0; + + return 1; +} +#endif + +typedef struct { + unsigned short reg; + unsigned int value; +} smsc9303i_config_entry1_t; + +static const smsc9303i_config_entry1_t smsc9303i_config_table1[] = +{ + {0x1a0, 0x00000006}, /* Port 1 Manual Flow Control Register */ + {0x1a4, 0x00000006}, /* Port 2 Manual Flow Control Register */ + {0x1a8, 0x00000006}, /* Port 0 Manual Flow Control Register */ +}; + +typedef struct +{ + unsigned char addr; + unsigned char reg; + unsigned short value; +} smsc9303i_config_entry2_t; + +static const smsc9303i_config_entry2_t smsc9303i_config_table2[] = +{ + {0x01, 0x00, 0x0100}, /* Port0 PHY Basic Control Register */ + {0x02, 0x00, 0x1100}, /* Port1 PHY Basic Control Register */ + {0x03, 0x00, 0x1100}, /* Port2 PHY Basic Control Register */ + + {0x01, 0x04, 0x0001}, /* Port0 PHY Auto-Negotiation Advertisement Register */ + {0x02, 0x04, 0x2de1}, /* Port1 PHY Auto-Negotiation Advertisement Register */ + {0x03, 0x04, 0x2de1}, /* Port2 PHY Auto-Negotiation Advertisement Register */ + + {0x01, 0x11, 0x0000}, /* Port0 PHY Mode Control/Status Register */ + {0x02, 0x11, 0x0000}, /* Port1 PHY Mode Control/Status Register */ + {0x03, 0x11, 0x0000}, /* Port2 PHY Mode Control/Status Register */ + + {0x01, 0x12, 0x0021}, /* Port0 PHY Special Modes Register */ + {0x02, 0x12, 0x00e2}, /* Port1 PHY Special Modes Register */ + {0x03, 0x12, 0x00e3}, /* Port2 PHY Special Modes Register */ + {0x01, 0x1b, 0x0000}, /* Port0 PHY Special Control/Status Indication Register */ + {0x02, 0x1b, 0x0000}, /* Port1 PHY Special Control/Status Indication Register */ + {0x03, 0x1b, 0x0000}, /* Port2 PHY Special Control/Status Indication Register */ + {0x01, 0x1e, 0x0000}, /* Port0 PHY Interrupt Source Flags Register */ + {0x02, 0x1e, 0x0000}, /* Port1 PHY Interrupt Source Flags Register */ + {0x03, 0x1e, 0x0000}, /* Port2 PHY Interrupt Source Flags Register */ +}; + +int init_smsc9303i_mii(void) +{ + unsigned int data; + unsigned int i; + + printf(" reset SMSC LAN9303i\n"); + + gpio_request(GPIO_PG10, "smsc9303"); + gpio_direction_output(GPIO_PG10, 0); + udelay(10000); + gpio_direction_output(GPIO_PG10, 1); + udelay(10000); + + gpio_free(GPIO_PG10); + +#if defined(CONFIG_MII_INIT) + mii_init(); +#endif + + printf(" write SMSC LAN9303i configuration\n"); + + if (!smc9303i_read_reg(0x50, &data)) + return 0; + + if ((data >> 16) != 0x9303) { + /* chip id not found */ + printf(" error identifying SMSC LAN9303i\n"); + return 0; + } + + for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table1); i++) { + const smsc9303i_config_entry1_t *entry = &smsc9303i_config_table1[i]; + + if (!smc9303i_write_reg(entry->reg, entry->value)) { + printf(" error writing SMSC LAN9303i configuration\n"); + return 0; + } + } + + for (i = 0; i < ARRAY_SIZE(smsc9303i_config_table2); i++) { + const smsc9303i_config_entry2_t *entry = &smsc9303i_config_table2[i]; + + if (!smc9303i_write_mii(entry->addr, entry->reg, entry->value)) { + printf(" error writing SMSC LAN9303i configuration\n"); + return 0; + } + } + + return 1; +} diff --git a/board/bct-brettl2/smsc9303.h b/board/bct-brettl2/smsc9303.h new file mode 100644 index 0000000000..a4ba40ef73 --- /dev/null +++ b/board/bct-brettl2/smsc9303.h @@ -0,0 +1,9 @@ +/* + * smsc9303.h - routines to initialize SMSC 9303 switch + * + * Copyright (c) 2010 BCT Electronic GmbH + * + * Licensed under the GPL-2 or later. + */ + +int init_smsc9303i_mii(void); diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk index 3f9d41f371..30b92a3c43 100644 --- a/board/bf518f-ezbrd/config.mk +++ b/board/bf518f-ezbrd/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf518-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk index 3f9d41f371..aaf4541feb 100644 --- a/board/bf526-ezbrd/config.mk +++ b/board/bf526-ezbrd/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf526-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c index b06d5ab2e8..ea405b639d 100644 --- a/board/bf527-ad7160-eval/bf527-ad7160-eval.c +++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c @@ -20,6 +20,6 @@ int checkboard(void) int misc_init_r(void) { /* CLKIN Buffer Output Enable */ - *pVR_CTL |= CLKBUFOE; + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); return 0; } diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk index 3f9d41f371..9784810af7 100644 --- a/board/bf527-ad7160-eval/config.mk +++ b/board/bf527-ad7160-eval/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf527-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk index 3f9d41f371..78eebff324 100644 --- a/board/bf527-ezkit/config.mk +++ b/board/bf527-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf527-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 51bdf02041..87e7658b4d 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -162,12 +162,12 @@ static int lq035q1_control(unsigned char reg, unsigned short value) /* enable and disable PPI functions */ void EnablePPI(void) { - *pPPI_CONTROL |= PORT_EN; + bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); } void DisablePPI(void) { - *pPPI_CONTROL &= ~PORT_EN; + bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); } void Init_Ports(void) @@ -182,119 +182,123 @@ void Init_Ports(void) void Init_PPI(void) { - *pPPI_DELAY = H_START; - *pPPI_COUNT = (H_ACTPIX-1); - *pPPI_FRAME = V_LINES; + bfin_write_PPI_DELAY(H_START); + bfin_write_PPI_COUNT(H_ACTPIX - 1); + bfin_write_PPI_FRAME(V_LINES); /* PPI control, to be replaced with definitions */ - *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */ + bfin_write_PPI_CONTROL( + PPI_TX_MODE | /* output mode , PORT_DIR */ PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ PPI_PACK_EN | /* packing enabled PACK_EN */ - PPI_POLS_1; /* faling edge syncs POLS */ + PPI_POLS_1 /* faling edge syncs POLS */ + ); } void Init_DMA(void *dst) { - *pDMA0_START_ADDR = dst; + bfin_write_DMA0_START_ADDR(dst); /* X count */ - *pDMA0_X_COUNT = H_ACTPIX / 2; - *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA0_X_COUNT(H_ACTPIX / 2); + bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8); /* Y count */ - *pDMA0_Y_COUNT = V_LINES; - *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA0_Y_COUNT(V_LINES); + bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8); /* DMA Config */ - *pDMA0_CONFIG = + bfin_write_DMA0_CONFIG( WDSIZE_16 | /* 16 bit DMA */ DMA2D | /* 2D DMA */ - FLOW_AUTO; /* autobuffer mode */ + FLOW_AUTO /* autobuffer mode */ + ); } - void EnableDMA(void) { - *pDMA0_CONFIG |= DMAEN; + bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN); } void DisableDMA(void) { - *pDMA0_CONFIG &= ~DMAEN; + bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN); } - /* Init TIMER0 as Frame Sync 1 generator */ void InitTIMER0(void) { - *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */ + bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */ SSYNC(); - *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */ + bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0); /* clear status */ SSYNC(); - *pTIMER0_PERIOD = H_PERIOD; + bfin_write_TIMER0_PERIOD(H_PERIOD); SSYNC(); - *pTIMER0_WIDTH = H_PULSE; + bfin_write_TIMER0_WIDTH(H_PULSE); SSYNC(); - *pTIMER0_CONFIG = PWM_OUT | + bfin_write_TIMER0_CONFIG( + PWM_OUT | PERIOD_CNT | TIN_SEL | CLK_SEL | - EMU_RUN; + EMU_RUN + ); SSYNC(); } void EnableTIMER0(void) { - *pTIMER_ENABLE |= TIMEN0; + bfin_write_TIMER_ENABLE(TIMEN0); SSYNC(); } void DisableTIMER0(void) { - *pTIMER_DISABLE |= TIMDIS0; + bfin_write_TIMER_DISABLE(TIMDIS0); SSYNC(); } void InitTIMER1(void) { - *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */ + bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */ SSYNC(); - *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */ + bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1); /* clear status */ SSYNC(); - - *pTIMER1_PERIOD = V_PERIOD; + bfin_write_TIMER1_PERIOD(V_PERIOD); SSYNC(); - *pTIMER1_WIDTH = V_PULSE; + bfin_write_TIMER1_WIDTH(V_PULSE); SSYNC(); - *pTIMER1_CONFIG = PWM_OUT | + bfin_write_TIMER1_CONFIG( + PWM_OUT | PERIOD_CNT | TIN_SEL | CLK_SEL | - EMU_RUN; + EMU_RUN + ); SSYNC(); } void EnableTIMER1(void) { - *pTIMER_ENABLE |= TIMEN1; + bfin_write_TIMER_ENABLE(TIMEN1); SSYNC(); } void DisableTIMER1(void) { - *pTIMER_DISABLE |= TIMDIS1; + bfin_write_TIMER_DISABLE(TIMDIS1); SSYNC(); } void EnableTIMER12(void) { - *pTIMER_ENABLE |= TIMEN1 | TIMEN0; + bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0); SSYNC(); } diff --git a/board/bf527-sdp/Makefile b/board/bf527-sdp/Makefile new file mode 100644 index 0000000000..f2bd2c247d --- /dev/null +++ b/board/bf527-sdp/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bf527-sdp/bf527-sdp.c b/board/bf527-sdp/bf527-sdp.c new file mode 100644 index 0000000000..504869d72a --- /dev/null +++ b/board/bf527-sdp/bf527-sdp.c @@ -0,0 +1,32 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <asm/blackfin.h> +#include <asm/gpio.h> +#include <asm/mach-common/bits/pll.h> + +int checkboard(void) +{ + printf("Board: ADI BF527 SDP board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + + /* Enable access to parallel flash */ + gpio_request(GPIO_PG0, "parallel-flash"); + gpio_direction_output(GPIO_PG0, 0); + + return 0; +} + +int misc_init_r(void) +{ + /* CLKIN Buffer Output Enable */ + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); + + return 0; +} diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk new file mode 100644 index 0000000000..744e7a5d0d --- /dev/null +++ b/board/bf527-sdp/config.mk @@ -0,0 +1,36 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf527-0.2 + +CFLAGS_lib_generic += -O2 +CFLAGS_lzma += -O2 + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index bc046f129f..60ec6b6c14 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf533-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index bc046f129f..60ec6b6c14 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf533-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf537-minotaur/config.mk b/board/bf537-minotaur/config.mk index d8308433b0..59e9a9c447 100644 --- a/board/bf537-minotaur/config.mk +++ b/board/bf537-minotaur/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-pnav/config.mk b/board/bf537-pnav/config.mk index eaa09ff795..ce8ef3b499 100644 --- a/board/bf537-pnav/config.mk +++ b/board/bf537-pnav/config.mk @@ -26,5 +26,7 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-srv1/config.mk b/board/bf537-srv1/config.mk index d8308433b0..59e9a9c447 100644 --- a/board/bf537-srv1/config.mk +++ b/board/bf537-srv1/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index 5766829115..3bac0adf3b 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 4daea627ef..49022dc930 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -97,19 +97,19 @@ void post_init_uart(int sclk) for (divisor = 0; sclk > 0; divisor++) sclk -= 57600 * 16; - *pPORTF_FER = 0x000F; - *pPORTH_FER = 0xFFFF; + bfin_write_PORTF_FER(0x000F); + bfin_write_PORTH_FER(0xFFFF); - *pUART_GCTL = 0x00; - *pUART_LCR = 0x83; + bfin_write_UART_GCTL(0x00); + bfin_write_UART_LCR(0x83); SSYNC(); - *pUART_DLL = (divisor & 0xFF); + bfin_write_UART_DLL(divisor & 0xFF); SSYNC(); - *pUART_DLH = ((divisor >> 8) & 0xFF); + bfin_write_UART_DLH((divisor >> 8) & 0xFF); SSYNC(); - *pUART_LCR = 0x03; + bfin_write_UART_LCR(0x03); SSYNC(); - *pUART_GCTL = 0x01; + bfin_write_UART_GCTL(0x01); SSYNC(); } @@ -121,8 +121,8 @@ void post_out_buff(char *buff) ; i = 0; while ((buff[i] != '\0') && (i != 100)) { - while (!(*pUART_LSR & 0x20)) ; - *pUART_THR = buff[i]; + while (!(bfin_read_pUART_LSR() & 0x20)) ; + bfin_write_UART_THR(buff[i]); SSYNC(); i++; } @@ -138,15 +138,15 @@ int post_key_pressed(void) int i, n; unsigned short value; - *pPORTF_FER &= ~PF5; - *pPORTFIO_DIR &= ~PF5; - *pPORTFIO_INEN |= PF5; + bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF5); + bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~PF5); + bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | PF5); SSYNC(); post_out_buff("########Press SW10 to enter Memory POST########: 3\0"); for (i = 0; i < KEY_LOOP; i++) { - value = *pPORTFIO & PF5; - if (*pUART0_RBR == 0x0D) { + value = bfin_read_PORTFIO() & PF5; + if (bfin_read_UART0_RBR() == 0x0D) { value = 0; goto key_pressed; } @@ -158,8 +158,8 @@ int post_key_pressed(void) post_out_buff("\b2\0"); for (i = 0; i < KEY_LOOP; i++) { - value = *pPORTFIO & PF5; - if (*pUART0_RBR == 0x0D) { + value = bfin_read_PORTFIO() & PF5; + if (bfin_read_UART0_RBR() == 0x0D) { value = 0; goto key_pressed; } @@ -171,8 +171,8 @@ int post_key_pressed(void) post_out_buff("\b1\0"); for (i = 0; i < KEY_LOOP; i++) { - value = *pPORTFIO & PF5; - if (*pUART0_RBR == 0x0D) { + value = bfin_read_PORTFIO() & PF5; + if (bfin_read_UART0_RBR() == 0x0D) { value = 0; goto key_pressed; } @@ -193,13 +193,13 @@ int post_key_pressed(void) void post_init_pll(int mult, int div) { - *pSIC_IWR = 0x01; - *pPLL_CTL = (mult << 9); - *pPLL_DIV = div; + bfin_write_SIC_IWR(0x01); + bfin_write_PLL_CTL((mult << 9)); + bfin_write_PLL_DIV(div); asm("CLI R2;"); asm("IDLE;"); asm("STI R2;"); - while (!(*pPLL_STAT & 0x20)) ; + while (!(bfin_read_PLL_STAT() & 0x20)) ; } int post_init_sdram(int sclk) @@ -302,15 +302,15 @@ int post_init_sdram(int sclk) SSYNC(); - *pEBIU_SDGCTL |= 0x1000000; + bfin_write_EBIU_SDGCTL(bfin_write_EBIU_SDGCTL() | 0x1000000); /* Set the SDRAM Refresh Rate control register based on SSCLK value */ - *pEBIU_SDRRC = mem_SDRRC; + bfin_write_EBIU_SDRRC(mem_SDRRC); /* SDRAM Memory Bank Control Register */ - *pEBIU_SDBCTL = mem_SDBCTL; + bfin_write_EBIU_SDBCTL(mem_SDBCTL); /* SDRAM Memory Global Control Register */ - *pEBIU_SDGCTL = mem_SDGCTL; + bfin_write_EBIU_SDGCTL(mem_SDGCTL); SSYNC(); return mem_SDRRC; } diff --git a/board/bf537-stamp/post.c b/board/bf537-stamp/post.c index c546ab6cb6..60eed5f68a 100644 --- a/board/bf537-stamp/post.c +++ b/board/bf537-stamp/post.c @@ -12,6 +12,7 @@ #include <config.h> #include <command.h> #include <asm/blackfin.h> +#include <asm/gpio.h> /* Using sw10-PF5 as the hotkey */ int post_hotkeys_pressed(void) @@ -20,14 +21,13 @@ int post_hotkeys_pressed(void) int i; unsigned short value; - *pPORTF_FER &= ~PF5; - *pPORTFIO_DIR &= ~PF5; - *pPORTFIO_INEN |= PF5; + gpio_request(GPIO_PF5, "post"); + gpio_direction_input(GPIO_PF5); printf("########Press SW10 to enter Memory POST########: %2d ", delay); while (delay--) { for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF5; + value = gpio_get_value(GPIO_PF5); if (value != 0) { break; } @@ -43,6 +43,8 @@ int post_hotkeys_pressed(void) printf("Hotkey has been pressed, Enter POST . . . . . .\n"); return 1; } + + gpio_free(GPIO_PF5); } int uart_post_test(int flags) @@ -106,34 +108,24 @@ int flash_post_test(int flags) ****************************************************/ int led_post_test(int flags) { - *pPORTF_FER &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11); - *pPORTFIO_DIR |= PF6 | PF7 | PF8 | PF9 | PF10 | PF11; - *pPORTFIO_INEN &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11); - *pPORTFIO &= ~(PF6 | PF7 | PF8 | PF9 | PF10 | PF11); - udelay(1000000); - printf("LED1 on"); - *pPORTFIO |= PF6; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED2 on"); - *pPORTFIO |= PF7; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED3 on"); - *pPORTFIO |= PF8; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED4 on"); - *pPORTFIO |= PF9; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("LED5 on"); - *pPORTFIO |= PF10; - udelay(1000000); - printf("\b\b\b\b\b\b\b"); - printf("lED6 on"); - *pPORTFIO |= PF11; - printf("\b\b\b\b\b\b\b "); + unsigned int leds[] = { + GPIO_PF6, GPIO_PF7, GPIO_PF8, + GPIO_PF9, GPIO_PF10, GPIO_PF11, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(leds); ++i) { + gpio_request(leds[i], "post"); + gpio_direction_output(leds[i], 0); + + printf("LED%i on", i + 1); + gpio_set_value(leds[i], 1); + udelay(1000000); + printf("\b\b\b\b\b\b\b"); + + gpio_free(leds[i]); + } + return 0; } @@ -143,88 +135,40 @@ int led_post_test(int flags) ************************************************/ int button_post_test(int flags) { + unsigned int buttons[] = { + GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, + }; + unsigned int sws[] = { 13, 12, 11, 10, }; int i, delay = 5; unsigned short value = 0; int result = 0; - *pPORTF_FER &= ~(PF5 | PF4 | PF3 | PF2); - *pPORTFIO_DIR &= ~(PF5 | PF4 | PF3 | PF2); - *pPORTFIO_INEN |= (PF5 | PF4 | PF3 | PF2); + for (i = 0; i < ARRAY_SIZE(buttons); ++i) { + gpio_request(buttons[i], "post"); + gpio_direction_input(buttons[i]); - printf("\n--------Press SW10: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF5; - if (value != 0) { - break; + delay = 5; + printf("\n--------Press SW%i: %2d ", sws[i], delay); + while (delay--) { + for (i = 0; i < 100; i++) { + value = gpio_get_value(buttons[i]); + if (value != 0) + break; + udelay(10000); } - udelay(10000); + printf("\b\b\b%2d ", delay); } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); - } - - delay = 5; - printf("\n--------Press SW11: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF4; - if (value != 0) { - break; - } - udelay(10000); + if (value != 0) + puts("\b\bOK"); + else { + result = -1; + puts("\b\bfailed"); } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); - } - delay = 5; - printf("\n--------Press SW12: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF3; - if (value != 0) { - break; - } - udelay(10000); - } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); + gpio_free(buttons[i]); } - delay = 5; - printf("\n--------Press SW13: %2d ", delay); - while (delay--) { - for (i = 0; i < 100; i++) { - value = *pPORTFIO & PF2; - if (value != 0) { - break; - } - udelay(10000); - } - printf("\b\b\b%2d ", delay); - } - if (value != 0) - printf("\b\bOK"); - else { - result = -1; - printf("\b\bfailed"); - } - printf("\n"); + puts("\n"); + return result; } diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index bc046f129f..170a2d56db 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf538-0.4 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index ce96c0d479..ec3c28e0b7 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf548-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index cde877aa0c..9bcf935568 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -153,24 +153,25 @@ void Init_DMA(void *dst) { #if defined(CONFIG_DEB_DMA_URGENT) - *pEBIU_DDRQUE |= DEB2_URGENT; + bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT); #endif - *pDMA12_START_ADDR = dst; + bfin_write_DMA12_START_ADDR(dst); /* X count */ - *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; - *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); + bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8); /* Y count */ - *pDMA12_Y_COUNT = LCD_Y_RES; - *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_Y_COUNT(LCD_Y_RES); + bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8); /* DMA Config */ - *pDMA12_CONFIG = + bfin_write_DMA12_CONFIG( WDSIZE_32 | /* 32 bit DMA */ DMA2D | /* 2D DMA */ - FLOW_AUTO; /* autobuffer mode */ + FLOW_AUTO /* autobuffer mode */ + ); } void Init_Ports(void) @@ -194,12 +195,12 @@ void Init_Ports(void) void EnableDMA(void) { - *pDMA12_CONFIG |= DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN); } void DisableDMA(void) { - *pDMA12_CONFIG &= ~DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN); } /* enable and disable PPI functions */ diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk index a90b193388..221de6524f 100644 --- a/board/bf561-acvilon/config.mk +++ b/board/bf561-acvilon/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.5 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index a90b193388..ff19190a26 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/blackstamp/config.mk b/board/blackstamp/config.mk index eaa09ff795..5035cb9c58 100644 --- a/board/blackstamp/config.mk +++ b/board/blackstamp/config.mk @@ -26,5 +26,7 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf532-0.5 + # Set some default LDR flags based on boot mode. LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/blackvme/Makefile b/board/blackvme/Makefile new file mode 100644 index 0000000000..f2bd2c247d --- /dev/null +++ b/board/blackvme/Makefile @@ -0,0 +1,54 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/blackvme/blackvme.c b/board/blackvme/blackvme.c new file mode 100644 index 0000000000..eccdaf3a48 --- /dev/null +++ b/board/blackvme/blackvme.c @@ -0,0 +1,31 @@ +/* U-boot - blackvme.c board specific routines + * (c) Wojtek Skulski 2010 info@skutek.com + * Board info: http://www.skutek.com + * Copyright (c) 2005-2009 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <netdev.h> + +int checkboard(void) +{ + printf("Board: BlackVME\n"); + printf("Support: http://www.skutek.com/\n"); + return 0; +} + +#ifdef CONFIG_DRIVER_AX88180 +/* + * The ax88180 driver had to be patched to work around a bug + * in Marvell 88E1111 B2 silicon. E-mail me for explanations. + */ +int board_eth_init(bd_t *bis) +{ + return ax88180_initialize(bis); +} +#endif /* CONFIG_DRIVER_AX88180 */ diff --git a/board/siemens/pcu_e/config.mk b/board/blackvme/config.mk index 10f37734ae..8d0fe3934d 100644 --- a/board/siemens/pcu_e/config.mk +++ b/board/blackvme/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -21,8 +23,10 @@ # MA 02111-1307 USA # -# -# Siemens PCU E Boards -# +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +CONFIG_BFIN_CPU = bf561-0.5 -TEXT_BASE = 0xFFF00000 +# Set some default LDR flags based on boot mode. +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c index b6815b1ccd..a5f70a4f83 100644 --- a/board/cm-bf527/cm-bf527.c +++ b/board/cm-bf527/cm-bf527.c @@ -13,7 +13,7 @@ #include <asm/blackfin.h> #include <asm/net.h> #include <asm/mach-common/bits/otp.h> -#include "gpio_cfi_flash.h" +#include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk index 3f9d41f371..78eebff324 100644 --- a/board/cm-bf527/config.mk +++ b/board/cm-bf527/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf527-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf527/gpio_cfi_flash.c b/board/cm-bf527/gpio_cfi_flash.c index f8ccc078ec..6e62fff230 100644 --- a/board/cm-bf527/gpio_cfi_flash.c +++ b/board/cm-bf527/gpio_cfi_flash.c @@ -1,60 +1,3 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include "gpio_cfi_flash.h" - -#define GPIO_PIN_1 GPIO_PH9 -#define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 GPIO_PG11 -#define GPIO_MASK_2 (1 << 22) -#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) - -void *gpio_cfi_flash_swizzle(void *vaddr) -{ - unsigned long addr = (unsigned long)vaddr; - - gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); - -#ifdef GPIO_MASK_2 - gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); -#endif - - SSYNC(); - - return (void *)(addr & ~GPIO_MASK); -} - -#define __raw_writeq(value, addr) *(volatile u64 *)addr = value -#define __raw_readq(addr) *(volatile u64 *)addr - -#define MAKE_FLASH(size, sfx) \ -void flash_write##size(u##size value, void *addr) \ -{ \ - __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ -} \ -u##size flash_read##size(void *addr) \ -{ \ - return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ -} -MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ -MAKE_FLASH(16, w) /* flash_write16() flash_read16() */ -MAKE_FLASH(32, l) /* flash_write32() flash_read32() */ -MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ - -void gpio_cfi_flash_init(void) -{ - gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 - gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); -#endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); -} +#define GPIO_PIN_1 GPIO_PH9 +#define GPIO_PIN_2 GPIO_PG11 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/cm-bf527/gpio_cfi_flash.h b/board/cm-bf527/gpio_cfi_flash.h deleted file mode 100644 index 5211e972ad..0000000000 --- a/board/cm-bf527/gpio_cfi_flash.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -void *gpio_cfi_flash_swizzle(void *vaddr); -void gpio_cfi_flash_init(void); diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk index bc046f129f..60ec6b6c14 100644 --- a/board/cm-bf533/config.mk +++ b/board/cm-bf533/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf533-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk index bc046f129f..1281da4bef 100644 --- a/board/cm-bf537e/config.mk +++ b/board/cm-bf537e/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf537e/gpio_cfi_flash.c b/board/cm-bf537e/gpio_cfi_flash.c index 79ee844135..1075cc4112 100644 --- a/board/cm-bf537e/gpio_cfi_flash.c +++ b/board/cm-bf537e/gpio_cfi_flash.c @@ -1,7 +1,7 @@ /* * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support * - * Copyright (c) 2009 Analog Devices Inc. + * Copyright (c) 2009-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -12,9 +12,22 @@ #include <asm/io.h> #include "gpio_cfi_flash.h" +/* Allow this driver to be shared among boards */ +#ifndef GPIO_PIN_1 #define GPIO_PIN_1 GPIO_PF4 +#endif #define GPIO_MASK_1 (1 << 21) -#define GPIO_MASK (GPIO_MASK_1) +#ifndef GPIO_PIN_2 +#define GPIO_MASK_2 (0) +#else +#define GPIO_MASK_2 (1 << 22) +#endif +#ifndef GPIO_PIN_3 +#define GPIO_MASK_3 (0) +#else +#define GPIO_MASK_3 (1 << 23) +#endif +#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2 | GPIO_MASK_3) void *gpio_cfi_flash_swizzle(void *vaddr) { @@ -22,11 +35,16 @@ void *gpio_cfi_flash_swizzle(void *vaddr) gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); -#ifdef GPIO_MASK_2 +#ifdef GPIO_PIN_2 gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); #endif +#ifdef GPIO_PIN_3 + gpio_set_value(GPIO_PIN_3, addr & GPIO_MASK_3); +#endif + SSYNC(); + udelay(1); return (void *)(addr & ~GPIO_MASK); } @@ -51,8 +69,13 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ void gpio_cfi_flash_init(void) { gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 + gpio_direction_output(GPIO_PIN_1, 0); +#ifdef GPIO_PIN_2 gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); + gpio_direction_output(GPIO_PIN_2, 0); +#endif +#ifdef GPIO_PIN_3 + gpio_request(GPIO_PIN_3, "gpio_cfi_flash"); + gpio_direction_output(GPIO_PIN_3, 0); #endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); } diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index 92fa5a0993..4b7e8642c9 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -13,7 +13,7 @@ #include <netdev.h> #include <asm/blackfin.h> #include <asm/net.h> -#include "gpio_cfi_flash.h" +#include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk index bc046f129f..1281da4bef 100644 --- a/board/cm-bf537u/config.mk +++ b/board/cm-bf537u/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c index 416c689500..ef5ea8b793 100644 --- a/board/cm-bf537u/gpio_cfi_flash.c +++ b/board/cm-bf537u/gpio_cfi_flash.c @@ -1,58 +1,2 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include "gpio_cfi_flash.h" - -#define GPIO_PIN_1 GPIO_PH0 -#define GPIO_MASK_1 (1 << 21) -#define GPIO_MASK (GPIO_MASK_1) - -void *gpio_cfi_flash_swizzle(void *vaddr) -{ - unsigned long addr = (unsigned long)vaddr; - - gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); - -#ifdef GPIO_MASK_2 - gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); -#endif - - SSYNC(); - - return (void *)(addr & ~GPIO_MASK); -} - -#define __raw_writeq(value, addr) *(volatile u64 *)addr = value -#define __raw_readq(addr) *(volatile u64 *)addr - -#define MAKE_FLASH(size, sfx) \ -void flash_write##size(u##size value, void *addr) \ -{ \ - __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ -} \ -u##size flash_read##size(void *addr) \ -{ \ - return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ -} -MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ -MAKE_FLASH(16, w) /* flash_write16() flash_read16() */ -MAKE_FLASH(32, l) /* flash_write32() flash_read32() */ -MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ - -void gpio_cfi_flash_init(void) -{ - gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 - gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); -#endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); -} +#define GPIO_PIN_1 GPIO_PH0 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/cm-bf537u/gpio_cfi_flash.h b/board/cm-bf537u/gpio_cfi_flash.h deleted file mode 100644 index 5211e972ad..0000000000 --- a/board/cm-bf537u/gpio_cfi_flash.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -void *gpio_cfi_flash_swizzle(void *vaddr); -void gpio_cfi_flash_init(void); diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk index f071a39d75..bce60e5baa 100644 --- a/board/cm-bf548/config.mk +++ b/board/cm-bf548/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf548-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index c501697404..4703098149 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -153,25 +153,26 @@ void Init_PPI(void) void Init_DMA(void *dst) { - #if defined(CONFIG_DEB_DMA_URGENT) - *pEBIU_DDRQUE |= DEB2_URGENT; + bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT); #endif - *pDMA12_START_ADDR = dst; + bfin_write_DMA12_START_ADDR(dst); /* X count */ - *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; - *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE); + bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8); /* Y count */ - *pDMA12_Y_COUNT = LCD_Y_RES; - *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; + bfin_write_DMA12_Y_COUNT(LCD_Y_RES); + bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8); /* DMA Config */ - *pDMA12_CONFIG = WDSIZE_32 | /* 32 bit DMA */ + bfin_write_DMA12_CONFIG( + WDSIZE_32 | /* 32 bit DMA */ DMA2D | /* 2D DMA */ - FLOW_AUTO; /* autobuffer mode */ + FLOW_AUTO /* autobuffer mode */ + ); } void Init_Ports(void) @@ -195,12 +196,12 @@ void Init_Ports(void) void EnableDMA(void) { - *pDMA12_CONFIG |= DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN); } void DisableDMA(void) { - *pDMA12_CONFIG &= ~DMAEN; + bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN); } /* enable and disable PPI functions */ diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk index a90b193388..ff19190a26 100644 --- a/board/cm-bf561/config.mk +++ b/board/cm-bf561/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.3 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index f17df60c20..31b079b1c3 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -119,11 +119,6 @@ int misc_init_r(void) tmp & 0x000000FF ); -#ifdef CONFIG_FSL_DIU_FB -# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) - mpc5121_diu_init(); -# endif -#endif return 0; } diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S index 1b07d622f7..137fe41b4b 100644 --- a/board/eNET/eNET_start.S +++ b/board/eNET/eNET_start.S @@ -27,19 +27,7 @@ .globl early_board_init early_board_init: /* No 32-bit board specific initialisation */ - jmp *%ebp /* return to caller */ - -.globl show_boot_progress_asm -show_boot_progress_asm: - - movb %al, %dl /* Create Working Copy */ - andb $0x80, %dl /* Mask in only Error bit */ - shrb $0x02, %dl /* Shift Error bit to Error LED */ - andb $0x0f, %al /* Mask out 'Error' bit */ - orb %dl, %al /* Mask in ERR LED */ - movw $LED_LATCH_ADDRESS, %dx - outb %al, %dx - jmp *%ebp /* return to caller */ + jmp early_board_init_ret .globl cpu_halt_asm cpu_halt_asm: diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index af2c132156..06cfd558d1 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -65,8 +65,7 @@ board_init16: movl $0x000000cb, %eax outl %eax, %dx - /* the return address is stored in bp */ - jmp *%bp + jmp board_init16_ret .section .bios, "ax" .code16 diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds index 7b0ffaa6cc..b414079bc1 100644 --- a/board/eNET/u-boot.lds +++ b/board/eNET/u-boot.lds @@ -27,66 +27,62 @@ ENTRY(_start) SECTIONS { - . = 0x06000000; /* Location of bootcode in flash */ - _i386boot_text_start = .; - .text : { *(.text); } + . = TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } . = ALIGN(4); + __u_boot_cmd_end = .; - .data : { *(.data) } . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - .interp : { *(.interp) } . = ALIGN(4); + .data : { *(.data*) } - .dynsym : { *(.dynsym) } . = ALIGN(4); + .dynsym : { *(.dynsym*) } - .dynstr : { *(.dynstr) } . = ALIGN(4); + .hash : { *(.hash*) } - .hash : { *(.hash) } . = ALIGN(4); + .got : { *(.got*) } - .got : { *(.got) } . = ALIGN(4); + __data_end = .; - .got.plt : { *(.got.plt) } . = ALIGN(4); - - .dynamic (NOLOAD) : { *(.dynamic) } + __bss_start = ABSOLUTE(.); + .bss (NOLOAD) : { *(.bss) } . = ALIGN(4); + __bss_end = ABSOLUTE(.); - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } . = ALIGN(4); - __u_boot_cmd_end = .; - _i386boot_cmd_start = LOADADDR(.u_boot_cmd); - - _i386boot_rel_dyn_start = .; + __rel_dyn_start = .; .rel.dyn : { *(.rel.dyn) } - _i386boot_rel_dyn_end = .; + __rel_dyn_end = .; - . = ALIGN(4); - _i386boot_bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } - _i386boot_bss_size = SIZEOF(.bss); + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } /* 16bit realmode trampoline code */ - .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { *(.realmode) } + .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) } - _i386boot_realmode = LOADADDR(.realmode); - _i386boot_realmode_size = SIZEOF(.realmode); + __realmode_start = LOADADDR(.realmode); + __realmode_size = SIZEOF(.realmode); /* 16bit BIOS emulation code (just enough to boot Linux) */ - .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) } + .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { KEEP(*(.bios)) } - _i386boot_bios = LOADADDR(.bios); - _i386boot_bios_size = SIZEOF(.bios); + __bios_start = LOADADDR(.bios); + __bios_size = SIZEOF(.bios); /* The load addresses below assumes that the flash * will be mapped so that 0x387f0000 == 0xffff0000 @@ -98,12 +94,11 @@ SECTIONS * The fff0 offset of resetvec is important, however. */ . = 0xfffffe00; - .start32 : AT (0x0603fe00) { *(.start32); } + .start32 : AT (TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); } . = 0xf800; - .start16 : AT (0x0603f800) { *(.start16); } + .start16 : AT (TEXT_BASE + 0x3f800) { KEEP(*(.start16)); } . = 0xfff0; - .resetvec : AT (0x0603fff0) { *(.resetvec); } - _i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) ); + .resetvec : AT (TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); } } diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 394b71f32f..35ed938bef 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -28,7 +28,7 @@ #include <malloc.h> #include <asm/io.h> -#include "fsl_diu_fb.h" +#include <fsl_diu_fb.h> struct fb_videomode { const char *name; /* optional */ @@ -472,3 +472,42 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) buf->offset = 0; return 0; } + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include <stdio_dev.h> +#include <video_fb.h> +/* + * The Graphic Device + */ +static GraphicDevice ctfb; + +void *video_hw_init(void) +{ + struct fb_info *info; + + if (platform_diu_init(&ctfb.winSizeX, &ctfb.winSizeY) < 0) + return NULL; + + /* fill in Graphic device struct */ + sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", + ctfb.winSizeX, ctfb.winSizeY, 32, 64, 60); + + ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info); + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; + + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; + + ctfb.isaBase = 0; + ctfb.pciBase = 0; + ctfb.memSize = info->screen_size; + + /* Cursor Start Address */ + ctfb.dprBase = 0; + ctfb.vprBase = 0; + ctfb.cprBase = 0; + + return &ctfb; +} +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 3929ad0aac..11dfd84fe6 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -28,13 +28,21 @@ #include <i2c.h> #include <linux/ctype.h> +#ifdef CONFIG_SYS_I2C_EEPROM_CCID #include "../common/eeprom.h" +#define MAX_NUM_PORTS 8 +#endif -#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID) -#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID" +#ifdef CONFIG_SYS_I2C_EEPROM_NXID +#define MAX_NUM_PORTS 8 +#define NXID_VERSION 0 #endif -#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */ +#ifdef CONFIG_SYS_I2C_EEPROM_NXID_1 +#define CONFIG_SYS_I2C_EEPROM_NXID +#define MAX_NUM_PORTS 23 +#define NXID_VERSION 1 +#endif /** * static eeprom: EEPROM layout for CCID or NXID formats @@ -68,8 +76,8 @@ static struct __attribute__ ((__packed__)) eeprom { u8 res_1[21]; /* 0x2b - 0x3f Reserved */ u8 mac_count; /* 0x40 Number of MAC addresses */ u8 mac_flag; /* 0x41 MAC table flags */ - u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */ - u32 crc; /* 0x72 CRC32 checksum */ + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */ + u32 crc; /* x+1 CRC32 checksum */ #endif } e; @@ -204,7 +212,7 @@ static void update_crc(void) */ static int prog_eeprom(void) { - int ret = 0; /* shut up gcc */ + int ret = 0; int i; void *p; #ifdef CONFIG_SYS_EEPROM_BUS_NUM @@ -225,6 +233,11 @@ static int prog_eeprom(void) i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif + /* + * The AT24C02 datasheet says that data can only be written in page + * mode, which means 8 bytes at a time, and it takes up to 5ms to + * complete a given write. + */ for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) { ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((sizeof(e) - i), 8)); @@ -233,12 +246,23 @@ static int prog_eeprom(void) udelay(5000); /* 5ms write cycle timing */ } + if (!ret) { + /* Verify the write by reading back the EEPROM and comparing */ + struct eeprom e2; + + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2)); + if (!ret && memcmp(&e, &e2, sizeof(e))) + ret = -1; + } + #ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); #endif if (ret) { printf("Programming failed.\n"); + has_been_read = 0; return -1; } @@ -300,7 +324,7 @@ static void set_mac_address(unsigned int index, const char *string) char *p = (char *) string; unsigned int i; - if (!string) { + if ((index >= MAX_NUM_PORTS) || !string) { printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n"); return; } @@ -333,7 +357,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (cmd == 'i') { #ifdef CONFIG_SYS_I2C_EEPROM_NXID memcpy(e.id, "NXID", sizeof(e.id)); - e.version = 0; + e.version = NXID_VERSION; #else memcpy(e.id, "CCID", sizeof(e.id)); #endif @@ -382,8 +406,8 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) e.mac_count = simple_strtoul(argv[2], NULL, 16); update_crc(); break; - case '0' ... '7': /* "mac 0" through "mac 7" */ - set_mac_address(cmd - '0', argv[2]); + case '0' ... '9': /* "mac 0" through "mac 22" */ + set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]); break; case 'h': /* help */ default: diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 2994e366c2..e1bca1984c 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -40,10 +40,14 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +#ifdef CONFIG_PCIE4 +static struct pci_controller pcie4_hose; +#endif + void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[3]; + struct fsl_pci_info pci_info[4]; u32 devdisr; int first_free_busno = 0; int num = 0; @@ -119,6 +123,28 @@ void pci_init_board(void) #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ #endif + +#ifdef CONFIG_PCIE4 + pcie_configured = is_serdes_configured(PCIE4); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { + set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_4); + set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_4); + SET_STD_PCIE_INFO(pci_info[num], 4); + pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); + printf(" PCIE4 connected to as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie4_hose, first_free_busno); + } else { + printf (" PCIE4: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ +#endif } void pci_of_setup(void *blob, bd_t *bd) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index e938788f07..e3f5b4aa21 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->write_data_delay = 2; /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed + * Enable half drive strength */ - popts->half_strength_driver_enable = 0; + popts->half_strength_driver_enable = 1; + + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x4; + + /* Rtt and Rtt_W override */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_60_OHM; + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ } diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 01b7dcb70c..795e5654e8 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -27,6 +27,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> @@ -211,6 +212,31 @@ int board_early_init_f (void) return 0; } +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_NAND_BASE; + const u8 flash_esel = 0; + + /* + * Remap Boot flash to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, /* ts, esel */ + BOOKE_PAGESZ_64M, 1); /* tsize, iprot */ + + return 0; +} + int checkboard (void) { printf ("Board: 8569 MDS\n"); diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c index 73dcc3e66c..f852fc35c3 100644 --- a/board/freescale/mpc8569mds/tlb.c +++ b/board/freescale/mpc8569mds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009-2010 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -46,15 +46,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 Initializations */ /* - * TLBe 0: 64M Non-cacheable, guarded + * TLBe 0: 64M write-through, guarded * Out of reset this entry is only 4K. - * 0xfc000000 256K NAND FLASH (CS3) - * 0xfe000000 32M NOR FLASH (CS0) + * 0xfc000000 32MB NAND FLASH (CS3) + * 0xfe000000 32MB NOR FLASH (CS0) */ +#ifdef CONFIG_NAND_SPL SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), - +#endif /* * TLBe 1: 256KB Non-cacheable, guarded * 0xf8000000 32K BCSR diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 960c8eda7d..81e53e734f 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -26,17 +26,7 @@ #include <common.h> #include <command.h> #include <asm/io.h> - -#ifdef CONFIG_FSL_DIU_FB - -#include "../common/fsl_diu_fb.h" - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) -#include <stdio_dev.h> -#include <video_fb.h> -#endif - -static int xres, yres; +#include <fsl_diu_fb.h> void diu_set_pixel_clock(unsigned int pixclock) { @@ -59,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); } -int mpc8610hpcd_diu_init(void) +int platform_diu_init(unsigned int *xres, unsigned int *yres) { char *monitor_port; int gamma_fix; @@ -73,8 +63,8 @@ int mpc8610hpcd_diu_init(void) monitor_port = getenv("monitor"); if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; if (pixis_arch == 0x01) pixel_format = 0x88882317; else @@ -83,68 +73,26 @@ int mpc8610hpcd_diu_init(void) out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ - xres = 1024; - yres = 768; + *xres = 1024; + *yres = 768; pixel_format = 0x88883316; gamma_fix = 0; out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10); } else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; pixel_format = 0x88883316; gamma_fix = 1; out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7); } else { /* DVI */ - xres = 1280; - yres = 1024; + *xres = 1280; + *yres = 1024; pixel_format = 0x88882317; gamma_fix = 0; out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } - return fsl_diu_init(xres, pixel_format, gamma_fix); -} - -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - -/* - * The Graphic Device - */ -static GraphicDevice ctfb; - -void *video_hw_init(void) -{ - struct fb_info *info; - - if (mpc8610hpcd_diu_init() < 0) - return NULL; - - /* fill in Graphic device struct */ - sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", xres, yres, 32, 64, 60); - - ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info); - ctfb.winSizeX = xres; - ctfb.winSizeY = yres; - ctfb.plnSizeX = ctfb.winSizeX; - ctfb.plnSizeY = ctfb.winSizeY; - - ctfb.gdfBytesPP = 4; - ctfb.gdfIndex = GDF_32BIT_X888RGB; - - ctfb.isaBase = 0; - ctfb.pciBase = 0; - ctfb.memSize = info->screen_size; - - /* Cursor Start Address */ - ctfb.dprBase = 0; - ctfb.vprBase = 0; - ctfb.cprBase = 0; - - return &ctfb; + return fsl_diu_init(*xres, pixel_format, gamma_fix); } - -#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ - -#endif /* CONFIG_FSL_DIU_FB */ diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index 8ede2d6055..678eb2ae06 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -16,6 +16,8 @@ COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o +COBJS-$(CONFIG_FSL_DIU_FB) += diu.o + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c new file mode 100644 index 0000000000..12b40a01ed --- /dev/null +++ b/board/freescale/p1022ds/diu.c @@ -0,0 +1,304 @@ +/* + * Copyright 2010 Freescale Semiconductor, Inc. + * Authors: Timur Tabi <timur@freescale.com> + * + * FSL DIU Framebuffer driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <stdio_dev.h> +#include <video_fb.h> +#include "../common/ngpixis.h" +#include <fsl_diu_fb.h> + +/* The CTL register is called 'csr' in the ngpixis_t structure */ +#define PX_CTL_ALTACC 0x80 + +#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0 +#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00 +#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0 +#define PX_BRDCFG0_ELBC_DIU 0x02 + +#define PX_BRDCFG1_DVIEN 0x80 +#define PX_BRDCFG1_DFPEN 0x40 +#define PX_BRDCFG1_BACKLIGHT 0x20 + +#define PMUXCR_ELBCDIU_MASK 0xc0000000 +#define PMUXCR_ELBCDIU_NOR16 0x80000000 + +/* + * DIU Area Descriptor + * + * Note that we need to byte-swap the value before it's written to the AD + * register. So even though the registers don't look like they're in the same + * bit positions as they are on the MPC8610, the same value is written to the + * AD register on the MPC8610 and on the P1022. + */ +#define AD_BYTE_F 0x10000000 +#define AD_ALPHA_C_SHIFT 25 +#define AD_BLUE_C_SHIFT 23 +#define AD_GREEN_C_SHIFT 21 +#define AD_RED_C_SHIFT 19 +#define AD_PIXEL_S_SHIFT 16 +#define AD_COMP_3_SHIFT 12 +#define AD_COMP_2_SHIFT 8 +#define AD_COMP_1_SHIFT 4 +#define AD_COMP_0_SHIFT 0 + +/* + * Variables used by the DIU/LBC switching code. It's safe to makes these + * global, because the DIU requires DDR, so we'll only run this code after + * relocation. + */ +static u8 px_brdcfg0; +static u32 pmuxcr; +static void *lbc_lcs0_ba; +static void *lbc_lcs1_ba; + +void diu_set_pixel_clock(unsigned int pixclock) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned long speed_ccb, temp; + u32 pixval; + + speed_ccb = get_bus_freq(0); + temp = 1000000000 / pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; + out_be32(&gur->clkdvdr, temp); /* turn off clock */ + out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); +} + +int platform_diu_init(unsigned int *xres, unsigned int *yres) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char *monitor_port; + u32 pixel_format; + u8 temp; + + /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ + lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000); + lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000); + + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); + + temp = in_8(&pixis->brdcfg1); + + monitor_port = getenv("monitor"); + if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ + *xres = 1024; + *yres = 768; + /* Enable the DFP port, disable the DVI and the backlight */ + temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT); + temp |= PX_BRDCFG1_DFPEN; + } else { /* DVI */ + *xres = 1280; + *yres = 1024; + /* Enable the DVI port, disable the DFP and the backlight */ + temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT); + temp |= PX_BRDCFG1_DVIEN; + } + + out_8(&pixis->brdcfg1, temp); + + /* + * Enable PIXIS indirect access mode. This is a hack that allows us to + * access PIXIS registers even when the LBC pins have been muxed to the + * DIU. + */ + setbits_8(&pixis->csr, PX_CTL_ALTACC); + + /* + * Route the LAD pins to the DIU. This will disable access to the eLBC, + * which means we won't be able to read/write any NOR flash addresses! + */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + px_brdcfg0 = in_8(lbc_lcs1_ba); + out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); + + /* Setting PMUXCR to switch to DVI from ELBC */ + clrsetbits_be32(&gur->pmuxcr, + PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16); + pmuxcr = in_be32(&gur->pmuxcr); + + return fsl_diu_init(*xres, pixel_format, 0); +} + +#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* + * set_mux_to_lbc - disable the DIU so that we can read/write to elbc + * + * On the Freescale P1022, the DIU video signal and the LBC address/data lines + * share the same pins, which means that when the DIU is active (e.g. the + * console is on the DVI display), NOR flash cannot be accessed. So we use the + * weak accessor feature of the CFI flash code to temporarily switch the pin + * mux from DIU to LBC whenever we want to read or write flash. This has a + * significant performance penalty, but it's the only way to make it work. + * + * There are two muxes: one on the chip, and one on the board. The chip mux + * controls whether the pins are used for the DIU or the LBC, and it is + * set via PMUXCR. The board mux controls whether those signals go to + * the video connector or the NOR flash chips, and it is set via the ngPIXIS. + */ +static int set_mux_to_lbc(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Switch the muxes only if they're currently set to DIU mode */ + if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) == + PMUXCR_ELBCDIU_NOR16) { + /* + * In DIU mode, the PIXIS can only be accessed indirectly + * since we can't read/write the LBC directly. + */ + + /* Set the board mux to LBC. This will disable the display. */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + px_brdcfg0 = in_8(lbc_lcs1_ba); + out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK + | PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC); + + /* Disable indirect PIXIS mode */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr)); + clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC); + + /* Set the chip mux to LBC mode, so that writes go to flash. */ + out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) | + PMUXCR_ELBCDIU_NOR16); + in_be32(&gur->pmuxcr); + + return 1; + } + + return 0; +} + +/* + * set_mux_to_diu - re-enable the DIU muxing + * + * This function restores the chip and board muxing to point to the DIU. + */ +static void set_mux_to_diu(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Enable indirect PIXIS mode */ + setbits_8(&pixis->csr, PX_CTL_ALTACC); + + /* Set the board mux to DIU. This will enable the display. */ + out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); + out_8(lbc_lcs1_ba, px_brdcfg0); + in_8(lbc_lcs1_ba); + + /* Set the chip mux to DIU mode. */ + out_be32(&gur->pmuxcr, pmuxcr); + in_be32(&gur->pmuxcr); +} + +void flash_write8(u8 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writeb(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write16(u16 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writew(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write32(u32 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + __raw_writel(value, addr); + if (sw) + set_mux_to_diu(); +} + +void flash_write64(u64 value, void *addr) +{ + int sw = set_mux_to_lbc(); + + /* There is no __raw_writeq(), so do the write manually */ + *(volatile u64 *)addr = value; + if (sw) + set_mux_to_diu(); +} + +u8 flash_read8(void *addr) +{ + u8 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readb(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u16 flash_read16(void *addr) +{ + u16 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readw(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u32 flash_read32(void *addr) +{ + u32 ret; + + int sw = set_mux_to_lbc(); + + ret = __raw_readl(addr); + if (sw) + set_mux_to_diu(); + + return ret; +} + +u64 flash_read64(void *addr) +{ + u64 ret; + + int sw = set_mux_to_lbc(); + + /* There is no __raw_readq(), so do the read manually */ + ret = *(volatile u64 *)addr; + if (sw) + set_mux_to_diu(); + + return ret; +} + +#endif diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 5cdee9ff70..ee93e8b815 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -27,6 +27,7 @@ #include <asm/mp.h> #include <netdev.h> #include <i2c.h> +#include <hwconfig.h> #include "../common/ngpixis.h" @@ -90,34 +91,58 @@ phys_size_t initdram(int board_type) #define CONFIG_TFP410_I2C_ADDR 0x38 +/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 + +/* Route the I2C1 pins to the SSI port instead. */ +#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 + +/* Choose the 12.288Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 + +/* Choose the 11.2896Mhz codec reference clock */ +#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 + int misc_init_r(void) { u8 temp; + const char *audclk; + size_t arglen; - /* Enable the TFP410 Encoder */ + /* For DVI, enable the TFP410 Encoder. */ temp = 0xBF; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n", temp); temp = 0x10; if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - - /* Verify if enabled */ - temp = 0; if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) return -1; - debug("DVI Encoder Read: 0x%02x\n",temp); + /* + * Enable the reference clock for the WM8776 codec, and route the MUX + * pins for SSI. The default is the 12.288 MHz clock + */ + + temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | + CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); + temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; + + audclk = hwconfig_arg("audclk", &arglen); + /* Check the first two chars only */ + if (audclk && (strncmp(audclk, "11", 2) == 0)) + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; + else + temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; + out_8(&pixis->brdcfg1, temp); + return 0; } @@ -310,6 +335,27 @@ int board_eth_init(bd_t *bis) } #ifdef CONFIG_OF_BOARD_SETUP +/** + * ft_codec_setup - fix up the clock-frequency property of the codec node + * + * Update the clock-frequency property based on the value of the 'audclk' + * hwconfig option. If audclk is not specified, then default to 12.288MHz. + */ +static void ft_codec_setup(void *blob, const char *compatible) +{ + const char *audclk; + size_t arglen; + u32 freq; + + audclk = hwconfig_arg("audclk", &arglen); + if (audclk && (strncmp(audclk, "11", 2) == 0)) + freq = 11289600; + else + freq = 12288000; + + do_fixup_by_compat_u32(blob, compatible, "clock-frequency", freq, 1); +} + void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -327,6 +373,9 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + + /* Update the WM8776 node's clock frequency property */ + ft_codec_setup(blob, "wlf,wm8776"); } #endif diff --git a/board/ibf-dsp561/config.mk b/board/ibf-dsp561/config.mk index 77c888b3bd..1fec4d020d 100644 --- a/board/ibf-dsp561/config.mk +++ b/board/ibf-dsp561/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf561-0.5 + # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/ip04/config.mk b/board/ip04/config.mk index 5766829115..683101b827 100644 --- a/board/ip04/config.mk +++ b/board/ip04/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf532-0.5 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c index 0e26b890b2..5231c7a5c6 100644 --- a/board/lwmon5/kbd.c +++ b/board/lwmon5/kbd.c @@ -45,6 +45,10 @@ static int compare_magic (uchar *kbd_data, uchar *str); /*--------------------- Local macros and constants --------------------*/ #define _NOT_USED_ 0xFFFFFFFF +/*------------------------- dspic io expander -----------------------*/ +#define DSPIC_PON_STATUS_REG 0x80A +#define DSPIC_PON_INV_STATUS_REG 0x80C +#define DSPIC_PON_KEY_REG 0x810 /*------------------------- Keyboard controller -----------------------*/ /* command codes */ #define KEYBD_CMD_READ_KEYS 0x01 @@ -75,6 +79,7 @@ static int compare_magic (uchar *kbd_data, uchar *str); /* maximum number of "magic" key codes that can be assigned */ static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; +static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR; static uchar *key_match (uchar *); @@ -167,6 +172,23 @@ static void kbd_init (void) } } + +/* Read a register from the dsPIC. */ +int _dspic_read(ushort reg, ushort *data) +{ + uchar buf[sizeof(*data)]; + int rval; + + if (i2c_read(dspic_addr, reg, 2, buf, 2)) + return -1; + + rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data)); + *data = (buf[0] << 8) | buf[1]; + + return rval; +} + + /*********************************************************************** F* Function: int misc_init_r (void) P*A*Z* * @@ -197,6 +219,7 @@ int misc_init_r_kbd (void) uchar kbd_init_status = gd->kbd_status >> 8; uchar kbd_status = gd->kbd_status; uchar val; + ushort data, inv_data; char *str; int i; @@ -231,9 +254,31 @@ int misc_init_r_kbd (void) i2c_write (kbd_addr, 0, 0, &val, 1); i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN); + /* read out start key from bse01 received via can */ + _dspic_read(DSPIC_PON_STATUS_REG, &data); + /* check highbyte from status register */ + if (data > 0xFF) { + _dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data); + + /* check inverse data */ + if ((data+inv_data) == 0xFFFF) { + /* don't overwrite local key */ + if (kbd_data[1] == 0) { + /* read key value */ + _dspic_read(DSPIC_PON_KEY_REG, &data); + str = (char *)&data; + /* swap bytes */ + kbd_data[1] = str[1]; + kbd_data[2] = str[0]; + printf("CAN received startkey: 0x%X\n", data); + } + } + } + for (i = 0; i < KEYBD_DATALEN; ++i) { sprintf (keybd_env + i + i, "%02X", kbd_data[i]); } + setenv ("keybd", keybd_env); str = strdup ((char *)key_match (kbd_data)); /* decode keys */ diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 9622b70d27..dd275bf777 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -24,10 +24,13 @@ #include <asm/processor.h> #include <asm/ppc4xx-gpio.h> #include <asm/io.h> +#include <post.h> +#include <flash.h> +#include <mtd/cfi_flash.h> DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST; ulong flash_get_size(ulong base, int banknum); int misc_init_r_kbd(void); @@ -97,16 +100,18 @@ int board_early_init_f(void) gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1); + /* enable the LSB transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1); + /* enable the CAN transmitter */ + gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1); reg = 0; /* reuse as counter */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & ~CONFIG_SYS_DSPIC_TEST_MASK); - while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { + while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { udelay(1000); } - gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0); if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { /* set "boot error" flag */ out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, @@ -135,9 +140,61 @@ int board_early_init_f(void) return 0; } -/*---------------------------------------------------------------------------+ - | misc_init_r. - +---------------------------------------------------------------------------*/ +/* + * Override weak default with board specific version + */ +phys_addr_t cfi_flash_bank_addr(int bank) +{ + return lwmon5_cfi_flash_bank_addr[bank]; +} + +/* + * Override the weak default mapping function with a board specific one + */ +u32 flash_get_bank_size(int cs, int idx) +{ + return flash_info[idx].size; +} + +int board_early_init_r(void) +{ + u32 val0, val1; + + /* + * lwmon5 is manufactured in 2 different board versions: + * The lwmon5a board has 64MiB NOR flash instead of the + * 128MiB of the original lwmon5. Unfortunately the CFI driver + * will report 2 banks of 64MiB even for the smaller flash + * chip, since the bank is mirrored. To fix this, we bring + * one bank into CFI query mode and read its response. This + * enables us to detect the real number of flash devices/ + * banks which will be used later on by the common CFI driver. + */ + + /* Put bank 0 into CFI command mode and read */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098); + val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP); + val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP); + + /* Reset flash again out of query mode */ + out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0); + + /* When not identical, we have 2 different flash devices/banks */ + if (val0 != val1) + return 0; + + /* + * Now we're sure that we're running on a LWMON5a board with + * only 64MiB NOR flash in one bank: + * + * Set flash base address and bank count for CFI driver probing. + */ + cfi_flash_num_flash_banks = 1; + lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0; + + return 0; +} + int misc_init_r(void) { u32 pbcr; @@ -145,7 +202,7 @@ int misc_init_r(void) u32 reg; unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; - unsigned long sdr0_pfc1; + unsigned long sdr0_pfc1, sdr0_srst; /* * FLASH stuff... @@ -158,32 +215,7 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; mfebc(PB0CR, pbcr); - switch (gd->bd->bi_flashsize) { - case 1 << 20: - size_val = 0; - break; - case 2 << 20: - size_val = 1; - break; - case 4 << 20: - size_val = 2; - break; - case 8 << 20: - size_val = 3; - break; - case 16 << 20: - size_val = 4; - break; - case 32 << 20: - size_val = 5; - break; - case 64 << 20: - size_val = 6; - break; - case 128 << 20: - size_val = 7; - break; - } + size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); mtebc(PB0CR, pbcr); @@ -193,53 +225,92 @@ int misc_init_r(void) flash_get_size(gd->bd->bi_flashstart, 0); /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[1]); + flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff, + &flash_info[cfi_flash_num_flash_banks - 1]); /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[1]); + flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[cfi_flash_num_flash_banks - 1]); /* * USB suff... */ + + /* Reset USB */ + /* Reset of USB2PHY0 must be active at least 10 us */ + mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D); + udelay(2000); + + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI | + SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 | + SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40); + udelay(2000); + + /* Errata CHIP_6 */ + + /* 1. Set internal PHY configuration */ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); mfsdr(SDR0_USB0, usb2d0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ - - /* An 8-bit/60MHz interface is the only possible alternative - when connecting the Device to the PHY */ - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* + * An 8-bit/60MHz interface is the only possible alternative + * when connecting the Device to the PHY + */ + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ mtsdr(SDR0_PFC1, sdr0_pfc1); mtsdr(SDR0_USB0, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); + /* 2. De-assert internal PHY reset */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst); + + /* 3. Wait for more than 1 ms */ + udelay(2000); + + /* 4. De-assert USB 2.0 Host main reset */ + mfsdr(SDR0_SRST0, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst); + udelay(1000); + + /* 5. De-assert reset of OPB2 cores */ + mfsdr(SDR0_SRST1, sdr0_srst); + sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40; + sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2; + mtsdr(SDR0_SRST1, sdr0_srst); + udelay(1000); + + /* 6. Set EHCI Configure FLAG */ + + /* 7. Reassert internal PHY reset: */ + mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY); + udelay(1000); + /* * Clear resets */ - udelay (1000); mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy) Device(ext phy)\n"); @@ -264,7 +335,7 @@ int checkboard(void) { char *s = getenv("serial#"); - printf("Board: lwmon5"); + puts("Board: lwmon5"); if (s != NULL) { puts(", serial# "); @@ -331,34 +402,33 @@ U_BOOT_CMD( extern GraphicDevice mb862xx; -static const gdc_regs init_regs [] = -{ - {0x0100, 0x00000f00}, - {0x0020, 0x801401df}, - {0x0024, 0x00000000}, - {0x0028, 0x00000000}, - {0x002c, 0x00000000}, - {0x0110, 0x00000000}, - {0x0114, 0x00000000}, - {0x0118, 0x01df0280}, - {0x0004, 0x031f0000}, - {0x0008, 0x027f027f}, - {0x000c, 0x015f028f}, - {0x0010, 0x020c0000}, - {0x0014, 0x01df01ea}, - {0x0018, 0x00000000}, - {0x001c, 0x01e00280}, - {0x0100, 0x80010f00}, - {0x0, 0x0} +static const gdc_regs init_regs [] = { + { 0x0100, 0x00000f00 }, + { 0x0020, 0x801401df }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x00000000 }, + { 0x002c, 0x00000000 }, + { 0x0110, 0x00000000 }, + { 0x0114, 0x00000000 }, + { 0x0118, 0x01df0280 }, + { 0x0004, 0x031f0000 }, + { 0x0008, 0x027f027f }, + { 0x000c, 0x015f028f }, + { 0x0010, 0x020c0000 }, + { 0x0014, 0x01df01ea }, + { 0x0018, 0x00000000 }, + { 0x001c, 0x01e00280 }, + { 0x0100, 0x80010f00 }, + { 0x0, 0x0 } }; -const gdc_regs *board_get_regs (void) +const gdc_regs *board_get_regs(void) { return init_regs; } /* Returns Lime base address */ -unsigned int board_video_init (void) +unsigned int board_video_init(void) { /* * Reset Lime controller @@ -375,7 +445,7 @@ unsigned int board_video_init (void) return CONFIG_SYS_LIME_BASE_0; } -#define DEFAULT_BRIGHTNESS 0x64 +#define DEFAULT_BRIGHTNESS 0x64 static void board_backlight_brightness(int brightness) { @@ -390,7 +460,7 @@ static void board_backlight_brightness(int brightness) } } -void board_backlight_switch (int flag) +void board_backlight_switch(int flag) { char * param; int rc; @@ -410,15 +480,14 @@ void board_backlight_switch (int flag) /* * Return text to be printed besides the logo. */ -void video_get_info_str (int line_number, char *info) +void video_get_info_str(int line_number, char *info) { - if (line_number == 1) { - strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); - } else { + if (line_number == 1) + strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)"); + else info [0] = '\0'; - } } -#endif +#endif /* CONFIG_CONSOLE_EXTRA_INFO */ #endif /* CONFIG_VIDEO */ void board_reset(void) diff --git a/board/hmi1001/Makefile b/board/manroland/hmi1001/Makefile index 442e2d0df2..442e2d0df2 100644 --- a/board/hmi1001/Makefile +++ b/board/manroland/hmi1001/Makefile diff --git a/board/hmi1001/config.mk b/board/manroland/hmi1001/config.mk index 8ccf33e15c..8ccf33e15c 100644 --- a/board/hmi1001/config.mk +++ b/board/manroland/hmi1001/config.mk diff --git a/board/hmi1001/hmi1001.c b/board/manroland/hmi1001/hmi1001.c index 9cbed4b8c5..9cbed4b8c5 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/manroland/hmi1001/hmi1001.c diff --git a/board/mucmc52/Makefile b/board/manroland/mucmc52/Makefile index 721c0164b2..721c0164b2 100644 --- a/board/mucmc52/Makefile +++ b/board/manroland/mucmc52/Makefile diff --git a/board/mucmc52/config.mk b/board/manroland/mucmc52/config.mk index 6850728331..6850728331 100644 --- a/board/mucmc52/config.mk +++ b/board/manroland/mucmc52/config.mk diff --git a/board/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c index 66973f09d1..66973f09d1 100644 --- a/board/mucmc52/mucmc52.c +++ b/board/manroland/mucmc52/mucmc52.c diff --git a/board/uc100/Makefile b/board/manroland/uc100/Makefile index 92ee091f68..92ee091f68 100644 --- a/board/uc100/Makefile +++ b/board/manroland/uc100/Makefile diff --git a/board/uc100/config.mk b/board/manroland/uc100/config.mk index a65a8ba2c7..a65a8ba2c7 100644 --- a/board/uc100/config.mk +++ b/board/manroland/uc100/config.mk diff --git a/board/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c index ad256783ce..ad256783ce 100644 --- a/board/uc100/pcmcia.c +++ b/board/manroland/uc100/pcmcia.c diff --git a/board/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index 0d8f605946..0d8f605946 100644 --- a/board/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds diff --git a/board/uc100/u-boot.lds.debug b/board/manroland/uc100/u-boot.lds.debug index a7caa8d90a..a7caa8d90a 100644 --- a/board/uc100/u-boot.lds.debug +++ b/board/manroland/uc100/u-boot.lds.debug diff --git a/board/uc100/uc100.c b/board/manroland/uc100/uc100.c index bdee4de366..bdee4de366 100644 --- a/board/uc100/uc100.c +++ b/board/manroland/uc100/uc100.c diff --git a/board/uc101/Makefile b/board/manroland/uc101/Makefile index 442e2d0df2..442e2d0df2 100644 --- a/board/uc101/Makefile +++ b/board/manroland/uc101/Makefile diff --git a/board/uc101/config.mk b/board/manroland/uc101/config.mk index 8ccf33e15c..8ccf33e15c 100644 --- a/board/uc101/config.mk +++ b/board/manroland/uc101/config.mk diff --git a/board/uc101/uc101.c b/board/manroland/uc101/uc101.c index c7dfb7bad1..c7dfb7bad1 100644 --- a/board/uc101/uc101.c +++ b/board/manroland/uc101/uc101.c diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 624c7088ac..d3300ed681 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -430,12 +430,12 @@ void check_env(void) int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - ulong size,src,ld_addr; + ulong ld_addr; int result; #if !defined(CONFIG_PATI) + ulong size = IMAGE_SIZE; + ulong src = MULTI_PURPOSE_SOCKET_ADDR; backup_t back; - src = MULTI_PURPOSE_SOCKET_ADDR; - size = IMAGE_SIZE; #endif if (strcmp(argv[1], "flash") == 0) @@ -480,30 +480,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* #if !defined(CONFIG_PATI) */ } - if (strcmp(argv[1], "mem") == 0) - { - result=0; - if(argc==3) - { - result = (int)simple_strtol(argv[2], NULL, 16); - } - src=(unsigned long)&result; - src-=CONFIG_SYS_MEMTEST_START; - src-=(100*1024); /* - 100k */ - src&=0xfff00000; - size=0; - do { - size++; - printf("\n\nPass %ld\n",size); - mem_test(CONFIG_SYS_MEMTEST_START,src,1); - if(ctrlc()) - break; - if(result>0) - result--; - - }while(result); - return 0; - } #if !defined(CONFIG_PATI) if (strcmp(argv[1], "clearenvvalues") == 0) { diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c deleted file mode 100644 index 9c08065992..0000000000 --- a/board/mpl/common/memtst.c +++ /dev/null @@ -1,565 +0,0 @@ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -/* NOT Used yet... - add following code to PIP405.c : -int testdram (void) -{ - unsigned char s[32]; - int i; - - i = getenv_f("testmem", s, 32); - if (i != 0) { - i = (int) simple_strtoul (s, NULL, 10); - if ((i > 0) && (i < 0xf)) { - printf ("testing "); - i = mem_test (0, ramsize, i); - if (i > 0) - printf ("ERROR "); - else - printf ("Ok "); - } - } - return (1); -} -*/ - - -#include <common.h> -#include <asm/processor.h> -#include <asm/ppc4xx-i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define FALSE 0 -#define TRUE 1 - -#define TEST_QUIET 8 -#define TEST_SHOW_PROG 4 -#define TEST_SHOW_ERR 2 -#define TEST_SHOW_ALL 1 - -#define TESTPAT1 0xAA55AA55 -#define TESTPAT2 0x55AA55AA -#define TEST_PASSED 0 -#define TEST_FAILED 1 -#define MEGABYTE (1024*1024) - - -typedef struct { - volatile unsigned long pat1; - volatile unsigned long pat2; -} RAM_MEMTEST_PATTERN2; - -typedef struct { - volatile unsigned long addr; -} RAM_MEMTEST_ADDRLINE; - -static __inline unsigned long Swap_32 (unsigned long val) -{ - return (((val << 16) & 0xFFFF0000) | ((val >> 16) & 0x0000FFFF)); -} - -void testm_puts (int quiet, char *buf) -{ - if ((quiet & TEST_SHOW_ALL) == TEST_SHOW_ALL) - puts (buf); -} - - -void Write_Error (int mode, unsigned long addr, unsigned long expected, - unsigned long actual) -{ - - char dispbuf[64]; - - sprintf (dispbuf, "\n ERROR @ 0x%08lX: (exp: 0x%08lX act: 0x%08lX) ", - addr, expected, actual); - testm_puts (((mode & TEST_SHOW_ERR) == - TEST_SHOW_ERR) ? TEST_SHOW_ALL : mode, dispbuf); -} - - -/* - * fills the memblock of <size> bytes from <startaddr> with pat1 and pat2 - */ - - -void RAM_MemTest_WritePattern2 (unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - p->pat1 = pat1; - p->pat2 = pat2; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> with pat1 and pat2 - * returns the address of the first error or NULL if all is well - */ - -void *RAM_MemTest_CheckPattern2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long pat1, - unsigned long pat2) -{ - RAM_MEMTEST_PATTERN2 *p, *pe; - unsigned long actual1, actual2; - - p = (RAM_MEMTEST_PATTERN2 *) startaddr; - pe = (RAM_MEMTEST_PATTERN2 *) (startaddr + size); - - while (p < pe) { - actual1 = p->pat1; - actual2 = p->pat2; - - if (actual1 != pat1) { - Write_Error (mode, (unsigned long) &(p->pat1), pat1, actual1); - return ((void *) &(p->pat1)); - } - /* endif */ - if (actual2 != pat2) { - Write_Error (mode, (unsigned long) &(p->pat2), pat2, actual2); - return ((void *) &(p->pat2)); - } - /* endif */ - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with the address - */ - -void RAM_MemTest_WriteAddrLine (unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - p->addr = (unsigned long) p; - p++; - } /* endwhile */ - } else { - while (p < pe) { - p->addr = Swap_32 ((unsigned long) p); - p++; - } /* endwhile */ - } /* endif */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLine (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) startaddr; - pe = (RAM_MEMTEST_ADDRLINE *) (startaddr + size); - - if (!swapped) { - while (p < pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } else { - while (p < pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p++; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * checks the memblock of <size> bytes from <startaddr+size> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckAddrLineReverse (int mode, unsigned long startaddr, - unsigned long size, int swapped) -{ - RAM_MEMTEST_ADDRLINE *p, *pe; - unsigned long actual, expected; - - p = (RAM_MEMTEST_ADDRLINE *) (startaddr + size - sizeof (p->addr)); - pe = (RAM_MEMTEST_ADDRLINE *) startaddr; - - if (!swapped) { - while (p > pe) { - actual = p->addr; - expected = (unsigned long) p; - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } else { - while (p > pe) { - actual = p->addr; - expected = Swap_32 ((unsigned long) p); - if (actual != expected) { - Write_Error (mode, (unsigned long) &(p->addr), expected, - actual); - return ((void *) &(p->addr)); - } /* endif */ - p--; - } /* endwhile */ - } /* endif */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with walking bit pattern - */ - -void RAM_MemTest_WriteWalkBit (unsigned long startaddr, unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - *p = 1UL << i; - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckWalkBit (int mode, unsigned long startaddr, - unsigned long size) -{ - volatile unsigned long *p, *pe; - unsigned long actual, expected; - unsigned long i; - - p = (unsigned long *) startaddr; - pe = (unsigned long *) (startaddr + size); - i = 0; - - while (p < pe) { - actual = *p; - expected = (1UL << i); - if (actual != expected) { - Write_Error (mode, (unsigned long) p, expected, actual); - return ((void *) p); - } /* endif */ - i = (i + 1 + (((unsigned long) p) >> 7)) % 32; - p++; - } /* endwhile */ - - return (NULL); -} - -/* - * fills the memblock of <size> bytes from <startaddr> with "random" pattern - */ - -void RAM_MemTest_WriteRandomPattern (unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - unsigned long i, p; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - *(unsigned long *) (startaddr + i * 4) = p; - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - *pat = p; -} - -/* - * checks the memblock of <size> bytes from <startaddr> - * returns the address of the error or NULL if all is well - */ - -void *RAM_MemTest_CheckRandomPattern (int mode, unsigned long startaddr, - unsigned long size, - unsigned long *pat) -{ - void *perr = NULL; - unsigned long i, p, p1; - - p = *pat; - - for (i = 0; i < (size / 4); i++) { - p1 = *(unsigned long *) (startaddr + i * 4); - if (p1 != p) { - if (perr == NULL) { - Write_Error (mode, startaddr + i * 4, p, p1); - perr = (void *) (startaddr + i * 4); - } /* endif */ - } - /* endif */ - if ((p % 2) > 0) { - p ^= i; - p >>= 1; - p |= 0x80000000; - } else { - p ^= ~i; - p >>= 1; - } /* endif */ - } /* endfor */ - - *pat = p; - return (perr); -} - - -void RAM_MemTest_WriteData1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT1, TESTPAT2); -} - -void *RAM_MemTest_CheckData1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT1, TESTPAT2)); -} - -void RAM_MemTest_WriteData2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WritePattern2 (startaddr, size, TESTPAT2, TESTPAT1); -} - -void *RAM_MemTest_CheckData2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckPattern2 - (mode, startaddr, size, TESTPAT2, TESTPAT1)); -} - -void RAM_MemTest_WriteAddr1 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, FALSE); -} - -void *RAM_MemTest_Check1Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, FALSE)); -} - -void *RAM_MemTest_Check2Addr1 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, FALSE)); -} - -void RAM_MemTest_WriteAddr2 (unsigned long startaddr, unsigned long size, - unsigned long *pat) -{ - RAM_MemTest_WriteAddrLine (startaddr, size, TRUE); -} - -void *RAM_MemTest_Check1Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLine (mode, startaddr, size, TRUE)); -} - -void *RAM_MemTest_Check2Addr2 (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat) -{ - return (RAM_MemTest_CheckAddrLineReverse - (mode, startaddr, size, TRUE)); -} - - -typedef struct { - void (*test_write) (unsigned long startaddr, unsigned long size, - unsigned long *pat); - char *test_write_desc; - void *(*test_check1) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); - void *(*test_check2) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat); -} RAM_MEMTEST_FUNC; - - -#define TEST_STAGES 5 -static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = { - {RAM_MemTest_WriteData1, "data test 1...\n", RAM_MemTest_CheckData1, - NULL}, - {RAM_MemTest_WriteData2, "data test 2...\n", RAM_MemTest_CheckData2, - NULL}, - {RAM_MemTest_WriteAddr1, "address line test...\n", - RAM_MemTest_Check1Addr1, RAM_MemTest_Check2Addr1}, - {RAM_MemTest_WriteAddr2, "address line test (swapped)...\n", - RAM_MemTest_Check1Addr2, RAM_MemTest_Check2Addr2}, - {RAM_MemTest_WriteRandomPattern, "random data test...\n", - RAM_MemTest_CheckRandomPattern, NULL} -}; - - -int mem_test (unsigned long start, unsigned long ramsize, int quiet) -{ - unsigned long errors, stage; - unsigned long startaddr, size, i; - const unsigned long blocksize = 0x80000; /* check in 512KB blocks */ - unsigned long *perr; - unsigned long rdatapat; - char dispbuf[80]; - int status = TEST_PASSED; - int prog = 0; - - errors = 0; - startaddr = start; - size = ramsize; - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - sprintf (dispbuf, "\nMemory Test: addr = 0x%lx size = 0x%lx\n", - startaddr, size); - testm_puts (quiet, dispbuf); - for (stage = 0; stage < TEST_STAGES; stage++) { - sprintf (dispbuf, test_stage[stage].test_write_desc); - testm_puts (quiet, dispbuf); - /* fill SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "writing block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - test_stage[stage].test_write (startaddr + i, blocksize, - &rdatapat); - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - /* check SDRAM */ - rdatapat = 0x12345678; - sprintf (dispbuf, "checking block: "); - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check1 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - if (test_stage[stage].test_check2 != NULL) { - /* check2 SDRAM */ - sprintf (dispbuf, "2nd checking block: "); - rdatapat = 0x12345678; - testm_puts (quiet, dispbuf); - for (i = 0; i < size; i += blocksize) { - sprintf (dispbuf, "%04lX\b\b\b\b", i / blocksize); - testm_puts (quiet, dispbuf); - if ((perr = - test_stage[stage].test_check2 (quiet, startaddr + i, - blocksize, - &rdatapat)) != NULL) { - status = TEST_FAILED; - } /* endif */ - } /* endfor */ - sprintf (dispbuf, "\n"); - testm_puts (quiet, dispbuf); - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - prog++; - printf ("."); - } - } - - } /* next stage */ - if ((quiet & TEST_SHOW_PROG) == TEST_SHOW_PROG) { - while (prog-- > 0) - printf ("\b \b"); - } - - if (status == TEST_FAILED) - errors++; - - return (errors); -} diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 18a8d8656c..21e3cdaeca 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ - ../common/usb_uhci.o ../common/memtst.o ../common/common_util.o + ../common/usb_uhci.o ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c index 8ddb54db1c..f7cc37b849 100644 --- a/board/mpl/mip405/cmd_mip405.c +++ b/board/mpl/mip405/cmd_mip405.c @@ -59,8 +59,7 @@ U_BOOT_CMD( "flash mem [SrcAddr] - updates U-Boot with image in memory\n" "mip405 flash mps - updates U-Boot with image from MPS\n" "mip405 info - displays board information\n" - "mip405 led <on> - switches LED on (on=1) or off (on=0)\n" - "mip405 mem [cnt] - Memory Test <cnt>-times, <cnt> = -1 loop forever" + "mip405 led <on> - switches LED on (on=1) or off (on=0)" ); /* ------------------------------------------------------------------------- */ diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index adeba69ee0..9f38d706ce 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS := pati.o ../common/flash.o ../common/memtst.o cmd_pati.o ../common/common_util.o +COBJS := pati.o ../common/flash.o cmd_pati.o ../common/common_util.o #### cmd_pati.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 774b59f84e..fb39ec3ec3 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -32,7 +32,7 @@ COBJS = $(BOARD).o \ ../common/flash.o cmd_pip405.o ../common/pci.o \ ../common/isa.o ../common/kbd.o \ ../common/usb_uhci.o \ - ../common/memtst.o ../common/common_util.o + ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 10bcb3b0a7..3f629fc099 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -29,7 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS := vcma9.o flash.o cmd_vcma9.o -COBJS += ../common/common_util.o ../common/memtst.o +COBJS += ../common/common_util.o SOBJS := lowlevel_init.o diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index e3abeb8ef1..e8714e3a79 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -237,9 +237,6 @@ int misc_init_r(void) #endif #ifdef CONFIG_FSL_DIU_FB -# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) - mpc5121_diu_init(); -#endif #if defined(CONFIG_SERIAL_MULTI) set_lcd_brightness(0); #endif diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index e41c84c763..4dc0237b9e 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -96,7 +96,6 @@ static void pm9263_nand_hw_init(void) static void pm9263_macb_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; /* * PB27 enables the 50MHz oscillator for Ethernet PHY diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 3b4d9a3459..f3d48f233e 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -96,7 +96,6 @@ static void pm9g45_nand_hw_init(void) static void pm9g45_macb_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; - at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; /* * PD2 enables the 50MHz oscillator for Ethernet PHY diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c deleted file mode 100644 index e91ceb079a..0000000000 --- a/board/siemens/CCM/ccm.c +++ /dev/null @@ -1,408 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -void can_driver_enable (void); -void can_driver_disable (void); - -int fpga_init(void); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -const uint sdram_table[] = -{ - /* - * Single Read. (Offset 0 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00, - 0x1FF5FC47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPMA RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */ - /* - * Burst Read. (Offset 8 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPMA RAM) - */ - 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPMA RAM) - */ - 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPMA RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - * Always return 1 (no second DRAM bank since based on TQM8xxL module) - */ - -int checkboard (void) -{ - unsigned char *s; - unsigned char buf[64]; - - s = (getenv_f("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL; - - puts ("Board: Siemens CCM"); - - if (s) { - puts (" ("); - - for (; *s; ++s) { - if (*s == ' ') - break; - putc (*s); - } - putc (')'); - } - - putc ('\n'); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * If Power-On-Reset switch off the Red and Green LED: At reset, the - * data direction registers are cleared and must therefore be restored. - */ -#define RSR_CSRS 0x08000000 - -int power_on_reset(void) -{ - /* Test Reset Status Register */ - return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; -} - -#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ -#define PB_LED_RED 0x20000 /* red LED is on PB.14 */ -#define PB_LEDS (PB_LED_GREEN | PB_LED_RED); - -static void init_leds (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - - immap->im_cpm.cp_pbpar &= ~PB_LEDS; - immap->im_cpm.cp_pbodr &= ~PB_LEDS; - immap->im_cpm.cp_pbdir |= PB_LEDS; - /* Check stop reset status */ - if (power_on_reset()) { - immap->im_cpm.cp_pbdat &= ~PB_LEDS; - } -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size8, size9; - long int size = 0; - unsigned long reg; - - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; - - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay(200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ - udelay(1); - memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ - udelay(1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* - * Check Bank 0 Memory Size for re-configuration - * - * try 8 column mode - */ - size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - udelay (1000); - - /* - * try 9 column mode - */ - size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); - - if (size8 < size9) { /* leave configuration at 9 columns */ - size = size9; -/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ - } else { /* back to 8 columns */ - size = size8; - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; - udelay(500); -/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ - } - - udelay (1000); - - /* - * Adjust refresh rate depending on SDRAM type - * For types > 128 MBit leave it at the current (fast) rate - */ - if (size < 0x02000000) { - /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - udelay(1000); - } - - /* - * Final mapping - */ - - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; - - - /* adjust refresh rate depending on SDRAM type, one bank */ - reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ - memctl->memc_mptpr = reg; - - can_driver_enable (); - init_leds (); - - udelay(10000); - - return (size); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Warning - both the PUMA load mode and the CAN driver use UPM B, - * so make sure only one of both is active. - */ -void can_driver_enable (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Initialize MBMR */ - memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ - - /* Initialize UPMB for CAN: single read */ - memctl->memc_mdr = 0xFFFFC004; - memctl->memc_mcr = 0x0100 | UPMB; - - memctl->memc_mdr = 0x0FFFD004; - memctl->memc_mcr = 0x0101 | UPMB; - - memctl->memc_mdr = 0x0FFFC000; - memctl->memc_mcr = 0x0102 | UPMB; - - memctl->memc_mdr = 0x3FFFC004; - memctl->memc_mcr = 0x0103 | UPMB; - - memctl->memc_mdr = 0xFFFFDC05; - memctl->memc_mcr = 0x0104 | UPMB; - - /* Initialize UPMB for CAN: single write */ - memctl->memc_mdr = 0xFFFCC004; - memctl->memc_mcr = 0x0118 | UPMB; - - memctl->memc_mdr = 0xCFFCD004; - memctl->memc_mcr = 0x0119 | UPMB; - - memctl->memc_mdr = 0x0FFCC000; - memctl->memc_mcr = 0x011A | UPMB; - - memctl->memc_mdr = 0x7FFCC004; - memctl->memc_mcr = 0x011B | UPMB; - - memctl->memc_mdr = 0xFFFDCC05; - memctl->memc_mcr = 0x011C | UPMB; - - /* Initialize OR3 / BR3 for CAN Bus Controller */ - memctl->memc_or3 = CONFIG_SYS_OR3_CAN; - memctl->memc_br3 = CONFIG_SYS_BR3_CAN; -} - -void can_driver_disable (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - /* Reset OR3 / BR3 to disable CAN Bus Controller */ - memctl->memc_br3 = 0; - memctl->memc_or3 = 0; - - memctl->memc_mbmr = 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, long int maxsize) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size(base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) - -#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN) - -void reset_phy(void) -{ - immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#ifdef CONFIG_SYS_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; -#else - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */ -#endif - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */ - - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CONFIG_SYS_PB_ETH_POWERDOWN; - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#ifdef CONFIG_SYS_ETH_CFG1_VALUE - value |= CONFIG_SYS_PB_ETH_CFG1; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG1); -#endif -#ifdef CONFIG_SYS_ETH_CFG2_VALUE - value |= CONFIG_SYS_PB_ETH_CFG2; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG2); -#endif -#ifdef CONFIG_SYS_ETH_CFG3_VALUE - value |= CONFIG_SYS_PB_ETH_CFG3; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET; - udelay (1000); -} - - -int misc_init_r (void) -{ - fpga_init(); - return (0); -} -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c deleted file mode 100644 index ad1ed793de..0000000000 --- a/board/siemens/CCM/flash.c +++ /dev/null @@ -1,553 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - /* Remap FLASH according to real size */ - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - if (size_b1) { - memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), - &flash_info[1]); - - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - switch (value) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - switch (value) { - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c deleted file mode 100644 index 50b08abce7..0000000000 --- a/board/siemens/CCM/fpga_ccm.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <common.h> - -#include "../common/fpga.h" - -fpga_t fpga_list[] = { - { "PUMA" , PUMA_CONF_BASE , - CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE } -}; -int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); - -void can_driver_enable (void); -void can_driver_disable (void); - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = -{ - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - - -ulong fpga_control (fpga_t* fpga, int cmd) -{ - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - switch (cmd) { - case FPGA_INIT_IS_HIGH: - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */ - return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0; - - case FPGA_INIT_SET_LOW: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat &= ~fpga->init_mask; - break; - - case FPGA_INIT_SET_HIGH: - immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */ - immr->im_ioport.iop_pcdat |= fpga->init_mask; - break; - - case FPGA_PROG_SET_LOW: - immr->im_ioport.iop_pcdat &= ~fpga->prog_mask; - break; - - case FPGA_PROG_SET_HIGH: - immr->im_ioport.iop_pcdat |= fpga->prog_mask; - break; - - case FPGA_DONE_IS_HIGH: - return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0; - - case FPGA_READ_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; - - /* (re-) enable CAN drivers */ - can_driver_enable (); - - break; - - case FPGA_LOAD_MODE: - /* disable FPGA in memory controller */ - memctl->memc_br4 = 0; - /* - * We must disable the CAN drivers first because - * they use UPM B, too. - */ - can_driver_disable (); - /* - * Configure UPMB for FPGA - */ - upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint)); - memctl->memc_or4 = PUMA_CONF_OR_LOAD; - memctl->memc_br4 = PUMA_CONF_BR_LOAD; - break; - - case FPGA_GET_ID: - return *(volatile ulong *)fpga->conf_base; - - case FPGA_INIT_PORTS: - immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */ - immr->im_ioport.iop_pcso &= ~fpga->init_mask; - immr->im_ioport.iop_pcdir &= ~fpga->init_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */ - immr->im_ioport.iop_pcso &= ~fpga->prog_mask; - immr->im_ioport.iop_pcdir |= fpga->prog_mask; - - immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */ - immr->im_ioport.iop_pcso &= ~fpga->done_mask; - immr->im_ioport.iop_pcdir &= ~fpga->done_mask; - - break; - - } - return 0; -} diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds deleted file mode 100644 index 36dd55dee4..0000000000 --- a/board/siemens/CCM/u-boot.lds +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - arch/powerpc/lib/ppcstring.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - lib/zlib.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug deleted file mode 100644 index 7e066b11e5..0000000000 --- a/board/siemens/CCM/u-boot.lds.debug +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) -/* - . = env_offset; - common/env_embedded.o(.text) -*/ - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/Makefile b/board/siemens/pcu_e/Makefile deleted file mode 100644 index dcb1907032..0000000000 --- a/board/siemens/pcu_e/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o flash.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c deleted file mode 100644 index 3ce7bb329a..0000000000 --- a/board/siemens/pcu_e/flash.c +++ /dev/null @@ -1,700 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -#if defined(CONFIG_ENV_IS_IN_FLASH) -# ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -# endif -# ifndef CONFIG_ENV_SIZE -# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -# endif -# ifndef CONFIG_ENV_SECT_SIZE -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - * - * The PCU E uses an address map where flash banks are aligned top - * down, so that the "first" flash bank ends at top of memory, and - * the monitor entry point is at address (0xFFF00100). The second - * flash bank is mapped immediately below bank 0. - * - * This is NOT in conformance to the "official" memory map! - * - */ - -#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \ - - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) ) - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long base, size_b0, size_b1; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - /* - * Warning: - * - * Since the PCU E memory map assigns flash banks top down, - * we swap the numbering later if both banks are equipped, - * so they look like a contiguous area of memory. - */ - DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM); - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM); - size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]); - - DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - DEBUGF ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br6, memctl->memc_or6); - - /* Remap FLASH according to real size */ - base = 0 - size_b0; - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)base, &flash_info[0]); - base = 0 - size_b0; - - flash_info[0].size = size_b0; - - flash_get_offsets (base, &flash_info[0]); - - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - PCU_MONITOR_BASE, - PCU_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif - - if (size_b1) { - flash_info_t tmp_info; - - memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) | - BR_PS_16 | BR_MS_GPCM | BR_V; - - DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n", - memctl->memc_br6, memctl->memc_or6); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(base - size_b1), - &flash_info[1]); - base -= size_b1; - - flash_get_offsets (base, &flash_info[1]); - - flash_info[1].size = size_b1; - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[1]); -#endif - /* - * Swap bank numbers so that addresses are in ascending order - */ - tmp_info = flash_info[0]; - flash_info[0] = flash_info[1]; - flash_info[1] = tmp_info; - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - - DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - short n; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) { - return; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322T: - case FLASH_AMDL323T: - case FLASH_AMDL324T: - /* set sector offsets for top boot block type */ - - base += info->size; - i = info->sector_count; - for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */ - base -= 8 << 10; - --i; - info->start[i] = base; - } - while (i > 0) { /* 64k regular sectors */ - base -= 64 << 10; - --i; - info->start[i] = base; - } - return; - case FLASH_AMDL322B: - case FLASH_AMDL323B: - case FLASH_AMDL324B: - /* set sector offsets for bottom boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - while (base < info->size) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - return; - case FLASH_AMDL640: - /* set sector offsets for dual boot block type */ - for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - } - n = info->sector_count - 8; - while (i < n) { /* 64k regular sectors */ - info->start[i] = base; - base += 64 << 10; - ++i; - } - while (i < info->sector_count) { /* 8 x 8k boot sectors */ - info->start[i] = base; - base += 8 << 10; - ++i; - } - return; - default: - return; - } - /* NOTREACHED */ -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n"); - break; - default: printf ("Unknown Chip Type 0x%lX\n", - info->flash_id); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ushort value; - vu_short *saddr = (vu_short *)addr; - - /* Write auto select command: read Manufacturer ID */ - saddr[0x0555] = 0x00AA; - saddr[0x02AA] = 0x0055; - saddr[0x0555] = 0x0090; - - value = saddr[0]; - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value); - - switch (value) { - case (AMD_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_AMD; - break; - case (FUJ_MANUFACT & 0xFFFF): - info->flash_id = FLASH_MAN_FUJ; - break; - default: - DEBUGF("Unknown Manufacturer ID\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = saddr[1]; /* device ID */ - - DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value); - - switch (value) { - - case (AMD_ID_DL322T & 0xFFFF): - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL322B & 0xFFFF): - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323T & 0xFFFF): - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL323B & 0xFFFF): - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324T & 0xFFFF): - info->flash_id += FLASH_AMDL324T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - - case (AMD_ID_DL324B & 0xFFFF): - info->flash_id += FLASH_AMDL324B; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 8 MB */ - case (AMD_ID_DL640 & 0xFFFF): - info->flash_id += FLASH_AMDL640; - info->sector_count = 142; - info->size = 0x00800000; - break; - default: - DEBUGF("Unknown Device ID\n"); - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - flash_get_offsets ((ulong)addr, info); - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { -#if 0 - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - saddr = (vu_short *)(info->start[i]); - info->protect[i] = saddr[2] & 1; -#else - info->protect[i] =0; -#endif - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - saddr = (vu_short *)info->start[0]; - *saddr = 0x00F0; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x0080; - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_short*)(info->start[sect]); - addr[0] = 0x0030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_short*)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -#define FLASH_WIDTH 2 /* flash bus width in bytes */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<FLASH_WIDTH && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += FLASH_WIDTH; - } - - /* - * handle FLASH_WIDTH aligned part - */ - while (cnt >= FLASH_WIDTH) { - data = 0; - for (i=0; i<FLASH_WIDTH; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data(info, wp, data)) != 0) { - return (rc); - } - wp += FLASH_WIDTH; - cnt -= FLASH_WIDTH; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<FLASH_WIDTH; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_data(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, ulong data) -{ - vu_short *addr = (vu_short*)(info->start[0]); - vu_short *sdest = (vu_short *)dest; - ushort sdata = (ushort)data; - ushort sval; - ulong start, passed; - int flag, rc; - - /* Check if Flash is (sufficiently) erased */ - if ((*sdest & sdata) != sdata) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA; - addr[0x02AA] = 0x0055; - addr[0x0555] = 0x00A0; - -#ifdef WORKAROUND_FOR_BROKEN_HARDWARE - /* work around the timeout bugs */ - udelay(20); -#endif - - *sdest = sdata; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - rc = 0; - /* data polling for D7 */ - start = get_timer (0); - - for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) { - - sval = *sdest; - - if ((sval & 0x0080) == (sdata & 0x0080)) - break; - - if ((sval & 0x0020) == 0) /* DQ5: Timeout? */ - continue; - - sval = *sdest; - - if ((sval & 0x0080) != (sdata & 0x0080)) - rc = 1; - - break; - } - - if (rc) { - DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - } - - if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) { - DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n", - dest, sval, sdata); - rc = 1; - } - - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - return (rc); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c deleted file mode 100644 index 97952844f9..0000000000 --- a/board/siemens/pcu_e/pcu_e.c +++ /dev/null @@ -1,562 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <i2c.h> -#include <command.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); -static void puma_status (void); -static void puma_set_mode (int mode); -static int puma_init_done (void); -static void puma_load (ulong addr, ulong len); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFFFFF - -/* - * 50 MHz SDRAM access using UPM A - */ -const uint sdram_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00, - 0x1ffddc47, /* last */ - /* - * SDRAM Initialization (offset 5 in UPM RAM) - * - * This is no UPM entry point. The following definition uses - * the remaining space to establish an initialization - * sequence, which is executed by a RUN command. - * - */ - 0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */ - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00, - 0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - 0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00, - 0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - 0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, /* last */ - _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - -/* - * PUMA access using UPM B - */ -const uint puma_table[] = { - /* - * Single Read. (Offset 0 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, - /* - * Precharge and MRS - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Read. (Offset 8 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Single Write. (Offset 18 in UPM RAM) - */ - 0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */ - _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Burst Write. (Offset 20 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Refresh (Offset 30 in UPM RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - /* - * Exception. (Offset 3c in UPM RAM) - */ - 0x7ffffc07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - * - */ - -int checkboard (void) -{ - puts ("Board: Siemens PCU E\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - long int size_b0, reg; - int i; - - /* - * Configure UPMA for SDRAM - */ - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = 0x00000088; - - /* - * Map controller bank 2 to the SDRAM bank at preliminary address. - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; - memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; -#else /* XXX */ - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; -#endif /* XXX */ - - /* initialize memory address register */ - memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */ - - /* mode initialization (offset 5) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (200); /* 0x8000A105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05); -#else /* XXX */ - udelay (200); /* 0x80004105 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05); -#endif /* XXX */ - - /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30); -#else /* XXX */ - udelay (1); /* 0x80004830 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30); -#endif /* XXX */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - udelay (1); /* 0x8000A106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06); -#else /* XXX */ - udelay (1); /* 0x80004106 */ - memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06); -#endif /* XXX */ - - reg = memctl->memc_mamr; - reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */ - reg |= MAMR_TLFA_4X; /* ... to 4x */ - reg |= MAMR_PTAE; /* enable refresh */ - memctl->memc_mamr = reg; - - udelay (200); - - /* Need at least 10 DRAM accesses to stabilize */ - for (i = 0; i < 10; ++i) { -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE5_PRELIM; -#else /* XXX */ - volatile unsigned long *addr = - (volatile unsigned long *) SDRAM_BASE2_PRELIM; -#endif /* XXX */ - unsigned long val; - - val = *(addr + i); - *(addr + i) = val; - } - - /* - * Check Bank 0 Memory Size for re-configuration - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); -#else /* XXX */ - size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); -#endif /* XXX */ - - memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE; - - /* - * Final mapping: - */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#else /* XXX */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; -#endif /* XXX */ - udelay (1000); - - /* - * Configure UPMB for PUMA - */ - upmconfig (UPMB, (uint *) puma_table, - sizeof (puma_table) / sizeof (uint)); - - return (size_b0); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} - -/* ------------------------------------------------------------------------- */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#else /* XXX */ -#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \ - CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#endif /* XXX */ - -#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET) - -void reset_phy (void) -{ - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - ulong value; - - /* Configure all needed port pins for GPIO */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; -# else - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */ -# endif - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */ -#endif /* XXX */ - immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ - - value = immr->im_cpm.cp_pbdat; - - /* Assert Powerdown and Reset signals */ - value |= CONFIG_SYS_PB_ETH_POWERDOWN; - value &= ~(CONFIG_SYS_PB_ETH_RESET); - - /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#if !PCU_E_WITH_SWAPPED_CS -# ifdef CONFIG_SYS_ETH_MDDIS_VALUE - value |= CONFIG_SYS_PB_ETH_MDDIS; -# else - value &= ~(CONFIG_SYS_PB_ETH_MDDIS); -# endif -#endif -#ifdef CONFIG_SYS_ETH_CFG1_VALUE - value |= CONFIG_SYS_PB_ETH_CFG1; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG1); -#endif -#ifdef CONFIG_SYS_ETH_CFG2_VALUE - value |= CONFIG_SYS_PB_ETH_CFG2; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG2); -#endif -#ifdef CONFIG_SYS_ETH_CFG3_VALUE - value |= CONFIG_SYS_PB_ETH_CFG3; -#else - value &= ~(CONFIG_SYS_PB_ETH_CFG3); -#endif - - /* Drive output signals to initial state */ - immr->im_cpm.cp_pbdat = value; - immr->im_cpm.cp_pbdir |= ETH_ALL_BITS; - udelay (10000); - - /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ - udelay (10000); - - /* de-assert RESET signal of PHY */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET; - udelay (1000); -} - -/*----------------------------------------------------------------------- - * Board Special Commands: access functions for "PUMA" FPGA - */ -#if defined(CONFIG_CMD_BSP) - -#define PUMA_READ_MODE 0 -#define PUMA_LOAD_MODE 1 - -int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr, len; - - switch (argc) { - case 2: /* PUMA reset */ - if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */ - puma_status (); - return 0; - } - break; - case 4: /* PUMA load addr len */ - if (strcmp (argv[1], "load") != 0) - break; - - addr = simple_strtoul (argv[2], NULL, 16); - len = simple_strtoul (argv[3], NULL, 16); - - printf ("PUMA load: addr %08lX len %ld (0x%lX): ", - addr, len, len); - puma_load (addr, len); - - return 0; - default: - break; - } - return cmd_usage(cmdtp); -} - -U_BOOT_CMD (puma, 4, 1, do_puma, - "access PUMA FPGA", - "status - print PUMA status\n" - "puma load addr len - load PUMA configuration data" -); -#endif - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_set_mode (int mode) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - /* disable PUMA in memory controller */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_br3 = 0; -#else /* XXX */ - memctl->memc_br4 = 0; -#endif /* XXX */ - - switch (mode) { - case PUMA_READ_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_READ; - memctl->memc_br3 = PUMA_CONF_BR_READ; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - case PUMA_LOAD_MODE: -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or3 = PUMA_CONF_OR_LOAD; - memctl->memc_br3 = PUMA_CONF_BR_LOAD; -#else /* XXX */ - memctl->memc_or4 = PUMA_CONF_OR_READ; - memctl->memc_br4 = PUMA_CONF_BR_READ; -#endif /* XXX */ - break; - } -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */ - -static void puma_load (ulong addr, ulong len) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */ - uchar *data = (uchar *) addr; - int i; - - /* align length */ - if (len & 1) - ++len; - - /* Reset FPGA */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */ - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT); - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */ - immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */ - immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */ -#else - immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */ - immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */ - immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */ - immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */ -#endif /* XXX */ - udelay (100); - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */ -#else - immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */ -#endif /* XXX */ - - /* wait until INIT indicates completion of reset */ - for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) { - udelay (1000); - if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT) - break; - } - if (i == PUMA_INIT_TIMEOUT) { - printf ("*** PUMA init timeout ***\n"); - return; - } - - puma_set_mode (PUMA_LOAD_MODE); - - while (len--) - *fpga_addr = *data++; - - puma_set_mode (PUMA_READ_MODE); - - puma_status (); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static void puma_status (void) -{ - /* Check state */ - printf ("PUMA initialization is %scomplete\n", - puma_init_done ()? "" : "NOT "); -} - -/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */ - -static int puma_init_done (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - - /* make sure pin is GPIO input */ - immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE); - immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE); - immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE); - - return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0; -} - -/* ------------------------------------------------------------------------- */ - -int misc_init_r (void) -{ - ulong addr = 0; - ulong len = 0; - char *s; - - printf ("PUMA: "); - if (puma_init_done ()) { - printf ("initialized\n"); - return 0; - } - - if ((s = getenv ("puma_addr")) != NULL) - addr = simple_strtoul (s, NULL, 16); - - if ((s = getenv ("puma_len")) != NULL) - len = simple_strtoul (s, NULL, 16); - - if ((!addr) || (!len)) { - printf ("net list undefined\n"); - return 0; - } - - printf ("loading... "); - - puma_load (addr, len); - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds deleted file mode 100644 index b871958f1b..0000000000 --- a/board/siemens/pcu_e/u-boot.lds +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/env_embedded.o(.text) - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.eh_frame) - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug deleted file mode 100644 index 131ad23c77..0000000000 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - arch/powerpc/lib/extable.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk index 3f9d41f371..30b92a3c43 100644 --- a/board/tcm-bf518/config.mk +++ b/board/tcm-bf518/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf518-0.0 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk index bc046f129f..1281da4bef 100644 --- a/board/tcm-bf537/config.mk +++ b/board/tcm-bf537/config.mk @@ -26,6 +26,8 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +CONFIG_BFIN_CPU = bf537-0.2 + CFLAGS_lib += -O2 CFLAGS_lib/lzma += -O2 diff --git a/board/tcm-bf537/gpio_cfi_flash.c b/board/tcm-bf537/gpio_cfi_flash.c index 08ea7af1fe..c4fef9f5e7 100644 --- a/board/tcm-bf537/gpio_cfi_flash.c +++ b/board/tcm-bf537/gpio_cfi_flash.c @@ -1,60 +1,3 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> -#include <asm/blackfin.h> -#include <asm/gpio.h> -#include <asm/io.h> -#include "gpio_cfi_flash.h" - -#define GPIO_PIN_1 GPIO_PF4 -#define GPIO_MASK_1 (1 << 21) -#define GPIO_PIN_2 GPIO_PF5 -#define GPIO_MASK_2 (1 << 22) -#define GPIO_MASK (GPIO_MASK_1 | GPIO_MASK_2) - -void *gpio_cfi_flash_swizzle(void *vaddr) -{ - unsigned long addr = (unsigned long)vaddr; - - gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1); - -#ifdef GPIO_MASK_2 - gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2); -#endif - - SSYNC(); - - return (void *)(addr & ~GPIO_MASK); -} - -#define __raw_writeq(value, addr) *(volatile u64 *)addr = value -#define __raw_readq(addr) *(volatile u64 *)addr - -#define MAKE_FLASH(size, sfx) \ -void flash_write##size(u##size value, void *addr) \ -{ \ - __raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \ -} \ -u##size flash_read##size(void *addr) \ -{ \ - return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \ -} -MAKE_FLASH(8, b) /* flash_write8() flash_read8() */ -MAKE_FLASH(16, w) /* flash_write16() flash_read16() */ -MAKE_FLASH(32, l) /* flash_write32() flash_read32() */ -MAKE_FLASH(64, q) /* flash_write64() flash_read64() */ - -void gpio_cfi_flash_init(void) -{ - gpio_request(GPIO_PIN_1, "gpio_cfi_flash"); -#ifdef GPIO_MASK_2 - gpio_request(GPIO_PIN_2, "gpio_cfi_flash"); -#endif - gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE); -} +#define GPIO_PIN_1 GPIO_PF4 +#define GPIO_PIN_2 GPIO_PF5 +#include "../cm-bf537e/gpio_cfi_flash.c" diff --git a/board/tcm-bf537/gpio_cfi_flash.h b/board/tcm-bf537/gpio_cfi_flash.h deleted file mode 100644 index 5211e972ad..0000000000 --- a/board/tcm-bf537/gpio_cfi_flash.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support - * - * Copyright (c) 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -void *gpio_cfi_flash_swizzle(void *vaddr); -void gpio_cfi_flash_init(void); diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 60742dfea5..04d6bdbd3e 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -13,7 +13,7 @@ #include <netdev.h> #include <asm/blackfin.h> #include <asm/net.h> -#include "gpio_cfi_flash.h" +#include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/boards.cfg b/boards.cfg index 88c40602a5..62ffa420ee 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,14 +94,14 @@ PATI powerpc mpc5xx pati mpl BC3450 powerpc mpc5xxx bc3450 canmb powerpc mpc5xxx cm5200 powerpc mpc5xxx -hmi1001 powerpc mpc5xxx +hmi1001 powerpc mpc5xxx - manroland inka4x0 powerpc mpc5xxx ipek01 powerpc mpc5xxx jupiter powerpc mpc5xxx -mucmc52 powerpc mpc5xxx +mucmc52 powerpc mpc5xxx - manroland munices powerpc mpc5xxx o2dnt powerpc mpc5xxx -uc101 powerpc mpc5xxx +uc101 powerpc mpc5xxx - manroland v38b powerpc mpc5xxx pf5200 powerpc mpc5xxx - esd aev powerpc mpc5xxx tqm5200 tqc @@ -154,7 +154,7 @@ RBC823 powerpc mpc8xx rbc823 rmu powerpc mpc8xx RPXlite powerpc mpc8xx spc1920 powerpc mpc8xx -uc100 powerpc mpc8xx +uc100 powerpc mpc8xx - manroland MHPC powerpc mpc8xx mhpc eltec TOP860 powerpc mpc8xx top860 emk kmsupx4 powerpc mpc8xx km8xx keymile @@ -162,9 +162,7 @@ mgsuvd powerpc mpc8xx km8xx keymile KUP4K powerpc mpc8xx kup4k kup KUP4X powerpc mpc8xx kup4x kup ELPT860 powerpc mpc8xx elpt860 LEOX -CCM powerpc mpc8xx - siemens IAD210 powerpc mpc8xx - siemens -pcu_e powerpc mpc8xx - siemens QS823 powerpc mpc8xx qs850 snmc QS850 powerpc mpc8xx qs850 snmc QS860T powerpc mpc8xx qs860t snmc @@ -185,6 +183,7 @@ t3corp powerpc ppc4xx zeus powerpc ppc4xx acadia powerpc ppc4xx - amcc bamboo powerpc ppc4xx - amcc +bluestone powerpc ppc4xx - amcc bubinga powerpc ppc4xx - amcc ebony powerpc ppc4xx - amcc katmai powerpc ppc4xx - amcc @@ -280,10 +279,12 @@ atstk1004 avr32 at32ap atstk1000 atmel at32ap700x atstk1006 avr32 at32ap atstk1000 atmel at32ap700x favr-32-ezkit avr32 at32ap - earthlcd at32ap700x hammerhead avr32 at32ap - miromico at32ap700x +bct-brettl2 blackfin blackfin bf518f-ezbrd blackfin blackfin bf526-ezbrd blackfin blackfin bf527-ad7160-eval blackfin blackfin bf527-ezkit blackfin blackfin +bf527-sdp blackfin blackfin bf533-ezkit blackfin blackfin bf533-stamp blackfin blackfin bf537-minotaur blackfin blackfin @@ -295,6 +296,7 @@ bf548-ezkit blackfin blackfin bf561-acvilon blackfin blackfin bf561-ezkit blackfin blackfin blackstamp blackfin blackfin +blackvme blackfin blackfin cm-bf527 blackfin blackfin cm-bf533 blackfin blackfin cm-bf537e blackfin blackfin diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 6b611b1482..1326c8fac1 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -385,7 +385,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bd_t *bd = gd->bd; char buf[32]; - print_num ("env_t", (ulong)bd->bi_env); print_num ("boot_params", (ulong)bd->bi_boot_params); print_num ("bi_memstart", bd->bi_memstart); print_num ("bi_memsize", bd->bi_memsize); diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 104d6e68b3..bf3261256f 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; #endif int valid_elf_image (unsigned long addr); -unsigned long load_elf_image (unsigned long addr); +static unsigned long load_elf_image_phdr(unsigned long addr); +static unsigned long load_elf_image_shdr(unsigned long addr); /* Allow ports to override the default behavior */ __attribute__((weak)) @@ -61,19 +62,34 @@ int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned long addr; /* Address of the ELF image */ unsigned long rc; /* Return value from user code */ + char *sload, *saddr; /* -------------------------------------------------- */ int rcode = 0; - if (argc < 2) - addr = load_addr; + sload = saddr = NULL; + if (argc == 3) { + sload = argv[1]; + saddr = argv[2]; + } else if (argc == 2) { + if (argv[1][0] == '-') + sload = argv[1]; + else + saddr = argv[1]; + } + + if (saddr) + addr = simple_strtoul(saddr, NULL, 16); else - addr = simple_strtoul (argv[1], NULL, 16); + addr = load_addr; if (!valid_elf_image (addr)) return 1; - addr = load_elf_image (addr); + if (sload && sload[1] == 'p') + addr = load_elf_image_phdr(addr); + else + addr = load_elf_image_shdr(addr); printf ("## Starting application at 0x%08lx ...\n", addr); @@ -204,7 +220,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) */ if (valid_elf_image (addr)) { - addr = load_elf_image (addr); + addr = load_elf_image_shdr (addr); } else { puts ("## Not an ELF image, assuming binary\n"); /* leave addr as load_addr */ @@ -258,7 +274,33 @@ int valid_elf_image (unsigned long addr) * A very simple elf loader, assumes the image is valid, returns the * entry point address. * ====================================================================== */ -unsigned long load_elf_image (unsigned long addr) +static unsigned long load_elf_image_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *) addr; + phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *) phdr->p_paddr; + void *src = (void *) addr + phdr->p_offset; + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst, phdr->p_filesz); + ++phdr; + } + + return ehdr->e_entry; +} + +static unsigned long load_elf_image_shdr(unsigned long addr) { Elf32_Ehdr *ehdr; /* Elf header structure pointer */ Elf32_Shdr *shdr; /* Section header structure pointer */ @@ -312,9 +354,11 @@ unsigned long load_elf_image (unsigned long addr) /* ====================================================================== */ U_BOOT_CMD( - bootelf, 2, 0, do_bootelf, + bootelf, 3, 0, do_bootelf, "Boot from an ELF image in memory", - " [address] - load address of ELF image." + "[-p|-s] [address]\n" + "\t- load ELF image at [address] via program headers (-p)\n" + "\t or via section headers (-s)" ); U_BOOT_CMD( diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index c3d63b8a43..3d30c321d5 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -837,6 +837,13 @@ static cmd_tbl_t cmd_env_sub[] = { U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""), }; +#if !defined(CONFIG_RELOC_FIXUP_WORKS) +void env_reloc(void) +{ + fixup_cmdtable(cmd_env_sub, ARRAY_SIZE(cmd_env_sub)); +} +#endif + static int do_env (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cmd_tbl_t *cp; diff --git a/common/cmd_otp.c b/common/cmd_otp.c index 56f08e0c05..eb93eb2db9 100644 --- a/common/cmd_otp.c +++ b/common/cmd_otp.c @@ -82,6 +82,7 @@ static void set_otp_timing(bool write) int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + char *cmd; uint32_t ret, base_flags; bool prompt_user, force_read; uint32_t (*otp_func)(uint32_t page, uint32_t flags, uint64_t *page_content); @@ -93,21 +94,21 @@ int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) prompt_user = false; base_flags = 0; - if (!strcmp(argv[1], "read")) + cmd = argv[1]; + if (!strcmp(cmd, "read")) otp_func = bfrom_OtpRead; - else if (!strcmp(argv[1], "dump")) { + else if (!strcmp(cmd, "dump")) { otp_func = bfrom_OtpRead; force_read = true; - } else if (!strcmp(argv[1], "write")) { + } else if (!strcmp(cmd, "write")) { otp_func = bfrom_OtpWrite; base_flags = OTP_CHECK_FOR_PREV_WRITE; if (!strcmp(argv[2], "--force")) { - argv[2] = argv[1]; argv++; --argc; } else prompt_user = false; - } else if (!strcmp(argv[1], "lock")) { + } else if (!strcmp(cmd, "lock")) { if (argc != 4) goto usage; otp_func = bfrom_OtpWrite; @@ -175,7 +176,7 @@ int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } printf("OTP memory %s: addr 0x%p page 0x%03X count %zu ... ", - argv[1], addr, page, count); + cmd, addr, page, count); set_otp_timing(otp_func == bfrom_OtpWrite); if (otp_func == bfrom_OtpWrite && check_voltage()) { diff --git a/common/cmd_spi.c b/common/cmd_spi.c index bafa217d03..8c623c9fcf 100644 --- a/common/cmd_spi.c +++ b/common/cmd_spi.c @@ -47,7 +47,9 @@ /* * Values from last command. */ -static unsigned int device; +static unsigned int bus; +static unsigned int cs; +static unsigned int mode; static int bitlen; static uchar dout[MAX_SPI_BYTES]; static uchar din[MAX_SPI_BYTES]; @@ -78,8 +80,18 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((flag & CMD_FLAG_REPEAT) == 0) { - if (argc >= 2) - device = simple_strtoul(argv[1], NULL, 10); + if (argc >= 2) { + mode = CONFIG_DEFAULT_SPI_MODE; + bus = simple_strtoul(argv[1], &cp, 10); + if (*cp == ':') { + cs = simple_strtoul(cp+1, &cp, 10); + } else { + cs = bus; + bus = CONFIG_DEFAULT_SPI_BUS; + } + if (*cp == '.'); + mode = simple_strtoul(cp+1, NULL, 10); + } if (argc >= 3) bitlen = simple_strtoul(argv[2], NULL, 10); if (argc >= 4) { @@ -91,7 +103,7 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if(tmp > 15) tmp -= ('a' - 'A'); if(tmp > 15) { - printf("Hex conversion error on %c, giving up.\n", *cp); + printf("Hex conversion error on %c\n", *cp); return 1; } if((j % 2) == 0) @@ -103,24 +115,20 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if ((bitlen < 0) || (bitlen > (MAX_SPI_BYTES * 8))) { - printf("Invalid bitlen %d, giving up.\n", bitlen); + printf("Invalid bitlen %d\n", bitlen); return 1; } - /* FIXME: Make these parameters run-time configurable */ - slave = spi_setup_slave(CONFIG_DEFAULT_SPI_BUS, device, 1000000, - CONFIG_DEFAULT_SPI_MODE); + slave = spi_setup_slave(bus, cs, 1000000, mode); if (!slave) { - printf("Invalid device %d, giving up.\n", device); + printf("Invalid device %d:%d\n", bus, cs); return 1; } - debug ("spi chipsel = %08X\n", device); - spi_claim_bus(slave); if(spi_xfer(slave, bitlen, dout, din, SPI_XFER_BEGIN | SPI_XFER_END) != 0) { - printf("Error with the SPI transaction.\n"); + printf("Error during SPI transaction\n"); rcode = 1; } else { for(j = 0; j < ((bitlen + 7) / 8); j++) { @@ -138,9 +146,11 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( sspi, 5, 1, do_spi, - "SPI utility commands", - "<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n" - "<device> - Identifies the chip select of the device\n" + "SPI utility command", + "[<bus>:]<cs>[.<mode>] <bit_len> <dout> - Send and receive bits\n" + "<bus> - Identifies the SPI bus\n" + "<cs> - Identifies the chip select\n" + "<mode> - Identifies the SPI mode to use\n" "<bit_len> - Number of bits to send (base 10)\n" "<dout> - Hexadecimal string that gets sent" ); diff --git a/common/env_common.c b/common/env_common.c index a415ef8efe..88f068cc38 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -227,6 +227,11 @@ int env_import(const char *buf, int check) void env_relocate (void) { +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + extern void env_reloc(void); + + env_reloc(); +#endif if (gd->env_valid == 0) { #if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */ set_default_env(NULL); diff --git a/common/env_mmc.c b/common/env_mmc.c index 14203b6e2e..cc288d487c 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -147,7 +147,6 @@ void env_relocate_spec(void) #if !defined(ENV_IS_EMBEDDED) static void use_default() { - puts ("*** Warning - bad CRC or MMC, using default environment\n\n"); - set_default_env(); + set_default_env(NULL); } #endif diff --git a/common/fdt_support.c b/common/fdt_support.c index 6f32e3f68d..0ed6e77292 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -620,7 +620,7 @@ int fdt_fixup_nor_flash_size(void *blob) int off; int len; struct fdt_property *prop; - u32 *reg; + u32 *reg, *reg2; int i; for (i = 0; i < 2; i++) { @@ -640,18 +640,21 @@ int fdt_fixup_nor_flash_size(void *blob) * There might be multiple reg-tuples, * so loop through them all */ - len /= tuple_size; - reg = (u32 *)&prop->data[0]; - for (idx = 0; idx < len; idx++) { + reg = reg2 = (u32 *)&prop->data[0]; + for (idx = 0; idx < (len / tuple_size); idx++) { /* * Update size in reg property */ reg[2] = flash_get_bank_size(reg[0], idx); - fdt_setprop(blob, off, "reg", reg, - tuple_size); - reg += tuple_size; + + /* + * Point to next reg tuple + */ + reg += 3; } + + fdt_setprop(blob, off, "reg", reg2, len); } /* Move to next compatible node */ diff --git a/common/main.c b/common/main.c index 8d548dbc85..d97ccd7dd8 100644 --- a/common/main.c +++ b/common/main.c @@ -518,9 +518,6 @@ void reset_cmd_timeout(void) } while (0) #define CTL_CH(c) ((c) - 'a' + 1) - -#define MAX_CMDBUF_SIZE CONFIG_SYS_CBSIZE - #define CTL_BACKSPACE ('\b') #define DEL ((char)255) #define DEL7 ((char)127) @@ -531,7 +528,7 @@ void reset_cmd_timeout(void) #define getcmd_cbeep() getcmd_putch('\a') #define HIST_MAX 20 -#define HIST_SIZE MAX_CMDBUF_SIZE +#define HIST_SIZE CONFIG_SYS_CBSIZE static int hist_max = 0; static int hist_add_idx = 0; @@ -947,7 +944,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) { char *p = buffer; #ifdef CONFIG_CMDLINE_EDITING - unsigned int len=MAX_CMDBUF_SIZE; + unsigned int len = CONFIG_SYS_CBSIZE; int rc; static int initted = 0; diff --git a/common/serial.c b/common/serial.c index 25b235aa13..7bebc12a66 100644 --- a/common/serial.c +++ b/common/serial.c @@ -54,6 +54,7 @@ struct serial_device *__default_serial_console (void) #else #error "Bad CONFIG_CONS_INDEX." #endif +#else return &serial0_device; #endif #elif defined(CONFIG_MPC512X) diff --git a/doc/README.fsl-hwconfig b/doc/README.fsl-hwconfig new file mode 100644 index 0000000000..03fea74db3 --- /dev/null +++ b/doc/README.fsl-hwconfig @@ -0,0 +1,21 @@ +Freescale-specific 'hwconfig' options. + +This file documents Freescale-specific key:value pairs for the 'hwconfig' +option. See README.hwconfig for general information about 'hwconfig'. + +audclk + Specific to the P1022DS reference board. + + This option specifies which of the two oscillator frequencies should be + routed to the Wolfson WM8776 codec. The ngPIXIS can be programmed to + route either a 11.2896MHz or a 12.288MHz clock. The default is + 12.288MHz. This option has two effects. First, the MUX on the board + will be programmed accordingly. Second, the clock-frequency property + in the codec node in the device tree will be updated to the correct + value. + + 'audclk:11' + Select the 11.2896MHz clock + + 'audclk:12' + Select the 12.288MHz clock diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index 5fe21e863f..ffe261513c 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -1,11 +1,38 @@ The following is a list of files and features that are going to be removed from the U-Boot source tree. Every entry should contain what exactly is going away, when it will be gone, why it is being removed, -and who is going to be doing the work. When the feature is removed +and who is going to be doing the work. When the feature is removed from U-Boot, its corresponding entry should also be removed from this file. --------------------------- +What: CONFIG_SYS_ARM_WITHOUT_RELOC option +When: After Release 2011.03 + +Why: The implementation of U-Boot for the ARM architecture has + been reworked to support relocation. This allows to + efficiently use the same U-Boot binary image on systems with + different RAM sizes, and brings the implementation much more + in line with the code used for example on Power Architecture + systems (eventually allowing to merge into common code). This + seems especailly interesting now that ARM is getting Device + Tree support as well. + + All ARM boards need to be adapted to this new code, which + requires testing on the actual hardware, so this is a task + for the respective board maintainers or other users. + + Please see the commit message of commit f1d2b31 for details: + + http://git.denx.de/?p=u-boot.git;a=commit;h=f1d2b31 + + Support for CONFIG_SYS_ARM_WITHOUT_RELOC will be removed + after release v2011.03; all boards that have not been + converted by then, i. e. that are still broken then, are + considered unmaintained and without interest for the + community and will be removed as well. + +--------------------------- What: CONFIG_NET_MULTI option When: Release 2009-11 diff --git a/drivers/hwmon/ds1621.c b/drivers/hwmon/ds1621.c index d15a082df5..5a2ea62899 100644 --- a/drivers/hwmon/ds1621.c +++ b/drivers/hwmon/ds1621.c @@ -22,7 +22,7 @@ */ /* - * Dallas Semiconductor's DS1621 Digital Thermometer and Thermostat. + * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat. */ #include <common.h> @@ -32,7 +32,7 @@ /* * Device code */ -#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */ +#define DTT_I2C_DEV_CODE 0x48 /* Dallas Semi's DS1621 */ #define DTT_READ_TEMP 0xAA #define DTT_READ_COUNTER 0xA8 #define DTT_READ_SLOPE 0xA9 @@ -42,148 +42,147 @@ #define DTT_TEMP_LOW 0xA2 #define DTT_CONFIG 0xAC +/* + * Config register bits + */ +#define DTT_CONFIG_1SHOT 0x01 +#define DTT_CONFIG_POLARITY 0x02 +#define DTT_CONFIG_R0 0x04 /* ds1631 only */ +#define DTT_CONFIG_R1 0x08 /* ds1631 only */ +#define DTT_CONFIG_NVB 0x10 +#define DTT_CONFIG_TLF 0x20 +#define DTT_CONFIG_THF 0x40 +#define DTT_CONFIG_DONE 0x80 + + int dtt_read(int sensor, int reg) { - int dlen; - uchar data[2]; - - /* - * Calculate sensor address and command. - * - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/ - - /* - * Prepare to handle 2 byte result. - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) - dlen = 2; - else - dlen = 1; - - /* - * Now try to read the register. - */ - if (i2c_read(sensor, reg, 1, data, dlen) != 0) - return 1; - - /* - * Handle 2 byte result. - */ - if (dlen == 2) - return ((int)((short)data[1] + (((short)data[0]) << 8))); - - return (int)data[0]; -} /* dtt_read() */ + int dlen; + uchar data[2]; + + /* Calculate sensor address and command */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); /* Calculate addr of ds1621*/ + + /* Prepare to handle 2 byte result */ + switch(reg) { + case DTT_READ_TEMP: + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + dlen = 2; + break; + default: + dlen = 1; + } + + /* Now try to read the register */ + if (i2c_read(sensor, reg, 1, data, dlen) != 0) + return 1; + + /* Handle 2 byte result */ + if (dlen == 2) + return (short)((data[0] << 8) | data[1]); + + return (int)data[0]; +} int dtt_write(int sensor, int reg, int val) { - int dlen; - uchar data[2]; - - /* - * Calculate sensor address and register. - * - */ - sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); - - /* - * Handle various data sizes. - */ - if ((reg == DTT_READ_TEMP) || - (reg == DTT_TEMP_HIGH) || (reg == DTT_TEMP_LOW)) { - dlen = 2; - data[0] = (char)((val >> 8) & 0xff); /* MSB first */ - data[1] = (char)(val & 0xff); - } - else if ((reg == DTT_WRITE_START_CONV) || (reg == DTT_WRITE_STOP_CONV)) { - dlen = 0; - data[0] = (char)0; - data[1] = (char)0; - } - else { - dlen = 1; - data[0] = (char)(val & 0xff); - } - - /* - * Write value to device. - */ - if (i2c_write(sensor, reg, 1, data, dlen) != 0) - return 1; - - return 0; -} /* dtt_write() */ + int dlen; + uchar data[2]; + + /* Calculate sensor address and register */ + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07); + + /* Handle various data sizes. */ + switch(reg) { + case DTT_READ_TEMP: + case DTT_TEMP_HIGH: + case DTT_TEMP_LOW: + dlen = 2; + data[0] = (char)((val >> 8) & 0xff); /* MSB first */ + data[1] = (char)(val & 0xff); + break; + case DTT_WRITE_START_CONV: + case DTT_WRITE_STOP_CONV: + dlen = 0; + data[0] = (char)0; + data[1] = (char)0; + break; + default: + dlen = 1; + data[0] = (char)(val & 0xff); + } + + /* Write value to device */ + if (i2c_write(sensor, reg, 1, data, dlen) != 0) + return 1; + + /* Poll NV memory busy bit in case write was to register stored in EEPROM */ + while(i2c_reg_read(sensor, DTT_CONFIG) & DTT_CONFIG_NVB) + ; + + return 0; +} static int _dtt_init(int sensor) { - int val; - - /* - * Setup High Temp. - */ - val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ - - /* - * Setup Low Temp - hysteresis. - */ - val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; - if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ - - /* - * Setup configuraton register - * - * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES - * - * We run in polled mode, since there isn't any way to know if this - * lousy device is ready to provide temperature readings on power up. - */ - val = 0x9; - if (dtt_write(sensor, DTT_CONFIG, val) != 0) - return 1; - udelay(50000); /* Max 50ms */ - - return 0; -} /* _dtt_init() */ + int val; + + /* Setup High Temp */ + val = ((CONFIG_SYS_DTT_MAX_TEMP * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_HIGH, val) != 0) + return 1; + + /* Setup Low Temp - hysteresis */ + val = (((CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS) * 2) << 7) & 0xff80; + if (dtt_write(sensor, DTT_TEMP_LOW, val) != 0) + return 1; + + /* + * Setup configuraton register + * + * Clear THF & TLF, Reserved = 1, Polarity = Active Low, One Shot = YES + * + * We run in polled mode, since there isn't any way to know if this + * lousy device is ready to provide temperature readings on power up. + */ + val = 0x9; + if (dtt_write(sensor, DTT_CONFIG, val) != 0) + return 1; + + return 0; +} int dtt_init (void) { - int i; - unsigned char sensors[] = CONFIG_DTT_SENSORS; + int i; + unsigned char sensors[] = CONFIG_DTT_SENSORS; - for (i = 0; i < sizeof(sensors); i++) { - if (_dtt_init(sensors[i]) != 0) - printf("DTT%d: FAILED\n", i+1); - else - printf("DTT%d: %i C\n", i+1, dtt_get_temp(sensors[i])); - } + for (i = 0; i < sizeof(sensors); i++) { + if (_dtt_init(sensors[i]) != 0) + printf("DTT%d: FAILED\n", i + 1); + else + printf("DTT%d: %i C\n", i + 1, dtt_get_temp(sensors[i])); + } - return (0); -} /* dtt_init() */ + return (0); +} int dtt_get_temp(int sensor) { - int i; - - /* - * Start a conversion, may take up to 1 second. - */ - dtt_write(sensor, DTT_WRITE_START_CONV, 0); - for (i = 0; i <= 10; i++) { - udelay(100000); - if (dtt_read(sensor, DTT_CONFIG) & 0x80) - break; - } - - return (dtt_read(sensor, DTT_READ_TEMP) / 256); -} /* dtt_get_temp() */ + int i; + + /* Start a conversion, may take up to 1 second. */ + dtt_write(sensor, DTT_WRITE_START_CONV, 0); + for (i = 0; i <= 10; i++) { + udelay(100000); + if (dtt_read(sensor, DTT_CONFIG) & DTT_CONFIG_DONE) + break; + } + + return (dtt_read(sensor, DTT_READ_TEMP) / 256); +} diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 4a77779f5b..27d9bf6cbf 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -58,27 +58,29 @@ static int sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) { - unsigned int sdh_cmd; - unsigned int status; + unsigned int status, timeout; int cmd = mmc_cmd->cmdidx; int flags = mmc_cmd->resp_type; int arg = mmc_cmd->cmdarg; - int ret = 0; - sdh_cmd = 0; - - sdh_cmd |= cmd; + int ret; + u16 sdh_cmd; + sdh_cmd = cmd | CMD_E; if (flags & MMC_RSP_PRESENT) sdh_cmd |= CMD_RSP; - if (flags & MMC_RSP_136) sdh_cmd |= CMD_L_RSP; bfin_write_SDH_ARGUMENT(arg); - bfin_write_SDH_COMMAND(sdh_cmd | CMD_E); + bfin_write_SDH_COMMAND(sdh_cmd); /* wait for a while */ + timeout = 0; do { + if (++timeout > 1000000) { + status = CMD_TIME_OUT; + break; + } udelay(1); status = bfin_read_SDH_STATUS(); } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | @@ -94,12 +96,15 @@ sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) } if (status & CMD_TIME_OUT) - ret |= TIMEOUT; + ret = TIMEOUT; else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) - ret |= COMM_ERR; + ret = COMM_ERR; + else + ret = 0; bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT); + return ret; } diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index d6c1a5f9d3..c0900f978f 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -52,6 +52,7 @@ #define SPSN_ID_S25FL128P 0x2018 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 +#define SPSN_EXT_ID_S25FL032P 0x4d00 #define SPANSION_SR_WIP (1 << 0) /* Write-in-Progress */ @@ -124,6 +125,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .nr_sectors = 64, .name = "S25FL128P_256K", }, + { + .idcode1 = SPSN_ID_S25FL032A, + .idcode2 = SPSN_EXT_ID_S25FL032P, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "S25FL032P", + }, }; static int spansion_wait_ready(struct spi_flash *flash, unsigned long timeout) @@ -262,7 +271,6 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) return -1; } - len /= sector_size; cmd[0] = CMD_S25FLXX_SE; cmd[2] = 0x00; cmd[3] = 0x00; @@ -274,8 +282,8 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) } ret = 0; - for (actual = 0; actual < len; actual++) { - cmd[1] = (offset / sector_size) + actual; + for (actual = 0; actual < len; actual += sector_size) { + cmd[1] = (offset + actual) >> 16; ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { @@ -298,7 +306,7 @@ int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) } debug("SF: SPANSION: Successfully erased %u bytes @ 0x%x\n", - len * sector_size, offset); + len, offset); spi_release_bus(flash->spi); return ret; diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index ff1df25a1d..de3aeb810a 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -27,6 +27,7 @@ #define WINBOND_ID_W25X16 0x3015 #define WINBOND_ID_W25X32 0x3016 #define WINBOND_ID_W25X64 0x3017 +#define WINBOND_ID_W25Q64 0x4017 #define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */ @@ -77,6 +78,14 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .nr_blocks = 128, .name = "W25X64", }, + { + .id = WINBOND_ID_W25Q64, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25Q64", + }, }; static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout) diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 36d4046ec1..dcc781a46a 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -131,12 +131,12 @@ static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, goto out; } - if ((*pDMA2_IRQ_STATUS & DMA_ERR) != 0) { + if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) { printf("Ethernet: tx DMA error\n"); goto out; } - for (i = 0; (*pDMA2_IRQ_STATUS & DMA_RUN) != 0; i++) { + for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) { if (i > TOUT_LOOP) { puts("Ethernet: tx time out\n"); goto out; @@ -145,9 +145,9 @@ static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, txbuf[txIdx]->FrmData->NoBytes = length; memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length); txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData; - *pDMA2_NEXT_DESC_PTR = txbuf[txIdx]->Dma; - *pDMA2_CONFIG = txdmacfg.data; - *pEMAC_OPMODE |= TE; + bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma); + bfin_write_DMA2_CONFIG(txdmacfg.data); + bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) { if (i > TOUT_LOOP) { @@ -194,7 +194,7 @@ static int bfin_EMAC_recv(struct eth_device *dev) NetRxPackets[rxIdx] = (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest); NetReceive(NetRxPackets[rxIdx], length - 4); - *pDMA1_IRQ_STATUS |= DMA_DONE | DMA_ERR; + bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR); rxbuf[rxIdx]->StatusWord = 0x00000000; if ((rxIdx + 1) >= PKTBUFSRX) rxIdx = 0; @@ -229,7 +229,7 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) size_t count; /* Enable PHY output */ - *pVR_CTL |= CLKBUFOE; + bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); /* Set all the pins to peripheral mode */ peripheral_request_list(pins, "bfin_mac"); @@ -265,30 +265,32 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) bfin_write_EMAC_MMC_CTL(RSTC | CROLL); /* Initialize the TX DMA channel registers */ - *pDMA2_X_COUNT = 0; - *pDMA2_X_MODIFY = 4; - *pDMA2_Y_COUNT = 0; - *pDMA2_Y_MODIFY = 0; + bfin_write_DMA2_X_COUNT(0); + bfin_write_DMA2_X_MODIFY(4); + bfin_write_DMA2_Y_COUNT(0); + bfin_write_DMA2_Y_MODIFY(0); /* Initialize the RX DMA channel registers */ - *pDMA1_X_COUNT = 0; - *pDMA1_X_MODIFY = 4; - *pDMA1_Y_COUNT = 0; - *pDMA1_Y_MODIFY = 0; + bfin_write_DMA1_X_COUNT(0); + bfin_write_DMA1_X_MODIFY(4); + bfin_write_DMA1_Y_COUNT(0); + bfin_write_DMA1_Y_MODIFY(0); return 0; } static int bfin_EMAC_setup_addr(struct eth_device *dev) { - *pEMAC_ADDRLO = + bfin_write_EMAC_ADDRLO( dev->enetaddr[0] | dev->enetaddr[1] << 8 | dev->enetaddr[2] << 16 | - dev->enetaddr[3] << 24; - *pEMAC_ADDRHI = + dev->enetaddr[3] << 24 + ); + bfin_write_EMAC_ADDRHI( dev->enetaddr[4] | - dev->enetaddr[5] << 8; + dev->enetaddr[5] << 8 + ); return 0; } @@ -328,8 +330,8 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) } /* Set RX DMA */ - *pDMA1_NEXT_DESC_PTR = rxbuf[0]->Dma; - *pDMA1_CONFIG = rxbuf[0]->Dma[0].CONFIG_DATA; + bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma); + bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA); /* Wait MII done */ bfin_miiphy_wait(); @@ -350,7 +352,7 @@ static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd) opmode |= TE | RMII; #endif /* Turn on the EMAC */ - *pEMAC_OPMODE = opmode; + bfin_write_EMAC_OPMODE(opmode); return 0; } @@ -358,11 +360,10 @@ static void bfin_EMAC_halt(struct eth_device *dev) { debug("Eth_halt: ......\n"); /* Turn off the EMAC */ - *pEMAC_OPMODE = 0x00000000; + bfin_write_EMAC_OPMODE(0); /* Turn off the EMAC RX DMA */ - *pDMA1_CONFIG = 0x0000; - *pDMA2_CONFIG = 0x0000; - + bfin_write_DMA1_CONFIG(0); + bfin_write_DMA2_CONFIG(0); } ADI_ETHER_BUFFER *SetupRxBuffer(int no) @@ -443,16 +444,19 @@ int ether_post_test(int flags) uchar buf[64]; int i, value = 0; int length; + uint addr; printf("\n--------"); bfin_EMAC_init(NULL, NULL); /* construct the package */ - buf[0] = buf[6] = (unsigned char)(*pEMAC_ADDRLO & 0xFF); - buf[1] = buf[7] = (unsigned char)((*pEMAC_ADDRLO & 0xFF00) >> 8); - buf[2] = buf[8] = (unsigned char)((*pEMAC_ADDRLO & 0xFF0000) >> 16); - buf[3] = buf[9] = (unsigned char)((*pEMAC_ADDRLO & 0xFF000000) >> 24); - buf[4] = buf[10] = (unsigned char)(*pEMAC_ADDRHI & 0xFF); - buf[5] = buf[11] = (unsigned char)((*pEMAC_ADDRHI & 0xFF00) >> 8); + addr = bfin_read_EMAC_ADDRLO(); + buf[0] = buf[6] = addr; + buf[1] = buf[7] = addr >> 8; + buf[2] = buf[8] = addr >> 16; + buf[3] = buf[9] = addr >> 24; + addr = bfin_read_EMAC_ADDRHI(); + buf[4] = buf[10] = addr; + buf[5] = buf[11] = addr >> 8; buf[12] = 0x08; /* Type: ARP */ buf[13] = 0x06; buf[14] = 0x00; /* Hardware type: Ethernet */ diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index 556b97a64d..d7e14749dd 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -1,7 +1,7 @@ /* * Driver for Blackfin On-Chip SPI device * - * Copyright (c) 2005-2008 Analog Devices Inc. + * Copyright (c) 2005-2010 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -13,6 +13,7 @@ #include <spi.h> #include <asm/blackfin.h> +#include <asm/dma.h> #include <asm/gpio.h> #include <asm/portmux.h> #include <asm/mach-common/bits/spi.h> @@ -237,10 +238,131 @@ void spi_release_bus(struct spi_slave *slave) SSYNC(); } +#ifdef __ADSPBF54x__ +# define SPI_DMA_BASE DMA4_NEXT_DESC_PTR +#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) +# define SPI_DMA_BASE DMA5_NEXT_DESC_PTR +#elif defined(__ADSPBF561__) +# define SPI_DMA_BASE DMA2_4_NEXT_DESC_PTR +#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \ + defined(__ADSPBF52x__) || defined(__ADSPBF51x__) +# define SPI_DMA_BASE DMA7_NEXT_DESC_PTR +#else +# error "Please provide SPI DMA channel defines" +#endif +static volatile struct dma_register *dma = (void *)SPI_DMA_BASE; + #ifndef CONFIG_BFIN_SPI_IDLE_VAL # define CONFIG_BFIN_SPI_IDLE_VAL 0xff #endif +#ifdef CONFIG_BFIN_SPI_NO_DMA +# define SPI_DMA 0 +#else +# define SPI_DMA 1 +#endif + +static int spi_dma_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx, + uint bytes) +{ + int ret = -1; + u16 ndsize, spi_config, dma_config; + struct dmasg dmasg[2]; + const u8 *buf; + + if (tx) { + debug("%s: doing half duplex TX\n", __func__); + buf = tx; + spi_config = TDBR_DMA; + dma_config = 0; + } else { + debug("%s: doing half duplex RX\n", __func__); + buf = rx; + spi_config = RDBR_DMA; + dma_config = WNR; + } + + dmasg[0].start_addr = (unsigned long)buf; + dmasg[0].x_modify = 1; + dma_config |= WDSIZE_8 | DMAEN; + if (bytes <= 65536) { + blackfin_dcache_flush_invalidate_range(buf, buf + bytes); + ndsize = NDSIZE_5; + dmasg[0].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN; + dmasg[0].x_count = bytes; + } else { + blackfin_dcache_flush_invalidate_range(buf, buf + 65536 - 1); + ndsize = NDSIZE_7; + dmasg[0].cfg = NDSIZE_5 | dma_config | FLOW_ARRAY | DMA2D; + dmasg[0].x_count = 0; /* 2^16 */ + dmasg[0].y_count = bytes >> 16; /* count / 2^16 */ + dmasg[0].y_modify = 1; + dmasg[1].start_addr = (unsigned long)(buf + (bytes & ~0xFFFF)); + dmasg[1].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN; + dmasg[1].x_count = bytes & 0xFFFF; /* count % 2^16 */ + dmasg[1].x_modify = 1; + } + + dma->cfg = 0; + dma->irq_status = DMA_DONE | DMA_ERR; + dma->curr_desc_ptr = dmasg; + write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE)); + write_SPI_STAT(bss, -1); + SSYNC(); + + write_SPI_TDBR(bss, CONFIG_BFIN_SPI_IDLE_VAL); + dma->cfg = ndsize | FLOW_ARRAY | DMAEN; + write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE) | spi_config); + SSYNC(); + + /* + * We already invalidated the first 64k, + * now while we just wait invalidate the remaining part. + * Its not likely that the DMA is going to overtake + */ + if (bytes > 65536) + blackfin_dcache_flush_invalidate_range(buf + 65536, buf + bytes); + + while (!(dma->irq_status & DMA_DONE)) + if (ctrlc()) + goto done; + + dma->cfg = 0; + + ret = 0; + done: + write_SPI_CTL(bss, bss->ctl); + return ret; +} + +static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx, + uint bytes) +{ + /* todo: take advantage of hardware fifos */ + while (bytes--) { + u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL); + debug("%s: tx:%x ", __func__, value); + write_SPI_TDBR(bss, value); + SSYNC(); + while ((read_SPI_STAT(bss) & TXS)) + if (ctrlc()) + return -1; + while (!(read_SPI_STAT(bss) & SPIF)) + if (ctrlc()) + return -1; + while (!(read_SPI_STAT(bss) & RXS)) + if (ctrlc()) + return -1; + value = read_SPI_RDBR(bss); + if (rx) + *rx++ = value; + debug("rx:%x\n", value); + } + + return 0; +} + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -265,32 +387,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); - /* todo: take advantage of hardware fifos and setup RX dma */ - while (bytes--) { - u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL); - debug("%s: tx:%x ", __func__, value); - write_SPI_TDBR(bss, value); - SSYNC(); - while ((read_SPI_STAT(bss) & TXS)) - if (ctrlc()) { - ret = -1; - goto done; - } - while (!(read_SPI_STAT(bss) & SPIF)) - if (ctrlc()) { - ret = -1; - goto done; - } - while (!(read_SPI_STAT(bss) & RXS)) - if (ctrlc()) { - ret = -1; - goto done; - } - value = read_SPI_RDBR(bss); - if (rx) - *rx++ = value; - debug("rx:%x\n", value); - } + /* TX DMA doesn't work quite right */ + if (SPI_DMA && bytes > 6 && (!tx /*|| !rx*/)) + ret = spi_dma_xfer(bss, tx, rx, bytes); + else + ret = spi_pio_xfer(bss, tx, rx, bytes); done: if (flags & SPI_XFER_END) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index db867638f6..c02ffd8036 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -143,8 +143,9 @@ void lcd_ctrl_init(void *lcdbase) /* Set contrast */ value = ATMEL_LCDC_PS_DIV8 | - ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE; + if (!panel_info.vl_cont_pol_low) + value |= ATMEL_LCDC_POL_POSITIVE; lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value); lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); diff --git a/include/commproc.h b/include/commproc.h index 762238ebec..a69a80913e 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -579,34 +579,6 @@ typedef struct scc_enet { /*********************************************************************/ - -/*** CCM and PCU E ***********************************************/ - -/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */ - -#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM) - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_PCU_E, CONFIG_CCM */ - /*** ELPT860 *********************************************************/ #ifdef CONFIG_ELPT860 diff --git a/include/compiler.h b/include/compiler.h index 23f4b834d8..91dbe56994 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -47,7 +47,6 @@ #elif defined(__MACH__) # include <machine/endian.h> typedef unsigned long ulong; -typedef unsigned int uint; #endif typedef uint8_t __u8; diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 4d83786767..555145e189 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -269,6 +269,7 @@ * PCI stuff */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP /* pci plug-and-play */ #define CONFIG_PCI_HOST PCI_HOST_AUTO #undef CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/CCM.h b/include/configs/CCM.h deleted file mode 100644 index 3f4a2c103e..0000000000 --- a/include/configs/CCM.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * configuration options, board specific, for Siemens Card Controller Module - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#undef CCM_80MHz /* define for 80 MHz CPU only */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ -#define CONFIG_CCM 1 /* on a Card Controller Module */ -#define CONFIG_MISC_INIT_R /* Call misc_init_r() */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#undef CONFIG_8xx_CONS_SMC2 -#undef CONFIG_8xx_CONS_NONE - -/* ENVIRONMENT */ - -#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */ -#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ - -#define CONFIG_IPADDR 192.168.0.42 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 0.0.0.0 -#define CONFIG_SERVERIP 192.168.0.254 - -#define CONFIG_HOSTNAME CCM - -#define CONFIG_LOADADDR 40180000 - -#undef CONFIG_BOOTARGS - -#define CONFIG_BOOTCOMMAND "setenv bootargs " \ - "mem=${mem} " \ - "root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ - "wt_8xx=timeout:3600; " \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#define CONFIG_WATCHDOG 1 /* watchdog enabled */ - -#undef CONFIG_STATUS_LED /* Status LED disabled */ - -#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SPI /* enable SPI driver */ -#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ - -/* ---------------------------------------------------------------- - * Offset to initial SPI buffers in DPRAM (used if the environment - * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to - * use at an early stage. It is used between the two initialization - * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it - * far enough from the start of the data area (as well as from the - * stack pointer). - * ---------------------------------------------------------------- */ -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */ - - -#define CONFIG_MAC_PARTITION /* nod used yet */ -#define CONFIG_DOS_PARTITION - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -/* Ethernet hardware configuration done using port pins */ -#define CONFIG_SYS_PA_ETH_RESET 0x0200 /* PA 6 */ -#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ -#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */ -#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */ -#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */ - -/* Ethernet settings: - * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex - */ -#define CONFIG_SYS_ETH_MDDIS_VALUE 0 -#define CONFIG_SYS_ETH_CFG1_VALUE 1 -#define CONFIG_SYS_ETH_CFG2_VALUE 1 -#define CONFIG_SYS_ETH_CFG3_VALUE 1 - -/* PUMA configuration */ -#define CONFIG_SYS_PC_PUMA_PROG 0x0200 /* PC 6 */ -#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */ -#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xF0000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#if 1 -/* Start port with environment in flash; switch to SPI EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_ENV_OFFSET 2048 -#define CONFIG_ENV_SIZE 2048 -#endif - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * we must activate GPL5 in the SIUMCR for CAN - */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_PLPRCR \ - ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) -#else /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) -#endif /* CCM_80MHz */ - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#else /* up to 50 MHz we use a 1:1 clock */ -#define CONFIG_SYS_SCCR (SCCR_TBS | \ - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) -#endif /* CCM_80MHz */ - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ - OR_SCY_5_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2 and OR2 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -/* - * BR3 and OR3 (CAN Controller) - */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) - -/* - * BR4/OR4: PUMA Config - * - * Memory controller will be used in 2 modes: - * - * - "read" mode: - * BR4: 0x10100801 OR4: 0xffff8520 - * - "load" mode (chip select on UPM B): - * BR4: 0x101004c1 OR4: 0xffff8600 - * - * Default initialization is in "read" mode - */ -#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ -#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ -#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK) -#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK) - -#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V) -#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) - -#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) - -#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ -#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ - -/* - * BR5/OR5: PUMA: SMA Bus 8 Bit - * BR5: 0x10200401 OR5: 0xffe0010a - */ -#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ -#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) - -/* - * BR6/OR6: PUMA: SMA Bus 16 Bit - * BR6: 0x10600801 OR6: 0xffe0010a - */ -#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ -#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) - -/* - * BR7/OR7: PUMA: external Flash - * BR7: 0x10a00801 OR7: 0xfe00010a - */ -#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ -#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ -#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) - - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ - -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index 668cfa2ebb..64512637d7 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -467,6 +467,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_PCI /* include pci support */ +#define CONFIG_SYS_EARLY_PCI_INIT #undef CONFIG_PCI_PNP #undef CONFIG_PCI_SCAN_SHOW diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 8ffd4583b5..95c0a9ffc4 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -74,6 +74,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R 1 #define CONFIG_HWCONFIG #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ @@ -505,8 +506,8 @@ extern unsigned long get_clock_freq(void); #else #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 #endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index dcaca2b617..da826fc26f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -134,6 +134,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG #define CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ @@ -177,14 +178,23 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) - /* Video */ -/* #define CONFIG_VIDEO */ -#ifdef CONFIG_VIDEO +#undef CONFIG_FSL_DIU_FB + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +/* + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so + * disable empty flash sector detection, which is I/O-intensive. + */ +#undef CONFIG_SYS_FLASH_EMPTY_INFO #endif /* diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h new file mode 100644 index 0000000000..09691d3737 --- /dev/null +++ b/include/configs/bct-brettl2.h @@ -0,0 +1,155 @@ +/* + * U-boot - Configuration file for BF536 brettl2 board + */ + +#ifndef __CONFIG_BCT_BRETTL2_H__ +#define __CONFIG_BCT_BRETTL2_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 16384000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 24 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 3 +#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + + +/* + * SDRAM Settings + */ +#define CONFIG_EBIU_SDRRC_VAL 0x07f6 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC 1 +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_HOSTNAME brettl2 +#define CONFIG_IPADDR 192.168.233.224 +#define CONFIG_GATEWAYIP 192.168.233.1 +#define CONFIG_SERVERIP 192.168.233.53 +#define CONFIG_ROOTPATH /romfs/brettl2 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ +#endif + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 135 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 + +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#endif + +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + arch/blackfin/cpu/traps.o (.text .text.*); \ + arch/blackfin/cpu/interrupt.o (.text .text.*); \ + arch/blackfin/cpu/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 + + +/* + * Misc Settings + */ +#define CONFIG_BOOTDELAY 1 +#define CONFIG_LOADADDR 0x800000 +#define CONFIG_MISC_INIT_R +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +/* disable unnecessary features */ +#undef CONFIG_BOOTM_RTEMS +#undef CONFIG_BZIP2 +#undef CONFIG_KALLSYMS + +#endif diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 6eec1c91a7..64ca9ed439 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf518-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 82396d0ed2..4c30c25392 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf526-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA @@ -53,7 +52,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) #define CONFIG_SYS_MALLOC_LEN (512 * 1024) @@ -62,7 +61,8 @@ * (can't be used same time as ethernet) */ #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) -#define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC +# define CONFIG_BFIN_NFC_BOOTROM_ECC #endif #ifdef CONFIG_BFIN_NFC #define CONFIG_BFIN_NFC_CTL_VAL 0x0033 diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h index eb3a2b7dc1..14ade1b1e6 100644 --- a/include/configs/bf527-ad7160-eval.h +++ b/include/configs/bf527-ad7160-eval.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf527-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER @@ -130,7 +129,7 @@ #define CONFIG_MMC #define CONFIG_CMD_EXT2 #define CONFIG_SPI_MMC -#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3) +#define CONFIG_SPI_MMC_DEFAULT_CS (MAX_CTRL_CS + GPIO_PH3) /* diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 07e4ce86e1..54fc063f9a 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf527-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h new file mode 100644 index 0000000000..358284619c --- /dev/null +++ b/include/configs/bf527-sdp.h @@ -0,0 +1,121 @@ +/* + * U-boot - Configuration file for BF527 SDP board + */ + +#ifndef __CONFIG_BF527_SDP_H__ +#define __CONFIG_BF527_SDP_H__ + +#include <asm/config-pre.h> + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 24000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 25 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + +#define CONFIG_PLL_LOCKCNT_VAL 0x0200 +#define CONFIG_PLL_CTL_VAL 0x2a00 +#define CONFIG_VR_CTL_VAL 0x7090 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x00FE +#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d + +#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) + +#define CONFIG_SYS_MONITOR_LEN (768 * 1024) +#define CONFIG_SYS_MALLOC_LEN (640 * 1024) + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 259 + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ALL + + +/* + * Env Storage Settings + */ +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x2000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 + + +/* + * Misc Settings + */ +#define CONFIG_MISC_INIT_R +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include <configs/bfin_adi_common.h> + +#endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 95d3afa85c..e1bb594438 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf533-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index f39bfee0a4..03bc811036 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf533-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS @@ -93,10 +92,7 @@ #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_ALL /* diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 86aa1f61e6..0ba29bc0cd 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -24,7 +24,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 39bbb41fb3..730ae279b6 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER @@ -52,7 +51,7 @@ #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index 7e9dd36bce..559428f484 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -24,7 +24,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index fc9784e083..22d31508eb 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS @@ -89,10 +88,7 @@ #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_ALL /* diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 1c14b6bdd3..04ba210171 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf538-0.4 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS @@ -86,10 +85,7 @@ #define CONFIG_ENV_SPI_MAX_HZ 30000000 #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_ATMEL -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_ALL /* diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 60cca0c07a..4412177ff0 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf548-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA @@ -183,6 +182,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_RTC_BFIN #define CONFIG_UART_CONSOLE 1 +#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000 #ifndef __ADSPBF542__ /* Don't waste time transferring a logo over the UART */ diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h index 0c0204fbd7..2b12c3fbe1 100644 --- a/include/configs/bf561-acvilon.h +++ b/include/configs/bf561-acvilon.h @@ -12,7 +12,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf561-0.5 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 4e293b58a8..1557e14f52 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf561-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 91dcaccb4f..608788a66f 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -47,6 +47,7 @@ # endif # if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN) # define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK # endif # ifdef CONFIG_POST # define CONFIG_CMD_DIAG @@ -119,10 +120,12 @@ /* * Env Settings */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) -# define CONFIG_BOOTDELAY -1 -#else -# define CONFIG_BOOTDELAY 5 +#ifndef CONFIG_BOOTDELAY +# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) +# define CONFIG_BOOTDELAY -1 +# else +# define CONFIG_BOOTDELAY 5 +# endif #endif #ifndef CONFIG_BOOTCOMMAND # define CONFIG_BOOTCOMMAND "run ramboot" @@ -169,9 +172,12 @@ # define UBOOT_ENV_UPDATE \ "eeprom write $(loadaddr) 0x0 $(filesize)" # else +# ifndef CONFIG_BFIN_SPI_IMG_SIZE +# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000 +# endif # define UBOOT_ENV_UPDATE \ "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ - "sf erase 0 0x40000;" \ + "sf erase 0 " MK_STR(CONFIG_BFIN_SPI_IMG_SIZE) ";" \ "sf write $(loadaddr) 0 $(filesize)" # endif # elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) @@ -231,20 +237,28 @@ #else # define NETWORK_ENV_SETTINGS #endif +#ifndef BOARD_ENV_SETTINGS +# define BOARD_ENV_SETTINGS +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ NAND_ENV_SETTINGS \ NETWORK_ENV_SETTINGS \ - FLASHBOOT_ENV_SETTINGS + FLASHBOOT_ENV_SETTINGS \ + BOARD_ENV_SETTINGS /* * Network Settings */ #ifdef CONFIG_CMD_NET -# define CONFIG_IPADDR 192.168.0.15 # define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_GATEWAYIP 192.168.0.1 -# define CONFIG_SERVERIP 192.168.0.2 -# define CONFIG_ROOTPATH /romfs +# ifndef CONFIG_IPADDR +# define CONFIG_IPADDR 192.168.0.15 +# define CONFIG_GATEWAYIP 192.168.0.1 +# define CONFIG_SERVERIP 192.168.0.2 +# endif +# ifndef CONFIG_ROOTPATH +# define CONFIG_ROOTPATH /romfs +# endif # ifdef CONFIG_CMD_DHCP # ifndef CONFIG_SYS_AUTOLOAD # define CONFIG_SYS_AUTOLOAD "no" @@ -255,6 +269,18 @@ #endif /* + * SPI Settings + */ +#ifdef CONFIG_SPI_FLASH_ALL +# define CONFIG_SPI_FLASH_ATMEL +# define CONFIG_SPI_FLASH_MACRONIX +# define CONFIG_SPI_FLASH_SPANSION +# define CONFIG_SPI_FLASH_SST +# define CONFIG_SPI_FLASH_STMICRO +# define CONFIG_SPI_FLASH_WINBOND +#endif + +/* * I2C Settings */ #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 85f08ea888..3f5c95917d 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -24,7 +24,6 @@ /* CPU Options * Be sure to set the Silicon Revision Correctly */ -#define CONFIG_BFIN_CPU bf532-0.5 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER /* diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h new file mode 100644 index 0000000000..8b2bdc715d --- /dev/null +++ b/include/configs/blackvme.h @@ -0,0 +1,246 @@ +/* U-boot for BlackVME. (C) Wojtek Skulski 2010. + * The board includes ADSP-BF561 rev. 0.5, + * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG), + * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell), + * SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB), + * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB), + * Spartan6-LX150 (memory-mapped; both PPIs also connected). + * See http://www.skutek.com + */ + +#ifndef __CONFIG_BLACKVME_H__ +#define __CONFIG_BLACKVME_H__ + +#include <asm/config-pre.h> + +/* Debugging: Set these options if you're having problems + * #define CONFIG_DEBUG_EARLY_SERIAL + * #define DEBUG + * #define CONFIG_DEBUG_DUMP + * #define CONFIG_DEBUG_DUMP_SYMS + * CONFIG_PANIC_HANG means that the board will not auto-reboot + */ +#define CONFIG_PANIC_HANG 0 + +/* CPU Options */ +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + +/* + * CLOCK SETTINGS CAVEAT + * You CANNOT just change the clock settings, esp. the SCLK. + * The SDRAM timing, SPI baud, and the serial UART baud + * use SCLK frequency to set their own frequencies. Therefore, + * if you change the SCLK_DIV, you may also have to adjust + * SDRAM refresh and other timings. + * -------------------------------------------------------------- + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * 25 * 8 / 1 = 200 MHz + * 25 * 16 / 1 = 400 MHz + * 25 * 24 / 1 = 600 MHz + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + * 25 * 8 / 2 = 100 MHz + * 25 * 24 / 6 = 100 MHz + * 25 * 24 / 5 = 120 MHz + * 25 * 16 / 3 = 133 MHz + * 25 MHz because the oscillator also feeds the ether chip. + * CONFIG_CLKIN_HZ is 25 MHz written in Hz + * CLKIN_HALF controls the DF bit in PLL_CTL + * 0 = CLKIN 1 = CLKIN / 2 + * PLL_BYPASS controls the BYPASS bit in PLL_CTL + * 0 = do not bypass 1 = bypass PLL + * VCO_MULT = MSEL (multiplier) in PLL_CTL + * Values can range from 0-63 (where 0 means 64) + * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY) + * SCLK_DIV = system clock divider, 1 to 15 + */ +#define CONFIG_CLKIN_HZ 25000000 +#define CONFIG_CLKIN_HALF 0 +#define CONFIG_PLL_BYPASS 0 +#define CONFIG_VCO_MULT 8 +#define CONFIG_CCLK_DIV 1 +#define CONFIG_SCLK_DIV 2 + +/* + * Ether chip in async memory space AMS3, same as BF561-EZ-KIT. + * Used in 32-bit mode. 16-bit mode not supported. + * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 + */ +/* + * Network settings using a dedicated 2nd ether card in PC + * Windows will automatically acquire IP of that card + * Then use the dedicated card IP + 1 for the board + * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network + */ +#define CONFIG_NET_MULTI + +#define CONFIG_DRIVER_AX88180 1 +#define AX88180_BASE 0x2c000000 +#define CONFIG_CMD_MII /* enable probing PHY */ + +#ifdef CONFIG_NET_MULTI /* also used as the network enabler */ +# define CONFIG_HOSTNAME blackvme /* Bfin board */ +# define CONFIG_IPADDR 169.254.144.145 /* Bfin board */ +# define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */ +# define CONFIG_SERVERIP 169.254.144.144 /* tftp server */ +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_ROOTPATH /export/uClinux-dist/romfs /*NFS*/ +# define CFG_AUTOLOAD "no" +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +# define CONFIG_ENV_OVERWRITE 1 /* enable changing MAC at runtime */ +/* Comment out hardcoded MAC to enable MAC storage in EEPROM */ +/* # define CONFIG_ETHADDR ff:ee:dd:cc:bb:aa */ +#endif + +/* + * SDRAM settings & memory map + */ + +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +/* + * SDRAM reference page + * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram + * NOTE: BlackVME populates only SDRAM bank 0 + */ +/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */ +#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */ +#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */ + +/* Async memory global settings. (ASRAM, not SDRAM) + * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1 + * CLKOUT enabled, all async banks enabled, core has priority + * bank 0&1 16 bit (FPGA) + * bank 2&3 32 bit (ether and USB chips) + */ +#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */ + +/* Async mem timing: BF561 HRM page 16-12 and 16-15. + * Default values 0xFFC2 FFC2 are the slowest supported. + * Example settings of CONFIG_EBIU_AMBCTL1_VAL + * 1. EZ-KIT settings: 0xFFC2 7BB0 + * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx + * See the following page: + * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180 + * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz: + * AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz + * One extra clock needed because AX88180 is asynchronous to CPU. + */ + /* bank 1 0 */ +#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2 + /* bank 3 2 */ +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2 + +/* memory layout */ + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (384 << 10) + +/* + * Serial SPI Flash + * For the M25P64 SCK should be kept < 15 MHz + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x40000 + +#define CONFIG_ENV_SPI_MAX_HZ 15000000 +#define CONFIG_SF_DEFAULT_SPEED 15000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +/* + * Interactive command settings + */ + +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE 1 + +#include <config_cmd_default.h> + +#define CONFIG_CMD_BOOTLDR +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CPLBINFO +#define CONFIG_CMD_SF +#define CONFIG_CMD_ELF + +/* + * Default: boot from SPI flash. + * "sfboot" is a composite command defined in extra settings + */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "run sfboot" + +/* + * Console settings + */ +#define CONFIG_BAUDRATE 57600 +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_UART_CONSOLE 0 + +/* + * U-Boot environment variables. Use "printenv" to examine. + * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env + */ +#define CONFIG_BOOTARGS \ + "root=/dev/mtdblock0 rw " \ + "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ + "earlyprintk=serial,uart0," \ + MK_STR(CONFIG_BAUDRATE) " " \ + "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " " + +/* Convenience env variables & commands. + * Reserve kernstart = 0x20000 = 128 kB for U-Boot. + * Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size). + * U-Boot image is saved at flash offset=0. + * Kernel image is saved at flash offset=$kernstart. + * Instructions. Ksave takes about a minute to complete. + * 1. Update U-Boot: run uget; run usave + * 2. Update kernel: run kget; run ksave + * After updating U-Boot also update the kernel per above instructions + * to make the saved environment consistent with the flash. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernstart=0x20000\0" \ + "kernarea=0x500000\0" \ + "uget=tftp u-boot.ldr\0" \ + "kget=tftp uImage\0" \ + "usave=sf probe 2; " \ + "sf erase 0 $(kernstart); " \ + "sf write $(fileaddr) 0 $(filesize)\0" \ + "ksave=sf probe 2; " \ + "saveenv; " \ + "echo Now patiently wait for the prompt...; " \ + "sf erase $(kernstart) $(kernarea); " \ + "sf write $(fileaddr) $(kernstart) $(filesize)\0" \ + "sfboot=sf probe 2; " \ + "sf read $(loadaddr) $(kernstart) $(filesize); " \ + "run addip; bootm\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):eth0:off\0" + +/* + * Soft I2C settings (BF561 does not have hard I2C) + * PF12,13 on SPI connector 0. + */ +#ifdef CONFIG_SOFT_I2C +# define CONFIG_CMD_I2C +# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12 +# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13 +# define CONFIG_SYS_I2C_SPEED 50000 +# define CONFIG_SYS_I2C_SLAVE 0xFE +#endif + +/* + * No Parallel Flash on this board + */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_FLASH + +#endif diff --git a/include/configs/bluestone.h b/include/configs/bluestone.h new file mode 100644 index 0000000000..560c64ff44 --- /dev/null +++ b/include/configs/bluestone.h @@ -0,0 +1,178 @@ +/* + * bluestone.h - configuration for Bluestone (APM821XX) + * + * Copyright (c) 2010, Applied Micro Circuits Corporation + * Author: Tirumala R Marri <tmarri@apm.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_APM821XX 1 /* APM821XX series */ +#define CONFIG_HOSTNAME bluestone + +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" +#define CONFIG_SYS_CLK_FREQ 50000000 + +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* EBC stuff */ +/* later mapped to this addr */ +#define CONFIG_SYS_FLASH_BASE 0xFFF00000 +#define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */ + +/* EBC Boot Space: 0xFF000000 */ +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/ + +#define CONFIG_SYS_SRAM_SIZE (256 << 10) +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Environment + */ +/* + * Define here the location of the environment variables (FLASH). + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 80 +/* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 +/* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 +/* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* SDRAM */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */ + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII +#define CONFIG_HAS_ETH0 +/* PHY address, See schematics */ +#define CONFIG_PHY_ADDR 0x1f +/* reset phy upon startup */ +#define CONFIG_PHY_RESET 1 +/* Include GbE speed/duplex detection */ +#define CONFIG_PHY_GIGE 1 +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +/* + * External Bus Controller (EBC) Setup + **/ +#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_2048PERCLK | \ + EBC_CFG_ATC_HI | \ + EBC_CFG_DTC_HI | \ + EBC_CFG_CTC_HI | \ + EBC_CFG_OEO_PREVIOUS) +/* NOR Flash */ +#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(64) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(1) | \ + EBC_BXAP_OEN_ENCODE(2) | \ + EBC_BXAP_WBN_ENCODE(2) | \ + EBC_BXAP_WBF_ENCODE(2) | \ + EBC_BXAP_TH_ENCODE(7) | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +/* Peripheral Bank Configuration Register - EBC_BxCR */ +#define CONFIG_SYS_EBC_PB0CR \ + (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_8BIT) + + +#endif /* __CONFIG_H */ diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index e0c6d53b2c..84c93099ce 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf527-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index 75152964b6..dbc4a5b100 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf533-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 742df9c019..df3fe48f65 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 9def99f728..e5b0ecfc5e 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index fa62a8e9c1..27b1cc519c 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf548-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index c60401c8fe..8c350bc263 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf561-0.3 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index d223a4d73b..9184eeb56d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -399,6 +399,14 @@ #endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 @@ -607,14 +615,17 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "ubootaddr=" MK_STR(TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p4080ds/ramdisk.uboot\0" \ diff --git a/include/configs/eNET.h b/include/configs/eNET.h index da2a97d26d..fc7c1c6ce9 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -29,8 +29,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_RELOC_FIXUP_WORKS - /* * Stuff still to be dealt with - */ diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 26992e7538..68bf99871e 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -191,7 +191,7 @@ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_SPR) -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #undef CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index f2ab50c759..5aa304d251 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -208,7 +208,7 @@ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_SPR) -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 53b5197112..cd856ac79c 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf561-0.5 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/ip04.h b/include/configs/ip04.h index c024d78c18..528363c6b4 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -20,7 +20,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf532-0.5 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 37eaf8f6be..612a0fe9ff 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -457,7 +457,8 @@ CONFIG_SYS_POST_UART) /* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 72e02f87d5..4a3b1dc11d 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2010 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -18,58 +18,63 @@ * MA 02111-1307 USA */ -/************************************************************************ +/* * lwmon5.h - configuration for lwmon5 board - ***********************************************************************/ + */ #ifndef __CONFIG_H #define __CONFIG_H -/*----------------------------------------------------------------------- +/* + * Liebherr extra version info + */ +#define CONFIG_IDENT_STRING " - v2.0" + +/* * High Level Configuration Options - *----------------------------------------------------------------------*/ + */ #define CONFIG_LWMON5 1 /* Board is lwmon5 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ #define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_BOARD_RESET 1 /* Call board_reset */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ +#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#define CONFIG_BOARD_RESET /* Call board_reset */ -/*----------------------------------------------------------------------- +/* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */ +#define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1) +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */ #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_LIME_BASE_0 0xc0000000 -#define CONFIG_SYS_LIME_BASE_1 0xc1000000 -#define CONFIG_SYS_LIME_BASE_2 0xc2000000 -#define CONFIG_SYS_LIME_BASE_3 0xc3000000 -#define CONFIG_SYS_FPGA_BASE_0 0xc4000000 -#define CONFIG_SYS_FPGA_BASE_1 0xc4200000 +#define CONFIG_SYS_LIME_BASE_0 0xc0000000 +#define CONFIG_SYS_LIME_BASE_1 0xc1000000 +#define CONFIG_SYS_LIME_BASE_2 0xc2000000 +#define CONFIG_SYS_LIME_BASE_3 0xc3000000 +#define CONFIG_SYS_FPGA_BASE_0 0xc4000000 +#define CONFIG_SYS_FPGA_BASE_1 0xc4200000 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000) +#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000) #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 -/*----------------------------------------------------------------------- - * Initial RAM & stack pointer - *----------------------------------------------------------------------*/ /* + * Initial RAM & stack pointer + * * On LWMON5 we use D-cache as init-ram and stack pointer. We also move * the POST_WORD from OCM to a 440EPx register that preserves it's * content during reset (GPT0_COMP6). This way we reserve the OCM (16k) @@ -77,18 +82,18 @@ */ #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_INIT_RAM_END (4 << 10) #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +/* unused GPT0 COMP reg */ #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6) - /* unused GPT0 COMP reg */ -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ - /* 440EPx errata CHIP 11 */ #define CONFIG_SYS_OCM_SIZE (16 << 10) +/* 440EPx errata CHIP 11: don't use last 4kbytes */ +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* Additional registers for watchdog timer post test */ - #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2) #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1) #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR @@ -100,9 +105,9 @@ #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00 -/*----------------------------------------------------------------------- +/* * Serial Port - *----------------------------------------------------------------------*/ + */ #define CONFIG_CONS_INDEX 2 /* Use UART1 */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -110,77 +115,80 @@ #define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_SERIAL_MULTI #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -/*----------------------------------------------------------------------- +/* * Environment - *----------------------------------------------------------------------*/ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + */ +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ -/*----------------------------------------------------------------------- +/* * FLASH related - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH0 0xFC000000 #define CONFIG_SYS_FLASH1 0xF8000000 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ +#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -/*----------------------------------------------------------------------- +/* * DDR SDRAM - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ + */ +#define CONFIG_SYS_MBYTES_SDRAM 256 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ -#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ -#define CONFIG_DDR_ECC 1 /* enable ECC */ -#define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CONFIG_DDR_ECC /* enable ECC */ /* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_ECC_ON | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_OCM | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_SPR | \ - CONFIG_SYS_POST_UART | \ - CONFIG_SYS_POST_SYSMON | \ - CONFIG_SYS_POST_WATCHDOG | \ - CONFIG_SYS_POST_DSP | \ - CONFIG_SYS_POST_BSPEC1 | \ - CONFIG_SYS_POST_BSPEC2 | \ - CONFIG_SYS_POST_BSPEC3 | \ - CONFIG_SYS_POST_BSPEC4 | \ +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_ECC | \ + CONFIG_SYS_POST_ETHER | \ + CONFIG_SYS_POST_FPU | \ + CONFIG_SYS_POST_I2C | \ + CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_OCM | \ + CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_SPR | \ + CONFIG_SYS_POST_UART | \ + CONFIG_SYS_POST_SYSMON | \ + CONFIG_SYS_POST_WATCHDOG | \ + CONFIG_SYS_POST_DSP | \ + CONFIG_SYS_POST_BSPEC1 | \ + CONFIG_SYS_POST_BSPEC2 | \ + CONFIG_SYS_POST_BSPEC3 | \ + CONFIG_SYS_POST_BSPEC4 | \ CONFIG_SYS_POST_BSPEC5) -#define CONFIG_POST_WATCHDOG {\ +/* Define here the base-addresses of the UARTs to test in POST */ +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } + +#define CONFIG_POST_WATCHDOG { \ "Watchdog timer test", \ "watchdog", \ "This test checks the watchdog timer.", \ @@ -188,10 +196,10 @@ &lwmon5_watchdog_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_WATCHDOG \ + CONFIG_SYS_POST_WATCHDOG \ } -#define CONFIG_POST_BSPEC1 {\ +#define CONFIG_POST_BSPEC1 { \ "dsPIC init test", \ "dspic_init", \ "This test returns result of dsPIC READY test run earlier.", \ @@ -199,10 +207,10 @@ &dspic_init_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC1 \ + CONFIG_SYS_POST_BSPEC1 \ } -#define CONFIG_POST_BSPEC2 {\ +#define CONFIG_POST_BSPEC2 { \ "dsPIC test", \ "dspic", \ "This test gets result of dsPIC POST and dsPIC version.", \ @@ -210,32 +218,32 @@ &dspic_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC2 \ + CONFIG_SYS_POST_BSPEC2 \ } -#define CONFIG_POST_BSPEC3 {\ +#define CONFIG_POST_BSPEC3 { \ "FPGA test", \ "fpga", \ "This test checks FPGA registers and memory.", \ - POST_RAM | POST_ALWAYS, \ + POST_RAM | POST_ALWAYS | POST_MANUAL, \ &fpga_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC3 \ + CONFIG_SYS_POST_BSPEC3 \ } -#define CONFIG_POST_BSPEC4 {\ +#define CONFIG_POST_BSPEC4 { \ "GDC test", \ "gdc", \ "This test checks GDC registers and memory.", \ - POST_RAM | POST_ALWAYS, \ + POST_RAM | POST_ALWAYS | POST_MANUAL,\ &gdc_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC4 \ + CONFIG_SYS_POST_BSPEC4 \ } -#define CONFIG_POST_BSPEC5 {\ +#define CONFIG_POST_BSPEC5 { \ "SYSMON1 test", \ "sysmon1", \ "This test checks GPIO_62_EPX pin indicating power failure.", \ @@ -243,7 +251,7 @@ &sysmon1_post_test, \ NULL, \ NULL, \ - CONFIG_SYS_POST_BSPEC5 \ + CONFIG_SYS_POST_BSPEC5 \ } #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ @@ -253,34 +261,53 @@ #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE) #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ -/*----------------------------------------------------------------------- +/* * I2C - *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */ +#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */ +#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */ +#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */ + #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */ /* 64 byte page write mode using*/ /* last 6 bits of the address */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ +#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ +#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ + +#define I2C_ADDR_LIST { \ + CONFIG_SYS_I2C_RTC_ADDR, \ + CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \ + CONFIG_SYS_I2C_EEPROM_MB_ADDR, \ + CONFIG_SYS_I2C_DSPIC_ADDR, \ + CONFIG_SYS_I2C_DSPIC_2_ADDR, \ + CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \ + CONFIG_SYS_I2C_DSPIC_IO_ADDR } -#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ -#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */ -#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */ +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +/* Update size in "reg" property of NOR FLASH device tree nodes */ +#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ -#if 0 -#define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */ -#define CONFIG_AUTOBOOT_PROMPT \ - "\nEnter password - autoboot in %d sec...\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */ -#endif #define CONFIG_PREBOOT "setenv bootdelay 15" @@ -314,15 +341,11 @@ "cp.b 200000 FFF80000 80000\0" \ "upd=run load update\0" \ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ - "source 200000\0" \ + "autoscr 200000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -410,9 +433,9 @@ #define CONFIG_CMD_USB #endif -/*----------------------------------------------------------------------- +/* * Miscellaneous configurable options - *----------------------------------------------------------------------*/ + */ #define CONFIG_SUPPORT_VFAT #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -445,9 +468,9 @@ #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------*/ + */ /* General PCI */ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ @@ -461,29 +484,32 @@ #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#ifndef DEBUG #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ +#endif #define CONFIG_WD_PERIOD 40000 /* in usec */ #define CONFIG_WD_MAX_RATE 66600 /* in ticks */ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the 40x Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ -/*----------------------------------------------------------------------- +/* * External Bus Controller (EBC) Setup - *----------------------------------------------------------------------*/ + */ #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE /* Memory Bank 0 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x03050200 +#define CONFIG_SYS_EBC_PB0AP 0x03000280 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000) /* Memory Bank 1 (Lime) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x01004380 -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000) +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000) /* Memory Bank 2 (FPGA) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x01004400 @@ -495,19 +521,27 @@ #define CONFIG_SYS_EBC_CFG 0xb8400000 -/*----------------------------------------------------------------------- +/* * Graphics (Fujitsu Lime) - *----------------------------------------------------------------------*/ + */ +/* SDRAM Clock frequency adjustment register */ +#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 +#if 1 /* 133MHz is not tested enough, use 100MHz for now */ /* Lime Clock frequency is to set 100MHz */ #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 -#if 0 +#else /* Lime Clock frequency for 133MHz */ #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 #endif -/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars - and pixel flare on display when 133MHz was configured. According to - SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ +/* SDRAM Parameter register */ +#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC +/* + * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars + * and pixel flare on display when 133MHz was configured. According to + * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed + * Grade + */ #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ @@ -516,13 +550,15 @@ #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ #endif -/*----------------------------------------------------------------------- +/* * GPIO Setup - *----------------------------------------------------------------------*/ + */ #define CONFIG_SYS_GPIO_PHY1_RST 12 #define CONFIG_SYS_GPIO_FLASH_WP 14 #define CONFIG_SYS_GPIO_PHY0_RST 22 #define CONFIG_SYS_GPIO_DSPIC_READY 51 +#define CONFIG_SYS_GPIO_CAN_ENABLE 53 +#define CONFIG_SYS_GPIO_LSB_ENABLE 54 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55 #define CONFIG_SYS_GPIO_HIGHSIDE 56 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57 @@ -532,7 +568,7 @@ #define CONFIG_SYS_GPIO_SYSMON_STATUS 62 #define CONFIG_SYS_GPIO_WATCHDOG 63 -/*----------------------------------------------------------------------- +/* * PPC440 GPIO Configuration */ #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 905c719103..80163d49ee 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -264,7 +264,8 @@ CONFIG_SYS_POST_UART) /* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2 } #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index 3e04cfe730..8dd87cb8c5 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -192,7 +192,7 @@ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_SPR) -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #undef CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h deleted file mode 100644 index 3aee206ad7..0000000000 --- a/include/configs/pcu_e.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * (C) Copyright 2001-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Workaround for layout bug on prototype board - */ -#define PCU_E_WITH_SWAPPED_CS 1 - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC860 1 /* This is a MPC860T CPU */ -#define CONFIG_MPC860T 1 -#define CONFIG_PCU_E 1 /* ...on a PCU E board */ - -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ - -#define CONFIG_BAUDRATE 9600 -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#endif - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */ - -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ - -#define CONFIG_SPI /* enable SPI driver */ -#define CONFIG_SPI_X /* 16 bit EEPROM addressing */ - -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - - -/* ---------------------------------------------------------------- - * Offset to initial SPI buffers in DPRAM (used if the environment - * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to - * use at an early stage. It is used between the two initialization - * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it - * far enough from the start of the data area (as well as from the - * stack pointer). - * ---------------------------------------------------------------- */ -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ - -/* Ethernet hardware configuration done using port pins */ -#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ -#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */ -#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */ -#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */ -#else /* XXX */ -#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */ -#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */ -#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */ -#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */ -#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */ -#endif /* XXX */ - -/* Ethernet settings: - * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex - */ -#define CONFIG_SYS_ETH_MDDIS_VALUE 0 -#define CONFIG_SYS_ETH_CFG1_VALUE 1 -#define CONFIG_SYS_ETH_CFG2_VALUE 1 -#define CONFIG_SYS_ETH_CFG3_VALUE 1 - -/* PUMA configuration */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */ -#else /* XXX */ -#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */ -#endif /* XXX */ -#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */ -#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFE000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Address accessed to reset the board - must not be mapped/assigned - */ -#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* this is an ugly hack needed because of the silly non-constant address map */ -#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size) - -#if defined(DEBUG) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#endif -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#if 0 -/* Start port with environment in flash; switch to SPI EEPROM later */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */ -#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */ -#else -/* Final version: environment in EEPROM */ -#define CONFIG_ENV_IS_IN_EEPROM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_OFFSET 1024 -#define CONFIG_ENV_SIZE 1024 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before - * running in RAM. - */ - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * External Arbitration max. priority (7), - * Debug pins configuration '11', - * Asynchronous external master enable. - */ -/* => 0x70600200 */ -#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME) - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit, set PLL multiplication factor ! - */ -/* 0x00004080 */ -#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */ -#define CONFIG_SYS_PLPRCR \ - ( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ - /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ - PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \ - ) - -#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - * - * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz - */ -#define SCCR_MASK SCCR_EBDF11 -/* 0x01800000 */ -#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \ - SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ - SCCR_EBDF00 | SCCR_DFSYNC00 | \ - SCCR_DFBRG00 | SCCR_DFNL000 | \ - SCCR_DFNH000 | SCCR_DFLCD100 | \ - SCCR_DFALCD01) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - * - * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!! - * - * Don't expect the "date" command to work without a 32kHz clock input! - */ -/* 0x00C3 => 0x0003 */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - - -/*----------------------------------------------------------------------- - * RCCR - RISC Controller Configuration Register 19-4 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RCCR 0x0000 - -/*----------------------------------------------------------------------- - * RMDS - RISC Microcode Development Support Control Register - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RMDS 0 - -/*----------------------------------------------------------------------- - * - * Interrupt Levels - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - second Flash bank optional - */ - -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */ -#else /* XXX */ -#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */ -#endif /* XXX */ - -/* - * used to re-map FLASH: restrict access enough but not too much to - * meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ - -/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR) - -#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \ - CONFIG_SYS_OR_TIMING_FLASH) -/* 16 bit, bank valid */ -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#else /* XXX */ -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) -#endif /* XXX */ - -/* - * BR2/OR2: SDRAM - * - * Multiplexed addresses, GPL5 output to GPL5_A (don't care) - */ -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */ -#else /* XXX */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */ -#endif /* XXX */ -#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */ -#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */ - -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* XXX */ -#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#endif /* XXX */ - -/* - * BR3/OR3: CAN Controller - * BR3: 0x10000401 OR3: 0xffff818a - */ -#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */ -#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */ -#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) -#else /* XXX */ -#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING) -#endif /* XXX */ - -/* - * BR4/OR4: PUMA Config - * - * Memory controller will be used in 2 modes: - * - * - "read" mode: - * BR4: 0x10100801 OR4: 0xffff8530 - * - "load" mode (chip select on UPM B): - * BR4: 0x101008c1 OR4: 0xffff8630 - * - * Default initialization is in "read" mode - */ -#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */ -#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */ -#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK) -#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK) - -#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \ - BR_PS_16 | BR_MS_UPMB | BR_V) -#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING) - -#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ -#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ -#else /* XXX */ -#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ -#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ -#endif /* XXX */ - -/* - * BR5/OR5: PUMA: SMA Bus 8 Bit - * BR5: 0x10200401 OR5: 0xffe0010a - */ -#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */ -#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) -#else /* XXX */ -#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA) -#endif /* XXX */ - -/* - * BR6/OR6: PUMA: SMA Bus 16 Bit - * BR6: 0x10600801 OR6: 0xffe0010a - */ -#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */ -#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */ -#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) -#else /* XXX */ -#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA) -#endif /* XXX */ - -/* - * BR7/OR7: PUMA: external Flash - * BR7: 0x10a00801 OR7: 0xfe00010a - */ -#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */ -#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */ -#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR) - -#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA) - -/* - * Memory Periodic Timer Prescaler - */ - -/* periodic timer for refresh */ -#define CONFIG_SYS_MPTPR 0x0200 - -/* - * MAMR settings for SDRAM - * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, - * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X - * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X - */ -/* periodic timer for refresh */ -#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */ - -#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_AMA_TYPE_1 | \ - MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | \ - MAMR_WLFA_1X | \ - MAMR_TLFA_8X ) - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 52055e80dc..042d78915c 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf518-0.0 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 24ce8f854a..dceff308b8 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -11,7 +11,6 @@ /* * Processor Settings */ -#define CONFIG_BFIN_CPU bf537-0.2 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS diff --git a/include/configs/zeus.h b/include/configs/zeus.h index aa250cc2d0..06d4526b07 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -94,7 +94,7 @@ #define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */ /* Define here the base-addresses of the UARTs to test in POST */ -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE} +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 } #define CONFIG_LOGBUFFER #define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */ diff --git a/board/freescale/common/fsl_diu_fb.h b/include/fsl_diu_fb.h index 3a5fc9ff82..87443e10c2 100644 --- a/board/freescale/common/fsl_diu_fb.h +++ b/include/fsl_diu_fb.h @@ -57,3 +57,4 @@ struct fb_info { extern char *fsl_fb_open(struct fb_info **info); int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix); +int platform_diu_init(unsigned int *xres, unsigned int *yres); diff --git a/include/lcd.h b/include/lcd.h index cd9d49d3ae..0e098d925e 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -167,6 +167,7 @@ typedef struct vidinfo { u_long vl_sync; /* Horizontal / vertical sync */ u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ u_long vl_tft; /* 0 = passive, 1 = TFT */ + u_long vl_cont_pol_low; /* contrast polarity is low */ /* Horizontal control register. */ u_long vl_hsync_len; /* Length of horizontal sync */ diff --git a/include/status_led.h b/include/status_led.h index b39ca64577..360195c961 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -190,22 +190,6 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -/***** PCU E and CCM ************************************************/ -#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM)) - -# define STATUS_LED_PAR im_cpm.cp_pbpar -# define STATUS_LED_DIR im_cpm.cp_pbdir -# define STATUS_LED_ODR im_cpm.cp_pbodr -# define STATUS_LED_DAT im_cpm.cp_pbdat - -# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - /***** ICU862 ********************************************************/ #elif defined(CONFIG_ICU862) @@ -270,7 +254,7 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ /***** KUP4K, KUP4X ****************************************************/ -#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM) +#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) # define STATUS_LED_PAR im_ioport.iop_papar # define STATUS_LED_DIR im_ioport.iop_padir diff --git a/lib/hashtable.c b/lib/hashtable.c index b747f1f799..57802cfb6d 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -45,6 +45,9 @@ # include <linux/string.h> #endif +#ifndef CONFIG_ENV_MIN_ENTRIES /* minimum number of entries */ +#define CONFIG_ENV_MIN_ENTRIES 64 +#endif #ifndef CONFIG_ENV_MAX_ENTRIES /* maximum number of entries */ #define CONFIG_ENV_MAX_ENTRIES 512 #endif @@ -647,13 +650,14 @@ int himport_r(struct hsearch_data *htab, * (CONFIG_ENV_SIZE). This heuristics will result in * unreasonably large numbers (and thus memory footprint) for * big flash environments (>8,000 entries for 64 KB - * envrionment size), so we clip it to a reasonable value - * (which can be overwritten in the board config file if - * needed). + * envrionment size), so we clip it to a reasonable value. + * On the other hand we need to add some more entries for free + * space when importing very small buffers. Both boundaries can + * be overwritten in the board config file if needed. */ if (!htab->table) { - int nent = size / 8; + int nent = CONFIG_ENV_MIN_ENTRIES + size / 8; if (nent > CONFIG_ENV_MAX_ENTRIES) nent = CONFIG_ENV_MAX_ENTRIES; diff --git a/post/board/lwmon5/dsp.c b/post/board/lwmon5/dsp.c index 0e6d9084a3..913cd97591 100644 --- a/post/board/lwmon5/dsp.c +++ b/post/board/lwmon5/dsp.c @@ -33,20 +33,37 @@ DECLARE_GLOBAL_DATA_PTR; -#define DSP_STATUS_REG 0xC4000008 +#define DSP_STATUS_REG 0xC4000008 +#define FPGA_STATUS_REG 0xC400000C int dsp_post_test(int flags) { + uint old_value; uint read_value; int ret; + /* momorize fpga status */ + old_value = in_be32((void *)FPGA_STATUS_REG); + /* enable outputs */ + out_be32((void *)FPGA_STATUS_REG, 0x30); + + /* generate sync signal */ + out_be32((void *)DSP_STATUS_REG, 0x300); + udelay(5); + out_be32((void *)DSP_STATUS_REG, 0); + udelay(500); + + /* read status */ ret = 0; read_value = in_be32((void *)DSP_STATUS_REG) & 0x3; - if (read_value != 0x3) { + if (read_value != 0x03) { post_log("\nDSP status read %08X\n", read_value); ret = 1; } + /* restore fpga status */ + out_be32((void *)FPGA_STATUS_REG, old_value); + return ret; } diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c index ff2ed0566f..861673952d 100644 --- a/post/board/lwmon5/dspic.c +++ b/post/board/lwmon5/dspic.c @@ -38,14 +38,16 @@ DECLARE_GLOBAL_DATA_PTR; #define DSPIC_POST_ERROR_REG 0x800 #define DSPIC_SYS_ERROR_REG 0x802 -#define DSPIC_VERSION_REG 0x804 +#define DSPIC_SYS_VERSION_REG 0x804 +#define DSPIC_FW_VERSION_REG 0x808 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 /* Verify that dsPIC ready test done early at hw init passed ok */ int dspic_init_post_test(int flags) { - if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & CONFIG_SYS_DSPIC_TEST_MASK) { + if (in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) & + CONFIG_SYS_DSPIC_TEST_MASK) { post_log("dsPIC init test failed\n"); return 1; } @@ -57,46 +59,60 @@ int dspic_init_post_test(int flags) #if CONFIG_POST & CONFIG_SYS_POST_BSPEC2 /* Read a register from the dsPIC. */ -int dspic_read(ushort reg) +int dspic_read(ushort reg, ushort *data) { - uchar buf[2]; + uchar buf[sizeof(*data)]; + int rval; if (i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, 2, buf, 2)) return -1; + rval = i2c_read(CONFIG_SYS_I2C_DSPIC_IO_ADDR, reg, sizeof(reg), + buf, sizeof(*data)); + *data = (buf[0] << 8) | buf[1]; - return (uint)((buf[0] << 8) | buf[1]); + return rval; } /* Verify error codes regs, display version */ int dspic_post_test(int flags) { - int data; + ushort data; int ret = 0; post_log("\n"); - data = dspic_read(DSPIC_VERSION_REG); - if (data == -1) { - post_log("dsPIC : failed read version\n"); + + /* read dspic FW-Version */ + if (dspic_read(DSPIC_FW_VERSION_REG, &data)) { + post_log("dsPIC: failed read FW-Version\n"); + ret = 1; + } else { + post_log("dsPIC FW-Version: %u.%u\n", + (data >> 8) & 0xFF, data & 0xFF); + } + + /* read dspic SYS-Version */ + if (dspic_read(DSPIC_SYS_VERSION_REG, &data)) { + post_log("dsPIC: failed read version\n"); ret = 1; } else { - post_log("dsPIC version: %u.%u\n", - (data >> 8) & 0xFF, data & 0xFF); + post_log("dsPIC SYS-Version: %u.%u\n", + (data >> 8) & 0xFF, data & 0xFF); } - data = dspic_read(DSPIC_POST_ERROR_REG); - if (data != 0) ret = 1; - if (data == -1) { - post_log("dsPIC : failed read POST code\n"); + /* read dspic POST error code */ + if (dspic_read(DSPIC_POST_ERROR_REG, &data)) { + post_log("dsPIC: failed read POST code\n"); + ret = 1; } else { - post_log("dsPIC POST code 0x%04X\n", data); + post_log("dsPIC POST-ERROR code: 0x%04X\n", data); } - data = dspic_read(DSPIC_SYS_ERROR_REG); - if (data == -1) { - post_log("dsPIC : failed read system error\n"); + /* read dspic SYS error code */ + if ((data = dspic_read(DSPIC_SYS_ERROR_REG, &data))) { + post_log("dsPIC: failed read system error\n"); ret = 1; } else { - post_log("dsPIC SYS-ERROR code: 0x%04X\n", data); + post_log("dsPIC SYS-ERROR code: 0x%04X\n", data); } return ret; diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c index 2b842908db..3067548483 100644 --- a/post/board/lwmon5/fpga.c +++ b/post/board/lwmon5/fpga.c @@ -28,7 +28,7 @@ */ #include <post.h> - +#include <watchdog.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -38,18 +38,28 @@ DECLARE_GLOBAL_DATA_PTR; #define FPGA_RAM_START 0xC4200000 #define FPGA_RAM_END 0xC4203FFF #define FPGA_STAT 0xC400000C +#define FPGA_BUFFER 0x00800000 +#define FPGA_RAM_SIZE (FPGA_RAM_END - FPGA_RAM_START + 1) #if CONFIG_POST & CONFIG_SYS_POST_BSPEC3 -/* Testpattern for fpga memorytest */ -static uint pattern[] = { +const static unsigned long pattern[] = { + 0xffffffff, + 0xaaaaaaaa, + 0xcccccccc, + 0xf0f0f0f0, + 0xff00ff00, + 0xffff0000, + 0x0000ffff, + 0x00ff00ff, + 0x0f0f0f0f, + 0x33333333, 0x55555555, - 0xAAAAAAAA, - 0xAA5555AA, - 0x55AAAA55, - 0x0 + 0x00000000, }; +const static unsigned long otherpattern = 0x01234567; + static int one_scratch_test(uint value) { uint read_value; @@ -62,51 +72,226 @@ static int one_scratch_test(uint value) read_value = in_be32((void *)FPGA_SCRATCH_REG); if (read_value != value) { post_log("FPGA SCRATCH test failed write %08X, read %08X\n", - value, read_value); - ret = 1; + value, read_value); + ret = -1; + } + + return ret; +} + +static int fpga_post_test1(ulong *start, ulong size, ulong val) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = val; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != val) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, val, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + return ret; +} + +static int fpga_post_test2(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = 1 << (i % 32); + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != 1 << (i % 32)) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, 1 << (i % 32), readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +static int fpga_post_test3(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != i) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +static int fpga_post_test4(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = ~i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != ~i) { + post_log("FPGA Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, ~i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); } return ret; } /* FPGA Memory-pattern-test */ -static int fpga_mem_test(void * address) +static int fpga_mem_test(void) { - int ret = 1; - uint read_value; - uint old_value; - uint i = 0; - /* save content */ - old_value = in_be32(address); - - while (pattern[i] != 0) { - out_be32(address, pattern[i]); - /* read other location (protect against data lines capacity) */ - ret = in_be16((void *)FPGA_VERSION_REG); - /* verify test pattern */ - read_value = in_be32(address); - - if (read_value != pattern[i]) { - post_log("FPGA Memory test failed."); - post_log(" write %08X, read %08X at address %08X\n", - pattern[i], read_value, address); + int ret = 0; + ulong* start = (ulong *)FPGA_RAM_START; + ulong size = FPGA_RAM_SIZE; + + if (ret == 0) + ret = fpga_post_test1(start, size, 0x00000000); + + if (ret == 0) + ret = fpga_post_test1(start, size, 0xffffffff); + + if (ret == 0) + ret = fpga_post_test1(start, size, 0x55555555); + + if (ret == 0) + ret = fpga_post_test1(start, size, 0xaaaaaaaa); + + WATCHDOG_RESET(); + + if (ret == 0) + ret = fpga_post_test2(start, size); + + if (ret == 0) + ret = fpga_post_test3(start, size); + + if (ret == 0) + ret = fpga_post_test4(start, size); + + return ret; +} + + + +/* Verify FPGA addresslines */ +static int fpga_post_addrline(ulong *address, ulong *base, ulong size) +{ + unsigned long *target; + unsigned long *end; + unsigned long readback; + unsigned long xor; + int ret = 0; + + end = (ulong *)((ulong)base + size); + xor = 0; + + for (xor = sizeof(ulong); xor > 0; xor <<= 1) { + target = (ulong*)((ulong)address ^ xor); + if ((target >= base) && (target < end)) { + *address = ~*target; + readback = *target; + + if (readback == *address) { + post_log("Memory (address line) error at %08x" + "XOR value %08x !\n", + address, target, xor); + ret = -1; + break; + } + } + } + + return ret; +} + +/* Verify FPGA addresslines */ +static int fpga_post_dataline(ulong *address) +{ + unsigned long temp32 = 0; + int i = 0; + int ret = 0; + + for (i = 0; i < ARRAY_SIZE(pattern); i++) { + *address = pattern[i]; + /* + * Put a different pattern on the data lines: otherwise they + * may float long enough to read back what we wrote. + */ + *(address + 1) = otherpattern; + temp32 = *address; + + if (temp32 != pattern[i]){ + post_log("Memory (date line) error at %08x, " + "wrote %08x, read %08x !\n", + address, pattern[i], temp32); ret = 1; - goto out; } - i++; } - ret = 0; -out: - out_be32(address, old_value); return ret; } + /* Verify FPGA, get version & memory size */ int fpga_post_test(int flags) { - uint address; uint old_value; - ushort version; + uint version; uint read_value; int ret = 0; @@ -120,24 +305,57 @@ int fpga_post_test(int flags) out_be32((void *)FPGA_SCRATCH_REG, old_value); - version = in_be16((void *)FPGA_VERSION_REG); - post_log("FPGA : version %u.%u\n", - (version >> 8) & 0xFF, version & 0xFF); + version = in_be32((void *)FPGA_VERSION_REG); + post_log("FPGA version %u.%u\n", + (version >> 8) & 0xFF, version & 0xFF); /* Enable write to FPGA RAM */ out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000); - read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000); - post_log("FPGA RAM size: %d bytes\n", read_value); + /* get RAM size */ + read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, FPGA_RAM_SIZE); + post_log("FPGA RAM size %d bytes\n", read_value); + WATCHDOG_RESET(); - for (address = 0; address < 0x1000; address++) { - if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) { - ret = 1; - goto out; - } + /* copy fpga memory to DDR2 RAM*/ + memcpy((void *)FPGA_BUFFER,(void *)FPGA_RAM_START, FPGA_RAM_SIZE); + WATCHDOG_RESET(); + + /* Test datalines */ + if (fpga_post_dataline((ulong *)FPGA_RAM_START)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* Test addresslines */ + if (fpga_post_addrline((ulong *)FPGA_RAM_START, + (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) { + ret = 1; + goto out; } + WATCHDOG_RESET(); + if (fpga_post_addrline((ulong *)FPGA_RAM_END - sizeof(long), + (ulong *)FPGA_RAM_START, FPGA_RAM_SIZE)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* Memory Pattern Test */ + if (fpga_mem_test()) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* restore memory */ + memcpy((void *)FPGA_RAM_START,(void *)FPGA_BUFFER, FPGA_RAM_SIZE); + WATCHDOG_RESET(); out: + /* Disable write to RAM */ + out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) & 0xEFFF); return ret; } diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c index eb16e36fcb..719194b5d9 100644 --- a/post/board/lwmon5/gdc.c +++ b/post/board/lwmon5/gdc.c @@ -28,18 +28,39 @@ */ #include <post.h> - +#include <watchdog.h> #include <asm/io.h> +#include <video.h> DECLARE_GLOBAL_DATA_PTR; -#define GDC_SCRATCH_REG 0xC1FF8044 -#define GDC_VERSION_REG 0xC1FF8084 -#define GDC_RAM_START 0xC0000000 -#define GDC_RAM_END 0xC2000000 +#define GDC_SCRATCH_REG 0xC1FF8044 +#define GDC_VERSION_REG 0xC1FF8084 +#define GDC_HOST_BASE 0xC1FC0000 +#define GDC_RAM_START 0xC0000000 +#define GDC_RAM_END (GDC_HOST_BASE - 1) +#define GDC_RAM_SIZE (GDC_RAM_END - GDC_RAM_START) #if CONFIG_POST & CONFIG_SYS_POST_BSPEC4 +const static unsigned long pattern[] = { + 0xffffffff, + 0xaaaaaaaa, + 0xcccccccc, + 0xf0f0f0f0, + 0xff00ff00, + 0xffff0000, + 0x0000ffff, + 0x00ff00ff, + 0x0f0f0f0f, + 0x33333333, + 0x55555555, + 0x00000000 +}; + +const static unsigned long otherpattern = 0x01234567; + +/* test write/read og a given LIME Register */ static int gdc_test_reg_one(uint value) { int ret; @@ -53,17 +74,229 @@ static int gdc_test_reg_one(uint value) read_value = in_be32((void *)GDC_SCRATCH_REG); if (read_value != value) { post_log("GDC SCRATCH test failed write %08X, read %08X\n", - value, read_value); + value, read_value); } return (read_value != value); } -/* Verify GDC, get memory size */ +/* test with a given static 32 bit pattern in a given memory addressrange */ +static int gdc_post_test1(ulong *start, ulong size, ulong val) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = val; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != val) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, val, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* test with dynamic 32 bit pattern in a given memory addressrange */ +static int gdc_post_test2(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = 1 << (i % 32); + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != 1 << (i % 32)) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, 1 << (i % 32), readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* test with dynamic 32 bit pattern in a given memory addressrange */ +static int gdc_post_test3(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != i) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* test with dynamic 32 bit pattern in a given memory addressrange */ +static int gdc_post_test4(ulong *start, ulong size) +{ + int ret = 0; + ulong i = 0; + ulong *mem = start; + ulong readback; + + for (i = 0; i < size / sizeof(ulong); i++) { + mem[i] = ~i; + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + for (i = 0; i < size / sizeof(ulong); i++) { + readback = mem[i]; + if (readback != ~i) { + post_log("GDC Memory error at %08x, " + "wrote %08x, read %08x !\n", + mem + i, ~i, readback); + ret = -1; + break; + } + if (i % 1024 == 0) + WATCHDOG_RESET(); + } + + return ret; +} + +/* do some patterntests in a given addressrange */ +int gdc_mem_test(ulong *start, ulong size) +{ + int ret = 0; + + /* + * check addressrange and do different static and dynamic + * pattern tests with it. + */ + if (((void *)start) + size <= (void *)GDC_RAM_END) { + if (ret == 0) + ret = gdc_post_test1(start, size, 0x00000000); + + if (ret == 0) + ret = gdc_post_test1(start, size, 0xffffffff); + + if (ret == 0) + ret = gdc_post_test1(start, size, 0x55555555); + + if (ret == 0) + ret = gdc_post_test1(start, size, 0xaaaaaaaa); + + if (ret == 0) + ret = gdc_post_test2(start, size); + + if (ret == 0) + ret = gdc_post_test3(start, size); + + if (ret == 0) + ret = gdc_post_test4(start, size); + } + + return ret; +} + +/* test function of gdc memory addresslines*/ +static int gdc_post_addrline(ulong *address, ulong *base, ulong size) +{ + ulong *target; + ulong *end; + ulong readback = 0; + ulong xor = 0; + int ret = 0; + + end = (ulong *)((ulong)base + size); + + for (xor = sizeof(long); xor > 0; xor <<= 1) { + target = (ulong *)((ulong)address ^ xor); + if ((target >= base) && (target < end)) { + *address = ~*target; + readback = *target; + } + + if (readback == *address) { + post_log("GDC Memory (address line) error at %08x" + "XOR value %08x !\n", + address, target , xor); + ret = -1; + break; + } + } + + return ret; +} + +static int gdc_post_dataline(ulong *address) +{ + unsigned long temp32 = 0; + int i = 0; + int ret = 0; + + for (i = 0; i < ARRAY_SIZE(pattern); i++) { + *address = pattern[i]; + /* + * Put a different pattern on the data lines: otherwise they + * may float long enough to read back what we wrote. + */ + *(address + 1) = otherpattern; + temp32 = *address; + + if (temp32 != pattern[i]){ + post_log("GDC Memory (date line) error at %08x, " + "wrote %08x, read %08x !\n", + address, pattern[i], temp32); + ret = 1; + } + } + + return ret; +} + +/* Verify GDC, get memory size, verify GDC memory */ int gdc_post_test(int flags) { - uint old_value; - int ret = 0; + uint old_value; + int i = 0; + int ret = 0; post_log("\n"); old_value = in_be32((void *)GDC_SCRATCH_REG); @@ -84,13 +317,64 @@ int gdc_post_test(int flags) old_value = in_be32((void *)GDC_VERSION_REG); post_log("GDC chip version %u.%u, year %04X\n", - (old_value >> 8) & 0xFF, old_value & 0xFF, - (old_value >> 16) & 0xFFFF); + (old_value >> 8) & 0xFF, old_value & 0xFF, + (old_value >> 16) & 0xFFFF); old_value = get_ram_size((void *)GDC_RAM_START, - GDC_RAM_END - GDC_RAM_START); + 0x02000000); + + debug("GDC RAM size (ist): %d bytes\n", old_value); + debug("GDC RAM size (soll): %d bytes\n", GDC_RAM_SIZE); post_log("GDC RAM size: %d bytes\n", old_value); + /* Test SDRAM datalines */ + if (gdc_post_dataline((ulong *)GDC_RAM_START)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* Test SDRAM adresslines */ + if (gdc_post_addrline((ulong *)GDC_RAM_START, + (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + if (gdc_post_addrline((ulong *)GDC_RAM_END - sizeof(long), + (ulong *)GDC_RAM_START, GDC_RAM_SIZE)) { + ret = 1; + goto out; + } + WATCHDOG_RESET(); + + /* memory pattern test */ + debug("GDC Memory test (flags %8x:%8x)\n", flags, + POST_SLOWTEST | POST_MANUAL); + + if (flags & POST_MANUAL) { + debug("Full memory test\n"); + if (gdc_mem_test((ulong *)GDC_RAM_START, GDC_RAM_SIZE)) { + ret = 1; + goto out; + } + /* load splashscreen again */ + } else { + debug("smart memory test\n"); + for (i = 0; i < (GDC_RAM_SIZE >> 20) && ret == 0; i++) { + if (ret == 0) + ret = gdc_mem_test((ulong *)(GDC_RAM_START + + (i << 20)), + 0x800); + if (ret == 0) + ret = gdc_mem_test((ulong *)(GDC_RAM_START + + (i << 20) + 0xff800), + 0x800); + } + } + WATCHDOG_RESET(); + +out: return ret; } #endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */ diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c index 9c49d0e646..4a7824065d 100644 --- a/post/board/lwmon5/sysmon.c +++ b/post/board/lwmon5/sysmon.c @@ -56,7 +56,7 @@ DECLARE_GLOBAL_DATA_PTR; /* from dspic.c */ -extern int dspic_read(ushort reg); +extern int dspic_read(ushort reg, ushort *data); #define REG_TEMPERATURE 0x12BC #define REG_VOLTAGE_5V 0x12CA @@ -76,31 +76,38 @@ extern int dspic_read(ushort reg); typedef struct sysmon_s sysmon_t; typedef struct sysmon_table_s sysmon_table_t; -static void sysmon_dspic_init (sysmon_t * this); -static int sysmon_dspic_read (sysmon_t * this, uint addr); -static void sysmon_backlight_disable (sysmon_table_t * this); +static void sysmon_dspic_init(sysmon_t *this); +static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val); +static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val); +static void sysmon_backlight_disable(sysmon_table_t *this); -struct sysmon_s -{ +struct sysmon_s { uchar chip; void (*init)(sysmon_t *); - int (*read)(sysmon_t *, uint); + int (*read)(sysmon_t *, uint, int *); }; -static sysmon_t sysmon_dspic = - {CONFIG_SYS_I2C_DSPIC_IO_ADDR, sysmon_dspic_init, sysmon_dspic_read}; +static sysmon_t sysmon_dspic = { + CONFIG_SYS_I2C_DSPIC_IO_ADDR, + sysmon_dspic_init, + sysmon_dspic_read +}; -static sysmon_t * sysmon_list[] = -{ +static sysmon_t sysmon_dspic_sgn = { + CONFIG_SYS_I2C_DSPIC_IO_ADDR, + sysmon_dspic_init, + sysmon_dspic_read_sgn +}; + +static sysmon_t *sysmon_list[] = { &sysmon_dspic, NULL }; -struct sysmon_table_s -{ - char * name; - char * unit_name; - sysmon_t * sysmon; +struct sysmon_table_s { + char *name; + char *unit_name; + sysmon_t *sysmon; void (*exec_before)(sysmon_table_t *); void (*exec_after)(sysmon_table_t *); @@ -118,37 +125,43 @@ struct sysmon_table_s uint addr; }; -static sysmon_table_t sysmon_table[] = -{ +static sysmon_table_t sysmon_table[] = { { - "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable, - 1, 1, -32768, 32767, 0xFFFF, - 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0, - 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0, - REG_TEMPERATURE, + "Temperature", " C", &sysmon_dspic, NULL, sysmon_backlight_disable, + 1, 1, -32768, 32767, 0xFFFF, + 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0, + 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0, + REG_TEMPERATURE, }, { - "+ 5 V", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, - 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, - 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, - REG_VOLTAGE_5V, + "+ 5 V", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, -0x8000, 0x7FFF, 0xFFFF, + 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, + 0x8000 + VOLTAGE_5V_MIN, 0x8000 + VOLTAGE_5V_MAX, 0, + REG_VOLTAGE_5V, }, { - "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, - 100, 1000, -0x8000, 0x7FFF, 0xFFFF, - 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, - 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, - REG_VOLTAGE_5V_STANDBY, + "+ 5 V standby", "V", &sysmon_dspic, NULL, NULL, + 100, 1000, -0x8000, 0x7FFF, 0xFFFF, + 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, + 0x8000 + VOLTAGE_5V_STANDBY_MIN, 0x8000 + VOLTAGE_5V_STANDBY_MAX, 0, + REG_VOLTAGE_5V_STANDBY, + }, + + { + "Temperature", "°C", &sysmon_dspic_sgn, NULL, sysmon_backlight_disable, + 1, 1, -32768, 32767, 0xFFFF, + 0x8000 + TEMPERATURE_MIN, 0x8000 + TEMPERATURE_MAX, 0, + 0x8000 + TEMPERATURE_DISPLAY_MIN, 0x8000 + TEMPERATURE_DISPLAY_MAX, 0, + REG_TEMPERATURE, }, }; -static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); -int sysmon_init_f (void) +int sysmon_init_f(void) { - sysmon_t ** l; + sysmon_t **l; for (l = sysmon_list; *l; l++) (*l)->init(*l); @@ -156,12 +169,12 @@ int sysmon_init_f (void) return 0; } -void sysmon_reloc (void) +void sysmon_reloc(void) { /* Do nothing for now, sysmon_reloc() is required by the sysmon post */ } -static char *sysmon_unit_value (sysmon_table_t *s, uint val) +static char *sysmon_unit_value(sysmon_table_t *s, uint val) { static char buf[32]; char *p, sign; @@ -176,14 +189,13 @@ static char *sysmon_unit_value (sysmon_table_t *s, uint val) if (unit_val < 0) { sign = '-'; unit_val = -unit_val; - } else + } else { sign = '+'; + } p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div); - frac = unit_val % s->unit_div; - frac /= (s->unit_div / s->unit_precision); decimal = s->unit_precision; @@ -197,58 +209,84 @@ static char *sysmon_unit_value (sysmon_table_t *s, uint val) return buf; } -static void sysmon_dspic_init (sysmon_t * this) +static void sysmon_dspic_init(sysmon_t *this) { } -static int sysmon_dspic_read (sysmon_t * this, uint addr) +static int sysmon_dspic_read(sysmon_t *this, uint addr, int *val) { - int res = dspic_read(addr); + ushort data; + + if (dspic_read(addr, &data) == 0){ + /* To fit into the table range we should add 0x8000 */ + *val = data + 0x8000; + return 0; + } - /* To fit into the table range we should add 0x8000 */ - return (res == -1) ? -1 : (res + 0x8000); + return -1; } -static void sysmon_backlight_disable (sysmon_table_t * this) +static int sysmon_dspic_read_sgn(sysmon_t *this, uint addr, int *val) +{ + ushort data; + + if (dspic_read(addr, &data) == 0){ + /* To fit into the table range we should add 0x8000 */ + *val = (signed short)data + 0x8000; + return 0; + } + + return -1; +} + +static void sysmon_backlight_disable(sysmon_table_t *this) { #if defined(CONFIG_VIDEO) board_backlight_switch(this->val_valid_alt); #endif } -int sysmon_post_test (int flags) +int sysmon_post_test(int flags) { int res = 0; sysmon_table_t * t; int val; - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { + for (t = sysmon_table; t < sysmon_table + ARRAY_SIZE(sysmon_table); t++) { + t->val_valid = 1; if (t->exec_before) t->exec_before(t); - val = t->sysmon->read(t->sysmon, t->addr); - if (val != -1) { - t->val_valid = val >= t->val_min && val <= t->val_max; - t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; - } else { + if (t->sysmon->read(t->sysmon, t->addr, &val) != 0) { t->val_valid = 0; t->val_valid_alt = 0; + post_log(": read failed\n"); + res = 1; + break; + } + + if (t->val_valid != 0) { + t->val_valid = val >= t->val_min && val <= t->val_max; + t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; } if (t->exec_after) t->exec_after(t); - if ((!t->val_valid) || (flags & POST_MANUAL)) { - printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); - printf("allowed range"); - printf(" %-8s ..", sysmon_unit_value(t, t->val_min)); - printf(" %-8s", sysmon_unit_value(t, t->val_max)); - printf(" %s\n", t->val_valid ? "OK" : "FAIL"); + if ((!t->val_valid) || (flags)) { + post_log("\n\t%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); + post_log("allowed range"); + post_log(" %-8s ..", sysmon_unit_value(t, t->val_min)); + post_log(" %-8s", sysmon_unit_value(t, t->val_max)); + post_log(" %s", t->val_valid ? "OK" : "FAIL"); } - if (!t->val_valid) + if (!t->val_valid) { res = 1; + break; + } } + post_log("\n"); return res; } diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c index f181506fe4..4e5ed0dda2 100644 --- a/post/board/lwmon5/watchdog.c +++ b/post/board/lwmon5/watchdog.c @@ -57,8 +57,11 @@ int sysmon1_post_test(int flags) * 3.1. GPIO62 is low * Assuming system voltage failure. */ - post_log("Abnormal voltage detected (GPIO62)\n"); + post_log("sysmon1 Abnormal voltage detected (GPIO62)\n"); + post_log("POST sysmon1 FAILED\n"); return 1; + } else { + post_log("sysmon1 PASSED\n"); } return 0; @@ -117,10 +120,16 @@ int lwmon5_watchdog_post_test(int flags) ulong time; /* 3.3.1. So, the test succeed, save measured time to syslog. */ time = in_be32((void *)CONFIG_SYS_WATCHDOG_TIME_ADDR); - post_log("hw watchdog time : %u ms, passed ", time); - /* 3.3.2. Set scratch register 1 to 0x0000xxxx */ - watchdog_magic_write(0); - return 0; + if (time > 90 ) { /* ms*/ + post_log("hw watchdog time : %u ms, passed ", time); + /* 3.3.2. Set scratch register 1 to 0x0000xxxx */ + watchdog_magic_write(0); + return 0; + } else { + /*test minimum watchdogtime */ + post_log("hw watchdog time : %u ms, failed ", time); + return 2; + } } return -1; } diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 6b61cc191e..d76895696b 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -26,9 +26,10 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ns16550.h> #include <asm/io.h> +#include <serial.h> /* * UART test @@ -46,299 +47,40 @@ * be overridden in the board config file */ #ifndef CONFIG_SYS_POST_UART_TABLE -#define CONFIG_SYS_POST_UART_TABLE {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE} -#endif - -#include <asm/processor.h> -#include <serial.h> - -#if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define UART0_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000300 -#define UART1_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 -#define UART2_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000500 -#define UART3_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000600 -#else -#define UART0_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000200 -#define UART1_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000300 -#endif - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_BASE CONFIG_SYS_PERIPHERAL_BASE + 0x00000600 -#endif - -#if defined(CONFIG_440GP) -#define CR0_MASK 0x3fff0000 -#define CR0_EXTCLK_ENA 0x00600000 -#define CR0_UDIV_POS 16 -#define UDIV_SUBTRACT 1 -#define UART0_SDR CPC0_CR0 -#define MFREG(a, d) d = mfdcr(a) -#define MTREG(a, d) mtdcr(a, d) -#else /* #if defined(CONFIG_440GP) */ -/* all other 440 PPC's access clock divider via sdr register */ -#define CR0_MASK 0xdfffffff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#define UDIV_SUBTRACT 0 -#define UART0_SDR SDR0_UART0 -#define UART1_SDR SDR0_UART1 -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_SDR SDR0_UART2 -#endif -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRX) -#define UART3_SDR SDR0_UART3 -#endif -#define MFREG(a, d) mfsdr(a, d) -#define MTREG(a, d) mtsdr(a, d) -#endif /* #if defined(CONFIG_440GP) */ -#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define UCR0_MASK 0x0000007f -#define UCR1_MASK 0x00007f00 -#define UCR0_UDIV_POS 0 -#define UCR1_UDIV_POS 8 -#define UDIV_MAX 127 -#elif defined(CONFIG_405EX) -#define UART0_BASE 0xef600200 -#define UART1_BASE 0xef600300 -#define CR0_MASK 0x000000ff -#define CR0_EXTCLK_ENA 0x00800000 -#define CR0_UDIV_POS 0 -#define UDIV_SUBTRACT 0 -#define UART0_SDR SDR0_UART0 -#define UART1_SDR SDR0_UART1 -#define MFREG(a, d) mfsdr(a, d) -#define MTREG(a, d) mtsdr(a, d) -#else /* CONFIG_405GP || CONFIG_405CR */ -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 -#define CR0_MASK 0x00001fff -#define CR0_EXTCLK_ENA 0x000000c0 -#define CR0_UDIV_POS 1 -#define UDIV_MAX 32 +#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ + CONFIG_SYS_NS16550_COM2, CONFIG_SYS_NS16550_COM3, \ + CONFIG_SYS_NS16550_COM4 } #endif DECLARE_GLOBAL_DATA_PTR; -static void uart_post_init_common(struct NS16550 *com_port, unsigned short bdiv) -{ - volatile char val; - - out_8(&com_port->lcr, 0x80); /* set DLAB bit */ - out_8(&com_port->dll, bdiv); /* set baudrate divisor */ - out_8(&com_port->dlm, bdiv >> 8); /* set baudrate divisor */ - out_8(&com_port->lcr, 0x03); /* clear DLAB; set 8 bits, no parity */ - out_8(&com_port->fcr, 0x00); /* disable FIFO */ - out_8(&com_port->mcr, 0x10); /* enable loopback mode */ - val = in_8(&com_port->lsr); /* clear line status */ - val = in_8(&com_port->rbr); /* read receive buffer */ - out_8(&com_port->scr, 0x00); /* set scratchpad */ - out_8(&com_port->ier, 0x00); /* set interrupt enable reg */ -} - -#if defined(CONFIG_440) || defined(CONFIG_405EX) -#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) -{ - sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ - - get_sys_info(&sysinfo); - - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ - - /* i is the test udiv value -- start with the largest - * possible (32) to minimize serial clock and constrain - * search to umin. - */ - for (i = 32; i > umin; i--) { - ibdiv = div / i; - est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); - if (idiff == 0) { - udiv = i; - break; /* can't do better */ - } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ - } - } - - *pudiv = udiv; - *pbdiv = div / udiv; -} -#endif - -static int uart_post_init (struct NS16550 *com_port) +static int test_ctlr (struct NS16550 *com_port, int index) { - unsigned long reg = 0; - unsigned long udiv; - unsigned short bdiv; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - unsigned long tmp; -#endif + int res = -1; + char test_str[] = "*** UART Test String ***\r\n"; int i; + int divisor; - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_THRE) - break; - udelay (100); - } - MFREG(UART0_SDR, reg); - reg &= ~CR0_MASK; - -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - /* For 440, the cpu clock is on divider chain A, UART on divider - * chain B ... so cpu clock is irrelevant. Get the "optimized" - * values that are subject to the 1/2 opb clock constraint - */ - serial_divs (gd->baudrate, &udiv, &bdiv); -#endif - - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + divisor = (get_serial_clock() + (gd->baudrate * (16 / 2))) / + (16 * gd->baudrate); + NS16550_init(com_port, divisor); /* - * Configure input clock to baudrate generator for all - * available serial ports here + * Set internal loopback mode in UART */ - MTREG(UART0_SDR, reg); -#if defined(UART1_SDR) - MTREG(UART1_SDR, reg); -#endif -#if defined(UART2_SDR) - MTREG(UART2_SDR, reg); -#endif -#if defined(UART3_SDR) - MTREG(UART3_SDR, reg); -#endif - - uart_post_init_common(com_port, bdiv); - - return 0; -} - -#else /* CONFIG_440 */ - -static int uart_post_init (struct NS16550 *com_port) -{ - unsigned long reg; - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - int i; - - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_THRE) - break; - udelay (100); - } - -#if defined(CONFIG_405EZ) - serial_divs(gd->baudrate, &udiv, &bdiv); - clk = tmp = reg = 0; -#else -#ifdef CONFIG_405EP - reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; - reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ - reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (CPC0_UCR, reg); -#else /* CONFIG_405EP */ - reg = mfdcr(CPC0_CR0) & ~CR0_MASK; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - clk = CONFIG_SYS_EXT_SERIAL_CLOCK; - udiv = 1; - reg |= CR0_EXTCLK_ENA; -#else - clk = gd->cpu_clk; -#ifdef CONFIG_SYS_405_UART_ERRATA_59 - udiv = 31; /* Errata 59: stuck at 31 */ -#else - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; -#endif -#endif - reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (CPC0_CR0, reg); -#endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; -#endif /* CONFIG_405EZ */ - - uart_post_init_common(com_port, bdiv); + out_8(&com_port->mcr, in_8(&com_port->mcr) | UART_MCR_LOOP); - return 0; -} -#endif /* CONFIG_440 */ - -static void uart_post_putc (struct NS16550 *com_port, char c) -{ - int i; - - out_8(&com_port->thr, c); /* put character out */ - - /* Wait for transfer completion */ - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_THRE) - break; - udelay (100); - } -} - -static int uart_post_getc (struct NS16550 *com_port) -{ - int i; - - /* Wait for character available */ - for (i = 0; i < 3500; i++) { - if (in_8(&com_port->lsr) & UART_LSR_DR) - break; - udelay (100); - } - - return 0xff & in_8(&com_port->rbr); -} - -static int test_ctlr (struct NS16550 *com_port, int index) -{ - int res = -1; - char test_str[] = "*** UART Test String ***\r\n"; - int i; + /* Reset FIFOs */ + out_8(&com_port->fcr, UART_FCR_RXSR | UART_FCR_TXSR); + udelay(100); - uart_post_init (com_port); + /* Flush RX-FIFO */ + while (NS16550_tstc(com_port)) + NS16550_getc(com_port); for (i = 0; i < sizeof (test_str) - 1; i++) { - uart_post_putc (com_port, test_str[i]); - if (uart_post_getc (com_port) != test_str[i]) + NS16550_putc(com_port, test_str[i]); + if (NS16550_getc(com_port) != test_str[i]) goto done; } res = 0; @@ -27,6 +27,7 @@ _depend: $(obj).depend $(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(SRCS) $(HOSTSRCS) @rm -f $@ + @touch $@ @for f in $(SRCS); do \ g=`basename $$f | sed -e 's/\(.*\)\.\w/\1.o/'`; \ $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ |
