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-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c11
-rw-r--r--board/freescale/mpc837xemds/mpc837xemds.c15
-rw-r--r--board/freescale/mpc837xerdb/mpc837xerdb.c15
-rw-r--r--cpu/mpc83xx/cpu.c166
-rw-r--r--include/mpc83xx.h95
5 files changed, 89 insertions, 213 deletions
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index d90cdb3d3c..2119320da7 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -98,11 +98,8 @@ int board_early_init_f(void)
/* Enable flash write */
bcsr[0xa] &= ~0x04;
- /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
- if (immr->sysconf.spridr == SPR_8360_REV20 ||
- immr->sysconf.spridr == SPR_8360E_REV20 ||
- immr->sysconf.spridr == SPR_8360_REV21 ||
- immr->sysconf.spridr == SPR_8360E_REV21)
+ /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
+ if (REVID_MAJOR(immr->sysconf.spridr) == 2)
bcsr[0xe] = 0x30;
/* Enable second UART */
@@ -308,8 +305,8 @@ void ft_board_setup(void *blob, bd_t *bd)
* if on mpc8360ea rev. 2.1,
* change both ucc phy-connection-types from rgmii-id to rgmii-rxid
*/
- if (immr->sysconf.spridr == SPR_8360_REV21 ||
- immr->sysconf.spridr == SPR_8360E_REV21) {
+ if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
+ (REVID_MINOR(immr->sysconf.spridr) == 1)) {
int nodeoffset;
const char *prop;
int path;
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 6fbd0e0c31..f7cd5fe176 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -36,24 +36,21 @@ int board_early_init_f(void)
u32 spridr = in_be32(&immr->sysconf.spridr);
/* we check only part num, and don't look for CPU revisions */
- switch (spridr >> 16) {
- case SPR_8379E_REV10 >> 16:
- case SPR_8379_REV10 >> 16:
+ switch (spridr) {
+ case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
- case SPR_8378E_REV10 >> 16:
- case SPR_8378_REV10 >> 16:
+ case SPR_8378:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
- case SPR_8377E_REV10 >> 16:
- case SPR_8377_REV10 >> 16:
+ case SPR_8379:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
default:
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 83fb60da00..e054f4e44d 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -140,24 +140,21 @@ int board_early_init_f(void)
u32 spridr = in_be32(&immr->sysconf.spridr);
/* we check only part num, and don't look for CPU revisions */
- switch (spridr >> 16) {
- case SPR_8379E_REV10 >> 16:
- case SPR_8379_REV10 >> 16:
+ switch (PARTID_NO_E(spridr)) {
+ case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
- case SPR_8378E_REV10 >> 16:
- case SPR_8378_REV10 >> 16:
+ case SPR_8378:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
- case SPR_8377E_REV10 >> 16:
- case SPR_8377_REV10 >> 16:
+ case SPR_8379:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
+ fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
default:
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index bff3cefda9..36de78d270 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -42,6 +42,30 @@ int checkcpu(void)
u32 pvr = get_pvr();
u32 spridr;
char buf[32];
+ int i;
+
+#define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
+ const struct cpu_type {
+ char name[15];
+ u32 partid;
+ } cpu_type_list [] = {
+ CPU_TYPE_ENTRY(8311),
+ CPU_TYPE_ENTRY(8313),
+ CPU_TYPE_ENTRY(8314),
+ CPU_TYPE_ENTRY(8315),
+ CPU_TYPE_ENTRY(8321),
+ CPU_TYPE_ENTRY(8323),
+ CPU_TYPE_ENTRY(8343),
+ CPU_TYPE_ENTRY(8347_TBGA_),
+ CPU_TYPE_ENTRY(8347_PBGA_),
+ CPU_TYPE_ENTRY(8349),
+ CPU_TYPE_ENTRY(8358_TBGA_),
+ CPU_TYPE_ENTRY(8358_PBGA_),
+ CPU_TYPE_ENTRY(8360),
+ CPU_TYPE_ENTRY(8377),
+ CPU_TYPE_ENTRY(8378),
+ CPU_TYPE_ENTRY(8379),
+ };
immr = (immap_t *)CFG_IMMR;
@@ -69,130 +93,26 @@ int checkcpu(void)
}
spridr = immr->sysconf.spridr;
- switch(spridr) {
- case SPR_8349E_REV10:
- case SPR_8349E_REV11:
- case SPR_8349E_REV31:
- puts("MPC8349E, ");
- break;
- case SPR_8349_REV10:
- case SPR_8349_REV11:
- case SPR_8349_REV31:
- puts("MPC8349, ");
- break;
- case SPR_8347E_REV10_TBGA:
- case SPR_8347E_REV11_TBGA:
- case SPR_8347E_REV31_TBGA:
- case SPR_8347E_REV10_PBGA:
- case SPR_8347E_REV11_PBGA:
- case SPR_8347E_REV31_PBGA:
- puts("MPC8347E, ");
- break;
- case SPR_8347_REV10_TBGA:
- case SPR_8347_REV11_TBGA:
- case SPR_8347_REV31_TBGA:
- case SPR_8347_REV10_PBGA:
- case SPR_8347_REV11_PBGA:
- case SPR_8347_REV31_PBGA:
- puts("MPC8347, ");
- break;
- case SPR_8343E_REV10:
- case SPR_8343E_REV11:
- case SPR_8343E_REV31:
- puts("MPC8343E, ");
- break;
- case SPR_8343_REV10:
- case SPR_8343_REV11:
- case SPR_8343_REV31:
- puts("MPC8343, ");
- break;
- case SPR_8360E_REV10:
- case SPR_8360E_REV11:
- case SPR_8360E_REV12:
- case SPR_8360E_REV20:
- case SPR_8360E_REV21:
- puts("MPC8360E, ");
- break;
- case SPR_8360_REV10:
- case SPR_8360_REV11:
- case SPR_8360_REV12:
- case SPR_8360_REV20:
- case SPR_8360_REV21:
- puts("MPC8360, ");
- break;
- case SPR_8323E_REV10:
- case SPR_8323E_REV11:
- puts("MPC8323E, ");
- break;
- case SPR_8323_REV10:
- case SPR_8323_REV11:
- puts("MPC8323, ");
- break;
- case SPR_8321E_REV10:
- case SPR_8321E_REV11:
- puts("MPC8321E, ");
- break;
- case SPR_8321_REV10:
- case SPR_8321_REV11:
- puts("MPC8321, ");
- break;
- case SPR_8311_REV10:
- puts("MPC8311, ");
- break;
- case SPR_8311E_REV10:
- puts("MPC8311E, ");
- break;
- case SPR_8313_REV10:
- puts("MPC8313, ");
- break;
- case SPR_8313E_REV10:
- puts("MPC8313E, ");
- break;
- case SPR_8315E_REV10:
- puts("MPC8315E, ");
- break;
- case SPR_8315_REV10:
- puts("MPC8315, ");
- break;
- case SPR_8314E_REV10:
- puts("MPC8314E, ");
- break;
- case SPR_8314_REV10:
- puts("MPC8314, ");
- break;
- case SPR_8379E_REV10:
- puts("MPC8379E, ");
- break;
- case SPR_8379_REV10:
- puts("MPC8379, ");
- break;
- case SPR_8378E_REV10:
- puts("MPC8378E, ");
- break;
- case SPR_8378_REV10:
- puts("MPC8378, ");
- break;
- case SPR_8377E_REV10:
- puts("MPC8377E, ");
- break;
- case SPR_8377_REV10:
- puts("MPC8377, ");
- break;
- default:
- printf("Rev: Unknown revision number:%08x\n"
- "Warning: Unsupported cpu revision!\n",spridr);
- return 0;
- }
-#if defined(CONFIG_MPC834X)
- /* Multiple revisons of 834x processors may have the same SPRIDR value.
- * So use PVR to identify the revision number.
- */
- printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
-#else
- printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
-#endif
- printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
+ for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
+ if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
+ puts("MPC");
+ puts(cpu_type_list[i].name);
+ if (IS_E_PROCESSOR(spridr))
+ puts("E");
+ if (REVID_MAJOR(spridr) >= 2)
+ puts("A");
+ printf(", Rev: %d.%d", REVID_MAJOR(spridr),
+ REVID_MINOR(spridr));
+ break;
+ }
+
+ if (i == ARRAY_SIZE(cpu_type_list))
+ printf("(SPRIDR %08x unknown), ", spridr);
+
+ printf(" at %s MHz, ", strmhz(buf, clock));
+
+ printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
return 0;
}
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 4ee38aafa9..d2e1e2bb6c 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -48,71 +48,36 @@
/* SPRIDR - System Part and Revision ID Register
*/
-#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */
-#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */
-
-#define SPR_8349E_REV10 0x80300100
-#define SPR_8349_REV10 0x80310100
-#define SPR_8347E_REV10_TBGA 0x80320100
-#define SPR_8347_REV10_TBGA 0x80330100
-#define SPR_8347E_REV10_PBGA 0x80340100
-#define SPR_8347_REV10_PBGA 0x80350100
-#define SPR_8343E_REV10 0x80360100
-#define SPR_8343_REV10 0x80370100
-
-#define SPR_8349E_REV11 0x80300101
-#define SPR_8349_REV11 0x80310101
-#define SPR_8347E_REV11_TBGA 0x80320101
-#define SPR_8347_REV11_TBGA 0x80330101
-#define SPR_8347E_REV11_PBGA 0x80340101
-#define SPR_8347_REV11_PBGA 0x80350101
-#define SPR_8343E_REV11 0x80360101
-#define SPR_8343_REV11 0x80370101
-
-#define SPR_8349E_REV31 0x80300300
-#define SPR_8349_REV31 0x80310300
-#define SPR_8347E_REV31_TBGA 0x80320300
-#define SPR_8347_REV31_TBGA 0x80330300
-#define SPR_8347E_REV31_PBGA 0x80340300
-#define SPR_8347_REV31_PBGA 0x80350300
-#define SPR_8343E_REV31 0x80360300
-#define SPR_8343_REV31 0x80370300
-
-#define SPR_8360E_REV10 0x80480010
-#define SPR_8360_REV10 0x80490010
-#define SPR_8360E_REV11 0x80480011
-#define SPR_8360_REV11 0x80490011
-#define SPR_8360E_REV12 0x80480012
-#define SPR_8360_REV12 0x80490012
-#define SPR_8360E_REV20 0x80480020
-#define SPR_8360_REV20 0x80490020
-#define SPR_8360E_REV21 0x80480021
-#define SPR_8360_REV21 0x80490021
-
-#define SPR_8323E_REV10 0x80620010
-#define SPR_8323_REV10 0x80630010
-#define SPR_8321E_REV10 0x80660010
-#define SPR_8321_REV10 0x80670010
-#define SPR_8323E_REV11 0x80620011
-#define SPR_8323_REV11 0x80630011
-#define SPR_8321E_REV11 0x80660011
-#define SPR_8321_REV11 0x80670011
-
-#define SPR_8313E_REV10 0x80B00010
-#define SPR_8313_REV10 0x80B10010
-#define SPR_8311E_REV10 0x80B20010
-#define SPR_8311_REV10 0x80B30010
-#define SPR_8315E_REV10 0x80B40010
-#define SPR_8315_REV10 0x80B50010
-#define SPR_8314E_REV10 0x80B60010
-#define SPR_8314_REV10 0x80B70010
-
-#define SPR_8379E_REV10 0x80C20010
-#define SPR_8379_REV10 0x80C30010
-#define SPR_8378E_REV10 0x80C40010
-#define SPR_8378_REV10 0x80C50010
-#define SPR_8377E_REV10 0x80C60010
-#define SPR_8377_REV10 0x80C70010
+#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
+#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
+
+#if defined(CONFIG_MPC834X)
+#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
+#define REVID_MINOR(spridr) (spridr & 0x000000FF)
+#else
+#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
+#define REVID_MINOR(spridr) (spridr & 0x0000000F)
+#endif
+
+#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
+#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */
+
+#define SPR_8311 0x80B2
+#define SPR_8313 0x80B0
+#define SPR_8314 0x80B6
+#define SPR_8315 0x80B4
+#define SPR_8321 0x8066
+#define SPR_8323 0x8062
+#define SPR_8343 0x8036
+#define SPR_8347_TBGA_ 0x8032
+#define SPR_8347_PBGA_ 0x8034
+#define SPR_8349 0x8030
+#define SPR_8358_TBGA_ 0x804A
+#define SPR_8358_PBGA_ 0x804E
+#define SPR_8360 0x8048
+#define SPR_8377 0x80C6
+#define SPR_8378 0x80C4
+#define SPR_8379 0x80C2
/* SPCR - System Priority Configuration Register
*/
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