diff options
131 files changed, 943 insertions, 1283 deletions
@@ -2947,7 +2947,7 @@ modnet50_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm720t modnet50 evb4510_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t evb4510 + @$(MKCONFIG) $(@:_config=) arm arm720t evb4510 NULL s3c4510b lpc2292sodimm_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm NULL lpc2292 diff --git a/board/netstar/Makefile b/board/netstar/Makefile index 8d911b845b..11a952b9b7 100644 --- a/board/netstar/Makefile +++ b/board/netstar/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := netstar.o flash.o nand.o +COBJS := netstar.o SOBJS := setup.o crcek.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) eeprom.c \ diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c index ce98e20267..e0cea9b3fb 100644 --- a/board/netstar/crcit.c +++ b/board/netstar/crcit.c @@ -31,11 +31,11 @@ #include <sys/stat.h> #include "crcek.h" -extern unsigned long crc32(unsigned long, const unsigned char *, unsigned int); +extern uint32_t crc32(uint32_t, const unsigned char *, uint); -uint32_t data[LOADER_SIZE/4 + 3]; +static uint32_t data[LOADER_SIZE/4 + 3]; -int doit(char *path, unsigned version) +static int do_crc(char *path, unsigned version) { uint32_t *p; ssize_t size; @@ -56,10 +56,10 @@ int doit(char *path, unsigned version) fprintf(stderr, "File too large\n"); return EXIT_FAILURE; } - size = (((size - 1) >> 2) + 1) << 2; + size = (size + 3) & ~3; /* round up to 4 bytes */ data[0] = size + 4; /* add size of version field */ data[1] = version; - data[(size >> 2) + 2] = crc32(0, (unsigned char *)(data + 1), data[0]); + data[2 + (size >> 2)] = crc32(0, (unsigned char *)(data + 1), data[0]); close(fd); if (write(STDOUT_FILENO, data, size + 3*4) == -1) { @@ -73,12 +73,12 @@ int doit(char *path, unsigned version) int main(int argc, char **argv) { if (argc == 2) { - return doit(argv[1], 0); + return do_crc(argv[1], 0); } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { char *endptr, *nptr = argv[2]; unsigned ver = strtoul(nptr, &endptr, 0); if (*nptr != '\0' && *endptr == '\0') - return doit(argv[3], ver); + return do_crc(argv[3], ver); } fprintf(stderr, "Usage: crcit [-v version] <image>\n"); diff --git a/board/netstar/flash.c b/board/netstar/flash.c deleted file mode 100644 index e9eca35e0f..0000000000 --- a/board/netstar/flash.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2005 - * 2N Telekomunikace, a.s. <www.2n.cz> - * Ladislav Michl <michl@2n.cz> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/*#if 0 */ -#if (PHYS_SDRAM_1_SIZE != SZ_32M) - -#include "crcek.h" - -#if (CONFIG_SYS_MAX_FLASH_BANKS > 1) -#error There is always only _one_ flash chip -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define CMD_READ_ARRAY 0x000000f0 -#define CMD_UNLOCK1 0x000000aa -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000a0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002aa << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -/*----------------------------------------------------------------------- - */ - -ulong flash_init(void) -{ - int i; - - flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); - flash_info[0].size = PHYS_FLASH_1_SIZE; - flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - for (i = 0; i < flash_info[0].sector_count; i++) { - switch (i) { - case 0: /* 16kB */ - flash_info[0].start[0] = CONFIG_SYS_FLASH_BASE; - break; - case 1: /* 8kB */ - flash_info[0].start[1] = CONFIG_SYS_FLASH_BASE + 0x4000; - break; - case 2: /* 8kB */ - flash_info[0].start[2] = CONFIG_SYS_FLASH_BASE + 0x4000 + - 0x2000; - break; - case 3: /* 32 KB */ - flash_info[0].start[3] = CONFIG_SYS_FLASH_BASE + 0x4000 + - 2 * 0x2000; - break; - case 4: - flash_info[0].start[4] = CONFIG_SYS_FLASH_BASE + 0x4000 + - 2 * 0x2000 + 0x8000; - break; - default: /* 64kB */ - flash_info[0].start[i] = flash_info[0].start[i-1] + - 0x10000; - break; - } - } - - /* U-Boot */ - flash_protect(FLAG_PROTECT_SET, - LOADER1_OFFSET, - LOADER1_OFFSET + LOADER_SIZE - 1, flash_info); - /* Protect crcek, env and r_env as well */ - flash_protect(FLAG_PROTECT_SET, 0, 0x8000 - 1, flash_info); - - return flash_info[0].size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info(flash_info_t *info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts("AMD: "); - break; - default: - puts("Unknown vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts("AM29LV800BB (8Mb)\n"); - break; - default: - puts("Unknown chip type\n"); - return; - } - - printf(" Size: %ld MB in %d sectors\n", - info->size >> 20, info->sector_count); - - puts(" Sector start addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) - puts("\n "); - - printf(" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts("\n"); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - ushort result; - int prot, sect; - int rc = ERR_OK; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) - return ERR_INVAL; - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) - if (info->protect[sect]) - prot++; - - if (prot) - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - else - putc('\n'); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - while (1) { - result = *addr; - - /* check timeout */ - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - rc = ERR_TIMOUT; - break; - } - - if ((result & 0xfff) & BIT_ERASE_DONE) - break; - - if ((result & 0xffff) & BIT_PROGRAM_ERROR) { - rc = ERR_PROG_ERROR; - break; - } - } - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (rc != ERR_OK) - goto out; - - putc('.'); - } - } -out: - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword(flash_info_t *info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - - /* check if flash is (sufficiently) erased */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked(); - - /* wait until flash is ready */ - while (1) { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - rc = ERR_TIMOUT; - break; - } - - if ((result & 0x80) == (data & 0x80)) - break; - - if ((result & 0xffff) & BIT_PROGRAM_ERROR) { - result = *addr; - - if ((result & 0x80) != (data & 0x80)) - rc = ERR_PROG_ERROR; - } - } - - *addr = CMD_READ_ARRAY; - - if (*addr != data) - rc = ERR_PROG_ERROR; - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) - data = (data >> 8) | (*(uchar *) cp << 8); - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) - data = (data >> 8) | (*(uchar *) cp << 8); - - if ((rc = write_hword(info, wp, data)) != 0) - return (rc); - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword(info, wp, data)) != 0) - return (rc); - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) - data = (data >> 8) | (*(uchar *) cp << 8); - - return write_hword(info, wp, data); -} - -#endif diff --git a/board/netstar/nand.c b/board/netstar/nand.c deleted file mode 100644 index e3ab66f2fb..0000000000 --- a/board/netstar/nand.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> - -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> - -/* - * hardware specific access to control-lines - */ -#define MASK_CLE 0x02 -#define MASK_ALE 0x04 - -static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - IO_ADDR_W |= MASK_CLE; - if ( ctrl & NAND_ALE ) - IO_ADDR_W |= MASK_ALE; - } - this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->options = NAND_SAMSUNG_LP_OPTIONS; - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = netstar_nand_hwcontrol; - nand->chip_delay = 400; - return 0; -} -#endif diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c index f52afe50c7..ee4f2cdca7 100644 --- a/board/netstar/netstar.c +++ b/board/netstar/netstar.c @@ -21,6 +21,11 @@ */ #include <common.h> +#include <i2c.h> +#include <flash.h> +#include <nand.h> + +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +57,10 @@ int dram_init(void) int misc_init_r(void) { +#if defined(CONFIG_RTC_DS1307) + /* enable trickle charge */ + i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0x10, 0xaa); +#endif return 0; } @@ -59,3 +68,50 @@ int board_late_init(void) { return 0; } + +#if defined(CONFIG_CMD_FLASH) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* AM29LV800 boot flash */ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; + } + + return 0; +} +#endif + +#if defined(CONFIG_CMD_NAND) +/* + * hardware specific access to control-lines + * + * NAND_NCE: bit 0 - don't care + * NAND_CLE: bit 1 -> bit 1 (0x0002) + * NAND_ALE: bit 2 -> bit 2 (0x0004) + */ +static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *chip = mtd->priv; + unsigned long mask; + + if (cmd == NAND_CMD_NONE) + return; + + mask = (ctrl & NAND_CLE) ? 0x02 : 0; + if (ctrl & NAND_ALE) + mask |= 0x04; + writeb(cmd, (unsigned long)chip->IO_ADDR_W | mask); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = netstar_nand_hwcontrol; + nand->chip_delay = 400; + return 0; +} +#endif diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index b648ffd6ff..0e06f0a2b2 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o serial.o generic.o +COBJS = interrupts.o generic.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c index fb02a49be7..6be1262f3a 100644 --- a/cpu/arm1136/omap24xx/interrupts.c +++ b/cpu/arm1136/omap24xx/interrupts.c @@ -49,7 +49,7 @@ int interrupt_init (void) /* Start the counter ticking up */ *((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/ - val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ + val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/ *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */ reset_timer_masked(); /* init the timestamp and lastinc value */ diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile index 4ab181159a..fa4ee3f24e 100644 --- a/cpu/arm1176/s3c64xx/Makefile +++ b/cpu/arm1176/s3c64xx/Makefile @@ -30,7 +30,6 @@ LIB = $(obj)lib$(SOC).a COBJS-y = interrupts.o COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o -COBJS-$(CONFIG_USB_OHCI_NEW) += usb.o OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) diff --git a/cpu/arm720t/Makefile b/cpu/arm720t/Makefile index c97f329638..d5ac7d3fd9 100644 --- a/cpu/arm720t/Makefile +++ b/cpu/arm720t/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o serial_netarm.o interrupts.o cpu.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 5ac8f59ab3..8166982e6a 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -188,71 +188,9 @@ int dcache_status (void) { return (read_p15_c1 () & C1_IDC) != 0; } - -#elif defined(CONFIG_S3C4510B) - -void icache_enable (void) -{ - s32 i; - - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); - - /* 8KB cache, write enable */ - SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); - - /* clear TAG RAM bits */ - for ( i = 0; i < 256; i++) - PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); - - /* clear SET0 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); - - /* clear SET1 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); - - /* enable cache */ - SET_REG( REG_SYSCFG, CACHE_ENABLE); - -} - -void icache_disable (void) -{ - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); -} - -int icache_status (void) -{ - return GET_REG( REG_SYSCFG) & CACHE_ENABLE; -} - -void dcache_enable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_enable(); -} - -void dcache_disable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_disable(); -} - -int dcache_status (void) -{ - /* we don't have seperate instruction/data caches */ - return icache_status(); -} - #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific cache setup for IntegratorAP/CM720T as yet */ void icache_enable (void) { } -#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */ -#else -#error No icache/dcache enable/disable functions defined for this CPU type #endif diff --git a/cpu/arm720t/s3c4510b/Makefile b/cpu/arm720t/s3c4510b/Makefile new file mode 100644 index 0000000000..c9520b632a --- /dev/null +++ b/cpu/arm720t/s3c4510b/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y += cache.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/cpu/arm720t/s3c4510b/cache.c b/cpu/arm720t/s3c4510b/cache.c new file mode 100644 index 0000000000..104d287b26 --- /dev/null +++ b/cpu/arm720t/s3c4510b/cache.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/hardware.h> + +void icache_enable (void) +{ + s32 i; + + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); + + /* 8KB cache, write enable */ + SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); + + /* clear TAG RAM bits */ + for ( i = 0; i < 256; i++) + PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); + + /* clear SET0 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); + + /* clear SET1 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); + + /* enable cache */ + SET_REG( REG_SYSCFG, CACHE_ENABLE); + +} + +void icache_disable (void) +{ + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); +} + +int icache_status (void) +{ + return GET_REG( REG_SYSCFG) & CACHE_ENABLE; +} + +void dcache_enable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_enable(); +} + +void dcache_disable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_disable(); +} + +int dcache_status (void) +{ + /* we don't have seperate instruction/data caches */ + return icache_status(); +} diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile index 9207ec1bcb..d3352deb4b 100644 --- a/cpu/arm920t/imx/Makefile +++ b/cpu/arm920t/imx/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = generic.o interrupts.o serial.o speed.o +COBJS = generic.o interrupts.o speed.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile index 7db9473524..f6b006300b 100644 --- a/cpu/arm920t/ks8695/Makefile +++ b/cpu/arm920t/ks8695/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = interrupts.o serial.o +COBJS = interrupts.o SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile index 676492025a..3afe19ce9c 100644 --- a/cpu/arm920t/s3c24x0/Makefile +++ b/cpu/arm920t/s3c24x0/Makefile @@ -25,8 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = i2c.o interrupts.o serial.o speed.o \ - usb.o usb_ohci.o nand.o +COBJS = interrupts.o speed.o usb.o usb_ohci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c index 3ef455447c..e5c77f7a0f 100644 --- a/cpu/arm925t/interrupts.c +++ b/cpu/arm925t/interrupts.c @@ -35,29 +35,26 @@ #include <common.h> #include <arm925t.h> #include <configs/omap1510.h> +#include <asm/io.h> #define TIMER_LOAD_VAL 0xffffffff -/* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8)) - -static ulong timestamp; -static ulong lastdec; +static uint32_t timestamp; +static uint32_t lastdec; /* nothing really to do with interrupts, just starts up a counter. */ int interrupt_init (void) { - int32_t val; - /* Start the decrementer ticking down from 0xffffffff */ - *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT); - *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; + __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); + __raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | + (CONFIG_SYS_PTV << MPUTIM_PTV_BIT), + CONFIG_SYS_TIMERBASE + CNTL_TIMER); /* init the timestamp and lastdec value */ reset_timer_masked(); - return (0); + return 0; } /* @@ -84,17 +81,17 @@ void udelay (unsigned long usec) { ulong tmo, tmp; - if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ - }else{ /* else small number, don't kill it prior to HZ multiply */ + } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; tmo /= (1000*1000); } tmp = get_timer (0); /* get current timestamp */ - if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + if ((tmo + tmp + 1) < tmp) /* if setting this fordward will roll time stamp */ reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ else tmo += tmp; /* else, set advancing stamp wake up time */ @@ -106,13 +103,13 @@ void udelay (unsigned long usec) void reset_timer_masked (void) { /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ + lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); timestamp = 0; /* start "advancing" time stamp from 0 */ } ulong get_timer_masked (void) { - ulong now = READ_TIMER; /* current tick value */ + uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); if (lastdec >= now) { /* normal mode (non roll) */ /* normal mode */ @@ -136,7 +133,7 @@ void udelay_masked (unsigned long usec) #ifdef CONFIG_INNOVATOROMAP1510 #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ volatile int i, time_remaining = LOOPS_PER_MSEC*usec; - for (i=time_remaining; i>0; i--) { } + for (i=time_remaining; i>0; i--) { } #else ulong tmo; @@ -145,7 +142,7 @@ void udelay_masked (unsigned long usec) if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ tmo /= 1000; /* finish normalize. */ } else { /* else small number, don't kill it prior to HZ multiply */ tmo = usec * CONFIG_SYS_HZ; @@ -176,8 +173,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk (void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index 0f77f402ed..ed24e6569f 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o +COBJS = timer.o ether.o lxt972.o dp83848.o SOBJS = lowlevel_init.o reset.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c index 49e74abb3b..bedc2e7544 100644 --- a/cpu/arm926ejs/omap/timer.c +++ b/cpu/arm926ejs/omap/timer.c @@ -52,7 +52,7 @@ int timer_init (void) /* Start the decrementer ticking down from 0xffffffff */ *((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; - val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT); + val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT); *((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val; /* init the timestamp and lastdec value */ diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c index 9e9817de64..5d9c4e32c2 100644 --- a/cpu/arm_cortexa8/omap3/interrupts.c +++ b/cpu/arm_cortexa8/omap3/interrupts.c @@ -175,7 +175,7 @@ int interrupt_init(void) /* start the counter ticking up, reload value on overflow */ writel(TIMER_LOAD_VAL, &timer_base->tldr); /* enable timer */ - writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, + writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, &timer_base->tclr); reset_timer_masked(); /* init the timestamp and lastinc value */ diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile index 790faebd39..ae909a699f 100644 --- a/cpu/s3c44b0/Makefile +++ b/cpu/s3c44b0/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o +COBJS = cache.o cpu.o interrupts.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/s3c44b0/cache.c b/cpu/s3c44b0/cache.c new file mode 100644 index 0000000000..bc10171515 --- /dev/null +++ b/cpu/s3c44b0/cache.c @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/hardware.h> + +static void s3c44b0_flush_cache(void) +{ + volatile int i; + /* flush cycle */ + for(i=0x10002000;i<0x10004800;i+=16) + { + *((int *)i)=0x0; + } +} + +void icache_enable (void) +{ + ulong reg; + + s3c44b0_flush_cache(); + + /* + Init cache + Non-cacheable area (everything outside RAM) + 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; + + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; +} + +void icache_disable (void) +{ + ulong reg; + + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; +} + +int icache_status (void) +{ + return 0; +} + +void dcache_enable (void) +{ + icache_enable(); +} + +void dcache_disable (void) +{ + icache_disable(); +} + +int dcache_status (void) +{ + return dcache_status(); +} + diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c index 2960f2f3af..e4cdb823b4 100644 --- a/cpu/s3c44b0/cpu.c +++ b/cpu/s3c44b0/cpu.c @@ -32,17 +32,6 @@ #include <command.h> #include <asm/hardware.h> -static void s3c44b0_flush_cache(void) -{ - volatile int i; - /* flush cycle */ - for(i=0x10002000;i<0x10004800;i+=16) - { - *((int *)i)=0x0; - } -} - - int cpu_init (void) { icache_enable(); @@ -92,422 +81,3 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /*NOTREACHED*/ return (0); } - -void icache_enable (void) -{ - ulong reg; - - s3c44b0_flush_cache(); - - /* - Init cache - Non-cacheable area (everything outside RAM) - 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; - - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; -} - -void icache_disable (void) -{ - ulong reg; - - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; -} - -int icache_status (void) -{ - return 0; -} - -void dcache_enable (void) -{ - icache_enable(); -} - -void dcache_disable (void) -{ - icache_disable(); -} - -int dcache_status (void) -{ - return dcache_status(); -} - -/* - RTC stuff -*/ -#include <rtc.h> -#ifndef BCD2HEX - #define BCD2HEX(n) ((n>>4)*10+(n&0x0f)) -#endif -#ifndef HEX2BCD - #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) -#endif - -int rtc_get (struct rtc_time* tm) -{ - RTCCON |= 1; - tm->tm_year = BCD2HEX(BCDYEAR); - tm->tm_mon = BCD2HEX(BCDMON); - tm->tm_wday = BCD2HEX(BCDDATE); - tm->tm_mday = BCD2HEX(BCDDAY); - tm->tm_hour = BCD2HEX(BCDHOUR); - tm->tm_min = BCD2HEX(BCDMIN); - tm->tm_sec = BCD2HEX(BCDSEC); - - if (tm->tm_sec==0) { - /* we have to re-read the rtc data because of the "one second deviation" problem */ - /* see RTC datasheet for more info about it */ - tm->tm_year = BCD2HEX(BCDYEAR); - tm->tm_mon = BCD2HEX(BCDMON); - tm->tm_mday = BCD2HEX(BCDDAY); - tm->tm_wday = BCD2HEX(BCDDATE); - tm->tm_hour = BCD2HEX(BCDHOUR); - tm->tm_min = BCD2HEX(BCDMIN); - tm->tm_sec = BCD2HEX(BCDSEC); - } - - RTCCON &= ~1; - - if(tm->tm_year >= 70) - tm->tm_year += 1900; - else - tm->tm_year += 2000; - - return 0; -} - -int rtc_set (struct rtc_time* tm) -{ - if(tm->tm_year < 2000) - tm->tm_year -= 1900; - else - tm->tm_year -= 2000; - - RTCCON |= 1; - BCDYEAR = HEX2BCD(tm->tm_year); - BCDMON = HEX2BCD(tm->tm_mon); - BCDDAY = HEX2BCD(tm->tm_mday); - BCDDATE = HEX2BCD(tm->tm_wday); - BCDHOUR = HEX2BCD(tm->tm_hour); - BCDMIN = HEX2BCD(tm->tm_min); - BCDSEC = HEX2BCD(tm->tm_sec); - RTCCON &= 1; - - return 0; -} - -void rtc_reset (void) -{ - RTCCON |= 1; - BCDYEAR = 0; - BCDMON = 0; - BCDDAY = 0; - BCDDATE = 0; - BCDHOUR = 0; - BCDMIN = 0; - BCDSEC = 0; - RTCCON &= 1; -} - - -/* - I2C stuff -*/ - -/* - * Initialization, must be called once on start up, may be called - * repeatedly to change the speed and slave addresses. - */ -void i2c_init(int speed, int slaveaddr) -{ - /* - setting up I2C support - */ - unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; - - save_F = PCONF; - save_PF = PUPF; - - rPCONF = ((save_F & ~(0xF))| 0xa); - rPUPF = (save_PF | 0x3); - PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ - PUPF = rPUPF; /* Disable pull-up */ - - /* Configuring pin for WC pin of EEprom */ - rPCONA = PCONA; - rPCONA &= ~(1<<9); - PCONA = rPCONA; - - rPDATA = PDATA; - rPDATA &= ~(1<<9); - PDATA = rPDATA; - - /* - Enable ACK, IICCLK=MCLK/16, enable interrupt - 75MHz/16/(12+1) = 390625 Hz - */ - rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); - IICCON = rIICCON; - - IICADD = slaveaddr; -} - -/* - * Probe the given I2C chip address. Returns 0 if a chip responded, - * not 0 on failure. - */ -int i2c_probe(uchar chip) -{ - /* - not implemented - */ - - printf("i2c_probe chip %d\n", (int) chip); - return -1; -} - -/* - * Read/Write interface: - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -#define S3C44B0X_rIIC_INTPEND (1<<4) -#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) -#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) -#define S3C44B0_IIC_TIMEOUT 100 - -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - - int k, j, temp; - u32 rIICSTAT; - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - /* wait and check ACK */ - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read operation... - */ - - IICDS = chip | 0x01; /* this is a read operation... */ - - rIICSTAT = 0x90; /*master recv*/ - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - for (j=0; j<len-1; j++) { - - /*clear pending bit to resume */ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - - buffer[j] = IICDS; /*save readed data*/ - - } /*end for(j)*/ - - /* - reading the last data - unset ACK generation - */ - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7)); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - buffer[j] = IICDS; /*save readed data*/ - - rIICSTAT = 0x90; /*master recv*/ - - /* Write operation Terminate sending STOP */ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - IICCON = IICCON | (1<<7); /*restore ACK generation*/ - - return 0; -} - -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) -{ - int j, k; - u32 rIICSTAT, temp; - - - /* - send the device offset - */ - - rIICSTAT = 0xD0; - IICSTAT = rIICSTAT; - - IICDS = chip; /* this is a write operation... */ - - rIICSTAT |= (1<<5); - IICSTAT = rIICSTAT; - - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - IICDS = addr; - IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); - - /* wait and check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - udelay(2000); - } - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - temp = IICSTAT; - if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) - return -1; - - /* - now we can start with the read write operation - */ - for (j=0; j<len; j++) { - - IICDS = buffer[j]; /*prerare data to write*/ - - /*clear pending bit to resume*/ - - temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); - IICCON = temp; - - /* wait but NOT check ACK */ - for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { - temp = IICCON; - if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) - break; - - udelay(2000); - } - - if (k==S3C44B0_IIC_TIMEOUT) - return -1; - - } /* end for(j) */ - - /* sending stop to terminate */ - rIICSTAT = 0xD0; /*master send*/ - IICSTAT = rIICSTAT; - /*Clear Int Pending Bit to RESUME*/ - temp = IICCON; - IICCON = temp & (~S3C44B0X_rIIC_INTPEND); - - return 0; -} diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile index 790faebd39..fd696f7efb 100644 --- a/cpu/sa1100/Makefile +++ b/cpu/sa1100/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = serial.o interrupts.o cpu.o +COBJS = interrupts.o cpu.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 9c74657dad..ef32f13377 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -26,11 +26,14 @@ include $(TOPDIR)/config.mk LIB := $(obj)libi2c.a COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o +COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o +COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o +COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o diff --git a/cpu/arm926ejs/davinci/i2c.c b/drivers/i2c/davinci_i2c.c index 3ba20ef186..eee1cbd25d 100644 --- a/cpu/arm926ejs/davinci/i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -25,9 +25,6 @@ */ #include <common.h> - -#ifdef CONFIG_DRIVER_DAVINCI_I2C - #include <i2c.h> #include <asm/arch/hardware.h> #include <asm/arch/i2c_defs.h> @@ -330,5 +327,3 @@ int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) return(0); } - -#endif /* CONFIG_DRIVER_DAVINCI_I2C */ diff --git a/cpu/arm920t/s3c24x0/i2c.c b/drivers/i2c/s3c24x0_i2c.c index fba5cd1b5f..f0c1aa3406 100644 --- a/cpu/arm920t/s3c24x0/i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -27,9 +27,6 @@ */ #include <common.h> - -#ifdef CONFIG_DRIVER_S3C24X0_I2C - #if defined(CONFIG_S3C2400) #include <s3c2400.h> #elif defined(CONFIG_S3C2410) @@ -443,5 +440,3 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) len) != 0); } #endif /* CONFIG_HARD_I2C */ - -#endif /* CONFIG_DRIVER_S3C24X0_I2C */ diff --git a/drivers/i2c/s3c44b0_i2c.c b/drivers/i2c/s3c44b0_i2c.c new file mode 100644 index 0000000000..b4d904b2eb --- /dev/null +++ b/drivers/i2c/s3c44b0_i2c.c @@ -0,0 +1,315 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/hardware.h> + +/* + * Initialization, must be called once on start up, may be called + * repeatedly to change the speed and slave addresses. + */ +void i2c_init(int speed, int slaveaddr) +{ + /* + setting up I2C support + */ + unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; + + save_F = PCONF; + save_PF = PUPF; + + rPCONF = ((save_F & ~(0xF))| 0xa); + rPUPF = (save_PF | 0x3); + PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ + PUPF = rPUPF; /* Disable pull-up */ + + /* Configuring pin for WC pin of EEprom */ + rPCONA = PCONA; + rPCONA &= ~(1<<9); + PCONA = rPCONA; + + rPDATA = PDATA; + rPDATA &= ~(1<<9); + PDATA = rPDATA; + + /* + Enable ACK, IICCLK=MCLK/16, enable interrupt + 75MHz/16/(12+1) = 390625 Hz + */ + rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); + IICCON = rIICCON; + + IICADD = slaveaddr; +} + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ +int i2c_probe(uchar chip) +{ + /* + not implemented + */ + + printf("i2c_probe chip %d\n", (int) chip); + return -1; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ + +#define S3C44B0X_rIIC_INTPEND (1<<4) +#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) +#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) +#define S3C44B0_IIC_TIMEOUT 100 + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + + int k, j, temp; + u32 rIICSTAT; + + /* + send the device offset + */ + + rIICSTAT = 0xD0; + IICSTAT = rIICSTAT; + + IICDS = chip; /* this is a write operation... */ + + rIICSTAT |= (1<<5); + IICSTAT = rIICSTAT; + + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + udelay(2000); + } + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + /* wait and check ACK */ + temp = IICSTAT; + if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) + return -1; + + IICDS = addr; + IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); + + /* wait and check ACK */ + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + udelay(2000); + } + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + temp = IICSTAT; + if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) + return -1; + + /* + now we can start with the read operation... + */ + + IICDS = chip | 0x01; /* this is a read operation... */ + + rIICSTAT = 0x90; /*master recv*/ + rIICSTAT |= (1<<5); + IICSTAT = rIICSTAT; + + IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); + + /* wait and check ACK */ + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + udelay(2000); + } + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + temp = IICSTAT; + if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) + return -1; + + for (j=0; j<len-1; j++) { + + /*clear pending bit to resume */ + + temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); + IICCON = temp; + + /* wait and check ACK */ + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + udelay(2000); + } + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + + buffer[j] = IICDS; /*save readed data*/ + + } /*end for(j)*/ + + /* + reading the last data + unset ACK generation + */ + temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7)); + IICCON = temp; + + /* wait but NOT check ACK */ + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + udelay(2000); + } + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + buffer[j] = IICDS; /*save readed data*/ + + rIICSTAT = 0x90; /*master recv*/ + + /* Write operation Terminate sending STOP */ + IICSTAT = rIICSTAT; + /*Clear Int Pending Bit to RESUME*/ + temp = IICCON; + IICCON = temp & (~S3C44B0X_rIIC_INTPEND); + + IICCON = IICCON | (1<<7); /*restore ACK generation*/ + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int j, k; + u32 rIICSTAT, temp; + + + /* + send the device offset + */ + + rIICSTAT = 0xD0; + IICSTAT = rIICSTAT; + + IICDS = chip; /* this is a write operation... */ + + rIICSTAT |= (1<<5); + IICSTAT = rIICSTAT; + + IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); + + /* wait and check ACK */ + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + udelay(2000); + } + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + temp = IICSTAT; + if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) + return -1; + + IICDS = addr; + IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); + + /* wait and check ACK */ + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + udelay(2000); + } + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + temp = IICSTAT; + if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) + return -1; + + /* + now we can start with the read write operation + */ + for (j=0; j<len; j++) { + + IICDS = buffer[j]; /*prerare data to write*/ + + /*clear pending bit to resume*/ + + temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); + IICCON = temp; + + /* wait but NOT check ACK */ + for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { + temp = IICCON; + if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) + break; + + udelay(2000); + } + + if (k==S3C44B0_IIC_TIMEOUT) + return -1; + + } /* end for(j) */ + + /* sending stop to terminate */ + rIICSTAT = 0xD0; /*master send*/ + IICSTAT = rIICSTAT; + /*Clear Int Pending Bit to RESUME*/ + temp = IICCON; + IICCON = temp & (~S3C44B0X_rIIC_INTPEND); + + return 0; +} diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 03b0028e7c..471cd6bcf7 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -37,9 +37,11 @@ endif COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o +COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o +COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o endif diff --git a/cpu/arm926ejs/davinci/nand.c b/drivers/mtd/nand/davinci_nand.c index 014e2b0c11..a974667dc9 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -43,10 +43,6 @@ #include <common.h> #include <asm/io.h> - -#ifdef CONFIG_SYS_USE_NAND -#if !defined(CONFIG_NAND_LEGACY) - #include <nand.h> #include <asm/arch/nand_defs.h> #include <asm/arch/emif_defs.h> @@ -468,8 +464,3 @@ int board_nand_init(struct nand_chip *nand) return(0); } - -#else -#error "U-Boot legacy NAND support not available for DaVinci chips" -#endif -#endif /* CONFIG_SYS_USE_NAND */ diff --git a/cpu/arm920t/s3c24x0/nand.c b/drivers/mtd/nand/s3c2410_nand.c index 60174fb4d2..d27a625471 100644 --- a/cpu/arm920t/s3c24x0/nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -26,9 +26,6 @@ #define DEBUGN(x, args ...) {} #endif -#if defined(CONFIG_CMD_NAND) -#if !defined(CONFIG_NAND_LEGACY) - #include <nand.h> #include <s3c2410.h> #include <asm/io.h> @@ -172,8 +169,3 @@ int board_nand_init(struct nand_chip *nand) return 0; } - -#else - #error "U-Boot legacy NAND support not available for S3C2410" -#endif -#endif diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 6adece23cc..822dc1a0e1 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -58,6 +58,7 @@ COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o COBJS-$(CONFIG_RTC_RX8025) += rx8025.o COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o +COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o COBJS-$(CONFIG_RTC_X1205) += x1205.o COBJS := $(sort $(COBJS-y)) diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c new file mode 100644 index 0000000000..489536f3fb --- /dev/null +++ b/drivers/rtc/s3c44b0_rtc.c @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * S3C44B0 CPU specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/hardware.h> +#include <rtc.h> +#include <bcd.h> + +int rtc_get (struct rtc_time* tm) +{ + RTCCON |= 1; + tm->tm_year = BCD2BIN(BCDYEAR); + tm->tm_mon = BCD2BIN(BCDMON); + tm->tm_wday = BCD2BIN(BCDDATE); + tm->tm_mday = BCD2BIN(BCDDAY); + tm->tm_hour = BCD2BIN(BCDHOUR); + tm->tm_min = BCD2BIN(BCDMIN); + tm->tm_sec = BCD2BIN(BCDSEC); + + if (tm->tm_sec==0) { + /* we have to re-read the rtc data because of the "one second deviation" problem */ + /* see RTC datasheet for more info about it */ + tm->tm_year = BCD2BIN(BCDYEAR); + tm->tm_mon = BCD2BIN(BCDMON); + tm->tm_mday = BCD2BIN(BCDDAY); + tm->tm_wday = BCD2BIN(BCDDATE); + tm->tm_hour = BCD2BIN(BCDHOUR); + tm->tm_min = BCD2BIN(BCDMIN); + tm->tm_sec = BCD2BIN(BCDSEC); + } + + RTCCON &= ~1; + + if(tm->tm_year >= 70) + tm->tm_year += 1900; + else + tm->tm_year += 2000; + + return 0; +} + +int rtc_set (struct rtc_time* tm) +{ + if(tm->tm_year < 2000) + tm->tm_year -= 1900; + else + tm->tm_year -= 2000; + + RTCCON |= 1; + BCDYEAR = BIN2BCD(tm->tm_year); + BCDMON = BIN2BCD(tm->tm_mon); + BCDDAY = BIN2BCD(tm->tm_mday); + BCDDATE = BIN2BCD(tm->tm_wday); + BCDHOUR = BIN2BCD(tm->tm_hour); + BCDMIN = BIN2BCD(tm->tm_min); + BCDSEC = BIN2BCD(tm->tm_sec); + RTCCON &= 1; + + return 0; +} + +void rtc_reset (void) +{ + RTCCON |= 1; + BCDYEAR = 0; + BCDMON = 0; + BCDDAY = 0; + BCDDATE = 0; + BCDHOUR = 0; + BCDMIN = 0; + BCDSEC = 0; + RTCCON &= 1; +} + diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index d0efd73c5b..696d5fbbba 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -33,10 +33,19 @@ COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o +COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o +COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o +COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o +COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o +COBJS-$(CONFIG_MX31_UART) += serial_mx31.o +COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o +COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o +COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o +COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/cpu/arm720t/serial.c b/drivers/serial/serial_clps7111.c index 54a9b3137b..a6aecadd13 100644 --- a/cpu/arm720t/serial.c +++ b/drivers/serial/serial_clps7111.c @@ -29,9 +29,6 @@ */ #include <common.h> - -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) - #include <clps7111.h> DECLARE_GLOBAL_DATA_PTR; @@ -122,81 +119,3 @@ serial_puts (const char *s) serial_putc (*s++); } } - -#elif defined(CONFIG_LPC2292) - -DECLARE_GLOBAL_DATA_PTR; - -#include <asm/arch/hardware.h> - -void serial_setbrg (void) -{ - unsigned short divisor = 0; - - switch (gd->baudrate) { - case 1200: divisor = 3072; break; - case 9600: divisor = 384; break; - case 19200: divisor = 192; break; - case 38400: divisor = 96; break; - case 57600: divisor = 64; break; - case 115200: divisor = 32; break; - default: hang (); break; - } - - /* init serial UART0 */ - PUT8(U0LCR, 0); - PUT8(U0IER, 0); - PUT8(U0LCR, 0x80); /* DLAB=1 */ - PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); - PUT8(U0DLM, (unsigned char)(divisor >> 8)); - PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ - PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ -} - -int serial_init (void) -{ - unsigned long pinsel0; - - serial_setbrg (); - - pinsel0 = GET32(PINSEL0); - pinsel0 &= ~(0x00000003); - pinsel0 |= 5; - PUT32(PINSEL0, pinsel0); - - return (0); -} - -void serial_putc (const char c) -{ - if (c == '\n') - { - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, '\r'); - } - - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, c); -} - -int serial_getc (void) -{ - while((GET8(U0LSR) & 1) == 0); - return GET8(U0RBR); -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -/* Test if there is a byte to read */ -int serial_tstc (void) -{ - return (GET8(U0LSR) & 1); -} - -#endif diff --git a/cpu/arm920t/imx/serial.c b/drivers/serial/serial_imx.c index 85f1167e36..b9ca748f69 100644 --- a/cpu/arm920t/imx/serial.c +++ b/drivers/serial/serial_imx.c @@ -18,12 +18,8 @@ */ #include <common.h> -#if defined (CONFIG_IMX) - #include <asm/arch/imx-regs.h> -#ifndef CONFIG_IMX_SERIAL_NONE - #if defined CONFIG_IMX_SERIAL1 #define UART_BASE IMX_UART1_BASE #elif defined CONFIG_IMX_SERIAL2 @@ -223,5 +219,3 @@ serial_puts (const char *s) serial_putc (*s++); } } -#endif /* CONFIG_IMX_SERIAL_NONE */ -#endif /* defined CONFIG_IMX */ diff --git a/cpu/arm920t/ks8695/serial.c b/drivers/serial/serial_ks8695.c index aacd1be630..aacd1be630 100644 --- a/cpu/arm920t/ks8695/serial.c +++ b/drivers/serial/serial_ks8695.c diff --git a/drivers/serial/serial_lpc2292.c b/drivers/serial/serial_lpc2292.c new file mode 100644 index 0000000000..87b7d5f411 --- /dev/null +++ b/drivers/serial/serial_lpc2292.c @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg (void) +{ + unsigned short divisor = 0; + + switch (gd->baudrate) { + case 1200: divisor = 3072; break; + case 9600: divisor = 384; break; + case 19200: divisor = 192; break; + case 38400: divisor = 96; break; + case 57600: divisor = 64; break; + case 115200: divisor = 32; break; + default: hang (); break; + } + + /* init serial UART0 */ + PUT8(U0LCR, 0); + PUT8(U0IER, 0); + PUT8(U0LCR, 0x80); /* DLAB=1 */ + PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); + PUT8(U0DLM, (unsigned char)(divisor >> 8)); + PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ + PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ +} + +int serial_init (void) +{ + unsigned long pinsel0; + + serial_setbrg (); + + pinsel0 = GET32(PINSEL0); + pinsel0 &= ~(0x00000003); + pinsel0 |= 5; + PUT32(PINSEL0, pinsel0); + + return (0); +} + +void serial_putc (const char c) +{ + if (c == '\n') + { + while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ + PUT8(U0THR, '\r'); + } + + while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ + PUT8(U0THR, c); +} + +int serial_getc (void) +{ + while((GET8(U0LSR) & 1) == 0); + return GET8(U0RBR); +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* Test if there is a byte to read */ +int serial_tstc (void) +{ + return (GET8(U0LSR) & 1); +} + diff --git a/cpu/arm1136/mx31/serial.c b/drivers/serial/serial_mx31.c index e025e941d9..7c0682ad77 100644 --- a/cpu/arm1136/mx31/serial.c +++ b/drivers/serial/serial_mx31.c @@ -18,9 +18,6 @@ */ #include <common.h> - -#if defined CONFIG_MX31_UART - #include <asm/arch/mx31.h> #define __REG(x) (*((volatile u32 *)(x))) @@ -227,6 +224,3 @@ int serial_init (void) return 0; } - - -#endif /* CONFIG_MX31 */ diff --git a/cpu/arm720t/serial_netarm.c b/drivers/serial/serial_netarm.c index 1a1b2dbd4f..2eb5393404 100644 --- a/cpu/arm720t/serial_netarm.c +++ b/drivers/serial/serial_netarm.c @@ -29,9 +29,6 @@ */ #include <common.h> - -#ifdef CONFIG_NETARM - #include <asm/hardware.h> DECLARE_GLOBAL_DATA_PTR; @@ -196,5 +193,3 @@ void serial_puts (const char *s) serial_putc (*s++); } } - -#endif /* CONFIG_NETARM */ diff --git a/cpu/arm920t/s3c24x0/serial.c b/drivers/serial/serial_s3c24x0.c index 064b99871d..1b1b7a612e 100644 --- a/cpu/arm920t/s3c24x0/serial.c +++ b/drivers/serial/serial_s3c24x0.c @@ -19,8 +19,6 @@ */ #include <common.h> -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) - #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) #include <s3c2400.h> #elif defined(CONFIG_S3C2410) @@ -300,5 +298,3 @@ struct serial_device s3c24xx_serial2_device = INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3"); #endif /* CONFIG_SERIAL_MULTI */ - -#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/cpu/s3c44b0/serial.c b/drivers/serial/serial_s3c44b0.c index 95d0266c6c..95d0266c6c 100644 --- a/cpu/s3c44b0/serial.c +++ b/drivers/serial/serial_s3c44b0.c diff --git a/cpu/sa1100/serial.c b/drivers/serial/serial_sa1100.c index 5d1887580d..5d1887580d 100644 --- a/cpu/sa1100/serial.c +++ b/drivers/serial/serial_sa1100.c diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index b306a65a98..7ddb72a0e1 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_USB_EHCI) += usb_ehci_core.o # host COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o +COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx_usb.o COBJS-$(CONFIG_USB_SL811HS) += sl811_usb.o COBJS-$(CONFIG_USB_EHCI_FSL) += usb_ehci_fsl.o COBJS-$(CONFIG_USB_EHCI_PCI) += usb_ehci_pci.o diff --git a/cpu/arm1176/s3c64xx/usb.c b/drivers/usb/s3c64xx_usb.c index 274a4ed309..274a4ed309 100644 --- a/cpu/arm1176/s3c64xx/usb.c +++ b/drivers/usb/s3c64xx_usb.c diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h index 3056ca7f67..ec053c9912 100644 --- a/include/asm-arm/arch-arm720t/hardware.h +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -24,9 +24,7 @@ * MA 02111-1307 USA */ -#if defined(CONFIG_S3C4510B) -#include <asm-arm/arch-arm720t/s3c4510b.h> -#elif defined(CONFIG_NETARM) +#if defined(CONFIG_NETARM) #include <asm-arm/arch-arm720t/netarm_registers.h> #elif defined(CONFIG_IMPA7) /* include IMPA7 specific hardware file if there was one */ diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-s3c4510b/hardware.h index 6b8c8edd7a..6b8c8edd7a 100644 --- a/include/asm-arm/arch-arm720t/s3c4510b.h +++ b/include/asm-arm/arch-s3c4510b/hardware.h diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index 0977bee35d..b8afc172c5 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -44,7 +44,6 @@ #define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */ #define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ #define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ /*------------------------------------------------------------------------ diff --git a/include/configs/B2.h b/include/configs/B2.h index c77ea1fc47..01b65c515d 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -65,8 +65,12 @@ /* * select serial console configuration */ +#define CONFIG_S3C44B0_SERIAL #define CONFIG_SERIAL1 1 /* we use Serial line 1 */ +#define CONFIG_S3C44B0_I2C +#define CONFIG_RTC_S3C44B0 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -116,8 +120,6 @@ #define CONFIG_SYS_MEMTEST_START 0x0C400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x0c700000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* 1 kHz */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index db9c17df91..45ff2f7dbc 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -50,7 +50,6 @@ #define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/ #define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ #define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ /*------------------------------------------------------------------------ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index 3bd270cdf2..ae567a32b3 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -48,7 +48,6 @@ #define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/ #define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */ #define CONFIG_SYS_HZ 1000 /* 1 msec time tick */ -#undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ /*------------------------------------------------------------------------ diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index 1dd6e573d2..4729464f21 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -129,8 +129,6 @@ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } -#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h index 45e6a58d99..05f6d9fc1a 100644 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -59,6 +59,7 @@ /* * select serial console configuration */ +#define CONFIG_LPC2292_SERIAL #define CONFIG_SERIAL1 1 /* we use Serial line 1 */ /* allow to overwrite serial and ethaddr */ @@ -139,8 +140,6 @@ #define CONFIG_SYS_MEMTEST_START 0x81800000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x83000000 /* 24 MB in SRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ /* for uClinux img is here*/ diff --git a/include/configs/SX1.h b/include/configs/SX1.h index 78c5152e6f..caa6592f7a 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -133,16 +133,14 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. * This time is further subdivided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index d9bcf6b7ae..5e614fd8e8 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -117,6 +117,7 @@ /* * select serial console configuration */ +#define CONFIG_S3C24X0_SERIAL #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ /************************************************************ @@ -172,9 +173,6 @@ #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */ - -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - /* we configure PWM Timer 4 to 1us ~ 1MHz */ /*#define CONFIG_SYS_HZ 1000000 */ #define CONFIG_SYS_HZ 1562500 diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 51d0a0a6ac..ceef76eeaf 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -131,8 +131,6 @@ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE {9600} -#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index ca1a9d4a77..11e063010b 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -139,8 +139,6 @@ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE {9600} -#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */ diff --git a/include/configs/actux1.h b/include/configs/actux1.h index adbc39951c..91f6ff03f9 100644 --- a/include/configs/actux1.h +++ b/include/configs/actux1.h @@ -95,8 +95,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* everything, incl board info, in Hz */ -#undef CONFIG_SYS_CLKS_IN_HZ /* spec says 66.666 MHz, but it appears to be 33 */ #define CONFIG_SYS_HZ 3333333 diff --git a/include/configs/actux2.h b/include/configs/actux2.h index 4c579ebe2f..b936938359 100644 --- a/include/configs/actux2.h +++ b/include/configs/actux2.h @@ -86,8 +86,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* everything, incl board info, in Hz */ -#undef CONFIG_SYS_CLKS_IN_HZ /* spec says 66.666 MHz, but it appears to be 33 */ #define CONFIG_SYS_HZ 3333333 diff --git a/include/configs/actux3.h b/include/configs/actux3.h index 694f52254a..f5ee899102 100644 --- a/include/configs/actux3.h +++ b/include/configs/actux3.h @@ -84,8 +84,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* everything, incl board info, in Hz */ -#undef CONFIG_SYS_CLKS_IN_HZ /* spec says 66.666 MHz, but it appears to be 33 */ #define CONFIG_SYS_HZ 3333333 diff --git a/include/configs/actux4.h b/include/configs/actux4.h index cdc9956725..8d70a268ce 100644 --- a/include/configs/actux4.h +++ b/include/configs/actux4.h @@ -83,8 +83,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 #define CONFIG_SYS_MEMTEST_END 0x00800000 -/* everything, incl board info, in Hz */ -#undef CONFIG_SYS_CLKS_IN_HZ /* spec says 66.666 MHz, but it appears to be 33 */ #define CONFIG_SYS_HZ 3333333 diff --git a/include/configs/apollon.h b/include/configs/apollon.h index f83dd9c243..04da083e69 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -196,7 +196,6 @@ #define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ /* default load address */ #define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) @@ -204,11 +203,9 @@ * or by 32KHz clk, or from external sig. This rate is divided by a local * divisor. */ -#define V_PVT 7 /* use with 12MHz/128 */ - #define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index 5a4ceaf69f..7ba5e174e2 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -64,6 +64,7 @@ /* * select serial console configuration */ +#define CONFIG_CLPS7111_SERIAL #define CONFIG_SERIAL1 1 /* we use Serial line 1 */ /* allow to overwrite serial and ethaddr */ @@ -105,8 +106,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/ #define CONFIG_SYS_HZ 2000 /* decrementer freq: 2 kHz */ diff --git a/include/configs/assabet.h b/include/configs/assabet.h index 024fa207e2..a6c442b51a 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -57,6 +57,7 @@ /* * select serial console configuration */ +#define CONFIG_SA1100_SERIAL #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on Intel Assabet */ /* allow to overwrite serial and ethaddr */ @@ -105,8 +106,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ - #define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */ #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index f19374e30c..751e03c13f 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -113,8 +113,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ - #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index ce36a24261..7ea1a46033 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -53,6 +53,7 @@ * select serial console configuration */ #define CONFIG_ENV_IS_NOWHERE +#define CONFIG_KS8695_SERIAL #define CONFIG_SERIAL1 #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 @@ -93,8 +94,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ #define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index 02cb1efd0f..ea374da86e 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -53,6 +53,7 @@ * select serial console configuration */ #define CONFIG_ENV_IS_NOWHERE +#define CONFIG_KS8695_SERIAL #define CONFIG_SERIAL1 #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 @@ -93,8 +94,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ #define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 5131175045..850d93b03e 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -99,8 +99,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/csb226.h b/include/configs/csb226.h index d65c14a672..d9f85f01ee 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -124,8 +124,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ /* RS: where is this documented? */ /* RS: is this where U-Boot is */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 5d3b09aa3c..204aea0e82 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -140,7 +140,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index a33efde9fe..9b3a11c1ac 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -139,7 +139,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */ #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 667c0d882e..b43beaa03e 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -112,6 +112,7 @@ /* Flash & Environment */ /*=====================*/ #ifdef CONFIG_SYS_USE_NAND +#define CONFIG_NAND_DAVINCI #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 22d3808a3d..2c97a00167 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -81,6 +81,7 @@ /*=====================*/ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH +#define CONFIG_NAND_DAVINCI #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE SZ_128K diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 875bab6f7d..9354c2ffb0 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -77,6 +77,7 @@ /* Flash & Environment */ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH +#define CONFIG_NAND_DAVINCI #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE SZ_128K diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 47ab27a870..0865d0d33b 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -112,6 +112,7 @@ /* Flash & Environment */ /*=====================*/ #ifdef CONFIG_SYS_USE_NAND +#define CONFIG_NAND_DAVINCI #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ diff --git a/include/configs/delta.h b/include/configs/delta.h index 001b48a7e7..f5508b7740 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -166,8 +166,6 @@ #define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index e329fd3a02..8f615bdb84 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -59,6 +59,7 @@ /* * select serial console configuration */ +#define CONFIG_SA1100_SERIAL #define CONFIG_SERIAL1 1 /* we use SERIAL 1 */ /* allow to overwrite serial and ethaddr */ @@ -109,8 +110,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xc0200000 /* default load address */ #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 84e1aefe1f..f7e6608baa 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -116,8 +116,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h index 322a3ca41a..630fff3903 100644 --- a/include/configs/ep7312.h +++ b/include/configs/ep7312.h @@ -55,6 +55,7 @@ /* * select serial console configuration */ +#define CONFIG_CLPS7111_SERIAL #define CONFIG_SERIAL1 1 /* we use Serial line 1 */ /* allow to overwrite serial and ethaddr */ @@ -107,8 +108,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xc0500000 /* default load address */ #define CONFIG_SYS_HZ 2000 /* decrementer freq: 2 kHz */ diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index cbaae62059..ffc9408bc8 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -122,8 +122,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00780000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00000000 /* default load address */ #define CONFIG_SYS_SYS_CLK_FREQ 50000000 /* CPU freq: 50 MHz */ diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index c0b3ab91e4..77d45783c3 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -70,6 +70,7 @@ /* * select serial console configuration */ +#define CONFIG_SA1100_SERIAL #define CONFIG_SERIAL3 1 /* we use SERIAL 3 on ADS GCPlus */ /* allow to overwrite serial and ethaddr */ @@ -118,8 +119,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */ #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 2dacfb6e07..284672b338 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -271,8 +271,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ -#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/impa7.h b/include/configs/impa7.h index a3d023f630..c7001cc7de 100644 --- a/include/configs/impa7.h +++ b/include/configs/impa7.h @@ -54,6 +54,7 @@ /* * select serial console configuration */ +#define CONFIG_CLPS7111_SERIAL #define CONFIG_SERIAL1 1 /* we use Serial line 1 */ /* allow to overwrite serial and ethaddr */ @@ -106,8 +107,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* default load address */ #define CONFIG_SYS_HZ 2000 /* decrementer freq: 2 kHz */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 043ae2f364..895998adf4 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -115,8 +115,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 6ce3b4dc01..9231e64039 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -102,7 +102,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ /*----------------------------------------------------------------------- diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 5b4747a575..b4219d03e1 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -121,7 +121,6 @@ SIB at Block62 End Block62 address 0x24f80000 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ /*----------------------------------------------------------------------- diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index 70f3987365..768e8366bd 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -104,8 +104,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ #define CONFIG_SYS_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 193008e0ef..75707e597d 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -115,7 +115,6 @@ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* valid baudrates */ diff --git a/include/configs/lart.h b/include/configs/lart.h index 38b8e75f45..e34ec222b8 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -52,6 +52,7 @@ /* * select serial console configuration */ +#define CONFIG_SA1100_SERIAL #define CONFIG_SERIAL3 1 /* we use SERIAL 3 on LART */ /* allow to overwrite serial and ethaddr */ @@ -102,8 +103,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xc8000000 /* default load address */ #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ diff --git a/include/configs/logodl.h b/include/configs/logodl.h index cd105da313..9afa800139 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -108,8 +108,6 @@ #define CONFIG_SYS_MEMTEST_START 0x08000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0800ffff /* 64 KiB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index 563d35b20c..1515038793 100644 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -59,6 +59,7 @@ /* * select serial console configuration */ +#define CONFIG_LPC2292_SERIAL #define CONFIG_SERIAL1 1 /* we use Serial line 1 */ /* allow to overwrite serial and ethaddr */ @@ -106,8 +107,6 @@ #define CONFIG_SYS_MEMTEST_START 0x40000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00040000 /* default load address for */ /* armadillo: kernel img is here*/ diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h index 575f2a1c5e..b1bd74fc6f 100644 --- a/include/configs/lpd7a400.h +++ b/include/configs/lpd7a400.h @@ -99,8 +99,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0300000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xc0f00000 /* default load address */ /* valid baudrates */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h index 3e726a01de..b197674d47 100644 --- a/include/configs/lpd7a404.h +++ b/include/configs/lpd7a404.h @@ -99,8 +99,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0300000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0500000 /* 2 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xc0f00000 /* default load address */ /* valid baudrates */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 69774d7467..a4b430bbc5 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -122,8 +122,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h index 27213a8d8d..74bab5fc4c 100644 --- a/include/configs/modnet50.h +++ b/include/configs/modnet50.h @@ -56,6 +56,7 @@ /* * select serial console configuration */ +#define CONFIG_NETARM_SERIAL #define CONFIG_SERIAL1 1 /* we use Serial line 1 */ /* allow to overwrite serial and ethaddr */ @@ -111,8 +112,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00500000 /* default load address */ #define CONFIG_SYS_HZ 900 /* decrementer freq: 2 kHz */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index f136b0ca8c..12e567bf7d 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -40,6 +40,7 @@ /* * Select serial console configuration */ +#define CONFIG_IMX_SERIAL #define CONFIG_IMX_SERIAL1 /* internal uart 1 */ /* #define _CONFIG_UART2 */ /* internal uart 2 */ /* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ @@ -133,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */ /*#define CONFIG_SYS_HZ 1000 */ #define CONFIG_SYS_HZ 3686400 diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index a19eb78409..431e6695e3 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -80,8 +80,6 @@ #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ #define CONFIG_SYS_MEMTEST_END 0x08F00000 -#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */ - #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ @@ -291,11 +289,12 @@ 0x000b00b ->3<- -> 64MHz/4=16MHz */ #ifdef _CONFIG_UART1 +#define CONFIG_IMX_SERIAL #define CONFIG_IMX_SERIAL1 #elif defined _CONFIG_UART2 +#define CONFIG_IMX_SERIAL #define CONFIG_IMX_SERIAL2 #elif defined _CONFIG_UART3 | defined _CONFIG_UART4 -#define CONFIG_IMX_SERIAL_NONE #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 3686400 diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 0b38549dff..39560de3c5 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -59,16 +59,6 @@ #define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -/* - * FLASH organization - */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define PHYS_FLASH_1_SIZE (1 * 1024 * 1024) -#define CONFIG_SYS_MAX_FLASH_SECT 19 -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* in ticks */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) - #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) @@ -106,10 +96,28 @@ #define CONFIG_DRIVER_SMC91111 #define CONFIG_SMC91111_BASE 0x04000300 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 19 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) #define NAND_ALLOW_ERASE_ALL 1 +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_DRIVER_OMAP1510_I2C + +#define CONFIG_RTC_DS1307 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 @@ -133,6 +141,7 @@ */ #define CONFIG_CMD_BDI #define CONFIG_CMD_BOOTD +#define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH @@ -211,16 +220,14 @@ #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \ (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE) -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */ /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. * This time is further subdivided by a local divisor. */ #define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(pvt+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) #define OMAP5910_DPLL_DIV 1 #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h index 543780d77f..6d7b94f9c9 100644 --- a/include/configs/nmdk8815.h +++ b/include/configs/nmdk8815.h @@ -96,7 +96,6 @@ /* timing informazion */ #define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */ #define CONFIG_SYS_TIMERBASE 0x101E2000 -#undef CONFIG_SYS_CLKS_IN_HZ /* serial port (PL011) configuration */ #define CONFIG_PL011_SERIAL diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h index b22c33cc80..79dcd647c2 100644 --- a/include/configs/ns9750dev.h +++ b/include/configs/ns9750dev.h @@ -122,8 +122,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */ #define CONFIG_SYS_HZ (CPU_CLK_FREQ/64) diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index c7d1b6c039..6c1c5ec0d7 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -130,16 +130,14 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. * This time is further subdivided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h index e2a63607c0..42e0198316 100644 --- a/include/configs/omap1610h2.h +++ b/include/configs/omap1610h2.h @@ -125,16 +125,14 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by * DPLL1. This time is further subdivided by a local divisor. */ #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h index 5dcfce1592..22c873e0ca 100644 --- a/include/configs/omap1610inn.h +++ b/include/configs/omap1610inn.h @@ -130,16 +130,14 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by * DPLL1. This time is further subdivided by a local divisor. */ #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 983b5f2517..331bf45305 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -216,22 +216,20 @@ #define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ #define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ #ifdef CONFIG_APTIX -#define V_PVT 3 +#define V_PTV 3 #else -#define V_PVT 7 /* use with 12MHz/128 */ +#define V_PTV 7 /* use with 12MHz/128 */ #endif -#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 +#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0f9344b0c4..7db1eb754b 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -219,8 +219,6 @@ #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ /* load address */ @@ -228,11 +226,9 @@ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index f4498a9bcc..2f532d5929 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -212,9 +212,6 @@ #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ - /* in Hz */ - #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ /* address */ @@ -222,11 +219,9 @@ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index dee0417de9..0c32100a0a 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -206,9 +206,6 @@ #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ - /* in Hz */ - #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ /* address */ @@ -216,11 +213,9 @@ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 00c0374644..fb4e50dbdb 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -208,9 +208,6 @@ #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ - /* in Hz */ - #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ /* address */ @@ -218,11 +215,9 @@ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index f8ae163947..883234a505 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -216,8 +216,6 @@ #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ /* load address */ @@ -225,11 +223,9 @@ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 - #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index 63cd9c6b76..d0ce9dc915 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -134,16 +134,14 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by * DPLL1. This time is further subdivided by a local divisor. */ #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h index 166d592ccd..32a9b2397b 100644 --- a/include/configs/omap730p2.h +++ b/include/configs/omap730p2.h @@ -142,18 +142,15 @@ #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ /* The OMAP730 has 3 general purpose MPU timers, they can be driven by * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a * local divisor. */ - -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 4da401f46b..edaa81b59b 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index 59741a98f9..ab9ea4fdee 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -122,8 +122,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index d1c2c650c2..5e2e7cfcc8 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -236,8 +236,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index bf4a14e004..af0018772c 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -70,6 +70,7 @@ /* * select serial console configuration */ +#define CONFIG_S3C24X0_SERIAL #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */ /************************************************************ @@ -135,8 +136,6 @@ #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ @@ -200,6 +199,7 @@ * NAND flash settings */ #if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_S3C2410 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 960350c6c6..3e2bb02a46 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -116,8 +116,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index 2445a34168..d42ef84216 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -117,8 +117,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index 5971df72fc..2f166c9d86 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -29,6 +29,7 @@ #define CONFIG_SCB9328 1 /* on a scb9328tronix board */ #undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ +#define CONFIG_IMX_SERIAL #define CONFIG_IMX_SERIAL1 /* * Select serial console configuration @@ -86,8 +87,6 @@ #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ #define CONFIG_SYS_MEMTEST_END 0x08F00000 -#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */ - #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ diff --git a/include/configs/shannon.h b/include/configs/shannon.h index 75ba34cdb8..c8b0b161d8 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -59,6 +59,7 @@ /* * select serial console configuration */ +#define CONFIG_SA1100_SERIAL #define CONFIG_SERIAL3 1 /* we use SERIAL 3 */ /* allow to overwrite serial and ethaddr */ @@ -105,8 +106,6 @@ #define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xd0000000 /* default load address */ #define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index 6388be4d49..ffdf21768b 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -63,6 +63,7 @@ /* * select serial console configuration */ +#define CONFIG_S3C24X0_SERIAL #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SAMSUNG */ #undef CONFIG_HWFLOW /* include RTS/CTS flow control support */ @@ -137,8 +138,6 @@ #define CONFIG_SYS_MEMTEST_START 0x0c000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0e000000 /* 32 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x0cf00000 /* default load address */ /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index ecd958b557..fb437069da 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -60,6 +60,7 @@ /* * select serial console configuration */ +#define CONFIG_S3C24X0_SERIAL #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ /************************************************************ @@ -120,8 +121,6 @@ #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 06d6a88592..d3cf6e58f4 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -288,6 +288,7 @@ #if !defined(CONFIG_ENABLE_MMU) #define CONFIG_CMD_USB 1 +#define CONFIG_USB_S3C64XX #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400" diff --git a/include/configs/trab.h b/include/configs/trab.h index 8f13c35614..520fe368de 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -111,6 +111,7 @@ /* * select serial console configuration */ +#define CONFIG_S3C24X0_SERIAL #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */ #define CONFIG_HWFLOW /* include RTS/CTS flow control support */ @@ -316,8 +317,6 @@ #define CONFIG_SYS_MEMTEST_START 0x0C000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0D000000 /* 16 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0x0CF00000 /* default load address */ #ifdef CONFIG_TRAB_50MHZ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 70e5ce97b0..c2744b5eba 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -163,8 +163,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 852becb36d..8f6383b051 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -144,7 +144,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ /*----------------------------------------------------------------------- diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index cadd90633d..3f97843722 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -210,14 +210,12 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1. * This time is further subdivided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE -#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) +#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) #define OMAP5910_DPLL_DIV 1 #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \ diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index d0afd29c32..717577f398 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -79,8 +79,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest test area */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 -#undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */ - #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 250247c5cc..086ca69c10 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -134,8 +134,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 8e9d5ab7b3..922eb2c6b0 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -117,8 +117,6 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index 5d13f9682e..cad414c1d9 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -139,7 +139,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ #define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 6febeeafab..064740d3cc 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -139,8 +139,6 @@ #define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */ -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ #define CONFIG_SYS_HZ 1000 |
