diff options
514 files changed, 18842 insertions, 4029 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e55893b52c..fd0c65c8d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21,6 +21,8 @@ Poonam Aggrwal <poonam.aggrwal@freescale.com> P2020RDB P2020 + BSC9131RDB BSC9131 + Greg Allen <gallen@arlut.utexas.edu> UTX8245 MPC8245 @@ -740,6 +742,9 @@ Sergey Lapin <slapin@ossfans.org> Valentin Longchamp <valentin.longchamp@keymile.com> km_kirkwood ARM926EJS (Kirkwood SoC) + kmnusa ARM926EJS (Kirkwood SoC) + mgcoge3un ARM926EJS (Kirkwood SoC) + kmcoge5un ARM926EJS (Kirkwood SoC) portl2 ARM926EJS (Kirkwood SoC) Nishanth Menon <nm@ti.com> @@ -808,6 +813,7 @@ Thierry Reding <thierry.reding@avionic-design.de> plutux Tegra2 (ARM7 & A9 Dual Core) medcom Tegra2 (ARM7 & A9 Dual Core) + tec Tegra2 (ARM7 & A9 Dual Core) Christian Riesch <christian.riesch@omicron.at> Manfred Rudigier <manfred.rudigier@omicron.at> @@ -845,12 +851,12 @@ Steve Sakoman <sakoman@gmail.com> Jens Scharsig <esw@bus-elektronik.de> eb_cpux9k2 ARM920T (AT91RM9200 SoC) + vl_ma2sc ARM926EJS (AT91SAM9263 SoC) Heiko Schocher <hs@denx.de> enbw_cmc ARM926EJS (AM1808 SoC) magnesium i.MX27 - mgcoge3un ARM926EJS (Kirkwood SoC) Michael Schwingen <michael@schwingen.org> @@ -904,6 +910,11 @@ Prafulla Wadaskar <prafulla@marvell.com> rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Michael Walle <michael@walle.cc> + + lschlv2 ARM926EJS (Kirkwood SoC) + lsxhl ARM926EJS (Kirkwood SoC) + Tom Warren <twarren@nvidia.com> harmony Tegra2 (ARM7 & A9 Dual Core) @@ -914,6 +925,8 @@ Stephen Warren <swarren@nvidia.com> ventana Tegra2 (ARM7 & A9 Dual Core) paz00 Tegra2 (ARM7 & A9 Dual Core) + trimslice Tegra2 (ARM7 & A9 Dual Core) + whistler Tegra2 (ARM7 & A9 Dual Core) Thomas Weber <weber@corscience.de> @@ -22,8 +22,8 @@ # VERSION = 2012 -PATCHLEVEL = 04 -SUBLEVEL = 01 +PATCHLEVEL = 07 +SUBLEVEL = EXTRAVERSION = ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) @@ -456,6 +456,22 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \ -o $(obj)u-boot.sb +# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. +# Both images are created using mkimage (crc etc), so that the ROM +# bootloader can check its integrity. Padding needs to be done to the +# SPL image (with mkimage header) and not the binary. Otherwise the resulting image +# which is loaded/copied by the ROM bootloader to SRAM doesn't fit. +# The resulting image containing both U-Boot images is called u-boot.spr +$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin + $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \ + -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img + tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \ + of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null + dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \ + conv=notrunc 2>/dev/null + cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@ + ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ @@ -601,7 +617,7 @@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \ $(obj)include/generated/asm-offsets.h: $(obj)include/autoconf.mk.dep \ $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s - @echo Generating $@ + @$(XECHO) Generating $@ tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@ $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/autoconf.mk.dep @@ -775,7 +791,8 @@ clobber: tidy @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb @rm -f $(obj)u-boot.sb - @rm -f $(obj)tools/inca-swap-bytes + @rm -f $(obj)u-boot.spr + @rm -f $(obj)tools/xway-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @@ -374,6 +374,15 @@ The following options need to be configured: Defines the string to utilize when trying to match PCIe device tree nodes for the given platform. + CONFIG_SYS_PPC_E500_DEBUG_TLB + + Enables a temporary TLB entry to be used during boot to work + around limitations in e500v1 and e500v2 external debugger + support. This reduces the portions of the boot code where + breakpoints and single stepping do not work. The value of this + symbol should be set to the TLB1 entry to be used for this + purpose. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN @@ -2140,6 +2149,13 @@ The following options need to be configured: Timeout waiting for an ARP reply in milliseconds. + CONFIG_NFS_TIMEOUT + + Timeout in milliseconds used in NFS protocol. + If you encounter "ERROR: Cannot umount" in nfs command, + try longer timeout such as + #define CONFIG_NFS_TIMEOUT 10000UL + - Command Interpreter: CONFIG_AUTO_COMPLETE @@ -2220,6 +2236,20 @@ The following options need to be configured: the environment like the "source" command or the boot command first. + CONFIG_ENV_VARS_UBOOT_CONFIG + + Define this in order to add variables describing the + U-Boot build configuration to the default environment. + These will be named arch, cpu, board, vendor, and soc. + + Enabling this option will cause the following to be defined: + + - CONFIG_SYS_ARCH + - CONFIG_SYS_CPU + - CONFIG_SYS_BOARD + - CONFIG_SYS_VENDOR + - CONFIG_SYS_SOC + - DataFlash Support: CONFIG_HAS_DATAFLASH diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c index f72bab6693..b98e3d9fac 100644 --- a/arch/arm/cpu/arm1136/cpu.c +++ b/arch/arm/cpu/arm1136/cpu.c @@ -95,7 +95,7 @@ void flush_dcache_all(void) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } -static inline int bad_cache_range(unsigned long start, unsigned long stop) +static int check_cache_range(unsigned long start, unsigned long stop) { int ok = 1; @@ -114,7 +114,7 @@ static inline int bad_cache_range(unsigned long start, unsigned long stop) void invalidate_dcache_range(unsigned long start, unsigned long stop) { - if (bad_cache_range(start, stop)) + if (!check_cache_range(start, stop)) return; while (start < stop) { @@ -125,7 +125,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) void flush_dcache_range(unsigned long start, unsigned long stop) { - if (bad_cache_range(start, stop)) + if (!check_cache_range(start, stop)) return; while (start < stop) { diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index c0db96cb15..2483c63efb 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -251,10 +251,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: #endif /* #ifndef CONFIG_SPL_BUILD */ /* diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 848144a851..d61364109e 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -351,11 +351,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l - + b clbss_l +clbss_e: #ifndef CONFIG_NAND_SPL bl coloured_LED_init bl red_led_on diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 540e3c2f72..3b97e804a6 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -228,10 +228,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: bl coloured_LED_init bl red_led_on diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 8c5612c31e..9b8604e907 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -271,10 +271,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: bl coloured_LED_init bl red_led_on diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index dbb93ef09f..1a54416866 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -265,10 +265,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: bl coloured_LED_init bl red_led_on diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S index 5b39484501..0e45426fbc 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S @@ -523,9 +523,8 @@ VTPLock: ldr r6, DDRVTPR ldr r7, [r6] - and r7, r7, $0x1f - and r8, r7, $0x3e0 - orr r8, r7, r8 + mov r8, r7, LSL #32-10 + mov r8, r8, LSR #32-10 /* grab low 10 bits */ ldr r7, VTP_RECAL orr r8, r7, r8 ldr r7, VTP_EN @@ -644,7 +643,7 @@ VTP_LOCK_COUNT: VTP_MASK: .word 0xffffdfff VTP_RECAL: - .word 0x40000 + .word 0x08000 VTP_EN: .word 0x02000 CFGTEST: diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 3da6c98d11..03eb2de520 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -31,7 +31,7 @@ static u32 kirkwood_variant(void) #define MPP_CTRL(i) (KW_MPP_BASE + (i* 4)) #define MPP_NR_REGS (1 + MPP_MAX/8) -void kirkwood_mpp_conf(u32 *mpp_list) +void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save) { u32 mpp_ctrl[MPP_NR_REGS]; unsigned int variant_mask; @@ -52,6 +52,7 @@ void kirkwood_mpp_conf(u32 *mpp_list) while (*mpp_list) { unsigned int num = MPP_NUM(*mpp_list); unsigned int sel = MPP_SEL(*mpp_list); + unsigned int sel_save; int shift; if (num > MPP_MAX) { @@ -66,6 +67,13 @@ void kirkwood_mpp_conf(u32 *mpp_list) } shift = (num & 7) << 2; + + if (mpp_save) { + sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf; + *mpp_save = num | (sel_save << 8) | variant_mask; + mpp_save++; + } + mpp_ctrl[num / 8] &= ~(0xf << shift); mpp_ctrl[num / 8] |= sel << shift; diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index a82ff2564b..ff25772099 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -153,7 +153,6 @@ int arch_misc_init(void) } #endif -#ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { struct mx28_clkctrl_regs *clkctrl_regs = @@ -187,7 +186,6 @@ int arch_cpu_init(void) return 0; } -#endif #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index 9fa5d29e6c..e17a4d7c7f 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -82,10 +82,18 @@ uint32_t dram_vals[] = { 0x00000000, 0x00010001 }; +void __mx28_adjust_memory_params(uint32_t *dram_vals) +{ +} +void mx28_adjust_memory_params(uint32_t *dram_vals) + __attribute__((weak, alias("__mx28_adjust_memory_params"))); + void init_m28_200mhz_ddr2(void) { int i; + mx28_adjust_memory_params(dram_vals); + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); } diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index f32ec4ccf3..d06f03d080 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -25,16 +25,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := reset.o \ +COBJS-y := cpu.o \ + reset.o \ timer.o -SOBJS := -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o spl_boot.o +COBJS-$(CONFIG_SPEAR600) += spear600.o +COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o +COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o +COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o +COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o +endif -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +SRCS := $(START:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c new file mode 100644 index 0000000000..e299de3137 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> + +int arch_cpu_init(void) +{ + struct misc_regs *const misc_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 periph1_clken, periph_clk_cfg; + + periph1_clken = readl(&misc_p->periph1_clken); + +#if defined(CONFIG_SPEAR3XX) + periph1_clken |= MISC_GPT2ENB; +#elif defined(CONFIG_SPEAR600) + periph1_clken |= MISC_GPT3ENB; +#endif + +#if defined(CONFIG_PL011_SERIAL) + periph1_clken |= MISC_UART0ENB; + + periph_clk_cfg = readl(&misc_p->periph_clk_cfg); + periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK; + periph_clk_cfg |= CONFIG_SPEAR_UART48M; + writel(periph_clk_cfg, &misc_p->periph_clk_cfg); +#endif +#if defined(CONFIG_DESIGNWARE_ETH) + periph1_clken |= MISC_ETHENB; +#endif +#if defined(CONFIG_DW_UDC) + periph1_clken |= MISC_USBDENB; +#endif +#if defined(CONFIG_DW_I2C) + periph1_clken |= MISC_I2CENB; +#endif +#if defined(CONFIG_ST_SMI) + periph1_clken |= MISC_SMIENB; +#endif +#if defined(CONFIG_NAND_FSMC) + periph1_clken |= MISC_FSMCENB; +#endif + + writel(periph1_clken, &misc_p->periph1_clken); + return 0; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ +#ifdef CONFIG_SPEAR300 + printf("CPU: SPEAr300\n"); +#elif defined(CONFIG_SPEAR310) + printf("CPU: SPEAr310\n"); +#elif defined(CONFIG_SPEAR320) + printf("CPU: SPEAr320\n"); +#elif defined(CONFIG_SPEAR600) + printf("CPU: SPEAr600\n"); +#else +#error CPU not supported in spear platform +#endif + return 0; +} +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c new file mode 100644 index 0000000000..ff52131b09 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spear600.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2000-2009 + * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/hardware.h> +#include <asm/io.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_defs.h> + +#define FALSE 0 +#define TRUE (!FALSE) + +static void sel_1v8(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddr1v8, ddr2v5; + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000003; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000010; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) + ; +} + +static void sel_2v5(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddr1v8, ddr2v5; + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000003; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000010; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) + ; +} + +/* + * plat_ddr_init: + */ +void plat_ddr_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 ddrpad; + u32 core3v3, ddr1v8, ddr2v5; + + /* DDR pad register configurations */ + ddrpad = readl(&misc_p->ddr_pad); + ddrpad &= ~DDR_PAD_CNF_MSK; + +#if (CONFIG_DDR_HCLK) + ddrpad |= 0xEAAB; +#elif (CONFIG_DDR_2HCLK) + ddrpad |= 0xEAAD; +#elif (CONFIG_DDR_PLL2) + ddrpad |= 0xEAAD; +#endif + writel(ddrpad, &misc_p->ddr_pad); + + /* Compensation register configurations */ + core3v3 = readl(&misc_p->core_3v3_compensation); + core3v3 &= 0x8080ffe0; + core3v3 |= 0x78000002; + writel(core3v3, &misc_p->core_3v3_compensation); + + ddr1v8 = readl(&misc_p->ddr_1v8_compensation); + ddr1v8 &= 0x8080ffc0; + ddr1v8 |= 0x78000004; + writel(ddr1v8, &misc_p->ddr_1v8_compensation); + + ddr2v5 = readl(&misc_p->ddr_2v5_compensation); + ddr2v5 &= 0x8080ffc0; + ddr2v5 |= 0x78000004; + writel(ddr2v5, &misc_p->ddr_2v5_compensation); + + if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) { + /* Software memory configuration */ + if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL) + sel_1v8(); + else + sel_2v5(); + } else { + /* Hardware memory configuration */ + if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE) + sel_1v8(); + else + sel_2v5(); + } +} + +/* + * soc_init: + */ +void soc_init(void) +{ + /* Nothing to be done for SPEAr600 */ +} + +/* + * xxx_boot_selected: + * + * return TRUE if the particular booting option is selected + * return FALSE otherwise + */ +static u32 read_bootstrap(void) +{ + return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT) + & CONFIG_SPEAR_BOOTSTRAPMASK; +} + +int snor_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (SNOR_BOOT_SUPPORTED) { + /* Check whether SNOR boot is selected */ + if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) == + CONFIG_SPEAR_ONLYSNORBOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND8BOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND16BOOT) + return TRUE; + } + + return FALSE; +} + +int nand_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (NAND_BOOT_SUPPORTED) { + /* Check whether NAND boot is selected */ + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND8BOOT) + return TRUE; + + if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == + CONFIG_SPEAR_NORNAND16BOOT) + return TRUE; + } + + return FALSE; +} + +int pnor_boot_selected(void) +{ + /* Parallel NOR boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int usb_boot_selected(void) +{ + u32 bootstrap = read_bootstrap(); + + if (USB_BOOT_SUPPORTED) { + /* Check whether USB boot is selected */ + if (!(bootstrap & CONFIG_SPEAR_USBBOOT)) + return TRUE; + } + + return FALSE; +} + +int tftp_boot_selected(void) +{ + /* TFTP boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int uart_boot_selected(void) +{ + /* UART boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int spi_boot_selected(void) +{ + /* SPI boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int i2c_boot_selected(void) +{ + /* I2C boot is not selected in any SPEAr600 revision */ + return FALSE; +} + +int mmc_boot_selected(void) +{ + return FALSE; +} + +void plat_late_init(void) +{ + spear_late_init(); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c new file mode 100644 index 0000000000..48e6efbc47 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_syscntl.h> + +inline void hang(void) +{ + serial_puts("### ERROR ### Please RESET the board ###\n"); + for (;;) + ; +} + +static void ddr_clock_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 clkenb, ddrpll; + + clkenb = readl(&misc_p->periph1_clken); + clkenb &= ~PERIPH_MPMCMSK; + clkenb |= PERIPH_MPMC_WE; + + /* Intentionally done twice */ + writel(clkenb, &misc_p->periph1_clken); + writel(clkenb, &misc_p->periph1_clken); + + ddrpll = readl(&misc_p->pll_ctr_reg); + ddrpll &= ~MEM_CLK_SEL_MSK; +#if (CONFIG_DDR_HCLK) + ddrpll |= MEM_CLK_HCLK; +#elif (CONFIG_DDR_2HCLK) + ddrpll |= MEM_CLK_2HCLK; +#elif (CONFIG_DDR_PLL2) + ddrpll |= MEM_CLK_PLL2; +#else +#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)" +#endif + writel(ddrpll, &misc_p->pll_ctr_reg); + + writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN, + &misc_p->periph1_clken); +} + +static void mpmc_init_values(void) +{ + u32 i; + u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; + u32 *mpmc_val_p = &mpmc_conf_vals[0]; + + for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++) + writel(*mpmc_val_p, mpmc_reg_p); + + mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE; + + /* + * MPMC controller start + * MPMC waiting for DLLLOCKREG high + */ + writel(0x01000100, &mpmc_reg_p[7]); + + while (!(readl(&mpmc_reg_p[3]) & 0x10000)) + ; +} + +static void mpmc_init(void) +{ + /* Clock related settings for DDR */ + ddr_clock_init(); + + /* + * DDR pad register bits are different for different SoCs + * Compensation values are also handled separately + */ + plat_ddr_init(); + + /* Initialize mpmc register values */ + mpmc_init_values(); +} + +static void pll_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Initialize PLLs */ + writel(FREQ_332, &misc_p->pll1_frq); + writel(0x1C0A, &misc_p->pll1_cntl); + writel(0x1C0E, &misc_p->pll1_cntl); + writel(0x1C06, &misc_p->pll1_cntl); + writel(0x1C0E, &misc_p->pll1_cntl); + + writel(FREQ_332, &misc_p->pll2_frq); + writel(0x1C0A, &misc_p->pll2_cntl); + writel(0x1C0E, &misc_p->pll2_cntl); + writel(0x1C06, &misc_p->pll2_cntl); + writel(0x1C0E, &misc_p->pll2_cntl); + + /* wait for pll locks */ + while (!(readl(&misc_p->pll1_cntl) & 0x1)) + ; + while (!(readl(&misc_p->pll2_cntl) & 0x1)) + ; +} + +static void mac_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC), + &misc_p->periph1_clken); + + writel(SYNTH23, &misc_p->gmac_synth_clk); + + switch (get_socrev()) { + case SOC_SPEAR600_AA: + case SOC_SPEAR600_AB: + case SOC_SPEAR600_BA: + case SOC_SPEAR600_BB: + case SOC_SPEAR600_BC: + case SOC_SPEAR600_BD: + writel(0x0, &misc_p->gmac_ctr_reg); + break; + + case SOC_SPEAR300: + case SOC_SPEAR310: + case SOC_SPEAR320: + writel(0x4, &misc_p->gmac_ctr_reg); + break; + } + + writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC, + &misc_p->periph1_clken); + + writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC, + &misc_p->periph1_rst); + writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC), + &misc_p->periph1_rst); +} + +static void sys_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct syscntl_regs *syscntl_p = + (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE; + + /* Set system state to SLOW */ + writel(SLOW, &syscntl_p->scctrl); + writel(PLL_TIM << 3, &syscntl_p->scpllctrl); + + /* Initialize PLLs */ + pll_init(); + + /* + * Ethernet configuration + * To be done only if the tftp boot is not selected already + * Boot code ensures the correct configuration in tftp booting + */ + if (!tftp_boot_selected()) + mac_init(); + + writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg); + writel(0x555, &misc_p->amba_clk_cfg); + + writel(NORMAL, &syscntl_p->scctrl); + + /* Wait for system to switch to normal mode */ + while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK) + != NORMAL) + ; +} + +/* + * get_socrev + * + * Get SoC Revision. + * @return SOC_SPEARXXX + */ +int get_socrev(void) +{ +#if defined(CONFIG_SPEAR600) + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 soc_id = readl(&misc_p->soc_core_id); + u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF; + u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF; + + if ((pri_socid == 'B') && (sec_socid == 'B')) + return SOC_SPEAR600_BB; + else if ((pri_socid == 'B') && (sec_socid == 'C')) + return SOC_SPEAR600_BC; + else if ((pri_socid == 'B') && (sec_socid == 'D')) + return SOC_SPEAR600_BD; + else if (soc_id == 0) + return SOC_SPEAR600_BA; + else + return SOC_SPEAR_NA; +#elif defined(CONFIG_SPEAR300) + return SOC_SPEAR300; +#elif defined(CONFIG_SPEAR310) + return SOC_SPEAR310; +#elif defined(CONFIG_SPEAR320) + return SOC_SPEAR320; +#endif +} + +void lowlevel_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + const char *u_boot_rev = U_BOOT_VERSION; + + /* Initialize PLLs */ + sys_init(); + + /* Initialize UART */ + serial_init(); + + /* Print U-Boot SPL version string */ + serial_puts("\nU-Boot SPL "); + /* Avoid a second "U-Boot" coming from this string */ + u_boot_rev = &u_boot_rev[7]; + serial_puts(u_boot_rev); + serial_puts(" ("); + serial_puts(U_BOOT_DATE); + serial_puts(" - "); + serial_puts(U_BOOT_TIME); + serial_puts(")\n"); + +#if defined(CONFIG_OS_BOOT) + writel(readl(&misc_p->periph1_clken) | PERIPH_UART1, + &misc_p->periph1_clken); +#endif + + /* Enable IPs (release reset) */ + writel(PERIPH_RST_ALL, &misc_p->periph1_rst); + + /* Initialize MPMC */ + serial_puts("Configure DDR\n"); + mpmc_init(); + + /* SoC specific initialization */ + soc_init(); +} + +void spear_late_init(void) +{ + struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + writel(0x80000007, &misc_p->arb_icm_ml1); + writel(0x80000007, &misc_p->arb_icm_ml2); + writel(0x80000007, &misc_p->arb_icm_ml3); + writel(0x80000007, &misc_p->arb_icm_ml4); + writel(0x80000007, &misc_p->arb_icm_ml5); + writel(0x80000007, &misc_p->arb_icm_ml6); + writel(0x80000007, &misc_p->arb_icm_ml7); + writel(0x80000007, &misc_p->arb_icm_ml8); + writel(0x80000007, &misc_p->arb_icm_ml9); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c new file mode 100644 index 0000000000..f2f9a4974e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <image.h> +#include <linux/compiler.h> +#include <asm/io.h> +#include <asm/arch/spr_defs.h> +#include <linux/mtd/st_smi.h> + +static const char kernel_name[] = "Linux"; +static const char loader_name[] = "U-Boot"; + +int image_check_header(image_header_t *hdr, const char *name) +{ + if (image_check_magic(hdr) && + (!strncmp(image_get_name(hdr), name, strlen(name))) && + image_check_hcrc(hdr)) { + return 1; + } + return 0; +} + +int image_check_data(image_header_t *hdr) +{ + if (image_check_dcrc(hdr)) + return 1; + + return 0; +} + +/* + * SNOR (Serial NOR flash) related functions + */ +void snor_init(void) +{ + struct smi_regs *const smicntl = + (struct smi_regs * const)CONFIG_SYS_SMI_BASE; + + /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ + writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, + &smicntl->smi_cr1); +} + +static int snor_image_load(u8 *load_addr, void (**image_p)(void), + const char *image_name) +{ + image_header_t *header; + + /* + * Since calculating the crc in the SNOR flash does not + * work, we copy the image to the destination address + * minus the header size. And point the header to this + * new destination. This will not work for address 0 + * of course. + */ + header = (image_header_t *)load_addr; + memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)), + (const ulong *)load_addr, + image_get_data_size(header) + sizeof(image_header_t)); + header = (image_header_t *)(image_get_load(header) - + sizeof(image_header_t)); + + if (image_check_header(header, image_name)) { + if (image_check_data(header)) { + /* Jump to boot image */ + *image_p = (void *)image_get_load(header); + return 1; + } + } + + return 0; +} + +static void boot_image(void (*image)(void)) +{ + void (*funcp)(void) __noreturn = (void *)image; + + (*funcp)(); +} + +/* + * spl_boot: + * + * All supported booting types of all supported SoCs are listed here. + * Generic readback APIs are provided for each supported booting type + * eg. nand_read_skip_bad + */ +u32 spl_boot(void) +{ + void (*image)(void); + +#ifdef CONFIG_SPEAR_USBTTY + plat_late_init(); + return 1; +#endif + + /* + * All the supported booting devices are listed here. Each of + * the booting type supported by the platform would define the + * macro xxx_BOOT_SUPPORTED to TRUE. + */ + + if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) { + /* SNOR-SMI initialization */ + snor_init(); + + serial_puts("Booting via SNOR\n"); + /* Serial NOR booting */ + if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE, + &image, loader_name)) { + /* Platform related late initialasations */ + plat_late_init(); + + /* Jump to boot image */ + serial_puts("Jumping to U-Boot\n"); + boot_image(image); + return 1; + } + } + + if (NAND_BOOT_SUPPORTED && nand_boot_selected()) { + /* NAND booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) { + /* PNOR booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) { + /* MMC booting */ + /* Not ported from XLoader to SPL yet */ + return 0; + } + + if (SPI_BOOT_SUPPORTED && spi_boot_selected()) { + /* SPI booting */ + /* Not supported for any platform as of now */ + return 0; + } + + if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) { + /* I2C booting */ + /* Not supported for any platform as of now */ + return 0; + } + + /* + * All booting types without memory are listed as below + * Control has to be returned to BootROM in case of all + * the following booting scenarios + */ + + if (USB_BOOT_SUPPORTED && usb_boot_selected()) { + plat_late_init(); + return 1; + } + + if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) { + plat_late_init(); + return 1; + } + + if (UART_BOOT_SUPPORTED && uart_boot_selected()) { + plat_late_init(); + return 1; + } + + /* Ideally, the control should not reach here. */ + hang(); +} diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c new file mode 100644 index 0000000000..5edc115d10 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_PLL2) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x00000001, + 0x00000000, + 0x01000000, + 0x00000101, + 0x00000001, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, + 0x00000003, + 0x01000201, + 0x06000202, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000404, + 0x02030202, + 0x03000204, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x08080a01, + 0x0000023f, + 0x00040800, + 0x00000000, + 0x00000f02, + 0x00001b1b, + 0x7f000000, + 0x005f0000, + 0x1c040b6a, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x000007ff, + 0x00000000, + 0x47ec00c8, + 0x00c8001f, + 0x00000000, + 0x0000cd98, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00270000, + 0x00250027, + 0x00300000, + 0x008900b7, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c new file mode 100644 index 0000000000..616b86194d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { +#if (CONFIG_DDR_PLL2) + 0x00000001, + 0x00000000, +#elif (CONFIG_DDR_2HCLK) + 0x02020201, + 0x02020202, +#endif + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x01010001, + 0x00000201, + 0x01000101, + 0x06000002, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000405, + 0x03040202, + 0x04000305, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x0a0a0a01, + 0x0000023f, + 0x00050a00, + 0x11000000, + 0x00001302, + 0x00000A0A, + 0x72000000, + 0x00550000, + 0x2b050e86, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000a24, + 0x43C20000, + 0x5b1c00c8, + 0x00c8002e, + 0x00000000, + 0x0001046b, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00210000, + 0x00010021, + 0x00200000, + 0x006c0090, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c new file mode 100644 index 0000000000..b89f77deb0 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c @@ -0,0 +1,130 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { + 0x03030301, + 0x03030303, + 0x01000000, + 0x00000101, + 0x00000001, + 0x01000000, + 0x00010001, + 0x00000100, + 0x00010001, + 0x00000003, + 0x01000201, + 0x06000202, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, + 0x02010106, + 0x03000404, + 0x02020202, + 0x03000203, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x08080a01, + 0x0000023f, + 0x00030600, + 0x00000000, + 0x00000a02, + 0x00001c1c, + 0x7f000000, + 0x005f0000, + 0x12030743, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x0000050e, + 0x00000000, + 0x2d8900c8, + 0x00c80014, + 0x00000000, + 0x00008236, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00400000, + 0x003a0040, + 0x00680000, + 0x00d80120, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c new file mode 100644 index 0000000000..0c39cd1059 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2000-2009 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK) + +const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = { +#if (CONFIG_DDR_PLL2) + 0x00000001, + 0x00000000, +#elif (CONFIG_DDR_2HCLK) + 0x02020201, + 0x02020202, +#endif + 0x01000000, + 0x00000101, + 0x00000101, + 0x01000000, + 0x00010001, + 0x00000100, + 0x01010001, + 0x00000201, + 0x01000101, + 0x06000002, + 0x06060106, + 0x03050502, + 0x03040404, + 0x02020503, +#ifdef CONFIG_X600 + 0x02030206, +#else + 0x02010106, +#endif + 0x03000405, + 0x03040202, + 0x04000305, + 0x0707073f, + 0x07070707, + 0x06060607, + 0x06060606, + 0x05050506, + 0x05050505, + 0x04040405, + 0x04040404, + 0x03030304, + 0x03030303, + 0x02020203, + 0x02020202, + 0x01010102, + 0x01010101, + 0x0a0a0a01, + 0x0000023f, + 0x00050a00, + 0x11000000, + 0x00001302, + 0x00000A0A, +#ifdef CONFIG_X600 + 0x7f000000, + 0x005c0000, +#else + 0x72000000, + 0x00550000, +#endif + 0x2b050e86, + 0x00640064, + 0x00640064, + 0x00640064, + 0x00000064, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00200020, + 0x00000a24, + 0x43C20000, + 0x5b1c00c8, + 0x00c8002e, + 0x00000000, + 0x0001046b, + 0x00000000, + 0x03030100, + 0x03030303, + 0x03030303, + 0x03030303, + 0x00210000, + 0x00010021, + 0x00200000, + 0x006c0090, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x003fffff, + 0x003fffff, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +#endif diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S new file mode 100644 index 0000000000..a103c0f4ab --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/start.S @@ -0,0 +1,122 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> + * Copyright (c) 2003 Kshitij <kshitij@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <config.h> + +.globl _start +_start: + b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: +_software_interrupt: +_prefetch_abort: +_data_abort: +_not_used: +_irq: +_fiq: + .word infinite_loop + +infinite_loop: + b infinite_loop + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * Below are the critical initializations already taken place in BootROM. + * So, these are not taken care in Xloader + * 1. Relocation to RAM + * 2. Initializing stacks + * + ************************************************************************* + */ + +/* + * the actual reset code + */ + +reset: +/* + * Xloader has to return back to BootROM in a few cases. + * eg. Ethernet boot, UART boot, USB boot + * Saving registers for returning back + */ + stmdb sp!, {r0-r12,r14} + bl cpu_init_crit +/* + * Clearing bss area is not done in Xloader. + * BSS area lies in the DDR location which is not yet initialized + * bss is assumed to be uninitialized. + */ + bl spl_boot + ldmia sp!, {r0-r12,pc} + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * enable instruction cache + */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + stmdb sp!, {lr} + bl lowlevel_init /* go setup pll,mux,memory */ + ldmia sp!, {pc} diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds new file mode 100644 index 0000000000..afd3381e16 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/arm926ejs/spear/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } + + _end = .; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 89ba5587e1..b4d1d2dd1c 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -236,10 +236,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - blo clbss_l + b clbss_l +clbss_e: #endif /* diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 2033b362f7..b85e7d4427 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -232,10 +232,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: bl coloured_LED_init bl red_led_on diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 6b7a494d7c..71309a7f47 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -40,6 +40,22 @@ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; #define UART_SMART_IDLE_EN (0x1 << 0x3) #endif +#ifdef CONFIG_SPL_BUILD +/* Initialize timer */ +static void init_timer(void) +{ + /* Reset the Timer */ + writel(0x2, (&timer_base->tscir)); + + /* Wait until the reset is done */ + while (readl(&timer_base->tiocp_cfg) & 1) + ; + + /* Start the Timer */ + writel(0x1, (&timer_base->tclr)); +} +#endif + /* * early system init of muxing and clocks. */ @@ -88,20 +104,6 @@ void s_init(void) enable_mmc0_pin_mux(); } -/* Initialize timer */ -void init_timer(void) -{ - /* Reset the Timer */ - writel(0x2, (&timer_base->tscir)); - - /* Wait until the reset is done */ - while (readl(&timer_base->tiocp_cfg) & 1) - ; - - /* Start the Timer */ - writel(0x1, (&timer_base->tclr)); -} - #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 5407cb68a8..560c084dc9 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -26,6 +26,8 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # supported by more tool-chains PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7) +PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED) # ========================================================================= # diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index 90ec2bd404..9119961d95 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += clock.o power.o soc.o system.o +COBJS += clock.o power.o soc.o system.o pinmux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c new file mode 100644 index 0000000000..d2b7d2cba7 --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2012 Samsung Electronics. + * Abhilash Kesavan <a.kesavan@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/sromc.h> + +static void exynos5_uart_config(int peripheral) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + +static int exynos5_mmc_config(int peripheral, int flags) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank, *bank_ext; + int i; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio1->c0; + bank_ext = &gpio1->c1; + break; + case PERIPH_ID_SDMMC1: + bank = &gpio1->c1; + bank_ext = NULL; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio1->c2; + bank_ext = &gpio1->c3; + break; + case PERIPH_ID_SDMMC3: + bank = &gpio1->c3; + bank_ext = NULL; + break; + } + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + return 0; +} + +static void exynos5_sromc_config(int flags) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + int i; + + /* + * SROM:CS1 and EBI + * + * GPY0[0] SROM_CSn[0] + * GPY0[1] SROM_CSn[1](2) + * GPY0[2] SROM_CSn[2] + * GPY0[3] SROM_CSn[3] + * GPY0[4] EBI_OEn(2) + * GPY0[5] EBI_EEn(2) + * + * GPY1[0] EBI_BEn[0](2) + * GPY1[1] EBI_BEn[1](2) + * GPY1[2] SROM_WAIT(2) + * GPY1[3] EBI_DATA_RDn(2) + */ + s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), + GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + + for (i = 0; i < 4; i++) + s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + + /* + * EBI: 8 Addrss Lines + * + * GPY3[0] EBI_ADDR[0](2) + * GPY3[1] EBI_ADDR[1](2) + * GPY3[2] EBI_ADDR[2](2) + * GPY3[3] EBI_ADDR[3](2) + * GPY3[4] EBI_ADDR[4](2) + * GPY3[5] EBI_ADDR[5](2) + * GPY3[6] EBI_ADDR[6](2) + * GPY3[7] EBI_ADDR[7](2) + * + * EBI: 16 Data Lines + * + * GPY5[0] EBI_DATA[0](2) + * GPY5[1] EBI_DATA[1](2) + * GPY5[2] EBI_DATA[2](2) + * GPY5[3] EBI_DATA[3](2) + * GPY5[4] EBI_DATA[4](2) + * GPY5[5] EBI_DATA[5](2) + * GPY5[6] EBI_DATA[6](2) + * GPY5[7] EBI_DATA[7](2) + * + * GPY6[0] EBI_DATA[8](2) + * GPY6[1] EBI_DATA[9](2) + * GPY6[2] EBI_DATA[10](2) + * GPY6[3] EBI_DATA[11](2) + * GPY6[4] EBI_DATA[12](2) + * GPY6[5] EBI_DATA[13](2) + * GPY6[6] EBI_DATA[14](2) + * GPY6[7] EBI_DATA[15](2) + */ + for (i = 0; i < 8; i++) { + s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + } +} + +static int exynos5_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos5_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos5_mmc_config(peripheral, flags); + case PERIPH_ID_SROMC: + exynos5_sromc_config(flags); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + +int exynos_pinmux_config(int peripheral, int flags) +{ + if (cpu_is_exynos5()) + return exynos5_pinmux_config(peripheral, flags); + else { + debug("pinmux functionality not supported\n"); + return -1; + } +} diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index c765304fd5..4116781a36 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -52,3 +52,25 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable) if (cpu_is_exynos4()) exynos4_mipi_phy_control(dev_index, enable); } + +void exynos5_set_usbhost_phy_ctrl(unsigned int enable) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + if (enable) { + /* Enabling USBHOST_PHY */ + setbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } else { + /* Disabling USBHOST_PHY */ + clrbits_le32(&power->usbhost_phy_control, + POWER_USB_HOST_PHY_CTRL_EN); + } +} + +void set_usbhost_phy_ctrl(unsigned int enable) +{ + if (cpu_is_exynos5()) + exynos5_set_usbhost_phy_ctrl(enable); +} diff --git a/arch/arm/cpu/armv7/exynos/system.c b/arch/arm/cpu/armv7/exynos/system.c index 6c34730b97..4426611d1b 100644 --- a/arch/arm/cpu/armv7/exynos/system.c +++ b/arch/arm/cpu/armv7/exynos/system.c @@ -25,6 +25,27 @@ #include <asm/io.h> #include <asm/arch/system.h> +static void exynos5_set_usbhost_mode(unsigned int mode) +{ + struct exynos5_sysreg *sysreg = + (struct exynos5_sysreg *)samsung_get_base_sysreg(); + + /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */ + if (mode == USB20_PHY_CFG_HOST_LINK_EN) { + setbits_le32(&sysreg->usb20phy_cfg, + USB20_PHY_CFG_HOST_LINK_EN); + } else { + clrbits_le32(&sysreg->usb20phy_cfg, + USB20_PHY_CFG_HOST_LINK_EN); + } +} + +void set_usbhost_mode(unsigned int mode) +{ + if (cpu_is_exynos5()) + exynos5_set_usbhost_mode(mode); +} + static void exynos4_set_system_display(void) { struct exynos4_sysreg *sysreg = diff --git a/arch/arm/cpu/armv7/imx-common/speed.c b/arch/arm/cpu/armv7/imx-common/speed.c index 2187e8ee5d..80989c4983 100644 --- a/arch/arm/cpu/armv7/imx-common/speed.c +++ b/arch/arm/cpu/armv7/imx-common/speed.c @@ -35,7 +35,11 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_USDHC + gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); +#else gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); #endif +#endif return 0; } diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fc2406bcad..64862b31f1 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -843,7 +843,7 @@ void mxc_set_sata_internal_clock(void) set_usb_phy1_clk(); - writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base); + writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base); } #endif diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 90f208809b..84b458c7eb 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -43,7 +43,6 @@ u32 get_cpu_rev(void) return system_rev; } -#ifdef CONFIG_ARCH_CPU_INIT void init_aips(void) { struct aipstz_regs *aips1, *aips2; @@ -113,7 +112,6 @@ int arch_cpu_init(void) return 0; } -#endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 10d286a6d4..b1fd277d6d 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -299,8 +299,12 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, - "core"); + if (omap_revision() != OMAP5432_ES1_0) + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + DPLL_NO_LOCK, "core"); + else + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + DPLL_LOCK, "core"); /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index db509c9295..30dcf1b0b0 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -31,6 +31,28 @@ #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> #include <asm/utils.h> +#include <linux/compiler.h> + +void set_lpmode_selfrefresh(u32 base) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 reg; + + reg = readl(&emif->emif_pwr_mgmt_ctrl); + reg &= ~EMIF_REG_LP_MODE_MASK; + reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; + reg &= ~EMIF_REG_SR_TIM_MASK; + writel(reg, &emif->emif_pwr_mgmt_ctrl); + + /* dummy read for the new SR_TIM to be loaded */ + readl(&emif->emif_pwr_mgmt_ctrl); +} + +void force_emif_self_refresh() +{ + set_lpmode_selfrefresh(EMIF1_BASE); + set_lpmode_selfrefresh(EMIF2_BASE); +} inline u32 emif_num(u32 base) { @@ -56,7 +78,12 @@ static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) mr = readl(&emif->emif_lpddr2_mode_reg_data); debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), cs, mr_addr, mr); - return mr; + if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && + ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && + ((mr & 0xff000000) >> 24) == (mr & 0xff)) + return mr & 0xff; + else + return mr; } static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) @@ -114,9 +141,6 @@ static void do_lpddr2_init(u32 base, u32 cs) static void lpddr2_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - u32 i = 0; /* Not NVM */ clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); @@ -134,29 +158,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) writel(regs->sdram_config_init, &emif->emif_sdram_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); - - if (omap_revision() >= OMAP5430_ES1_0) { - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - - /* - * external phy 6-24 registers do not change with - * ddr frequency - */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - } - } + do_ext_phy_settings(base, regs); do_lpddr2_init(base, CS0); if (regs->sdram_config & EMIF_REG_EBANK_MASK) @@ -168,6 +170,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs) /* Enable refresh now */ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); + } + +__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ } void emif_update_timings(u32 base, const struct emif_regs *regs) @@ -190,7 +196,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - if (omap_revision() == OMAP5430_ES1_0) { + if (omap_revision() >= OMAP5430_ES1_0) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -202,6 +208,101 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } } +static void ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* keep sdram in self-refresh */ + writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + __udelay(130); + + /* + * Set invert_clkout (if activated)--DDR_PHYCTRL_1 + * Invert clock adds an additional half cycle delay on the command + * interface. The additional half cycle, is usually meant to enable + * leveling in the situation that DQS is later than CK on the board.It + * also helps provide some additional margin for leveling. + */ + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + __udelay(130); + + writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + + /* Launch Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + /* Wait till full leveling is complete */ + readl(&emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Read data eye leveling no of samples */ + config_data_eye_leveling_samples(base); + + /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Launch Incremental leveling */ + writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); +} + +static void ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + /* + * Set SDRAM_CONFIG and PHY control registers to locked frequency + * and RL =7. As the default values of the Mode Registers are not + * defined, contents of mode Registers must be fully initialized. + * H/W takes care of this initialization + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } + + /* enable leveling */ + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + + ddr3_leveling(base, regs); +} + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) @@ -826,7 +927,7 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs, } mr = get_mr(base, cs, LPDDR2_MR5); - if (mr >= 0xFF) { + if (mr > 0xFF) { /* Mode register value bigger than 8 bit */ return 0; } @@ -895,7 +996,7 @@ struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, return NULL; /* Do the minimum init for mode register accesses */ - if (!running_from_sdram()) { + if (!(running_from_sdram() || warm_reset())) { phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); writel(phy, &emif->emif_ddr_phy_ctrl_1); } @@ -975,8 +1076,12 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!in_sdram) - lpddr2_init(base, regs); + if (!(in_sdram || warm_reset())) { + if (omap_revision() != OMAP5432_ES1_0) + lpddr2_init(base, regs); + else + ddr3_init(base, regs); + } /* Write to the shadow registers */ emif_update_timings(base, regs); @@ -1133,6 +1238,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; + u32 omap_rev = omap_revision(); debug(">>sdram_init()\n"); @@ -1142,25 +1248,34 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!in_sdram) - bypass_dpll(&prcm->cm_clkmode_dpll_core); - + if (!(in_sdram || warm_reset())) { + if (omap_rev != OMAP5432_ES1_0) + bypass_dpll(&prcm->cm_clkmode_dpll_core); + else + writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); + } do_sdram_init(EMIF1_BASE); do_sdram_init(EMIF2_BASE); - if (!in_sdram) { + if (!in_sdram) dmm_init(DMM_BASE); + + if (!(in_sdram || warm_reset())) { emif_post_init_config(EMIF1_BASE); emif_post_init_config(EMIF2_BASE); } /* for the shadow registers to take effect */ - freq_update_core(); + if (omap_rev != OMAP5432_ES1_0) + freq_update_core(); /* Do some testing after the init */ if (!in_sdram) { size_prog = omap_sdram_size(); + size_prog = log_2_n_round_down(size_prog); + size_prog = (1 << size_prog); + size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, size_prog); /* Compare with the size programmed */ diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index cf71ab4443..459ebb55e5 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -111,6 +111,10 @@ static void init_boot_params(void) void s_init(void) { init_omap_revision(); +#ifdef CONFIG_SPL_BUILD + if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) + force_emif_self_refresh(); +#endif watchdog_init(); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD @@ -162,11 +166,16 @@ void watchdog_init(void) */ u32 omap_sdram_size(void) { - u32 section, i, total_size = 0, size, addr; + u32 section, i, valid; + u64 sdram_start = 0, sdram_end = 0, addr, + size, total_size = 0, trap_size = 0; for (i = 0; i < 4; i++) { section = __raw_readl(DMM_BASE + i*4); + valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> + (EMIF_SDRC_ADDRSPC_SHIFT); addr = section & EMIF_SYS_ADDR_MASK; + /* See if the address is valid */ if ((addr >= DRAM_ADDR_SPACE_START) && (addr < DRAM_ADDR_SPACE_END)) { @@ -174,9 +183,20 @@ u32 omap_sdram_size(void) EMIF_SYS_SIZE_SHIFT); size = 1 << size; size *= SZ_16M; - total_size += size; + + if (valid != DMM_SDRC_ADDR_SPC_INVALID) { + if (!sdram_start || (addr < sdram_start)) + sdram_start = addr; + if (!sdram_end || ((addr + size) > sdram_end)) + sdram_end = addr + size; + } else { + trap_size = size; + } + } + } + total_size = (sdram_end - sdram_start) - (trap_size); return total_size; } diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c index 234e90a868..587bb47745 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.c +++ b/arch/arm/cpu/armv7/omap-common/reset.c @@ -34,3 +34,8 @@ void __weak reset_cpu(unsigned long ignored) { writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); } + +u32 __weak warm_reset(void) +{ + return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK); +} diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index c568951a91..5bd0a88fde 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ }; /* ABE M & N values with sys_clk as source */ @@ -354,6 +354,7 @@ void enable_basic_clocks(void) }; u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_memif_emif_1_clkctrl, &prcm->cm_memif_emif_2_clkctrl, &prcm->cm_l4cfg_l4_cfg_clkctrl, @@ -363,9 +364,6 @@ void enable_basic_clocks(void) &prcm->cm_l4per_gpio4_clkctrl, &prcm->cm_l4per_gpio5_clkctrl, &prcm->cm_l4per_gpio6_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_clksel_usb_60mhz, - &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -376,7 +374,6 @@ void enable_basic_clocks(void) &prcm->cm_l4per_gptimer2_clkctrl, &prcm->cm_wkup_wdtimer2_clkctrl, &prcm->cm_l4per_uart3_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -413,6 +410,9 @@ void enable_basic_uboot_clocks(void) u32 *const clk_modules_hw_auto_essential[] = { &prcm->cm_l3init_hsusbotg_clkctrl, &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_l3init_usbphy_clkctrl, + &prcm->cm_clksel_usb_60mhz, + &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -422,6 +422,7 @@ void enable_basic_uboot_clocks(void) &prcm->cm_l4per_i2c2_clkctrl, &prcm->cm_l4per_i2c3_clkctrl, &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; @@ -452,12 +453,10 @@ void enable_non_essential_clocks(void) }; u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_l3instr_l3_3_clkctrl, &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; @@ -497,7 +496,6 @@ void enable_non_essential_clocks(void) &prcm->cm_cam_fdif_clkctrl, &prcm->cm_dss_dss_clkctrl, &prcm->cm_sgx_sgx_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, 0 }; diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 187e93887b..2c34e48f42 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -118,6 +118,11 @@ void do_io_settings(void) } #endif +/* dummy fuction for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + void init_omap_revision(void) { /* diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b5389606b6..b9128faa56 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -91,7 +91,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { }; /* Dummy registers for OMAP44xx */ -const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index 1a59f265f7..eecfbade35 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void) */ void scale_vcores(void) { - u32 volt; + u32 volt_core, volt_mpu, volt_mm; omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); /* Palmas settings */ - volt = VDD_CORE; - do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); - - volt = VDD_MPU; - do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - - volt = VDD_MM; - do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - + if (omap_revision() != OMAP5432_ES1_0) { + volt_core = VDD_CORE; + volt_mpu = VDD_MPU; + volt_mm = VDD_MM; + } else { + volt_core = VDD_CORE_5432; + volt_mpu = VDD_MPU_5432; + volt_mm = VDD_MM_5432; + } + + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core); + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); + + if (omap_revision() == OMAP5432_ES1_0) { + /* Configure LDO SRAM "magic" bits */ + writel(2, &prcm->prm_sldo_core_setup); + writel(2, &prcm->prm_sldo_mpu_setup); + writel(2, &prcm->prm_sldo_mm_setup); + } } u32 get_offset_code(u32 volt_offset) @@ -306,6 +317,7 @@ void enable_basic_clocks(void) }; u32 *const clk_modules_hw_auto_essential[] = { + &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_memif_emif_1_clkctrl, &prcm->cm_memif_emif_2_clkctrl, &prcm->cm_l4cfg_l4_cfg_clkctrl, @@ -382,6 +394,9 @@ void enable_basic_uboot_clocks(void) &prcm->cm_l4per_i2c2_clkctrl, &prcm->cm_l4per_i2c3_clkctrl, &prcm->cm_l4per_i2c4_clkctrl, + &prcm->cm_l3init_hsusbtll_clkctrl, + &prcm->cm_l3init_hsusbhost_clkctrl, + &prcm->cm_l3init_fsusb_clkctrl, 0 }; @@ -416,12 +431,10 @@ void enable_non_essential_clocks(void) &prcm->cm_ivahd_ivahd_clkctrl, &prcm->cm_ivahd_sl2_clkctrl, &prcm->cm_dsp_dsp_clkctrl, - &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_l3instr_l3_3_clkctrl, &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l3init_hsusbtll_clkctrl, &prcm->cm_l4per_hdq1w_clkctrl, 0 }; @@ -460,8 +473,6 @@ void enable_non_essential_clocks(void) &prcm->cm_cam_fdif_clkctrl, &prcm->cm_dss_dss_clkctrl, &prcm->cm_sgx_sgx_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, - &prcm->cm_l3init_fsusb_clkctrl, 0 }; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d01cc81333..d0c3ff7021 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -35,6 +35,7 @@ #include <asm/sizes.h> #include <asm/utils.h> #include <asm/arch/gpio.h> +#include <asm/emif.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +53,81 @@ static struct gpio_bank gpio_bank_54xx[6] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; #ifdef CONFIG_SPL_BUILD +/* LPDDR2 specific IO settings */ +static void io_settings_lpddr2(void) +{ + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_1)); + writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, + &(ioregs_base->control_ddrio_0)); + writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, + &(ioregs_base->control_ddrio_1)); + writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, + &(ioregs_base->control_ddrio_2)); +} + +/* DDR3 specific IO settings */ +static void io_settings_ddr3(void) +{ + u32 io_settings = 0; + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddr3ch1_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch1_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch1_1)); + + writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddr3ch2_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch2_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch2_1)); + + writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_0)); + writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_1)); + writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_2)); + + /* omap5432 does not use lpddr2 */ + writel(0x0, &(ioregs_base->control_lpddr2ch1_0)); + writel(0x0, &(ioregs_base->control_lpddr2ch1_1)); + + writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + &(ioregs_base->control_emif1_sdram_config_ext)); + writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + &(ioregs_base->control_emif2_sdram_config_ext)); + + /* Disable DLL select */ + io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config)) + & 0xFFEFFFFF); + writel(io_settings, + &(ioregs_base->control_port_emif1_sdram_config)); + + io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config)) + & 0xFFEFFFFF); + writel(io_settings, + &(ioregs_base->control_port_emif2_sdram_config)); +} + /* * Some tuning of IOs for optimal power and performance */ @@ -115,25 +191,10 @@ void do_io_settings(void) (sc_fast << 17) | (sc_fast << 14); writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); - /* LPDDR2 io settings */ - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_1)); - writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - &(ioregs_base->control_ddrio_0)); - writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - &(ioregs_base->control_ddrio_1)); - writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, - &(ioregs_base->control_ddrio_2)); + if (omap_revision() <= OMAP5430_ES1_0) + io_settings_lpddr2(); + else + io_settings_ddr3(); /* Efuse settings */ writel(EFUSE_1, &(ioregs_base->control_efuse_1)); @@ -143,6 +204,20 @@ void do_io_settings(void) } #endif +void config_data_eye_leveling_samples(u32 emif_base) +{ + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ + if (emif_base == EMIF1_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif1_sdram_config_ext)); + else if (emif_base == EMIF2_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif2_sdram_config_ext)); +} + void init_omap_revision(void) { /* @@ -154,7 +229,15 @@ void init_omap_revision(void) switch (rev) { case MIDR_CORTEX_A15_R0P0: - *omap_si_rev = OMAP5430_ES1_0; + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + default: + *omap_si_rev = OMAP5432_ES1_0; + break; + } break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index b2b5753e89..6ebdf5fbfd 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -86,11 +86,34 @@ const struct emif_regs emif_regs_266_mhz_2cs = { .emif_ddr_ext_phy_ctrl_5 = 0x04010040 }; +const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0020420A, + .emif_ddr_phy_ctlr_1 = 0x0024420A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, - .dmm_lisa_map_1 = 0, - .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80740300 + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80740300, + .dmm_lisa_map_3 = 0xFF020100 }; const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { @@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000077 }; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x01004010, + 0x00001004, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x0, + 0x0, + 0x0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { - *regs = &emif_regs_532_mhz_2cs; + if (omap_revision() == OMAP5432_ES1_0) + *regs = &emif_regs_ddr3_532_mhz_1cs; + else + *regs = &emif_regs_532_mhz_2cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -156,6 +204,37 @@ void emif_get_device_details(u32 emif_nr, #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ +void do_ext_phy_settings(u32 base, const struct emif_regs *regs) +{ + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } +} + #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS static const struct lpddr2_ac_timings timings_jedec_532_mhz = { .max_freq = 532000000, diff --git a/arch/arm/cpu/armv7/s5p-common/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index 527f32deef..16427333ac 100644 --- a/arch/arm/cpu/armv7/s5p-common/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -48,8 +48,9 @@ int print_cpuinfo(void) { char buf[32]; - printf("CPU:\tS5P%X@%sMHz\n", - s5p_cpu_id, strmhz(buf, get_arm_clk())); + printf("CPU:\t%s%X@%sMHz\n", + s5p_get_cpu_name(), s5p_cpu_id, + strmhz(buf, get_arm_clk())); return 0; } diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 261835b6c6..aee27fdc4d 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -259,10 +259,12 @@ clear_bss: #endif mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: /* * We are done. Do not return, instead branch to second part of board @@ -277,6 +279,18 @@ jump_2_ram: mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif +/* + * Move vector table + */ +#if !defined(CONFIG_TEGRA2) +#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + add r0, r0, r9 + mcr p15, 0, r0, c12, c0, 0 @Set VBAR +#endif +#endif /* !Tegra2 */ + ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index 08c4137a34..80da4536d3 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS-$(CONFIG_TEGRA_PMU) += pmu.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o +COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 698bfd0e17..1aad3879ee 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -77,8 +77,10 @@ static int ap20_cpu_is_cortexa9(void) void init_pllx(void) { - struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU]; + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll_simple *pll = + &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE]; u32 reg; /* If PLLX is already enabled, just return */ @@ -312,9 +314,28 @@ void enable_scu(void) writel(reg, &scu->scu_ctrl); } +static u32 get_odmdata(void) +{ + /* + * ODMDATA is stored in the BCT in IRAM by the BootROM. + * The BCT start and size are stored in the BIT in IRAM. + * Read the data @ bct_start + (bct_size - 12). This works + * on T20 and T30 BCTs, which are locked down. If this changes + * in new chips (T114, etc.), we can revisit this algorithm. + */ + + u32 bct_start, odmdata; + + bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR); + odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); + + return odmdata; +} + void init_pmc_scratch(void) { struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + u32 odmdata; int i; /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ @@ -322,7 +343,8 @@ void init_pmc_scratch(void) writel(0, &pmc->pmc_scratch1+i); /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ - writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); + odmdata = get_odmdata(); + writel(odmdata, &pmc->pmc_scratch20); #ifdef CONFIG_TEGRA2_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index a50b1b988a..923678d063 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -101,6 +101,22 @@ int arch_cpu_init(void) } #endif +static int uart_configs[] = { +#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB) + FUNCMUX_UART1_UAA_UAB, +#elif defined(CONFIG_TEGRA2_UARTA_GPU) + FUNCMUX_UART1_GPU, +#elif defined(CONFIG_TEGRA2_UARTA_SDIO1) + FUNCMUX_UART1_SDIO1, +#else + FUNCMUX_UART1_IRRX_IRTX, +#endif + FUNCMUX_UART2_IRDA, + -1, + FUNCMUX_UART4_GMC, + -1, +}; + /** * Set up the specified uarts * @@ -120,7 +136,7 @@ static void setup_uarts(int uart_ids) if (uart_ids & (1 << i)) { enum periph_id id = id_for_uart[i]; - funcmux_select(id, FUNCMUX_DEFAULT); + funcmux_select(id, uart_configs[i]); clock_ll_start_uart(id); } } diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index ccad351639..602589cde0 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - assert(clock_id_isvalid(clkid)); + assert(clock_id_is_pll(clkid)); return &clkrst->crc_pll[clkid]; } @@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, assert(clkid != CLOCK_ID_USB); /* Safety check, adds to code size but is small */ - if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB) + if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB) return -1; data = readl(&pll->pll_base); *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT; diff --git a/arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c new file mode 100644 index 0000000000..2fcd107df5 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * Derived from code (arch/arm/lib/reset.c) that is: + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2004 + * DAVE Srl + * http://www.dave-tech.it + * http://www.wawnet.biz + * mailto:info@wawnet.biz + * + * (C) Copyright 2004 Texas Insturments + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/pmc.h> + +static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + + puts("Entering RCM...\n"); + udelay(50000); + + pmc->pmc_scratch0 = 2; + disable_interrupts(); + reset_cpu(0); + + return 0; +} + +U_BOOT_CMD( + enterrcm, 1, 0, do_enterrcm, + "reset Tegra and enter USB Recovery Mode", + "" +); diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index fe9ef5b763..4dd8cb8442 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -24,10 +24,13 @@ # MA 02111-1307 USA # -# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this -# file with compatible flags +# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these +# files with compatible flags ifdef CONFIG_TEGRA2 CFLAGS_arch/arm/lib/board.o += -march=armv4t +CFLAGS_arch/arm/lib/memset.o += -march=armv4t +CFLAGS_lib/string.o += -march=armv4t +CFLAGS_common/cmd_nvedit.o += -march=armv4t endif USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c index 0ef7753021..4a31a4cf0c 100644 --- a/arch/arm/cpu/armv7/tegra2/funcmux.c +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c @@ -31,11 +31,32 @@ int funcmux_select(enum periph_id id, int config) switch (id) { case PERIPH_ID_UART1: - if (config == FUNCMUX_UART1_IRRX_IRTX) { + switch (config) { + case FUNCMUX_UART1_IRRX_IRTX: pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); pinmux_tristate_disable(PINGRP_IRRX); pinmux_tristate_disable(PINGRP_IRTX); + break; + case FUNCMUX_UART1_UAA_UAB: + pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA); + pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_UAA); + pinmux_tristate_disable(PINGRP_UAB); + bad_config = 0; + break; + case FUNCMUX_UART1_GPU: + pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_GPU); + bad_config = 0; + break; + case FUNCMUX_UART1_SDIO1: + pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_SDIO1); + bad_config = 0; + break; + } + if (!bad_config) { /* * Tegra appears to boot with function UARTA pre- * selected on mux group SDB. If two mux groups are @@ -106,6 +127,13 @@ int funcmux_select(enum periph_id id, int config) } break; + case PERIPH_ID_SDMMC1: + if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) { + pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); + pinmux_tristate_disable(PINGRP_SDIO1); + } + break; + case PERIPH_ID_SDMMC2: if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) { pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2); @@ -181,9 +209,30 @@ int funcmux_select(enum periph_id id, int config) pinmux_set_func(grp[i], PMUX_FUNC_KBC); pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); } + } + break; - break; + case PERIPH_ID_USB2: + if (config == FUNCMUX_USB2_ULPI) { + pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI); + pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI); + pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI); + + pinmux_tristate_disable(PINGRP_UAA); + pinmux_tristate_disable(PINGRP_UAB); + pinmux_tristate_disable(PINGRP_UDA); } + break; + + case PERIPH_ID_SPI1: + if (config == FUNCMUX_SPI1_GMC_GMD) { + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); + pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); + + pinmux_tristate_disable(PINGRP_GMC); + pinmux_tristate_disable(PINGRP_GMD); + } + break; default: debug("%s: invalid periph_id %d", __func__, id); diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c index c80de7f6a3..5f2b243750 100644 --- a/arch/arm/cpu/armv7/tegra2/usb.c +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -290,7 +290,7 @@ static int init_usb_controller(struct fdt_usb *config, break; udelay(1); } - if (loop_count == 100000) + if (!loop_count) return -1; return 0; diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index cb32121a07..59c359a353 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -334,10 +334,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: bl coloured_LED_init bl red_led_on diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 62de8b8fc7..bd68cd47cf 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -245,10 +245,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: #endif /* diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index ba0de8f1db..33c73f67b5 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -258,10 +258,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: #endif /* #ifndef CONFIG_SPL_BUILD */ /* diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index a29d5b4964..8daf26c4f0 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -217,10 +217,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: bl coloured_LED_init bl red_led_on diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 92546d8ba7..bcea2a8deb 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -221,10 +221,12 @@ clear_bss: add r1, r1, r4 mov r2, #0x00000000 /* clear */ -clbss_l:str r2, [r0] /* clear loop... */ +clbss_l:cmp r0, r1 /* clear loop... */ + bhs clbss_e /* if reached end of bss, exit */ + str r2, [r0] add r0, r0, #4 - cmp r0, r1 - bne clbss_l + b clbss_l +clbss_e: #endif /* diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index abc5b6b411..d748dd2787 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -19,16 +19,16 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ -#define OSC 24 +#define OSC (V_OSCK/1000000) /* MAIN PLL Fdll = 550 MHZ, */ #define MPUPLL_M 550 -#define MPUPLL_N 23 +#define MPUPLL_N (OSC-1) #define MPUPLL_M2 1 /* Core PLL Fdll = 1 GHZ, */ #define COREPLL_M 1000 -#define COREPLL_N 23 +#define COREPLL_N (OSC-1) #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ @@ -40,13 +40,13 @@ * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below */ #define PERPLL_M 960 -#define PERPLL_N 23 +#define PERPLL_N (OSC-1) #define PERPLL_M2 5 /* DDR Freq is 266 MHZ for now */ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ #define DDRPLL_M 266 -#define DDRPLL_N 23 +#define DDRPLL_N (OSC-1) #define DDRPLL_M2 1 extern void pll_init(void); diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index cd002e632d..a027e3128f 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -53,8 +53,10 @@ /* Reset control */ #ifdef CONFIG_AM33XX #define PRM_RSTCTRL 0x44E00F00 +#define PRM_RSTST 0x44E00F08 #endif #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST_WARM_RESET_MASK 0x232 #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ @@ -62,7 +64,7 @@ struct cm_wkuppll { unsigned int wkclkstctrl; /* offset 0x00 */ unsigned int wkctrlclkctrl; /* offset 0x04 */ - unsigned int resv1[1]; + unsigned int wkgpio0clkctrl; /* offset 0x08 */ unsigned int wkl4wkclkctrl; /* offset 0x0c */ unsigned int resv2[4]; unsigned int idlestdpllmpu; /* offset 0x20 */ @@ -111,34 +113,54 @@ struct cm_perpll { unsigned int l3clkstctrl; /* offset 0x0c */ unsigned int resv1; unsigned int cpgmac0clkctrl; /* offset 0x14 */ - unsigned int resv2[4]; + unsigned int lcdclkctrl; /* offset 0x18 */ + unsigned int usb0clkctrl; /* offset 0x1C */ + unsigned int resv2; + unsigned int tptc0clkctrl; /* offset 0x24 */ unsigned int emifclkctrl; /* offset 0x28 */ unsigned int ocmcramclkctrl; /* offset 0x2c */ unsigned int gpmcclkctrl; /* offset 0x30 */ - unsigned int resv3[2]; + unsigned int mcasp0clkctrl; /* offset 0x34 */ + unsigned int uart5clkctrl; /* offset 0x38 */ unsigned int mmc0clkctrl; /* offset 0x3C */ unsigned int elmclkctrl; /* offset 0x40 */ unsigned int i2c2clkctrl; /* offset 0x44 */ unsigned int i2c1clkctrl; /* offset 0x48 */ unsigned int spi0clkctrl; /* offset 0x4C */ unsigned int spi1clkctrl; /* offset 0x50 */ - unsigned int resv4[3]; + unsigned int resv3[3]; unsigned int l4lsclkctrl; /* offset 0x60 */ unsigned int l4fwclkctrl; /* offset 0x64 */ - unsigned int resv5[6]; + unsigned int mcasp1clkctrl; /* offset 0x68 */ + unsigned int uart1clkctrl; /* offset 0x6C */ + unsigned int uart2clkctrl; /* offset 0x70 */ + unsigned int uart3clkctrl; /* offset 0x74 */ + unsigned int uart4clkctrl; /* offset 0x78 */ + unsigned int timer7clkctrl; /* offset 0x7C */ unsigned int timer2clkctrl; /* offset 0x80 */ - unsigned int resv6[11]; + unsigned int timer3clkctrl; /* offset 0x84 */ + unsigned int timer4clkctrl; /* offset 0x88 */ + unsigned int resv4[8]; + unsigned int gpio1clkctrl; /* offset 0xAC */ unsigned int gpio2clkctrl; /* offset 0xB0 */ - unsigned int resv7[7]; + unsigned int gpio3clkctrl; /* offset 0xB4 */ + unsigned int resv5; + unsigned int tpccclkctrl; /* offset 0xBC */ + unsigned int dcan0clkctrl; /* offset 0xC0 */ + unsigned int dcan1clkctrl; /* offset 0xC4 */ + unsigned int resv6[2]; unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int resv8[2]; + unsigned int resv7[2]; unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ - unsigned int resv9[14]; + unsigned int resv8[4]; + unsigned int mmc1clkctrl; /* offset 0xF4 */ + unsigned int mmc2clkctrl; /* offset 0xF8 */ + unsigned int resv9[8]; unsigned int l4hsclkstctrl; /* offset 0x11C */ unsigned int l4hsclkctrl; /* offset 0x120 */ unsigned int resv10[8]; - unsigned int cpswclkctrl; /* offset 0x144 */ + unsigned int cpswclkstctrl; /* offset 0x144 */ }; /* Encapsulating Display pll registers */ @@ -213,8 +235,6 @@ struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ }; - -void init_timer(void); #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 366e2bbec5..32b225800d 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -34,9 +34,9 @@ struct i2c { unsigned short revnb_lo; /* 0x00 */ unsigned short res1; unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[13]; - unsigned short sysc; /* 0x20 */ - unsigned short res3; + unsigned short res2[5]; + unsigned short sysc; /* 0x10 */ + unsigned short res3[9]; unsigned short irqstatus_raw; /* 0x24 */ unsigned short res4; unsigned short stat; /* 0x28 */ @@ -76,6 +76,6 @@ struct i2c { }; #define I2C_IP_CLK 48000000 -#define I2C_INTERNAL_SAMLPING_CLK 12000000 +#define I2C_INTERNAL_SAMPLING_CLK 12000000 #endif /* _I2C_H_ */ diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf87c..0483c9820e 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -66,14 +66,50 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; +#if defined(CPU_HAS_PIO3) + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; /* */ +#else u32 asr; /* 0x70 Select A Register */ u32 bsr; /* 0x74 Select B Register */ u32 absr; /* 0x78 AB Select Status Register */ u32 reserved5[9]; /* */ +#endif u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ + u32 owsr; /* OxA8 Output Write Status Register */ +#if defined(CPU_HAS_PIO3) + u32 reserved7; /* */ + u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ + u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ + u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */ + u32 reserved8; /* */ + u32 esr; /* 0xC0 Edge Select Register */ + u32 lsr; /* 0xC4 Level Select Register */ + u32 elsr; /* 0xC8 Edge/Level Status Register */ + u32 reserved9; /* 0xCC */ + u32 fellsr; /* 0xD0 Falling /Low Level Select Register */ + u32 rehlsr; /* 0xD4 Rising /High Level Select Register */ + u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ + u32 reserved10; /* */ + u32 locksr; /* 0xE0 Lock Status */ + u32 wpmr; /* 0xE4 Write Protect Mode Register */ + u32 wpsr; /* 0xE8 Write Protect Status Register */ + u32 reserved11[5]; /* */ + u32 schmitt; /* 0x100 Schmitt Trigger Register */ + u32 reserved12[63]; +#else u32 reserved6[85]; +#endif } at91_port_t; typedef union at91_pio { @@ -94,6 +130,13 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +#if defined(CPU_HAS_PIO3) +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); +#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7354..0c341d4318 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -24,6 +24,7 @@ #define DEVICE_NOT_AVAILABLE 0 +#define EXYNOS_CPU_NAME "Exynos" #define EXYNOS4_ADDR_BASE 0x10000000 /* EXYNOS4 */ @@ -45,6 +46,7 @@ #define EXYNOS4_USBOTG_BASE 0x12480000 #define EXYNOS4_MMC_BASE 0x12510000 #define EXYNOS4_SROMC_BASE 0x12570000 +#define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000 #define EXYNOS4_USBPHY_BASE 0x125B0000 #define EXYNOS4_UART_BASE 0x13800000 #define EXYNOS4_ADC_BASE 0x13910000 @@ -68,10 +70,11 @@ #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 +#define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 +#define EXYNOS5_USBPHY_BASE 0x12130000 +#define EXYNOS5_USBOTG_BASE 0x12140000 #define EXYNOS5_MMC_BASE 0x12200000 #define EXYNOS5_SROMC_BASE 0x12250000 -#define EXYNOS5_USBOTG_BASE 0x12480000 -#define EXYNOS5_USBPHY_BASE 0x12480000 #define EXYNOS5_UART_BASE 0x12C00000 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5_GPIO_PART2_BASE 0x13400000 @@ -93,29 +96,42 @@ static inline int s5p_get_cpu_rev(void) static inline void s5p_set_cpu_id(void) { - s5p_cpu_id = readl(EXYNOS4_PRO_ID); - s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12)); - - /* - * 0xC200: EXYNOS4210 EVT0 - * 0xC210: EXYNOS4210 EVT1 - */ - if (s5p_cpu_id == 0xC200) { - s5p_cpu_id |= 0x10; + unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12; + + switch (pro_id) { + case 0x200: + /* Exynos4210 EVT0 */ + s5p_cpu_id = 0x4210; s5p_cpu_rev = 0; - } else if (s5p_cpu_id == 0xC210) { - s5p_cpu_rev = 1; + break; + case 0x210: + /* Exynos4210 EVT1 */ + s5p_cpu_id = 0x4210; + break; + case 0x412: + /* Exynos4412 */ + s5p_cpu_id = 0x4412; + break; + case 0x520: + /* Exynos5250 */ + s5p_cpu_id = 0x5250; + break; } } +static inline char *s5p_get_cpu_name(void) +{ + return EXYNOS_CPU_NAME; +} + #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ - return s5p_cpu_id == id ? 1 : 0; \ + return (s5p_cpu_id >> 12) == id; \ } -IS_SAMSUNG_TYPE(exynos4, 0xc210) -IS_SAMSUNG_TYPE(exynos5, 0xc520) +IS_SAMSUNG_TYPE(exynos4, 0x4) +IS_SAMSUNG_TYPE(exynos5, 0x5) #define SAMSUNG_BASE(device, base) \ static inline unsigned int samsung_get_base_##device(void) \ @@ -145,6 +161,7 @@ SAMSUNG_BASE(swreset, SWRESET) SAMSUNG_BASE(timer, PWMTIMER_BASE) SAMSUNG_BASE(uart, UART_BASE) SAMSUNG_BASE(usb_phy, USBPHY_BASE) +SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE) SAMSUNG_BASE(usb_otg, USBOTG_BASE) SAMSUNG_BASE(watchdog, WATCHDOG_BASE) SAMSUNG_BASE(power, POWER_BASE) diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h b/arch/arm/include/asm/arch-exynos/ehci.h index 68feb85ede..8aeff8ab2f 100644 --- a/arch/arm/include/asm/arch-exynos/ehci-s5p.h +++ b/arch/arm/include/asm/arch-exynos/ehci.h @@ -1,5 +1,5 @@ /* - * SAMSUNG S5P USB HOST EHCI Controller + * SAMSUNG EXYNOS USB HOST EHCI Controller * * Copyright (C) 2012 Samsung Electronics Co.Ltd * Vivek Gautam <gautam.vivek@samsung.com> @@ -20,8 +20,8 @@ * MA 02110-1301 USA */ -#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ -#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ +#ifndef __ASM_ARM_ARCH_EHCI_H__ +#define __ASM_ARM_ARCH_EHCI_H__ #define CLK_24MHZ 5 @@ -43,7 +43,7 @@ #define EHCICTRL_ENAINCR16 (1 << 26) /* Register map for PHY control */ -struct s5p_usb_phy { +struct exynos_usb_phy { unsigned int usbphyctrl0; unsigned int usbphytune0; unsigned int reserved1[2]; @@ -63,4 +63,4 @@ struct s5p_usb_phy { /* Switch on the VBUS power. */ int board_usb_vbus_init(void); -#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */ +#endif /* __ASM_ARM_ARCH_EHCI_H__ */ diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h new file mode 100644 index 0000000000..5db25aa88a --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde <rajeshwari.s@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals requiring clock/pinmux configuration. List will + * grow with support for more devices getting added. + * + */ +enum periph_id { + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_SROMC, + PERIPH_ID_UART0, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h new file mode 100644 index 0000000000..10ea736c7d --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan <a.kesavan@samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +#endif diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index 6444fd04ec..e5467e242d 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -225,6 +225,628 @@ struct exynos4_power { unsigned int gps_alive_status; unsigned int gps_alive_option; }; + +struct exynos5_power { + unsigned int om_stat; + unsigned char res1[0x18]; + unsigned int rtc_clko_sel; + unsigned int gnss_rtc_out_ctrl; + unsigned char res2[0x1dc]; + unsigned int central_seq_configuration; + unsigned int central_seq_status; + unsigned int central_seq_option; + unsigned char res3[0x14]; + unsigned int seq_transition0; + unsigned int seq_transition1; + unsigned int seq_transition2; + unsigned int seq_transition3; + unsigned int seq_transition4; + unsigned int seq_transition5; + unsigned int seq_transition6; + unsigned int seq_transition7; + unsigned int central_seq_dmc_configuration; + unsigned int central_seq_dmc_status; + unsigned int central_seq_dmc_option; + unsigned char res4[0x14]; + unsigned int seq_dmc_transition0; + unsigned int seq_dmc_transition1; + unsigned int seq_dmc_transition2; + unsigned int seq_dmc_transition3; + unsigned int seq_dmc_transition4; + unsigned int seq_dmc_transition5; + unsigned int seq_dmc_transition6; + unsigned int seq_dmc_transition7; + unsigned char res5[0x180]; + unsigned int swreset; + unsigned int rst_stat; + unsigned int automatic_wdt_reset_disable; + unsigned int mask_wdt_reset_request; + unsigned int mask_wreset_request; + unsigned char res6[0xec]; + unsigned int reset_sequencer_configuration; + unsigned int reset_sequencer_status; + unsigned int reset_sequencer_option; + unsigned char res7[0xf4]; + unsigned int wakeup_stat; + unsigned int eint_wakeup_mask; + unsigned int wakeup_mask; + unsigned int wakeup_interrupt; + unsigned char res8[0x10]; + unsigned int wakeup_stat_dmc; + unsigned int eint_wakeup_mask_dmc; + unsigned int wakeup_mask_dmc; + unsigned int wakeup_interrupt_dmc; + unsigned char res9[0xd0]; + unsigned int hdmi_phy_control; + unsigned int usbdrd_phy_control; + unsigned int usbhost_phy_control; + unsigned int efnand_phy_control; + unsigned int mipi_phy0_control; + unsigned int mipi_phy1_control; + unsigned int adc_phy_control; + unsigned int mtcadc_phy_control; + unsigned int dptx_phy_control; + unsigned int sata_phy_control; + unsigned char res10[0xd8]; + unsigned int inform0; + unsigned int inform1; + unsigned int inform2; + unsigned int inform3; + unsigned int sysip_dat0; + unsigned int sysip_dat1; + unsigned int sysip_dat2; + unsigned int sysip_dat3; + unsigned char res11[0xe0]; + unsigned int pmu_spare0; + unsigned int pmu_spare1; + unsigned int pmu_spare2; + unsigned int pmu_spare3; + unsigned char res12[0x70]; + unsigned int irom_data_reg0; + unsigned int irom_data_reg1; + unsigned int irom_data_reg2; + unsigned int irom_data_reg3; + unsigned char res13[0x70]; + unsigned int pmu_debug; + unsigned char res14[0x5fc]; + unsigned int arm_core0_sys_pwr_reg; + unsigned int dis_irq_arm_core0_local_sys_pwr_reg; + unsigned int dis_irq_arm_core0_central_sys_pwr_reg; + unsigned char res15[0x4]; + unsigned int arm_core1_sys_pwr_reg; + unsigned int dis_irq_arm_core1_local_sys_pwr_reg; + unsigned int dis_irq_arm_core1_central_sys_pwr_reg; + unsigned char res16[0x24]; + unsigned int fsys_arm_sys_pwr_reg; + unsigned int dis_irq_fsys_arm_local_sys_pwr_reg; + unsigned int dis_irq_fsys_arm_central_sys_pwr_reg; + unsigned char res17[0x4]; + unsigned int isp_arm_sys_pwr_reg; + unsigned int dis_irq_isp_arm_local_sys_pwr_reg; + unsigned int dis_irq_isp_arm_central_sys_pwr_reg; + unsigned char res18[0x24]; + unsigned int arm_common_sys_pwr_reg; + unsigned char res19[0x3c]; + unsigned int arm_l2_sys_pwr_reg; + unsigned char res20[0x3c]; + unsigned int cmu_aclkstop_sys_pwr_reg; + unsigned int cmu_sclkstop_sys_pwr_reg; + unsigned char res21[0x4]; + unsigned int cmu_reset_sys_pwr_reg; + unsigned char res22[0x10]; + unsigned int cmu_aclkstop_dmc_sys_pwr_reg; + unsigned int cmu_sclkstop_dmc_sys_pwr_reg; + unsigned char res23[0x4]; + unsigned int cmu_reset_dmc_sys_pwr_reg; + unsigned char res24[0x8]; + unsigned int ddrphy_dlllock_sys_pwr_reg; + unsigned char res25[0x4]; + unsigned int apll_sysclk_sys_pwr_reg; + unsigned int mpll_sysclk_sys_pwr_reg; + unsigned int vpll_sysclk_sys_pwr_reg; + unsigned int epll_sysclk_sys_pwr_reg; + unsigned int bpll_sysclk_sys_pwr_reg; + unsigned int cpll_sysclk_sys_pwr_reg; + unsigned int gpll_sysclk_sys_pwr_reg; + unsigned char res26[0x8]; + unsigned int mplluser_sysclk_sys_pwr_reg; + unsigned char res27[0x8]; + unsigned int bplluser_sysclk_sys_pwr_reg; + unsigned char res28[0xc]; + unsigned int top_bus_sys_pwr_reg; + unsigned int top_retention_sys_pwr_reg; + unsigned int top_pwr_sys_pwr_reg; + unsigned char res29[0x4]; + unsigned int top_bus_dmc_sys_pwr_reg; + unsigned int top_retention_dmc_sys_pwr_reg; + unsigned int top_pwr_dmc_sys_pwr_reg; + unsigned char res30[0x4]; + unsigned int logic_reset_sys_pwr_reg; + unsigned int oscclk_gate_sys_pwr_reg; + unsigned char res31[0x8]; + unsigned int logic_reset_dmc_sys_pwr_reg; + unsigned int oscclk_gate_dmc_sys_pwr_reg; + unsigned char res32[0x8]; + unsigned int usbotg_mem_sys_pwr_reg; + unsigned char res33[0x4]; + unsigned int g2d_mem_sys_pwr_reg; + unsigned int usbdrd_mem_sys_pwr_reg; + unsigned int efnand_mem_sys_pwr_reg; + unsigned int cssys_mem_sys_pwr_reg; + unsigned int secss_mem_sys_pwr_reg; + unsigned int rotator_mem_sys_pwr_reg; + unsigned int intram_mem_sys_pwr_reg; + unsigned int introm_mem_sys_pwr_reg; + unsigned int jpeg_mem_sys_pwr_reg; + unsigned int hsi_mem_sys_pwr_reg; + unsigned char res34[0x4]; + unsigned int mcuiop_mem_sys_pwr_reg; + unsigned char res35[0x4]; + unsigned int sata_mem_sys_pwr_reg; + unsigned int pad_retention_dram_sys_pwr_reg; + unsigned int pad_retention_mau_sys_pwr_reg; + unsigned int pad_retention_jtag_sys_pwr_reg; + unsigned char res36[0xc]; + unsigned int pad_retention_mmc2_sys_pwr_reg; + unsigned int pad_retention_mmc3_sys_pwr_reg; + unsigned int pad_retention_gpio_sys_pwr_reg; + unsigned int pad_retention_uart_sys_pwr_reg; + unsigned int pad_retention_mmc0_sys_pwr_reg; + unsigned int pad_retention_mmc1_sys_pwr_reg; + unsigned int pad_retention_ebia_sys_pwr_reg; + unsigned int pad_retention_ebib_sys_pwr_reg; + unsigned int pad_retention_spi_sys_pwr_reg; + unsigned int pad_retention_gpio_dmc_sys_pwr_reg; + unsigned int pad_isolation_sys_pwr_reg; + unsigned char res37[0xc]; + unsigned int pad_isolation_dmc_sys_pwr_reg; + unsigned char res38[0xc]; + unsigned int pad_alv_sel_sys_pwr_reg; + unsigned char res39[0x20]; + unsigned int xxti_sys_pwr_reg; + unsigned char res40[0x38]; + unsigned int ext_regulator_sys_pwr_reg; + unsigned char res41[0x3c]; + unsigned int gpio_mode_sys_pwr_reg; + unsigned char res42[0x1c]; + unsigned int gpio_mode_dmc_sys_pwr_reg; + unsigned char res43[0x1c]; + unsigned int gpio_mode_mau_sys_pwr_reg; + unsigned int top_asb_reset_sys_pwr_reg; + unsigned int top_asb_isolation_sys_pwr_reg; + unsigned char res44[0xb4]; + unsigned int gscl_sys_pwr_reg; + unsigned int isp_sys_pwr_reg; + unsigned int mfc_sys_pwr_reg; + unsigned int g3d_sys_pwr_reg; + unsigned char res45[0x4]; + unsigned int disp1_sys_pwr_reg; + unsigned int mau_sys_pwr_reg; + unsigned char res46[0x64]; + unsigned int cmu_clkstop_gscl_sys_pwr_reg; + unsigned int cmu_clkstop_isp_sys_pwr_reg; + unsigned int cmu_clkstop_mfc_sys_pwr_reg; + unsigned int cmu_clkstop_g3d_sys_pwr_reg; + unsigned char res47[0x4]; + unsigned int cmu_clkstop_disp1_sys_pwr_reg; + unsigned int cmu_clkstop_mau_sys_pwr_reg; + unsigned char res48[0x24]; + unsigned int cmu_sysclk_gscl_sys_pwr_reg; + unsigned int cmu_sysclk_isp_sys_pwr_reg; + unsigned int cmu_sysclk_mfc_sys_pwr_reg; + unsigned int cmu_sysclk_g3d_sys_pwr_reg; + unsigned char res49[0x4]; + unsigned int cmu_sysclk_disp1_sys_pwr_reg; + unsigned int cmu_sysclk_mau_sys_pwr_reg; + unsigned char res50[0xa4]; + unsigned int cmu_reset_gscl_sys_pwr_reg; + unsigned int cmu_reset_isp_sys_pwr_reg; + unsigned int cmu_reset_mfc_sys_pwr_reg; + unsigned int cmu_reset_g3d_sys_pwr_reg; + unsigned char res51[0x4]; + unsigned int cmu_reset_disp1_sys_pwr_reg; + unsigned int cmu_reset_mau_sys_pwr_reg; + unsigned char res52[0xa64]; + unsigned int arm_core0_configuration; + unsigned int arm_core0_status; + unsigned int arm_core0_option; + unsigned char res53[0x14]; + unsigned int dis_irq_arm_core0_local_configuration; + unsigned int dis_irq_arm_core0_local_status; + unsigned int dis_irq_arm_core0_local_option; + unsigned char res54[0x14]; + unsigned int dis_irq_arm_core0_central_configuration; + unsigned int dis_irq_arm_core0_central_status; + unsigned int dis_irq_arm_core0_central_option; + unsigned char res55[0x34]; + unsigned int arm_core1_configuration; + unsigned int arm_core1_status; + unsigned int arm_core1_option; + unsigned char res56[0x14]; + unsigned int dis_irq_arm_core1_local_configuration; + unsigned int dis_irq_arm_core1_local_status; + unsigned int dis_irq_arm_core1_local_option; + unsigned char res57[0x14]; + unsigned int dis_irq_arm_core1_central_configuration; + unsigned int dis_irq_arm_core1_central_status; + unsigned int dis_irq_arm_core1_central_option; + unsigned char res58[0x134]; + unsigned int fsys_arm_configuration; + unsigned int fsys_arm_status; + unsigned int fsys_arm_option; + unsigned char res59[0x14]; + unsigned int dis_irq_fsys_arm_local_configuration; + unsigned int dis_irq_fsys_arm_local_status; + unsigned int dis_irq_fsys_arm_local_option; + unsigned char res60[0x14]; + unsigned int dis_irq_fsys_arm_central_configuration; + unsigned int dis_irq_fsys_arm_central_status; + unsigned int dis_irq_fsys_arm_central_option; + unsigned char res61[0x34]; + unsigned int isp_arm_configuration; + unsigned int isp_arm_status; + unsigned int isp_arm_option; + unsigned char res62[0x14]; + unsigned int dis_irq_isp_arm_local_configuration; + unsigned int dis_irq_isp_arm_local_status; + unsigned int dis_irq_isp_arm_local_option; + unsigned char res63[0x14]; + unsigned int dis_irq_isp_arm_central_configuration; + unsigned int dis_irq_isp_arm_central_status; + unsigned int dis_irq_isp_arm_central_option; + unsigned char res64[0x134]; + unsigned int arm_common_configuration; + unsigned int arm_common_status; + unsigned int arm_common_option; + unsigned char res65[0x1f4]; + unsigned int arm_l2_configuration; + unsigned int arm_l2_status; + unsigned int arm_l2_option; + unsigned char res66[0x1f4]; + unsigned int cmu_aclkstop_configuration; + unsigned int cmu_aclkstop_status; + unsigned int cmu_aclkstop_option; + unsigned char res67[0x14]; + unsigned int cmu_sclkstop_configuration; + unsigned int cmu_sclkstop_status; + unsigned int cmu_sclkstop_option; + unsigned char res68[0x34]; + unsigned int cmu_reset_configuration; + unsigned int cmu_reset_status; + unsigned int cmu_reset_option; + unsigned char res69[0x94]; + unsigned int cmu_aclkstop_dmc_configuration; + unsigned int cmu_aclkstop_dmc_status; + unsigned int cmu_aclkstop_dmc_option; + unsigned char res70[0x14]; + unsigned int cmu_sclkstop_dmc_configuration; + unsigned int cmu_sclkstop_dmc_status; + unsigned int cmu_sclkstop_dmc_option; + unsigned char res71[0x34]; + unsigned int cmu_reset_dmc_configuration; + unsigned int cmu_reset_dmc_status; + unsigned int cmu_reset_dmc_option; + unsigned char res72[0x54]; + unsigned int ddrphy_dlllock_configuration; + unsigned int ddrphy_dlllock_status; + unsigned int ddrphy_dlllock_option; + unsigned char res73[0x34]; + unsigned int apll_sysclk_configuration; + unsigned int apll_sysclk_status; + unsigned int apll_sysclk_option; + unsigned char res74[0x18]; + unsigned int mpll_sysclk_status; + unsigned int mpll_sysclk_option; + unsigned char res75[0x14]; + unsigned int vpll_sysclk_configuration; + unsigned int vpll_sysclk_status; + unsigned int vpll_sysclk_option; + unsigned char res76[0x14]; + unsigned int epll_sysclk_configuration; + unsigned int epll_sysclk_status; + unsigned int epll_sysclk_option; + unsigned char res77[0x14]; + unsigned int bpll_sysclk_configuration; + unsigned int bpll_sysclk_status; + unsigned int bpll_sysclk_option; + unsigned char res78[0x14]; + unsigned int cpll_sysclk_configuration; + unsigned int cpll_sysclk_status; + unsigned int cpll_sysclk_option; + unsigned char res79[0x14]; + unsigned int gpll_sysclk_configuration; + unsigned int gpll_sysclk_status; + unsigned int gpll_sysclk_option; + unsigned char res80[0x54]; + unsigned int mplluser_sysclk_configuration; + unsigned int mplluser_sysclk_status; + unsigned int mplluser_sysclk_option; + unsigned char res81[0x54]; + unsigned int bplluser_sysclk_configuration; + unsigned int bplluser_sysclk_status; + unsigned int bplluser_sysclk_option; + unsigned char res82[0x74]; + unsigned int top_bus_configuration; + unsigned int top_bus_status; + unsigned int top_bus_option; + unsigned char res83[0x14]; + unsigned int top_retention_configuration; + unsigned int top_retention_status; + unsigned int top_retention_option; + unsigned char res84[0x14]; + unsigned int top_pwr_configuration; + unsigned int top_pwr_status; + unsigned int top_pwr_option; + unsigned char res85[0x34]; + unsigned int top_bus_dmc_configuration; + unsigned int top_bus_dmc_status; + unsigned int top_bus_dmc_option; + unsigned char res86[0x14]; + unsigned int top_retention_dmc_configuration; + unsigned int top_retention_dmc_status; + unsigned int top_retention_dmc_option; + unsigned char res87[0x14]; + unsigned int top_pwr_dmc_configuration; + unsigned int top_pwr_dmc_status; + unsigned int top_pwr_dmc_option; + unsigned char res88[0x34]; + unsigned int logic_reset_configuration; + unsigned int logic_reset_status; + unsigned int logic_reset_option; + unsigned char res89[0x14]; + unsigned int oscclk_gate_configuration; + unsigned int oscclk_gate_status; + unsigned int oscclk_gate_option; + unsigned char res90[0x54]; + unsigned int logic_reset_dmc_configuration; + unsigned int logic_reset_dmc_status; + unsigned int logic_reset_dmc_option; + unsigned char res91[0x14]; + unsigned int oscclk_gate_dmc_configuration; + unsigned int oscclk_gate_dmc_status; + unsigned int oscclk_gate_dmc_option; + unsigned char res92[0x54]; + unsigned int usbotg_mem_configuration; + unsigned int usbotg_mem_status; + unsigned int usbotg_mem_option; + unsigned char res93[0x34]; + unsigned int g2d_mem_configuration; + unsigned int g2d_mem_status; + unsigned int g2d_mem_option; + unsigned char res94[0x14]; + unsigned int usbdrd_mem_configuration; + unsigned int usbdrd_mem_status; + unsigned int usbdrd_mem_option; + unsigned char res95[0x14]; + unsigned int efnand_mem_configuration; + unsigned int efnand_mem_status; + unsigned int efnand_mem_option; + unsigned char res96[0x14]; + unsigned int cssys_mem_configuration; + unsigned int cssys_mem_status; + unsigned int cssys_mem_option; + unsigned char res97[0x14]; + unsigned int secss_mem_configuration; + unsigned int secss_mem_status; + unsigned int secss_mem_option; + unsigned char res98[0x14]; + unsigned int rotator_mem_configuration; + unsigned int rotator_mem_status; + unsigned int rotator_mem_option; + unsigned char res99[0x14]; + unsigned int intram_mem_configuration; + unsigned int intram_mem_status; + unsigned int intram_mem_option; + unsigned char res100[0x14]; + unsigned int introm_mem_configuration; + unsigned int introm_mem_status; + unsigned int introm_mem_option; + unsigned char res101[0x14]; + unsigned int jpeg_mem_configuration; + unsigned int jpeg_mem_status; + unsigned int jpeg_mem_option; + unsigned char res102[0x14]; + unsigned int hsi_mem_configuration; + unsigned int hsi_mem_status; + unsigned int hsi_mem_option; + unsigned char res103[0x34]; + unsigned int mcuiop_mem_configuration; + unsigned int mcuiop_mem_status; + unsigned int mcuiop_mem_option; + unsigned char res104[0x14]; + unsigned int sata_mem_configuration; + unsigned int sata_mem_status; + unsigned int sata_mem_option; + unsigned char res105[0x34]; + unsigned int pad_retention_dram_configuration; + unsigned int pad_retention_dram_status; + unsigned int pad_retention_dram_option; + unsigned char res106[0x14]; + unsigned int pad_retention_mau_configuration; + unsigned int pad_retention_mau_status; + unsigned int pad_retention_mau_option; + unsigned char res107[0x14]; + unsigned int pad_retention_jtag_configuration; + unsigned int pad_retention_jtag_status; + unsigned int pad_retention_jtag_option; + unsigned char res108[0x74]; + unsigned int pad_retention_mmc2_configuration; + unsigned int pad_retention_mmc2_status; + unsigned int pad_retention_mmc2_option; + unsigned char res109[0x14]; + unsigned int pad_retention_mmc3_configuration; + unsigned int pad_retention_mmc3_status; + unsigned int pad_retention_mmc3_option; + unsigned char res110[0x14]; + unsigned int pad_retention_gpio_configuration; + unsigned int pad_retention_gpio_status; + unsigned int pad_retention_gpio_option; + unsigned char res111[0x14]; + unsigned int pad_retention_uart_configuration; + unsigned int pad_retention_uart_status; + unsigned int pad_retention_uart_option; + unsigned char res112[0x14]; + unsigned int pad_retention_mmc0_configuration; + unsigned int pad_retention_mmc0_status; + unsigned int pad_retention_mmc0_option; + unsigned char res113[0x14]; + unsigned int pad_retention_mmc1_configuration; + unsigned int pad_retention_mmc1_status; + unsigned int pad_retention_mmc1_option; + unsigned char res114[0x14]; + unsigned int pad_retention_ebia_configuration; + unsigned int pad_retention_ebia_status; + unsigned int pad_retention_ebia_option; + unsigned char res115[0x14]; + unsigned int pad_retention_ebib_configuration; + unsigned int pad_retention_ebib_status; + unsigned int pad_retention_ebib_option; + unsigned char res116[0x14]; + unsigned int pad_retention_spi_configuration; + unsigned int pad_retention_spi_status; + unsigned int pad_retention_spi_option; + unsigned char res117[0x14]; + unsigned int pad_retention_gpio_dmc_configuration; + unsigned int pad_retention_gpio_dmc_status; + unsigned int pad_retention_gpio_dmc_option; + unsigned char res118[0x14]; + unsigned int pad_isolation_configuration; + unsigned int pad_isolation_status; + unsigned int pad_isolation_option; + unsigned char res119[0x74]; + unsigned int pad_isolation_dmc_configuration; + unsigned int pad_isolation_dmc_status; + unsigned int pad_isolation_dmc_option; + unsigned char res120[0x74]; + unsigned int pad_alv_sel_configuration; + unsigned int pad_alv_sel_status; + unsigned int pad_alv_sel_option0; + unsigned int ps_hold_control; + unsigned char res130[0x110]; + unsigned int xxti_configuration; + unsigned int xxti_status; + unsigned int xxti_option; + unsigned char res131[0x10]; + unsigned int xxti_duration3; + unsigned char res132[0x1c0]; + unsigned int ext_regulator_configuration; + unsigned int ext_regulator_status; + unsigned int ext_regulator_option; + unsigned char res133[0x10]; + unsigned int ext_regulator_duration3; + unsigned char res134[0x1e0]; + unsigned int gpio_mode_configuration; + unsigned int gpio_mode_status; + unsigned int gpio_mode_option; + unsigned char res135[0xf4]; + unsigned int gpio_mode_dmc_configuration; + unsigned int gpio_mode_dmc_status; + unsigned int gpio_mode_dmc_option; + unsigned char res136[0xd4]; + unsigned int gpio_mode_mau_configuration; + unsigned int gpio_mode_mau_status; + unsigned int gpio_mode_mau_option; + unsigned char res137[0x14]; + unsigned int top_asb_reset_configuration; + unsigned int top_asb_reset_status; + unsigned int top_asb_reset_option; + unsigned char res138[0x14]; + unsigned int top_asb_isolation_configuration; + unsigned int top_asb_isolation_status; + unsigned int top_asb_isolation_option; + unsigned char res139[0x5d4]; + unsigned int gscl_configuration; + unsigned int gscl_status; + unsigned int gscl_option; + unsigned char res140[0x14]; + unsigned int isp_configuration; + unsigned int isp_status; + unsigned int isp_option; + unsigned char res141[0x14]; + unsigned int mfc_configuration; + unsigned int mfc_status; + unsigned int mfc_option; + unsigned char res142[0x14]; + unsigned int g3d_configuration; + unsigned int g3d_status; + unsigned int g3d_option; + unsigned char res143[0x34]; + unsigned int disp1_configuration; + unsigned int disp1_status; + unsigned int disp1_option; + unsigned char res144[0x14]; + unsigned int mau_configuration; + unsigned int mau_status; + unsigned int mau_option; + unsigned char res145[0x334]; + unsigned int cmu_clkstop_gscl_configuration; + unsigned int cmu_clkstop_gscl_status; + unsigned int cmu_clkstop_gscl_option; + unsigned char res146[0x14]; + unsigned int cmu_clkstop_isp_configuration; + unsigned int cmu_clkstop_isp_status; + unsigned int cmu_clkstop_isp_option; + unsigned char res147[0x14]; + unsigned int cmu_clkstop_mfc_configuration; + unsigned int cmu_clkstop_mfc_status; + unsigned int cmu_clkstop_mfc_option; + unsigned char res148[0x14]; + unsigned int cmu_clkstop_g3d_configuration; + unsigned int cmu_clkstop_g3d_status; + unsigned int cmu_clkstop_g3d_option; + unsigned char res149[0x34]; + unsigned int cmu_clkstop_disp1_configuration; + unsigned int cmu_clkstop_disp1_status; + unsigned int cmu_clkstop_disp1_option; + unsigned char res150[0x14]; + unsigned int cmu_clkstop_mau_configuration; + unsigned int cmu_clkstop_mau_status; + unsigned int cmu_clkstop_mau_option; + unsigned char res151[0x134]; + unsigned int cmu_sysclk_gscl_configuration; + unsigned int cmu_sysclk_gscl_status; + unsigned int cmu_sysclk_gscl_option; + unsigned char res152[0x18]; + unsigned int cmu_sysclk_isp_status; + unsigned int cmu_sysclk_isp_option; + unsigned char res153[0x18]; + unsigned int cmu_sysclk_mfc_status; + unsigned int cmu_sysclk_mfc_option; + unsigned char res154[0x18]; + unsigned int cmu_sysclk_g3d_status; + unsigned int cmu_sysclk_g3d_option; + unsigned char res155[0x38]; + unsigned int cmu_sysclk_disp1_status; + unsigned int cmu_sysclk_disp1_option; + unsigned char res156[0x18]; + unsigned int cmu_sysclk_mau_status; + unsigned int cmu_sysclk_mau_option; + unsigned char res157[0x534]; + unsigned int cmu_reset_gscl_configuration; + unsigned int cmu_reset_gscl_status; + unsigned int cmu_reset_gscl_option; + unsigned char res158[0x14]; + unsigned int cmu_reset_isp_configuration; + unsigned int cmu_reset_isp_status; + unsigned int cmu_reset_isp_option; + unsigned char res159[0x14]; + unsigned int cmu_reset_mfc_configuration; + unsigned int cmu_reset_mfc_status; + unsigned int cmu_reset_mfc_option; + unsigned char res160[0x14]; + unsigned int cmu_reset_g3d_configuration; + unsigned int cmu_reset_g3d_status; + unsigned int cmu_reset_g3d_option; + unsigned char res161[0x34]; + unsigned int cmu_reset_disp1_configuration; + unsigned int cmu_reset_disp1_status; + unsigned int cmu_reset_disp1_option; + unsigned char res162[0x14]; + unsigned int cmu_reset_mau_configuration; + unsigned int cmu_reset_mau_status; + unsigned int cmu_reset_mau_option; + unsigned char res163[0x24]; +}; #endif /* __ASSEMBLY__ */ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); @@ -233,4 +855,8 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) #define EXYNOS_MIPI_PHY_MRESETN (1 << 2) +void set_usbhost_phy_ctrl(unsigned int enable); + +#define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) +#define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) #endif diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index c85f949da4..42e1d21e53 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -42,12 +42,16 @@ struct exynos5_sysreg { unsigned int reserved; unsigned int ispblk_cfg; unsigned int usb20phy_cfg; + unsigned char res2[0x29c]; unsigned int mipi_dphy; unsigned int dptx_dphy; unsigned int phyclk_sel; }; #endif +#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) + +void set_usbhost_mode(unsigned int mode); void set_system_display_ctrl(void); #endif /* _EXYNOS4_SYSTEM_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 91164eb402..a9499b70cd 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -82,9 +82,15 @@ #ifdef CONFIG_CMD_SF #define CONFIG_HARD_SPI 1 #define CONFIG_KIRKWOOD_SPI 1 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */ +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif #endif /* diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h index b3c090edcd..8e50ee7f14 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/include/asm/arch-kirkwood/mpp.h @@ -312,6 +312,6 @@ #define MPP_MAX 49 -void kirkwood_mpp_conf(unsigned int *mpp_list); +void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save); #endif diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-kirkwood/spi.h index 1d5043f94f..c79bed7ed9 100644 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ b/arch/arm/include/asm/arch-kirkwood/spi.h @@ -37,6 +37,17 @@ struct kwspi_registers { u32 irq_mask; /* 0x10614 */ }; +/* They are used to define CONFIG_SYS_KW_SPI_MPP + * each of the below #defines selects which mpp is + * configured for each SPI signal in spi_claim_bus + * bit 0: selects pin for MOSI (MPP1 if 0, MPP6 if 1) + * bit 1: selects pin for SCK (MPP2 if 0, MPP10 if 1) + * bit 2: selects pin for MISO (MPP3 if 0, MPP11 if 1) + */ +#define MOSI_MPP6 (1 << 0) +#define SCK_MPP10 (1 << 1) +#define MISO_MPP11 (1 << 2) + #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h index 94b512d18a..d2e19538af 100644 --- a/arch/arm/include/asm/arch-mx28/regs-common.h +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -70,7 +70,7 @@ struct mx28_register_32 { #define mx28_reg_8(name) \ union { \ struct { __mx28_reg_8(name) }; \ - struct mx28_register_32 name##_reg; \ + struct mx28_register_8 name##_reg; \ }; #define mx28_reg_32(name) \ diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 6454acbd42..7ddbbd627c 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -606,6 +606,13 @@ struct esdc_regs { #define UART4_BASE 0x43FB0000 #define UART5_BASE 0x43FB4000 +#define I2C1_BASE_ADDR 0x43f80000 +#define I2C1_CLK_OFFSET 26 +#define I2C2_BASE_ADDR 0x43F98000 +#define I2C2_CLK_OFFSET 28 +#define I2C3_BASE_ADDR 0x43f84000 +#define I2C3_CLK_OFFSET 30 + #define ESDCTL_SDE (1 << 31) #define ESDCTL_CMD_RW (0 << 28) #define ESDCTL_CMD_PRECHARGE (1 << 28) diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h index e570ad1e36..314600621c 100644 --- a/arch/arm/include/asm/arch-mx35/imx-regs.h +++ b/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -39,7 +39,7 @@ #define MAX_BASE_ADDR 0x43F04000 #define EVTMON_BASE_ADDR 0x43F08000 #define CLKCTL_BASE_ADDR 0x43F0C000 -#define I2C_BASE_ADDR 0x43F80000 +#define I2C1_BASE_ADDR 0x43F80000 #define I2C3_BASE_ADDR 0x43F84000 #define ATA_BASE_ADDR 0x43F8C000 #define UART1_BASE 0x43F90000 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 88fb7cb63d..8117f4f91a 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -50,8 +50,6 @@ #error "CPU_TYPE not defined" #endif -#define IPU_CTRL_BASE_ADDR IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET - #define IRAM_SIZE 0x00020000 /* 128 KB */ /* diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index e165810ddc..5d77603ebf 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -73,6 +73,9 @@ #define MMDC1_ARB_BASE_ADDR 0x80000000 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR +#define IPU_SOC_OFFSET 0x00200000 + /* Defines for Blocks connected via AIPS (SkyBlue) */ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR diff --git a/arch/arm/include/asm/arch-mx6/mx6x_pins.h b/arch/arm/include/asm/arch-mx6/mx6x_pins.h index afaa068bb9..cf9103c3d2 100644 --- a/arch/arm/include/asm/arch-mx6/mx6x_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h @@ -48,8 +48,8 @@ #define PAD_CTL_SRE_FAST (1 << 0) #define PAD_CTL_SRE_SLOW (0 << 0) -#define NO_MUX_I 0x3FF -#define NO_PAD_I 0x7FF +#define NO_MUX_I 0 +#define NO_PAD_I 0 enum { MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0), @@ -530,8 +530,8 @@ enum { MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0), MX6Q_PAD_EIM_BCLK__GPIO_6_31 = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0), MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0), - MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), + MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0), + MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0), MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0), MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0), MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 457f99d2c5..5683e16177 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -479,6 +479,8 @@ struct prm { #define PRM_RSTCTRL 0x48307250 #define PRM_RSTCTRL_RESET 0x04 +#define PRM_RSTST 0x48307258 +#define PRM_RSTST_WARM_RESET_MASK 0x7D2 #define SYSCLKDIV_1 (0x1 << 6) #define SYSCLKDIV_2 (0x1 << 7) diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 2a89e56534..9e52b12aa2 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -74,4 +74,5 @@ void power_init_r(void); void dieid_num_r(void); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap3_gp_romcode_call(u32 service_id, u32 parameter); +u32 warm_reset(void); #endif diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 617729c32b..be20fc0ce6 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -525,6 +525,11 @@ struct omap4_scrm_regs { #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index feddb7de51..a8c4c60c8c 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -178,5 +178,7 @@ struct watchdog { #define PRM_RSTCTRL PRM_DEVICE_BASE #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x07EA #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 47c5883025..03bd923145 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -112,7 +112,7 @@ #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C #define LPDDR2IO_GR10_WD_MASK (3 << 17) -#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index c6e3ad26ff..d633573c25 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -57,6 +57,8 @@ void init_omap_revision(void); void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); /* * This is used to verify if the configuration header * was executed by Romcode prior to control of transfer diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index f32cf3eeef..5f1a7aa770 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -480,6 +480,13 @@ struct omap5_prcm_regs { u32 pad217[4]; u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ + u32 pad218[2]; + u32 prm_sldo_core_setup; /* 4ae07bc4 */ + u32 prm_sldo_core_ctrl; /* 4ae07bc8 */ + u32 prm_sldo_mpu_setup; /* 4ae07bcc */ + u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */ + u32 prm_sldo_mm_setup; /* 4ae07bd4 */ + u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */ }; /* DPLL register offsets */ @@ -490,6 +497,11 @@ struct omap5_prcm_regs { #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ +/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) @@ -641,6 +653,9 @@ struct omap5_prcm_regs { #define VDD_MPU 1000 #define VDD_MM 1000 #define VDD_CORE 1040 +#define VDD_MPU_5432 1150 +#define VDD_MM_5432 1150 +#define VDD_CORE_5432 1150 /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 8ef17c9a14..5e62013236 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -182,5 +182,7 @@ struct watchdog { #define PRM_RSTCTRL PRM_DEVICE_BASE #define PRM_RSTCTRL_RESET 0x01 +#define PRM_RSTST (PRM_DEVICE_BASE + 0x4) +#define PRM_RSTST_WARM_RESET_MASK 0x7FEA #endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index e3f55d2020..7f05cb5b4a 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -40,7 +40,7 @@ #define OMAP54XX_L4_PER_BASE 0x48000000 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END @@ -56,7 +56,8 @@ #define CONTROL_ID_CODE (CTRL_BASE + 0x204) /* To be verified */ -#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F /* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) @@ -178,7 +179,14 @@ struct omap_sys_ctrl_regs { u32 control_srcomp_east_side; /*0x4A002E7C*/ u32 control_srcomp_west_side; /*0x4A002E80*/ u32 control_srcomp_code_latch; /*0x4A002E84*/ - u32 pad4[3680198]; + u32 pad4[3679394]; + u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ + u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ + u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ + u32 pad5[10]; + u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ + u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ + u32 pad6[789]; u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ u32 control_padconf_mode; /* 0x4AE0CDA8 */ @@ -233,6 +241,12 @@ struct omap_sys_ctrl_regs { #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000 +#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 + #define EFUSE_1 0x45145100 #define EFUSE_2 0x45145100 #define EFUSE_3 0x45145100 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 8396a22141..74feb90277 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -57,6 +57,8 @@ void init_omap_revision(void); void do_io_settings(void); void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); +u32 warm_reset(void); +void force_emif_self_refresh(void); /* * This is used to verify if the configuration header diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index 510ead4d99..2362b9985b 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -23,6 +23,7 @@ #ifndef _S5PC1XX_CPU_H #define _S5PC1XX_CPU_H +#define S5P_CPU_NAME "S5P" #define S5PC1XX_ADDR_BASE 0xE0000000 /* S5PC100 */ @@ -71,6 +72,11 @@ static inline void s5p_set_cpu_id(void) s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); } +static inline char *s5p_get_cpu_name(void) +{ + return S5P_CPU_NAME; +} + #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ diff --git a/board/avionic-design/common/tamonten.h b/arch/arm/include/asm/arch-spear/clk.h index 0e60b0fadc..a45ec1861c 100644 --- a/board/avionic-design/common/tamonten.h +++ b/arch/arm/include/asm/arch-spear/clk.h @@ -1,8 +1,6 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011 - * Avionic Design GmbH <www.avionic-design.de> + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> * * See file CREDITS for list of people who contributed to this * project. @@ -14,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -23,10 +21,7 @@ * MA 02111-1307 USA */ -#ifndef _TAMONTEN_H_ -#define _TAMONTEN_H_ - -void tegra2_start(void); -void gpio_config_mmc(void); - -#endif /* TAMONTEN_H */ +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return 83000000; +} diff --git a/arch/arm/include/asm/arch-spear/gpio.h b/arch/arm/include/asm/arch-spear/gpio.h new file mode 100644 index 0000000000..c3697de8c5 --- /dev/null +++ b/arch/arm/include/asm/arch-spear/gpio.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#ifndef __ASM_ARCH_SPEAR_GPIO_H +#define __ASM_ARCH_SPEAR_GPIO_H + +enum gpio_direction { + GPIO_DIRECTION_IN, + GPIO_DIRECTION_OUT, +}; + +struct gpio_regs { + u32 gpiodata[0x100]; /* 0x000 ... 0x3fc */ + u32 gpiodir; /* 0x400 */ +}; + +#define SPEAR_GPIO_COUNT 8 +#define DATA_REG_ADDR(gpio) (1 << (gpio + 2)) + +#endif /* __ASM_ARCH_SPEAR_GPIO_H */ diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 818f36cc66..81509119dd 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -24,43 +24,68 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H -#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) -#define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) -#define CONFIG_SPEAR_TIMERBASE (0xFC800000) -#define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SYS_USBD_BASE 0xE1100000 +#define CONFIG_SYS_PLUG_BASE 0xE1200000 +#define CONFIG_SYS_FIFO_BASE 0xE1000800 +#define CONFIG_SYS_SMI_BASE 0xFC000000 +#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000 +#define CONFIG_SPEAR_TIMERBASE 0xFC800000 +#define CONFIG_SPEAR_MISCBASE 0xFCA80000 +#define CONFIG_SPEAR_ETHBASE 0xE0800000 +#define CONFIG_SPEAR_MPMCBASE 0xFC600000 +#define CONFIG_SSP1_BASE 0xD0100000 +#define CONFIG_SSP2_BASE 0xD0180000 +#define CONFIG_SSP3_BASE 0xD8180000 +#define CONFIG_GPIO_BASE 0xD8100000 #define CONFIG_SYS_NAND_CLE (1 << 16) #define CONFIG_SYS_NAND_ALE (1 << 17) #if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SPEAR_FSMCBASE (0xD1800000) +#define CONFIG_SYS_I2C_BASE 0xD0200000 +#define CONFIG_SYS_FSMC_BASE 0xD1800000 +#define CONFIG_FSMC_NAND_BASE 0xD2000000 + +#define CONFIG_SPEAR_BOOTSTRAPCFG 0xFCA80000 +#define CONFIG_SPEAR_BOOTSTRAPSHFT 16 +#define CONFIG_SPEAR_BOOTSTRAPMASK 0xB +#define CONFIG_SPEAR_ONLYSNORBOOT 0xA +#define CONFIG_SPEAR_NORNANDBOOT 0xB +#define CONFIG_SPEAR_NORNAND8BOOT 0x8 +#define CONFIG_SPEAR_NORNAND16BOOT 0x9 +#define CONFIG_SPEAR_USBBOOT 0x8 + +#define CONFIG_SPEAR_MPMCREGS 100 #elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x94000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x94000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x44000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x44000000 #undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE #define CONFIG_SYS_NAND_CLE (1 << 17) #define CONFIG_SYS_NAND_ALE (1 << 16) -#define CONFIG_SPEAR_EMIBASE (0x4F000000) -#define CONFIG_SPEAR_RASBASE (0xB4000000) +#define CONFIG_SPEAR_EMIBASE 0x4F000000 +#define CONFIG_SPEAR_RASBASE 0xB4000000 + +#define CONFIG_SYS_MACB0_BASE 0xB0000000 +#define CONFIG_SYS_MACB1_BASE 0xB0800000 +#define CONFIG_SYS_MACB2_BASE 0xB1000000 +#define CONFIG_SYS_MACB3_BASE 0xB1800000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x4C000000) +#define CONFIG_SYS_I2C_BASE 0xD0180000 +#define CONFIG_SYS_FSMC_BASE 0x4C000000 + +#define CONFIG_SPEAR_EMIBASE 0x40000000 +#define CONFIG_SPEAR_RASBASE 0xB3000000 -#define CONFIG_SPEAR_EMIBASE (0x40000000) -#define CONFIG_SPEAR_RASBASE (0xB3000000) +#define CONFIG_SYS_MACB0_BASE 0xAA000000 #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear/spr_defs.h b/arch/arm/include/asm/arch-spear/spr_defs.h index fa8412ccfc..71d64a1992 100644 --- a/arch/arm/include/asm/arch-spear/spr_defs.h +++ b/arch/arm/include/asm/arch-spear/spr_defs.h @@ -28,6 +28,23 @@ extern int spear_board_init(ulong); extern void setfreq(unsigned int, unsigned int); extern unsigned int setfreq_sz; +void plat_ddr_init(void); +void soc_init(void); +void spear_late_init(void); +void plat_late_init(void); + +int snor_boot_selected(void); +int nand_boot_selected(void); +int pnor_boot_selected(void); +int usb_boot_selected(void); +int uart_boot_selected(void); +int tftp_boot_selected(void); +int i2c_boot_selected(void); +int spi_boot_selected(void); +int mmc_boot_selected(void); + +extern u32 mpmc_conf_vals[]; + struct chip_data { int cpufreq; int dramfreq; @@ -43,4 +60,10 @@ struct chip_data { #define MAC_OFF 0x2 #define MAC_LEN 0x6 +#define PNOR_WIDTH_8 0 +#define PNOR_WIDTH_16 1 +#define PNOR_WIDTH_32 2 +#define PNOR_WIDTH_NUM 3 +#define PNOR_WIDTH_SEARCH 0xff + #endif diff --git a/arch/arm/include/asm/arch-spear/spr_gpt.h b/arch/arm/include/asm/arch-spear/spr_gpt.h index 965b5abb9a..d95ba52597 100644 --- a/arch/arm/include/asm/arch-spear/spr_gpt.h +++ b/arch/arm/include/asm/arch-spear/spr_gpt.h @@ -79,7 +79,7 @@ struct gpt_regs { #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_SPEAR_HZ (1000) -#define CONFIG_SPEAR_HZ_CLOCK (8300000) +#define CONFIG_SPEAR_HZ 1000 +#define CONFIG_SPEAR_HZ_CLOCK 8300000 #endif diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index 8b96d9b52a..5f67a5fa20 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -37,7 +37,7 @@ struct misc_regs { u32 amba_clk_cfg; /* 0x24 */ u32 periph_clk_cfg; /* 0x28 */ u32 periph1_clken; /* 0x2C */ - u32 periph2_clken; /* 0x30 */ + u32 soc_core_id; /* 0x30 */ u32 ras_clken; /* 0x34 */ u32 periph1_rst; /* 0x38 */ u32 periph2_rst; /* 0x3C */ @@ -46,7 +46,7 @@ struct misc_regs { u32 prsc2_clk_cfg; /* 0x48 */ u32 prsc3_clk_cfg; /* 0x4C */ u32 amem_cfg_ctrl; /* 0x50 */ - u32 port_cfg_ctrl; /* 0x54 */ + u32 expi_clk_cfg; /* 0x54 */ u32 reserved_1; /* 0x58 */ u32 clcd_synth_clk; /* 0x5C */ u32 irda_synth_clk; /* 0x60 */ @@ -101,6 +101,37 @@ struct misc_regs { u32 ras_gpp2_out; /* 0x800C */ }; +/* SYNTH_CLK value*/ +#define SYNTH23 0x00020003 + +/* PLLx_FRQ value */ +#if defined(CONFIG_SPEAR3XX) +#define FREQ_332 0xA600010C +#define FREQ_266 0x8500010C +#elif defined(CONFIG_SPEAR600) +#define FREQ_332 0xA600010F +#define FREQ_266 0x8500010F +#endif + +/* PLL_CTR_REG */ +#define MEM_CLK_SEL_MSK 0x70000000 +#define MEM_CLK_HCLK 0x00000000 +#define MEM_CLK_2HCLK 0x10000000 +#define MEM_CLK_PLL2 0x30000000 + +#define EXPI_CLK_CFG_LOW_COMPR 0x2000 +#define EXPI_CLK_CFG_CLK_EN 0x0400 +#define EXPI_CLK_CFG_RST 0x0200 +#define EXPI_CLK_SYNT_EN 0x0010 +#define EXPI_CLK_CFG_SEL_PLL2 0x0004 +#define EXPI_CLK_CFG_INT_CLK_EN 0x0001 + +#define PLL2_CNTL_6UA 0x1c00 +#define PLL2_CNTL_SAMPLE 0x0008 +#define PLL2_CNTL_ENABLE 0x0004 +#define PLL2_CNTL_RESETN 0x0002 +#define PLL2_CNTL_LOCK 0x0001 + /* AUTO_CFG_REG value */ #define MISC_SOCCFGMSK 0x0000003F #define MISC_SOCCFG30 0x0000000C @@ -110,6 +141,8 @@ struct misc_regs { /* PERIPH_CLK_CFG value */ #define MISC_GPT3SYNTH 0x00000400 #define MISC_GPT4SYNTH 0x00000800 +#define CONFIG_SPEAR_UART48M 0 +#define CONFIG_SPEAR_UARTCLKMSK (0x1 << 4) /* PRSC_CLK_CFG value */ /* @@ -126,5 +159,115 @@ struct misc_regs { /* PERIPH1_CLKEN, PERIPH1_RST value */ #define MISC_USBDENB 0x01000000 +#define MISC_ETHENB 0x00800000 +#define MISC_SMIENB 0x00200000 +#define MISC_GPT3ENB 0x00010000 +#define MISC_GPIO4ENB 0x00002000 +#define MISC_GPT2ENB 0x00000800 +#define MISC_FSMCENB 0x00000200 +#define MISC_I2CENB 0x00000080 +#define MISC_SSP2ENB 0x00000070 +#define MISC_UART0ENB 0x00000008 + +/* PERIPH_CLK_CFG */ +#define XTALTIMEEN 0x00000001 +#define PLLTIMEEN 0x00000002 +#define CLCDCLK_SYNTH 0x00000000 +#define CLCDCLK_48MHZ 0x00000004 +#define CLCDCLK_EXT 0x00000008 +#define UARTCLK_MASK (0x1 << 4) +#define UARTCLK_48MHZ 0x00000000 +#define UARTCLK_SYNTH 0x00000010 +#define IRDACLK_48MHZ 0x00000000 +#define IRDACLK_SYNTH 0x00000020 +#define IRDACLK_EXT 0x00000040 +#define RTC_DISABLE 0x00000080 +#define GPT1CLK_48MHZ 0x00000000 +#define GPT1CLK_SYNTH 0x00000100 +#define GPT2CLK_48MHZ 0x00000000 +#define GPT2CLK_SYNTH 0x00000200 +#define GPT3CLK_48MHZ 0x00000000 +#define GPT3CLK_SYNTH 0x00000400 +#define GPT4CLK_48MHZ 0x00000000 +#define GPT4CLK_SYNTH 0x00000800 +#define GPT5CLK_48MHZ 0x00000000 +#define GPT5CLK_SYNTH 0x00001000 +#define GPT1_FREEZE 0x00002000 +#define GPT2_FREEZE 0x00004000 +#define GPT3_FREEZE 0x00008000 +#define GPT4_FREEZE 0x00010000 +#define GPT5_FREEZE 0x00020000 + +/* PERIPH1_CLKEN bits */ +#define PERIPH_ARM1_WE 0x00000001 +#define PERIPH_ARM1 0x00000002 +#define PERIPH_ARM2 0x00000004 +#define PERIPH_UART1 0x00000008 +#define PERIPH_UART2 0x00000010 +#define PERIPH_SSP1 0x00000020 +#define PERIPH_SSP2 0x00000040 +#define PERIPH_I2C 0x00000080 +#define PERIPH_JPEG 0x00000100 +#define PERIPH_FSMC 0x00000200 +#define PERIPH_FIRDA 0x00000400 +#define PERIPH_GPT4 0x00000800 +#define PERIPH_GPT5 0x00001000 +#define PERIPH_GPIO4 0x00002000 +#define PERIPH_SSP3 0x00004000 +#define PERIPH_ADC 0x00008000 +#define PERIPH_GPT3 0x00010000 +#define PERIPH_RTC 0x00020000 +#define PERIPH_GPIO3 0x00040000 +#define PERIPH_DMA 0x00080000 +#define PERIPH_ROM 0x00100000 +#define PERIPH_SMI 0x00200000 +#define PERIPH_CLCD 0x00400000 +#define PERIPH_GMAC 0x00800000 +#define PERIPH_USBD 0x01000000 +#define PERIPH_USBH1 0x02000000 +#define PERIPH_USBH2 0x04000000 +#define PERIPH_MPMC 0x08000000 +#define PERIPH_RAMW 0x10000000 +#define PERIPH_MPMC_EN 0x20000000 +#define PERIPH_MPMC_WE 0x40000000 +#define PERIPH_MPMCMSK 0x60000000 + +#define PERIPH_CLK_ALL 0x0FFFFFF8 +#define PERIPH_RST_ALL 0x00000004 + +/* DDR_PAD values */ +#define DDR_PAD_CNF_MSK 0x0000ffff +#define DDR_PAD_SW_CONF 0x00060000 +#define DDR_PAD_SSTL_SEL 0x00000001 +#define DDR_PAD_DRAM_TYPE 0x00008000 + +/* DDR_COMP values */ +#define DDR_COMP_ACCURATE 0x00000010 + +/* SoC revision stuff */ +#define SOC_PRI_SHFT 16 +#define SOC_SEC_SHFT 8 + +/* Revision definitions */ +#define SOC_SPEAR_NA 0 + +/* + * The definitons have started from + * 101 for SPEAr6xx + * 201 for SPEAr3xx + * 301 for SPEAr13xx + */ +#define SOC_SPEAR600_AA 101 +#define SOC_SPEAR600_AB 102 +#define SOC_SPEAR600_BA 103 +#define SOC_SPEAR600_BB 104 +#define SOC_SPEAR600_BC 105 +#define SOC_SPEAR600_BD 106 + +#define SOC_SPEAR300 201 +#define SOC_SPEAR310 202 +#define SOC_SPEAR320 203 + +extern int get_socrev(void); #endif diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h deleted file mode 100644 index 2b63dc7e8e..0000000000 --- a/arch/arm/include/asm/arch-spear/spr_nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_NAND_H__ -#define __SPR_NAND_H__ - -struct fsmc_regs { - u32 reserved_1[0x10]; - u32 genmemctrl_pc; - u32 reserved_2; - u32 genmemctrl_comm; - u32 genmemctrl_attrib; - u32 reserved_3; - u32 genmemctrl_ecc; -}; - -/* genmemctrl_pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* genmemctrl_comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/board/avionic-design/plutux/plutux.c b/arch/arm/include/asm/arch-spear/spr_ssp.h index 42c80940c1..4f144ee4d6 100644 --- a/board/avionic-design/plutux/plutux.c +++ b/arch/arm/include/asm/arch-spear/spr_ssp.h @@ -1,8 +1,5 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011 - * Avionic Design GmbH <www.avionic-design.de> + * Copyright (C) 2012 Stefan Roese <sr@denx.de> * * See file CREDITS for list of people who contributed to this * project. @@ -23,23 +20,26 @@ * MA 02111-1307 USA */ -#include <common.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/tegra2.h> -#ifdef CONFIG_TEGRA2_MMC -#include <mmc.h> -#endif +#ifndef _SPR_SSP_H +#define _SPR_SSP_H + +struct ssp_regs { + u32 sspcr0; + u32 sspcr1; + u32 sspdr; + u32 sspsr; + u32 sspcpsr; + u32 sspimsc; + u32 sspicr; + u32 sspdmacr; +}; + +#define SSPCR0_FRF_MOT_SPI 0x0000 +#define SSPCR0_DSS_16BITS 0x000f + +#define SSPCR1_SSE 0x0002 + +#define SSPSR_TNF 0x2 +#define SSPSR_TFE 0x1 -#ifdef CONFIG_TEGRA2_MMC -/* - * Routine: gpio_config_mmc - * Description: Set GPIOs for SD card - */ -void gpio_config_mmc(void) -{ - /* configure pin as input for card detect */ - gpio_request(GPIO_PH2, "SD4 CD"); - gpio_direction_input(GPIO_PH2); -} #endif diff --git a/arch/arm/include/asm/arch-spear/spr_syscntl.h b/arch/arm/include/asm/arch-spear/spr_syscntl.h index 3c92f094cf..2393d89c0f 100644 --- a/arch/arm/include/asm/arch-spear/spr_syscntl.h +++ b/arch/arm/include/asm/arch-spear/spr_syscntl.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __SYSCTRL_H +#define __SYSCTRL_H + struct syscntl_regs { u32 scctrl; u32 scsysstat; @@ -36,3 +39,14 @@ struct syscntl_regs { const u32 scperclken; const u32 scperstat; }; + +#define MODE_SHIFT 0x00000003 + +#define NORMAL 0x00000004 +#define SLOW 0x00000002 +#define DOZE 0x00000001 +#define SLEEP 0x00000000 + +#define PLL_TIM 0x01FFFFFF + +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_xloader_table.h b/arch/arm/include/asm/arch-spear/spr_xloader_table.h deleted file mode 100644 index 7e3da18578..0000000000 --- a/arch/arm/include/asm/arch-spear/spr_xloader_table.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SPR_XLOADER_TABLE_H -#define _SPR_XLOADER_TABLE_H - -#define XLOADER_TABLE_VERSION_1_1 2 -#define XLOADER_TABLE_VERSION_1_2 3 - -#define XLOADER_TABLE_ADDRESS 0xD2801FF0 - -#define DDRMOBILE 1 -#define DDR2 2 - -#define REV_BA 1 -#define REV_AA 2 -#define REV_AB 3 - -struct xloader_table_1_1 { - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -struct xloader_table_1_2 { - unsigned const char *version; - - unsigned short ddrfreq; - unsigned char ddrsize; - unsigned char ddrtype; - - unsigned char soc_rev; -} __attribute__ ((packed)); - -union table_contents { - struct xloader_table_1_1 table_1_1; - struct xloader_table_1_2 table_1_2; -}; - -struct xloader_table { - unsigned char table_version; - union table_contents table; -} __attribute__ ((packed)); - -#endif diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 1d3ae38644..ff83bbf293 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -186,8 +186,9 @@ enum periph_id { /* Mask value for a clock (within PERIPH_REG(id)) */ #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) -/* return 1 if a PLL ID is in range */ -#define clock_id_isvalid(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT) +/* return 1 if a PLL ID is in range, and not a simple PLL */ +#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ + (id) < CLOCK_ID_FIRST_SIMPLE) /* PLL stabilization delay in usec */ #define CLOCK_PLL_STABLE_DELAY_US 300 diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h index ae73c72ebe..dcd512f084 100644 --- a/arch/arm/include/asm/arch-tegra2/funcmux.h +++ b/arch/arm/include/asm/arch-tegra2/funcmux.h @@ -30,6 +30,9 @@ enum { /* UART configs */ FUNCMUX_UART1_IRRX_IRTX = 0, + FUNCMUX_UART1_UAA_UAB, + FUNCMUX_UART1_GPU, + FUNCMUX_UART1_SDIO1, FUNCMUX_UART2_IRDA = 0, FUNCMUX_UART4_GMC = 0, @@ -41,12 +44,19 @@ enum { FUNCMUX_I2C3_DTF = 0, /* SDMMC configs */ + FUNCMUX_SDMMC1_SDIO1_4BIT = 0, FUNCMUX_SDMMC2_DTA_DTD_8BIT = 0, FUNCMUX_SDMMC3_SDB_4BIT = 0, FUNCMUX_SDMMC3_SDB_SLXA_8BIT, FUNCMUX_SDMMC4_ATC_ATD_8BIT = 0, FUNCMUX_SDMMC4_ATB_GMA_4_BIT, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT, + + /* USB configs */ + FUNCMUX_USB2_ULPI = 0, + + /* Serial Flash configs */ + FUNCMUX_SPI1_GMC_GMD = 0, }; /** diff --git a/arch/arm/include/asm/arch-tegra2/gpio.h b/arch/arm/include/asm/arch-tegra2/gpio.h index 41e66fe1b1..40ddb02565 100644 --- a/arch/arm/include/asm/arch-tegra2/gpio.h +++ b/arch/arm/include/asm/arch-tegra2/gpio.h @@ -2,6 +2,7 @@ * Copyright (c) 2011, Google Inc. All rights reserved. * See file CREDITS for list of people who contributed to this * project. + * Portions Copyright 2011-2012 NVIDIA Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,8 +20,8 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA2_GPIO_H_ -#define _TEGRA2_GPIO_H_ +#ifndef _TEGRA_GPIO_H_ +#define _TEGRA_GPIO_H_ /* * The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports, @@ -286,4 +287,4 @@ enum gpio_pin { void gpio_info(void); #define gpio_status() gpio_info() -#endif /* TEGRA2_GPIO_H_ */ +#endif /* TEGRA_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h index 469d742cc3..03fa7ca643 100644 --- a/arch/arm/include/asm/arch-tegra2/pinmux.h +++ b/arch/arm/include/asm/arch-tegra2/pinmux.h @@ -67,7 +67,7 @@ enum pmux_pingrp { PINGRP_KBCF, PINGRP_GMA, PINGRP_GMC, - PINGRP_SDMMC1, + PINGRP_SDIO1, PINGRP_OWC, /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index d4ada10ea8..13d68c017c 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -45,6 +45,7 @@ #define NV_PA_CSITE_BASE 0x70040000 #define TEGRA_USB1_BASE 0xC5000000 #define TEGRA_USB3_BASE 0xC5008000 +#define TEGRA_USB_ADDR_MASK 0xFFFFC000 #define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC @@ -60,6 +61,10 @@ struct timerus { /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ #define AP20_WB_RUN_ADDRESS 0x40020000 +#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */ +#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */ +#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ + /* These are the available SKUs (product types) for Tegra */ enum { SKU_ID_T20 = 0x8, diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra_spi.h index ceec4287a3..892d90c00b 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h +++ b/arch/arm/include/asm/arch-tegra2/tegra_spi.h @@ -1,7 +1,7 @@ /* * NVIDIA Tegra2 SPI-FLASH controller * - * Copyright 2010-2011 NVIDIA Corporation + * Copyright 2010-2012 NVIDIA Corporation * * This software may be used and distributed according to the * terms of the GNU Public License, Version 2, incorporated @@ -22,8 +22,8 @@ * MA 02111-1307 USA */ -#ifndef _TEGRA2_SPI_H_ -#define _TEGRA2_SPI_H_ +#ifndef _TEGRA_SPI_H_ +#define _TEGRA_SPI_H_ #include <asm/types.h> @@ -72,5 +72,4 @@ struct spi_tegra { #define SPI_TIMEOUT 1000 #define TEGRA2_SPI_MAX_FREQ 52000000 - -#endif /* _TEGRA2_SPI_H_ */ +#endif /* _TEGRA_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h index e4503b15b0..82ac180acd 100644 --- a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h +++ b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h @@ -29,7 +29,7 @@ * time! If the board file provides this, the board config will declare it. * Let this be a lesson for others. */ -void pinmux_select_uart(NS16550_t regs); +void pinmux_select_uart(void); /* * Signal that we are about the use the SPI bus. @@ -38,7 +38,7 @@ void pinmux_select_spi(void); #else /* not CONFIG_SPI_UART_SWITCH */ -static inline void pinmux_select_uart(NS16550_t regs) {} +static inline void pinmux_select_uart(void) {} static inline void pinmux_select_spi(void) {} #endif diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index f1e3ad212e..674c3de661 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -471,6 +471,49 @@ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) +/*EMIF_READ_WRITE_LEVELING_CONTROL*/ +#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 +#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ +#define EMIF_REG_RDWRLVL_EN_SHIFT 31 +#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ +#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 +#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) + +/*Leveling Fields */ +#define DDR3_WR_LVL_INT 0x73 +#define DDR3_RD_LVL_INT 0x33 +#define DDR3_RD_LVL_GATE_INT 0x59 +#define RD_RW_LVL_INC_PRE 0x0 +#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) + +#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ + | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ + | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ + | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) + +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 +#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 + /* DMM */ #define DMM_BASE 0x4E000040 @@ -650,6 +693,7 @@ struct dmm_lisa_map_regs { }; extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define CS0 0 #define CS1 1 @@ -1073,6 +1117,10 @@ struct emif_regs { u32 emif_ddr_ext_phy_ctrl_3; u32 emif_ddr_ext_phy_ctrl_4; u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 emif_rd_wr_exec_thresh; }; /* assert macros */ @@ -1093,11 +1141,13 @@ void emif_get_device_timings(u32 emif_nr, const struct lpddr2_device_timings **cs1_device_timings); #endif +void do_ext_phy_settings(u32 base, const struct emif_regs *regs); + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; extern u32 *const T_den; extern u32 *const emif_sizes; #endif - +void config_data_eye_leveling_samples(u32 emif_base); #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 459b6b16e2..4e95eee59b 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -136,4 +136,5 @@ static inline u32 omap_revision(void) /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 +#define OMAP5432_ES1_0 0x54320100 #endif /* _OMAP_COMMON_H_ */ diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 4ca75f9f93..9f3cae5ece 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -52,6 +52,7 @@ void cpu_init_cp15(void); /* cpu/.../arch/cpu.c */ int arch_cpu_init(void); int arch_misc_init(void); +int arch_early_init_r(void); /* board/.../... */ int board_init(void); diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 024646cae5..f1951e883e 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -224,10 +224,16 @@ void __dram_init_banksize(void) void dram_init_banksize(void) __attribute__((weak, alias("__dram_init_banksize"))); +int __arch_cpu_init(void) +{ + return 0; +} +int arch_cpu_init(void) + __attribute__((weak, alias("__arch_cpu_init"))); + init_fnc_t *init_sequence[] = { -#if defined(CONFIG_ARCH_CPU_INIT) arch_cpu_init, /* basic arch cpu dependent setup */ -#endif + #if defined(CONFIG_BOARD_EARLY_INIT_F) board_early_init_f, #endif @@ -500,6 +506,10 @@ void board_init_r(gd_t *id, ulong dest_addr) malloc_start = dest_addr - TOTAL_MALLOC_LEN; mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); +#ifdef CONFIG_ARCH_EARLY_INIT_R + arch_early_init_r(); +#endif + #if !defined(CONFIG_SYS_NO_FLASH) puts("Flash: "); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e6c3eae6f9..939de10e03 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit) { uint32_t reg; + reg = get_cr(); + cp_delay(); + if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ - reg = get_cr(); if ((reg & CR_C) != CR_C) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; flush_dcache_all(); } - reg = get_cr(); - cp_delay(); set_cr(reg & ~cache_bit); } #endif diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c index 2028dbd715..44eebe0a5d 100644 --- a/arch/arm/lib/eabi_compat.c +++ b/arch/arm/lib/eabi_compat.c @@ -13,7 +13,8 @@ int raise (int signum) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + /* Even if printf() is available, it's large. Punt it for SPL builds */ +#if !defined(CONFIG_SPL_BUILD) printf("raise: Signal # %d caught\n", signum); #endif return 0; diff --git a/arch/blackfin/include/asm/bfin_logo_230x230.h b/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h index 3a79631fcd..3a79631fcd 100644 --- a/arch/blackfin/include/asm/bfin_logo_230x230.h +++ b/arch/blackfin/include/asm/bfin_logo_230x230_gzip.h diff --git a/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h b/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h new file mode 100644 index 0000000000..ae9554f89e --- /dev/null +++ b/arch/blackfin/include/asm/bfin_logo_230x230_lzma.h @@ -0,0 +1,1819 @@ +/* + * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi + * + * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y) + * + * Where: 'screen' is the pointer to the frame buffer + * 'width' is the screen width + * 'x' is the horizontal position + * 'y' is the vertical position + */ + +#define EASYLOGO_ENABLE_LZMA 28532 + +static unsigned char EASYLOGO_DECOMP_BUFFER[158700]; + +#include <video_easylogo.h> + +#define DEF_BFIN_LOGO_WIDTH 230 +#define DEF_BFIN_LOGO_HEIGHT 230 +#define DEF_BFIN_LOGO_PIXELS 52900 +#define DEF_BFIN_LOGO_BPP 24 +#define DEF_BFIN_LOGO_PIXEL_SIZE 3 +#define DEF_BFIN_LOGO_SIZE 158700 + +unsigned char DEF_BFIN_LOGO_DATA[] = { + 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f, + 0xfd, 0xf8, 0xb8, 0x51, 0x47, 0x76, 0x83, 0x1a, 0x36, 0xff, 0xdf, 0x25, 0x3b, 0x9e, 0x1e, 0xfc, + 0x17, 0x17, 0x7c, 0x3f, 0x4c, 0x3f, 0x42, 0x00, 0x19, 0xe1, 0x7c, 0x13, 0xce, 0xa1, 0xb5, 0xdf, + 0x06, 0x70, 0x2e, 0xb6, 0x6c, 0xe0, 0xcb, 0x11, 0xf6, 0x92, 0x94, 0x8a, 0x99, 0x3e, 0x21, 0xb2, + 0x27, 0xe8, 0x4c, 0x5d, 0x4c, 0x45, 0x6d, 0xfa, 0x0d, 0x07, 0x51, 0x9c, 0xc1, 0xf2, 0x53, 0x6d, + 0x9e, 0x57, 0xb5, 0x3a, 0x93, 0x8c, 0x7e, 0x3d, 0x18, 0x78, 0x1a, 0x13, 0x72, 0x7a, 0xa6, 0x0f, + 0x90, 0x31, 0x39, 0xfe, 0xe1, 0x4c, 0x12, 0xda, 0x4f, 0xe8, 0xe7, 0x3f, 0x68, 0xe5, 0xc3, 0x2e, + 0x8c, 0xeb, 0x62, 0x9a, 0x99, 0x26, 0xf6, 0x64, 0x2e, 0x15, 0x1f, 0xd6, 0xa2, 0xbd, 0xe9, 0xa2, + 0x87, 0x70, 0xd8, 0x35, 0x60, 0x6d, 0x05, 0x11, 0x97, 0x62, 0x11, 0x11, 0x31, 0x08, 0xb8, 0xe5, + 0xe1, 0x76, 0x47, 0x2d, 0x42, 0x5d, 0x06, 0xa1, 0x5c, 0x30, 0xf0, 0x11, 0x9d, 0xf7, 0x13, 0x4d, + 0xbd, 0x5f, 0x8f, 0x2b, 0xb2, 0x2e, 0x47, 0x7e, 0x21, 0x1e, 0xce, 0x05, 0x29, 0x0d, 0x38, 0xcb, + 0x05, 0xc9, 0x55, 0xde, 0xc9, 0x66, 0xb3, 0xf9, 0x0b, 0xbb, 0x76, 0x6b, 0x36, 0x81, 0x16, 0x59, + 0xce, 0xbf, 0x02, 0x66, 0x52, 0xa1, 0x75, 0xff, 0xb0, 0xb7, 0x8e, 0x5b, 0x56, 0xaf, 0xdc, 0x62, + 0x7a, 0xc5, 0xf0, 0xa8, 0xc3, 0xf8, 0xf5, 0x32, 0xef, 0xd7, 0x65, 0xdf, 0x2b, 0x64, 0x9d, 0x1b, + 0x99, 0x63, 0x0d, 0x11, 0xb2, 0xc8, 0x4a, 0xf6, 0x27, 0xb7, 0xa1, 0xfb, 0x25, 0x7a, 0xfd, 0x69, + 0x01, 0xfa, 0xc8, 0x2b, 0xe8, 0x44, 0x83, 0x66, 0x72, 0xb6, 0xa9, 0x8a, 0xb2, 0x2a, 0x6f, 0xfe, + 0xe8, 0xca, 0x85, 0x21, 0x83, 0x77, 0x08, 0x03, 0xc2, 0xd5, 0xd0, 0x68, 0xc4, 0xb3, 0xca, 0x54, + 0x9b, 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0x32, 0x01, 0x64, 0x1b, 0x7f, 0x0d, 0x00, 0xbf, + 0x1d, 0xa1, 0x81, 0x51, 0x0f, 0x96, 0x2e, 0x02, 0x80, 0x26, 0xc1, 0x90, 0x70, 0x81, 0xfd, 0x20, + 0x79, 0xd1, 0x61, 0x06, 0x0a, 0xab, 0x43, 0x02, 0xc1, 0x80, 0x0e, 0xbb, 0x1a, 0xb1, 0xfa, 0x98, + 0x64, 0xcc, 0xbb, 0xe3, 0xf3, 0x58, 0x23, 0x7e, 0xfa, 0x91, 0x22, 0x5e, 0x61, 0x11, 0xe5, 0xff, + 0xfa, 0xe5, 0x64, 0xa4 +}; + +fastimage_t bfin_logo = { + DEF_BFIN_LOGO_DATA, + DEF_BFIN_LOGO_WIDTH, + DEF_BFIN_LOGO_HEIGHT, + DEF_BFIN_LOGO_BPP, + DEF_BFIN_LOGO_PIXEL_SIZE, + DEF_BFIN_LOGO_SIZE +}; diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h index c5b0be96f1..c5b0be96f1 100644 --- a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h +++ b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h diff --git a/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h new file mode 100644 index 0000000000..1955f668ff --- /dev/null +++ b/arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h @@ -0,0 +1,1079 @@ +/* + * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi + * + * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y) + * + * Where: 'screen' is the pointer to the frame buffer + * 'width' is the screen width + * 'x' is the horizontal position + * 'y' is the vertical position + */ + +#define EASYLOGO_ENABLE_LZMA 16703 + +static unsigned char EASYLOGO_DECOMP_BUFFER[105800]; + +#include <video_easylogo.h> + +#define DEF_BFIN_LOGO_WIDTH 230 +#define DEF_BFIN_LOGO_HEIGHT 230 +#define DEF_BFIN_LOGO_PIXELS 52900 +#define DEF_BFIN_LOGO_BPP 16 +#define DEF_BFIN_LOGO_PIXEL_SIZE 2 +#define DEF_BFIN_LOGO_SIZE 105800 + +unsigned char DEF_BFIN_LOGO_DATA[] = { + 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f, + 0xfd, 0xff, 0xff, 0x86, 0x51, 0xd0, 0x3c, 0xfc, 0x65, 0xea, 0x02, 0x56, 0x77, 0x71, 0xde, 0xb1, + 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0xcc, + 0x1b, 0x0b, 0x97, 0x26, 0x7a, 0x53, 0x09, 0x05, 0x37, 0xa1, 0x6d, 0x36, 0x62, 0xe9, 0x43, 0xb1, + 0xf3, 0xe3, 0xb1, 0xc0, 0x80, 0xf7, 0x2e, 0xae, 0x49, 0x7a, 0xe6, 0xba, 0x1b, 0x42, 0x87, 0x5c, + 0xc3, 0xae, 0x2c, 0xd0, 0xd2, 0x98, 0x77, 0x43, 0xd1, 0x81, 0x26, 0x9a, 0xe2, 0xbf, 0xf4, 0x6f, + 0xee, 0x24, 0x52, 0xfb, 0x1f, 0x6a, 0x1f, 0x21, 0xef, 0xf0, 0xc6, 0x02, 0x85, 0xde, 0x1a, 0x4d, + 0x13, 0xff, 0xa1, 0x58, 0x43, 0x79, 0xb7, 0xc9, 0x45, 0x51, 0x3f, 0x90, 0xb6, 0x76, 0xbb, 0xfb, + 0x51, 0x8e, 0x37, 0xab, 0x13, 0x36, 0x84, 0x7b, 0xea, 0xea, 0x68, 0x49, 0xd7, 0x5b, 0x42, 0x64, + 0x09, 0x76, 0x7b, 0x6e, 0xe6, 0x93, 0xd3, 0x27, 0x37, 0xce, 0x2f, 0xd7, 0x3b, 0x1e, 0xf0, 0xd2, + 0x15, 0xb0, 0xc9, 0xb3, 0x09, 0xef, 0xfe, 0x60, 0xa5, 0x79, 0xb5, 0xb6, 0x30, 0x85, 0x0e, 0xcc, + 0xbb, 0x23, 0x53, 0x58, 0x28, 0xf5, 0x66, 0xe7, 0xed, 0x2a, 0x0e, 0x8e, 0xdd, 0x23, 0x0d, 0x36, + 0x84, 0xf3, 0xbe, 0x75, 0xe9, 0xf7, 0x47, 0x07, 0xf4, 0x39, 0x7b, 0x57, 0xe7, 0x1d, 0x94, 0xff, + 0xe7, 0xe4, 0x9b, 0x91, 0x3d, 0x6e, 0xba, 0x28, 0xca, 0x07, 0xbb, 0xc9, 0xb1, 0x84, 0x7c, 0x6a, + 0x50, 0x97, 0xf1, 0xf7, 0x22, 0xa7, 0xa3, 0x36, 0x28, 0xe9, 0x3a, 0x60, 0x30, 0x84, 0x73, 0xe8, + 0x60, 0xbf, 0x26, 0xac, 0x57, 0xa9, 0xab, 0xd2, 0xb1, 0x3f, 0xff, 0xfc, 0x33, 0xe0, 0x8d +}; + +fastimage_t bfin_logo = { + DEF_BFIN_LOGO_DATA, + DEF_BFIN_LOGO_WIDTH, + DEF_BFIN_LOGO_HEIGHT, + DEF_BFIN_LOGO_BPP, + DEF_BFIN_LOGO_PIXEL_SIZE, + DEF_BFIN_LOGO_SIZE +}; diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c index c2636b1215..a9991e7673 100644 --- a/arch/nds32/cpu/n1213/ag101/cpu.c +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -82,115 +82,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /*NOTREACHED*/ } - -static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) -{ - if (cache == ICACHE) - return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ - >> ICM_CFG_OFF_ISZ) - 1); - else - return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ - >> DCM_CFG_OFF_DSZ) - 1); -} - -void dcache_flush_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(DCACHE); - - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start)); - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void icache_inval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(ICACHE); - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void flush_cache(unsigned long addr, unsigned long size) -{ - dcache_flush_range(addr, addr + size); - icache_inval_range(addr, addr + size); -} - -void icache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x01\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void icache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x01\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int icache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} - -void dcache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x02\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void dcache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x02\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int dcache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c index ed88b522a4..252b69db7c 100644 --- a/arch/nds32/cpu/n1213/ag102/cpu.c +++ b/arch/nds32/cpu/n1213/ag102/cpu.c @@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /*NOTREACHED*/ } - -static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) -{ - if (cache == ICACHE) - return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ - >> ICM_CFG_OFF_ISZ) - 1); - else - return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ - >> DCM_CFG_OFF_DSZ) - 1); -} - -void dcache_flush_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(DCACHE); - - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start)); - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void icache_inval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(ICACHE); - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void flush_cache(unsigned long addr, unsigned long size) -{ - dcache_flush_range(addr, addr + size); - icache_inval_range(addr, addr + size); -} - -void icache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x01\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void icache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x01\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int icache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} - -void dcache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x02\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void dcache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x02\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int dcache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile index e5c31c3128..581a2e758a 100644 --- a/arch/nds32/lib/Makefile +++ b/arch/nds32/lib/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o -OBJS := board.o bootm.o interrupts.o +OBJS := board.o bootm.o cache.o interrupts.o all: $(LIB) diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c new file mode 100644 index 0000000000..0f1a886d30 --- /dev/null +++ b/arch/nds32/lib/cache.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2012 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> + +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) +{ + if (cache == ICACHE) + return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ + >> ICM_CFG_OFF_ISZ) - 1); + else + return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ + >> DCM_CFG_OFF_DSZ) - 1); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_WB" + "\n\tcctl %0, L1D_VA_INVAL" + : + : "r" (start) + ); + start += line_size; + } +} + +void invalidate_icache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(ICACHE); + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1I_VA_INVAL" + : + : "r"(start) + ); + start += line_size; + } +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_INVAL" + : + : "r"(start) + ); + start += line_size; + } +} + +void flush_cache(unsigned long addr, unsigned long size) +{ + flush_dcache_range(addr, addr + size); + invalidate_icache_range(addr, addr + size); +} + +void icache_enable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "ori $p0, $p0, 0x01\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +void icache_disable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "li $p1, ~0x01\n\t" + "and $p0, $p0, $p1\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +int icache_status(void) +{ + int ret; + + asm volatile ( + "mfsr $p0, $mr8\n\t" + "andi %0, $p0, 0x01\n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} + +void dcache_enable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "ori $p0, $p0, 0x02\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +void dcache_disable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "li $p1, ~0x02\n\t" + "and $p0, $p0, $p1\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +int dcache_status(void) +{ + int ret; + + asm volatile ( + "mfsr $p0, $mr8\n\t" + "andi %0, $p0, 0x02\n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c index ca8a3e5246..1e495d442d 100644 --- a/arch/nios2/lib/board.c +++ b/arch/nios2/lib/board.c @@ -87,17 +87,15 @@ void board_init (void) { bd_t *bd; init_fnc_t **init_fnc_ptr; + static gd_t gd_data; + static bd_t bd_data; - /* Pointer is writable since we allocated a register for it. - * Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address. - */ - gd = (gd_t *)CONFIG_SYS_GBL_DATA_OFFSET; + /* Pointer is writable since we allocated a register for it. */ + gd = &gd_data; /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); - memset( gd, 0, GENERATED_GBL_DATA_SIZE ); - - gd->bd = (bd_t *)(gd+1); /* At end of global data */ + gd->bd = &bd_data; gd->baudrate = CONFIG_BAUDRATE; gd->cpu_clk = CONFIG_SYS_CLK_FREQ; diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 012ab6b020..687f5e90a4 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -42,7 +42,7 @@ COBJS-$(CONFIG_PCIE) += pcie.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o # Stub implementations of cache management functions for USB -COBJS-$(CONFIG_USB_EHCI) += cache.o +COBJS-y += cache.o ifdef CONFIG_FSL_DDR2 COBJS_LN-$(CONFIG_MPC8349) += ddr-gen2.o diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index a88fab91b2..2d5ee03814 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -1,7 +1,7 @@ /* * Freescale SerDes initialization routine * - * Copyright (C) 2007,2011 Freescale Semicondutor, Inc. + * Copyright 2007,2011 Freescale Semiconductor, Inc. * Copyright (C) 2008 MontaVista Software, Inc. * * Author: Li Yang <leoli@freescale.com> diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index c512b337f1..34f6c54698 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o +COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o @@ -130,7 +131,7 @@ COBJS += tlb.o COBJS += traps.o # Stub implementations of cache management functions for USB -COBJS-$(CONFIG_USB_EHCI) += cache.o +COBJS += cache.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 2ed5a98424..4e1a54ad0c 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -33,9 +33,7 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (IS_SVR_REV(svr, 1, 0)) { switch (SVR_SOC_VER(svr)) { case SVR_P1013: - case SVR_P1013_E: case SVR_P1022: - case SVR_P1022_E: puts("Work-around for Erratum SATA A001 enabled\n"); } } @@ -51,7 +49,16 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum SERDES-A005 enabled\n"); #endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - puts("Work-around for Erratum CPU22 enabled\n"); + if (SVR_MAJ(svr) < 3) + puts("Work-around for Erratum CPU22 enabled\n"); +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 + /* + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) + puts("Work-around for Erratum CPU-A011 enabled\n"); #endif #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) puts("Work-around for Erratum CPU-A003999 enabled\n"); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2cd5db7c59..fc6c2877d2 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -308,10 +308,18 @@ int cpu_init_r(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; #endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - flush_dcache(); - mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); - sync(); +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + if (SVR_SOC_VER(svr) != SVR_P4080 || SVR_MAJ(svr) < 3) { + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); + sync(); + } #endif puts ("L2: "); @@ -354,8 +362,7 @@ int cpu_init_r(void) break; case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { + ver == SVR_8541 || ver == SVR_8555) { puts("128 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */ cache_ctl = 0xc4000000; @@ -366,8 +373,7 @@ int cpu_init_r(void) break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) { + ver == SVR_8541 || ver == SVR_8555) { puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; @@ -403,8 +409,7 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) - if ((SVR_SOC_VER(svr) == SVR_P2040) || - (SVR_SOC_VER(svr) == SVR_P2040_E)) { + if (SVR_SOC_VER(svr) == SVR_P2040) { puts("N/A\n"); goto skip_l2; } @@ -506,9 +511,7 @@ skip_l2: */ if (IS_SVR_REV(svr, 1, 0) && ((SVR_SOC_VER(svr) == SVR_P1022) || - (SVR_SOC_VER(svr) == SVR_P1022_E) || - (SVR_SOC_VER(svr) == SVR_P1013) || - (SVR_SOC_VER(svr) == SVR_P1013_E))) { + (SVR_SOC_VER(svr) == SVR_P1013))) { fsl_sata_reg_t *reg; /* first SATA controller */ @@ -537,7 +540,7 @@ void arch_preboot_os(void) * disabled by the time we get called. */ msr = mfmsr(); - msr &= ~(MSR_ME|MSR_CE|MSR_DE); + msr &= ~(MSR_ME|MSR_CE); mtmsr(msr); setup_ivors(); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 091af7c95a..dacfdd15ea 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc + * Copyright 2009-2012 Freescale Semiconductor, Inc * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -53,6 +53,36 @@ void setup_ifc(void) asm volatile("isync;msync;tlbwe;isync"); +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + * + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's physical address is going to change as + * CONFIG_SYS_FLASH_BASE_PHYS. + */ + _mas0 = MAS0_TLBSEL(1) | + MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); + _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT | + MAS1_TSIZE(BOOKE_PAGESZ_4M); + _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G); + _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX); + _mas7 = FSL_BOOKE_MAS7(flash_phys); + + mtspr(MAS0, _mas0); + mtspr(MAS1, _mas1); + mtspr(MAS2, _mas2); + mtspr(MAS3, _mas3); + mtspr(MAS7, _mas7); + + asm volatile("isync;msync;tlbwe;isync"); +#endif + + /* Change flash's physical address */ out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0); out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c index f33db021f1..bf7a6f6be6 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c @@ -26,32 +26,6 @@ void cpu_init_f(void) { -#ifdef CONFIG_FSL_LBC - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - /* - * LCRR - Clock Ratio Register - set up local bus timing - * when needed - */ - out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#else -#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined -#endif -#endif -#ifdef CONFIG_FSL_IFC -#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); -#endif -#endif -#endif - #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 977770e99d..21c3ad49bf 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -139,16 +139,14 @@ static inline u32 l2cache_size(void) break; case 0x1: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) + ver == SVR_8541 || ver == SVR_8555) return 128; else return 256; break; case 0x2: if (ver == SVR_8540 || ver == SVR_8560 || - ver == SVR_8541 || ver == SVR_8541_E || - ver == SVR_8555 || ver == SVR_8555_E) + ver == SVR_8541 || ver == SVR_8555) return 256; else return 512; @@ -231,8 +229,7 @@ static inline void ft_fixup_l2cache(void *blob) int has_l2 = 1; /* P2040/P2040E has no L2, so dont set any L2 props */ - if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || - (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + if (SVR_SOC_VER(get_svr()) == SVR_P2040) has_l2 = 0; size = (l2cfg0 & 0x3fff) * 64 * 1024; @@ -407,7 +404,7 @@ static void ft_fixup_qe_snum(void *blob) unsigned int svr; svr = mfspr(SPRN_SVR); - if (SVR_SOC_VER(svr) == SVR_8569_E) { + if (SVR_SOC_VER(svr) == SVR_8569) { if(IS_SVR_REV(svr, 1, 0)) do_fixup_by_compat_u32(blob, "fsl,qe", "fsl,qe-num-snums", 46, 1); diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index f68f28191f..eec4ffe516 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -78,7 +78,7 @@ enum srds_prtcl serdes_get_prtcl(int cfg, int lane) prtcl = serdes_cfg_tbl[cfg][lane]; /* P2040[e] does not support XAUI */ - if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + if (ver == SVR_P2040 && prtcl == XAUI_FM1) prtcl = NONE; return prtcl; @@ -94,7 +94,7 @@ int is_serdes_prtcl_valid(u32 prtcl) return 0; /* P2040[e] does not support XAUI */ - if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + if (ver == SVR_P2040 && prtcl == XAUI_FM1) return 0; for (i = 0; i < SRDS_MAX_LANES; i++) { diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index c81e19c0e9..1860684c11 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -143,23 +143,40 @@ __secondary_start_page: mtspr L1CSR2,r8 #endif -#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) - mfspr r8,L1CSR2 - oris r8,r8,(L1CSR2_DCWS)@h - mtspr L1CSR2,r8 +#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ + defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) + /* + * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 + * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 + */ + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit */ + + lis r5,SVR_P4080@h + ori r5,r5,SVR_P4080@l + cmpw r6,r5 + bne 1f + + rlwinm r3,r3,0,0xf0 + li r5,0x30 + cmpw r3,r5 + bge 2f +1: + mfspr r3,L1CSR2 + oris r3,r3,(L1CSR2_DCWS)@h + mtspr L1CSR2,r3 +2: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE /* skip L2 setup on P2040/P2040E as they have no L2 */ - mfspr r2,SPRN_SVR + mfspr r3,SPRN_SVR + rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */ + lis r3,SVR_P2040@h ori r3,r3,SVR_P2040@l - cmpw r2,r3 - beq 3f - - lis r3,SVR_P2040_E@h - ori r3,r3,SVR_P2040_E@l - cmpw r2,r3 + cmpw r6,r3 beq 3f /* Enable/invalidate the L2 cache */ diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 8e99ef6c68..6aabc30c28 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -82,6 +82,9 @@ .globl _start_e500 _start_e500: +/* Enable debug exception */ + li r1,MSR_DE + mtmsr r1 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) /* ISBC uses L2 as stack. @@ -179,6 +182,72 @@ l2_disabled: andi. r1,r3,L1CSR0_DCE@l beq 2b +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL) +/* + * TLB entry for debuggging in AS1 + * Create temporary TLB entry in AS0 to handle debug exception + * As on debug exception MSR is cleared i.e. Address space is changed + * to 0. A TLB entry (in AS0) is required to handle debug exception generated + * in AS1. + */ + + lis r6,FSL_BOOKE_MAS0(1, + CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h + ori r6,r6,FSL_BOOKE_MAS0(1, + CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l + +#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT) +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. + * and this window is outside of 4K boot window. + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, + (MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, + (MAS2_I|MAS2_G))@l + + /* The 85xx has the default boot window 0xff800000 - 0xffffffff */ + lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l +#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l + + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l +#else +/* + * TLB entry is created for IVPR + IVOR15 to map on valid OP code address + * because "nexti" will resize TLB to 4K + */ + lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l + + lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h + ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, + (MAS2_I))@l + lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@h + ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, + (MAS3_SX|MAS3_SW|MAS3_SR))@l +#endif + mtspr MAS0,r6 + mtspr MAS1,r7 + mtspr MAS2,r8 + mtspr MAS3,r9 + tlbwe + isync +#endif + /* * Ne need to setup interrupt vector for NAND SPL * because NAND SPL never compiles it. @@ -733,8 +802,8 @@ create_init_ram_area: msync tlbwe - lis r6,MSR_IS|MSR_DS@h - ori r6,r6,MSR_IS|MSR_DS@l + lis r6,MSR_IS|MSR_DS|MSR_DE@h + ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l lis r7,switch_as@h ori r7,r7,switch_as@l @@ -1372,17 +1441,24 @@ relocate_code: 7: sync /* Wait for all icbi to complete on bus */ isync - /* - * Re-point the IVPR at RAM - */ - mtspr IVPR,r10 - /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. */ addi r0,r10,in_ram - _start + _START_OFFSET + + /* + * As IVPR is going to point RAM address, + * Make sure IVOR15 has valid opcode to support debugger + */ + mtspr IVOR15,r0 + + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + mtlr r0 blr /* NEVER RETURNS! */ .globl in_ram diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 5cbf9a688e..b3fcfe5626 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -41,6 +41,7 @@ #include <netdev.h> #include <asm/cache.h> #include <linux/compiler.h> +#include <asm/io.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> @@ -253,7 +254,7 @@ static int check_CPU (long clock, uint pvr, uint immr) if ((pvr >> 16) != 0x0050) return -1; - k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]); + k = (immr << 16) | in_be16((ushort *)&immap->im_cpm.cp_dparam[0xB0]); m = 0; switch (k) { diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 0365ca8aa2..cbc674211a 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -37,82 +37,47 @@ DECLARE_GLOBAL_DATA_PTR; struct cpu_type cpu_type_list [] = { #if defined(CONFIG_MPC85xx) CPU_TYPE_ENTRY(8533, 8533, 1), - CPU_TYPE_ENTRY(8533, 8533_E, 1), CPU_TYPE_ENTRY(8535, 8535, 1), - CPU_TYPE_ENTRY(8535, 8535_E, 1), CPU_TYPE_ENTRY(8536, 8536, 1), - CPU_TYPE_ENTRY(8536, 8536_E, 1), CPU_TYPE_ENTRY(8540, 8540, 1), CPU_TYPE_ENTRY(8541, 8541, 1), - CPU_TYPE_ENTRY(8541, 8541_E, 1), CPU_TYPE_ENTRY(8543, 8543, 1), - CPU_TYPE_ENTRY(8543, 8543_E, 1), CPU_TYPE_ENTRY(8544, 8544, 1), - CPU_TYPE_ENTRY(8544, 8544_E, 1), CPU_TYPE_ENTRY(8545, 8545, 1), - CPU_TYPE_ENTRY(8545, 8545_E, 1), - CPU_TYPE_ENTRY(8547, 8547_E, 1), + CPU_TYPE_ENTRY(8547, 8547, 1), CPU_TYPE_ENTRY(8548, 8548, 1), - CPU_TYPE_ENTRY(8548, 8548_E, 1), CPU_TYPE_ENTRY(8555, 8555, 1), - CPU_TYPE_ENTRY(8555, 8555_E, 1), CPU_TYPE_ENTRY(8560, 8560, 1), CPU_TYPE_ENTRY(8567, 8567, 1), - CPU_TYPE_ENTRY(8567, 8567_E, 1), CPU_TYPE_ENTRY(8568, 8568, 1), - CPU_TYPE_ENTRY(8568, 8568_E, 1), CPU_TYPE_ENTRY(8569, 8569, 1), - CPU_TYPE_ENTRY(8569, 8569_E, 1), CPU_TYPE_ENTRY(8572, 8572, 2), - CPU_TYPE_ENTRY(8572, 8572_E, 2), CPU_TYPE_ENTRY(P1010, P1010, 1), - CPU_TYPE_ENTRY(P1010, P1010_E, 1), CPU_TYPE_ENTRY(P1011, P1011, 1), - CPU_TYPE_ENTRY(P1011, P1011_E, 1), CPU_TYPE_ENTRY(P1012, P1012, 1), - CPU_TYPE_ENTRY(P1012, P1012_E, 1), CPU_TYPE_ENTRY(P1013, P1013, 1), - CPU_TYPE_ENTRY(P1013, P1013_E, 1), - CPU_TYPE_ENTRY(P1014, P1014_E, 1), CPU_TYPE_ENTRY(P1014, P1014, 1), - CPU_TYPE_ENTRY(P1015, P1015_E, 1), CPU_TYPE_ENTRY(P1015, P1015, 1), - CPU_TYPE_ENTRY(P1016, P1016_E, 1), CPU_TYPE_ENTRY(P1016, P1016, 1), CPU_TYPE_ENTRY(P1017, P1017, 1), - CPU_TYPE_ENTRY(P1017, P1017_E, 1), CPU_TYPE_ENTRY(P1020, P1020, 2), - CPU_TYPE_ENTRY(P1020, P1020_E, 2), CPU_TYPE_ENTRY(P1021, P1021, 2), - CPU_TYPE_ENTRY(P1021, P1021_E, 2), CPU_TYPE_ENTRY(P1022, P1022, 2), - CPU_TYPE_ENTRY(P1022, P1022_E, 2), CPU_TYPE_ENTRY(P1023, P1023, 2), - CPU_TYPE_ENTRY(P1023, P1023_E, 2), CPU_TYPE_ENTRY(P1024, P1024, 2), - CPU_TYPE_ENTRY(P1024, P1024_E, 2), CPU_TYPE_ENTRY(P1025, P1025, 2), - CPU_TYPE_ENTRY(P1025, P1025_E, 2), CPU_TYPE_ENTRY(P2010, P2010, 1), - CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), - CPU_TYPE_ENTRY(P2020, P2020_E, 2), CPU_TYPE_ENTRY(P2040, P2040, 4), - CPU_TYPE_ENTRY(P2040, P2040_E, 4), CPU_TYPE_ENTRY(P2041, P2041, 4), - CPU_TYPE_ENTRY(P2041, P2041_E, 4), CPU_TYPE_ENTRY(P3041, P3041, 4), - CPU_TYPE_ENTRY(P3041, P3041_E, 4), CPU_TYPE_ENTRY_MASK(P3060, P3060, 6, 0xf3), - CPU_TYPE_ENTRY_MASK(P3060, P3060_E, 6, 0xf3), CPU_TYPE_ENTRY(P4040, P4040, 4), - CPU_TYPE_ENTRY(P4040, P4040_E, 4), CPU_TYPE_ENTRY(P4080, P4080, 8), - CPU_TYPE_ENTRY(P4080, P4080_E, 8), CPU_TYPE_ENTRY(P5010, P5010, 1), - CPU_TYPE_ENTRY(P5010, P5010_E, 1), CPU_TYPE_ENTRY(P5020, P5020, 2), - CPU_TYPE_ENTRY(P5020, P5020_E, 2), + CPU_TYPE_ENTRY(BSC9130, 9130, 1), + CPU_TYPE_ENTRY(BSC9131, 9131, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 191629b628..b6c44bb11d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -122,6 +122,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_FSL_SATA_V2 @@ -138,6 +139,7 @@ #elif defined(CONFIG_P1011) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -149,6 +151,7 @@ #elif defined(CONFIG_P1012) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -163,6 +166,7 @@ #elif defined(CONFIG_P1013) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_FSL_SATA_V2 @@ -175,6 +179,7 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_FSL_SATA_V2 @@ -190,6 +195,7 @@ #elif defined(CONFIG_P1015) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -201,6 +207,7 @@ #elif defined(CONFIG_P1016) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -228,6 +235,7 @@ #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -238,6 +246,7 @@ #elif defined(CONFIG_P1021) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -251,6 +260,7 @@ #elif defined(CONFIG_P1022) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_FSL_SATA_V2 @@ -276,6 +286,7 @@ #elif defined(CONFIG_P1024) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -287,6 +298,7 @@ #elif defined(CONFIG_P1025) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_SYS_FSL_SEC_COMPAT 2 @@ -301,6 +313,7 @@ #elif defined(CONFIG_P2010) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -309,6 +322,7 @@ #elif defined(CONFIG_P2020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -335,6 +349,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -359,6 +374,7 @@ #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -446,6 +462,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 #define CONFIG_SYS_FSL_ERRATUM_ESDHC136 #define CONFIG_SYS_P4080_ERRATUM_CPU22 +#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 @@ -505,6 +522,18 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#elif defined(CONFIG_BSC9131) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 632e3c1669..53d563ed0a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) @@ -1934,7 +1934,11 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 #else +#ifdef CONFIG_BSC9131 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#else #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#endif #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 #endif #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 @@ -2081,6 +2085,50 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 #define MPC85xx_PMUXCR_SPI 0x00000000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 +#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 +#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 +#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 +#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 +#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 +#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 +#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 +#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 +#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 +#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 +#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 +#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 +#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 +#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 +#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 +#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 +#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 +#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 +#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 +#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 +#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 +#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 +#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 +#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 +#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 +#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 +#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 +#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 +#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 +#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 +#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 +#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 +#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 +#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C +#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 +#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 +#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 @@ -2111,7 +2159,69 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 +#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 +#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 +#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 +#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 +#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 +#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 +#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 +#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 +#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 +#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 +#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 +#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 +#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 + u32 pmuxcr3; + +#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 +#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 +#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 +#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 +#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 +#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 +#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 +#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 + u32 pmuxcr4; +#else u8 res6[8]; +#endif u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 #define MPC85xx_DEVDISR_PCI2 0x40000000 @@ -2166,7 +2276,14 @@ typedef struct ccsr_gur { u32 ddrdllcr; /* DDR DLL control */ u8 res14[12]; u32 lbcdllcr; /* LBC DLL control */ +#if defined(CONFIG_BSC9131) + u8 res15[12]; + u32 halt_req_mask; +#define HALTED_TO_HALT_REQ_MASK_0 0x80000000 + u8 res18[232]; +#else u8 res15[248]; +#endif u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ u32 ddrioovcr; /* DDR IO Override Control */ diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h index 56ac9fe6c5..6b52a94ffb 100644 --- a/arch/powerpc/include/asm/io.h +++ b/arch/powerpc/include/asm/io.h @@ -295,7 +295,7 @@ static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { #ifdef CONFIG_ADDR_MAP - return (void *)(addrmap_phys_to_virt(paddr)); + return addrmap_phys_to_virt(paddr); #else return (void *)((unsigned long)paddr); #endif diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 4e32639821..4eb88e9096 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1036,7 +1036,7 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/ /* whether MPC8xxxE (i.e. has SEC) */ #if defined(CONFIG_MPC85xx) @@ -1055,87 +1055,55 @@ */ #define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 #define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 #define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 #define SVR_8540 0x803000 #define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 #define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 #define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 #define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 +#define SVR_8547 0x803101 #define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 #define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 #define SVR_8560 0x807000 #define SVR_8567 0x807501 -#define SVR_8567_E 0x807D01 #define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 #define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 #define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 #define SVR_P1010 0x80F100 -#define SVR_P1010_E 0x80F900 #define SVR_P1011 0x80E500 -#define SVR_P1011_E 0x80ED00 #define SVR_P1012 0x80E501 -#define SVR_P1012_E 0x80ED01 #define SVR_P1013 0x80E700 -#define SVR_P1013_E 0x80EF00 #define SVR_P1014 0x80F101 -#define SVR_P1014_E 0x80F901 #define SVR_P1015 0x80E502 -#define SVR_P1015_E 0x80ED02 #define SVR_P1016 0x80E503 -#define SVR_P1016_E 0x80ED03 #define SVR_P1017 0x80F700 -#define SVR_P1017_E 0x80FF00 #define SVR_P1020 0x80E400 -#define SVR_P1020_E 0x80EC00 #define SVR_P1021 0x80E401 -#define SVR_P1021_E 0x80EC01 #define SVR_P1022 0x80E600 -#define SVR_P1022_E 0x80EE00 #define SVR_P1023 0x80F600 -#define SVR_P1023_E 0x80FE00 #define SVR_P1024 0x80E402 -#define SVR_P1024_E 0x80EC02 #define SVR_P1025 0x80E403 -#define SVR_P1025_E 0x80EC03 #define SVR_P2010 0x80E300 -#define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 #define SVR_P2040 0x821000 -#define SVR_P2040_E 0x821800 #define SVR_P2041 0x821001 -#define SVR_P2041_E 0x821801 #define SVR_P3041 0x821103 -#define SVR_P3041_E 0x821903 #define SVR_P3060 0x820002 -#define SVR_P3060_E 0x820802 #define SVR_P4040 0x820100 -#define SVR_P4040_E 0x820900 #define SVR_P4080 0x820000 -#define SVR_P4080_E 0x820800 #define SVR_P5010 0x822100 -#define SVR_P5010_E 0x822900 #define SVR_P5020 0x822000 -#define SVR_P5020_E 0x822800 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 #define SVR_8641D 0x809001 +#define SVR_9130 0x860001 +#define SVR_9130_E 0x860801 +#define SVR_9131 0x860000 +#define SVR_9131_E 0x860800 + #define SVR_Unknown 0xFFFFFF #define _GLOBAL(n)\ diff --git a/doc/README.ag101 b/board/AndesTech/adp-ag101/README index 46fc637742..46fc637742 100644 --- a/doc/README.ag101 +++ b/board/AndesTech/adp-ag101/README diff --git a/board/spear/spear310/config.mk b/board/BuS/vl_ma2sc/Makefile index f8a6bdb976..1cadfb30e0 100644 --- a/board/spear/spear310/config.mk +++ b/board/BuS/vl_ma2sc/Makefile @@ -1,6 +1,10 @@ # -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2009-2012 +# Jens Scharsig <esw@bus-elekronik.de> +# BuS Elektronik GmbH & Co. KG # # See file CREDITS for list of people who contributed to this # project. @@ -12,7 +16,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -21,24 +25,24 @@ # MA 02111-1307 USA # -######################################################################### +include $(TOPDIR)/config.mk -CONFIG_SYS_TEXT_BASE = 0x00700000 +LIB = $(obj)lib$(BOARD).o -ALL-y += $(obj)u-boot.img +COBJS += vl_ma2sc.o -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -# Support parallel flash -ifeq ($(FLASH),PNOR) -PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR -endif +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c new file mode 100644 index 0000000000..62ed6fb432 --- /dev/null +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -0,0 +1,551 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig <esw@bus-elekronik.de> + * BuS Elektronik GmbH & Co. KG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/sizes.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_common.h> +#include <lcd.h> +#include <i2c.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NAND +static void vl_ma2sc_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */ + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + /* Configure RDY/BSY */ +#ifdef CONFIG_SYS_NAND_READY_PIN + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + /* Enable NandFlash */ + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void vl_ma2sc_macb_hw_init(void) +{ + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + .vl_col = 320, + .vl_row = 240, + .vl_clk = 6500000, + .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED | + ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVVD_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5), + .vl_tft = 1, + .vl_hsync_len = 5, /* Horiz Sync Pulse Width */ + .vl_left_margin = 68, /* horiz back porch */ + .vl_right_margin = 20, /* horiz front porch */ + .vl_vsync_len = 2, /* vert Sync Pulse Width */ + .vl_upper_margin = 18, /* vert back porch */ + .vl_lower_margin = 4, /* vert front porch */ + .mmio = ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ +} + +void lcd_disable(void) +{ +} + +static void vl_ma2sc_lcd_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */ + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */ + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */ + at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */ + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */ + at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */ + at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */ + at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */ + + at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + gd->fb_base = ATMEL_BASE_SRAM0; +} +#endif /* Config LCD */ + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + at91_seriald_hw_init(); + + return 0; +} +#endif + +int board_init(void) +{ + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + pin = 0x1F000001; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); + writel((1 << 25), &pio->pioa.codr); + + pin = 0x1F000100; + writel(pin, &pio->piob.idr); + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.codr); + writel((1 << 24), &pio->piob.sodr); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + + pin = 0x0000000F; /* HWversion als Input */ + writel(pin, &pio->piod.idr); + writel(pin, &pio->piod.puer); + writel(pin, &pio->piod.per); + writel(pin, &pio->piod.odr); + writel(pin, &pio->piod.owdr); + + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup); + writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle); + writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse); + writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup); + +#ifdef CONFIG_CMD_NAND + vl_ma2sc_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + vl_ma2sc_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + vl_ma2sc_lcd_hw_init(); +#endif + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + uchar buffer[8]; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + buffer[0] = 0x04; + buffer[1] = 0x00; + if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0) + puts("error reseting rtc clock\n\0"); + + /* read hardware version */ + + pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44; + printf("Board: revision %c\n", pin); + buffer[0] = pin; + buffer[1] = 0; + setenv("revision", (char *) buffer); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01); +#endif + return rc; +} + +#ifdef CONFIG_SOFT_I2C +void i2c_init_board(void) +{ + u32 pin; + + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u8 sda = (1<<4); + u8 scl = (1<<5); + + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); + pin = sda | scl; + writel(pin, &pio->piob.idr); /* Disable Interupt */ + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.sodr); +} +#endif + +void watchdog_reset(void) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin = 0x1; /* PA0 */ + + if ((readl(&pio->pioa.odsr) & pin) > 0) + writel(pin, &pio->pioa.codr); + else + writel(pin, &pio->pioa.sodr); +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +/*---------------------------------------------------------------------------*/ + +int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + int col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */ + + pins = 0x1F000000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.oer); + writel(pins, &pio->pioa.sodr); + + pinz = 0x1F000000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.sodr); + + for (row = 0; row < 5; row++) { + for (col = 0; col < 5; col++) { + writel((0x01000000 << col), &pio->piob.sodr); + writel((0x01000000 << row), &pio->pioa.codr); + printf("LED Test %d x %d\n", row, col); + udelay(1000000); + writel(pinz, &pio->piob.codr); + writel(pins, &pio->pioa.sodr); + } + } + return rcode; +} + +void poweroff(void) +{ + watchdog_reset(); + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */ + udelay(100); + while (1) + watchdog_reset(); +} + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + poweroff(); + return rcode; +} + +int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + u32 freq; + u32 durate; + int rcode = 1; + + freq = 1000; + durate = 2; + switch (argc) { + case 3: + durate = simple_strtoul(argv[2], NULL, 10); + case 2: + freq = simple_strtoul(argv[1], NULL, 10); + case 1: + break; + default: + cmd_usage(cmdtp); + rcode = 1; + break; + } + durate = durate * freq; + freq = 500000 / freq; + for (i = 0; i < durate; i++) { + at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/ + udelay(freq); + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + udelay(freq); + } + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + return rcode; +} + +int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + u32 col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + writel((1 << ATMEL_ID_PIOA), &pmc->pcer); + + pins = 0x001F0000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.odr); + + pinz = 0x000F0000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.codr); + + while (1) { + col = 0; + for (row = 0; row < 4; row++) { + writel((0x00010000 << row), &pio->piob.sodr); + udelay(10000); + col <<= 4; + col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ; + writel(pinz, &pio->piob.codr); + } + printf("Matix: "); + for (row = 0; row < 16; row++) { + printf("%1.1d", col & 1); + col >>= 1; + } + printf(" SP %d\r ", + 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20))); + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) { + /* SHUTDOWN */ + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) + row++; + udelay(100); + } + udelay(100000); + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) { + row++; + udelay(1000); + } + } + poweroff(); + while (1) + ; + } + } + return rcode; +} + +/*****************************************************************************/ + +U_BOOT_CMD( + ledtest, 1, 0, do_ledtest, + "test ledmatrix", + "\n" + ); + +U_BOOT_CMD( + keytest, 1, 0, do_keytest, + "test keymatix and special keys, poweroff on pressing ON key", + "\n" + ); + +U_BOOT_CMD( + poweroff, 1, 0, do_poweroff, + "power off", + "\n" + ); + +U_BOOT_CMD( + beep, 3, 0, do_beep, + "[freq [duration]]", + "freq frequence of beep\nduration duration of beep\n" + ); + +/*****************************************************************************/ diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c index dc5350dc28..78d0edc66d 100644 --- a/board/LaCie/common/common.c +++ b/board/LaCie/common/common.c @@ -20,34 +20,25 @@ #define MV88E1116_RGMII_TXTM_CTRL (1 << 4) #define MV88E1116_RGMII_RXTM_CTRL (1 << 5) -void mv_phy_88e1116_init(const char *name) +void mv_phy_88e1116_init(const char *name, u16 phyaddr) { u16 reg; - u16 devadr; if (miiphy_set_current_dev(name)) return; - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; - } - /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); - printf("88E1116 Initialized on %s\n", name); + if (miiphy_reset(name, phyaddr) == 0) + printf("88E1116 Initialized on %s\n", name); } #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h index 82a9522236..2edd5abbcd 100644 --- a/board/LaCie/common/common.h +++ b/board/LaCie/common/common.h @@ -11,7 +11,7 @@ #define _LACIE_COMMON_H #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) -void mv_phy_88e1116_init(const char *name); +void mv_phy_88e1116_init(const char *name, u16 phyaddr); #endif #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) int lacie_read_mac_address(uchar *mac); diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index 1b33875f2f..4a9b30834a 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -96,6 +96,6 @@ int board_init(void) /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index d0b4adffc0..0e06c29153 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -75,7 +75,7 @@ int board_early_init_f(void) 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -109,7 +109,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index fbf020fde1..68e8a770c7 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -73,7 +73,7 @@ int board_early_init_f(void) MPP33_GPIO, /* Fan speed (bit 2) */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } @@ -107,7 +107,7 @@ int misc_init_r(void) /* Configure and initialize PHY */ void reset_phy(void) { - mv_phy_88e1116_init("egiga0"); + mv_phy_88e1116_init("egiga0", 8); } #endif diff --git a/doc/README.db64360 b/board/Marvell/db64360/README index ebac4cec19..ebac4cec19 100644 --- a/doc/README.db64360 +++ b/board/Marvell/db64360/README diff --git a/doc/README.db64460 b/board/Marvell/db64460/README index c6e01fe1ef..c6e01fe1ef 100644 --- a/doc/README.db64460 +++ b/board/Marvell/db64460/README diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index 31b73c98b0..d6497aaa07 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -99,7 +99,7 @@ int board_early_init_f(void) MPP49_GPIO, /* Wifi AP LED */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index 057c558682..f5c1c3cfd9 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -96,7 +96,7 @@ int board_early_init_f(void) MPP49_GPIO, /* B_GLED */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index 4c41f3b2ef..43852f6b24 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -98,7 +98,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index 2a10e69faf..d48f05a048 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -102,7 +102,7 @@ int board_early_init_f(void) 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 9c768bf595..1fd7677dcb 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -97,7 +97,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 71e6793098..688d3086d4 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -96,7 +96,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/doc/README.RPXClassic b/board/RPXClassic/README index e03f670d1c..e03f670d1c 100644 --- a/doc/README.RPXClassic +++ b/board/RPXClassic/README diff --git a/doc/README.RPXlite b/board/RPXlite/README index 3ca671126d..3ca671126d 100644 --- a/doc/README.RPXlite +++ b/board/RPXlite/README diff --git a/doc/README.PlanetCore b/board/RPXlite/README.PlanetCore index b73c5f5a87..b73c5f5a87 100644 --- a/doc/README.PlanetCore +++ b/board/RPXlite/README.PlanetCore diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index 38473e5808..fc88520b2d 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -100,7 +100,7 @@ int board_early_init_f(void) MPP49_GPIO, 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/doc/README.alaska8220 b/board/alaska/README index 334507397d..334507397d 100644 --- a/doc/README.alaska8220 +++ b/board/alaska/README diff --git a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c index 77cadeacbc..ff37df1f5c 100644 --- a/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c +++ b/board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c @@ -90,7 +90,7 @@ int checkboard(void) /* IPSR11 */ #define ET0_ERXD4 (0x4 << 4) #define ET0_ERXD5 (0x4 << 7) -#define ET0_ERXD6 (0x4 << 4) +#define ET0_ERXD6 (0x3 << 10) #define ET0_TX_EN (0x2 << 19) #define ET0_TX_ER (0x2 << 21) #define ET0_TX_CLK_A (0x4 << 23) @@ -99,7 +99,7 @@ int checkboard(void) (ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \ ET0_TX_CLK_A | ET0_RX_CLK_A) -#define GPSR1_INIT (0xFFBF7FFF) +#define GPSR1_INIT (0xFFFF7FFF) #define GPSR2_INIT (0x4005FEFF) #define GPSR3_INIT (0x2EFFFFFF) #define GPSR4_INIT (0xC7000000) diff --git a/doc/README.bamboo b/board/amcc/bamboo/README index e139c6d129..e139c6d129 100644 --- a/doc/README.bamboo +++ b/board/amcc/bamboo/README diff --git a/doc/README.ebony b/board/amcc/ebony/README index 4df00b3561..4df00b3561 100644 --- a/doc/README.ebony +++ b/board/amcc/ebony/README diff --git a/doc/README.ocotea b/board/amcc/ocotea/README.ocotea index be79b03c8a..be79b03c8a 100644 --- a/doc/README.ocotea +++ b/board/amcc/ocotea/README.ocotea diff --git a/doc/README.ocotea-PIBS-to-U-Boot b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot index 25dd2a2378..25dd2a2378 100644 --- a/doc/README.ocotea-PIBS-to-U-Boot +++ b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot diff --git a/doc/README-integrator b/board/armltd/integrator/README index 5a0e934924..5a0e934924 100644 --- a/doc/README-integrator +++ b/board/armltd/integrator/README diff --git a/board/atmel/at91sam9260ek/partition.c b/board/atmel/at91sam9260ek/partition.c index 2629c67186..9ec054f22b 100644 --- a/board/atmel/at91sam9260ek/partition.c +++ b/board/atmel/at91sam9260ek/partition.c @@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c index c739b116bf..51cac77d4f 100644 --- a/board/atmel/at91sam9261ek/partition.c +++ b/board/atmel/at91sam9261ek/partition.c @@ -34,7 +34,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 41ec752570..60ff1c0cd3 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -254,6 +254,7 @@ int board_early_init_f(void) (1 << ATMEL_ID_PIOCDE), &pmc->pcer); + at91_seriald_hw_init(); return 0; } @@ -267,7 +268,6 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); #endif diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c index 7e1d46f530..d48fab791c 100644 --- a/board/atmel/at91sam9263ek/partition.c +++ b/board/atmel/at91sam9263ek/partition.c @@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c index 7e1d46f530..d48fab791c 100644 --- a/board/atmel/at91sam9rlek/partition.c +++ b/board/atmel/at91sam9rlek/partition.c @@ -33,7 +33,7 @@ struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, + {0x00008400, 0x00083FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00084000, 0x00293FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00294000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, }; diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index f23b657041..2c14462eb6 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2010,2011 * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011 + * (C) Copyright 2011-2012 * Avionic Design GmbH <www.avionic-design.de> * * See file CREDITS for list of people who contributed to this @@ -36,75 +36,50 @@ #include <asm/arch/pinmux.h> #include <asm/arch/uart.h> #include <asm/arch/mmc.h> -#include "tamonten.h" -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif -DECLARE_GLOBAL_DATA_PTR; - -const struct tegra2_sysinfo sysinfo = { - CONFIG_TEGRA2_BOARD_STRING -}; - /* - * Routine: timer_init - * Description: init the timestamp and lastinc value + * Routine: gpio_config_uart + * Description: Does nothing on Tamonten - no conflict w/SPI. */ -int timer_init(void) +void gpio_config_uart(void) { - return 0; } -#ifdef CONFIG_TEGRA2_MMC -/* - * Routine: pin_mux_mmc - * Description: setup the pin muxes/tristate values for the SDMMC(s) - */ -static void pin_mux_mmc(void) +#ifdef CONFIG_BOARD_EARLY_INIT_F +void gpio_early_init(void) { - funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); + gpio_request(GPIO_PI4, NULL); + gpio_direction_output(GPIO_PI4, 1); } #endif +#ifdef CONFIG_TEGRA_MMC /* - * Routine: board_init - * Description: Early hardware init. + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) */ -int board_init(void) +static void pin_mux_mmc(void) { - clock_init(); - clock_verify(); - - /* boot param addr */ - gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); - - return 0; + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); + /* for write-protect GPIO PI6 */ + pinmux_tristate_disable(PINGRP_ATA); + /* for CD GPIO PH2 */ + pinmux_tristate_disable(PINGRP_ATD); } -#ifdef CONFIG_TEGRA2_MMC /* this is a weak define that we are overriding */ int board_mmc_init(bd_t *bd) { - debug("board_mmc_init called\n"); /* Enable muxes, etc. for SDMMC controllers */ pin_mux_mmc(); - gpio_config_mmc(); - debug("board_mmc_init: init eMMC\n"); - /* init dev 0, eMMC chip, with 4-bit bus */ - tegra2_mmc_init(0, 4, -1, GPIO_PH2); + /* init dev 0, SD slot, with 4-bit bus */ + tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2); return 0; } #endif - -#ifdef CONFIG_BOARD_EARLY_INIT_F -int board_early_init_f(void) -{ - /* Initialize selected UARTs */ - board_init_uart_f(); - return 0; -} -#endif /* EARLY_INIT */ diff --git a/board/avionic-design/dts/tegra2-medcom.dts b/board/avionic-design/dts/tegra2-medcom.dts new file mode 100644 index 0000000000..fc52f9ce4e --- /dev/null +++ b/board/avionic-design/dts/tegra2-medcom.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Avionic Design Medcom-Wide"; + compatible = "avionic-design,medcom", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/avionic-design/dts/tegra2-plutux.dts b/board/avionic-design/dts/tegra2-plutux.dts new file mode 100644 index 0000000000..cef49ad804 --- /dev/null +++ b/board/avionic-design/dts/tegra2-plutux.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Avionic Design Plutux"; + compatible = "avionic-design,plutux", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/avionic-design/dts/tegra2-tec.dts b/board/avionic-design/dts/tegra2-tec.dts new file mode 100644 index 0000000000..9faebd8bc6 --- /dev/null +++ b/board/avionic-design/dts/tegra2-tec.dts @@ -0,0 +1,58 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Avionic Design Tamonten Evaluation Carrier"; + compatible = "avionic-design,tec", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/avionic-design/medcom/Makefile b/board/avionic-design/medcom/Makefile index b0c318c439..d96d04306c 100644 --- a/board/avionic-design/medcom/Makefile +++ b/board/avionic-design/medcom/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2010,2011 # NVIDIA Corporation <www.nvidia.com> -# (C) Copyright 2011 +# (C) Copyright 2011,2012 # Avionic Design GmbH <www.avionic-design.de> # # See file CREDITS for list of people who contributed to this @@ -26,12 +26,12 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) +$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) endif LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o +COBJS := ../../nvidia/common/board.o COBJS += ../common/tamonten.o SRCS := $(COBJS:.o=.c) diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index b0c318c439..d96d04306c 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -1,7 +1,7 @@ # # (C) Copyright 2010,2011 # NVIDIA Corporation <www.nvidia.com> -# (C) Copyright 2011 +# (C) Copyright 2011,2012 # Avionic Design GmbH <www.avionic-design.de> # # See file CREDITS for list of people who contributed to this @@ -26,12 +26,12 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) +$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) endif LIB = $(obj)lib$(BOARD).o -COBJS := $(BOARD).o +COBJS := ../../nvidia/common/board.o COBJS += ../common/tamonten.o SRCS := $(COBJS:.o=.c) diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile new file mode 100644 index 0000000000..d96d04306c --- /dev/null +++ b/board/avionic-design/tec/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# (C) Copyright 2011,2012 +# Avionic Design GmbH <www.avionic-design.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := ../../nvidia/common/board.o +COBJS += ../common/tamonten.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c index a9e490252d..fefffc39c2 100644 --- a/board/bc3450/cmd_bc3450.c +++ b/board/bc3450/cmd_bc3450.c @@ -32,13 +32,6 @@ */ #if defined(CONFIG_CMD_BSP) -#undef DEBUG -#ifdef DEBUG -# define dprintf(fmt,args...) printf(fmt, ##args) -#else -# define dprintf(fmt,args...) -#endif - /* * Definitions for DS1620 chip */ @@ -52,7 +45,6 @@ #define THERM_WRITE_TL 0x02 #define THERM_WRITE_TH 0x01 -#define CONFIG_SYS_CPU 2 #define CONFIG_SYS_1SHOT 1 #define CONFIG_SYS_STANDALONE 0 @@ -129,7 +121,7 @@ int sm501_gpio_init (void) static int init_done = 0; if (init_done) { -/* dprintf("sm501_gpio_init: nothing to be done.\n"); */ + debug("sm501_gpio_init: nothing to be done.\n"); return 1; } @@ -162,7 +154,8 @@ int sm501_gpio_init (void) (PWR_OFF | BUZZER | FP_DATA_TRI); init_done = 1; -/* dprintf("sm501_gpio_init: done.\n"); */ + debug("sm501_gpio_init: done.\n"); + return 0; } diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index ca5e9b0454..5d8a0910de 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -17,6 +17,10 @@ #include <linux/types.h> #include <stdio_dev.h> +#include <lzma/LzmaTypes.h> +#include <lzma/LzmaDec.h> +#include <lzma/LzmaTools.h> + #include <asm/mach-common/bits/ppi.h> #include <asm/mach-common/bits/timer.h> @@ -24,12 +28,9 @@ #define LCD_Y_RES 240 /* Vertical Resolution */ #define DMA_BUS_SIZE 16 -#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */ +#include EASYLOGO_HEADER -#if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \ - !defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI) -# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI -#endif +#ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */ /* Interface 16/18-bit TFT over an 8-bit wide PPI using a * small Programmable Logic Device (CPLD) @@ -37,14 +38,12 @@ */ #ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI -#include <asm/bfin_logo_rgb565_230x230.h> #define LCD_BPP 16 /* Bit Per Pixel */ #define CLOCKS_PPIX 2 /* Clocks per pixel */ #define CPLD_DELAY 3 /* RGB565 pipeline delay */ #endif #ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI -#include <asm/bfin_logo_230x230.h> #define LCD_BPP 24 /* Bit Per Pixel */ #define CLOCKS_PPIX 3 /* Clocks per pixel */ #define CPLD_DELAY 5 /* RGB888 pipeline delay */ @@ -96,7 +95,6 @@ #endif #else /* t350mcqb */ -#include <asm/bfin_logo_230x230.h> #define LCD_BPP 24 /* Bit Per Pixel */ #define CLOCKS_PPIX 3 /* Clocks per pixel */ @@ -419,13 +417,23 @@ int drv_video_init(void) #ifdef EASYLOGO_ENABLE_GZIP unsigned char *data = EASYLOGO_DECOMP_BUFFER; unsigned long src_len = EASYLOGO_ENABLE_GZIP; - if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { + error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len); + bfin_logo.data = data; +#elif defined(EASYLOGO_ENABLE_LZMA) + unsigned char *data = EASYLOGO_DECOMP_BUFFER; + SizeT lzma_len = bfin_logo.size; + error = lzmaBuffToBuffDecompress(data, &lzma_len, + bfin_logo.data, EASYLOGO_ENABLE_LZMA); + bfin_logo.data = data; +#else + error = 0; +#endif + + if (error) { puts("Failed to decompress logo\n"); free(dst); return -1; } - bfin_logo.data = data; -#endif memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index 9bcf935568..6737ac1628 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -18,11 +18,15 @@ #include <linux/types.h> #include <stdio_dev.h> +#include <lzma/LzmaTypes.h> +#include <lzma/LzmaDec.h> +#include <lzma/LzmaTools.h> + #define DMA_SIZE16 2 #include <asm/mach-common/bits/eppi.h> -#include <asm/bfin_logo_230x230.h> +#include EASYLOGO_HEADER #define LCD_X_RES 480 /*Horizontal Resolution */ #define LCD_Y_RES 272 /* Vertical Resolution */ @@ -303,13 +307,23 @@ int drv_video_init(void) #ifdef EASYLOGO_ENABLE_GZIP unsigned char *data = EASYLOGO_DECOMP_BUFFER; unsigned long src_len = EASYLOGO_ENABLE_GZIP; - if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { + error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len); + bfin_logo.data = data; +#elif defined(EASYLOGO_ENABLE_LZMA) + unsigned char *data = EASYLOGO_DECOMP_BUFFER; + SizeT lzma_len = bfin_logo.size; + error = lzmaBuffToBuffDecompress(data, &lzma_len, + bfin_logo.data, EASYLOGO_ENABLE_LZMA); + bfin_logo.data = data; +#else + error = 0; +#endif + + if (error) { puts("Failed to decompress logo\n"); free(dst); return -1; } - bfin_logo.data = data; -#endif memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); diff --git a/board/spear/spear320/config.mk b/board/buffalo/lsxl/Makefile index f8a6bdb976..36f2560ba9 100644 --- a/board/spear/spear320/config.mk +++ b/board/buffalo/lsxl/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# Copyright (c) 2012 Michael Walle +# Michael Walle <michael@walle.cc> # # See file CREDITS for list of people who contributed to this # project. @@ -12,33 +12,33 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA # -######################################################################### +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := lsxl.o -CONFIG_SYS_TEXT_BASE = 0x00700000 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -ALL-y += $(obj)u-boot.img +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -# Support parallel flash -ifeq ($(FLASH),PNOR) -PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR -endif +sinclude $(obj).depend -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif +######################################################################### diff --git a/board/buffalo/lsxl/kwbimage-lschl.cfg b/board/buffalo/lsxl/kwbimage-lschl.cfg new file mode 100644 index 0000000000..2b9b3cd1b7 --- /dev/null +++ b/board/buffalo/lsxl/kwbimage-lschl.cfg @@ -0,0 +1,229 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle <michael@walle.cc> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B1B9B + +# L2 RAM Timing 0 +DATA 0xFFD20134 0xBBBBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# L2 RAM Timing 1 +DATA 0xFFD20138 0x00BBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# DDR Configuration register +DATA 0xFFD01400 0x43000618 +# bit13-0: 0x618, 1560 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +# DDR Controller Control Low +DATA 0xFFD01404 0x39543000 +# bit3-0: 0 required +# bit4: 0, addr/cmd in same cycle +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +# DDR Timing (Low) +DATA 0xFFD01408 0x3302444F +# bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0]) +# bit7-4: 4, 5 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 4, 5 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 0, 16 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 3, 4 cycle tRRD +# bit31-28: 3, 4 cyle tRTP + +# DDR Timing (High) +DATA 0xFFD0140C 0x00000823 +# bit6-0: 0x23, 35 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +# DDR Address Control +DATA 0xFFD01410 0x00000009 +# bit1-0: 1, Cs0width=x16 +# bit3-2: 2, Cs0size=512Mbit +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +# DDR Open Pages Control +DATA 0xFFD01414 0x00000000 +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +# DDR Operation +DATA 0xFFD01418 0x00000000 +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +# DDR Mode +DATA 0xFFD0141C 0x00000652 +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 3, Write recovery for auto-precharge (3 required) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +# DDR Extended Mode +DATA 0xFFD01420 0x00000042 +# bit0: 0, DRAM DLL enabled +# bit1: 1, DRAM drive strength reduced +# bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination) +# bit5-3: 0 required +# bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +# DDR Controller Control High +DATA 0xFFD01424 0x0000F17F +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required (???) +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +# DDR2 ODT Read Timing (default values) +DATA 0xFFD01428 0x00085520 +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +# DDR2 ODT Write Timing (default values) +DATA 0xFFD0147C 0x00008552 +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +# CS[0]n Base address +DATA 0xFFD01500 0x00000000 +# at 0x0 + +# CS[0]n Size +DATA 0xFFD01504 0x03FFFFF1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x03, Size (i.e. 64MB) + +# CS[1]n Size +DATA 0xFFD0150C 0x00000000 +# window disabled + +# CS[2]n Size +DATA 0xFFD01514 0x00000000 +# window disabled + +# CS[3]n Size +DATA 0xFFD0151C 0x00000000 +# window disabled + +# DDR ODT Control (Low) +DATA 0xFFD01494 0x003C0000 +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3 +# bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1 +# bit31-24: 0 required + +# DDR ODT Control (High) +DATA 0xFFD01498 0x00000000 +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +# CPU ODT Control +DATA 0xFFD0149C 0x0000E80F +# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +# DDR Initialization Control +DATA 0xFFD01480 0x00000001 +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/kwbimage-lsxhl.cfg b/board/buffalo/lsxl/kwbimage-lsxhl.cfg new file mode 100644 index 0000000000..8a94b6c718 --- /dev/null +++ b/board/buffalo/lsxl/kwbimage-lsxhl.cfg @@ -0,0 +1,229 @@ +# +# Copyright (c) 2012 Michael Walle +# Michael Walle <michael@walle.cc> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100E0 0x1B1B9B9B + +# L2 RAM Timing 0 +DATA 0xFFD20134 0xBBBBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# L2 RAM Timing 1 +DATA 0xFFD20138 0x00BBBBBB +# not further specified in HW manual, timing taken from original vendor port + +# DDR Configuration register +DATA 0xFFD01400 0x43000618 +# bit13-0: 0x618, 1560 DDR2 clks refresh rate +# bit23-14: 0 required +# bit24: 1, enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: 0 required +# bit31-30: 0b01 required + +# DDR Controller Control Low +DATA 0xFFD01404 0x39543010 +# bit3-0: 0 required +# bit4: 1, T2 mode, addr/cmd are driven for two cycles +# bit5: 0, clk is driven during self refresh, we don't care for APX +# bit6: 0, use recommended falling edge of clk for addr/cmd +# bit11-7: 0 required +# bit12: 1 required +# bit13: 1 required +# bit14: 0, input buffer always powered up +# bit17-15: 0 required +# bit18: 1, cpu lock transaction enabled +# bit19: 0 required +# bit23-20: 5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 9, CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0, no additional STARTBURST delay + +# DDR Timing (Low) +DATA 0xFFD01408 0x22125441 +# bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0]) +# bit7-4: 4, 5 cycle tRCD +# bit11-8: 4, 5 cyle tRP +# bit15-12: 5, 6 cyle tWR +# bit19-16: 2, 3 cyle tWTR +# bit20: 1, 18 cycle tRAS (tRAS[4]) +# bit23-21: 0 required +# bit27-24: 2, 3 cycle tRRD +# bit31-28: 2, 3 cyle tRTP + +# DDR Timing (High) +DATA 0xFFD0140C 0x00000832 +# bit6-0: 0x32, 50 cycle tRFC +# bit8-7: 0, 1 cycle tR2R +# bit10-9: 0, 1 cyle tR2W +# bit12-11: 1, 2 cylce tW2W +# bit31-13: 0 required + +# DDR Address Control +DATA 0xFFD01410 0x0000000C +# bit1-0: 0, Cs0width=x8 +# bit3-2: 3, Cs0size=1Gbit +# bit5-4: 0, Cs1width=nonexistent +# bit7-6: 0, Cs1size=nonexistent +# bit9-8: 0, Cs2width=nonexistent +# bit11-10: 0, Cs2size=nonexistent +# bit13-12: 0, Cs3width=nonexistent +# bit15-14: 0, Cs3size=nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +# DDR Open Pages Control +DATA 0xFFD01414 0x00000000 +# bit0: 0, OPEn=OpenPage enabled +# bit31-1: 0 required + +# DDR Operation +DATA 0xFFD01418 0x00000000 +# bit3-0: 0, Cmd=Normal SDRAM Mode +# bit31-4: 0 required + +# DDR Mode +DATA 0xFFD0141C 0x00000652 +# bit2-0: 2, Burst Length (2 required) +# bit3: 0, Burst Type (0 required) +# bit6-4: 5, CAS Latency (CL) 5 +# bit7: 0, (Test Mode) Normal operation +# bit8: 0, (Reset DLL) Normal operation +# bit11-9: 3, Write recovery for auto-precharge (3 required) +# bit12: 0, Fast Active power down exit time (0 required) +# bit31-13: 0 required + +# DDR Extended Mode +DATA 0xFFD01420 0x00000006 +# bit0: 0, DRAM DLL enabled +# bit1: 1, DRAM drive strength reduced +# bit2: 1, ODT control Rtt[0] (Rtt=1, 75 ohm termination) +# bit5-3: 0 required +# bit6: 0, ODT control Rtt[1] (Rtt=1, 75 ohm termination) +# bit9-7: 0 required +# bit10: 0, differential DQS enabled +# bit11: 0 required +# bit12: 0, DRAM output buffer enabled +# bit31-13: 0 required + +# DDR Controller Control High +DATA 0xFFD01424 0x0000F17F +# bit2-0: 0x7 required +# bit3: 1, MBUS Burst Chop disabled +# bit6-4: 0x7 required +# bit7: 0 required (???) +# bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0, no half clock cycle addition to dataout +# bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf required +# bit31-16: 0 required + +# DDR2 ODT Read Timing (default values) +DATA 0xFFD01428 0x00085520 +# bit3-0: 0 required +# bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal +# bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal +# bit31-20: 0 required + +# DDR2 ODT Write Timing (default values) +DATA 0xFFD0147C 0x00008552 +# bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal +# bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal +# bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal +# bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal +# bit31-16: 0 required + +# CS[0]n Base address +DATA 0xFFD01500 0x00000000 +# at 0x0 + +# CS[0]n Size +DATA 0xFFD01504 0x0FFFFFF1 +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff required +# bit31-24: 0x0f, Size (i.e. 256MB) + +# CS[1]n Size +DATA 0xFFD0150C 0x00000000 +# window disabled + +# CS[2]n Size +DATA 0xFFD01514 0x00000000 +# window disabled + +# CS[3]n Size +DATA 0xFFD0151C 0x00000000 +# window disabled + +# DDR ODT Control (Low) +DATA 0xFFD01494 0x00010000 +# bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM +# bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM +# bit15-8: 0 required +# bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0 +# bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM +# bit31-24: 0 required + +# DDR ODT Control (High) +DATA 0xFFD01498 0x00000000 +# bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register +# bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register +# bit31-4 0 required + +# CPU ODT Control +DATA 0xFFD0149C 0x0000E80F +# bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3 +# bit9-8: 0, Internal ODT assertion is controlled by fiels +# bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm +# bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm +# bit14: 1, M_STARTBURST_IN ODT enabled +# bit15: 1, DDR IO ODT Unit: Drive ODT calibration values +# bit20-16: 0, Pad N channel driving strength for ODT +# bit25-21: 0, Pad P channel driving strength for ODT +# bit31-26: 0 required + +# DDR Initialization Control +DATA 0xFFD01480 0x00000001 +# bit0: 1, enable DDR init upon this register write +# bit31-1: 0, required + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c new file mode 100644 index 0000000000..fe155112c9 --- /dev/null +++ b/board/buffalo/lsxl/lsxl.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle <michael@walle.cc> + * + * Based on sheevaplug/sheevaplug.c by + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <net.h> +#include <malloc.h> +#include <netdev.h> +#include <miiphy.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> +#include <spi_flash.h> + +#include "lsxl.h" + +/* + * Rescue mode + * + * Selected by holding the push button for 3 seconds, while powering on + * the device. + * + * These linkstations don't have a (populated) serial port. There is no + * way to access an (unmodified) board other than using the netconsole. If + * you want to recover from a bad environment setting or an empty environment, + * you can do this only with a working network connection. Therefore, a random + * ethernet address is generated if none is set and a DHCP request is sent. + * After a successful DHCP response is received, the network settings are + * configured and the ncip parameter is set to the serverip. Eg. for a working + * resuce mode, you should set 'next-server' to the host where the netconsole + * client is started. + * Additionally, the bootsource is set to 'rescue'. + */ + +#ifndef CONFIG_ENV_OVERWRITE +# error "You need to set CONFIG_ENV_OVERWRITE" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(LSXL_OE_VAL_LOW, + LSXL_OE_VAL_HIGH, + LSXL_OE_LOW, LSXL_OE_HIGH); + + /* + * Multi-Purpose Pins Functionality configuration + * These strappings are taken from the original vendor uboot port. + */ + u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_UART0_RXD, + MPP5_UART0_TXD, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_GPIO, + MPP9_GPIO, + MPP10_GPO, /* HDD power */ + MPP11_GPIO, /* USB Vbus enable */ + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_GPO, /* fan speed high */ + MPP19_GPO, /* fan speed low */ + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, /* function LED */ + MPP37_GPIO, /* alarm LED */ + MPP38_GPIO, /* info LED */ + MPP39_GPIO, /* power LED */ + MPP40_GPIO, /* fan alarm */ + MPP41_GPIO, /* funtion button */ + MPP42_GPIO, /* power switch */ + MPP43_GPIO, /* power auto switch */ + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, /* function red LED */ + MPP49_GPIO, + 0 + }; + + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +#define LED_OFF 0 +#define LED_ALARM_ON 1 +#define LED_ALARM_BLINKING 2 +#define LED_POWER_ON 3 +#define LED_POWER_BLINKING 4 +#define LED_INFO_ON 5 +#define LED_INFO_BLINKING 6 + +static void __set_led(int blink_alarm, int blink_info, int blink_power, + int value_alarm, int value_info, int value_power) +{ + kw_gpio_set_blink(GPIO_ALARM_LED, blink_alarm); + kw_gpio_set_blink(GPIO_INFO_LED, blink_info); + kw_gpio_set_blink(GPIO_POWER_LED, blink_power); + kw_gpio_set_value(GPIO_ALARM_LED, value_alarm); + kw_gpio_set_value(GPIO_INFO_LED, value_info); + kw_gpio_set_value(GPIO_POWER_LED, value_power); +} + +static void set_led(int state) +{ + switch (state) { + case LED_OFF: + __set_led(0, 0, 0, 0, 0, 0); + break; + case LED_ALARM_ON: + __set_led(0, 0, 0, 0, 1, 1); + break; + case LED_ALARM_BLINKING: + __set_led(1, 0, 0, 1, 1, 1); + break; + case LED_INFO_ON: + __set_led(0, 0, 0, 1, 0, 1); + break; + case LED_INFO_BLINKING: + __set_led(0, 1, 0, 1, 1, 1); + break; + case LED_POWER_ON: + __set_led(0, 0, 0, 1, 1, 0); + break; + case LED_POWER_BLINKING: + __set_led(0, 0, 1, 1, 1, 1); + break; + } +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + set_led(LED_POWER_BLINKING); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +void check_enetaddr(void) +{ + uchar enetaddr[6]; + + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + /* signal unset/invalid ethaddr to user */ + set_led(LED_INFO_BLINKING); + } +} + +static void erase_environment(void) +{ + struct spi_flash *flash; + + printf("Erasing environment..\n"); + flash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!flash) { + printf("Erasing flash failed\n"); + return; + } + + spi_flash_erase(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); + spi_flash_free(flash); + do_reset(NULL, 0, 0, NULL); +} + +static void rescue_mode(void) +{ + uchar enetaddr[6]; + + printf("Entering rescue mode..\n"); +#ifdef CONFIG_RANDOM_MACADDR + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { + eth_random_enetaddr(enetaddr); + if (eth_setenv_enetaddr("ethaddr", enetaddr)) { + printf("Failed to set ethernet address\n"); + set_led(LED_ALARM_BLINKING); + return; + } + } +#endif + setenv("bootsource", "rescue"); +} + +static void check_push_button(void) +{ + int i = 0; + + while (!kw_gpio_get_value(GPIO_FUNC_BUTTON)) { + udelay(100000); + i++; + + if (i == 10) + set_led(LED_INFO_ON); + + if (i >= 100) { + set_led(LED_INFO_BLINKING); + break; + } + } + + if (i >= 100) + erase_environment(); + else if (i >= 10) + rescue_mode(); +} + +int misc_init_r(void) +{ + check_enetaddr(); + check_push_button(); + + return 0; +} +#endif + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int progress) +{ + if (progress > 0) + return; + + /* this is not an error, eg. bootp with autoload=no will trigger this */ + if (progress == -BOOTSTAGE_ID_NET_LOADED) + return; + + set_led(LED_ALARM_BLINKING); +} +#endif diff --git a/board/buffalo/lsxl/lsxl.h b/board/buffalo/lsxl/lsxl.h new file mode 100644 index 0000000000..2a2642e487 --- /dev/null +++ b/board/buffalo/lsxl/lsxl.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle <michael@walle.cc> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __LSXL_H +#define __LSXL_H + +#define GPIO_HDD_POWER 10 +#define GPIO_USB_VBUS 11 +#define GPIO_FAN_HIGH 18 +#define GPIO_FAN_LOW 19 +#define GPIO_FUNC_LED 36 +#define GPIO_ALARM_LED 37 +#define GPIO_INFO_LED 38 +#define GPIO_POWER_LED 39 +#define GPIO_FAN_LOCK 40 +#define GPIO_FUNC_BUTTON 41 +#define GPIO_POWER_SWITCH 42 +#define GPIO_POWER_AUTO_SWITCH 43 +#define GPIO_FUNC_RED_LED 48 + +#define _BIT(x) (1<<(x)) + +#define LSXL_OE_LOW (~(_BIT(GPIO_HDD_POWER) \ + | _BIT(GPIO_USB_VBUS) \ + | _BIT(GPIO_FAN_HIGH) \ + | _BIT(GPIO_FAN_LOW))) + +#define LSXL_OE_HIGH (~(_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32))) + +#define LSXL_OE_VAL_LOW (_BIT(GPIO_HDD_POWER) \ + | _BIT(GPIO_USB_VBUS)) + +#define LSXL_OE_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32)) + +#define LSXL_POL_VAL_LOW (_BIT(GPIO_FAN_HIGH) \ + | _BIT(GPIO_FAN_LOW)) + +#define LSXL_POL_VAL_HIGH (_BIT(GPIO_FUNC_LED - 32) \ + | _BIT(GPIO_ALARM_LED - 32) \ + | _BIT(GPIO_INFO_LED - 32) \ + | _BIT(GPIO_POWER_LED - 32) \ + | _BIT(GPIO_FUNC_BUTTON - 32) \ + | _BIT(GPIO_POWER_SWITCH - 32) \ + | _BIT(GPIO_POWER_AUTO_SWITCH - 32) \ + | _BIT(GPIO_FUNC_RED_LED - 32)) + +#endif /* __LSXL_H */ diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index ff3421d576..bac9ce55a8 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -71,7 +71,7 @@ int board_early_init_f(void) MPP49_GPIO, /* LED orange */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index 4703098149..a43413e976 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -18,13 +18,15 @@ #include <linux/types.h> #include <stdio_dev.h> -#ifdef CONFIG_VIDEO +#include <lzma/LzmaTypes.h> +#include <lzma/LzmaDec.h> +#include <lzma/LzmaTools.h> #define DMA_SIZE16 2 #include <asm/mach-common/bits/eppi.h> -#include <asm/bfin_logo_230x230.h> +#include EASYLOGO_HEADER #define LCD_X_RES 480 /*Horizontal Resolution */ #define LCD_Y_RES 272 /* Vertical Resolution */ @@ -303,16 +305,27 @@ int drv_video_init(void) printf("Failed to alloc FB memory\n"); return -1; } + #ifdef EASYLOGO_ENABLE_GZIP unsigned char *data = EASYLOGO_DECOMP_BUFFER; unsigned long src_len = EASYLOGO_ENABLE_GZIP; - if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { + error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len); + bfin_logo.data = data; +#elif defined(EASYLOGO_ENABLE_LZMA) + unsigned char *data = EASYLOGO_DECOMP_BUFFER; + SizeT lzma_len = bfin_logo.size; + error = lzmaBuffToBuffDecompress(data, &lzma_len, + bfin_logo.data, EASYLOGO_ENABLE_LZMA); + bfin_logo.data = data; +#else + error = 0; +#endif + + if (error) { puts("Failed to decompress logo\n"); free(dst); return -1; } - bfin_logo.data = data; -#endif memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); @@ -335,5 +348,3 @@ int drv_video_init(void) return (error == 0) ? devices : error; } - -#endif diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 89e6b08e7f..700c184944 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -99,6 +99,39 @@ int board_init(void) return 0; } +static u32 cm_t3x_rev; + +/* + * Routine: get_board_rev + * Description: read system revision + */ +u32 get_board_rev(void) +{ + if (!cm_t3x_rev) + cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); + + return cm_t3x_rev; +}; + +/* + * Routine: misc_init_r + * Description: display die ID + */ +int misc_init_r(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); + dieid_num_r(); + + return 0; +} + /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the diff --git a/board/cm_t35/eeprom.c b/board/cm_t35/eeprom.c index dfa171d233..b0af103cdd 100644 --- a/board/cm_t35/eeprom.c +++ b/board/cm_t35/eeprom.c @@ -27,8 +27,7 @@ #define BOARD_SERIAL_OFFSET_LEGACY 8 #define BOARD_REV_OFFSET 0 #define BOARD_REV_OFFSET_LEGACY 6 -#define BOARD_REV_SIZE 4 -#define BOARD_REV_SIZE_LEGACY 2 +#define BOARD_REV_SIZE 2 #define MAC_ADDR_OFFSET 4 #define MAC_ADDR_OFFSET_LEGACY 0 @@ -100,25 +99,32 @@ int cm_t3x_eeprom_read_mac_addr(uchar *buf) } /* - * Routine: get_board_rev - * Description: read system revision + * Routine: cm_t3x_eeprom_get_board_rev + * Description: read system revision from eeprom */ -u32 get_board_rev(void) +u32 cm_t3x_eeprom_get_board_rev(void) { u32 rev = 0; + char str[5]; /* Legacy representation can contain at most 4 digits */ uint offset = BOARD_REV_OFFSET_LEGACY; - int len = BOARD_REV_SIZE_LEGACY; if (eeprom_setup_layout()) return 0; - if (eeprom_layout != LAYOUT_LEGACY) { + if (eeprom_layout != LAYOUT_LEGACY) offset = BOARD_REV_OFFSET; - len = BOARD_REV_SIZE; - } - if (cm_t3x_eeprom_read(offset, (uchar *)&rev, len)) + if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) return 0; + /* + * Convert legacy syntactic representation to semantic + * representation. i.e. for rev 1.00: 0x100 --> 0x64 + */ + if (eeprom_layout == LAYOUT_LEGACY) { + sprintf(str, "%x", rev); + rev = simple_strtoul(str, NULL, 10); + } + return rev; }; diff --git a/board/cm_t35/eeprom.h b/board/cm_t35/eeprom.h index ec772c6710..38824d162b 100644 --- a/board/cm_t35/eeprom.h +++ b/board/cm_t35/eeprom.h @@ -23,11 +23,16 @@ #ifdef CONFIG_DRIVER_OMAP34XX_I2C int cm_t3x_eeprom_read_mac_addr(uchar *buf); +u32 cm_t3x_eeprom_get_board_rev(void); #else static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) { return 1; } +static inline u32 cm_t3x_eeprom_get_board_rev(void) +{ + return 0; +} #endif #endif diff --git a/doc/README.cmi b/board/cmi/README index 0edd50ad22..0edd50ad22 100644 --- a/doc/README.cmi +++ b/board/cmi/README diff --git a/doc/README.COBRA5272 b/board/cobra5272/README index ae0f148258..ae0f148258 100644 --- a/doc/README.COBRA5272 +++ b/board/cobra5272/README diff --git a/board/compal/dts/tegra2-paz00.dts b/board/compal/dts/tegra2-paz00.dts new file mode 100644 index 0000000000..9e3e169069 --- /dev/null +++ b/board/compal/dts/tegra2-paz00.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x20000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c index 3b48917430..ec678746d3 100644 --- a/board/compal/paz00/paz00.c +++ b/board/compal/paz00/paz00.c @@ -20,7 +20,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif @@ -32,7 +32,7 @@ void gpio_config_uart(void) { } -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) @@ -48,15 +48,15 @@ static void pin_mux_mmc(void) pinmux_tristate_disable(PINGRP_GMA); pinmux_tristate_disable(PINGRP_GME); - /* SDMMC1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ - pinmux_set_func(PINGRP_SDMMC1, PMUX_FUNC_SDIO1); + /* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */ + pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PINGRP_SDMMC1); + pinmux_tristate_disable(PINGRP_SDIO1); /* For power GPIO PV1 */ pinmux_tristate_disable(PINGRP_UAC); - /* For CD GPIO PI5 */ - pinmux_tristate_disable(PINGRP_ATC); + /* For CD GPIO PV5 */ + pinmux_tristate_disable(PINGRP_GPV); } /* this is a weak define that we are overriding */ @@ -74,7 +74,7 @@ int board_mmc_init(bd_t *bd) debug("board_mmc_init: init SD slot\n"); /* init dev 3, SD slot, with 4-bit bus */ - tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PI5); + tegra2_mmc_init(3, 4, GPIO_PV1, GPIO_PV5); return 0; } diff --git a/board/compulab/dts/tegra2-trimslice.dts b/board/compulab/dts/tegra2-trimslice.dts new file mode 100644 index 0000000000..db79e7796d --- /dev/null +++ b/board/compulab/dts/tegra2-trimslice.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "Compulab TrimSlice board"; + compatible = "compulab,trimslice", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = <216000000>; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile new file mode 100644 index 0000000000..bf624f41a2 --- /dev/null +++ b/board/compulab/trimslice/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../nvidia/common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +COBJS += ../../nvidia/common/board.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c new file mode 100644 index 0000000000..1ac15f8da5 --- /dev/null +++ b/board/compulab/trimslice/trimslice.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/mmc.h> +#include <asm/gpio.h> +#ifdef CONFIG_TEGRA_MMC +#include <mmc.h> +#endif + +/* + * Routine: gpio_config_uart + * Description: Does nothing on TrimSlice - no UART-related GPIOs. + */ +void gpio_config_uart(void) +{ +} + +void pin_mux_spi(void) +{ + funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); + + /* For CD GPIO PP1 */ + pinmux_tristate_disable(PINGRP_DAP3); +} + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("board_mmc_init called\n"); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */ + tegra2_mmc_init(0, 4, -1, GPIO_PP1); + + /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */ + tegra2_mmc_init(3, 4, -1, -1); + + return 0; +} diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 990d79fe11..11260fe5f6 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -97,7 +97,7 @@ int board_early_init_f(void) MPP49_GPIO, /* thermal sensor */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1); diff --git a/doc/README.hawkboard b/board/davinci/da8xxevm/README.hawkboard index d6ae02ec02..d6ae02ec02 100644 --- a/doc/README.hawkboard +++ b/board/davinci/da8xxevm/README.hawkboard diff --git a/doc/README.dnp5370 b/board/dnp5370/README index 0172698e96..0172698e96 100644 --- a/doc/README.dnp5370 +++ b/board/dnp5370/README diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile index fdd188ecfc..bd2174fec3 100644 --- a/board/efikamx/Makefile +++ b/board/efikamx/Makefile @@ -33,12 +33,11 @@ ifdef CONFIG_CMD_USB COBJS += efikamx-usb.o endif -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 6c0d931eea..0874e9c4e8 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -35,6 +35,8 @@ #include <mmc.h> #include <net.h> #include <netdev.h> +#include <spi.h> +#include <linux/ctype.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/da850_lowlevel.h> @@ -86,16 +88,22 @@ static const struct pinmux_config enbw_pins[] = { { pinmux(5), 1, 0 }, { pinmux(5), 1, 3 }, { pinmux(5), 1, 7 }, - { pinmux(6), 1, 0 }, - { pinmux(6), 1, 1 }, + { pinmux(5), 1, 5 }, + { pinmux(5), 1, 4 }, + { pinmux(5), 1, 3 }, + { pinmux(5), 1, 2 }, + { pinmux(5), 1, 1 }, + { pinmux(5), 1, 0 }, + { pinmux(6), 8, 0 }, + { pinmux(6), 8, 1 }, { pinmux(6), 8, 2 }, { pinmux(6), 8, 3 }, - { pinmux(6), 1, 4 }, + { pinmux(6), 8, 4 }, { pinmux(6), 8, 5 }, { pinmux(6), 1, 7 }, { pinmux(7), 8, 2 }, { pinmux(7), 1, 3 }, - { pinmux(7), 1, 6 }, + { pinmux(7), 8, 6 }, { pinmux(7), 1, 7 }, { pinmux(13), 8, 2 }, { pinmux(13), 8, 3 }, @@ -163,24 +171,37 @@ struct gpio_config { unsigned char value; }; -static const struct gpio_config enbw_gpio_config[] = { +static const struct gpio_config enbw_gpio_config_hut[] = { + { "RS485 enable", 8, 11, 1, 0 }, + { "RS485 iso", 8, 10, 1, 1 }, + { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, + { "W2HUT RS485 iso", 8, 8, 1, 1 }, +}; + +static const struct gpio_config enbw_gpio_config_w[] = { { "RS485 enable", 8, 11, 1, 0 }, { "RS485 iso", 8, 10, 1, 0 }, { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, { "W2HUT RS485 iso", 8, 8, 1, 0 }, +}; + +static const struct gpio_config enbw_gpio_config[] = { { "LAN reset", 7, 15, 1, 1 }, { "ena 11V PLC", 7, 14, 1, 0 }, { "ena 1.5V PLC", 7, 13, 1, 0 }, { "disable VBUS", 7, 12, 1, 1 }, - { "PLC reset", 6, 13, 1, 1 }, + { "PLC reset", 6, 13, 1, 0 }, { "LCM RS", 6, 12, 1, 0 }, { "LCM R/W", 6, 11, 1, 0 }, { "PLC pairing", 6, 10, 1, 1 }, { "PLC MDIO CLK", 6, 9, 1, 0 }, { "HK218", 6, 8, 1, 0 }, { "HK218 Rx", 6, 1, 1, 1 }, - { "TPM reset", 6, 0, 1, 1 }, - { "LCM E", 2, 2, 1, 1 }, + { "TPM reset", 6, 0, 1, 0 }, + { "Board-Type", 3, 9, 0, 0 }, + { "HW-ID0", 2, 7, 0, 0 }, + { "HW-ID1", 2, 6, 0, 0 }, + { "HW-ID2", 2, 3, 0, 0 }, { "PV-IF RxD ena", 0, 15, 1, 1 }, { "LED1", 1, 15, 1, 1 }, { "LED2", 0, 1, 1, 1 }, @@ -229,34 +250,57 @@ static void enbw_cmc_switch(int port, int on) } } -int board_init(void) +static int enbw_cmc_init_gpio(const struct gpio_config *conf, int sz) { int i, ret; -#ifndef CONFIG_USE_IRQ - irq_init(); -#endif - /* address of boot parameters, not used as booting with DTT */ - gd->bd->bi_boot_params = 0; + for (i = 0; i < sz; i++) { + int gpio = conf[i].bank * 16 + + conf[i].gpio; - for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) { - int gpio = enbw_gpio_config[i].bank * 16 + - enbw_gpio_config[i].gpio; - - ret = gpio_request(gpio, enbw_gpio_config[i].name); + ret = gpio_request(gpio, conf[i].name); if (ret) { printf("%s: Could not get %s gpio\n", __func__, - enbw_gpio_config[i].name); - return -1; + conf[i].name); + return ret; } - if (enbw_gpio_config[i].out) + if (conf[i].out) gpio_direction_output(gpio, - enbw_gpio_config[i].value); + conf[i].value); else gpio_direction_input(gpio); } + return 0; +} + +int board_init(void) +{ + int board_type, hw_id; + +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + /* address of boot parameters, not used as booting with DTT */ + gd->bd->bi_boot_params = 0; + + enbw_cmc_init_gpio(enbw_gpio_config, ARRAY_SIZE(enbw_gpio_config)); + + /* detect HW version */ + board_type = gpio_get_value(CONFIG_ENBW_CMC_BOARD_TYPE); + hw_id = gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT0) + + (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT1) << 1) + + (gpio_get_value(CONFIG_ENBW_CMC_HW_ID_BIT2) << 2); + printf("BOARD: CMC-%s hw id: %d\n", (board_type ? "w2" : "hut"), + hw_id); + if (board_type) + enbw_cmc_init_gpio(enbw_gpio_config_w, + ARRAY_SIZE(enbw_gpio_config_w)); + else + enbw_cmc_init_gpio(enbw_gpio_config_hut, + ARRAY_SIZE(enbw_gpio_config_hut)); + /* setup the SUSPSRC for ARM to control emulation suspend */ clrbits_le32(&davinci_syscfg_regs->suspsrc, (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | @@ -267,14 +311,231 @@ int board_init(void) } #ifdef CONFIG_DRIVER_TI_EMAC + +#define KSZ_CMD_READ 0x03 +#define KSZ_CMD_WRITE 0x02 +#define KSZ_ID 0x95 + +static int enbw_cmc_switch_read(struct spi_slave *spi, u8 reg, u8 *val) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + int cmd_len; + u8 cmd[2]; + + cmd[0] = KSZ_CMD_READ; + cmd[1] = reg; + cmd_len = 2; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("Failed to send command (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + flags |= SPI_XFER_END; + *val = 0; + cmd_len = 1; + ret = spi_xfer(spi, cmd_len * 8, NULL, val, flags); + if (ret) { + debug("Failed to read (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + + return 0; +} + +static int enbw_cmc_switch_read_ident(struct spi_slave *spi) +{ + int ret; + u8 val; + + ret = enbw_cmc_switch_read(spi, 0, &val); + if (ret) { + debug("Failed to read\n"); + return -EINVAL; + } + + if (val != KSZ_ID) + return -EINVAL; + + return 0; +} + +static int enbw_cmc_switch_write(struct spi_slave *spi, unsigned long reg, + unsigned long val) +{ + unsigned long flags = SPI_XFER_BEGIN; + int ret; + int cmd_len; + u8 cmd[3]; + + cmd[0] = KSZ_CMD_WRITE; + cmd[1] = reg; + cmd[2] = val; + cmd_len = 3; + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); + if (ret) { + debug("Failed to send command (%zu bytes): %d\n", + cmd_len, ret); + return -EINVAL; + } + + udelay(1000); + ret = enbw_cmc_switch_read(spi, reg, &cmd[0]); + if (ret) { + debug("Failed to read\n"); + return -EINVAL; + } + if (val != cmd[0]) + debug("warning: reg: %lx va: %x soll: %lx\n", + reg, cmd[0], val); + + return 0; +} + +static int enbw_cmc_eof(unsigned char *ptr) +{ + if (*ptr == 0xff) + return 1; + + return 0; +} + +static char *enbw_cmc_getnewline(char *ptr) +{ + while (*ptr != 0x0a) { + ptr++; + if (enbw_cmc_eof((unsigned char *)ptr)) + return NULL; + } + + ptr++; + return ptr; +} + +static char *enbw_cmc_getvalue(char *ptr, int *value) +{ + int end = 0; + + *value = -EINVAL; + + if (!isxdigit(*ptr)) + end = 1; + + while (end) { + if ((*ptr == '#') || (*ptr == ';')) { + ptr = enbw_cmc_getnewline(ptr); + return ptr; + } + if (ptr != NULL) { + if (isxdigit(*ptr)) { + end = 0; + } else if (*ptr == 0x0a) { + ptr++; + return ptr; + } else { + ptr++; + if (enbw_cmc_eof((unsigned char *)ptr)) + return NULL; + } + } else { + return NULL; + } + } + *value = (int)simple_strtoul((const char *)ptr, &ptr, 16); + ptr++; + return ptr; +} + +static int enbw_cmc_config_switch(unsigned long addr) +{ + struct spi_slave *spi; + char *ptr = (char *)addr; + int value, reg; + int ret; + int bus, cs, max_hz, spi_mode; + + debug("configure switch with file on addr: 0x%lx\n", addr); + + bus = 0; + cs = 0; + max_hz = 1000000; + spi_mode = 0; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + printf("Failed to set up slave\n"); + return -EINVAL; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("Failed to claim SPI bus: %d\n", ret); + goto err_claim_bus; + } + + ret = enbw_cmc_switch_read_ident(spi); + if (ret) + goto err_claim_bus; + + ptr = (char *)addr; + while (ptr != NULL) { + ptr = enbw_cmc_getvalue(ptr, ®); + if (ptr != NULL) { + ptr = enbw_cmc_getvalue(ptr, &value); + if ((ptr != NULL) && (value >= 0)) + if (enbw_cmc_switch_write(spi, reg, value)) + goto err_read; + } + } + return 0; + +err_read: + spi_release_bus(spi); +err_claim_bus: + spi_free_slave(spi); + return -EINVAL; +} + +static int do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + unsigned long addr; + + if (argc < 2) + return cmd_usage(cmdtp); + + addr = simple_strtoul(argv[1], NULL, 16); + enbw_cmc_config_switch(addr); + + return 0; +} + +U_BOOT_CMD(switch, 3, 1, do_switch, + "switch addr", + "[addr]" +); + /* * Initializes on-board ethernet controllers. */ int board_eth_init(bd_t *bis) { -#ifdef CONFIG_DRIVER_TI_EMAC + const char *s; + size_t len; + davinci_emac_mii_mode_sel(0); -#endif /* CONFIG_DRIVER_TI_EMAC */ + + /* send a config file to the switch */ + s = hwconfig_subarg("switch", "config", &len); + if (len) { + unsigned long addr = simple_strtoul(s, NULL, 16); + + enbw_cmc_config_switch(addr); + } if (!davinci_emac_initialize()) { printf("Error: Ethernet init failed!\n"); @@ -546,6 +807,29 @@ ulong bootcount_load(void) } #endif +ulong post_word_load(void) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; + + return in_be32(®->scratch2); +} + +void post_word_store(ulong value) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_POST_WORD_ADDR; + + /* + * write RTC kick register to enable write + * for RTC Scratch registers. Cratch0 and 1 are + * used for bootcount values. + */ + writel(RTC_KICK0R_WE, ®->kick0r); + writel(RTC_KICK1R_WE, ®->kick1r); + out_be32(®->scratch2, value); +} + void board_gpio_init(void) { struct davinci_gpio *gpio = davinci_gpio_bank01; @@ -558,6 +842,19 @@ void board_gpio_init(void) clrbits_le32(&gpio->out_data, 0x8000407e); /* set LED 1 - 5 to state on */ setbits_le32(&gpio->out_data, 0x8000001e); + + /* + * set some gpio pins to low, this is needed early, + * so we have no gpio Interface here + * gpios: + * 8[8] Mode PV select low + * 8[9] Debug Rx Enable low + * 8[10] Mode Select PV low + * 8[11] Counter Interface RS485 Rx-Enable low + */ + gpio = davinci_gpio_bank8; + clrbits_le32(&gpio->dir, 0x00000f00); + clrbits_le32(&gpio->out_data, 0x0f00); } int board_late_init(void) diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile index f3b13bccaf..ab18944f49 100644 --- a/board/esg/ima3-mx53/Makefile +++ b/board/esg/ima3-mx53/Makefile @@ -25,7 +25,7 @@ LIB = $(obj)lib$(BOARD).o COBJS := ima3-mx53.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) diff --git a/doc/README.evb64260 b/board/evb64260/README index 74211dea43..74211dea43 100644 --- a/doc/README.evb64260 +++ b/board/evb64260/README diff --git a/doc/README.EVB-64260-750CX b/board/evb64260/README.EVB-64260-750CX index 5ea38eaea3..5ea38eaea3 100644 --- a/doc/README.EVB-64260-750CX +++ b/board/evb64260/README.EVB-64260-750CX diff --git a/doc/README.fads b/board/fads/README index bae9652f01..bae9652f01 100644 --- a/doc/README.fads +++ b/board/fads/README diff --git a/board/spear/spear600/config.mk b/board/freescale/bsc9131rdb/Makefile index 5848ef89f8..6f4cb268f1 100644 --- a/board/spear/spear600/config.mk +++ b/board/freescale/bsc9131rdb/Makefile @@ -1,6 +1,5 @@ # -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# Copyright 2011-2012 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this # project. @@ -12,7 +11,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -21,19 +20,34 @@ # MA 02111-1307 USA # -######################################################################### +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +#COBJS-y += bsc9131rdb_mux.o -CONFIG_SYS_TEXT_BASE = 0x00700000 +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -ALL-y += $(obj)u-boot.img +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif +clean: + rm -f $(OBJS) $(SOBJS) -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README new file mode 100644 index 0000000000..065faa378d --- /dev/null +++ b/board/freescale/bsc9131rdb/README @@ -0,0 +1,137 @@ +Overview +-------- +- BSC9131 is integrated device that targets Femto base station market. + It combines Power Architecture e500v2 and DSP StarCore SC3850 core + technologies with MAPLE-B2F baseband acceleration processing elements. +- It's MAPLE disabled personality is called 9231. + +The BSC9131 SoC includes the following function and features: +. Power Architecture subsystem including a e500 processor with 256-Kbyte shared + L2 cache +. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache +. The Multi Accelerator Platform Engine for Femto BaseStation Baseband + Processing (MAPLE-B2F) +. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, + Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, + and CRC algorithms +. Consists of accelerators for Convolution, Filtering, Turbo Encoding, + Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion + operations +. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with + ECC, up to 400-MHz clock/800 MHz data rate +. Dedicated security engine featuring trusted boot +. DMA controller +. OCNDMA with four bidirectional channels +. Interfaces +. Two triple-speed Gigabit Ethernet controllers featuring network acceleration + including IEEE 1588. v2 hardware support and virtualization (eTSEC) +. eTSEC 1 supports RGMII/RMII +. eTSEC 2 supports RGMII +. High-speed USB 2.0 host and device controller with ULPI interface +. Enhanced secure digital (SD/MMC) host controller (eSDHC) +. Antenna interface controller (AIC), supporting three industry standard + JESD207/three custom ADI RF interfaces (two dual port and one single port) + and three MAXIM's MaxPHY serial interfaces +. ADI lanes support both full duplex FDD support and half duplex TDD support +. Universal Subscriber Identity Module (USIM) interface that facilitates + communication to SIM cards or Eurochip pre-paid phone cards +. TDM with one TDM port +. Two DUART, four eSPI, and two I2C controllers +. Integrated Flash memory controller (IFC) +. TDM with 256 channels +. GPIO +. Sixteen 32-bit timers + +The e500 core subsystem within the Power Architecture consists of the following: +. 32-Kbyte L1 instruction cache +. 32-Kbyte L1 data cache +. 256-Kbyte L2 cache/L2 memory/L2 stash +. programmable interrupt controller (PIC) +. Debug support +. Timers + +The SC3850 core subsystem consists of the following: +. 32 Kbyte 8-way level 1 instruction cache (L1 ICache) +. 32 Kbyte 8-way level 1 data cache (L1 DCache) +. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory) +. Memory management unit (MMU) +. Enhanced programmable interrupt controller (EPIC) +. Debug and profiling unit (DPU) +. Two 32-bit timers + +BSC9131RDB board Overview +------------------------- + 1Gbyte DDR3 (on board DDR) + 128Mbyte 2K page size NAND Flash + 256 Kbit M24256 I2C EEPROM + 128 Mbit SPI Flash memory + USB-ULPI + eTSEC1: Connected to RGMII PHY + eTSEC2: Connected to RGMII PHY + DUART interface: supports one UARTs up to 115200 bps for console display + USIM connector + +Frequency Combinations Supported +-------------------------------- +Core MHz/CCB MHz/DDR(MT/s) +1. 1000/500/800 +2. 800/400/667 + +Boot Methods Supported +----------------------- +1. NAND Flash +2. SPI Flash + +Default Boot Method +-------------------- +NAND boot + +Building U-boot +-------------- +To build the u-boot for BSC9131RDB: +1. NAND Flash + make BSC9131RDB_NAND +2. SPI Flash + make BSC9131RDB_SPIFLASH + +Memory map +----------- + 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable + 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M + 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K + 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K + 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K + 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M + 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M + +Flashing Images +--------------- +To place a new u-boot image in the NAND flash and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot-nand.bin + nand erase 0 100000 + nand write 1000000 0 100000 + reset + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 bsc9131rdb.dtb + bootm 1000000 2000000 c00000 diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c new file mode 100644 index 0000000000..2e0e55f47b --- /dev/null +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -0,0 +1,83 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <netdev.h> + + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | + MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); + setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0); + clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | + MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, + MPC85xx_PMUXCR_IFC_AD_GPIO | + MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); + + return 0; +} + +int checkboard(void) +{ + struct cpu_type *cpu; + + cpu = gd->cpu; + printf("Board: %sRDB\n", cpu->name); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c new file mode 100644 index 0000000000..c753edf904 --- /dev/null +++ b/board/freescale/bsc9131rdb/ddr.c @@ -0,0 +1,187 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_DRAM_SIZE 1024 + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {0, 0, NULL} +}; + +unsigned long get_sdram_size(void) +{ + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); +} + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) { + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + } + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_SYS_DDR_RAW_TIMING */ +/* Micron MT41J256M8HX-15E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c new file mode 100644 index 0000000000..201c147079 --- /dev/null +++ b/board/freescale/bsc9131rdb/law.c @@ -0,0 +1,31 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c new file mode 100644 index 0000000000..5b68f4af3c --- /dev/null +++ b/board/freescale/bsc9131rdb/tlb.c @@ -0,0 +1,67 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR (PA) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1) + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c index 8a55fde6f1..6ddf816201 100644 --- a/board/freescale/common/fman.c +++ b/board/freescale/common/fman.c @@ -37,31 +37,33 @@ * ... update that Ethernet node's phy-handle property to point to the * ethernet-phy node. This is how we link an Ethernet node to its PHY, so each * PHY in a virtual MDIO node must have an alias. + * + * Returns 0 on success, or a negative FDT error code on error. */ -void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, +int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, const char *alias) { - int offset, ph; + int offset; + unsigned int ph; const char *path; /* Get a path to the node that 'alias' points to */ path = fdt_get_alias(fdt, alias); - if (path) { - /* Get the offset of that node */ - int off = fdt_path_offset(fdt, path); - if (off > 0) - ph = fdt_create_phandle(fdt, off); - else - return; - } else { - return ; - } + if (!path) + return -FDT_ERR_BADPATH; + + /* Get the offset of that node */ + offset = fdt_path_offset(fdt, path); + if (offset < 0) + return offset; - /* failed to create a phandle */ - if (ph <= 0) - return ; + ph = fdt_create_phandle(fdt, offset); + if (!ph) + return -FDT_ERR_BADPHANDLE; offset = fdt_node_offset_by_compat_reg(fdt, compat, addr); - if (offset > 0) - fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); + if (offset < 0) + return offset; + + return fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph)); } diff --git a/board/freescale/common/fman.h b/board/freescale/common/fman.h index 19ef7c4fbc..d39ef080c1 100644 --- a/board/freescale/common/fman.h +++ b/board/freescale/common/fman.h @@ -20,7 +20,7 @@ #ifndef __FMAN_BOARD_HELPER__ #define __FMAN_BOARD_HELPER__ -void fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, +int fdt_set_phy_handle(void *fdt, char *compat, phys_addr_t addr, const char *alias); #endif diff --git a/doc/README.m52277evb b/board/freescale/m52277evb/README index b6e955bcad..b6e955bcad 100644 --- a/doc/README.m52277evb +++ b/board/freescale/m52277evb/README diff --git a/doc/README.m5253evbe b/board/freescale/m5253evbe/README index f51609f3e0..f51609f3e0 100644 --- a/doc/README.m5253evbe +++ b/board/freescale/m5253evbe/README diff --git a/doc/README.m53017evb b/board/freescale/m53017evb/README index 64a3d42f0c..64a3d42f0c 100644 --- a/doc/README.m53017evb +++ b/board/freescale/m53017evb/README diff --git a/doc/README.m5373evb b/board/freescale/m5373evb/README index 419d4d6d1e..419d4d6d1e 100644 --- a/doc/README.m5373evb +++ b/board/freescale/m5373evb/README diff --git a/doc/README.m54455evb b/board/freescale/m54455evb/README index 2bc6ce4bf3..2bc6ce4bf3 100644 --- a/doc/README.m54455evb +++ b/board/freescale/m54455evb/README diff --git a/doc/README.m5475evb b/board/freescale/m547xevb/README index d3aec20e4f..d3aec20e4f 100644 --- a/doc/README.m5475evb +++ b/board/freescale/m547xevb/README diff --git a/doc/README.mpc7448hpc2 b/board/freescale/mpc7448hpc2/README index cbb043e1d0..cbb043e1d0 100644 --- a/doc/README.mpc7448hpc2 +++ b/board/freescale/mpc7448hpc2/README diff --git a/doc/README.mpc8313erdb b/board/freescale/mpc8313erdb/README index be7ef32b45..be7ef32b45 100644 --- a/doc/README.mpc8313erdb +++ b/board/freescale/mpc8313erdb/README diff --git a/doc/README.mpc8315erdb b/board/freescale/mpc8315erdb/README index b32132d053..b32132d053 100644 --- a/doc/README.mpc8315erdb +++ b/board/freescale/mpc8315erdb/README diff --git a/doc/README.mpc8323erdb b/board/freescale/mpc8323erdb/README index 6f89829373..6f89829373 100644 --- a/doc/README.mpc8323erdb +++ b/board/freescale/mpc8323erdb/README diff --git a/doc/README.mpc832xemds b/board/freescale/mpc832xemds/README index 4142aa9c8d..4142aa9c8d 100644 --- a/doc/README.mpc832xemds +++ b/board/freescale/mpc832xemds/README diff --git a/doc/README.mpc8349itx b/board/freescale/mpc8349itx/README index 48bbd50356..48bbd50356 100644 --- a/doc/README.mpc8349itx +++ b/board/freescale/mpc8349itx/README diff --git a/doc/README.mpc8360emds b/board/freescale/mpc8360emds/README index 6afa753969..6afa753969 100644 --- a/doc/README.mpc8360emds +++ b/board/freescale/mpc8360emds/README diff --git a/doc/README.mpc837xemds b/board/freescale/mpc837xemds/README index faf21c9ffb..faf21c9ffb 100644 --- a/doc/README.mpc837xemds +++ b/board/freescale/mpc837xemds/README diff --git a/doc/README.mpc837xerdb b/board/freescale/mpc837xerdb/README index cfb6efa27e..cfb6efa27e 100644 --- a/doc/README.mpc837xerdb +++ b/board/freescale/mpc837xerdb/README diff --git a/doc/README.mpc8536ds b/board/freescale/mpc8536ds/README index 2a38bd6dda..2a38bd6dda 100644 --- a/doc/README.mpc8536ds +++ b/board/freescale/mpc8536ds/README diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 6d0bfde232..7898708853 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -290,5 +290,10 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_fdt_fixup(blob); #endif + +#ifdef CONFIG_HAS_FSL_MPH_USB + fdt_fixup_dr_usb(blob, bd); +#endif + } #endif diff --git a/doc/README.mpc8544ds b/board/freescale/mpc8544ds/README index b49c3c07c4..b49c3c07c4 100644 --- a/doc/README.mpc8544ds +++ b/board/freescale/mpc8544ds/README diff --git a/doc/README.mpc8569mds b/board/freescale/mpc8569mds/README index 3d12a964cd..3d12a964cd 100644 --- a/doc/README.mpc8569mds +++ b/board/freescale/mpc8569mds/README diff --git a/doc/README.mpc8572ds b/board/freescale/mpc8572ds/README index 57fd2ad616..57fd2ad616 100644 --- a/doc/README.mpc8572ds +++ b/board/freescale/mpc8572ds/README diff --git a/doc/README.mpc8610hpcd b/board/freescale/mpc8610hpcd/README index 31a9af3fee..31a9af3fee 100644 --- a/doc/README.mpc8610hpcd +++ b/board/freescale/mpc8610hpcd/README diff --git a/doc/README.mpc8641hpcn b/board/freescale/mpc8641hpcn/README index d8fe0a4a13..d8fe0a4a13 100644 --- a/doc/README.mpc8641hpcn +++ b/board/freescale/mpc8641hpcn/README diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 6587c454fe..40d8cf6097 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -159,8 +159,25 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, MX28_PAD_SSP2_SS0__SSP2_D3 | (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, }; +#define HW_DRAM_CTL29 (0x74 >> 2) +#define CS_MAP 0xf +#define COLUMN_SIZE 0x2 +#define ADDR_PINS 0x1 +#define APREBIT 0xa + +#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ + ADDR_PINS << 8 | APREBIT) + +void mx28_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; +} + void board_init_ll(void) { mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); diff --git a/doc/README.mx35pdk b/board/freescale/mx35pdk/README index 3d69ed5839..3d69ed5839 100644 --- a/doc/README.mx35pdk +++ b/board/freescale/mx35pdk/README diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile index 470588eb66..224eaa3c73 100644 --- a/board/freescale/mx51evk/Makefile +++ b/board/freescale/mx51evk/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx51evk.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53ard/Makefile b/board/freescale/mx53ard/Makefile index eac4b2a903..335af11790 100644 --- a/board/freescale/mx53ard/Makefile +++ b/board/freescale/mx53ard/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53ard.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53evk/Makefile b/board/freescale/mx53evk/Makefile index b7f92b3d87..dcc83e2d51 100644 --- a/board/freescale/mx53evk/Makefile +++ b/board/freescale/mx53evk/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53evk.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile index a6ea9396fb..8bc69a92c1 100644 --- a/board/freescale/mx53loco/Makefile +++ b/board/freescale/mx53loco/Makefile @@ -24,12 +24,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53loco.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d8e027ce66..cbdcfadf27 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -75,6 +75,9 @@ u32 get_board_rev(void) int rev = readl(&fuse->gp[6]); + if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) + rev = 0; + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; } @@ -495,11 +498,6 @@ int print_cpuinfo(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { - setup_iomux_i2c(); - if (!power_init()) - clock_1GHz(); - print_cpuinfo(); - setenv("stdout", "serial"); return 0; @@ -511,6 +509,10 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; mxc_set_sata_internal_clock(); + setup_iomux_i2c(); + if (!power_init()) + clock_1GHz(); + print_cpuinfo(); lcd_enable(); diff --git a/board/freescale/mx53smd/Makefile b/board/freescale/mx53smd/Makefile index ed8e473649..8a404c8ab7 100644 --- a/board/freescale/mx53smd/Makefile +++ b/board/freescale/mx53smd/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx53smd.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx6qarm2/Makefile b/board/freescale/mx6qarm2/Makefile index 79bc315dd3..6ce449552a 100644 --- a/board/freescale/mx6qarm2/Makefile +++ b/board/freescale/mx6qarm2/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx6qarm2.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index ceecbf925d..bf941a3198 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabrelite/Makefile b/board/freescale/mx6qsabrelite/Makefile index 53c26e7ba6..cf344e4323 100644 --- a/board/freescale/mx6qsabrelite/Makefile +++ b/board/freescale/mx6qsabrelite/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := mx6qsabrelite.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/doc/README.mx6qsabrelite b/board/freescale/mx6qsabrelite/README index 6f2f5343de..6f2f5343de 100644 --- a/doc/README.mx6qsabrelite +++ b/board/freescale/mx6qsabrelite/README diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index c389427191..62498abca3 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 29cbfed120..0eae96d3a3 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -55,6 +55,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -72,6 +77,11 @@ iomux_v3_cfg_t uart2_pads[] = { MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), }; +iomux_v3_cfg_t i2c3_pads[] = { + MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL), + MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL), +}; + iomux_v3_cfg_t usdhc3_pads[] = { MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -336,6 +346,7 @@ int board_init(void) #ifdef CONFIG_MXC_SPI setup_spi(); #endif + imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads)); #ifdef CONFIG_CMD_SATA setup_sata(); diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README new file mode 100644 index 0000000000..7f18aaa1b2 --- /dev/null +++ b/board/freescale/p1010rdb/README @@ -0,0 +1,208 @@ +Overview +========= +The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), +that addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB board features are as follows: +Memory subsystem: + - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32 Mbyte NOR flash single-chip memory + - 32 Mbyte NAND flash memory + - 256 Kbit M24256 I2C EEPROM + - 16 Mbyte SPI memory + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - PCIe: + - Lane0: x1 mini-PCIe slot + - Lane1: x1 PCIe standard slot + - SATA: + - 1 internal SATA connector to 2.5” 160G SATA2 HDD + - 1 eSATA connector to rear panel + - 10/100/1000 BaseT Ethernet ports: + - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO + - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - USB 2.0 port: + - x1 USB2.0 port via an external ULPI PHY to micro-AB connector + - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector + - FlexCAN ports: + - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) + interface; + - DUART interface: + - DUART interface: supports two UARTs up to 115200 bps for + console display + - RJ45 connectors are used for these 2 UART ports. + - TDM + - 2 FXS ports connected via an external SLIC to the TDM interface. + SLIC is controllled via SPI. + - 1 FXO port connected via a relay to FXS for switchover to POTS +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging +IEEE Std. 1588 signals for test and measurement +Real-time clock on I2C bus +POR + - support critical POR setting changed via switch on board +PCB + - 6-layer routing (4-layer signals, 2-layer power and ground) + + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +Settings of DIP-switch +====================== + SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash + SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash + SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +Note: 1 stands for 'on', 0 stands for 'off' + + +Setting of hwconfig +=================== +If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or +"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: +setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" +By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection +is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM +instead of to CAN/UART1. + + +Build and burn u-boot to NOR flash +================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NOR + +2. Burn u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff80000 +$filesize + => erase eff80000 +$filesize + => cp.b $loadaddr eff80000 $filesize + +3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. + + +Alternate NOR bank +================== +1. Burn u-boot.bin into alternate NOR bank + => tftp $loadaddr $uboot + => protect off eef80000 +$filesize + => erase eef80000 +$filesize + => cp.b $loadaddr eef80000 $filesize + +2. Switch to alternate NOR bank + => mw.b ffb00009 1 + => reset + or set SW1[8]= ON + +SW1[8]= OFF: Upper bank used for booting start +SW1[8]= ON: Lower bank used for booting start +CPLD NOR bank selection register address 0xFFB00009 Bit[0]: +0 - boot from upper 4 sectors +1 - boot from lower 4 sectors + + +Build and burn u-boot to NAND flash +=================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NAND + +2. Burn u-boot-nand.bin into NAND flash + => tftp $loadaddr $uboot-nand + => nand erase 0 $filesize + => nand write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. + + +Build and burn u-boot to SPI flash +================================== +1. Build u-boot-spi.bin image + make P1010RDB_SPIFLASH_config; make + Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb + Download u-boot.bin to linux and you can find some config files + under /usr/share such as config_xx.dat. Do below command: + boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ + u-boot-spi.bin + to generate u-boot-spi.bin. + +2. Burn u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. + + +CPLD POR setting registers +========================== +1. Set POR switch selection register (addr 0xFFB00011) to 0. +2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with + proper values. + If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 + switch command by I2C. +3. Send reset command. + After reset, the new POR setting will be implemented. + +Two examples are given in below: +Switch from NOR to NAND boot with default frequency: + => i2c dev 0 + => i2c mw 18 1 f9 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00017 1 + => reset +Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): + => i2c dev 0 + => i2c mw 18 1 f1 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00014 2 + => mw.b ffb00015 5 + => mw.b ffb00016 3 + => mw.b ffb00017 f + => reset + + +Boot Linux from network using TFTP on P1010RDB +============================================== +Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +Please contact your local field applications engineer or sales representative +to obtain related documents, such as P1010-RDB User Guide for details. diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index 36c8545059..10c5a42d1e 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -101,7 +101,7 @@ unsigned long get_sdram_size(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + if (cpu->soc_ver == SVR_P1014) ddr_size = (CONFIG_SYS_DRAM_SIZE / 2); else ddr_size = CONFIG_SYS_DRAM_SIZE; @@ -146,7 +146,7 @@ phys_size_t fixed_sdram(void) cpu = gd->cpu; /* P1014 and it's derivatives support max 16bit DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + if (cpu->soc_ver == SVR_P1014) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_16_BE; ddr_cfg_regs.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS >> 1; ddr_cfg_regs.ddr_sdram_cfg &= ~0x00180000; @@ -238,7 +238,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, cpu = gd->cpu; /* P1014 and it's derivatives support max 16it DDR width */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) + if (cpu->soc_ver == SVR_P1014) popts->data_bus_width = DDR_DATA_BUS_WIDTH_16; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 79a6ead7dd..dfeb86f63e 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -190,7 +190,7 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 /* P1014 and it's derivatives do not support eTSEC3 */ - if (cpu->soc_ver != SVR_P1014 && cpu->soc_ver != SVR_P1014_E) { + if (cpu->soc_ver != SVR_P1014) { SET_STD_TSEC_INFO(tsec_info[num], 3); num++; } @@ -252,6 +252,31 @@ void fdt_del_tdm(void *blob) } } +void fdt_del_sdhc(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,esdhc")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + +void fdt_disable_uart1(void *blob) +{ + int nodeoff; + + nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", + CONFIG_SYS_NS16550_COM2); + + if (nodeoff > 0) { + fdt_status_disabled(blob, nodeoff); + } else { + printf("WARNING unable to set status for fsl,ns16550 " + "uart1: %s\n", fdt_strerror(nodeoff)); + } +} + void ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; @@ -276,24 +301,31 @@ void ft_board_setup(void *blob, bd_t *bd) #endif /* P1014 and it's derivatives don't support CAN and eTSEC3 */ - if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { + if (cpu->soc_ver == SVR_P1014) { fdt_del_flexcan(blob); fdt_del_node_and_alias(blob, "ethernet2"); } #ifndef CONFIG_SDCARD + /* disable sdhc due to sdhc bug */ + fdt_del_sdhc(blob); if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { - printf("fdt CAN"); fdt_del_tdm(blob); fdt_del_spi_slic(blob); - } -#ifndef CONFIG_SPIFLASH - else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - printf("fdt TDM"); + } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { fdt_del_flexcan(blob); fdt_del_spi_flash(blob); + fdt_disable_uart1(blob); + } else { + /* + * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" + * explicitly, defaultly spi_cs_sel to spi-flash instead of + * to tdm/slic. + */ + fdt_del_tdm(blob); + fdt_del_flexcan(blob); + fdt_disable_uart1(blob); } #endif -#endif } #endif @@ -309,10 +341,7 @@ int misc_init_r(void) MPC85xx_PMUXCR_CAN2_TDM | MPC85xx_PMUXCR_CAN2_UART); out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); - } -#ifndef CONFIG_SPIFLASH - if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { - printf("TDM"); + } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | MPC85xx_PMUXCR_CAN1_UART); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | @@ -321,8 +350,11 @@ int misc_init_r(void) setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); - } -#endif + } else { + /* defaultly spi_cs_sel to flash */ + out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); + } + return 0; } #endif diff --git a/doc/README.p1022ds b/board/freescale/p1022ds/README index 04d9197074..04d9197074 100644 --- a/doc/README.p1022ds +++ b/board/freescale/p1022ds/README diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index aca30f3680..56dfcce410 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * @@ -337,6 +337,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/doc/README.p1023rds b/board/freescale/p1023rds/README index 685f5daa99..685f5daa99 100644 --- a/doc/README.p1023rds +++ b/board/freescale/p1023rds/README diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 082976a924..eb11f3fe12 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Authors: Roy Zang <tie-fei.zang@freescale.com> * Chunhe Lan <b25806@freescale.com> @@ -202,6 +202,9 @@ void ft_board_setup(void *blob, bd_t *bd) do_fixup_by_path_string(blob, "nor_flash", "status", "disabled"); do_fixup_by_path_string(blob, "nand_flash", "status", "okay"); #endif +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif fdt_fixup_fman_ethernet(blob); } diff --git a/doc/README.p2020rdb b/board/freescale/p1_p2_rdb/README index cb664a5bd7..cb664a5bd7 100644 --- a/doc/README.p2020rdb +++ b/board/freescale/p1_p2_rdb/README diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 71c60888ac..916439c17f 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -204,8 +204,7 @@ phys_size_t fixed_sdram (void) cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ - if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || - cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } else { ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; @@ -232,8 +231,7 @@ phys_size_t fixed_sdram (void) strmhz(buf, ddr_freq)); /* P1020 and it's derivatives support max 32bit DDR width */ - if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || - cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; } diff --git a/doc/README.p1_p2_rdb_pc b/board/freescale/p1_p2_rdb_pc/README index 44377317dd..44377317dd 100644 --- a/doc/README.p1_p2_rdb_pc +++ b/board/freescale/p1_p2_rdb_pc/README diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c index 8cf7beea72..ba4ef87255 100644 --- a/board/freescale/p2020come/p2020come.c +++ b/board/freescale/p2020come/p2020come.c @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -282,6 +282,8 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB fdt_fixup_dr_usb(blob, bd); +#endif } #endif diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index e8d31a4acf..3188f59e4b 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -257,6 +257,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + FT_FSL_PCI_SETUP; #ifdef CONFIG_FSL_SGMII_RISER diff --git a/doc/README.p2041rdb b/board/freescale/p2041rdb/README index 292d0d39cf..292d0d39cf 100644 --- a/doc/README.p2041rdb +++ b/board/freescale/p2041rdb/README diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 976c8d290b..d2732f5505 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -211,6 +211,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif diff --git a/doc/README.p3060qds b/board/freescale/p3060qds/README index ec627980c1..ec627980c1 100644 --- a/doc/README.p3060qds +++ b/board/freescale/p3060qds/README diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c index c7cca2a0cc..43e7f2888a 100644 --- a/board/freescale/p3060qds/p3060qds.c +++ b/board/freescale/p3060qds/p3060qds.c @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -323,6 +323,10 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) + fdt_fixup_dr_usb(blob, bd); +#endif + #ifdef CONFIG_PCI pci_of_setup(blob, bd); #endif diff --git a/doc/README.IceCube b/board/icecube/README index 5252bc9767..5252bc9767 100644 --- a/doc/README.IceCube +++ b/board/icecube/README diff --git a/doc/README.Lite5200B_low_power b/board/icecube/README.Lite5200B_low_power index 5b04fbba72..5b04fbba72 100644 --- a/doc/README.Lite5200B_low_power +++ b/board/icecube/README.Lite5200B_low_power diff --git a/doc/README.INCA-IP b/board/incaip/README index 132915292e..132915292e 100644 --- a/doc/README.INCA-IP +++ b/board/incaip/README diff --git a/doc/README.IPHASE4539 b/board/iphase4539/README index c5146d9b18..c5146d9b18 100644 --- a/doc/README.IPHASE4539 +++ b/board/iphase4539/README diff --git a/board/spear/spear300/config.mk b/board/karo/tk71/Makefile index 5848ef89f8..934e3911d1 100644 --- a/board/spear/spear300/config.mk +++ b/board/karo/tk71/Makefile @@ -1,6 +1,7 @@ # -# (C) Copyright 2009 -# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# Copyright (C) 2012 Marek Vasut <marex@denx.de> +# on behalf of DENX Software Engineering GmbH +# # # See file CREDITS for list of people who contributed to this # project. @@ -12,28 +13,33 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA # -######################################################################### +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tk71.o -CONFIG_SYS_TEXT_BASE = 0x00700000 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -ALL-y += $(obj)u-boot.img +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg new file mode 100644 index 0000000000..0166826e72 --- /dev/null +++ b/board/karo/tk71/kwbimage.cfg @@ -0,0 +1,174 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# adopted to TK71 by +# Nils Faerber <nils.faerber@kernelconcepts.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000034 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c new file mode 100644 index 0000000000..96410d77d6 --- /dev/null +++ b/board/karo/tk71/tk71.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2012 Marek Vasut <marex@denx.de> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TK71_OE_LOW (~0) +#define TK71_OE_HIGH (~0) +#define TK71_OE_VAL_LOW (0) +#define TK71_OE_VAL_HIGH (0) + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_NET + +#define MV88E1116_MAC_CTRL2_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +static void mv_phy_88e1118_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1118 Initialized on %s\n", name); +} + +/* Configure and enable Switch and PHY */ +void reset_phy(void) +{ + /* configure and initialize PHY */ + mv_phy_88e1118_init("egiga0"); + +} +#endif diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index f457aa30c6..aab706e6c9 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -131,6 +131,11 @@ struct bfticu_iomap { int ethernet_present(void); int ivm_read_eeprom(void); +int trigger_fpga_config(void); +int wait_for_fpga_config(void); +int fpga_reset(void); +int toggle_eeprom_spi_bus(void); + int set_km_env(void); int fdt_set_node_and_value(void *blob, char *nodename, diff --git a/doc/README.kmeter1 b/board/keymile/km83xx/README.kmeter1 index 7f4fc999f8..7f4fc999f8 100644 --- a/doc/README.kmeter1 +++ b/board/keymile/km83xx/README.kmeter1 diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index aa51255265..13d485aedb 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -31,6 +31,10 @@ LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o ../common/common.o ../common/ivm.o +ifdef CONFIG_KM_FPGA_CONFIG +COBJS += fpga_config.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c new file mode 100644 index 0000000000..66a3baf0f7 --- /dev/null +++ b/board/keymile/km_arm/fpga_config.c @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2012 + * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> + +/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ +#define KM_XLX_PROGRAM_B_PIN 39 + +#define BOCO_ADDR 0x10 + +#define ID_REG 0x00 +#define BOCO2_ID 0x5b + +static int check_boco2(void) +{ + int ret; + u8 id; + + ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1); + if (ret) { + printf("%s: error reading the BOCO id !!\n", __func__); + return ret; + } + + return (id == BOCO2_ID); +} + +static int boco_clear_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval &= ~flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +static int boco_set_bits(u8 reg, u8 flags) +{ + int ret; + u8 regval; + + /* give access to the EEPROM from FPGA */ + ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + regval |= flags; + ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); + if (ret) { + printf("%s: error writing the BOCO @%#x !!\n", + __func__, reg); + return ret; + } + + return 0; +} + +#define SPI_REG 0x06 +#define CFG_EEPROM 0x02 +#define FPGA_PROG 0x04 +#define FPGA_INIT_B 0x10 +#define FPGA_DONE 0x20 + +static int fpga_done(void) +{ + int ret = 0; + u8 regval; + + /* this is only supported with the boco2 design */ + if (!check_boco2()) + return 0; + + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1); + if (ret) { + printf("%s: error reading the BOCO @%#x !!\n", + __func__, SPI_REG); + return 0; + } + + return regval & FPGA_DONE ? 1 : 0; +} + +int skip; + +int trigger_fpga_config(void) +{ + int ret = 0; + + /* if the FPGA is already configured, we do not want to + * reconfigure it */ + skip = 0; + if (fpga_done()) { + printf("PCIe FPGA config: skipped\n"); + skip = 1; + return 0; + } + + if (check_boco2()) { + /* we have a BOCO2, this has to be triggered here */ + + /* make sure the FPGA_can access the EEPROM */ + ret = boco_clear_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + /* trigger the config start */ + ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + /* up signal for pulse end */ + ret = boco_set_bits(SPI_REG, FPGA_PROG); + if (ret) + return ret; + + /* finally, raise INIT_B to remove the config delay */ + ret = boco_set_bits(SPI_REG, FPGA_INIT_B); + if (ret) + return ret; + + } else { + /* we do it the old way, with the gpio pin */ + kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); + kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); + /* small delay for the pulse */ + udelay(10); + kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); + } + + return 0; +} + +int wait_for_fpga_config(void) +{ + int ret = 0; + u8 spictrl; + u32 timeout = 20000; + + if (skip) + return 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + printf("PCIe FPGA config:"); + do { + ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1); + if (ret) { + printf("%s: error reading the BOCO spictrl !!\n", + __func__); + return ret; + } + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + return -EFAULT; + } + udelay(10); + } while (!(spictrl & FPGA_DONE)); + + printf(" done\n"); + + return 0; +} + +#define PRST1 0x4 +#define PCIE_RST 0x10 +#define TRAFFIC_RST 0x04 + +int fpga_reset(void) +{ + int ret = 0; + u8 resets; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + /* if we have skipped, we only want to reset the PCIe part */ + resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; + + ret = boco_clear_bits(PRST1, resets); + if (ret) + return ret; + + /* small delay for the pulse */ + udelay(10); + + ret = boco_set_bits(PRST1, resets); + if (ret) + return ret; + + return 0; +} + +/* the FPGA was configured, we configure the BOCO2 so that the EEPROM + * is available from the Bobcat SPI bus */ +int toggle_eeprom_spi_bus(void) +{ + int ret = 0; + + if (!check_boco2()) { + /* we do not have BOCO2, this is not really used */ + return 0; + } + + ret = boco_set_bits(SPI_REG, CFG_EEPROM); + if (ret) + return ret; + + return 0; +} diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 9e9940c51f..2b2ca39376 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -33,6 +33,7 @@ #include <nand.h> #include <netdev.h> #include <miiphy.h> +#include <spi.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> @@ -113,7 +114,7 @@ u32 kwmpp_config[] = { 0 }; -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne */ @@ -133,10 +134,10 @@ int startup_allowed(void) } #endif -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) /* - * These two boards have always ethernet present. Its connected to the mv - * switch. + * All boards with PIGGY4 connected via a simple switch have ethernet always + * present. */ int ethernet_present(void) { @@ -201,7 +202,7 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } -#if defined(CONFIG_MGCOGE3UN) +#if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); if (wait_for_ne != NULL) { @@ -242,90 +243,93 @@ int misc_init_r(void) int board_early_init_f(void) { +#if defined(CONFIG_SOFT_I2C) u32 tmp; - kirkwood_mpp_conf(kwmpp_config); + /* set the 2 bitbang i2c pins as output gpios */ + tmp = readl(KW_GPIO0_BASE + 4); + writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4); +#endif + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ /* - * The FLASH_GPIO_PIN switches between using a + * arch number of board + */ + gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; + + /* address of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + /* + * The KM_FLASH_GPIO_PIN switches between using a * NAND or a SPI FLASH. Set this pin on start * to NAND mode. */ - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - tmp = readl(KW_GPIO0_BASE + 4); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4); + kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); + kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); #if defined(CONFIG_SOFT_I2C) - /* init the GPIO for I2C Bitbang driver */ + /* + * Reinit the GPIO for I2C Bitbang driver so that the now + * available gpio framework is consistent. The calls to + * direction output in are not necessary, they are already done in + * board_early_init_f + */ kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); - kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0); - kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0); #endif + #if defined(CONFIG_SYS_EEPROM_WREN) kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); #endif -#if defined(CONFIG_KM_RECONFIG_XLX) - /* trigger the reconfiguration of the xilinx fpga */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); + +#if defined(CONFIG_KM_FPGA_CONFIG) + trigger_fpga_config(); #endif + return 0; } -int board_init(void) +int board_late_init(void) { - /* address of boot parameters */ - gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; +#if defined(CONFIG_KMCOGE5UN) +/* I/O pin to erase flash RGPP09 = MPP43 */ +#define KM_FLASH_ERASE_ENABLE 43 + u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); + + /* if pin 1 do full erase */ + if (dip_switch != 0) { + /* start bootloader */ + puts("DIP: Enabled\n"); + setenv("actual_bank", "0"); + } +#endif +#if defined(CONFIG_KM_FPGA_CONFIG) + wait_for_fpga_config(); + fpga_reset(); + toggle_eeprom_spi_bus(); +#endif return 0; } -#if defined(CONFIG_CMD_SF) -int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int board_spi_claim_bus(struct spi_slave *slave) { - u32 tmp; - if (argc < 2) - return cmd_usage(cmdtp); - - if ((strcmp(argv[1], "off") == 0)) { - printf("SPI FLASH disabled, NAND enabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_NF_IO2; - kwmpp_config[1] = MPP1_NF_IO3; - kwmpp_config[2] = MPP2_NF_IO4; - kwmpp_config[3] = MPP3_NF_IO5; - - kirkwood_mpp_conf(kwmpp_config); - tmp = readl(KW_GPIO0_BASE); - writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE); - } else if ((strcmp(argv[1], "on") == 0)) { - printf("SPI FLASH enabled, NAND disabled\n"); - /* Multi-Purpose Pins Functionality configuration */ - kwmpp_config[0] = MPP0_SPI_SCn; - kwmpp_config[1] = MPP1_SPI_MOSI; - kwmpp_config[2] = MPP2_SPI_SCK; - kwmpp_config[3] = MPP3_SPI_MISO; - - kirkwood_mpp_conf(kwmpp_config); - tmp = readl(KW_GPIO0_BASE); - writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE); - } else { - return cmd_usage(cmdtp); - } + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); return 0; } -U_BOOT_CMD( - spitoggle, 2, 0, do_spi_toggle, - "En-/disable SPI FLASH access", - "<on|off> - Enable (on) or disable (off) SPI FLASH access\n" - ); -#endif +void board_spi_release_bus(struct spi_slave *slave) +{ + kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); +} int dram_init(void) { @@ -347,15 +351,15 @@ void dram_init_banksize(void) } } -#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2)) +#if (defined(CONFIG_KM_PIGGY4_88E6061)) -#define PHY_LED_SEL 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8<<4) -#define PHY_LED2_INT (0xe<<8) -#define PHY_SPEC_CTRL 0x1c +#define PHY_LED_SEL_REG 0x18 +#define PHY_LED0_LINK (0x5) +#define PHY_LED1_ACT (0x8<<4) +#define PHY_LED2_INT (0xe<<8) +#define PHY_SPEC_CTRL_REG 0x1c #define PHY_RGMII_CLK_STABLE (0x1<<10) -#define PHY_CLSA (0x1<<1) +#define PHY_CLSA (0x1<<1) /* Configure and enable MV88E3018 PHY */ void reset_phy(void) @@ -367,15 +371,15 @@ void reset_phy(void) return; /* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, ®) != 0) + if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®)) printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, + reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) printf("Error writing PHY spec ctrl reg\n"); /* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT) != 0) + if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, + PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) printf("Error writing PHY LED reg\n"); /* reset the phy */ @@ -410,7 +414,7 @@ const ulong patterns[] = { 0x00000000, 0xFF00FF00, 0x0F0F0F0F, 0xF0F0F0F0}; -const ulong NBR_OF_PATTERNS = sizeof(patterns)/sizeof(*patterns); +const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns); const ulong OFFS_PATTERN = 3; const ulong REPEAT_PATTERN = 1000; @@ -486,7 +490,11 @@ int get_scl(void) int post_hotkeys_pressed(void) { +#if defined(CONFIG_KM_COGE5UN) + return kw_gpio_get_value(KM_POST_EN_L); +#else return !kw_gpio_get_value(KM_POST_EN_L); +#endif } ulong post_word_load(void) diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg index 2faaf2b4c9..6df2ad7902 100644 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ b/board/keymile/km_arm/kwbimage-memphis.cfg @@ -149,7 +149,7 @@ DATA 0xFFD01424 0x0000F17F # DDR Controller Control High DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low # bit3-0 : 0000, required # bit7-4 : 0010, M_ODT assertion 2 cycles after read -# bit11-8 : 1001, M_ODT de-assertion 5 cycles after read +# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read # bit15-12: 0100, internal ODT assertion 4 cycles after read # bit19-16: 1000, internal ODT de-assertion 8 cycles after read # bit31-20: 0 , required diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg new file mode 100644 index 0000000000..bcce9073f6 --- /dev/null +++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg @@ -0,0 +1,294 @@ +# +# (C) Copyright 2010 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# (C) Copyright 2012 +# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# +# (C) Copyright 2012 +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] +# bit 7-4: 0, MPPSel9 GPIO[9] +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 UA1_TXD +# bit 27-24: 3, MPPSel14 UA1_RXD +# bit 31-28: 0, MPPSel15 GPIO[15] + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 12-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserve +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ???, Reserve +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ???,Reserve + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM +# bit 30-28: 3, required +# bit 31: 0,no additional STARTBURST delay + +DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xE, TRAS, 15 clk (45 ns) +# bit 7-4: 0x4, TRCD, 5 clk (15 ns) +# bit 11-8: 0x4, TRP, 5 clk (15 ns) +# bit 15-12: 0x4, TWR, 5 clk (15 ns) +# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x3, TRRD, 4 clk (10 ns) +# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) + +DATA 0xFFD0140C 0x0000003e # DDR Timing (High) +# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000001 # DDR Address Control +# bit 1-0: 1, Cs0width=x16 +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strength reduced +# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for f > 266 MHz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 0, ODT1 controlled by register +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM +# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg new file mode 100644 index 0000000000..3e1237bbe3 --- /dev/null +++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg @@ -0,0 +1,296 @@ +# +# (C) Copyright 2012 +# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com +# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com +# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# +# This configuration applies to COGE5 design (ARM-part) +# Two 8-Bit devices are connected on the 16-Bit bus on the same +# chip-select. The supported devices are +# MT47H256M8EB-3IT:C +# MT47H256M8EB-25EIT:C + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +DATA 0xFFD10000 0x01112222 # MPP Control 0 Register +# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) +# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) +# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) +# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) +# bit 19-16: 1, MPPSel4 NF_IO[6] +# bit 23-20: 1, MPPSel5 NF_IO[7] +# bit 27-24: 1, MPPSel6 SYSRST_O +# bit 31-28: 0, MPPSel7 GPO[7] + +DATA 0xFFD10004 0x03303300 # MPP Control 1 Register +# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged +# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged +# bit 12-8: 3, MPPSel10 UA0_TXD +# bit 15-12: 3, MPPSel11 UA0_RXD +# bit 19-16: 0, MPPSel12 not connected +# bit 23-20: 3, MPPSel13 GPIO[14] +# bit 27-24: 3, MPPSel14 GPIO[15] +# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) + +DATA 0xFFD10008 0x00001100 # MPP Control 2 Register +# bit 3-0: 0, MPPSel16 GPIO[16] +# bit 7-4: 0, MPPSel17 not connected +# bit 11-8: 1, MPPSel18 NF_IO[0] +# bit 15-12: 1, MPPSel19 NF_IO[1] +# bit 19-16: 0, MPPSel20 GPIO[20] +# bit 23-20: 0, MPPSel21 GPIO[21] +# bit 27-24: 0, MPPSel22 GPIO[22] +# bit 31-28: 0, MPPSel23 GPIO[23] + +# MPP Control 3-6 Register untouched (MPP24-49) + +DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register +# bit 2-0: 3, Reserved +# bit 5-3: 3, Reserved +# bit 6: 0, Reserved +# bit 7: 0, RGMII-pads voltage = 3.3V +# bit 10-8: 3, Reserved +# bit 13-11: 3, Reserved +# bit 14: 0, Reserved +# bit 15: 0, MPP RGMII-pads voltage = 3.3V +# bit 31-16 0x1B1B, Reserved + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +# bit 0-1: 2, Tag RAM RTC RAM0 +# bit 3-2: 1, Tag RAM WTC RAM0 +# bit 7-4: 6, Reserved +# bit 9-8: 2, Valid RAM RTC RAM +# bit 11-10: 1, Valid RAM WTC RAM +# bit 13-12: 2, Dirty RAM RTC RAM +# bit 15-14: 1, Dirty RAM WTC RAM +# bit 17-16: 2, Data RAM RTC RAM0 +# bit 19-18: 1, Data RAM WTC RAM0 +# bit 21-20: 2, Data RAM RTC RAM1 +# bit 23-22: 1, Data RAM WTC RAM1 +# bit 25-24: 2, Data RAM RTC RAM2 +# bit 27-26: 1, Data RAM WTC RAM2 +# bit 29-28: 2, Data RAM RTC RAM3 +# bit 31-30: 1, Data RAM WTC RAM4 + +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register +# bit 15-0: ?, Reserved +# bit 17-16: 2, ECC RAM RTC RAM0 +# bit 19-18: 1, ECC RAM WTC RAM0 +# bit 31-20: ?,Reserved + +DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register +# bit 23-0: 0x000200, Addr Config tuning +# bit 31-24: 0, Reserved + +# ??? Missing register # CPU RAM Management Control2 Register + +DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register +# bit 15-0: 0x1C00, Opmux Tuning +# bit 31-16: 0, Pc Dp Tuning + +DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register +# bit 1-0: 1, addr clk tune +# bit 3-2: 0, reserved +# bit 5-4: 0, dtcmp clk tune +# bit 7-6: 0, reserved +# bit 9-8: 0, macdrv clk tune +# bit 11-10: 0, opmuxgm2 clk tune +# bit 15-14: 0, rf clk tune +# bit 17-16: 0, rfbypass clk tune +# bit 19-18: 0, pc dp clk tune +# bit 23-20: 0, icache clk tune +# bit 27:24: 0, dcache clk tune +# bit 31:28: 0, regfile tunin + +# SDRAM initalization +DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register +# bit 13-0: 0x4E0, DDR2 clks refresh rate +# bit 14: 0, reserved +# bit 15: 0, reserved +# bit 16: 0, CPU to Dram Write buffer policy +# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic +# bit 19-18: 0, reserved +# bit 23-20: 0, reserved +# bit 24: 1, enable exit self refresh mode on DDR access +# bit 25: 1, required +# bit 29-26: 0, reserved +# bit 31-30: 1, reserved + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 3-0: 0, reserved +# bit 4: 0, 2T mode =addr/cmd in same cycle +# bit 5: 0, clk is driven during self refresh, we don't care for APX +# bit 6: 0, use recommended falling edge of clk for addr/cmd +# bit 7-11: 0, reserved +# bit 12-13: 1, reserved, required 1 +# bit 14: 0, input buffer always powered up +# bit 17-15: 0, reserved +# bit 18: 1, cpu lock transaction enabled +# bit 19: 0, reserved +# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 +# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM +# bit 30-28: 3, required +# bit 31: 0, no additional STARTBURST delay + +DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) +# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles +# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles +# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles +# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles +# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles +# bit 20: 0, extended TRAS msb +# bit 23-21: 0, reserved +# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles +# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles + +DATA 0xFFD0140C 0x0000003E # DDR Timing (High) +# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles +# bit 8-7: 0, TR2R +# bit 10-9: 0, TR2W +# bit 12-11: 0, TW2W +# bit 31-13: 0, reserved + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit 1-0: 0, Cs0width=x8 (2 devices) +# bit 3-2: 0, Cs0size=2Gb +# bit 5-4: 0, Cs1width=nonexistent +# bit 7-6: 0, Cs1size =nonexistent +# bit 9-8: 0, Cs2width=nonexistent +# bit 11-10: 0, Cs2size =nonexistent +# bit 13-12: 0, Cs3width=nonexistent +# bit 15-14: 0, Cs3size =nonexistent +# bit 16: 0, Cs0AddrSel +# bit 17: 0, Cs1AddrSel +# bit 18: 0, Cs2AddrSel +# bit 19: 0, Cs3AddrSel +# bit 31-20: 0, required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit 0: 0, OpenPage enabled +# bit 31-1: 0, required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit 3-0: 0, DDR cmd +# bit 31-4: 0, required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit 2-0: 2, Burst Length = 4 +# bit 3: 0, Burst Type +# bit 6-4: 5, CAS Latency = 5 +# bit 7: 0, Test mode +# bit 8: 0, DLL Reset +# bit 11-9: 3, Write recovery for auto-precharge must be 3 +# bit 12: 0, Active power down exit time, fast exit +# bit 14-13: 0, reserved +# bit 31-15: 0, reserved + +DATA 0xFFD01420 0x00000006 # DDR Extended Mode +# bit 0: 0, DDR DLL enabled +# bit 1: 1, DDR drive strenght reduced +# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] +# bit 5-3: 0, required +# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] +# bit 9-7: 0, required +# bit 10: 0, differential DQS enabled +# bit 11: 0, required +# bit 12: 0, DDR output buffer enabled +# bit 31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit 2-0: 7, required +# bit 3: 1, MBUS Burst Chop disabled +# bit 6-4: 7, required +# bit 7: 0, reserved +# bit 8: 1, add sample stage required for > 266Mhz +# bit 9: 0, no half clock cycle addition to dataout +# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit 11: 0, 1/4 clock cycle skew disabled for write mesh +# bit 15-12:0xf, required +# bit 31-16: 0, required + +DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low +# bit 3-0: 0, required +# bit 7-4: 2, M_ODT assertion 2 cycles after read start command +# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command +# (ODT turn off delay 2,5 clk cycles) +# bit 15-12: 4, internal ODT time based on bit 7-4 +# with the considered SDRAM internal delay +# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 +# with the considered SDRAM internal delay +# bit 31-20: 0, required + +DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High +# bit 3-0: 2, M_ODT assertion same as bit 11-8 +# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 +# bit 11-8: 4, internal ODT assertion 2 cycles after write start command +# with the considered SDRAM internal delay +# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command +# with the considered SDRAM internal delay + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +# bit 23-0: 0, reserved +# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] + +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit 0: 1, Window enabled +# bit 1: 0, Write Protect disabled +# bit 3-2: 0, CS0 hit selected +# bit 23-4:ones, required +# bit 31-24:0x1F, Size (i.e. 512MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 +# bit 7-4: 0, ODT0Rd, MODT[1] not asserted +# bit 11-8: 0, required +# big 15-11: 0, required +# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 +# bit 23-20: 0, ODT0Wr, MODT[1] not asserted +# bit 27-24: 0, required +# bit 31-28: 0, required + +DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) +# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above +# bit 3-2: 1, ODT1 never active +# bit 31-4: 0, required + +DATA 0xFFD0149C 0x0000E801 # CPU ODT Control +# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 +# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr +# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm +# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm +# bit 14: 1, STARTBURST ODT enabled +# bit 15: 1, Use ODT Block + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +# bit 0: 1, enable DDR init upon this register write +# bit 31-1: 0, reserved + +# End of Header extension +DATA 0x0 0x0 diff --git a/doc/README.korat b/board/korat/README index e059f788c4..e059f788c4 100644 --- a/doc/README.korat +++ b/board/korat/README diff --git a/doc/README.mergerbox b/board/matrix_vision/mergerbox/README index 1994b65be1..1994b65be1 100644 --- a/doc/README.mergerbox +++ b/board/matrix_vision/mergerbox/README diff --git a/doc/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p index a691137550..a691137550 100644 --- a/doc/README.mvbc_p +++ b/board/matrix_vision/mvbc_p/README.mvbc_p diff --git a/doc/README.mvblm7 b/board/matrix_vision/mvblm7/README.mvblm7 index a0686f7fa5..a0686f7fa5 100644 --- a/doc/README.mvblm7 +++ b/board/matrix_vision/mvblm7/README.mvblm7 diff --git a/doc/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr index 8e34cb7838..8e34cb7838 100644 --- a/doc/README.mvsmr +++ b/board/matrix_vision/mvsmr/README.mvsmr diff --git a/doc/README.MBX b/board/mbx8xx/README index c889fe9791..c889fe9791 100644 --- a/doc/README.MBX +++ b/board/mbx8xx/README diff --git a/doc/README.PIP405 b/board/mpl/pip405/README index 012db1c5f7..012db1c5f7 100644 --- a/doc/README.PIP405 +++ b/board/mpl/pip405/README diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 2e22133591..e65fc9e843 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -64,6 +64,12 @@ void __pin_mux_usb(void) void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb"))); +void __pin_mux_spi(void) +{ +} + +void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi"))); + /* * Routine: power_det_init * Description: turn off power detects @@ -94,7 +100,8 @@ int board_init(void) #ifdef CONFIG_SPI_UART_SWITCH gpio_config_uart(); #endif -#ifdef CONFIG_TEGRA2_SPI +#ifdef CONFIG_TEGRA_SPI + pin_mux_spi(); spi_init(); #endif /* boot param addr */ @@ -132,11 +139,18 @@ int board_init(void) } #ifdef CONFIG_BOARD_EARLY_INIT_F +static void __gpio_early_init(void) +{ +} + +void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); + int board_early_init_f(void) { board_init_uart_f(); /* Initialize periph GPIOs */ + gpio_early_init(); #ifdef CONFIG_SPI_UART_SWITCH gpio_early_init_uart(); #else diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index 09fb158f4e..dada4c4f9c 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -25,6 +25,7 @@ #define _BOARD_H_ void gpio_config_uart(void); +void gpio_early_init(void); void gpio_early_init_uart(void); /* diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c index 23aa0b9d19..307937a836 100644 --- a/board/nvidia/common/uart-spi-switch.c +++ b/board/nvidia/common/uart-spi-switch.c @@ -21,12 +21,11 @@ */ #include <common.h> -#include <ns16550.h> #include <asm/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart-spi-switch.h> #include <asm/arch/tegra2.h> -#include <asm/arch/tegra2_spi.h> +#include <asm/arch/tegra_spi.h> /* position of the UART/SPI select switch */ @@ -40,7 +39,6 @@ enum spi_uart_switch { /* Information about the spi/uart switch */ struct spi_uart { int gpio; /* GPIO to control switch */ - NS16550_t regs; /* Address of UART affected */ u32 port; /* Port number of UART affected */ }; @@ -52,7 +50,6 @@ static void get_config(struct spi_uart *config) { #if defined CONFIG_SPI_CORRUPTS_UART config->gpio = CONFIG_UART_DISABLE_GPIO; - config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART; config->port = CONFIG_SPI_CORRUPTS_UART_NR; #else config->gpio = -1; @@ -101,34 +98,24 @@ static void spi_uart_switch(struct spi_uart *config, if (switch_pos == SWITCH_BOTH || new_pos == switch_pos) return; - /* if the UART was selected, allow it to drain */ - if (switch_pos == SWITCH_UART) - NS16550_drain(config->regs, config->port); + /* pre-delay, allow SPI/UART to settle, FIFO to empty, etc. */ + udelay(CONFIG_SPI_CORRUPTS_UART_DLY); /* We need to dynamically change the pinmux, shared w/UART RXD/CTS */ pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ? PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD); /* - * On Seaboard, MOSI/MISO are shared w/UART. - * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. - * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. - */ + * On Seaboard, MOSI/MISO are shared w/UART. + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. + */ gpio_direction_output(config->gpio, new_pos == SWITCH_SPI); switch_pos = new_pos; - - /* if the SPI was selected, clear any junk bytes in the UART */ - if (switch_pos == SWITCH_UART) { - /* TODO: What if it is part-way through clocking in junk? */ - udelay(100); - NS16550_clear(config->regs, config->port); - } } -void pinmux_select_uart(NS16550_t regs) +void pinmux_select_uart(void) { - /* Also prevents calling spi_uart_switch() before relocation */ - if (regs == local.regs) spi_uart_switch(&local, SWITCH_UART); } diff --git a/board/nvidia/dts/tegra2-harmony.dts b/board/nvidia/dts/tegra2-harmony.dts new file mode 100644 index 0000000000..4f60a05f33 --- /dev/null +++ b/board/nvidia/dts/tegra2-harmony.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Harmony evaluation board"; + compatible = "nvidia,harmony", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/nvidia/dts/tegra2-ventana.dts b/board/nvidia/dts/tegra2-ventana.dts new file mode 100644 index 0000000000..900e871d74 --- /dev/null +++ b/board/nvidia/dts/tegra2-ventana.dts @@ -0,0 +1,57 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; + + aliases { + usb0 = "/usb@c5008000"; + }; + + memory { + reg = <0x00000000 0x40000000>; + }; + + clocks { + clk_32k: clk_32k { + clock-frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006300 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + status = "disabled"; + }; + + usb@c5000000 { + status = "disabled"; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/nvidia/dts/tegra2-whistler.dts b/board/nvidia/dts/tegra2-whistler.dts new file mode 100644 index 0000000000..b22d4073f6 --- /dev/null +++ b/board/nvidia/dts/tegra2-whistler.dts @@ -0,0 +1,67 @@ +/dts-v1/; + +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Tegra2 Whistler evaluation board"; + compatible = "nvidia,whistler", "nvidia,tegra20"; + + aliases { + i2c0 = "/i2c@7000d000"; + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + }; + + memory { + device_type = "memory"; + reg = < 0x00000000 0x20000000 >; + }; + + clocks { + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + clock-frequency = < 216000000 >; + }; + + i2c@7000c000 { + status = "disabled"; + }; + + i2c@7000c400 { + status = "disabled"; + }; + + i2c@7000c500 { + status = "disabled"; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + + pmic@3c { + compatible = "maxim,max8907b"; + reg = <0x3c>; + + clk_32k: clock { + compatible = "fixed-clock"; + /* + * leave out for now due to CPP: + * #clock-cells = <0>; + */ + clock-frequency = <32768>; + }; + }; + }; + + usb@c5004000 { + status = "disabled"; + }; +}; diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 8f8e7bf3fe..f27ad37b70 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -29,7 +29,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif @@ -41,7 +41,7 @@ void gpio_config_uart(void) { } -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 94efb1e83d..36039c4ed8 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -29,7 +29,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/mmc.h> #include <asm/gpio.h> -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC #include <mmc.h> #endif @@ -54,7 +54,7 @@ void gpio_config_uart(void) } #endif -#ifdef CONFIG_TEGRA2_MMC +#ifdef CONFIG_TEGRA_MMC /* * Routine: pin_mux_mmc * Description: setup the pin muxes/tristate values for the SDMMC(s) diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile new file mode 100644 index 0000000000..a910577f21 --- /dev/null +++ b/board/nvidia/whistler/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c new file mode 100644 index 0000000000..3ec24df2e7 --- /dev/null +++ b/board/nvidia/whistler/whistler.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/mmc.h> +#include <asm/gpio.h> +#ifdef CONFIG_TEGRA_MMC +#include <mmc.h> +#endif + +/* + * Routine: gpio_config_uart + * Description: Does nothing on Whistler - no UART-related GPIOs. + */ +void gpio_config_uart(void) +{ +} + +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT); + funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT); +} + +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + uchar val; + int ret; + + debug("board_mmc_init called\n"); + + /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x29; + ret = i2c_write(0x3c, 0x46, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); + val = 0x00; + ret = i2c_write(0x3c, 0x45, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); + val = 0x1f; + ret = i2c_write(0x3c, 0x44, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); + + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + + /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */ + tegra2_mmc_init(0, 8, -1, -1); + + /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */ + tegra2_mmc_init(1, 8, -1, -1); + + return 0; +} + +/* this is a weak define that we are overriding */ +void pin_mux_usb(void) +{ + uchar val; + int ret; + + /* + * This is a hack. This should be represented in DT using the + * vbus-gpio property. However, U-Boot's DT support doesn't + * support any GPIO controller other than the Tegra's yet. + */ + + /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ + ret = i2c_set_bus_num(0); + if (ret) + printf("i2c_set_bus_num failed: %d\n", ret); + val = 0x03; + ret = i2c_write(0x20, 2, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 2 failed: %d\n", ret); + val = 0xfc; + ret = i2c_write(0x20, 6, 1, &val, 1); + if (ret) + printf("i2c_write 0 0x20 6 failed: %d\n", ret); +} diff --git a/doc/README.phytec.pcm030 b/board/phytec/pcm030/README index 05faab68c8..05faab68c8 100644 --- a/doc/README.phytec.pcm030 +++ b/board/phytec/pcm030/README diff --git a/board/qemu-mips/README b/board/qemu-mips/README index 565241b587..9fd97e1249 100644 --- a/board/qemu-mips/README +++ b/board/qemu-mips/README @@ -13,3 +13,170 @@ Derived from au1x00 with a lot of things cut out. Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with recent qemu versions. When using emulated flash, launch with -pflash <filename> and erase mips_bios.bin. + + + +Notes for the Qemu MIPS port +---------------------------- + +I) Example usage: + +# ln -s u-boot.bin mips_bios.bin +start it: +qemu-system-mips -L . /dev/null -nographic + +or + +if you use a qemu version after commit 4224 + +create image: +# dd of=flash bs=1k count=4k if=/dev/zero +# dd of=flash bs=1k conv=notrunc if=u-boot.bin +start it: +# qemu-system-mips -M mips -pflash flash -monitor null -nographic + +2) Download kernel + initrd + +On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/ +you can downland + +#config to build the kernel +qemu_mips_defconfig +#patch to fix mips interrupt init on 2.6.24.y kernel +qemu_mips_kernel.patch +initrd.gz +vmlinux +vmlinux.bin +System.map + +4) Generate uImage + +# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage + +5) Copy uImage to Flash +# dd if=uImage bs=1k conv=notrunc seek=224 of=flash + +6) Generate Ide Disk + +# dd of=ide bs=1k cout=100k if=/dev/zero + +# sfdisk -C 261 -d ide +# partition table of ide +unit: sectors + + ide1 : start= 63, size= 32067, Id=83 + ide2 : start= 32130, size= 32130, Id=83 + ide3 : start= 64260, size= 4128705, Id=83 + ide4 : start= 0, size= 0, Id= 0 + +7) Copy to ide + +# dd if=uImage bs=512 conv=notrunc seek=63 of=ide + +8) Generate ext2 on part 2 on Copy uImage and initrd.gz + +# Attached as loop device ide offset = 32130 * 512 +# losetup -o 16450560 -f ide +# Format as ext2 ( arg2 : nb blocks) +# mke2fs /dev/loop0 16065 +# losetup -d /dev/loop0 +# Mount and copy uImage and initrd.gz to it +# mount -o loop,offset=16450560 -t ext2 ide /mnt +# mkdir /mnt/boot +# cp {initrd.gz,uImage} /mnt/boot/ +# Umount it +# umount /mnt + +9) Set Environment + +setenv rd_start 0x80800000 +setenv rd_size 2663940 +setenv kernel BFC38000 +setenv oad_addr 80500000 +setenv load_addr2 80F00000 +setenv kernel_flash BFC38000 +setenv load_addr_hello 80200000 +setenv bootargs 'root=/dev/ram0 init=/bin/sh' +setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz' +setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz' +setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2' +setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage' +setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage' +setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}' +setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}' +setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}' +setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}' +setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}' +setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin' +setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}' +setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}' +setenv bootcmd 'run boot_tftp_flash' + +10) Now you can boot from flash, ide, ide+ext2 and tfp + +# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + +II) How to debug U-Boot + +In order to debug U-Boot you need to start qemu with gdb server support (-s) +and waiting the connection to start the CPU (-S) + +# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide + +in an other console you start gdb + +1) Debugging of U-Boot Before Relocation + +Before relocation, the addresses in the ELF file can be used without any problems +by connecting to the gdb server localhost:1234 + +# mipsel-unknown-linux-gnu-gdb u-boot +GNU gdb 6.6 +Copyright (C) 2006 Free Software Foundation, Inc. +GDB is free software, covered by the GNU General Public License, and you are +welcome to change it and/or distribute copies of it under certain conditions. +Type "show copying" to see the conditions. +There is absolutely no warranty for GDB. Type "show warranty" for details. +This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"... +(gdb) target remote localhost:1234 +Remote debugging using localhost:1234 +_start () at start.S:64 +64 RVECENT(reset,0) /* U-boot entry point */ +Current language: auto; currently asm +(gdb) b board.c:289 +Breakpoint 1 at 0xbfc00cc8: file board.c, line 289. +(gdb) c +Continuing. + +Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290 +290 relocate_code (addr_sp, id, addr); +Current language: auto; currently c +(gdb) p/x addr +$1 = 0x87fa0000 + +2) Debugging of U-Boot After Relocation + +For debugging U-Boot after relocation we need to know the address to which +U-Boot relocates itself to 0x87fa0000 by default. +And replace the symbol table to this offset. + +(gdb) symbol-file +Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y +Error in re-setting breakpoint 1: +No symbol table is loaded. Use the "file" command. +No symbol file now. +(gdb) add-symbol-file u-boot 0x87fa0000 +add symbol table from file "u-boot" at + .text_addr = 0x87fa0000 +(y or n) y +Reading symbols from /private/u-boot-arm/u-boot...done. +Breakpoint 1 at 0x87fa0cc8: file board.c, line 289. +(gdb) c +Continuing. + +Program received signal SIGINT, Interrupt. +0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78 +78 while ((tmo - read_c0_count()) < 0x7fffffff) diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 65f2c2ea6a..1164d6bf3f 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -66,7 +66,7 @@ int board_early_init_f(void) MPP29_GPIO, /* USB Copy button */ 0 }; - kirkwood_mpp_conf(kwmpp_config); + kirkwood_mpp_conf(kwmpp_config, NULL); return 0; } diff --git a/doc/README.sh7757lcr b/board/renesas/sh7757lcr/README.sh7757lcr index 3e9c1c1a1e..3e9c1c1a1e 100644 --- a/doc/README.sh7757lcr +++ b/board/renesas/sh7757lcr/README.sh7757lcr diff --git a/doc/README.sh7785lcr b/board/renesas/sh7785lcr/README.sh7785lcr index 56455fc162..56455fc162 100644 --- a/doc/README.sh7785lcr +++ b/board/renesas/sh7785lcr/README.sh7785lcr diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 32786e228f..3b078da65d 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -26,81 +26,16 @@ #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> #include <asm/arch/sromc.h> DECLARE_GLOBAL_DATA_PTR; -struct exynos5_gpio_part1 *gpio1; #ifdef CONFIG_SMC911X -static void smc9115_pre_init(void) +static int smc9115_pre_init(void) { u32 smc_bw_conf, smc_bc_conf; - int i; - - /* - * SROM:CS1 and EBI - * - * GPY0[0] SROM_CSn[0] - * GPY0[1] SROM_CSn[1](2) - * GPY0[2] SROM_CSn[2] - * GPY0[3] SROM_CSn[3] - * GPY0[4] EBI_OEn(2) - * GPY0[5] EBI_EEn(2) - * - * GPY1[0] EBI_BEn[0](2) - * GPY1[1] EBI_BEn[1](2) - * GPY1[2] SROM_WAIT(2) - * GPY1[3] EBI_DATA_RDn(2) - */ - s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); - s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); - - for (i = 0; i < 4; i++) - s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); - - /* - * EBI: 8 Addrss Lines - * - * GPY3[0] EBI_ADDR[0](2) - * GPY3[1] EBI_ADDR[1](2) - * GPY3[2] EBI_ADDR[2](2) - * GPY3[3] EBI_ADDR[3](2) - * GPY3[4] EBI_ADDR[4](2) - * GPY3[5] EBI_ADDR[5](2) - * GPY3[6] EBI_ADDR[6](2) - * GPY3[7] EBI_ADDR[7](2) - * - * EBI: 16 Data Lines - * - * GPY5[0] EBI_DATA[0](2) - * GPY5[1] EBI_DATA[1](2) - * GPY5[2] EBI_DATA[2](2) - * GPY5[3] EBI_DATA[3](2) - * GPY5[4] EBI_DATA[4](2) - * GPY5[5] EBI_DATA[5](2) - * GPY5[6] EBI_DATA[6](2) - * GPY5[7] EBI_DATA[7](2) - * - * GPY6[0] EBI_DATA[8](2) - * GPY6[1] EBI_DATA[9](2) - * GPY6[2] EBI_DATA[10](2) - * GPY6[3] EBI_DATA[11](2) - * GPY6[4] EBI_DATA[12](2) - * GPY6[5] EBI_DATA[13](2) - * GPY6[6] EBI_DATA[14](2) - * GPY6[7] EBI_DATA[15](2) - */ - for (i = 0; i < 8; i++) { - s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); - - s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); - s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); - } + int err; /* Ethernet needs data bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK) @@ -112,14 +47,20 @@ static void smc9115_pre_init(void) | SROMC_BC_PMC(0x01); /* Select and configure the SROMC bank */ + err = exynos_pinmux_config(PERIPH_ID_SROMC, + CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT); + if (err) { + debug("SROMC not configured\n"); + return err; + } + s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + return 0; } #endif int board_init(void) { - gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); return 0; } @@ -168,7 +109,8 @@ void dram_init_banksize(void) int board_eth_init(bd_t *bis) { #ifdef CONFIG_SMC911X - smc9115_pre_init(); + if (smc9115_pre_init()) + return -1; return smc911x_initialize(0, CONFIG_SMC911X_BASE); #endif return 0; @@ -186,31 +128,12 @@ int checkboard(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - int i, err; - - /* - * MMC2 SD card GPIO: - * - * GPC2[0] SD_2_CLK(2) - * GPC2[1] SD_2_CMD(2) - * GPC2[2] SD_2_CDn - * GPC2[3:6] SD_2_DATA[0:3](2) - */ - for (i = 0; i < 7; i++) { - /* GPC2[0:6] special function 2 */ - s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2)); - - /* GPK2[0:6] drv 4x */ - s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X); + int err; - /* GPK2[0:1] pull disable */ - if (i == 0 || i == 1) { - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE); - continue; - } - - /* GPK2[2:6] pull up */ - s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP); + err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); + if (err) { + debug("SDMMC2 not configured\n"); + return err; } err = s5p_mmc_init(2, 4); @@ -218,63 +141,40 @@ int board_mmc_init(bd_t *bis) } #endif -static void board_uart_init(void) +static int board_uart_init(void) { - struct exynos5_gpio_part1 *gpio1 = - (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); - int i; + int err; - /* - * UART0 GPIOs : GPA0CON[3:0] 0x2222 - * Must set CFG17 switches to select UART0 to use. - */ - for (i = 0; i <= 3; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE); + if (err) { + debug("UART0 not configured\n"); + return err; } - /* - * UART1 GPIOs : GPA0CON[5:4] 0x22 - * Must set CFG17 switches to select UART1 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE); + if (err) { + debug("UART1 not configured\n"); + return err; } - /* - * UART2 GPIOs : GPA1CON[1:0] 0x22 - * Must set CFG17 switches to select UART2 to use. - * - * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down - * in order to use them (so that those pins can be used for I2C). - */ - for (i = 0; i <= 1; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE); + if (err) { + debug("UART2 not configured\n"); + return err; } - /* - * UART3 GPIOs : GPA1CON[5:4] 0x22 - * Must set CFG16 switches to select UART3 to use. - */ - for (i = 4; i <= 5; i++) { - s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2)); + err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); + if (err) { + debug("UART3 not configured\n"); + return err; } - /* - * There's no mux for UART4--it's internal only - */ + return 0; } #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - board_uart_init(); - return 0; + return board_uart_init(); } #endif diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index a0eec75bc5..a8b2b11c4c 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -220,6 +220,7 @@ int board_mmc_init(bd_t *bis) static int s5pc210_phy_control(int on) { int ret = 0; + u32 val = 0; struct pmic *p = get_pmic(); if (pmic_probe(p)) @@ -228,11 +229,17 @@ static int s5pc210_phy_control(int on) if (on) { ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_ON); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); } else { - ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO); - ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO); + ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); + + ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, ENSAFEOUT1, LDO_OFF); } @@ -461,42 +468,44 @@ static int mipi_power(void) return 0; } +vidinfo_t panel_info = { + .vl_freq = 60, + .vl_col = 720, + .vl_row = 1280, + .vl_width = 720, + .vl_height = 1280, + .vl_clkp = CONFIG_SYS_HIGH, + .vl_hsp = CONFIG_SYS_LOW, + .vl_vsp = CONFIG_SYS_LOW, + .vl_dp = CONFIG_SYS_LOW, + .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ + + /* s6e8ax0 Panel infomation */ + .vl_hspw = 5, + .vl_hbpd = 10, + .vl_hfpd = 10, + + .vl_vspw = 2, + .vl_vbpd = 1, + .vl_vfpd = 13, + .vl_cmd_allow_len = 0xf, + + .win_id = 3, + .cfg_gpio = NULL, + .backlight_on = NULL, + .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ + .reset_lcd = lcd_reset, + .dual_lcd_enabled = 0, + + .init_delay = 0, + .power_on_delay = 0, + .reset_delay = 0, + .interface_mode = FIMD_RGB_INTERFACE, + .mipi_enabled = 1, +}; + void init_panel_info(vidinfo_t *vid) { - vid->vl_freq = 60; - vid->vl_col = 720; - vid->vl_row = 1280; - vid->vl_width = 720; - vid->vl_height = 1280; - vid->vl_clkp = CONFIG_SYS_HIGH; - vid->vl_hsp = CONFIG_SYS_LOW; - vid->vl_vsp = CONFIG_SYS_LOW; - vid->vl_dp = CONFIG_SYS_LOW; - - vid->vl_bpix = 5; - vid->dual_lcd_enabled = 0; - - /* s6e8ax0 Panel */ - vid->vl_hspw = 5; - vid->vl_hbpd = 10; - vid->vl_hfpd = 10; - - vid->vl_vspw = 2; - vid->vl_vbpd = 1; - vid->vl_vfpd = 13; - vid->vl_cmd_allow_len = 0xf; - - vid->win_id = 3; - vid->cfg_gpio = NULL; - vid->backlight_on = NULL; - vid->lcd_power_on = NULL; /* lcd_power_on in mipi dsi driver */ - vid->reset_lcd = lcd_reset; - - vid->init_delay = 0; - vid->power_on_delay = 0; - vid->reset_delay = 0; - vid->interface_mode = FIMD_RGB_INTERFACE; - vid->mipi_enabled = 1; vid->logo_on = 1, vid->resolution = HD_RESOLUTION, vid->rgb_mode = MODE_RGB_P, diff --git a/doc/README.sandbox b/board/sandbox/sandbox/README.sandbox index 04692b34fa..04692b34fa 100644 --- a/doc/README.sandbox +++ b/board/sandbox/sandbox/README.sandbox diff --git a/board/sandpoint/README b/board/sandpoint/README index 9e48168a24..a2e0831f33 100644 --- a/board/sandpoint/README +++ b/board/sandpoint/README @@ -13,3 +13,401 @@ seem to maintain it any more. I can be reached by mail as tkoeller@gmx.net. Thomas Koeller + + + + +The port was tested on a Sandpoint 8240 X3 board, with U-Boot +installed in the flash memory of the CPU card. Please use the +following DIP switch settings: + +Motherboard: + +SW1.1: on SW1.2: on SW1.3: on SW1.4: on +SW1.5: on SW1.6: on SW1.7: on SW1.8: on + +SW2.1: on SW2.2: on SW2.3: on SW2.4: on +SW2.5: on SW2.6: on SW2.7: on SW2.8: on + + +CPU Card: + +SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on +SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF + +SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF +SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on + + +The followind detailed description of installation and initial steps +with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>: + + +Directions for installing U-Boot on Sandpoint+Unity8240 +using the Abatron BDI2000 BDM/JTAG debugger ... + +Background and Reference info: +http://u-boot.sourceforge.net/ +http://www.abatron.ch/ +http://www.abatron.ch/BDI/bdihw.html +http://www.abatron.ch/DataSheets/BDI2000.pdf +http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf +http://e-www.motorola.com/collateral/SPX3UM.pdf +http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf + + +Connection Diagram: + =========== + === ===== |----- | +| | <---------------> | | | | | +|PC | rs232 | BDI |=============[] | | +| | |2000 | BDM probe | | | +| | <---------------> | | |----- | + === ethernet ===== | | + | | + =========== + Sandpoint X3 with + Unity 8240 proc + + +PART 1) + DIP Switch Settings: + +Sandpoint X3 8240 processor board DIP switch settings, with +U-Boot to be installed in the flash memory of the CPU card: + +Motorola Sandpoint X3 Motherboard: +SW1.1: on SW1.2: on SW1.3: on SW1.4: on +SW1.5: on SW1.6: on SW1.7: on SW1.8: on +SW2.1: on SW2.2: on SW2.3: on SW2.4: on +SW2.5: on SW2.6: on SW2.7: on SW2.8: on + +Motorola Unity 8240 CPU Card: +SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on +SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF +SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF +SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on + + +PART 2) + Connect the BDI2000 Cable to the Sandpoint/Unity 8240: + +BDM Pin 1 on the Unity 8240 processor board is towards the +PCI PMC connectors, or away from the socketed SDRAM, i.e.: + + ==================== + | ---------------- | + | | SDRAM | | + | | | | + | ---------------- | + | |~| | + | |B| ++++++ | + | |D| + uP + | + | |M| +8240+ | + | ~ 1 ++++++ | + | | + | | + | | + | PMC conn ====== | + | ===== ====== | + | | + ==================== + + +PART 3) + Setting up the BDI2000, and preparing for TCP/IP network comms: + +Connect the BDI2000 to the PC using the supplied serial cable. +Download the BDI2000 software and install it using setup.exe. + +[Note: of course you can also use the Linux command line tool +"bdisetup" to configure your BDI2000 - the sources are included on +the floppy disk that comes with your BDI2000. Just in case you don't +have any Windows PC's - like me :-) -- wd ] + +Power up the BDI2000; then follow directions to assign the IP +address and related network information. Note that U-Boot +will be loaded to the Sandpoint via tftp. You need to either +use the Abatron-provided tftp application or provide a tftp +server (e.g. Linux/Solaris/*BSD) somewhere on your network. +Once the IP address etc are assigned via the RS232 port, +further communication with the BDI2000 will happen via the +ethernet connection. + +PART 4) + Making a TCP/IP network connection to the Abatron BDI2000: + +Telnet to the Abatron BDI2000. Assuming that all of the +networking info was loaded via RS232 correctly, you will see +the following (scrolling): + +- TARGET: waiting for target Vcc +- TARGET: waiting for target Vcc + + +PART 5) + Power up the target Sandpoint: +If the BDM connections are correct, the following will now appear: + +- TARGET: waiting for target Vcc +- TARGET: waiting for target Vcc +- TARGET: processing power-up delay +- TARGET: processing user reset request +- BDI asserts HRESET +- Reset JTAG controller passed +- Bypass check: 0x55 => 0xAA +- Bypass check: 0x55 => 0xAA +- JTAG exists check passed +- Target PVR is 0x00810101 +- COP status is 0x01 +- Check running state passed +- BDI scans COP freeze command +- BDI removes HRESET +- COP status is 0x05 +- Check stopped state passed +- Check LSRL length passed +- BDI sets breakpoint at 0xFFF00100 +- BDI resumes program execution +- Waiting for target stop passed +- TARGET: Target PVR is 0x00810101 +- TARGET: reseting target passed +- TARGET: processing target startup .... +- TARGET: processing target startup passed +BDI> + + +PART 6) + Erase the current contents of the flash memory: + +BDI>era 0xFFF00000 + Erasing flash at 0xfff00000 + Erasing flash passed +BDI>era 0xFFF04000 + Erasing flash at 0xfff04000 + Erasing flash passed +BDI>era 0xFFF06000 + Erasing flash at 0xfff06000 + Erasing flash passed +BDI>era 0xFFF08000 + Erasing flash at 0xfff08000 + Erasing flash passed +BDI>era 0xFFF10000 + Erasing flash at 0xfff10000 + Erasing flash passed +BDI>era 0xFFF20000 + Erasing flash at 0xfff20000 + Erasing flash passed + + +PART 7) + Program the flash memory with the U-Boot image: + +BDI>prog 0xFFF00000 u-boot.bin bin + Programming u-boot.bin , please wait .... + Programming flash passed + + +PART 8) + Connect PC to Sandpoint: +Using a crossover serial cable, attach the PC serial port to the +Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud. + + +PART 9) + Reset the Unity and begin U-Boot execution: + +BDI>reset +- TARGET: processing user reset request +- TARGET: Target PVR is 0x00810101 +- TARGET: reseting target passed +- TARGET: processing target init list .... +- TARGET: processing target init list passed + +BDI>go + +Now see output from U-Boot running, sent via serial port: + +U-Boot 1.1.4 (Jan 23 2002 - 18:29:19) + +CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache +Board: Sandpoint 8240 Unity +DRAM: 64 MB +FLASH: 2 MB +PCI: scanning bus0 ... + bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE + 00 00 00 1057 0003 060000 13 00000008 00000000 01 00 + 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00 + 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00 +In: serial +Out: serial +Err: serial +=> + + +PART 10) + Set and save any required environmental variables, examples of some: + +=> setenv ethaddr 00:03:47:97:D0:79 +=> setenv bootfile your_qnx_image_here +=> setenv hostname sandpointX +=> setenv netmask 255.255.255.0 +=> setenv ipaddr 192.168.0.11 +=> setenv serverip 192.168.0.10 +=> setenv gatewayip=192.168.0.1 +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + +**** Example environment: **** + +=> printenv +baudrate=9600 +bootfile=telemetry +hostname=sp1 +ethaddr=00:03:47:97:E4:6B +load=tftp 100000 u-boot.bin +update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv +filesize=1f304 +gatewayip=145.17.228.1 +netmask=255.255.255.0 +ipaddr=145.17.228.42 +serverip=145.17.242.46 +stdin=serial +stdout=serial +stderr=serial + +Environment size: 332/8188 bytes +=> + +here's some text useful stuff for cut-n-paste: +setenv hostname sandpoint1 +setenv netmask 255.255.255.0 +setenv ipaddr 145.17.228.81 +setenv serverip 145.17.242.46 +setenv gatewayip 145.17.228.1 +saveenv + +PART 11) + Test U-Boot by tftp'ing new U-Boot, overwriting current: + +=> protect off all +Un-Protect Flash Bank # 1 +=> tftp 100000 u-boot.bin +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'u-boot.bin'. +Load address: 0x100000 +Loading: ######################### +done +Bytes transferred = 127628 (1f28c hex) +=> era all +Erase Flash Bank # 1 + done +Erase Flash Bank # 2 - missing +=> cp.b 0x100000 FFF00000 1f28c +Copy to Flash... done +=> saveenv +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> reset + +You can put these commands into some environment variables; + +=> setenv load tftp 100000 u-boot.bin +=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv +=> saveenv + +Then you just have to type "run load" then "run update" + +=> run load +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'u-boot.bin'. +Load address: 0x100000 +Loading: ######################### +done +Bytes transferred = 127748 (1f304 hex) +=> run update +Un-Protect Flash Bank # 1 +Un-Protect Flash Bank # 2 +Erase Flash from 0xfff00000 to 0xfff3ffff + done +Erased 7 sectors +Copy to Flash... done +Saving Environment to Flash... +Un-Protected 1 sectors +Erasing Flash... + done +Erased 1 sectors +Writing to Flash... done +Protected 1 sectors +=> + + +PART 12) + Load OS image (ELF format) via U-Boot using tftp + + +=> tftp 800000 sandpoint-simple.elf +eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) +ARP broadcast 1 +TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through + gateway 145.17.228.1 +Filename 'sandpoint-simple.elf'. +Load address: 0x800000 +Loading: ################################################################# + ################################################################# + ################################################################# + ######################## +done +Bytes transferred = 1120284 (11181c hex) +==> + +PART 13) + Begin OS image execution: (note that unless you have the +serial parameters of your OS image set to 9600 (i.e. same as +the U-Boot binary) you will get garbage here until you change +the serial communications speed. + +=> bootelf 800000 +Loading @ 0x001f0100 (1120028 bytes) +## Starting application at 0x001f1d28 ... +Replace init_hwinfo() with a board specific version + +Loading QNX6.... + +Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1 +<...loader and kernel messages snipped...> + +Welcome to Neutrino on the Sandpoint +# + + +other information: + +CVS Retrieval Notes: + +U-Boot's SourceForge CVS repository can be checked out +through anonymous (pserver) CVS with the following +instruction set. The module you wish to check out must +be specified as the modulename. When prompted for a +password for anonymous, simply press the Enter key. + +cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login + +cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot diff --git a/doc/README.sbc8349 b/board/sbc8349/README index 2c35919f28..2c35919f28 100644 --- a/doc/README.sbc8349 +++ b/board/sbc8349/README diff --git a/doc/README.sbc8548 b/board/sbc8548/README index feac5e3e63..feac5e3e63 100644 --- a/doc/README.sbc8548 +++ b/board/sbc8548/README diff --git a/doc/README.SBC8560 b/board/sbc8560/README index c4b642236e..c4b642236e 100644 --- a/doc/README.SBC8560 +++ b/board/sbc8560/README diff --git a/doc/README.sbc8641d b/board/sbc8641d/README index a051466a11..a051466a11 100644 --- a/doc/README.sbc8641d +++ b/board/sbc8641d/README diff --git a/doc/README.simpc8313 b/board/sheldon/simpc8313/README.simpc8313 index b362c6aeea..b362c6aeea 100644 --- a/doc/README.simpc8313 +++ b/board/sheldon/simpc8313/README.simpc8313 diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 11f81e4803..5c66c3f092 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -29,8 +29,10 @@ endif LIB = $(obj)lib$(VENDOR).o +ifndef CONFIG_SPL_BUILD COBJS := spr_misc.o SOBJS := spr_lowlevel_init.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 0812c20b8c..99a6595966 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -25,10 +25,10 @@ #include <command.h> #include <i2c.h> #include <net.h> +#include <linux/mtd/st_smi.h> #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_emi.h> -#include <asm/arch/spr_xloader_table.h> #include <asm/arch/spr_defs.h> #define CPU 0 @@ -36,31 +36,16 @@ #define SRAM_REL 0xD2801000 DECLARE_GLOBAL_DATA_PTR; -static struct chip_data chip_data; + +#if defined(CONFIG_CMD_NET) +static int i2c_read_mac(uchar *buffer); +#endif int dram_init(void) { - struct xloader_table *xloader_tb = - (struct xloader_table *)XLOADER_TABLE_ADDRESS; - struct xloader_table_1_1 *table_1_1; - struct xloader_table_1_2 *table_1_2; - struct chip_data *chip = &chip_data; - + /* Store complete RAM size and return */ gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE); - if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) { - table_1_1 = &xloader_tb->table.table_1_1; - chip->dramfreq = table_1_1->ddrfreq; - chip->dramtype = table_1_1->ddrtype; - - } else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { - table_1_2 = &xloader_tb->table.table_1_2; - chip->dramfreq = table_1_2->ddrfreq; - chip->dramtype = table_1_2->ddrtype; - } else { - chip->dramfreq = -1; - } - return 0; } @@ -70,6 +55,13 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = gd->ram_size; } +int board_early_init_f() +{ +#if defined(CONFIG_ST_SMI) + smi_init(); +#endif + return 0; +} int misc_init_r(void) { #if defined(CONFIG_CMD_NET) @@ -84,6 +76,10 @@ int misc_init_r(void) setenv("stdin", "usbtty"); setenv("stdout", "usbtty"); setenv("stderr", "usbtty"); + +#ifndef CONFIG_SYS_NO_DCACHE + dcache_enable(); +#endif #endif return 0; } @@ -145,31 +141,18 @@ void spear_emi_init(void) int spear_board_init(ulong mach_type) { - struct xloader_table *xloader_tb = - (struct xloader_table *)XLOADER_TABLE_ADDRESS; - struct xloader_table_1_2 *table_1_2; - struct chip_data *chip = &chip_data; - gd->bd->bi_arch_number = mach_type; /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; - /* CPU is initialized to work at 333MHz in Xloader */ - chip->cpufreq = 333; - - if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) { - table_1_2 = &xloader_tb->table.table_1_2; - memcpy(chip->version, table_1_2->version, - sizeof(chip->version)); - } - #ifdef CONFIG_SPEAR_EMI spear_emi_init(); #endif return 0; } +#if defined(CONFIG_CMD_NET) static int i2c_read_mac(uchar *buffer) { u8 buf[2]; @@ -206,18 +189,18 @@ static int write_mac(uchar *mac) return 0; } - puts("I2C EEPROM writing failed \n"); + puts("I2C EEPROM writing failed\n"); return -1; } +#endif int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { void (*sram_setfreq) (unsigned int, unsigned int); - struct chip_data *chip = &chip_data; + unsigned int frequency; +#if defined(CONFIG_CMD_NET) unsigned char mac[6]; - unsigned int reg, frequency; - char *s, *e; - char i2c_mac[20]; +#endif if ((argc > 3) || (argc < 2)) return cmd_usage(cmdtp); @@ -236,19 +219,18 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (!strcmp(argv[1], "cpufreq")) { sram_setfreq(CPU, frequency); printf("CPU frequency changed to %u\n", frequency); - - chip->cpufreq = frequency; } else { sram_setfreq(DDR, frequency); printf("DDR frequency changed to %u\n", frequency); - - chip->dramfreq = frequency; } return 0; + +#if defined(CONFIG_CMD_NET) } else if (!strcmp(argv[1], "ethaddr")) { - s = argv[2]; + u32 reg; + char *e, *s = argv[2]; for (reg = 0; reg < 6; ++reg) { mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; if (s) @@ -257,34 +239,15 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) write_mac(mac); return 0; +#endif } else if (!strcmp(argv[1], "print")) { - - if (chip->cpufreq == -1) - printf("CPU Freq = Not Known\n"); - else - printf("CPU Freq = %d MHz\n", chip->cpufreq); - - if (chip->dramfreq == -1) - printf("DDR Freq = Not Known\n"); - else - printf("DDR Freq = %d MHz\n", chip->dramfreq); - - if (chip->dramtype == DDRMOBILE) - printf("DDR Type = MOBILE\n"); - else if (chip->dramtype == DDR2) - printf("DDR Type = DDR2\n"); - else - printf("DDR Type = Not Known\n"); - +#if defined(CONFIG_CMD_NET) if (!i2c_read_mac(mac)) { - sprintf(i2c_mac, "%pM", mac); - printf("Ethaddr (from i2c mem) = %s\n", i2c_mac); + printf("Ethaddr (from i2c mem) = %pM\n", mac); } else { printf("Ethaddr (from i2c mem) = Not set\n"); } - - printf("Xloader Rev = %s\n", chip->version); - +#endif return 0; } @@ -294,4 +257,7 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(chip_config, 3, 1, do_chip_config, "configure chip", "chip_config cpufreq/ddrfreq frequency\n" +#if defined(CONFIG_CMD_NET) + "chip_config ethaddr XX:XX:XX:XX:XX:XX\n" +#endif "chip_config print"); diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 60ee54470e..f809c2dc91 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -22,12 +22,16 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -41,18 +45,33 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } +#endif + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; - return -1; +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif + return ret; } diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 03dfe16175..8609a5910f 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -23,12 +23,16 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -42,18 +46,50 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } +#endif + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) >= 0) + ret++; + + if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, + CONFIG_MACB1_PHY) >= 0) + ret++; + + if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, + CONFIG_MACB2_PHY) >= 0) + ret++; - return -1; + if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, + CONFIG_MACB3_PHY) >= 0) + ret++; +#endif + return ret; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 2ba2dbb566..54a2e1003c 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -23,15 +23,29 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +#define PLGPIO_SEL_36 0xb3000028 +#define PLGPIO_IO_36 0xb3000038 + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +static void spear_phy_reset(void) +{ + writel(0x10, PLGPIO_IO_36); + writel(0x10, PLGPIO_SEL_36); +} int board_init(void) { + spear_phy_reset(); return spear_board_init(MACH_TYPE_SPEAR320); } @@ -42,18 +56,39 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + fsmc_nand_init(nand); } +#endif + + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; - return -1; +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) >= 0) + ret++; +#endif + return ret; } diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile index e2bd5ab7f5..ee66fc6520 100644 --- a/board/spear/spear600/Makefile +++ b/board/spear/spear600/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := spear600.o +endif SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index eef9a3771c..814f9ccb6b 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -22,12 +22,16 @@ */ #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; int board_init(void) { @@ -41,13 +45,31 @@ int board_init(void) * Called by nand_init_chip to initialize the board specific functions */ -int board_nand_init(struct nand_chip *nand) +void board_nand_init() { struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; +#if defined(CONFIG_NAND_FSMC) if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) - return spear_nand_init(nand); + fsmc_nand_init(nand); +#endif + return; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; - return -1; +#if defined(CONFIG_DESIGNWARE_ETH) + u32 interface = PHY_INTERFACE_MODE_MII; +#if defined(CONFIG_DW_AUTONEG) + interface = PHY_INTERFACE_MODE_GMII; +#endif + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, + interface) >= 0) + ret++; +#endif + return ret; } diff --git a/doc/README.nhk8815 b/board/st/nhk8815/README.nhk8815 index 9008e39363..9008e39363 100644 --- a/doc/README.nhk8815 +++ b/board/st/nhk8815/README.nhk8815 diff --git a/doc/README.stxxtc b/board/stx/stxxtc/README.stxxtc index 7d9d4d3a2e..7d9d4d3a2e 100644 --- a/doc/README.stxxtc +++ b/board/stx/stxxtc/README.stxxtc diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c index 13dc60361a..5e2d53ab42 100644 --- a/board/ti/am335x/evm.c +++ b/board/ti/am335x/evm.c @@ -29,17 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; /* * Basic board specific setup */ -int init_basic_setup(void) -{ - /* Initialize the Timer */ - init_timer(); - - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; - - return 0; -} - int board_init(void) { enable_uart0_pin_mux(); @@ -49,7 +38,7 @@ int board_init(void) i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif - init_basic_setup(); + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; return 0; } diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9edd3c5c4f..2ef22900d7 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -68,6 +68,7 @@ #define BBTOYS_VGA 0x02000B00 #define BBTOYS_LCD 0x03000B00 #define BCT_BRETTL3 0x01000F00 +#define BCT_BRETTL4 0x02000F00 #define BEAGLE_NO_EEPROM 0xffffffff DECLARE_GLOBAL_DATA_PTR; @@ -417,8 +418,11 @@ int misc_init_r(void) printf("Recognized BeagleBoardToys LCD board\n"); break;; case BCT_BRETTL3: - printf("Recognized bct electronic GmbH brettl3 board\n"); - break; + printf("Recognized bct electronic GmbH brettl3 board\n"); + break; + case BCT_BRETTL4: + printf("Recognized bct electronic GmbH brettl4 board\n"); + break; case BEAGLE_NO_EEPROM: printf("No EEPROM on expansion board\n"); setenv("buddy", "none"); diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h index 296eb682e1..a82795dc13 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_evm/mux_data.h @@ -47,6 +47,15 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ + {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ + {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ + {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ + {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ + {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ + {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ + {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ + {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ + {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ }; @@ -114,10 +123,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ - {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ - {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ - {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ - {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ @@ -254,11 +259,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ - {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ - {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ - {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ - {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ - {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ diff --git a/doc/README.omap730p2 b/board/ti/omap730p2/README.omap730p2 index 7c70916120..7c70916120 100644 --- a/doc/README.omap730p2 +++ b/board/ti/omap730p2/README.omap730p2 diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index dc8b3886c2..5939257ff1 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -62,7 +62,26 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ -{UART3_TX_IRTX, (M0)} /* uart3_tx */ +{UART3_TX_IRTX, (M0)}, /* uart3_tx */ +{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ +{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ +{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ +{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ +{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ +{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ +{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ +{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ +{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ +{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ +{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ +{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ +{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ +{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ +{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ +{UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ +{GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ +{FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ }; @@ -70,7 +89,8 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ -{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ +{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ +{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ }; @@ -109,7 +129,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */ {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ @@ -136,22 +155,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ - {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ - {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ - {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ @@ -211,7 +214,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ - {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ @@ -222,7 +224,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ @@ -272,7 +273,6 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 6140b999ef..0760dad620 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -53,8 +53,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ -{UART3_TX_IRTX, (M0)} /* uart3_tx */ - +{UART3_TX_IRTX, (M0)}, /* uart3_tx */ +{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ +{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ +{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ +{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ +{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ +{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ +{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ +{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ +{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ +{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ +{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ }; const struct pad_conf_entry wkup_padconf_array_essential[] = { @@ -135,14 +145,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ - {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ - {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ - {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ @@ -210,9 +212,6 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ diff --git a/doc/README.timll b/board/timll/devkit8000/README index 609bf51aee..609bf51aee 100644 --- a/doc/README.timll +++ b/board/timll/devkit8000/README diff --git a/doc/README.TQM8260 b/board/tqc/tqm8260/README index 93b55068f5..93b55068f5 100644 --- a/doc/README.TQM8260 +++ b/board/tqc/tqm8260/README diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile index 393ad68f77..1e018b0701 100644 --- a/board/ttcontrol/vision2/Makefile +++ b/board/ttcontrol/vision2/Makefile @@ -25,12 +25,11 @@ LIB = $(obj)lib$(BOARD).o COBJS := vision2.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/doc/README.xpedite1k b/board/xes/xpedite1000/README index 1da8b800be..1da8b800be 100644 --- a/doc/README.xpedite1k +++ b/board/xes/xpedite1000/README diff --git a/doc/README.zeus b/board/zeus/README index 1848d8cd38..1848d8cd38 100644 --- a/doc/README.zeus +++ b/board/zeus/README diff --git a/boards.cfg b/boards.cfg index a723f67eb1..2d36d83335 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,8 @@ at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 +vl_ma2sc arm arm926ejs vl_ma2sc BuS at91 +vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM @@ -138,10 +140,14 @@ enbw_cmc arm arm926ejs enbw_cmc enbw calimain arm arm926ejs calimain omicron davinci pogo_e02 arm arm926ejs - cloudengines kirkwood dns325 arm arm926ejs - d-link kirkwood -km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI -km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_RECONFIG_XLX -mgcoge3un arm arm926ejs km_arm keymile kirkwood -portl2 arm arm926ejs km_arm keymile kirkwood +lschlv2 arm arm926ejs lsxl buffalo kirkwood lsxl:LSCHLV2 +lsxhl arm arm926ejs lsxl buffalo kirkwood lsxl:LSXHL +km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD +km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI +kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA +mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN +kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN +portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 inetspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:INETSPACE_V2 net2big_v2 arm arm926ejs net2big_v2 LaCie kirkwood lacie_kw:NET2BIG_V2 netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 @@ -156,6 +162,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood ib62x0 arm arm926ejs ib62x0 raidsonic kirkwood dockstar arm arm926ejs - Seagate kirkwood +tk71 arm arm926ejs tk71 karo kirkwood devkit3250 arm arm926ejs devkit3250 timll lpc32xx jadecpu arm arm926ejs jadecpu syteco mb86r0x mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg @@ -173,10 +180,26 @@ omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2_cs3boot arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT edminiv2 arm arm926ejs - LaCie orion5x dkb arm arm926ejs - Marvell pantheon -spear300 arm arm926ejs spear300 spear spear spear3xx:spear300 -spear310 arm arm926ejs spear310 spear spear spear3xx:spear310 -spear320 arm arm926ejs spear320 spear spear spear3xx:spear320 -spear600 arm arm926ejs spear600 spear spear spear6xx:spear600 +spear300 arm arm926ejs spear300 spear spear spear3xx_evb:spear300 +spear300_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,nand +spear300_usbtty arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty +spear300_usbtty_nand arm arm926ejs spear300 spear spear spear3xx_evb:spear300,usbtty,nand +spear310 arm arm926ejs spear310 spear spear spear3xx_evb:spear310 +spear310_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,FLASH_PNOR +spear310_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,nand +spear310_usbtty arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty +spear310_usbtty_pnor arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,FLASH_PNOR +spear310_usbtty_nand arm arm926ejs spear310 spear spear spear3xx_evb:spear310,usbtty,nand +spear320 arm arm926ejs spear320 spear spear spear3xx_evb:spear320 +spear320_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,FLASH_PNOR +spear320_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,nand +spear320_usbtty arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty +spear320_usbtty_pnor arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,FLASH_PNOR +spear320_usbtty_nand arm arm926ejs spear320 spear spear spear3xx_evb:spear320,usbtty,nand +spear600 arm arm926ejs spear600 spear spear spear6xx_evb:spear600 +spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand +spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty +spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB @@ -231,6 +254,7 @@ trats arm armv7 trats samsung harmony arm armv7 harmony nvidia tegra2 seaboard arm armv7 seaboard nvidia tegra2 ventana arm armv7 ventana nvidia tegra2 +whistler arm armv7 whistler nvidia tegra2 u8500_href arm armv7 u8500 st-ericsson u8500 actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2 actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB @@ -258,7 +282,9 @@ colibri_pxa270 arm pxa - toradex jornada arm sa1100 plutux arm armv7 plutux avionic-design tegra2 medcom arm armv7 medcom avionic-design tegra2 +tec arm armv7 tec avionic-design tegra2 paz00 arm armv7 paz00 compal tegra2 +trimslice arm armv7 trimslice compulab tegra2 atngw100 avr32 at32ap - atmel at32ap700x atstk1002 avr32 at32ap atstk1000 atmel at32ap700x atstk1003 avr32 at32ap atstk1000 atmel at32ap700x @@ -775,6 +801,7 @@ P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freesca P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 +BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/common/Makefile b/common/Makefile index 31175e34d3..483eb4daa3 100644 --- a/common/Makefile +++ b/common/Makefile @@ -31,7 +31,6 @@ COBJS-y += main.o COBJS-y += command.o COBJS-y += exports.o COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o -COBJS-y += image.o COBJS-y += s_record.o COBJS-$(CONFIG_SERIAL_MULTI) += serial.o COBJS-y += xyzModem.o @@ -191,6 +190,7 @@ COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o endif COBJS-y += console.o COBJS-y += dlmalloc.o +COBJS-y += image.o COBJS-y += memsize.o COBJS-y += stdio.o diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index 2b1115d727..77a7dd17ac 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -26,7 +26,6 @@ #define MAX_TFTP_PATH_LEN 127 - /* * Like getenv, but prints an error if envvar isn't defined in the * environment. It always returns what getenv does, so it can be used in @@ -175,8 +174,6 @@ static int do_get_fat(char *file_path, char *file_addr) return -ENOENT; } - - /* * As in pxelinux, paths to files referenced from files we retrieve are * relative to the location of bootfile. get_relfile takes such a path and @@ -365,7 +362,6 @@ do_pxe_get(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc != 1) return CMD_RET_USAGE; - pxefile_addr_str = from_env("pxefile_addr_r"); if (!pxefile_addr_str) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 9c76464a9a..5ac1d0c4c1 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -211,6 +211,13 @@ static int do_spi_flash_read_write(int argc, char * const argv[]) if (*argv[3] == 0 || *endp != 0) return -1; + /* Consistency checking */ + if (offset + len > flash->size) { + printf("ERROR: attempting %s past flash size (%#x)\n", + argv[0], flash->size); + return 1; + } + buf = map_physmem(addr, len, MAP_WRBACK); if (!buf) { puts("Failed to map physical memory\n"); @@ -252,6 +259,13 @@ static int do_spi_flash_erase(int argc, char * const argv[]) if (ret != 1) return -1; + /* Consistency checking */ + if (offset + len > flash->size) { + printf("ERROR: attempting %s past flash size (%#x)\n", + argv[0], flash->size); + return 1; + } + ret = spi_flash_erase(flash, offset, len); if (ret) { printf("SPI flash %s failed\n", argv[0]); diff --git a/common/env_common.c b/common/env_common.c index c33d22d752..d9e990dbbe 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -116,6 +116,17 @@ const uchar default_environment[] = { #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0" #endif +#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG + "arch=" CONFIG_SYS_ARCH "\0" + "cpu=" CONFIG_SYS_CPU "\0" + "board=" CONFIG_SYS_BOARD "\0" +#ifdef CONFIG_SYS_VENDOR + "vendor=" CONFIG_SYS_VENDOR "\0" +#endif +#ifdef CONFIG_SYS_SOC + "soc=" CONFIG_SYS_SOC "\0" +#endif +#endif #ifdef CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS #endif diff --git a/common/env_embedded.c b/common/env_embedded.c index 80fb29dd5e..3872878885 100644 --- a/common/env_embedded.c +++ b/common/env_embedded.c @@ -179,6 +179,17 @@ env_t environment __PPCENV__ = { #if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0) "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0" #endif +#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG + "arch=" CONFIG_SYS_ARCH "\0" + "cpu=" CONFIG_SYS_CPU "\0" + "board=" CONFIG_SYS_BOARD "\0" +#ifdef CONFIG_SYS_VENDOR + "vendor=" CONFIG_SYS_VENDOR "\0" +#endif +#ifdef CONFIG_SYS_SOC + "soc=" CONFIG_SYS_SOC "\0" +#endif +#endif #ifdef CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS #endif diff --git a/common/env_mmc.c b/common/env_mmc.c index 0c58ae19b2..be2f2be205 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -95,7 +95,7 @@ static inline int write_env(struct mmc *mmc, unsigned long size, int saveenv(void) { - env_t env_new; + ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); ssize_t len; char *res; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); @@ -104,16 +104,16 @@ int saveenv(void) if (init_mmc_for_env(mmc) || mmc_get_env_addr(mmc, &offset)) return 1; - res = (char *)&env_new.data; + res = (char *)&env_new->data; len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL); if (len < 0) { error("Cannot export environment: errno = %d\n", errno); return 1; } - env_new.crc = crc32(0, env_new.data, ENV_SIZE); + env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE); printf("Writing to MMC(%d)... ", CONFIG_SYS_MMC_ENV_DEV); - if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)&env_new)) { + if (write_env(mmc, CONFIG_ENV_SIZE, offset, (u_char *)env_new)) { puts("failed\n"); return 1; } @@ -140,7 +140,7 @@ static inline int read_env(struct mmc *mmc, unsigned long size, void env_relocate_spec(void) { #if !defined(ENV_IS_EMBEDDED) - char buf[CONFIG_ENV_SIZE]; + ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); u32 offset; diff --git a/common/lcd.c b/common/lcd.c index 85c6cf4374..506a138cdd 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -76,42 +76,42 @@ DECLARE_GLOBAL_DATA_PTR; ulong lcd_setmem (ulong addr); -static void lcd_drawchars (ushort x, ushort y, uchar *str, int count); -static inline void lcd_puts_xy (ushort x, ushort y, uchar *s); -static inline void lcd_putc_xy (ushort x, ushort y, uchar c); +static void lcd_drawchars(ushort x, ushort y, uchar *str, int count); +static inline void lcd_puts_xy(ushort x, ushort y, uchar *s); +static inline void lcd_putc_xy(ushort x, ushort y, uchar c); -static int lcd_init (void *lcdbase); +static int lcd_init(void *lcdbase); static void *lcd_logo (void); -static int lcd_getbgcolor (void); -static void lcd_setfgcolor (int color); -static void lcd_setbgcolor (int color); +static int lcd_getbgcolor(void); +static void lcd_setfgcolor(int color); +static void lcd_setbgcolor(int color); char lcd_is_enabled = 0; #ifdef NOT_USED_SO_FAR -static void lcd_getcolreg (ushort regno, +static void lcd_getcolreg(ushort regno, ushort *red, ushort *green, ushort *blue); -static int lcd_getfgcolor (void); +static int lcd_getfgcolor(void); #endif /* NOT_USED_SO_FAR */ /************************************************************************/ /*----------------------------------------------------------------------*/ -static void console_scrollup (void) +static void console_scrollup(void) { /* Copy up rows ignoring the first one */ - memcpy (CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE); + memcpy(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE); /* Clear the last one */ - memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE); + memset(CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE); } /*----------------------------------------------------------------------*/ -static inline void console_back (void) +static inline void console_back(void) { if (--console_col < 0) { console_col = CONSOLE_COLS-1 ; @@ -120,14 +120,13 @@ static inline void console_back (void) } } - lcd_putc_xy (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, - ' '); + lcd_putc_xy(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, ' '); } /*----------------------------------------------------------------------*/ -static inline void console_newline (void) +static inline void console_newline(void) { ++console_row; console_col = 0; @@ -135,61 +134,62 @@ static inline void console_newline (void) /* Check if we need to scroll the terminal */ if (console_row >= CONSOLE_ROWS) { /* Scroll everything up */ - console_scrollup () ; + console_scrollup(); --console_row; } } /*----------------------------------------------------------------------*/ -void lcd_putc (const char c) +void lcd_putc(const char c) { if (!lcd_is_enabled) { serial_putc(c); + return; } switch (c) { - case '\r': console_col = 0; - return; + case '\r': + console_col = 0; - case '\n': console_newline(); - return; + return; + case '\n': + console_newline(); + return; case '\t': /* Tab (8 chars alignment) */ - console_col += 8; - console_col &= ~7; + console_col += 8; + console_col &= ~7; - if (console_col >= CONSOLE_COLS) { - console_newline(); - } - return; + if (console_col >= CONSOLE_COLS) + console_newline(); - case '\b': console_back(); - return; + return; + case '\b': + console_back(); - default: lcd_putc_xy (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, - c); - if (++console_col >= CONSOLE_COLS) { - console_newline(); - } - return; + return; + default: + lcd_putc_xy(console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, c); + if (++console_col >= CONSOLE_COLS) + console_newline(); } - /* NOTREACHED */ } /*----------------------------------------------------------------------*/ -void lcd_puts (const char *s) +void lcd_puts(const char *s) { if (!lcd_is_enabled) { - serial_puts (s); + serial_puts(s); + return; } while (*s) { - lcd_putc (*s++); + lcd_putc(*s++); } } @@ -211,7 +211,7 @@ void lcd_printf(const char *fmt, ...) /* ** Low-Level Graphics Routines */ /************************************************************************/ -static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) +static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) { uchar *dest; ushort row; @@ -226,7 +226,7 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8); - for (row=0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { + for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { uchar *s = str; int i; #if LCD_BPP == LCD_COLOR16 @@ -239,7 +239,7 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) uchar rest = *d & -(1 << (8-off)); uchar sym; #endif - for (i=0; i<count; ++i) { + for (i = 0; i < count; ++i) { uchar c, bits; c = *s++; @@ -247,18 +247,18 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) #if LCD_BPP == LCD_MONOCHROME sym = (COLOR_MASK(lcd_color_fg) & bits) | - (COLOR_MASK(lcd_color_bg) & ~bits); + (COLOR_MASK(lcd_color_bg) & ~bits); *d++ = rest | (sym >> off); rest = sym << (8-off); #elif LCD_BPP == LCD_COLOR8 - for (c=0; c<8; ++c) { + for (c = 0; c < 8; ++c) { *d++ = (bits & 0x80) ? lcd_color_fg : lcd_color_bg; bits <<= 1; } #elif LCD_BPP == LCD_COLOR16 - for (c=0; c<8; ++c) { + for (c = 0; c < 8; ++c) { *d++ = (bits & 0x80) ? lcd_color_fg : lcd_color_bg; bits <<= 1; @@ -273,14 +273,14 @@ static void lcd_drawchars (ushort x, ushort y, uchar *str, int count) /*----------------------------------------------------------------------*/ -static inline void lcd_puts_xy (ushort x, ushort y, uchar *s) +static inline void lcd_puts_xy(ushort x, ushort y, uchar *s) { lcd_drawchars(x, y, s, strlen((char *)s)); } /*----------------------------------------------------------------------*/ -static inline void lcd_putc_xy (ushort x, ushort y, uchar c) +static inline void lcd_putc_xy(ushort x, ushort y, uchar c) { lcd_drawchars(x, y, &c, 1); } @@ -298,7 +298,7 @@ static int test_colors[N_BLK_HOR*N_BLK_VERT] = { CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN, }; -static void test_pattern (void) +static void test_pattern(void) { ushort v_max = panel_info.vl_row; ushort h_max = panel_info.vl_col; @@ -307,13 +307,13 @@ static void test_pattern (void) ushort v, h; uchar *pix = (uchar *)lcd_base; - printf ("[LCD] Test Pattern: %d x %d [%d x %d]\n", + printf("[LCD] Test Pattern: %d x %d [%d x %d]\n", h_max, v_max, h_step, v_step); /* WARNING: Code silently assumes 8bit/pixel */ - for (v=0; v<v_max; ++v) { + for (v = 0; v < v_max; ++v) { uchar iy = v / v_step; - for (h=0; h<h_max; ++h) { + for (h = 0; h < h_max; ++h) { uchar ix = N_BLK_HOR * iy + (h/h_step); *pix++ = test_colors[ix]; } @@ -335,12 +335,12 @@ int drv_lcd_init (void) lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - lcd_init (lcd_base); /* LCD initialization */ + lcd_init(lcd_base); /* LCD initialization */ /* Device initialization */ - memset (&lcddev, 0, sizeof (lcddev)); + memset(&lcddev, 0, sizeof(lcddev)); - strcpy (lcddev.name, "lcd"); + strcpy(lcddev.name, "lcd"); lcddev.ext = 0; /* No extensions */ lcddev.flags = DEV_FLAGS_OUTPUT; /* Output only */ lcddev.putc = lcd_putc; /* 'putc' function */ @@ -367,35 +367,35 @@ void lcd_clear(void) #elif LCD_BPP == LCD_COLOR8 /* Setting the palette */ - lcd_setcolreg (CONSOLE_COLOR_BLACK, 0, 0, 0); - lcd_setcolreg (CONSOLE_COLOR_RED, 0xFF, 0, 0); - lcd_setcolreg (CONSOLE_COLOR_GREEN, 0, 0xFF, 0); - lcd_setcolreg (CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0); - lcd_setcolreg (CONSOLE_COLOR_BLUE, 0, 0, 0xFF); - lcd_setcolreg (CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF); - lcd_setcolreg (CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF); - lcd_setcolreg (CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA); - lcd_setcolreg (CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); + lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0); + lcd_setcolreg(CONSOLE_COLOR_RED, 0xFF, 0, 0); + lcd_setcolreg(CONSOLE_COLOR_GREEN, 0, 0xFF, 0); + lcd_setcolreg(CONSOLE_COLOR_YELLOW, 0xFF, 0xFF, 0); + lcd_setcolreg(CONSOLE_COLOR_BLUE, 0, 0, 0xFF); + lcd_setcolreg(CONSOLE_COLOR_MAGENTA, 0xFF, 0, 0xFF); + lcd_setcolreg(CONSOLE_COLOR_CYAN, 0, 0xFF, 0xFF); + lcd_setcolreg(CONSOLE_COLOR_GREY, 0xAA, 0xAA, 0xAA); + lcd_setcolreg(CONSOLE_COLOR_WHITE, 0xFF, 0xFF, 0xFF); #endif #ifndef CONFIG_SYS_WHITE_ON_BLACK - lcd_setfgcolor (CONSOLE_COLOR_BLACK); - lcd_setbgcolor (CONSOLE_COLOR_WHITE); + lcd_setfgcolor(CONSOLE_COLOR_BLACK); + lcd_setbgcolor(CONSOLE_COLOR_WHITE); #else - lcd_setfgcolor (CONSOLE_COLOR_WHITE); - lcd_setbgcolor (CONSOLE_COLOR_BLACK); + lcd_setfgcolor(CONSOLE_COLOR_WHITE); + lcd_setbgcolor(CONSOLE_COLOR_BLACK); #endif /* CONFIG_SYS_WHITE_ON_BLACK */ #ifdef LCD_TEST_PATTERN test_pattern(); #else /* set framebuffer to background color */ - memset ((char *)lcd_base, + memset((char *)lcd_base, COLOR_MASK(lcd_getbgcolor()), lcd_line_length*panel_info.vl_row); #endif /* Paint the logo and retrieve LCD base address */ - debug ("[LCD] Drawing the logo...\n"); + debug("[LCD] Drawing the logo...\n"); lcd_console_address = lcd_logo (); console_col = 0; @@ -410,12 +410,12 @@ U_BOOT_CMD( /*----------------------------------------------------------------------*/ -static int lcd_init (void *lcdbase) +static int lcd_init(void *lcdbase) { /* Initialize the lcd controller */ - debug ("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); + debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); - lcd_ctrl_init (lcdbase); + lcd_ctrl_init(lcdbase); lcd_is_enabled = 1; lcd_clear(); lcd_enable (); @@ -442,13 +442,13 @@ static int lcd_init (void *lcdbase) * * Note that this is running from ROM, so no write access to global data. */ -ulong lcd_setmem (ulong addr) +ulong lcd_setmem(ulong addr) { ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; + int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; - debug ("LCD panel info: %d x %d, %d bit/pix\n", - panel_info.vl_col, panel_info.vl_row, NBITS (panel_info.vl_bpix) ); + debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col, + panel_info.vl_row, NBITS(panel_info.vl_bpix)); size = line_length * panel_info.vl_row; @@ -458,21 +458,21 @@ ulong lcd_setmem (ulong addr) /* Allocate pages for the frame buffer. */ addr -= size; - debug ("Reserving %ldk for LCD Framebuffer at: %08lx\n", size>>10, addr); + debug("Reserving %ldk for LCD Framebuffer at: %08lx\n", size>>10, addr); - return (addr); + return addr; } /*----------------------------------------------------------------------*/ -static void lcd_setfgcolor (int color) +static void lcd_setfgcolor(int color) { lcd_color_fg = color; } /*----------------------------------------------------------------------*/ -static void lcd_setbgcolor (int color) +static void lcd_setbgcolor(int color) { lcd_color_bg = color; } @@ -480,7 +480,7 @@ static void lcd_setbgcolor (int color) /*----------------------------------------------------------------------*/ #ifdef NOT_USED_SO_FAR -static int lcd_getfgcolor (void) +static int lcd_getfgcolor(void) { return lcd_color_fg; } @@ -488,7 +488,7 @@ static int lcd_getfgcolor (void) /*----------------------------------------------------------------------*/ -static int lcd_getbgcolor (void) +static int lcd_getbgcolor(void) { return lcd_color_bg; } @@ -499,7 +499,7 @@ static int lcd_getbgcolor (void) /* ** Chipset depending Bitmap / Logo stuff... */ /************************************************************************/ #ifdef CONFIG_LCD_LOGO -void bitmap_plot (int x, int y) +void bitmap_plot(int x, int y) { #ifdef CONFIG_ATMEL_LCD uint *cmap; @@ -517,7 +517,7 @@ void bitmap_plot (int x, int y) volatile cpm8xx_t *cp = &(immr->im_cpm); #endif - debug ("Logo: width %d height %d colors %d cmap %d\n", + debug("Logo: width %d height %d colors %d cmap %d\n", BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS, ARRAY_SIZE(bmp_logo_palette)); @@ -527,9 +527,9 @@ void bitmap_plot (int x, int y) if (NBITS(panel_info.vl_bpix) < 12) { /* Leave room for default color map */ #if defined(CONFIG_CPU_PXA) - cmap = (ushort *)fbi->palette; + cmap = (ushort *) fbi->palette; #elif defined(CONFIG_MPC823) - cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]); + cmap = (ushort *) &(cp->lcd_cmap[BMP_LOGO_OFFSET * sizeof(ushort)]); #elif defined(CONFIG_ATMEL_LCD) cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0)); #else @@ -550,12 +550,12 @@ void bitmap_plot (int x, int y) uint lut_entry; #ifdef CONFIG_ATMEL_LCD_BGR555 lut_entry = ((colreg & 0x000F) << 11) | - ((colreg & 0x00F0) << 2) | - ((colreg & 0x0F00) >> 7); + ((colreg & 0x00F0) << 2) | + ((colreg & 0x0F00) >> 7); #else /* CONFIG_ATMEL_LCD_RGB565 */ lut_entry = ((colreg & 0x000F) << 1) | - ((colreg & 0x00F0) << 3) | - ((colreg & 0x0F00) << 4); + ((colreg & 0x00F0) << 3) | + ((colreg & 0x0F00) << 4); #endif *(cmap + BMP_LOGO_OFFSET) = lut_entry; cmap++; @@ -570,8 +570,8 @@ void bitmap_plot (int x, int y) WATCHDOG_RESET(); - for (i=0; i<BMP_LOGO_HEIGHT; ++i) { - memcpy (fb, bmap, BMP_LOGO_WIDTH); + for (i = 0; i < BMP_LOGO_HEIGHT; ++i) { + memcpy(fb, bmap, BMP_LOGO_WIDTH); bmap += BMP_LOGO_WIDTH; fb += panel_info.vl_col; } @@ -579,8 +579,8 @@ void bitmap_plot (int x, int y) else { /* true color mode */ u16 col16; fb16 = (ushort *)(lcd_base + y * lcd_line_length + x); - for (i=0; i<BMP_LOGO_HEIGHT; ++i) { - for (j=0; j<BMP_LOGO_WIDTH; j++) { + for (i = 0; i < BMP_LOGO_HEIGHT; ++i) { + for (j = 0; j < BMP_LOGO_WIDTH; j++) { col16 = bmp_logo_palette[(bmap[j]-16)]; fb16[j] = ((col16 & 0x000F) << 1) | @@ -630,14 +630,15 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) volatile cpm8xx_t *cp = &(immr->im_cpm); #endif - if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) { - printf ("Error: no valid bmp image at %lx\n", bmp_image); + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { + printf("Error: no valid bmp image at %lx\n", bmp_image); + return 1; } - width = le32_to_cpu (bmp->header.width); - height = le32_to_cpu (bmp->header.height); + width = le32_to_cpu(bmp->header.width); + height = le32_to_cpu(bmp->header.height); bmp_bpix = le16_to_cpu(bmp->header.bit_count); colors = 1 << bmp_bpix; @@ -646,6 +647,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) if ((bpix != 1) && (bpix != 8) && (bpix != 16) && (bpix != 32)) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, bmp_bpix); + return 1; } @@ -654,10 +656,11 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, le16_to_cpu(bmp->header.bit_count)); + return 1; } - debug ("Display-bmp: %d x %d with %d colors\n", + debug("Display-bmp: %d x %d with %d colors\n", (int)width, (int)height, (int)colors); #if !defined(CONFIG_MCC200) @@ -674,7 +677,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) cmap_base = cmap; /* Set color map */ - for (i=0; i<colors; ++i) { + for (i = 0; i < colors; ++i) { bmp_color_table_entry_t cte = bmp->color_table[i]; #if !defined(CONFIG_ATMEL_LCD) ushort colreg = @@ -709,8 +712,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) * specific. */ #if defined(CONFIG_MCC200) - if (bpix==1) - { + if (bpix == 1) { width = ((width + 7) & ~7) >> 3; x = ((x + 7) & ~7) >> 3; pwidth= ((pwidth + 7) & ~7) >> 3; @@ -731,12 +733,12 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) y = max(0, panel_info.vl_row - height + y + 1); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ - if ((x + width)>pwidth) + if ((x + width) > pwidth) width = pwidth - x; - if ((y + height)>panel_info.vl_row) + if ((y + height) > panel_info.vl_row) height = panel_info.vl_row - y; - bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); + bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x * bpix / 8); @@ -806,11 +808,11 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) break; }; - return (0); + return 0; } #endif -static void *lcd_logo (void) +static void *lcd_logo(void) { #ifdef CONFIG_SPLASH_SCREEN char *s; @@ -823,13 +825,15 @@ static void *lcd_logo (void) addr = simple_strtoul (s, NULL, 16); #ifdef CONFIG_SPLASH_SCREEN_ALIGN - if ((s = getenv ("splashpos")) != NULL) { + s = getenv("splashpos"); + if (s != NULL) { if (s[0] == 'm') x = BMP_ALIGN_CENTER; else - x = simple_strtol (s, NULL, 0); + x = simple_strtol(s, NULL, 0); - if ((s = strchr (s + 1, ',')) != NULL) { + s = strchr(s + 1, ','); + if (s != NULL) { if (s[1] == 'm') y = BMP_ALIGN_CENTER; else @@ -842,15 +846,14 @@ static void *lcd_logo (void) bmp_image_t *bmp = (bmp_image_t *)addr; unsigned long len; - if (!((bmp->header.signature[0]=='B') && - (bmp->header.signature[1]=='M'))) { + if (!((bmp->header.signature[0] == 'B') && + (bmp->header.signature[1] == 'M'))) { addr = (ulong)gunzip_bmp(addr, &len); } #endif - if (lcd_display_bitmap (addr, x, y) == 0) { - return ((void *)lcd_base); - } + if (lcd_display_bitmap(addr, x, y) == 0) + return (void *)lcd_base; } #endif /* CONFIG_SPLASH_SCREEN */ @@ -863,9 +866,9 @@ static void *lcd_logo (void) #endif /* CONFIG_LCD_INFO */ #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) - return ((void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length)); + return (void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length); #else - return ((void *)lcd_base); + return (void *)lcd_base; #endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */ } diff --git a/common/usb.c b/common/usb.c index c80155ce76..1b40228b28 100644 --- a/common/usb.c +++ b/common/usb.c @@ -188,7 +188,8 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, request, requesttype, value, index, size); dev->status = USB_ST_NOT_PROC; /*not yet processed */ - submit_control_msg(dev, pipe, data, size, setup_packet); + if (submit_control_msg(dev, pipe, data, size, setup_packet) < 0) + return -1; if (timeout == 0) return (int)size; @@ -220,7 +221,8 @@ int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, if (len < 0) return -1; dev->status = USB_ST_NOT_PROC; /*not yet processed */ - submit_bulk_msg(dev, pipe, data, len); + if (submit_bulk_msg(dev, pipe, data, len) < 0) + return -1; while (timeout--) { if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC)) break; @@ -799,12 +801,13 @@ int usb_new_device(struct usb_device *dev) dev->epmaxpacketin[0] = 8; dev->epmaxpacketout[0] = 8; - err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8); + err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, tmpbuf, 8); if (err < 8) { printf("\n USB device not responding, " \ "giving up (status=%lX)\n", dev->status); return 1; } + memcpy(&dev->descriptor, tmpbuf, 8); #else /* This is a Windows scheme of initialization sequence, with double * reset of the device (Linux uses the same sequence) @@ -893,7 +896,7 @@ int usb_new_device(struct usb_device *dev) tmp = sizeof(dev->descriptor); err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, - &dev->descriptor, sizeof(dev->descriptor)); + tmpbuf, sizeof(dev->descriptor)); if (err < tmp) { if (err < 0) printf("unable to get device descriptor (error=%d)\n", @@ -903,6 +906,7 @@ int usb_new_device(struct usb_device *dev) "(expected %i, got %i)\n", tmp, err); return 1; } + memcpy(&dev->descriptor, tmpbuf, sizeof(dev->descriptor)); /* correct le values */ le16_to_cpus(&dev->descriptor.bcdUSB); le16_to_cpus(&dev->descriptor.idVendor); diff --git a/common/usb_storage.c b/common/usb_storage.c index faad23706f..bdc306f587 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -150,12 +150,17 @@ struct us_data { unsigned int irqpipe; /* pipe for release_irq */ unsigned char irqmaxp; /* max packed for irq Pipe */ unsigned char irqinterval; /* Intervall for IRQ Pipe */ - unsigned long max_xfer_blk; /* Max blocks per xfer */ ccb *srb; /* current srb */ trans_reset transport_reset; /* reset routine */ trans_cmnd transport; /* transport routine */ }; +/* + * The U-Boot EHCI driver cannot handle more than 5 page aligned buffers + * of 4096 bytes in a transfer without running itself out of qt_buffers + */ +#define USB_MAX_XFER_BLK(start, blksz) (((4096 * 5) - (start % 4096)) / blksz) + static struct us_data usb_stor[USB_MAX_STOR_DEV]; @@ -1041,7 +1046,7 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor, unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer) { - unsigned long start, blks, buf_addr; + unsigned long start, blks, buf_addr, max_xfer_blk; unsigned short smallblks; struct usb_device *dev; struct us_data *ss; @@ -1083,12 +1088,14 @@ unsigned long usb_stor_read(int device, unsigned long blknr, /* XXX need some comment here */ retry = 2; srb->pdata = (unsigned char *)buf_addr; - if (blks > ss->max_xfer_blk) - smallblks = ss->max_xfer_blk; + max_xfer_blk = USB_MAX_XFER_BLK(buf_addr, + usb_dev_desc[device].blksz); + if (blks > max_xfer_blk) + smallblks = (unsigned short) max_xfer_blk; else smallblks = (unsigned short) blks; retry_it: - if (smallblks == ss->max_xfer_blk) + if (smallblks == max_xfer_blk) usb_show_progress(); srb->datalen = usb_dev_desc[device].blksz * smallblks; srb->pdata = (unsigned char *)buf_addr; @@ -1109,7 +1116,7 @@ retry_it: start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ - if (blkcnt >= ss->max_xfer_blk) + if (blkcnt >= max_xfer_blk) debug("\n"); return blkcnt; } @@ -1117,7 +1124,7 @@ retry_it: unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer) { - unsigned long start, blks, buf_addr; + unsigned long start, blks, buf_addr, max_xfer_blk; unsigned short smallblks; struct usb_device *dev; struct us_data *ss; @@ -1162,12 +1169,14 @@ unsigned long usb_stor_write(int device, unsigned long blknr, */ retry = 2; srb->pdata = (unsigned char *)buf_addr; - if (blks > ss->max_xfer_blk) - smallblks = ss->max_xfer_blk; + max_xfer_blk = USB_MAX_XFER_BLK(buf_addr, + usb_dev_desc[device].blksz); + if (blks > max_xfer_blk) + smallblks = (unsigned short) max_xfer_blk; else smallblks = (unsigned short) blks; retry_it: - if (smallblks == ss->max_xfer_blk) + if (smallblks == max_xfer_blk) usb_show_progress(); srb->datalen = usb_dev_desc[device].blksz * smallblks; srb->pdata = (unsigned char *)buf_addr; @@ -1188,7 +1197,7 @@ retry_it: start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ - if (blkcnt >= ss->max_xfer_blk) + if (blkcnt >= max_xfer_blk) debug("\n"); return blkcnt; @@ -1415,12 +1424,6 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, USB_STOR_PRINTF(" address %d\n", dev_desc->target); USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type); - /* - * The U-Boot EHCI driver cannot handle more than 4096 * 5 bytes in a - * transfer without running itself out of qt_buffers. - */ - ss->max_xfer_blk = (4096 * 5) / dev_desc->blksz; - init_part(dev_desc); USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type); @@ -205,6 +205,10 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) CPPFLAGS += -DCONFIG_SPL_TEXT_BASE=$(CONFIG_SPL_TEXT_BASE) endif +ifneq ($(CONFIG_SPL_PAD_TO),) +CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO) +endif + ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -DCONFIG_SPL_BUILD endif diff --git a/doc/README.OXC b/doc/README.OXC deleted file mode 100644 index c5db5f8859..0000000000 --- a/doc/README.OXC +++ /dev/null @@ -1,24 +0,0 @@ -This document contains different information about the port -of U-Boot for the OXC board designed by Lucent Technologies, -Inc. - -1. Showing activity - -U-Boot for the OXC board can show its current status using -the Active LED. This feature is configured by the following -options: - -CONFIG_SHOW_ACTIVITY - - When this option is on, the Active LED is blinking fast -when U-Boot runs in the idle loop (i.e. waits for user -commands from serial console) and blinking slow when it -downloads an image over network. When U-Boot loads an image -over serial line the Active LED does not blink and its state -is random (i.e. either constant on or constant off). - -CONFIG_SHOW_BOOT_PROGRESS - - When this option is on, U-Boot switches the Active LED -off before booting an image and switches it on if booting -failed due to some reasons. diff --git a/doc/README.Sandpoint8240 b/doc/README.Sandpoint8240 deleted file mode 100644 index fa846dc33e..0000000000 --- a/doc/README.Sandpoint8240 +++ /dev/null @@ -1,394 +0,0 @@ -The port was tested on a Sandpoint 8240 X3 board, with U-Boot -installed in the flash memory of the CPU card. Please use the -following DIP switch settings: - -Motherboard: - -SW1.1: on SW1.2: on SW1.3: on SW1.4: on -SW1.5: on SW1.6: on SW1.7: on SW1.8: on - -SW2.1: on SW2.2: on SW2.3: on SW2.4: on -SW2.5: on SW2.6: on SW2.7: on SW2.8: on - - -CPU Card: - -SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on -SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF - -SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF -SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on - - -The followind detailed description of installation and initial steps -with U-Boot and QNX was provided by Jim Sandoz <sandoz@lucent.com>: - - -Directions for installing U-Boot on Sandpoint+Unity8240 -using the Abatron BDI2000 BDM/JTAG debugger ... - -Background and Reference info: -http://u-boot.sourceforge.net/ -http://www.abatron.ch/ -http://www.abatron.ch/BDI/bdihw.html -http://www.abatron.ch/DataSheets/BDI2000.pdf -http://www.abatron.ch/Manuals/ManGdbCOP-2000C.pdf -http://e-www.motorola.com/collateral/SPX3UM.pdf -http://e-www.motorola.com/collateral/UNITYX4CONFIG.pdf - - -Connection Diagram: - =========== - === ===== |----- | -| | <---------------> | | | | | -|PC | rs232 | BDI |=============[] | | -| | |2000 | BDM probe | | | -| | <---------------> | | |----- | - === ethernet ===== | | - | | - =========== - Sandpoint X3 with - Unity 8240 proc - - -PART 1) - DIP Switch Settings: - -Sandpoint X3 8240 processor board DIP switch settings, with -U-Boot to be installed in the flash memory of the CPU card: - -Motorola Sandpoint X3 Motherboard: -SW1.1: on SW1.2: on SW1.3: on SW1.4: on -SW1.5: on SW1.6: on SW1.7: on SW1.8: on -SW2.1: on SW2.2: on SW2.3: on SW2.4: on -SW2.5: on SW2.6: on SW2.7: on SW2.8: on - -Motorola Unity 8240 CPU Card: -SW2.1: OFF SW2.2: OFF SW2.3: on SW2.4: on -SW2.5: OFF SW2.6: OFF SW2.7: OFF SW2.8: OFF -SW3.1: OFF SW3.2: on SW3.3: OFF SW3.4: OFF -SW3.5: on SW3.6: OFF SW3.7: OFF SW3.8: on - - -PART 2) - Connect the BDI2000 Cable to the Sandpoint/Unity 8240: - -BDM Pin 1 on the Unity 8240 processor board is towards the -PCI PMC connectors, or away from the socketed SDRAM, i.e.: - - ==================== - | ---------------- | - | | SDRAM | | - | | | | - | ---------------- | - | |~| | - | |B| ++++++ | - | |D| + uP + | - | |M| +8240+ | - | ~ 1 ++++++ | - | | - | | - | | - | PMC conn ====== | - | ===== ====== | - | | - ==================== - - -PART 3) - Setting up the BDI2000, and preparing for TCP/IP network comms: - -Connect the BDI2000 to the PC using the supplied serial cable. -Download the BDI2000 software and install it using setup.exe. - -[Note: of course you can also use the Linux command line tool -"bdisetup" to configure your BDI2000 - the sources are included on -the floppy disk that comes with your BDI2000. Just in case you don't -have any Windows PC's - like me :-) -- wd ] - -Power up the BDI2000; then follow directions to assign the IP -address and related network information. Note that U-Boot -will be loaded to the Sandpoint via tftp. You need to either -use the Abatron-provided tftp application or provide a tftp -server (e.g. Linux/Solaris/*BSD) somewhere on your network. -Once the IP address etc are assigned via the RS232 port, -further communication with the BDI2000 will happen via the -ethernet connection. - -PART 4) - Making a TCP/IP network connection to the Abatron BDI2000: - -Telnet to the Abatron BDI2000. Assuming that all of the -networking info was loaded via RS232 correctly, you will see -the following (scrolling): - -- TARGET: waiting for target Vcc -- TARGET: waiting for target Vcc - - -PART 5) - Power up the target Sandpoint: -If the BDM connections are correct, the following will now appear: - -- TARGET: waiting for target Vcc -- TARGET: waiting for target Vcc -- TARGET: processing power-up delay -- TARGET: processing user reset request -- BDI asserts HRESET -- Reset JTAG controller passed -- Bypass check: 0x55 => 0xAA -- Bypass check: 0x55 => 0xAA -- JTAG exists check passed -- Target PVR is 0x00810101 -- COP status is 0x01 -- Check running state passed -- BDI scans COP freeze command -- BDI removes HRESET -- COP status is 0x05 -- Check stopped state passed -- Check LSRL length passed -- BDI sets breakpoint at 0xFFF00100 -- BDI resumes program execution -- Waiting for target stop passed -- TARGET: Target PVR is 0x00810101 -- TARGET: reseting target passed -- TARGET: processing target startup .... -- TARGET: processing target startup passed -BDI> - - -PART 6) - Erase the current contents of the flash memory: - -BDI>era 0xFFF00000 - Erasing flash at 0xfff00000 - Erasing flash passed -BDI>era 0xFFF04000 - Erasing flash at 0xfff04000 - Erasing flash passed -BDI>era 0xFFF06000 - Erasing flash at 0xfff06000 - Erasing flash passed -BDI>era 0xFFF08000 - Erasing flash at 0xfff08000 - Erasing flash passed -BDI>era 0xFFF10000 - Erasing flash at 0xfff10000 - Erasing flash passed -BDI>era 0xFFF20000 - Erasing flash at 0xfff20000 - Erasing flash passed - - -PART 7) - Program the flash memory with the U-Boot image: - -BDI>prog 0xFFF00000 u-boot.bin bin - Programming u-boot.bin , please wait .... - Programming flash passed - - -PART 8) - Connect PC to Sandpoint: -Using a crossover serial cable, attach the PC serial port to the -Sandpoint's COM1. Set communications parameters to 8N1 / 9600 baud. - - -PART 9) - Reset the Unity and begin U-Boot execution: - -BDI>reset -- TARGET: processing user reset request -- TARGET: Target PVR is 0x00810101 -- TARGET: reseting target passed -- TARGET: processing target init list .... -- TARGET: processing target init list passed - -BDI>go - -Now see output from U-Boot running, sent via serial port: - -U-Boot 1.1.4 (Jan 23 2002 - 18:29:19) - -CPU: MPC8240 Revision 1.1 at 264 MHz: 16 kB I-Cache 16 kB D-Cache -Board: Sandpoint 8240 Unity -DRAM: 64 MB -FLASH: 2 MB -PCI: scanning bus0 ... - bus dev fn venID devID class rev MBAR0 MBAR1 IPIN ILINE - 00 00 00 1057 0003 060000 13 00000008 00000000 01 00 - 00 0b 00 10ad 0565 060100 10 00000000 00000000 00 00 - 00 0f 00 8086 1229 020000 08 80000000 80000001 01 00 -In: serial -Out: serial -Err: serial -=> - - -PART 10) - Set and save any required environmental variables, examples of some: - -=> setenv ethaddr 00:03:47:97:D0:79 -=> setenv bootfile your_qnx_image_here -=> setenv hostname sandpointX -=> setenv netmask 255.255.255.0 -=> setenv ipaddr 192.168.0.11 -=> setenv serverip 192.168.0.10 -=> setenv gatewayip=192.168.0.1 -=> saveenv -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> - -**** Example environment: **** - -=> printenv -baudrate=9600 -bootfile=telemetry -hostname=sp1 -ethaddr=00:03:47:97:E4:6B -load=tftp 100000 u-boot.bin -update=protect off all;era FFF00000 FFF3FFFF;cp.b 100000 FFF00000 ${filesize};saveenv -filesize=1f304 -gatewayip=145.17.228.1 -netmask=255.255.255.0 -ipaddr=145.17.228.42 -serverip=145.17.242.46 -stdin=serial -stdout=serial -stderr=serial - -Environment size: 332/8188 bytes -=> - -here's some text useful stuff for cut-n-paste: -setenv hostname sandpoint1 -setenv netmask 255.255.255.0 -setenv ipaddr 145.17.228.81 -setenv serverip 145.17.242.46 -setenv gatewayip 145.17.228.1 -saveenv - -PART 11) - Test U-Boot by tftp'ing new U-Boot, overwriting current: - -=> protect off all -Un-Protect Flash Bank # 1 -=> tftp 100000 u-boot.bin -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 127628 (1f28c hex) -=> era all -Erase Flash Bank # 1 - done -Erase Flash Bank # 2 - missing -=> cp.b 0x100000 FFF00000 1f28c -Copy to Flash... done -=> saveenv -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> reset - -You can put these commands into some environment variables; - -=> setenv load tftp 100000 u-boot.bin -=> setenv update protect off all\;era FFF00000 FFF3FFFF\;cp.b 100000 FFF00000 \${filesize}\;saveenv -=> saveenv - -Then you just have to type "run load" then "run update" - -=> run load -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'u-boot.bin'. -Load address: 0x100000 -Loading: ######################### -done -Bytes transferred = 127748 (1f304 hex) -=> run update -Un-Protect Flash Bank # 1 -Un-Protect Flash Bank # 2 -Erase Flash from 0xfff00000 to 0xfff3ffff - done -Erased 7 sectors -Copy to Flash... done -Saving Environment to Flash... -Un-Protected 1 sectors -Erasing Flash... - done -Erased 1 sectors -Writing to Flash... done -Protected 1 sectors -=> - - -PART 12) - Load OS image (ELF format) via U-Boot using tftp - - -=> tftp 800000 sandpoint-simple.elf -eth: Intel i82559 PCI EtherExpressPro @0x80000000(bus=0, device=15, func=0) -ARP broadcast 1 -TFTP from server 145.17.242.46; our IP address is 145.17.228.42; sending through - gateway 145.17.228.1 -Filename 'sandpoint-simple.elf'. -Load address: 0x800000 -Loading: ################################################################# - ################################################################# - ################################################################# - ######################## -done -Bytes transferred = 1120284 (11181c hex) -==> - -PART 13) - Begin OS image execution: (note that unless you have the -serial parameters of your OS image set to 9600 (i.e. same as -the U-Boot binary) you will get garbage here until you change -the serial communications speed. - -=> bootelf 800000 -Loading @ 0x001f0100 (1120028 bytes) -## Starting application at 0x001f1d28 ... -Replace init_hwinfo() with a board specific version - -Loading QNX6.... - -Header size=0x0000009c, Total Size=0x000005c0, #Cpu=1, Type=1 -<...loader and kernel messages snipped...> - -Welcome to Neutrino on the Sandpoint -# - - -other information: - -CVS Retrieval Notes: - -U-Boot's SourceForge CVS repository can be checked out -through anonymous (pserver) CVS with the following -instruction set. The module you wish to check out must -be specified as the modulename. When prompted for a -password for anonymous, simply press the Enter key. - -cvs -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot login - -cvs -z6 -d:pserver:anonymous@cvs.u-boot.sourceforge.net:/cvsroot/u-boot co -P u-boot diff --git a/doc/README.amigaone b/doc/README.amigaone deleted file mode 100644 index 9975977917..0000000000 --- a/doc/README.amigaone +++ /dev/null @@ -1,12 +0,0 @@ -AmigaOne U-Boot and the SciTech emulator - -The directory board/MAI/bios_emulator contains the source code -of the SciTech x86 emulator. This emulator is normally available -under a BSD license. However, SciTech kindly gave us permission -to use their emulator in PPCBoot for the AmigaOne. It's available -in this form only under GPL. - -Thanks to Kendall Bennett and the rest of the team at SciTech. -See http://www.scitechsoft.com for their web site - -The GPL license can be found at http://www.gnu.org/licenses/gpl.html diff --git a/doc/README.enetaddr b/doc/README.enetaddr index 2d8e24f5cb..1eaeaf9416 100644 --- a/doc/README.enetaddr +++ b/doc/README.enetaddr @@ -32,7 +32,11 @@ Correct flow of setting up the MAC address (summarized): 1. Read from hardware in initialize() function 2. Read from environment in net/eth.c after initialize() -3. Give priority to the value in the environment if a conflict +3. The environment variable will be compared to the driver initialized + struct eth_device->enetaddr. If they differ, a warning is printed, and the + environment variable will be used unchanged. + If the environment variable is not set, it will be initialized from + eth_device->enetaddr, and a warning will be printed. 4. Program the address into hardware if the following conditions are met: a) The relevant driver has a 'write_addr' function b) The user hasn't set an 'ethmacskip' environment variable diff --git a/doc/README.link-local b/doc/README.link-local index e623e5659f..9586eca269 100644 --- a/doc/README.link-local +++ b/doc/README.link-local @@ -73,4 +73,3 @@ If both fail or are disabled, static settings are used. "setenv netmask $snetmask; " \ "setenv gatewayip $sgatewayip; " \ "fi;\0" \ - diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx new file mode 100644 index 0000000000..5a4b591a89 --- /dev/null +++ b/doc/README.mpc85xx @@ -0,0 +1,166 @@ +External Debug Support +---------------------- + +Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some +restrictions on external debugging (JTAG). In particular, for the debugger to +be able to receive control after a single step or breakpoint: + - MSR[DE] must be set + - A valid opcode must be fetchable, through the MMU, from the debug + exception vector (IVPR + IVOR15). + +To maximize the time during which this requirement is met, U-Boot sets MSR[DE] +immediately on entry and keeps it set. It also uses a temporary TLB to keep a +mapping to a valid opcode at the debug exception vector, even if we normally +don't support exception vectors being used that early, and that's not the area +where U-Boot currently executes from. + +Note that there may still be some small windows where debugging will not work, +such as in between updating IVPR and IVOR15. + +Config Switches: +---------------- + +Please refer README section "MPC85xx External Debug Support" + +Major Config Switches during various boot Modes +---------------------------------------------- + +NOR boot + !defined(CONFIG_SYS_RAMBOOT) +NOR boot Secure + !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +RAMBOOT(SD, SPI & NAND boot) + defined(CONFIG_SYS_RAMBOOT) +RAMBOOT Secure (SD, SPI & NAND) + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +NAND SPL BOOT + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) + + +TLB Entries during u-boot execution +----------------------------------- + +Note: Sequence number is in order of execution + +A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot + + 1) TLB entry to overcome e500 v1/v2 debug restriction + Location : Label "_start_e500" + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE + Properties : 256K, AS0, I, IPROT + + 2) TLB entry for working in AS1 + Location : Label "create_init_ram_area" + TLB Entry : 15 + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE + Properties : 1M, AS1, I, G, IPROT + + 3) TLB entry for the stack during AS1 + Location : Lable "create_init_ram_area" + TLB Entry : 14 + EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + Properties : 16K, AS1, IPROT + + 4) TLB entry for CCSRBAR during AS1 execution + Location : cpu_init_early_f + TLB Entry : 13 + EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + Properties : 1M, AS1, I, G + + 5) Invalidate unproctected TLB Entries + Location : cpu_init_early_f + Invalidated: 13 + + 6) Create TLB entries as per boards/freescale/<board>/tlb.c + Location : cpu_init_early_f --> init_tlbs() + Properties : ..., AS0, ... + Please note It can overwrites previous TLB Entries. + + 7) Disable TLB Entries of AS1 + Location : cpu_init_f --> disable_tlb() + Disable : 15, 14 + + 8) Update Flash's TLB entry + Location : Board_init_r + TLB entry : Search from TLB entries + EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + Properties : Board specific size, AS0, I, G, IPROT + + +B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot + + 1) TLB entry to overcome e500 v1/v2 debug restriction + Location : Label "_start_e500" + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB +#if defined(CONFIG_SECURE_BOOT) + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + Properties : 1M, AS1, I, G, IPROT +#else + EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 + Properties : 4M, AS0, I, G, IPROT +#endif + + 2) TLB entry for working in AS1 + Location : Label "create_init_ram_area" + TLB Entry : 15 +#if defined(CONFIG_SECURE_BOOT) + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + Properties : 1M, AS1, I, G, IPROT +#else + EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 + Properties : 4M, AS1, I, G, IPROT +#endif + + 3) TLB entry for the stack during AS1 + Location : Lable "create_init_ram_area" + TLB Entry : 14 + EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + Properties : 16K, AS1, IPROT + + 4) TLB entry for CCSRBAR during AS1 execution + Location : cpu_init_early_f + TLB Entry : 13 + EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + Properties : 1M, AS1, I, G + + 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 + Location : cpu_init_early_f + TLB Entry : 9 + EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR + Properties : 1M, AS1, I + + 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr + Location : cpu_init_early_f --> setup_ifc + TLB Entry : Get Flash TLB + EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys + Properties : 4M, AS1, I, G, IPROT + + 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction + Location : cpu_init_early_f --> setup_ifc + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB + EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys + Properties : 4M, AS0, I, G, IPROT + + 8) Invalidate unproctected TLB Entries + Location : cpu_init_early_f + Invalidated: 13, 9 + + 9) Create TLB entries as per boards/freescale/<board>/tlb.c + Location : cpu_init_early_f --> init_tlbs() + Properties : ..., AS0, ... + Note: It can overwrites previous TLB Entries + + 10) Disable TLB Entries of AS1 + Location : cpu_init_f --> disable_tlb() + Disable : 15, 14 + + 11) Create DDR's TLB entriy + Location : Board_init_f -> init_func_ram -> initdram + TLB entry : Search free TLB entry + + 12) Update Flash's TLB entry + Location : Board_init_r + TLB entry : Search from TLB entries + EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + Properties : Board specific size, AS0, I, G, IPROT diff --git a/doc/README.mx28_common b/doc/README.mx28_common index 448d221162..8bacaf8a5e 100644 --- a/doc/README.mx28_common +++ b/doc/README.mx28_common @@ -19,6 +19,7 @@ Contents 1) Prerequisites 2) Compiling U-Boot for a MX28 based board 3) Installation of U-Boot for a MX28 based board to SD card +4) Installation of U-Boot into NAND flash 1) Prerequisites ---------------- @@ -29,14 +30,14 @@ is the "mxsboot" tool found in U-Boot source tree. Firstly, obtain the elftosb archive from the following location: - http://foss.doredevelopment.dk/mirrors/imx/elftosb-10.12.01.tar.gz + ftp://ftp.denx.de/pub/tools/elftosb-10.12.01.tar.gz We use a $VER variable here to denote the current version. At the time of writing of this document, that is "10.12.01". To obtain the file from command line, use: $ VER="10.12.01" - $ wget http://foss.doredevelopment.dk/mirrors/imx/elftosb-${VER}.tar.gz + $ wget ftp://ftp.denx.de/pub/tools/elftosb-${VER}.tar.gz Extract the file: @@ -146,8 +147,8 @@ NOTE: If the user needs to adjust the start sector, the "mxsboot" tool contains a "-p" switch for that purpose. The "-p" switch takes the sector number as an argument. -4) Installation of U-Boot for NAND flash ------------------------------------------------ +4) Installation of U-Boot into NAND flash +----------------------------------------- To boot a MX28 based board from NAND, set the boot mode DIP switches according to i.MX28 manual chapter 12.2.1 (Table 12-2), PORT=GPMI, NAND 1.8 V. diff --git a/doc/README.mx28evk b/doc/README.mx28evk index c6c3d37830..571dfdab8d 100644 --- a/doc/README.mx28evk +++ b/doc/README.mx28evk @@ -17,7 +17,7 @@ Jumper configuration To boot MX28EVK from an SD card, set the boot mode DIP switches as: * Boot Mode Select: 1 0 0 1 (Boot from SD card Slot 0 - U42) - * JTAG PSWITCH RESET: To the left (reset enabled) + * JTAG PSWITCH RESET: To the right (reset disabled) * Battery Source: Down * Wall 5V: Up * VDD 5V: To the left (off) diff --git a/doc/README.p4080ds b/doc/README.p4080ds deleted file mode 100644 index 3ed59a8cff..0000000000 --- a/doc/README.p4080ds +++ /dev/null @@ -1,32 +0,0 @@ -Overview --------- -The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC. - -SerDes hwconfig configuration ------------------------------ -The P4080 RCW includes three sets of bits the specify which SerDes lanes -should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two), -and SRDS_LPD_B3 (for bank three). Each of these contains four bits, one for -each lane in the bank. SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and -SRDS_LPD_B3 be set to 0b1111. This forces banks two and three to be powered -down at reset. - -To re-enable these banks in U-Boot, two hwconfig are available: -"fsl_srds_lpd_b2" and "fsl_srds_lpd_b3". The value passed via fsl_srds_lpd_b2 -is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into -SRDS_LPD_B3. Each bit represents one of each bank, and a value of '1' -indicates that the lane should be powered down. - -For example, to indicate that both SerDes banks 2 and 3 are powered down, add -the following to hwconfig: - - serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf - -The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant -bit corresponds to lane A. To indicate that just lane A of bank 3 is to be -powered down, use: - - serdes:fsl_srds_lpd_b3=8 - -These options should be specified only if U-Boot does not automatically power -on the correct lanes. diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips deleted file mode 100644 index e6a3855738..0000000000 --- a/doc/README.qemu_mips +++ /dev/null @@ -1,164 +0,0 @@ - -Notes for the Qemu MIPS port - -I) Example usage: - -# ln -s u-boot.bin mips_bios.bin -start it: -qemu-system-mips -L . /dev/null -nographic - -or - -if you use a qemu version after commit 4224 - -create image: -# dd of=flash bs=1k count=4k if=/dev/zero -# dd of=flash bs=1k conv=notrunc if=u-boot.bin -start it: -# qemu-system-mips -M mips -pflash flash -monitor null -nographic - -2) Download kernel + initrd - -On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/ -you can downland - -#config to build the kernel -qemu_mips_defconfig -#patch to fix mips interrupt init on 2.6.24.y kernel -qemu_mips_kernel.patch -initrd.gz -vmlinux -vmlinux.bin -System.map - -4) Generate uImage - -# tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage - -5) Copy uImage to Flash -# dd if=uImage bs=1k conv=notrunc seek=224 of=flash - -6) Generate Ide Disk - -# dd of=ide bs=1k cout=100k if=/dev/zero - -# sfdisk -C 261 -d ide -# partition table of ide -unit: sectors - - ide1 : start= 63, size= 32067, Id=83 - ide2 : start= 32130, size= 32130, Id=83 - ide3 : start= 64260, size= 4128705, Id=83 - ide4 : start= 0, size= 0, Id= 0 - -7) Copy to ide - -# dd if=uImage bs=512 conv=notrunc seek=63 of=ide - -8) Generate ext2 on part 2 on Copy uImage and initrd.gz - -# Attached as loop device ide offset = 32130 * 512 -# losetup -o 16450560 -f ide -# Format as ext2 ( arg2 : nb blocks) -# mke2fs /dev/loop0 16065 -# losetup -d /dev/loop0 -# Mount and copy uImage and initrd.gz to it -# mount -o loop,offset=16450560 -t ext2 ide /mnt -# mkdir /mnt/boot -# cp {initrd.gz,uImage} /mnt/boot/ -# Umount it -# umount /mnt - -9) Set Environment - -setenv rd_start 0x80800000 -setenv rd_size 2663940 -setenv kernel BFC38000 -setenv oad_addr 80500000 -setenv load_addr2 80F00000 -setenv kernel_flash BFC38000 -setenv load_addr_hello 80200000 -setenv bootargs 'root=/dev/ram0 init=/bin/sh' -setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz' -setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz' -setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2' -setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage' -setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage' -setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}' -setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}' -setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}' -setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}' -setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}' -setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}' -setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}' -setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}' -setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin' -setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}' -setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}' -setenv bootcmd 'run boot_tftp_flash' - -10) Now you can boot from flash, ide, ide+ext2 and tfp - -# qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide - -II) How to debug U-Boot - -In order to debug U-Boot you need to start qemu with gdb server support (-s) -and waiting the connection to start the CPU (-S) - -# qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide - -in an other console you start gdb - -1) Debugging of U-Boot Before Relocation - -Before relocation, the addresses in the ELF file can be used without any problems -by connecting to the gdb server localhost:1234 - -# mipsel-unknown-linux-gnu-gdb u-boot -GNU gdb 6.6 -Copyright (C) 2006 Free Software Foundation, Inc. -GDB is free software, covered by the GNU General Public License, and you are -welcome to change it and/or distribute copies of it under certain conditions. -Type "show copying" to see the conditions. -There is absolutely no warranty for GDB. Type "show warranty" for details. -This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"... -(gdb) target remote localhost:1234 -Remote debugging using localhost:1234 -_start () at start.S:64 -64 RVECENT(reset,0) /* U-boot entry point */ -Current language: auto; currently asm -(gdb) b board.c:289 -Breakpoint 1 at 0xbfc00cc8: file board.c, line 289. -(gdb) c -Continuing. - -Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290 -290 relocate_code (addr_sp, id, addr); -Current language: auto; currently c -(gdb) p/x addr -$1 = 0x87fa0000 - -2) Debugging of U-Boot After Relocation - -For debugging U-Boot after relocation we need to know the address to which -U-Boot relocates itself to 0x87fa0000 by default. -And replace the symbol table to this offset. - -(gdb) symbol-file -Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y -Error in re-setting breakpoint 1: -No symbol table is loaded. Use the "file" command. -No symbol file now. -(gdb) add-symbol-file u-boot 0x87fa0000 -add symbol table from file "u-boot" at - .text_addr = 0x87fa0000 -(y or n) y -Reading symbols from /private/u-boot-arm/u-boot...done. -Breakpoint 1 at 0x87fa0cc8: file board.c, line 289. -(gdb) c -Continuing. - -Program received signal SIGINT, Interrupt. -0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78 -78 while ((tmo - read_c0_count()) < 0x7fffffff) diff --git a/doc/README.spear b/doc/README.spear index a8b1052449..0789b3fd27 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -6,9 +6,10 @@ SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic The SPEAr SoC family embeds a customizable logic that can be programmed one-time by a customer at silicon mask level (i.e. not at runtime!). -We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx. +U-Boot supports four SoCs: SPEAr600, SPEAr3xx -All 4 SoCs share common peripherals. +All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. SPEAr300 and +SPEAr600 do not have EMI. 1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux) 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) @@ -22,7 +23,7 @@ All 4 SoCs share common peripherals. 10. others .. Everything is supported in Linux. -u-boot is not currently supporting all peripeharls (just a few as listed below). +u-boot is currently not supporting all peripeharls (just a few as listed below). 1. USB Device 2. NAND controller (FSMC) 3. Serial Memory Interface @@ -31,18 +32,43 @@ u-boot is not currently supporting all peripeharls (just a few as listed below). 5. UART Build options - make spear600_config + make spear320_config + spear320 build with environment variables placed at default + location i.e. Serial NOR device + make spear320_pnor_config + This option generates a uboot image that supports emi controller + for CFI compliant parallel NOR flash. Environment variables are + placed in Parallel NOR device + make spear320_nand_config + spear320 build with environment variables placed in NAND device + make spear320_usbtty_config + spear320 build with usbtty terminal as default and environment + placed at default location + make spear320_usbtty_pnor_config + spear320 build with usbtty terminal as default and environment + placed in pnor device + make spear320_usbtty_nand_config + Build with usbtty terminal as default and environment placed in + NAND device make spear300_config + make spear300_nand_config + make spear300_usbtty_config + make spear300_usbtty_nand_config make spear310_config - make spear320_config - -Further options - make ENV=NAND (supported by all 4 SoCs) - - This option generates a uboot image that saves environment inn NAND + make spear310_pnor_config + make spear310_nand_config + make spear310_usbtty_config + make spear310_usbtty_pnor_config + make spear310_usbtty_nand_config + make spear600_config + make spear600_nand_config + make spear600_usbtty_config + make spear600_usbtty_nand_config - make CONSOLE=USB (supported by all 4 SoCs) - - This option generates a uboot image for using usbdevice as a tty i/f +Mac id storage and retrieval in spear platforms - make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - - This option generates a uboot image that supports emi controller for - CFI compliant parallel NOR flash +Please read doc/README.enetaddr for the implementation guidelines for mac id +usage. Basically, environment has precedence over board specific storage. The +ethaddr beeing used for the network interface is always taken only from +environment variables. Although, we can check the mac id programmed in i2c +memory by using chip_config command diff --git a/doc/README.switch_config b/doc/README.switch_config new file mode 100644 index 0000000000..f8903738e1 --- /dev/null +++ b/doc/README.switch_config @@ -0,0 +1,25 @@ +On the enbw_cmc board is a KSZ8864RMN switch which needs +configured through spi before working. This is done on +startup from u-boot through a config file stored at an +address specified in the "hwconfig" environment variable, +subcommand "config". + +For example on the enbw_cmc board: + +hwconfig=switch:lan=on,pwl=off,config=0x60160000 + +The file has the following structure: + +- a comment starts with a '#' or a ';' and ends with a newline +- The switch needs for its config a reg/value pair, so we + have two columns in the file: + reg : contains the register address + value: contains a 8 bit register value + This 2 columns are seperated through space or tab. + +example (minimal configuration on the enbw_cmc board): + +;reg value comment +;----------------------------------------- +0x01 0x00 +0x01 0x01 ; Start Switch with this configuration diff --git a/doc/kwboot.1 b/doc/kwboot.1 new file mode 100644 index 0000000000..ed0839836e --- /dev/null +++ b/doc/kwboot.1 @@ -0,0 +1,84 @@ +.TH KWBOOT 1 "2012-05-19" + +.SH NAME +kwboot \- Boot Marvell Kirkwood SoCs over a serial link. +.SH SYNOPSIS +.B kwboot +.RB [ "-b \fIimage\fP" ] +.RB [ "-p" ] +.RB [ "-t" ] +.RB [ "-B \fIbaudrate\fP" ] +.RB \fITTY\fP +.SH "DESCRIPTION" + +The \fBmkimage\fP program boots boards based on Marvell's Kirkwood +platform over their integrated UART. Boot image files will typically +contain a second stage boot loader, such as U-Boot. The image file +must conform to Marvell's BootROM firmware image format +(\fIkwbimage\fP), created using a tool such as \fBmkimage\fP. + +Following power-up or a system reset, system BootROM code polls the +UART for a brief period of time, sensing a handshake message which +initiates an image upload. This program sends this boot message until +it receives a positive acknowledgement. The image is transfered using +Xmodem. + +Additionally, this program implements a minimal terminal mode, which +can be used either standalone, or entered immediately following boot +image transfer completion. This is often useful to catch early boot +messages, or to manually interrupt a default boot procedure performed +by the second-stage loader. + +.SH "OPTIONS" + +.TP +.BI "\-b \fIimage\fP" +Handshake; then upload file \fIimage\fP over \fITTY\fP. + +Note that for the encapsulated boot code to be executed, \fIimage\fP +must be of type "UART boot" (0x69). Boot images of different types, +such as backup images of vendor firmware downloaded from flash memory +(type 0x8B), will not work (or not as expected). See \fB-p\fP for a +workaround. + +This mode writes handshake status and upload progress indication to +stdout. + +.TP +.BI "\-p" +In combination with \fB-b\fP, patches the header in \fIimage\fP prior +to upload, to "UART boot" type. + +This option attempts on-the-fly conversion of some none-UART image +types, such as images which were originally formatted to be stored in +flash memory. + +Conversion is performed in memory. The contents of \fIimage\fP will +not be altered. + +.TP +.BI "\-t" +Run a terminal program, connecting standard input and output to +.RB \fITTY\fP. + +If used in combination with \fB-b\fP, terminal mode is entered +immediately following a successful image upload. + +If standard I/O streams connect to a console, this mode will terminate +after receiving 'ctrl-\\' followed by 'c' from console input. + +.TP +.BI "\-B \fIbaudrate\fP" +Adjust the baud rate on \fITTY\fP. Default rate is 115200. + +.SH "SEE ALSO" +.PP +\fBmkimage\fP(1) + +.SH "AUTHORS" + +Daniel Stodden <daniel.stodden@gmail.com> +.br +Luka Perkov <uboot@lukaperkov.net> +.br +David Purdy <david.c.purdy@gmail.com> diff --git a/drivers/block/sata_sil.c b/drivers/block/sata_sil.c index 5e7ef5e0de..fb7cd2aae2 100644 --- a/drivers/block/sata_sil.c +++ b/drivers/block/sata_sil.c @@ -30,7 +30,6 @@ /* Convert sectorsize to wordsize */ #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2) -#define mdelay(n) udelay((n)*1000) #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) static struct sata_info sata_info; diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb3b09ae74..32a2474980 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -35,7 +35,8 @@ COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_PCA9698) += pca9698.o COBJS-$(CONFIG_S5P) += s5p_gpio.o COBJS-$(CONFIG_SANDBOX_GPIO) += sandbox.o -COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o +COBJS-$(CONFIG_SPEAR_GPIO) += spear_gpio.o +COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index be2a0268e8..ac3b322af2 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -86,7 +86,14 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].asr); +#endif writel(mask, &pio->port[port].pdr); } return 0; @@ -104,12 +111,63 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].bsr); +#endif writel(mask, &pio->port[port].pdr); } return 0; } +#if defined(CPU_HAS_PIO3) +/* + * mux the pin to the "C" internal peripheral role. + */ +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * mux the pin to the "D" internal peripheral role. + */ +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} +#endif + /* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. @@ -162,13 +220,76 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; - if (is_on) + if (is_on) { +#if defined(CPU_HAS_PIO3) + writel(mask, &pio->port[port].ifscdr); +#endif writel(mask, &pio->port[port].ifer); - else + } else { writel(mask, &pio->port[port].ifdr); + } + } + return 0; +} + +#if defined(CPU_HAS_PIO3) +/* + * enable/disable the debounce filter. + */ +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + if (is_on) { + writel(mask, &pio->port[port].ifscer); + writel(div & PIO_SCDR_DIV, &pio->port[port].scdr); + writel(mask, &pio->port[port].ifer); + } else { + writel(mask, &pio->port[port].ifdr); + } + } + return 0; +} + +/* + * enable/disable the pull-down. + * If pull-up already enabled while calling the function, we disable it. + */ +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].pudr); + if (is_on) + writel(mask, &pio->port[port].ppder); + else + writel(mask, &pio->port[port].ppddr); + } + return 0; +} + +/* + * disable Schmitt trigger + */ +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(readl(&pio->port[port].schmitt) | mask, + &pio->port[port].schmitt); } return 0; } +#endif /* * enable/disable the multi-driver. This is only valid for output and diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c new file mode 100644 index 0000000000..d3c728e137 --- /dev/null +++ b/drivers/gpio/spear_gpio.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Driver for SPEAr600 GPIO controller + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <errno.h> + +static int gpio_direction(unsigned gpio, + enum gpio_direction direction) +{ + struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; + u32 val; + + val = readl(®s->gpiodir); + + if (direction == GPIO_DIRECTION_OUT) + val |= 1 << gpio; + else + val &= ~(1 << gpio); + + writel(val, ®s->gpiodir); + + return 0; +} + +int gpio_set_value(unsigned gpio, int value) +{ + struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; + + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]); + + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE; + u32 val; + + val = readl(®s->gpiodata[DATA_REG_ADDR(gpio)]); + + return !!val; +} + +int gpio_request(unsigned gpio, const char *label) +{ + if (gpio >= SPEAR_GPIO_COUNT) + return -EINVAL; + + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} + +void gpio_toggle_value(unsigned gpio) +{ + gpio_set_value(gpio, !gpio_get_value(gpio)); +} + +int gpio_direction_input(unsigned gpio) +{ + return gpio_direction(gpio, GPIO_DIRECTION_IN); +} + +int gpio_direction_output(unsigned gpio, int value) +{ + int ret = gpio_direction(gpio, GPIO_DIRECTION_OUT); + + if (ret < 0) + return ret; + + gpio_set_value(gpio, value); + return 0; +} diff --git a/drivers/gpio/tegra2_gpio.c b/drivers/gpio/tegra_gpio.c index 70ca46fae5..60ec6e3d78 100644 --- a/drivers/gpio/tegra2_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -1,6 +1,6 @@ /* * NVIDIA Tegra2 GPIO handling. - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2012 * NVIDIA Corporation <www.nvidia.com> * * See file CREDITS for list of people who contributed to this diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 6d118acec4..bf64a2a643 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -90,7 +90,7 @@ static void set_speed(int i2c_spd) * * Set the i2c speed. */ -void i2c_set_bus_speed(int speed) +int i2c_set_bus_speed(int speed) { if (speed >= I2C_MAX_SPEED) set_speed(IC_SPEED_MODE_MAX); @@ -98,6 +98,8 @@ void i2c_set_bus_speed(int speed) set_speed(IC_SPEED_MODE_FAST); else set_speed(IC_SPEED_MODE_STANDARD); + + return 0; } /* @@ -215,10 +217,8 @@ static int check_params(uint addr, int alen, uchar *buffer, int len) static int i2c_xfer_init(uchar chip, uint addr) { - if (i2c_wait_for_bb()) { - printf("Timed out waiting for bus\n"); + if (i2c_wait_for_bb()) return 1; - } i2c_setaddress(chip); writel(addr, &i2c_regs_p->ic_cmd_data); @@ -282,7 +282,6 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) start_time_rx = get_timer(0); } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { - printf("Timed out. i2c read Failed\n"); return 1; } } @@ -334,9 +333,14 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_probe(uchar chip) { u32 tmp; + int ret; /* * Try to read the first location of the chip. */ - return i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); + if (ret) + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return ret; } diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index c88ac7cf98..fc68062b11 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -59,27 +59,10 @@ struct mxc_i2c_regs { #define I2SR_IIF (1 << 1) #define I2SR_RX_NO_AK (1 << 0) -#if defined(CONFIG_SYS_I2C_MX31_PORT1) -#define I2C_BASE 0x43f80000 -#define I2C_CLK_OFFSET 26 -#elif defined (CONFIG_SYS_I2C_MX31_PORT2) -#define I2C_BASE 0x43f98000 -#define I2C_CLK_OFFSET 28 -#elif defined (CONFIG_SYS_I2C_MX31_PORT3) -#define I2C_BASE 0x43f84000 -#define I2C_CLK_OFFSET 30 -#elif defined(CONFIG_SYS_I2C_MX53_PORT1) -#define I2C_BASE I2C1_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX53_PORT2) -#define I2C_BASE I2C2_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX35_PORT1) -#define I2C_BASE I2C_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX35_PORT2) -#define I2C_BASE I2C2_BASE_ADDR -#elif defined(CONFIG_SYS_I2C_MX35_PORT3) -#define I2C_BASE I2C3_BASE_ADDR +#ifdef CONFIG_SYS_I2C_BASE +#define I2C_BASE CONFIG_SYS_I2C_BASE #else -#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" +#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" #endif #define I2C_MAX_TIMEOUT 10000 @@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate) (struct clock_control_regs *)CCM_BASE; /* start the required I2C clock */ - writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), + writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), &sc_regs->cgr0); #endif @@ -248,12 +231,6 @@ int i2c_imx_start(void) struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; unsigned int temp = 0; int result; - int speed = i2c_get_bus_speed(); - u8 clk_idx = i2c_imx_get_clk(speed); - u8 idx = i2c_clk_div[clk_idx][1]; - - /* Store divider value */ - writeb(idx, &i2c_regs->ifdr); /* Enable I2C controller */ writeb(0, &i2c_regs->i2sr); diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c index c8fea32355..48aaaa6268 100644 --- a/drivers/i2c/mxs_i2c.c +++ b/drivers/i2c/mxs_i2c.c @@ -97,7 +97,7 @@ void mxs_i2c_write(uchar chip, uint addr, int alen, for (i = 0; i < alen; i++) { data >>= 8; - data |= ((char *)&addr)[i] << 24; + data |= ((char *)&addr)[alen - i - 1] << 24; if ((i & 3) == 2) writel(data, &i2c_regs->hw_i2c_data); } diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a7ffd95d5d..81193b0e6e 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -202,7 +202,7 @@ static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value) } if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) *value = readb(&i2c_base->data); #else *value = readw(&i2c_base->data); @@ -232,7 +232,7 @@ static void flush_fifo(void) stat = readw(&i2c_base->stat); if (stat == I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) readb(&i2c_base->data); #else readw(&i2c_base->data); @@ -255,23 +255,43 @@ int i2c_probe(uchar chip) /* wait until bus not busy */ wait_for_bb(); - /* try to write one byte */ + /* try to read one byte */ writew(1, &i2c_base->cnt); /* set slave address */ writew(chip, &i2c_base->sa); /* stop bit needed here */ - writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, &i2c_base->con); - - status = wait_for_pin(); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); - /* check for ACK (!NAK) */ - if (!(status & I2C_STAT_NACK)) - res = 0; - - /* abort transfer (force idle state) */ - writew(0, &i2c_base->con); + while (1) { + status = wait_for_pin(); + if (status == 0 || status & I2C_STAT_AL) { + res = 1; + goto probe_exit; + } + if (status & I2C_STAT_NACK) { + res = 1; + writew(0xff, &i2c_base->stat); + writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); + wait_for_bb (); + break; + } + if (status & I2C_STAT_ARDY) { + writew(I2C_STAT_ARDY, &i2c_base->stat); + break; + } + if (status & I2C_STAT_RRDY) { + res = 0; +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) + readb(&i2c_base->data); +#else + readw(&i2c_base->data); +#endif + writew(I2C_STAT_RRDY, &i2c_base->stat); + } + } +probe_exit: flush_fifo(); /* don't allow any more data in... we don't want it. */ writew(0, &i2c_base->cnt); diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a8e681c2fe..c567737015 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -42,7 +42,7 @@ COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o COBJS-$(CONFIG_SDHCI) += sdhci.o COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o -COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o +COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 07370b5729..b6c969d2c8 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -190,6 +190,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); esdhc_write32(®s->dsaddr, (u32)data->dest); } else { + flush_dcache_range((ulong)data->src, + (ulong)data->src+data->blocks + *data->blocksize); + if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { @@ -249,7 +253,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) return 0; } - +static void check_and_invalidate_dcache_range + (struct mmc_cmd *cmd, + struct mmc_data *data) { + unsigned start = (unsigned)data->dest ; + unsigned size = roundup(ARCH_DMA_MINALIGN, + data->blocks*data->blocksize); + unsigned end = start+size ; + invalidate_dcache_range(start, end); +} /* * Sends a command out on the bus. Takes the mmc pointer, * a command pointer, and an optional data pointer. @@ -315,6 +327,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) while (!(esdhc_read32(®s->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE))) ; + if (data && (data->flags & MMC_DATA_READ)) + check_and_invalidate_dcache_range(cmd, data); + irqstat = esdhc_read32(®s->irqstat); esdhc_write32(®s->irqstat, irqstat); @@ -528,6 +543,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) /* First reset the eSDHC controller */ esdhc_reset(regs); + esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN + | SYSCTL_IPGEN | SYSCTL_CKEN); + mmc->priv = cfg; mmc->send_cmd = esdhc_send_cmd; mmc->set_ios = esdhc_set_ios; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578ff6..c1c2862986 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -333,6 +333,7 @@ mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt) int err = 0; struct mmc *mmc = find_mmc_device(dev_num); lbaint_t blk = 0, blk_r = 0; + int timeout = 1000; if (!mmc) return -1; @@ -352,6 +353,10 @@ mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt) break; blk += blk_r; + + /* Waiting for the ready status */ + if (mmc_send_status(mmc, timeout)) + return 0; } return blk; @@ -1195,9 +1200,9 @@ int mmc_startup(struct mmc *mmc) } if (mmc->card_caps & MMC_MODE_HS) - mmc_set_clock(mmc, 50000000); + mmc->tran_speed = 50000000; else - mmc_set_clock(mmc, 25000000); + mmc->tran_speed = 25000000; } else { width = ((mmc->host_caps & MMC_MODE_MASK_WIDTH_BITS) >> MMC_MODE_WIDTH_BITS_SHIFT); @@ -1234,13 +1239,14 @@ int mmc_startup(struct mmc *mmc) if (mmc->card_caps & MMC_MODE_HS) { if (mmc->card_caps & MMC_MODE_HS_52MHz) - mmc_set_clock(mmc, 52000000); + mmc->tran_speed = 52000000; else - mmc_set_clock(mmc, 26000000); - } else - mmc_set_clock(mmc, 20000000); + mmc->tran_speed = 26000000; + } } + mmc_set_clock(mmc, mmc->tran_speed); + /* fill in device description */ mmc->block_dev.lun = 0; mmc->block_dev.type = 0; @@ -1305,8 +1311,11 @@ int mmc_register(struct mmc *mmc) block_dev_desc_t *mmc_get_dev(int dev) { struct mmc *mmc = find_mmc_device(dev); + if (!mmc) + return NULL; - return mmc ? &mmc->block_dev : NULL; + mmc_init(mmc); + return &mmc->block_dev; } #endif diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra_mmc.c index fb8a57d162..29bf58359d 100644 --- a/drivers/mmc/tegra2_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -2,7 +2,7 @@ * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang <mk7.kang@samsung.com> * Jaehoon Chung <jh80.chung@samsung.com> - * Portions Copyright 2011 NVIDIA Corporation + * Portions Copyright 2011-2012 NVIDIA Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,7 +25,7 @@ #include <asm/io.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> -#include "tegra2_mmc.h" +#include "tegra_mmc.h" /* support 4 mmc hosts */ struct mmc mmc_dev[4]; diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra_mmc.h index 67c00db9de..f9cdcaaaa6 100644 --- a/drivers/mmc/tegra2_mmc.h +++ b/drivers/mmc/tegra_mmc.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang <mk7.kang@samsung.com> - * Portions Copyright (C) 2011 NVIDIA Corporation + * Portions Copyright (C) 2011-2012 NVIDIA Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,8 +19,8 @@ * */ -#ifndef __TEGRA2_MMC_H_ -#define __TEGRA2_MMC_H_ +#ifndef __TEGRA_MMC_H_ +#define __TEGRA_MMC_H_ #define TEGRA2_SDMMC1_BASE 0xC8000000 #define TEGRA2_SDMMC2_BASE 0xC8000200 @@ -128,4 +128,4 @@ struct mmc_host { }; #endif /* __ASSEMBLY__ */ -#endif /* __TEGRA2_MMC_H_ */ +#endif /* __TEGRA_MMC_H_ */ diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 5a5ecdfe3c..543c845ff0 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -35,7 +35,7 @@ COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FTSMC020) += ftsmc020.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o -COBJS-$(CONFIG_SPEARSMI) += spr_smi.o +COBJS-$(CONFIG_ST_SMI) += st_smi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 1d1b628651..29dc20ef5e 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -49,6 +49,7 @@ COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c new file mode 100644 index 0000000000..7a61d88cc5 --- /dev/null +++ b/drivers/mtd/nand/fsmc_nand.c @@ -0,0 +1,486 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. + * + * (C) Copyright 2012 + * Amit Virdi, ST Microelectronics, amit.virdi@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/fsmc_nand.h> +#include <asm/arch/hardware.h> + +static u32 fsmc_version; +static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *) + CONFIG_SYS_FSMC_BASE; + +/* + * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of + * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can + * correct 1 bit in 512 bytes + */ + +static struct nand_ecclayout fsmc_ecc4_lp_layout = { + .eccbytes = 104, + .eccpos = { 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, + 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, + 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, + 50, 51, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, + 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, + 82, 83, 84, 85, 86, 87, 88, + 89, 90, 91, 92, 93, 94, + 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, + 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126 + }, + .oobfree = { + {.offset = 15, .length = 3}, + {.offset = 31, .length = 3}, + {.offset = 47, .length = 3}, + {.offset = 63, .length = 3}, + {.offset = 79, .length = 3}, + {.offset = 95, .length = 3}, + {.offset = 111, .length = 3}, + {.offset = 127, .length = 1} + } +}; + +/* + * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes + * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118 + * bytes are free for use. + */ +static struct nand_ecclayout fsmc_ecc4_224_layout = { + .eccbytes = 104, + .eccpos = { 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, + 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, + 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, + 50, 51, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, + 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, + 82, 83, 84, 85, 86, 87, 88, + 89, 90, 91, 92, 93, 94, + 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, + 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126 + }, + .oobfree = { + {.offset = 15, .length = 3}, + {.offset = 31, .length = 3}, + {.offset = 47, .length = 3}, + {.offset = 63, .length = 3}, + {.offset = 79, .length = 3}, + {.offset = 95, .length = 3}, + {.offset = 111, .length = 3}, + {.offset = 127, .length = 97} + } +}; + +/* + * ECC placement definitions in oobfree type format + * There are 13 bytes of ecc for every 512 byte block and it has to be read + * consecutively and immediately after the 512 byte data block for hardware to + * generate the error bit offsets in 512 byte data + * Managing the ecc bytes in the following way makes it easier for software to + * read ecc bytes consecutive to data bytes. This way is similar to + * oobfree structure maintained already in u-boot nand driver + */ +static struct fsmc_eccplace fsmc_eccpl_lp = { + .eccplace = { + {.offset = 2, .length = 13}, + {.offset = 18, .length = 13}, + {.offset = 34, .length = 13}, + {.offset = 50, .length = 13}, + {.offset = 66, .length = 13}, + {.offset = 82, .length = 13}, + {.offset = 98, .length = 13}, + {.offset = 114, .length = 13} + } +}; + +static struct nand_ecclayout fsmc_ecc4_sp_layout = { + .eccbytes = 13, + .eccpos = { 0, 1, 2, 3, 6, 7, 8, + 9, 10, 11, 12, 13, 14 + }, + .oobfree = { + {.offset = 15, .length = 1}, + } +}; + +static struct fsmc_eccplace fsmc_eccpl_sp = { + .eccplace = { + {.offset = 0, .length = 4}, + {.offset = 6, .length = 9} + } +}; + +static struct nand_ecclayout fsmc_ecc1_layout = { + .eccbytes = 24, + .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, + 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, + .oobfree = { + {.offset = 8, .length = 8}, + {.offset = 24, .length = 8}, + {.offset = 40, .length = 8}, + {.offset = 56, .length = 8}, + {.offset = 72, .length = 8}, + {.offset = 88, .length = 8}, + {.offset = 104, .length = 8}, + {.offset = 120, .length = 8} + } +}; + +/* Count the number of 0's in buff upto a max of max_bits */ +static int count_written_bits(uint8_t *buff, int size, int max_bits) +{ + int k, written_bits = 0; + + for (k = 0; k < size; k++) { + written_bits += hweight8(~buff[k]); + if (written_bits > max_bits) + break; + } + + return written_bits; +} + +static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ALE; + + if (ctrl & NAND_NCE) { + writel(readl(&fsmc_regs_p->pc) | + FSMC_ENABLE, &fsmc_regs_p->pc); + } else { + writel(readl(&fsmc_regs_p->pc) & + ~FSMC_ENABLE, &fsmc_regs_p->pc); + } + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + /* The calculated ecc is actually the correction index in data */ + u32 err_idx[8]; + u32 num_err, i; + u32 ecc1, ecc2, ecc3, ecc4; + + num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF; + + if (likely(num_err == 0)) + return 0; + + if (unlikely(num_err > 8)) { + /* + * This is a temporary erase check. A newly erased page read + * would result in an ecc error because the oob data is also + * erased to FF and the calculated ecc for an FF data is not + * FF..FF. + * This is a workaround to skip performing correction in case + * data is FF..FF + * + * Logic: + * For every page, each bit written as 0 is counted until these + * number of bits are greater than 8 (the maximum correction + * capability of FSMC for each 512 + 13 bytes) + */ + + int bits_ecc = count_written_bits(read_ecc, 13, 8); + int bits_data = count_written_bits(dat, 512, 8); + + if ((bits_ecc + bits_data) <= 8) { + if (bits_data) + memset(dat, 0xff, 512); + return bits_data + bits_ecc; + } + + return -EBADMSG; + } + + ecc1 = readl(&fsmc_regs_p->ecc1); + ecc2 = readl(&fsmc_regs_p->ecc2); + ecc3 = readl(&fsmc_regs_p->ecc3); + ecc4 = readl(&fsmc_regs_p->sts); + + err_idx[0] = (ecc1 >> 0) & 0x1FFF; + err_idx[1] = (ecc1 >> 13) & 0x1FFF; + err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); + err_idx[3] = (ecc2 >> 7) & 0x1FFF; + err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); + err_idx[5] = (ecc3 >> 1) & 0x1FFF; + err_idx[6] = (ecc3 >> 14) & 0x1FFF; + err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); + + i = 0; + while (i < num_err) { + err_idx[i] ^= 3; + + if (err_idx[i] < 512 * 8) + __change_bit(err_idx[i], dat); + + i++; + } + + return num_err; +} + +static int fsmc_read_hwecc(struct mtd_info *mtd, + const u_char *data, u_char *ecc) +{ + u_int ecc_tmp; + int timeout = CONFIG_SYS_HZ; + ulong start; + + switch (fsmc_version) { + case FSMC_VER8: + start = get_timer(0); + while (get_timer(start) < timeout) { + /* + * Busy waiting for ecc computation + * to finish for 512 bytes + */ + if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY) + break; + } + + ecc_tmp = readl(&fsmc_regs_p->ecc1); + ecc[0] = (u_char) (ecc_tmp >> 0); + ecc[1] = (u_char) (ecc_tmp >> 8); + ecc[2] = (u_char) (ecc_tmp >> 16); + ecc[3] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->ecc2); + ecc[4] = (u_char) (ecc_tmp >> 0); + ecc[5] = (u_char) (ecc_tmp >> 8); + ecc[6] = (u_char) (ecc_tmp >> 16); + ecc[7] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->ecc3); + ecc[8] = (u_char) (ecc_tmp >> 0); + ecc[9] = (u_char) (ecc_tmp >> 8); + ecc[10] = (u_char) (ecc_tmp >> 16); + ecc[11] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->sts); + ecc[12] = (u_char) (ecc_tmp >> 16); + break; + + default: + ecc_tmp = readl(&fsmc_regs_p->ecc1); + ecc[0] = (u_char) (ecc_tmp >> 0); + ecc[1] = (u_char) (ecc_tmp >> 8); + ecc[2] = (u_char) (ecc_tmp >> 16); + break; + } + + return 0; +} + +void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) +{ + writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256, + &fsmc_regs_p->pc); + writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN, + &fsmc_regs_p->pc); + writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN, + &fsmc_regs_p->pc); +} + +/* + * fsmc_read_page_hwecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + * + * This routine is needed for fsmc verison 8 as reading from NAND chip has to be + * performed in a strict sequence as follows: + * data(512 byte) -> ecc(13 byte) + * After this read, fsmc hardware generates and reports error data bits(upto a + * max of 8 bits) + */ +static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + struct fsmc_eccplace *fsmc_eccpl; + int i, j, s, stat, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *ecc_calc = chip->buffers->ecccalc; + uint8_t *ecc_code = chip->buffers->ecccode; + int off, len, group = 0; + uint8_t oob[13] __attribute__ ((aligned (2))); + + /* Differentiate between small and large page ecc place definitions */ + if (mtd->writesize == 512) + fsmc_eccpl = &fsmc_eccpl_sp; + else + fsmc_eccpl = &fsmc_eccpl_lp; + + for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { + + chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + + for (j = 0; j < eccbytes;) { + off = fsmc_eccpl->eccplace[group].offset; + len = fsmc_eccpl->eccplace[group].length; + group++; + + /* + * length is intentionally kept a higher multiple of 2 + * to read at least 13 bytes even in case of 16 bit NAND + * devices + */ + if (chip->options & NAND_BUSWIDTH_16) + len = roundup(len, 2); + chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); + chip->read_buf(mtd, oob + j, len); + j += len; + } + + memcpy(&ecc_code[i], oob, 13); + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], + &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + + return 0; +} + +int fsmc_nand_init(struct nand_chip *nand) +{ + static int chip_nr; + struct mtd_info *mtd; + int i; + u32 peripid2 = readl(&fsmc_regs_p->peripid2); + + fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) & + FSMC_REVISION_MSK; + + writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl); + +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, + &fsmc_regs_p->pc); +#elif defined(CONFIG_SYS_FSMC_NAND_8BIT) + writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, + &fsmc_regs_p->pc); +#else +#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT +#endif + writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1, + &fsmc_regs_p->pc); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->comm); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->attrib); + + nand->options = 0; +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + nand->options |= NAND_BUSWIDTH_16; +#endif + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 512; + nand->ecc.calculate = fsmc_read_hwecc; + nand->ecc.hwctl = fsmc_enable_hwecc; + nand->cmd_ctrl = fsmc_nand_hwcontrol; + nand->IO_ADDR_R = nand->IO_ADDR_W = + (void __iomem *)CONFIG_SYS_NAND_BASE; + nand->badblockbits = 7; + + mtd = &nand_info[chip_nr++]; + mtd->priv = nand; + + switch (fsmc_version) { + case FSMC_VER8: + nand->ecc.bytes = 13; + nand->ecc.correct = fsmc_bch8_correct_data; + nand->ecc.read_page = fsmc_read_page_hwecc; + if (mtd->writesize == 512) + nand->ecc.layout = &fsmc_ecc4_sp_layout; + else { + if (mtd->oobsize == 224) + nand->ecc.layout = &fsmc_ecc4_224_layout; + else + nand->ecc.layout = &fsmc_ecc4_lp_layout; + } + + break; + default: + nand->ecc.bytes = 3; + nand->ecc.layout = &fsmc_ecc1_layout; + nand->ecc.correct = nand_correct_data; + break; + } + + /* Detect NAND chips */ + if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) + return -ENXIO; + + if (nand_scan_tail(mtd)) + return -ENXIO; + + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + if (nand_register(i)) + return -ENXIO; + + return 0; +} diff --git a/drivers/mtd/nand/spr_nand.c b/drivers/mtd/nand/spr_nand.c deleted file mode 100644 index 097d0c60bf..0000000000 --- a/drivers/mtd/nand/spr_nand.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <nand.h> -#include <linux/mtd/nand_ecc.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_nand.h> - -static struct fsmc_regs *const fsmc_regs_p = - (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE; - -static struct nand_ecclayout spear_nand_ecclayout = { - .eccbytes = 24, - .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, - 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, - .oobfree = { - {.offset = 8, .length = 8}, - {.offset = 24, .length = 8}, - {.offset = 40, .length = 8}, - {.offset = 56, .length = 8}, - {.offset = 72, .length = 8}, - {.offset = 88, .length = 8}, - {.offset = 104, .length = 8}, - {.offset = 120, .length = 8} - } -}; - -static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ALE; - - if (ctrl & NAND_NCE) { - writel(readl(&fsmc_regs_p->genmemctrl_pc) | - FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } else { - writel(readl(&fsmc_regs_p->genmemctrl_pc) & - ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int spear_read_hwecc(struct mtd_info *mtd, - const u_char *data, u_char ecc[3]) -{ - u_int ecc_tmp; - - /* read the h/w ECC */ - ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc); - - ecc[0] = (u_char) (ecc_tmp & 0xFF); - ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8); - ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16); - - return 0; -} - -void spear_enable_hwecc(struct mtd_info *mtd, int mode) -{ - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); -} - -int spear_nand_init(struct nand_chip *nand) -{ - writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1, - &fsmc_regs_p->genmemctrl_pc); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_comm); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_attrib); - - nand->options = 0; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &spear_nand_ecclayout; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.calculate = spear_read_hwecc; - nand->ecc.hwctl = spear_enable_hwecc; - nand->ecc.correct = nand_correct_data; - nand->cmd_ctrl = spear_nand_hwcontrol; - return 0; -} diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c index f9352f95a6..691ed4efc4 100644 --- a/drivers/mtd/spi/eon.c +++ b/drivers/mtd/spi/eon.c @@ -10,24 +10,8 @@ #include "spi_flash_internal.h" -/* EN25Q128-specific commands */ -#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ -#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ -#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ -#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ -#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ -#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_EN25Q128_PP 0x02 /* Page Program */ -#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ -#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ -#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ -#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ - struct eon_spi_flash_params { u8 idcode1; - u16 page_size; - u16 pages_per_sector; - u16 sectors_per_block; u16 nr_sectors; const char *name; }; @@ -35,35 +19,16 @@ struct eon_spi_flash_params { static const struct eon_spi_flash_params eon_spi_flash_table[] = { { .idcode1 = 0x16, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_sectors = 1024, .name = "EN25Q32B", }, { .idcode1 = 0x18, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_sectors = 4096, .name = "EN25Q128", }, - { - .idcode1 = 0x16, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_sectors = 1024, - .name = "EN25Q32B", - }, }; -static int eon_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len); -} - struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) { const struct eon_spi_flash_params *params; @@ -91,12 +56,11 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) flash->name = params->name; flash->write = spi_flash_cmd_write_multi; - flash->erase = eon_erase; + flash->erase = spi_flash_cmd_erase; flash->read = spi_flash_cmd_read_fast; - flash->page_size = params->page_size; - flash->sector_size = params->page_size * params->pages_per_sector - * params->sectors_per_block; - flash->size = params->page_size * params->pages_per_sector + flash->page_size = 256; + flash->sector_size = 256 * 16 * 16; + flash->size = 256 * 16 * params->nr_sectors; return flash; diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c index dacbc28b3e..c97a39d499 100644 --- a/drivers/mtd/spi/macronix.c +++ b/drivers/mtd/spi/macronix.c @@ -35,25 +35,8 @@ #include "spi_flash_internal.h" -/* MX25xx-specific commands */ -#define CMD_MX25XX_WREN 0x06 /* Write Enable */ -#define CMD_MX25XX_WRDI 0x04 /* Write Disable */ -#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */ -#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */ -#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */ -#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_MX25XX_PP 0x02 /* Page Program */ -#define CMD_MX25XX_SE 0x20 /* Sector Erase */ -#define CMD_MX25XX_BE 0xD8 /* Block Erase */ -#define CMD_MX25XX_CE 0xc7 /* Chip Erase */ -#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */ -#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */ - struct macronix_spi_flash_params { u16 idcode; - u16 page_size; - u16 pages_per_sector; - u16 sectors_per_block; u16 nr_blocks; const char *name; }; @@ -61,106 +44,41 @@ struct macronix_spi_flash_params { static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { { .idcode = 0x2013, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 8, .name = "MX25L4005", }, { .idcode = 0x2014, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 16, .name = "MX25L8005", }, { .idcode = 0x2015, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 32, .name = "MX25L1605D", }, { .idcode = 0x2016, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 64, .name = "MX25L3205D", }, { .idcode = 0x2017, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 128, .name = "MX25L6405D", }, { .idcode = 0x2018, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 256, .name = "MX25L12805D", }, { .idcode = 0x2618, - .page_size = 256, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 256, .name = "MX25L12855E", }, }; -static int macronix_write_status(struct spi_flash *flash, u8 sr) -{ - u8 cmd; - int ret; - - ret = spi_flash_cmd_write_enable(flash); - if (ret < 0) { - debug("SF: enabling write failed\n"); - return ret; - } - - cmd = CMD_MX25XX_WRSR; - ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1); - if (ret) { - debug("SF: fail to write status register\n"); - return ret; - } - - ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret < 0) { - debug("SF: write status register timed out\n"); - return ret; - } - - return 0; -} - -static int macronix_unlock(struct spi_flash *flash) -{ - int ret; - - /* Enable status register writing and clear BP# bits */ - ret = macronix_write_status(flash, 0); - if (ret) - debug("SF: fail to disable write protection\n"); - - return ret; -} - -static int macronix_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - return spi_flash_cmd_erase(flash, CMD_MX25XX_BE, offset, len); -} - struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) { const struct macronix_spi_flash_params *params; @@ -189,15 +107,14 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) flash->name = params->name; flash->write = spi_flash_cmd_write_multi; - flash->erase = macronix_erase; + flash->erase = spi_flash_cmd_erase; flash->read = spi_flash_cmd_read_fast; - flash->page_size = params->page_size; - flash->sector_size = params->page_size * params->pages_per_sector - * params->sectors_per_block; + flash->page_size = 256; + flash->sector_size = 256 * 16 * 16; flash->size = flash->sector_size * params->nr_blocks; /* Clear BP# bits for read-only flash */ - macronix_unlock(flash); + spi_flash_cmd_write_status(flash, 0); return flash; } diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c index 27d4039aad..0999781496 100644 --- a/drivers/mtd/spi/ramtron.c +++ b/drivers/mtd/spi/ramtron.c @@ -54,19 +54,6 @@ #include <spi_flash.h> #include "spi_flash_internal.h" -/* RAMTRON commands common to all devices */ -#define CMD_RAMTRON_WREN 0x06 /* Write Enable */ -#define CMD_RAMTRON_WRDI 0x04 /* Write Disable */ -#define CMD_RAMTRON_RDSR 0x05 /* Read Status Register */ -#define CMD_RAMTRON_WRSR 0x01 /* Write Status Register */ -#define CMD_RAMTRON_READ 0x03 /* Read Data Bytes */ -#define CMD_RAMTRON_WRITE 0x02 /* Write Data Bytes */ -/* not all have those: */ -#define CMD_RAMTRON_FSTRD 0x0b /* Fast Read (for compatibility - not used here) */ -#define CMD_RAMTRON_SLEEP 0xb9 /* Enter Sleep Mode */ -#define CMD_RAMTRON_RDID 0x9f /* Read ID */ -#define CMD_RAMTRON_SNR 0xc3 /* Read Serial Number */ - /* * Properties of supported FRAMs * Note: speed is currently not used because we have no method to deliver that @@ -196,7 +183,7 @@ static int ramtron_common(struct spi_flash *flash, return ret; } - if (command == CMD_RAMTRON_WRITE) { + if (command == CMD_PAGE_PROGRAM) { /* send WREN */ ret = spi_flash_cmd_write_enable(flash); if (ret < 0) { @@ -206,7 +193,7 @@ static int ramtron_common(struct spi_flash *flash, } /* do the transaction */ - if (command == CMD_RAMTRON_WRITE) + if (command == CMD_PAGE_PROGRAM) ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len); else ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len); @@ -223,14 +210,14 @@ static int ramtron_read(struct spi_flash *flash, u32 offset, size_t len, void *buf) { return ramtron_common(flash, offset, len, buf, - CMD_RAMTRON_READ); + CMD_READ_ARRAY_SLOW); } static int ramtron_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { return ramtron_common(flash, offset, len, (void *)buf, - CMD_RAMTRON_WRITE); + CMD_PAGE_PROGRAM); } static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len) @@ -270,7 +257,7 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) * We COULD have a non JEDEC conformant FRAM here, * read the status register to verify */ - ret = spi_flash_cmd(spi, CMD_RAMTRON_RDSR, &sr, 1); + ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1); if (ret) return NULL; diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 6301d87123..9a114ac6a1 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -31,34 +31,9 @@ #include "spi_flash_internal.h" -/* S25FLxx-specific commands */ -#define CMD_S25FLXX_READ 0x03 /* Read Data Bytes */ -#define CMD_S25FLXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_S25FLXX_READID 0x90 /* Read Manufacture ID and Device ID */ -#define CMD_S25FLXX_WREN 0x06 /* Write Enable */ -#define CMD_S25FLXX_WRDI 0x04 /* Write Disable */ -#define CMD_S25FLXX_RDSR 0x05 /* Read Status Register */ -#define CMD_S25FLXX_WRSR 0x01 /* Write Status Register */ -#define CMD_S25FLXX_PP 0x02 /* Page Program */ -#define CMD_S25FLXX_SE 0xd8 /* Sector Erase */ -#define CMD_S25FLXX_BE 0xc7 /* Bulk Erase */ -#define CMD_S25FLXX_DP 0xb9 /* Deep Power-down */ -#define CMD_S25FLXX_RES 0xab /* Release from DP, and Read Signature */ - -#define SPSN_ID_S25FL008A 0x0213 -#define SPSN_ID_S25FL016A 0x0214 -#define SPSN_ID_S25FL032A 0x0215 -#define SPSN_ID_S25FL064A 0x0216 -#define SPSN_ID_S25FL128P 0x2018 -#define SPSN_EXT_ID_S25FL128P_256KB 0x0300 -#define SPSN_EXT_ID_S25FL128P_64KB 0x0301 -#define SPSN_EXT_ID_S25FL032P 0x4d00 -#define SPSN_EXT_ID_S25FL129P 0x4d01 - struct spansion_spi_flash_params { u16 idcode1; u16 idcode2; - u16 page_size; u16 pages_per_sector; u16 nr_sectors; const char *name; @@ -66,76 +41,63 @@ struct spansion_spi_flash_params { static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { { - .idcode1 = SPSN_ID_S25FL008A, + .idcode1 = 0x0213, .idcode2 = 0, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 16, .name = "S25FL008A", }, { - .idcode1 = SPSN_ID_S25FL016A, + .idcode1 = 0x0214, .idcode2 = 0, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 32, .name = "S25FL016A", }, { - .idcode1 = SPSN_ID_S25FL032A, + .idcode1 = 0x0215, .idcode2 = 0, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 64, .name = "S25FL032A", }, { - .idcode1 = SPSN_ID_S25FL064A, + .idcode1 = 0x0216, .idcode2 = 0, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 128, .name = "S25FL064A", }, { - .idcode1 = SPSN_ID_S25FL128P, - .idcode2 = SPSN_EXT_ID_S25FL128P_64KB, - .page_size = 256, + .idcode1 = 0x2018, + .idcode2 = 0x0301, .pages_per_sector = 256, .nr_sectors = 256, .name = "S25FL128P_64K", }, { - .idcode1 = SPSN_ID_S25FL128P, - .idcode2 = SPSN_EXT_ID_S25FL128P_256KB, - .page_size = 256, + .idcode1 = 0x2018, + .idcode2 = 0x0300, .pages_per_sector = 1024, .nr_sectors = 64, .name = "S25FL128P_256K", }, { - .idcode1 = SPSN_ID_S25FL032A, - .idcode2 = SPSN_EXT_ID_S25FL032P, - .page_size = 256, + .idcode1 = 0x0215, + .idcode2 = 0x4d00, .pages_per_sector = 256, .nr_sectors = 64, .name = "S25FL032P", }, { - .idcode1 = SPSN_ID_S25FL128P, - .idcode2 = SPSN_EXT_ID_S25FL129P, - .page_size = 256, + .idcode1 = 0x2018, + .idcode2 = 0x4d01, .pages_per_sector = 256, .nr_sectors = 256, .name = "S25FL129P_64K", }, }; -static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len); -} - struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) { const struct spansion_spi_flash_params *params; @@ -169,10 +131,10 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) flash->name = params->name; flash->write = spi_flash_cmd_write_multi; - flash->erase = spansion_erase; + flash->erase = spi_flash_cmd_erase; flash->read = spi_flash_cmd_read_fast; - flash->page_size = params->page_size; - flash->sector_size = params->page_size * params->pages_per_sector; + flash->page_size = 256; + flash->sector_size = 256 * params->pages_per_sector; flash->size = flash->sector_size * params->nr_sectors; return flash; diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index f689cc47cf..00aece9291 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -190,8 +190,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) CMD_READ_STATUS, STATUS_WIP); } -int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, - u32 offset, size_t len) +int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) { u32 start, end, erase_size; int ret; @@ -209,7 +208,10 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, return ret; } - cmd[0] = erase_cmd; + if (erase_size == 4096) + cmd[0] = CMD_ERASE_4K; + else + cmd[0] = CMD_ERASE_64K; start = offset; end = start + len; @@ -240,6 +242,33 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, return ret; } +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) +{ + u8 cmd; + int ret; + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + cmd = CMD_WRITE_STATUS; + ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1); + if (ret) { + debug("SF: fail to write status register\n"); + return ret; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: write status register timed out\n"); + return ret; + } + + return 0; +} + /* * The following table holds all device probe functions * diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 91e036a4e7..141cfa8b26 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -17,12 +17,16 @@ #define CMD_READ_ARRAY_SLOW 0x03 #define CMD_READ_ARRAY_FAST 0x0b -#define CMD_READ_ARRAY_LEGACY 0xe8 +#define CMD_WRITE_STATUS 0x01 #define CMD_PAGE_PROGRAM 0x02 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_STATUS 0x05 #define CMD_WRITE_ENABLE 0x06 +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_32K 0x52 +#define CMD_ERASE_64K 0xd8 +#define CMD_ERASE_CHIP 0xc7 /* Common status */ #define STATUS_WIP 0x01 @@ -70,6 +74,9 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); } +/* Program the status register. */ +int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); + /* * Same as spi_flash_cmd_read() except it also claims/releases the SPI * bus. Used as common part of the ->read() operation. @@ -88,8 +95,7 @@ int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); /* Erase sectors. */ -int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, - u32 offset, size_t len); +int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len); /* Manufacturer-specific probe functions */ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c index 9559c80072..ced4f2473f 100644 --- a/drivers/mtd/spi/sst.c +++ b/drivers/mtd/spi/sst.c @@ -18,15 +18,8 @@ #include "spi_flash_internal.h" -#define CMD_SST_WREN 0x06 /* Write Enable */ -#define CMD_SST_WRDI 0x04 /* Write Disable */ -#define CMD_SST_RDSR 0x05 /* Read Status Register */ -#define CMD_SST_WRSR 0x01 /* Write Status Register */ -#define CMD_SST_READ 0x03 /* Read Data Bytes */ -#define CMD_SST_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ #define CMD_SST_BP 0x02 /* Byte Program */ #define CMD_SST_AAI_WP 0xAD /* Auto Address Increment Word Program */ -#define CMD_SST_SE 0x20 /* Sector Erase */ #define SST_SR_WIP (1 << 0) /* Write-in-Progress */ #define SST_SR_WEL (1 << 1) /* Write enable */ @@ -51,13 +44,6 @@ struct sst_spi_flash { const struct sst_spi_flash_params *params; }; -static inline struct sst_spi_flash *to_sst_spi_flash(struct spi_flash *flash) -{ - return container_of(flash, struct sst_spi_flash, flash); -} - -#define SST_SECTOR_SIZE (4 * 1024) -#define SST_PAGE_SIZE 256 static const struct sst_spi_flash_params sst_spi_flash_table[] = { { .idcode1 = 0x8d, @@ -108,24 +94,6 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { }; static int -sst_enable_writing(struct spi_flash *flash) -{ - int ret = spi_flash_cmd_write_enable(flash); - if (ret) - debug("SF: Enabling Write failed\n"); - return ret; -} - -static int -sst_disable_writing(struct spi_flash *flash) -{ - int ret = spi_flash_cmd_write_disable(flash); - if (ret) - debug("SF: Disabling Write failed\n"); - return ret; -} - -static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) { int ret; @@ -137,9 +105,9 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) }; debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); + spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); - ret = sst_enable_writing(flash); + ret = spi_flash_cmd_write_enable(flash); if (ret) return ret; @@ -172,7 +140,7 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) } offset += actual; - ret = sst_enable_writing(flash); + ret = spi_flash_cmd_write_enable(flash); if (ret) goto done; @@ -184,7 +152,7 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) for (; actual < len - 1; actual += 2) { debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", - spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], + spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, cmd[0], offset); ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, @@ -203,7 +171,7 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) } if (!ret) - ret = sst_disable_writing(flash); + ret = spi_flash_cmd_write_disable(flash); /* If there is a single trailing byte, write it out */ if (!ret && actual != len) @@ -217,32 +185,6 @@ sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, const void *buf) return ret; } -static int sst_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - return spi_flash_cmd_erase(flash, CMD_SST_SE, offset, len); -} - -static int -sst_unlock(struct spi_flash *flash) -{ - int ret; - u8 cmd, status; - - ret = sst_enable_writing(flash); - if (ret) - return ret; - - cmd = CMD_SST_WRSR; - status = 0; - ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &status, 1); - if (ret) - debug("SF: Unable to set status byte\n"); - - debug("SF: sst: status = %x\n", spi_w8r8(flash->spi, CMD_SST_RDSR)); - - return ret; -} - struct spi_flash * spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) { @@ -275,14 +217,14 @@ spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) stm->flash.write = sst_write_wp; else stm->flash.write = spi_flash_cmd_write_multi; - stm->flash.erase = sst_erase; + stm->flash.erase = spi_flash_cmd_erase; stm->flash.read = spi_flash_cmd_read_fast; - stm->flash.page_size = SST_PAGE_SIZE; - stm->flash.sector_size = SST_SECTOR_SIZE; + stm->flash.page_size = 256; + stm->flash.sector_size = 4096; stm->flash.size = stm->flash.sector_size * params->nr_sectors; /* Flash powers up read-only, so clear BP# bits */ - sst_unlock(&stm->flash); + spi_flash_cmd_write_status(&stm->flash, 0); return &stm->flash; } diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index a9b33cfd94..dbd1fc1854 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -34,21 +34,10 @@ #include "spi_flash_internal.h" /* M25Pxx-specific commands */ -#define CMD_M25PXX_WREN 0x06 /* Write Enable */ -#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ -#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ -#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ -#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ -#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_M25PXX_PP 0x02 /* Page Program */ -#define CMD_M25PXX_SE 0xd8 /* Sector Erase */ -#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ -#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ #define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ struct stmicro_spi_flash_params { u8 idcode1; - u16 page_size; u16 pages_per_sector; u16 nr_sectors; const char *name; @@ -57,67 +46,60 @@ struct stmicro_spi_flash_params { static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { { .idcode1 = 0x11, - .page_size = 256, .pages_per_sector = 128, .nr_sectors = 4, .name = "M25P10", }, { .idcode1 = 0x15, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 32, .name = "M25P16", }, { .idcode1 = 0x12, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 4, .name = "M25P20", }, { .idcode1 = 0x16, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 64, .name = "M25P32", }, { .idcode1 = 0x13, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 8, .name = "M25P40", }, { .idcode1 = 0x17, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 128, .name = "M25P64", }, { .idcode1 = 0x14, - .page_size = 256, .pages_per_sector = 256, .nr_sectors = 16, .name = "M25P80", }, { .idcode1 = 0x18, - .page_size = 256, .pages_per_sector = 1024, .nr_sectors = 64, .name = "M25P128", }, + { + .idcode1 = 0x19, + .pages_per_sector = 256, + .nr_sectors = 512, + .name = "N25Q256", + }, }; -static int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - return spi_flash_cmd_erase(flash, CMD_M25PXX_SE, offset, len); -} - struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) { const struct stmicro_spi_flash_params *params; @@ -159,10 +141,10 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) flash->name = params->name; flash->write = spi_flash_cmd_write_multi; - flash->erase = stmicro_erase; + flash->erase = spi_flash_cmd_erase; flash->read = spi_flash_cmd_read_fast; - flash->page_size = params->page_size; - flash->sector_size = params->page_size * params->pages_per_sector; + flash->page_size = 256; + flash->sector_size = 256 * params->pages_per_sector; flash->size = flash->sector_size * params->nr_sectors; return flash; diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index a6a66537ba..427b71fcdc 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -10,26 +10,8 @@ #include "spi_flash_internal.h" -/* M25Pxx-specific commands */ -#define CMD_W25_WREN 0x06 /* Write Enable */ -#define CMD_W25_WRDI 0x04 /* Write Disable */ -#define CMD_W25_RDSR 0x05 /* Read Status Register */ -#define CMD_W25_WRSR 0x01 /* Write Status Register */ -#define CMD_W25_READ 0x03 /* Read Data Bytes */ -#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_W25_PP 0x02 /* Page Program */ -#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_W25_CE 0xc7 /* Chip Erase */ -#define CMD_W25_DP 0xb9 /* Deep Power-down */ -#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ - struct winbond_spi_flash_params { uint16_t id; - /* Log2 of page size in power-of-two mode */ - uint8_t l2_page_size; - uint16_t pages_per_sector; - uint16_t sectors_per_block; uint16_t nr_blocks; const char *name; }; @@ -37,81 +19,56 @@ struct winbond_spi_flash_params { static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { { .id = 0x3013, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 8, .name = "W25X40", }, { .id = 0x3015, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 32, .name = "W25X16", }, { .id = 0x3016, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 64, .name = "W25X32", }, { .id = 0x3017, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 128, .name = "W25X64", }, { + .id = 0x4014, + .nr_blocks = 16, + .name = "W25Q80BL", + }, + { .id = 0x4015, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 32, .name = "W25Q16", }, { .id = 0x4016, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 64, .name = "W25Q32", }, { .id = 0x4017, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 128, .name = "W25Q64", }, { .id = 0x4018, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, .nr_blocks = 256, .name = "W25Q128", }, }; -static int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - return spi_flash_cmd_erase(flash, CMD_W25_SE, offset, len); -} - struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) { const struct winbond_spi_flash_params *params; struct spi_flash *flash; unsigned int i; - unsigned page_size; for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { params = &winbond_spi_flash_table[i]; @@ -134,17 +91,12 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) flash->spi = spi; flash->name = params->name; - /* Assuming power-of-two page size initially. */ - page_size = 1 << params->l2_page_size; - flash->write = spi_flash_cmd_write_multi; - flash->erase = winbond_erase; + flash->erase = spi_flash_cmd_erase; flash->read = spi_flash_cmd_read_fast; - flash->page_size = page_size; - flash->sector_size = page_size * params->pages_per_sector; - flash->size = page_size * params->pages_per_sector - * params->sectors_per_block - * params->nr_blocks; + flash->page_size = 4096; + flash->sector_size = 4096; + flash->size = 4096 * 16 * params->nr_blocks; return flash; } diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/st_smi.c index 6d4257a3f5..7507e5d077 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/st_smi.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. * * See file CREDITS for list of people who contributed to this * project. @@ -24,10 +24,10 @@ #include <common.h> #include <flash.h> #include <linux/err.h> +#include <linux/mtd/st_smi.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_smi.h> #if !defined(CONFIG_SYS_NO_FLASH) @@ -37,19 +37,61 @@ static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_ADDR_BASE; flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -#define ST_M25Pxx_ID 0x00002020 - -static struct flash_dev flash_ids[] = { - {0x10, 0x10000, 2}, /* 64K Byte */ - {0x11, 0x20000, 4}, /* 128K Byte */ - {0x12, 0x40000, 4}, /* 256K Byte */ - {0x13, 0x80000, 8}, /* 512K Byte */ - {0x14, 0x100000, 16}, /* 1M Byte */ - {0x15, 0x200000, 32}, /* 2M Byte */ - {0x16, 0x400000, 64}, /* 4M Byte */ - {0x17, 0x800000, 128}, /* 8M Byte */ - {0x18, 0x1000000, 64}, /* 16M Byte */ - {0x00,} +/* data structure to maintain flash ids from different vendors */ +struct flash_device { + char *name; + u8 erase_cmd; + u32 device_id; + u32 pagesize; + unsigned long sectorsize; + unsigned long size_in_bytes; +}; + +#define FLASH_ID(n, es, id, psize, ssize, size) \ +{ \ + .name = n, \ + .erase_cmd = es, \ + .device_id = id, \ + .pagesize = psize, \ + .sectorsize = ssize, \ + .size_in_bytes = size \ +} + +/* + * List of supported flash devices. + * Currently the erase_cmd field is not used in this driver. + */ +static struct flash_device flash_devices[] = { + FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000), + FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000), + FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000), + FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000), + FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000), + FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000), + FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000), + FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000), + FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000), + FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000), + FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000), + FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000), + FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000), + FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000), + FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000), + FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000), + FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000), + FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000), + FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000), + FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000), + FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000), + FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), + FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), + FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000), + FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000), + FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000), + FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), + FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), + FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000), + FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000), }; /* @@ -58,13 +100,19 @@ static struct flash_dev flash_ids[] = { * * Wait until TFF is set in status register */ -static void smi_wait_xfer_finish(int timeout) +static int smi_wait_xfer_finish(int timeout) { - while (timeout--) { + ulong start = get_timer(0); + + while (get_timer(start) < timeout) { if (readl(&smicntl->smi_sr) & TFF) - break; - udelay(1000); - } + return 0; + + /* Try after 10 ms */ + udelay(10); + }; + + return -1; } /* @@ -82,7 +130,9 @@ static unsigned int smi_read_id(flash_info_t *info, int banknum) writel(READ_ID, &smicntl->smi_tr); writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO; value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); @@ -103,30 +153,30 @@ static unsigned int smi_read_id(flash_info_t *info, int banknum) static ulong flash_get_size(ulong base, int banknum) { flash_info_t *info = &flash_info[banknum]; - struct flash_dev *dev; - unsigned int value; - unsigned int density; + int value; int i; value = smi_read_id(info, banknum); - density = (value >> 16) & 0xff; - - for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; - i++, dev = &flash_ids[i]) { - if (dev->density == density) { - info->size = dev->size; - info->sector_count = dev->sector_count; - break; - } - } - if (dev->density == 0x0) + if (value < 0) { + printf("Flash id could not be read\n"); return 0; + } - info->flash_id = value & 0xffff; - info->start[0] = base; + /* Matches chip-id to entire list of 'serial-nor flash' ids */ + for (i = 0; i < ARRAY_SIZE(flash_devices); i++) { + if (flash_devices[i].device_id == value) { + info->size = flash_devices[i].size_in_bytes; + info->flash_id = value; + info->start[0] = base; + info->sector_count = + info->size/flash_devices[i].sectorsize; - return info->size; + return info->size; + } + } + + return 0; } /* @@ -136,9 +186,9 @@ static ulong flash_get_size(ulong base, int banknum) * This routine will get the status register of the flash chip present at the * given bank */ -static unsigned int smi_read_sr(int bank) +static int smi_read_sr(int bank) { - u32 ctrlreg1; + u32 ctrlreg1, val; /* store the CTRL REG1 state */ ctrlreg1 = readl(&smicntl->smi_cr1); @@ -150,12 +200,15 @@ static unsigned int smi_read_sr(int bank) /* Performing a RSR instruction in HW mode */ writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1; + + val = readl(&smicntl->smi_sr); /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); - return readl(&smicntl->smi_sr); + return val; } /* @@ -169,22 +222,20 @@ static unsigned int smi_read_sr(int bank) */ static int smi_wait_till_ready(int bank, int timeout) { - int count; - unsigned int sr; + int sr; + ulong start = get_timer(0); /* One chip guarantees max 5 msec wait here after page writes, but potentially three seconds (!) after page erase. */ - for (count = 0; count < timeout; count++) { - + while (get_timer(start) < timeout) { sr = smi_read_sr(bank); - if (sr < 0) - break; - else if (!(sr & WIP_BIT)) + if ((sr >= 0) && (!(sr & WIP_BIT))) return 0; - /* Try again after 1m-sec */ - udelay(1000); - } + /* Try again after 10 usec */ + udelay(10); + } while (timeout--); + printf("SMI controller is still in wait, timeout=%d\n", timeout); return -EIO; } @@ -199,7 +250,9 @@ static int smi_wait_till_ready(int bank, int timeout) static int smi_write_enable(int bank) { u32 ctrlreg1; + u32 start; int timeout = WMODE_TOUT; + int sr; /* Store the CTRL REG1 state */ ctrlreg1 = readl(&smicntl->smi_cr1); @@ -210,19 +263,21 @@ static int smi_write_enable(int bank) /* Give the Flash, Write Enable command */ writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1; /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); - while (timeout--) { - if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) - break; - udelay(1000); - } + start = get_timer(0); + while (get_timer(start) < timeout) { + sr = smi_read_sr(bank); + if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) + return 0; - if (timeout) - return 0; + /* Try again after 10 usec */ + udelay(10); + }; return -1; } @@ -232,7 +287,7 @@ static int smi_write_enable(int bank) * * SMI initialization routine. Sets SMI control register1. */ -static void smi_init(void) +void smi_init(void) { /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, @@ -275,45 +330,39 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); - if (info->flash_id == ST_M25Pxx_ID) { - /* Wait until finished previous write command. */ - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; + /* Wait until finished previous write command. */ + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; - /* Send write enable, before erase commands. */ - if (smi_write_enable(bank)) - return -EIO; + /* Send write enable, before erase commands. */ + if (smi_write_enable(bank)) + return -EIO; - /* Put SMI in SW mode */ - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); + /* Put SMI in SW mode */ + writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - /* Send Sector Erase command in SW Mode */ - writel(instruction, &smicntl->smi_tr); - writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, + /* Send Sector Erase command in SW Mode */ + writel(instruction, &smicntl->smi_tr); + writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO; - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; + if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) + return -EBUSY; - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, + /* Put SMI in HW mode */ + writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - return 0; - } else { - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, - &smicntl->smi_cr1); - return -EINVAL; - } + return 0; } /* * smi_write - Write to SMI flash * @src_addr: source buffer * @dst_addr: destination buffer - * @length: length to write in words + * @length: length to write in bytes * @bank: bank base address * * Write to SMI flash @@ -321,7 +370,10 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, unsigned int length, ulong bank_addr) { + u8 *src_addr8 = (u8 *)src_addr; + u8 *dst_addr8 = (u8 *)dst_addr; int banknum; + int i; switch (bank_addr) { case SMIBANK0_BASE: @@ -350,7 +402,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -EIO; /* Perform the write command */ - while (length--) { + for (i = 0; i < length; i += 4) { if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) @@ -360,7 +412,18 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, return -EIO; } - *dst_addr++ = *src_addr++; + if (length < 4) { + int k; + + /* + * Handle special case, where length < 4 (redundant env) + */ + for (k = 0; k < length; k++) + *dst_addr8++ = *src_addr8++; + } else { + /* Normal 32bit write */ + *dst_addr++ = *src_addr++; + } if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) return -EIO; @@ -386,7 +449,7 @@ static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) { return smi_write((unsigned int *)src, (unsigned int *)dest_addr, - (length + 3) / 4, info->start[0]); + length, info->start[0]); } /* @@ -429,8 +492,13 @@ void flash_print_info(flash_info_t *info) puts("missing or unknown FLASH type\n"); return; } - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); + + if (info->size >= 0x100000) + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + else + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); puts(" Sector Start Addresses:"); for (i = 0; i < info->sector_count; ++i) { @@ -483,11 +551,6 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) int prot = 0; flash_sect_t sect; - if (info->flash_id != ST_M25Pxx_ID) { - puts("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { puts("- no sectors to erase\n"); return 1; diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index e24ac4a174..c63398ebf8 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -190,8 +190,7 @@ static int bfin_EMAC_recv(struct eth_device *dev) debug("%s: len = %d\n", __func__, length - 4); - NetRxPackets[rxIdx] = - (volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest); + NetRxPackets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest; NetReceive(NetRxPackets[rxIdx], length - 4); bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR); rxbuf[rxIdx]->StatusWord = 0x00000000; diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index e471d2ce33..b2516d1768 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -895,5 +895,13 @@ int davinci_emac_initialize(void) miiphy_register(phy[i].name, davinci_mii_phy_read, davinci_mii_phy_write); } + +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ + defined(CONFIG_MACH_DAVINCI_DA850_EVM) + for (i = 0; i < num_phy; i++) { + if (phy[i].is_phy_connected(i)) + phy[i].auto_negotiate(i); + } +#endif return(1); } diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9b17db41f6..bf21a08bdf 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -28,6 +28,7 @@ #include <common.h> #include <miiphy.h> #include <malloc.h> +#include <linux/compiler.h> #include <linux/err.h> #include <asm/io.h> #include "designware.h" @@ -153,6 +154,13 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) if (priv->phy_configured != 1) configure_phy(dev); + /* Print link status only once */ + if (!priv->link_printed) { + printf("ENET Speed is %d Mbps - %s duplex connection\n", + priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); + priv->link_printed = 1; + } + /* Reset ethernet hardware */ if (mac_reset(dev) < 0) return -1; @@ -163,15 +171,22 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); - writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | + TXSECONDFRAME, &dma_p->opmode); conf = FRAMEBURSTENABLE | DISABLERXOWN; - if (priv->speed != SPEED_1000M) + if (priv->speed != 1000) conf |= MII_PORTSELECT; - if (priv->duplex == FULL_DUPLEX) + if ((priv->interface != PHY_INTERFACE_MODE_MII) && + (priv->interface != PHY_INTERFACE_MODE_GMII)) { + + if (priv->speed == 100) + conf |= FES_100; + } + + if (priv->duplex == FULL) conf |= FULLDPLXMODE; writel(conf, &mac_p->conf); @@ -389,6 +404,16 @@ static int dw_reset_phy(struct eth_device *dev) return 0; } +/* + * Add weak default function for board specific PHY configuration + */ +int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) +{ + return 0; +} + static int configure_phy(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; @@ -398,9 +423,6 @@ static int configure_phy(struct eth_device *dev) u16 bmsr; u32 timeout; ulong start; - u16 anlpar, btsr; -#else - u16 ctrl; #endif #if defined(CONFIG_DW_SEARCH_PHY) @@ -412,6 +434,16 @@ static int configure_phy(struct eth_device *dev) #else phy_addr = priv->address; #endif + + /* + * Some boards need board specific PHY initialization. This is + * after the main driver init code but before the auto negotiation + * is run. + */ + if (designware_board_phy_init(dev, phy_addr, + eth_mdio_write, dw_reset_phy) < 0) + return -1; + if (dw_reset_phy(dev) < 0) return -1; @@ -437,72 +469,32 @@ static int configure_phy(struct eth_device *dev) #if defined(CONFIG_DW_AUTONEG) timeout = CONFIG_AUTONEG_TIMEOUT; start = get_timer(0); - + puts("Waiting for PHY auto negotiation to complete"); while (get_timer(start) < timeout) { eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) + if (bmsr & BMSR_ANEGCOMPLETE) { + priv->phy_configured = 1; break; - - /* Try again after 10usec */ - udelay(10); - }; - - eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar); - eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr); - - if (bmsr & BMSR_ANEGCOMPLETE) { - if (btsr & PHY_1000BTSR_1000FD) { - priv->speed = SPEED_1000M; - bmcr |= BMCR_SPEED1000; - priv->duplex = FULL_DUPLEX; - bmcr |= BMCR_FULLDPLX; - } else if (btsr & PHY_1000BTSR_1000HD) { - priv->speed = SPEED_1000M; - bmcr |= BMCR_SPEED1000; - priv->duplex = HALF_DUPLEX; - bmcr &= ~BMCR_FULLDPLX; - } else if (anlpar & LPA_100FULL) { - priv->speed = SPEED_100M; - bmcr |= BMCR_SPEED100; - priv->duplex = FULL_DUPLEX; - bmcr |= BMCR_FULLDPLX; - } else if (anlpar & LPA_100HALF) { - priv->speed = SPEED_100M; - bmcr |= BMCR_SPEED100; - priv->duplex = HALF_DUPLEX; - bmcr &= ~BMCR_FULLDPLX; - } else if (anlpar & LPA_10FULL) { - priv->speed = SPEED_10M; - bmcr &= ~BMCR_SPEED100; - priv->duplex = FULL_DUPLEX; - bmcr |= BMCR_FULLDPLX; - } else { - priv->speed = SPEED_10M; - bmcr &= ~BMCR_SPEED100; - priv->duplex = HALF_DUPLEX; - bmcr &= ~BMCR_FULLDPLX; } - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - } else - return -1; -#else - if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0) - return -1; - if (ctrl & BMCR_FULLDPLX) - priv->duplex = FULL_DUPLEX; - else - priv->duplex = HALF_DUPLEX; + /* Print dot all 1s to show progress */ + if ((get_timer(start) % 1000) == 0) + putc('.'); - if (ctrl & BMCR_SPEED1000) - priv->speed = SPEED_1000M; - else if (ctrl & BMCR_SPEED100) - priv->speed = SPEED_100M; + /* Try again after 1msec */ + udelay(1000); + }; + + if (!(bmsr & BMSR_ANEGCOMPLETE)) + puts(" TIMEOUT!\n"); else - priv->speed = SPEED_10M; -#endif + puts(" done\n"); +#else priv->phy_configured = 1; +#endif + + priv->speed = miiphy_speed(dev->name, phy_addr); + priv->duplex = miiphy_duplex(dev->name, phy_addr); return 0; } @@ -531,7 +523,7 @@ static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) } #endif -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -565,11 +557,7 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) DW_DMA_BASE_OFFSET); priv->address = phy_addr; priv->phy_configured = 0; - - if (mac_reset(dev) < 0) - return -1; - - configure_phy(dev); + priv->interface = interface; dev->init = dw_eth_init; dev->send = dw_eth_send; diff --git a/drivers/net/designware.h b/drivers/net/designware.h index abf729d57d..d668f8fbf0 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -234,11 +234,13 @@ struct dmamacdescr { struct dw_eth_dev { u32 address; + u32 interface; u32 speed; u32 duplex; u32 tx_currdescnum; u32 rx_currdescnum; u32 phy_configured; + int link_printed; u32 padding; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index eee41d7c8b..fbfc842aca 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -424,14 +424,12 @@ static void fec_reg_setup(struct fec_priv *fec) /* Start with frame length = 1518, common for all modes. */ rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; - if (fec->xcv_type == SEVENWIRE) - rcntrl |= FEC_RCNTRL_FCE; - else if (fec->xcv_type == RGMII) + if (fec->xcv_type != SEVENWIRE) /* xMII modes */ + rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; + if (fec->xcv_type == RGMII) rcntrl |= FEC_RCNTRL_RGMII; else if (fec->xcv_type == RMII) rcntrl |= FEC_RCNTRL_RMII; - else /* MII mode */ - rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; writel(rcntrl, &fec->eth->r_cntrl); } @@ -510,7 +508,13 @@ static int fec_open(struct eth_device *edev) fec_eth_phy_config(edev); if (fec->phydev) { /* Start up the PHY */ - phy_startup(fec->phydev); + int ret = phy_startup(fec->phydev); + + if (ret) { + printf("Could not initialize PHY %s\n", + fec->phydev->dev->name); + return ret; + } speed = fec->phydev->speed; } else { speed = _100BASET; @@ -599,7 +603,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) fec_reg_setup(fec); - if (fec->xcv_type == MII10 || fec->xcv_type == MII100) + if (fec->xcv_type != SEVENWIRE) fec_mii_setspeed(fec); /* diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index f34f4db6b6..2b616adb6e 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -363,6 +363,9 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd) { struct fm_eth *fm_eth; struct fsl_enet_mac *mac; +#ifdef CONFIG_PHYLIB + int ret; +#endif fm_eth = (struct fm_eth *)dev->priv; mac = fm_eth->mac; @@ -384,7 +387,11 @@ static int fm_eth_open(struct eth_device *dev, bd_t *bd) fmc_tx_port_graceful_stop_disable(fm_eth); #ifdef CONFIG_PHYLIB - phy_startup(fm_eth->phydev); + ret = phy_startup(fm_eth->phydev); + if (ret) { + printf("%s: Could not initialize\n", fm_eth->phydev->dev->name); + return ret; + } #else fm_eth->phydev->speed = SPEED_1000; fm_eth->phydev->link = 1; diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index e3043dfa20..30f3264897 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -35,6 +35,12 @@ static struct phy_driver KSZ804_driver = { .shutdown = &genphy_shutdown, }; +#ifndef CONFIG_PHY_MICREL_KSZ9021 +/* + * I can't believe Micrel used the exact same part number + * for the KSZ9021 + * Shame Micrel, Shame!!!!! + */ static struct phy_driver KS8721_driver = { .name = "Micrel KS8721BL", .uid = 0x221610, @@ -44,7 +50,9 @@ static struct phy_driver KS8721_driver = { .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; +#endif +#ifdef CONFIG_PHY_MICREL_KSZ9021 /* ksz9021 PHY Registers */ #define MII_KSZ9021_EXTENDED_CTRL 0x0b #define MII_KSZ9021_EXTENDED_DATAW 0x0c @@ -127,12 +135,15 @@ static struct phy_driver ksz9021_driver = { .startup = &ksz9021_startup, .shutdown = &genphy_shutdown, }; +#endif int phy_micrel_init(void) { phy_register(&KSZ804_driver); - phy_register(&KS8721_driver); +#ifdef CONFIG_PHY_MICREL_KSZ9021 phy_register(&ksz9021_driver); - +#else + phy_register(&KS8721_driver); +#endif return 0; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 7d327f766a..baef60f827 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -723,10 +723,13 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, return phydev; } +/* + * Start the PHY. Returns 0 on success, or a negative error code. + */ int phy_startup(struct phy_device *phydev) { if (phydev->drv->startup) - phydev->drv->startup(phydev); + return phydev->drv->startup(phydev); return 0; } diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index bb57e4d53a..09af8606db 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -1,5 +1,5 @@ /* - * sh_eth.c - Driver for Renesas SH7763's ethernet controler. + * sh_eth.c - Driver for Renesas ethernet controler. * * Copyright (C) 2008, 2011 Renesas Solutions Corp. * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu @@ -76,8 +76,8 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len) port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; /* Restart the transmitter if disabled */ - if (!(inl(EDTRR(port)) & EDTRR_TRNS)) - outl(EDTRR_TRNS, EDTRR(port)); + if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS)) + sh_eth_write(eth, EDTRR_TRNS, EDTRR); /* Wait until packet is transmitted */ timeout = TIMEOUT_CNT; @@ -129,25 +129,24 @@ int sh_eth_recv(struct eth_device *dev) } /* Restart the receiver if disabled */ - if (!(inl(EDRRR(port)) & EDRRR_R)) - outl(EDRRR_R, EDRRR(port)); + if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) + sh_eth_write(eth, EDRRR_R, EDRRR); return len; } static int sh_eth_reset(struct sh_eth_dev *eth) { - int port = eth->port; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) int ret = 0, i; /* Start e-dmac transmitter and receiver */ - outl(EDSR_ENALL, EDSR(port)); + sh_eth_write(eth, EDSR_ENALL, EDSR); /* Perform a software reset and wait for it to complete */ - outl(EDMR_SRST, EDMR(port)); + sh_eth_write(eth, EDMR_SRST, EDMR); for (i = 0; i < TIMEOUT_CNT ; i++) { - if (!(inl(EDMR(port)) & EDMR_SRST)) + if (!(sh_eth_read(eth, EDMR) & EDMR_SRST)) break; udelay(1000); } @@ -159,9 +158,9 @@ static int sh_eth_reset(struct sh_eth_dev *eth) return ret; #else - outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port)); + sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR); udelay(3000); - outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port)); + sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR); return 0; #endif @@ -207,11 +206,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) /* Point the controller to the tx descriptor list. Must use physical addresses */ - outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port)); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) - outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port)); - outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port)); - outl(0x01, TDFFR(port));/* Last discriptor bit */ + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR); + sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */ #endif err: @@ -275,11 +274,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) cur_rx_desc->rd0 |= RD_RDLE; /* Point the controller to the rx descriptor list */ - outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port)); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) - outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port)); - outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port)); - outl(RDFFR_RDLF, RDFFR(port)); + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); + sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR); + sh_eth_write(eth, RDFFR_RDLF, RDFFR); #endif return ret; @@ -364,49 +363,39 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) struct phy_device *phy; /* Configure e-dmac registers */ - outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); - outl(0, EESIPR(port)); - outl(0, TRSCER(port)); - outl(0, TFTR(port)); - outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port)); - outl(RMCR_RST, RMCR(port)); -#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) - outl(0, RPADIR(port)); + sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, + EDMR); + sh_eth_write(eth, 0, EESIPR); + sh_eth_write(eth, 0, TRSCER); + sh_eth_write(eth, 0, TFTR); + sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); + sh_eth_write(eth, RMCR_RST, RMCR); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, 0, RPADIR); #endif - outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port)); + sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); /* Configure e-mac registers */ -#if defined(CONFIG_CPU_SH7757) - outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | - ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port)); -#else - outl(0, ECSIPR(port)); -#endif + sh_eth_write(eth, 0, ECSIPR); /* Set Mac address */ val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; - outl(val, MAHR(port)); + sh_eth_write(eth, val, MAHR); val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; - outl(val, MALR(port)); - - outl(RFLR_RFL_MIN, RFLR(port)); -#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) - outl(0, PIPR(port)); -#endif -#if !defined(CONFIG_CPU_SH7724) - outl(APR_AP, APR(port)); - outl(MPR_MP, MPR(port)); -#endif -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) - outl(TPAUSER_TPAUSE, TPAUSER(port)); -#elif defined(CONFIG_CPU_SH7757) - outl(TPAUSER_UNLIMITED, TPAUSER(port)); + sh_eth_write(eth, val, MALR); + + sh_eth_write(eth, RFLR_RFL_MIN, RFLR); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, 0, PIPR); + sh_eth_write(eth, APR_AP, APR); + sh_eth_write(eth, MPR_MP, MPR); + sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); #endif #if defined(CONFIG_CPU_SH7734) - outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port)); + sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); #endif /* Configure phy */ ret = sh_eth_phy_config(eth); @@ -415,42 +404,47 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) goto err_phy_cfg; } phy = port_info->phydev; - phy_startup(phy); + ret = phy_startup(phy); + if (ret) { + printf(SHETHER_NAME ": phy startup failure\n"); + return ret; + } val = 0; /* Set the transfer speed */ if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) - outl(GECMR_100B, GECMR(port)); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) - outl(1, RTRATE(port)); + sh_eth_write(eth, 1, RTRATE); #elif defined(CONFIG_CPU_SH7724) val = ECMR_RTM; #endif } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) - outl(GECMR_10B, GECMR(port)); +#if defined(SH_ETH_TYPE_GETHER) + sh_eth_write(eth, GECMR_10B, GECMR); #elif defined(CONFIG_CPU_SH7757) - outl(0, RTRATE(port)); + sh_eth_write(eth, 0, RTRATE); #endif } -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) else if (phy->speed == 1000) { printf(SHETHER_NAME ": 1000Base/"); - outl(GECMR_1000B, GECMR(port)); + sh_eth_write(eth, GECMR_1000B, GECMR); } #endif /* Check if full duplex mode is supported by the phy */ if (phy->duplex) { printf("Full\n"); - outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), + ECMR); } else { printf("Half\n"); - outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port)); + sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); } return ret; @@ -465,12 +459,12 @@ static void sh_eth_start(struct sh_eth_dev *eth) * Enable the e-dmac receiver only. The transmitter will be enabled when * we have something to transmit */ - outl(EDRRR_R, EDRRR(eth->port)); + sh_eth_write(eth, EDRRR_R, EDRRR); } static void sh_eth_stop(struct sh_eth_dev *eth) { - outl(~EDRRR_R, EDRRR(eth->port)); + sh_eth_write(eth, ~EDRRR_R, EDRRR); } int sh_eth_init(struct eth_device *dev, bd_t *bd) @@ -574,9 +568,8 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus) static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; - outl(inl(PIR(port)) | PIR_MMD, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR); return 0; } @@ -584,9 +577,8 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; - outl(inl(PIR(port)) & ~PIR_MMD, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR); return 0; } @@ -594,12 +586,11 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; if (v) - outl(inl(PIR(port)) | PIR_MDO, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR); else - outl(inl(PIR(port)) & ~PIR_MDO, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR); return 0; } @@ -607,9 +598,8 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; - *v = (inl(PIR(port)) & PIR_MDI) >> 3; + *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3; return 0; } @@ -617,12 +607,11 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { struct sh_eth_dev *eth = bus->priv; - int port = eth->port; if (v) - outl(inl(PIR(port)) | PIR_MDC, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR); else - outl(inl(PIR(port)) & ~PIR_MDC, PIR(port)); + sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR); return 0; } diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index a1ba68b1b4..3703c55a74 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -97,143 +97,208 @@ struct sh_eth_dev { struct sh_eth_info port_info[MAX_PORT_NUM]; }; -/* Register Address */ -#ifdef CONFIG_CPU_SH7763 -#define BASE_IO_ADDR 0xfee00000 +/* from linux/drivers/net/ethernet/renesas/sh_eth.h */ +enum { + /* E-DMAC registers */ + EDSR = 0, + EDMR, + EDTRR, + EDRRR, + EESR, + EESIPR, + TDLAR, + TDFAR, + TDFXR, + TDFFR, + RDLAR, + RDFAR, + RDFXR, + RDFFR, + TRSCER, + RMFCR, + TFTR, + FDR, + RMCR, + EDOCR, + TFUCR, + RFOCR, + FCFTR, + RPADIR, + TRIMD, + RBWAR, + TBRAR, + + /* Ether registers */ + ECMR, + ECSR, + ECSIPR, + PIR, + PSR, + RDMLR, + PIPR, + RFLR, + IPGR, + APR, + MPR, + PFTCR, + PFRCR, + RFCR, + RFCF, + TPAUSER, + TPAUSECR, + BCFR, + BCFRR, + GECMR, + BCULR, + MAHR, + MALR, + TROCR, + CDCR, + LCCR, + CNDCR, + CEFCR, + FRECR, + TSFRCR, + TLFRCR, + CERCR, + CEECR, + MAFCR, + RTRATE, + CSMR, + RMII_MII, + + /* This value must be written at last. */ + SH_ETH_MAX_REGISTER_OFFSET, +}; + +static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { + [EDSR] = 0x0000, + [EDMR] = 0x0400, + [EDTRR] = 0x0408, + [EDRRR] = 0x0410, + [EESR] = 0x0428, + [EESIPR] = 0x0430, + [TDLAR] = 0x0010, + [TDFAR] = 0x0014, + [TDFXR] = 0x0018, + [TDFFR] = 0x001c, + [RDLAR] = 0x0030, + [RDFAR] = 0x0034, + [RDFXR] = 0x0038, + [RDFFR] = 0x003c, + [TRSCER] = 0x0438, + [RMFCR] = 0x0440, + [TFTR] = 0x0448, + [FDR] = 0x0450, + [RMCR] = 0x0458, + [RPADIR] = 0x0460, + [FCFTR] = 0x0468, + [CSMR] = 0x04E4, + + [ECMR] = 0x0500, + [ECSR] = 0x0510, + [ECSIPR] = 0x0518, + [PIR] = 0x0520, + [PSR] = 0x0528, + [PIPR] = 0x052c, + [RFLR] = 0x0508, + [APR] = 0x0554, + [MPR] = 0x0558, + [PFTCR] = 0x055c, + [PFRCR] = 0x0560, + [TPAUSER] = 0x0564, + [GECMR] = 0x05b0, + [BCULR] = 0x05b4, + [MAHR] = 0x05c0, + [MALR] = 0x05c8, + [TROCR] = 0x0700, + [CDCR] = 0x0708, + [LCCR] = 0x0710, + [CEFCR] = 0x0740, + [FRECR] = 0x0748, + [TSFRCR] = 0x0750, + [TLFRCR] = 0x0758, + [RFCR] = 0x0760, + [CERCR] = 0x0768, + [CEECR] = 0x0770, + [MAFCR] = 0x0778, + [RMII_MII] = 0x0790, +}; -#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) - -#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) -#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014) -#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) -#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c) - -#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) -#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034) -#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) -#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c) - -#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400) -#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408) -#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410) -#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428) -#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430) -#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438) -#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448) -#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450) -#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458) -#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460) -#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468) -#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500) -#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508) -#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518) -#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520) -#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c) -#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554) -#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558) -#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564) -#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0) -#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8) -#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0) +static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { + [ECMR] = 0x0100, + [RFLR] = 0x0108, + [ECSR] = 0x0110, + [ECSIPR] = 0x0118, + [PIR] = 0x0120, + [PSR] = 0x0128, + [RDMLR] = 0x0140, + [IPGR] = 0x0150, + [APR] = 0x0154, + [MPR] = 0x0158, + [TPAUSER] = 0x0164, + [RFCF] = 0x0160, + [TPAUSECR] = 0x0168, + [BCFRR] = 0x016c, + [MAHR] = 0x01c0, + [MALR] = 0x01c8, + [TROCR] = 0x01d0, + [CDCR] = 0x01d4, + [LCCR] = 0x01d8, + [CNDCR] = 0x01dc, + [CEFCR] = 0x01e4, + [FRECR] = 0x01e8, + [TSFRCR] = 0x01ec, + [TLFRCR] = 0x01f0, + [RFCR] = 0x01f4, + [MAFCR] = 0x01f8, + [RTRATE] = 0x01fc, + + [EDMR] = 0x0000, + [EDTRR] = 0x0008, + [EDRRR] = 0x0010, + [TDLAR] = 0x0018, + [RDLAR] = 0x0020, + [EESR] = 0x0028, + [EESIPR] = 0x0030, + [TRSCER] = 0x0038, + [RMFCR] = 0x0040, + [TFTR] = 0x0048, + [FDR] = 0x0050, + [RMCR] = 0x0058, + [TFUCR] = 0x0064, + [RFOCR] = 0x0068, + [FCFTR] = 0x0070, + [RPADIR] = 0x0078, + [TRIMD] = 0x007c, + [RBWAR] = 0x00c8, + [RDFAR] = 0x00cc, + [TBRAR] = 0x00d4, + [TDFAR] = 0x00d8, +}; +/* Register Address */ +#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xfee00000 #elif defined(CONFIG_CPU_SH7757) +#if defined(CONFIG_SH_ETHER_USE_GETHER) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xfee00000 +#else +#define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xfef00000 - -#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018) -#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020) - -#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000) -#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008) -#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010) -#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028) -#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030) -#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038) -#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048) -#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050) -#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058) -#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070) -#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100) -#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108) -#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118) -#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120) -#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154) -#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158) -#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164) -#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0) -#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8) -#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc) - +#endif #elif defined(CONFIG_CPU_SH7724) +#define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xA4600000 - -#define TDLAR(port) (BASE_IO_ADDR + 0x0018) -#define RDLAR(port) (BASE_IO_ADDR + 0x0020) - -#define EDMR(port) (BASE_IO_ADDR + 0x0000) -#define EDTRR(port) (BASE_IO_ADDR + 0x0008) -#define EDRRR(port) (BASE_IO_ADDR + 0x0010) -#define EESR(port) (BASE_IO_ADDR + 0x0028) -#define EESIPR(port) (BASE_IO_ADDR + 0x0030) -#define TRSCER(port) (BASE_IO_ADDR + 0x0038) -#define TFTR(port) (BASE_IO_ADDR + 0x0048) -#define FDR(port) (BASE_IO_ADDR + 0x0050) -#define RMCR(port) (BASE_IO_ADDR + 0x0058) -#define FCFTR(port) (BASE_IO_ADDR + 0x0070) -#define ECMR(port) (BASE_IO_ADDR + 0x0100) -#define RFLR(port) (BASE_IO_ADDR + 0x0108) -#define ECSIPR(port) (BASE_IO_ADDR + 0x0118) -#define PIR(port) (BASE_IO_ADDR + 0x0120) -#define APR(port) (BASE_IO_ADDR + 0x0154) -#define MPR(port) (BASE_IO_ADDR + 0x0158) -#define TPAUSER(port) (BASE_IO_ADDR + 0x0164) -#define MAHR(port) (BASE_IO_ADDR + 0x01c0) -#define MALR(port) (BASE_IO_ADDR + 0x01c8) - -#elif defined(CONFIG_CPU_SH7734) -#define BASE_IO_ADDR 0xFEE00000 - -#define EDSR(port) (BASE_IO_ADDR) - -#define TDLAR(port) (BASE_IO_ADDR + 0x0010) -#define TDFAR(port) (BASE_IO_ADDR + 0x0014) -#define TDFXR(port) (BASE_IO_ADDR + 0x0018) -#define TDFFR(port) (BASE_IO_ADDR + 0x001c) -#define RDLAR(port) (BASE_IO_ADDR + 0x0030) -#define RDFAR(port) (BASE_IO_ADDR + 0x0034) -#define RDFXR(port) (BASE_IO_ADDR + 0x0038) -#define RDFFR(port) (BASE_IO_ADDR + 0x003c) - -#define EDMR(port) (BASE_IO_ADDR + 0x0400) -#define EDTRR(port) (BASE_IO_ADDR + 0x0408) -#define EDRRR(port) (BASE_IO_ADDR + 0x0410) -#define EESR(port) (BASE_IO_ADDR + 0x0428) -#define EESIPR(port) (BASE_IO_ADDR + 0x0430) -#define TRSCER(port) (BASE_IO_ADDR + 0x0438) -#define TFTR(port) (BASE_IO_ADDR + 0x0448) -#define FDR(port) (BASE_IO_ADDR + 0x0450) -#define RMCR(port) (BASE_IO_ADDR + 0x0458) -#define RPADIR(port) (BASE_IO_ADDR + 0x0460) -#define FCFTR(port) (BASE_IO_ADDR + 0x0468) -#define ECMR(port) (BASE_IO_ADDR + 0x0500) -#define RFLR(port) (BASE_IO_ADDR + 0x0508) -#define ECSIPR(port) (BASE_IO_ADDR + 0x0518) -#define PIR(port) (BASE_IO_ADDR + 0x0520) -#define PIPR(port) (BASE_IO_ADDR + 0x052c) -#define APR(port) (BASE_IO_ADDR + 0x0554) -#define MPR(port) (BASE_IO_ADDR + 0x0558) -#define TPAUSER(port) (BASE_IO_ADDR + 0x0564) -#define GECMR(port) (BASE_IO_ADDR + 0x05b0) -#define MAHR(port) (BASE_IO_ADDR + 0x05C0) -#define MALR(port) (BASE_IO_ADDR + 0x05C8) -#define RMII_MII(port) (BASE_IO_ADDR + 0x0790) - #endif /* * Register's bits * Copy from Linux driver source code */ -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) /* EDSR */ enum EDSR_BIT { EDSR_ENT = 0x01, EDSR_ENR = 0x02, @@ -244,15 +309,15 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) EDMR_SRST = 0x03, /* Receive/Send reset */ EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ -#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724) +#elif defined(SH_ETH_TYPE_ETHER) EDMR_SRST = 0x01, EMDR_DESC_R = 0x30, /* Descriptor reserve size */ EDMR_EL = 0x40, /* Litte endian */ -#else /* CONFIG_CPU_SH7763 */ +#else EDMR_SRST = 0x01, #endif }; @@ -262,7 +327,7 @@ enum DMAC_M_BIT { /* EDTRR */ enum DMAC_T_BIT { -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) EDTRR_TRNS = 0x03, #else EDTRR_TRNS = 0x01, @@ -271,7 +336,11 @@ enum DMAC_T_BIT { /* GECMR */ enum GECMR_BIT { +#if defined(CONFIG_CPU_SH7757) + GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00, +#else GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00, +#endif }; /* EDRRR*/ @@ -302,7 +371,7 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, }; /* EESR */ enum EESR_BIT { -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) EESR_TWB = 0x40000000, #else EESR_TWB = 0xC0000000, @@ -312,14 +381,14 @@ enum EESR_BIT { #endif EESR_TABT = 0x04000000, EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) EESR_ADE = 0x00800000, #endif EESR_ECI = 0x00400000, EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, -#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) EESR_CND = 0x00000800, #endif EESR_DLC = 0x00000400, @@ -331,7 +400,7 @@ enum EESR_BIT { }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define TX_CHECK (EESR_TC1 | EESR_FTC) # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI) @@ -391,8 +460,7 @@ enum FCFTR_BIT { /* Transfer descriptor bit */ enum TD_STS_BIT { -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \ - || defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) TD_TACT = 0x80000000, #else TD_TACT = 0x7fffffff, @@ -408,7 +476,7 @@ enum TD_STS_BIT { enum RECV_RST_BIT { RMCR_RST = 0x01, }; /* ECMR */ enum FELIC_MODE_BIT { -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000, ECMR_RZPF = 0x00100000, #endif @@ -423,12 +491,10 @@ enum FELIC_MODE_BIT { }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \ ECMR_TXF | ECMR_MCT) -#elif CONFIG_CPU_SH7757 -#define ECMR_CHG_DM (ECMR_ZPF) -#elif CONFIG_CPU_SH7724 +#elif defined(SH_ETH_TYPE_ETHER) #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF) #else #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT) @@ -436,14 +502,14 @@ enum FELIC_MODE_BIT { /* ECSR */ enum ECSR_STATUS_BIT { -#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) +#if defined(SH_ETH_TYPE_ETHER) ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, #endif ECSR_LCHNG = 0x04, ECSR_MPD = 0x02, ECSR_ICD = 0x01, }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP) #else # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \ @@ -452,20 +518,19 @@ enum ECSR_STATUS_BIT { /* ECSIPR */ enum ECSIPR_STATUS_MASK_BIT { -#if defined(CONFIG_CPU_SH7724) +#if defined(SH_ETH_TYPE_ETHER) + ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, - ECSIPR_LCHNGIP = 0x04, - ECSIPR_ICDIP = 0x01, -#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#elif defined(SH_ETY_TYPE_GETHER) ECSIPR_PSRTOIP = 0x10, ECSIPR_PHYIP = 0x08, +#endif ECSIPR_LCHNGIP = 0x04, ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, -#endif }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP) #else # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \ @@ -474,20 +539,12 @@ enum ECSIPR_STATUS_MASK_BIT { /* APR */ enum APR_BIT { -#ifdef CONFIG_CPU_SH7757 - APR_AP = 0x00000001, -#else APR_AP = 0x00000004, -#endif }; /* MPR */ enum MPR_BIT { -#ifdef CONFIG_CPU_SH7757 - MPR_MP = 0x00000001, -#else MPR_MP = 0x00000006, -#endif }; /* TRSCER */ @@ -504,7 +561,7 @@ enum RPADIR_BIT { RPADIR_PADR = 0x0003f, }; -#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) +#if defined(SH_ETH_TYPE_GETHER) # define RPADIR_INIT (0x00) #else # define RPADIR_INIT (RPADIR_PADS1) @@ -514,3 +571,28 @@ enum RPADIR_BIT { enum FIFO_SIZE_BIT { FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, }; + +static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth, + int enum_index) +{ +#if defined(SH_ETH_TYPE_GETHER) + const u16 *reg_offset = sh_eth_offset_gigabit; +#elif defined(SH_ETH_TYPE_ETHER) + const u16 *reg_offset = sh_eth_offset_fast_sh4; +#else +#error +#endif + return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port; +} + +static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data, + int enum_index) +{ + outl(data, sh_eth_reg_addr(eth, enum_index)); +} + +static inline unsigned long sh_eth_read(struct sh_eth_dev *eth, + int enum_index) +{ + return inl(sh_eth_reg_addr(eth, enum_index)); +} diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3c1c8f0799..f5e314b9ee 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -480,6 +480,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; tsec_t *regs = priv->regs; + int ret; /* Make sure the controller is stopped */ tsec_halt(dev); @@ -511,7 +512,12 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) startup_tsec(dev); /* Start up the PHY */ - phy_startup(priv->phydev); + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } adjust_link(priv, priv->phydev); diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 7854a04cae..d77714440a 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -272,7 +272,11 @@ static int setup_phy(struct eth_device *dev) phydev->advertising = phydev->supported; priv->phydev = phydev; phy_config(phydev); - phy_startup(phydev); + if (phy_startup(phydev)) { + printf("axiemac: could not initialize PHY %s\n", + phydev->dev->name); + return 0; + } switch (phydev->speed) { case 1000: diff --git a/drivers/net/xilinx_ll_temac.c b/drivers/net/xilinx_ll_temac.c index 27dafc15c0..b67153bec8 100644 --- a/drivers/net/xilinx_ll_temac.c +++ b/drivers/net/xilinx_ll_temac.c @@ -232,6 +232,7 @@ static void ll_temac_halt(struct eth_device *dev) static int ll_temac_init(struct eth_device *dev, bd_t *bis) { struct ll_temac *ll_temac = dev->priv; + int ret; printf("%s: Xilinx XPS LocalLink Tri-Mode Ether MAC #%d at 0x%08X.\n", dev->name, dev->index, dev->iobase); @@ -240,7 +241,12 @@ static int ll_temac_init(struct eth_device *dev, bd_t *bis) return -1; /* Start up the PHY */ - phy_startup(ll_temac->phydev); + ret = phy_startup(ll_temac->phydev); + if (ret) { + printf("%s: Could not initialize PHY %s\n", + dev->name, ll_temac->phydev->dev->name); + return ret; + } if (!ll_temac_adjust_link(dev)) { ll_temac_halt(dev); diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 62c2446939..8721e7468a 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -63,6 +63,8 @@ #define M41T62_FEATURE_HT (1 << 0) #define M41T62_FEATURE_BL (1 << 1) +#define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ + int rtc_get(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; @@ -132,9 +134,15 @@ int rtc_set(struct rtc_time *tm) void rtc_reset(void) { + u8 val; + /* - * Nothing to do + * M41T82: Make sure HT (Halt Update) bit is cleared. + * This bit is 0 in M41T62 so its save to clear it always. */ + i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + val &= ~M41T80_ALHOUR_HT; + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } #endif diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3ae38e5907..cd3f9fa856 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -43,6 +43,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o +COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index db8ba8bdac..f4523a3929 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -34,16 +34,14 @@ static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE; +u32 cs_spi_mpp_back[2]; + struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct spi_slave *slave; u32 data; - u32 kwspi_mpp_config[] = { - MPP0_GPIO, - MPP7_SPI_SCn, - 0 - }; + u32 kwspi_mpp_config[] = { 0, 0 }; if (!spi_cs_is_valid(bus, cs)) return NULL; @@ -70,29 +68,75 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, /* program mpp registers to select SPI_CSn */ if (cs) { - kwspi_mpp_config[0] = MPP0_GPIO; - kwspi_mpp_config[1] = MPP7_SPI_SCn; + kwspi_mpp_config[0] = MPP7_SPI_SCn; } else { kwspi_mpp_config[0] = MPP0_SPI_SCn; - kwspi_mpp_config[1] = MPP7_GPO; } - kirkwood_mpp_conf(kwspi_mpp_config); + kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back); return slave; } void spi_free_slave(struct spi_slave *slave) { + kirkwood_mpp_conf(cs_spi_mpp_back, NULL); free(slave); } -int spi_claim_bus(struct spi_slave *slave) +#if defined(CONFIG_SYS_KW_SPI_MPP) +u32 spi_mpp_backup[4]; +#endif + +__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) { return 0; } +int spi_claim_bus(struct spi_slave *slave) +{ +#if defined(CONFIG_SYS_KW_SPI_MPP) + u32 config; + u32 spi_mpp_config[4]; + + config = CONFIG_SYS_KW_SPI_MPP; + + if (config & MOSI_MPP6) + spi_mpp_config[0] = MPP6_SPI_MOSI; + else + spi_mpp_config[0] = MPP1_SPI_MOSI; + + if (config & SCK_MPP10) + spi_mpp_config[1] = MPP10_SPI_SCK; + else + spi_mpp_config[1] = MPP2_SPI_SCK; + + if (config & MISO_MPP11) + spi_mpp_config[2] = MPP11_SPI_MISO; + else + spi_mpp_config[2] = MPP3_SPI_MISO; + + spi_mpp_config[3] = 0; + spi_mpp_backup[3] = 0; + + /* set new spi mpp and save current mpp config */ + kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); + +#endif + + return board_spi_claim_bus(slave); +} + +__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave) +{ +} + void spi_release_bus(struct spi_slave *slave) { +#if defined(CONFIG_SYS_KW_SPI_MPP) + kirkwood_mpp_conf(spi_mpp_backup, NULL); +#endif + + board_spi_release_bus(slave); } #ifndef CONFIG_SPI_CS_IS_VALID diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra_spi.c index 56cb22963d..4a3e7996f9 100644 --- a/drivers/spi/tegra2_spi.c +++ b/drivers/spi/tegra_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011 NVIDIA Corporation + * Copyright (c) 2010-2012 NVIDIA Corporation * With help from the mpc8xxx SPI driver * With more help from omap3_spi SPI driver * @@ -28,12 +28,17 @@ #include <spi.h> #include <asm/io.h> #include <asm/gpio.h> -#include <ns16550.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart-spi-switch.h> -#include <asm/arch/tegra2_spi.h> +#include <asm/arch/tegra_spi.h> + +#if defined(CONFIG_SPI_CORRUPTS_UART) + #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY); +#else + #define corrupt_delay() +#endif struct tegra_spi_slave { struct spi_slave slave; @@ -161,14 +166,20 @@ void spi_cs_activate(struct spi_slave *slave) /* CS is negated on Tegra, so drive a 1 to get a 0 */ setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); + + corrupt_delay(); /* Let UART settle */ } void spi_cs_deactivate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); + pinmux_select_uart(); + /* CS is negated on Tegra, so drive a 0 to get a 1 */ clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); + + corrupt_delay(); /* Let SPI settle */ } int spi_xfer(struct spi_slave *slave, unsigned int bitlen, diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index a3bf51a64d..8fb7fc8c90 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -168,27 +168,28 @@ static inline int asix_set_hw_mii(struct ueth_data *dev) static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc) { - __le16 res; + ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); asix_set_sw_mii(dev); - asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, &res); + asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, res); asix_set_hw_mii(dev); debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", - phy_id, loc, le16_to_cpu(res)); + phy_id, loc, le16_to_cpu(*res)); - return le16_to_cpu(res); + return le16_to_cpu(*res); } static void asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val) { - __le16 res = cpu_to_le16(val); + ALLOC_CACHE_ALIGN_BUFFER(__le16, res, 1); + *res = cpu_to_le16(val); debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", phy_id, loc, val); asix_set_sw_mii(dev); - asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res); + asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, res); asix_set_hw_mii(dev); } @@ -210,7 +211,8 @@ static int asix_sw_reset(struct ueth_data *dev, u8 flags) static inline int asix_get_phy_addr(struct ueth_data *dev) { - u8 buf[2]; + ALLOC_CACHE_ALIGN_BUFFER(u8, buf, 2); + int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf); debug("asix_get_phy_addr()\n"); @@ -242,13 +244,14 @@ static int asix_write_medium_mode(struct ueth_data *dev, u16 mode) static u16 asix_read_rx_ctl(struct ueth_data *dev) { - __le16 v; - int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v); + ALLOC_CACHE_ALIGN_BUFFER(__le16, v, 1); + + int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, v); if (ret < 0) debug("Error reading RX_CTL register: %02x\n", ret); else - ret = le16_to_cpu(v); + ret = le16_to_cpu(*v); return ret; } @@ -313,7 +316,7 @@ static int mii_nway_restart(struct ueth_data *dev) static int asix_init(struct eth_device *eth, bd_t *bd) { int embd_phy; - unsigned char buf[ETH_ALEN]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, ETH_ALEN); u16 rx_ctl; struct ueth_data *dev = (struct ueth_data *)eth->priv; int timeout = 0; @@ -425,7 +428,8 @@ static int asix_send(struct eth_device *eth, void *packet, int length) int err; u32 packet_len; int actual_len; - unsigned char msg[PKTSIZE + sizeof(packet_len)]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, + PKTSIZE + sizeof(packet_len)); debug("** %s(), len %d\n", __func__, length); @@ -452,7 +456,7 @@ static int asix_send(struct eth_device *eth, void *packet, int length) static int asix_recv(struct eth_device *eth) { struct ueth_data *dev = (struct ueth_data *)eth->priv; - static unsigned char recv_buf[AX_RX_URB_SIZE]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); unsigned char *buf_ptr; int err; int actual_len; diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index c7aebea4e3..c62a8c112e 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -153,13 +153,15 @@ static int curr_eth_dev; /* index for name of next device detected */ static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) { int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); cpu_to_le32s(&data); + tmpbuf[0] = data; len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0), USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - 00, index, &data, sizeof(data), USB_CTRL_SET_TIMEOUT); + 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT); if (len != sizeof(data)) { debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", index, data, len); @@ -171,11 +173,13 @@ static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data) static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data) { int len; + ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0), USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, - 00, index, data, sizeof(data), USB_CTRL_GET_TIMEOUT); + 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT); + *data = tmpbuf[0]; if (len != sizeof(data)) { debug("smsc95xx_read_reg failed: index=%d, len=%d", index, len); @@ -664,7 +668,8 @@ static int smsc95xx_send(struct eth_device *eth, void* packet, int length) int actual_len; u32 tx_cmd_a; u32 tx_cmd_b; - unsigned char msg[PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, + PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg); if (length > PKTSIZE) @@ -695,7 +700,7 @@ static int smsc95xx_send(struct eth_device *eth, void* packet, int length) static int smsc95xx_recv(struct eth_device *eth) { struct ueth_data *dev = (struct ueth_data *)eth->priv; - static unsigned char recv_buf[AX_RX_URB_SIZE]; + DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); unsigned char *buf_ptr; int err; int actual_len; diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 59c3e57563..6de91640d6 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -36,11 +36,13 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o # echi COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o +COBJS-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o ifdef CONFIG_MPC512X COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o else COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif +COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o @@ -50,7 +52,6 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o -COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c new file mode 100644 index 0000000000..15b9b60eb4 --- /dev/null +++ b/drivers/usb/host/ehci-atmel.c @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2012 + * Atmel Semiconductor <www.atmel.com> + * Written-by: Bo Shen <voice.shen@atmel.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> + +#include "ehci.h" +#include "ehci-core.h" + +/* Enable UTMI PLL time out 500us + * 10 times as datasheet specified + */ +#define EN_UPLL_TIMEOUT 500UL + +int ehci_hcd_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + start_time = get_timer(0); + /* Enable UTMI PLL */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) != AT91_PMC_LOCKU) { + WATCHDOG_RESET(); + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { + printf("ERROR: failed to enable UPLL\n"); + return -1; + } + } + + /* Enable USB Host clock */ + writel(1 << ATMEL_ID_UHPHS, &pmc->pcer); + + hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI; + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return 0; +} + +int ehci_hcd_stop(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + ulong start_time, tmp_time; + + /* Disable USB Host Clock */ + writel(1 << ATMEL_ID_UHPHS, &pmc->pcdr); + + start_time = get_timer(0); + /* Disable UTMI PLL */ + writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr); + while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) { + WATCHDOG_RESET(); + tmp_time = get_timer(0); + if ((tmp_time - start_time) > EN_UPLL_TIMEOUT) { + printf("ERROR: failed to stop UPLL\n"); + return -1; + } + } + + return 0; +} diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-exynos.c index 4dd4ec168f..a71b3977d8 100644 --- a/drivers/usb/host/ehci-s5p.c +++ b/drivers/usb/host/ehci-exynos.c @@ -1,5 +1,5 @@ /* - * SAMSUNG S5P USB HOST EHCI Controller + * SAMSUNG EXYNOS USB HOST EHCI Controller * * Copyright (C) 2012 Samsung Electronics Co.Ltd * Vivek Gautam <gautam.vivek@samsung.com> @@ -23,13 +23,19 @@ #include <common.h> #include <usb.h> #include <asm/arch/cpu.h> -#include <asm/arch/ehci-s5p.h> +#include <asm/arch/ehci.h> +#include <asm/arch/system.h> +#include <asm/arch/power.h> #include "ehci.h" #include "ehci-core.h" /* Setup the EHCI host controller. */ -static void setup_usb_phy(struct s5p_usb_phy *usb) +static void setup_usb_phy(struct exynos_usb_phy *usb) { + set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN); + + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN); + clrbits_le32(&usb->usbphyctrl0, HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N | @@ -61,7 +67,7 @@ static void setup_usb_phy(struct s5p_usb_phy *usb) } /* Reset the EHCI host controller. */ -static void reset_usb_phy(struct s5p_usb_phy *usb) +static void reset_usb_phy(struct exynos_usb_phy *usb) { /* HOST_PHY reset */ setbits_le32(&usb->usbphyctrl0, @@ -70,6 +76,8 @@ static void reset_usb_phy(struct s5p_usb_phy *usb) HOST_CTRL0_SIDDQ | HOST_CTRL0_FORCESUSPEND | HOST_CTRL0_FORCESLEEP); + + set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE); } /* @@ -79,12 +87,12 @@ static void reset_usb_phy(struct s5p_usb_phy *usb) */ int ehci_hcd_init(void) { - struct s5p_usb_phy *usb; + struct exynos_usb_phy *usb; - usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); + usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); setup_usb_phy(usb); - hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE); + hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci(); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); @@ -101,9 +109,9 @@ int ehci_hcd_init(void) */ int ehci_hcd_stop() { - struct s5p_usb_phy *usb; + struct exynos_usb_phy *usb; - usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy(); + usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); reset_usb_phy(usb); return 0; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 04300be110..2a82a29125 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -34,7 +34,10 @@ struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ volatile struct ehci_hcor *hcor; static uint16_t portreset; -static struct QH qh_list __attribute__((aligned(32))); +DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN); + +#define ALIGN_END_ADDR(type, ptr, size) \ + ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN)) static struct descriptor { struct usb_hub_descriptor hub; @@ -172,18 +175,15 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) { uint32_t delta, next; uint32_t addr = (uint32_t)buf; - size_t rsz = roundup(sz, 32); int idx; - if (sz != rsz) - debug("EHCI-HCD: Misaligned buffer size (%08x)\n", sz); - - if (addr & 31) + if (addr != ALIGN(addr, ARCH_DMA_MINALIGN)) debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf); + flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN)); + idx = 0; while (idx < 5) { - flush_dcache_range(addr, addr + rsz); td->qt_buffer[idx] = cpu_to_hc32(addr); td->qt_buffer_hi[idx] = 0; next = (addr + 4096) & ~4095; @@ -196,7 +196,7 @@ static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) } if (idx == 5) { - debug("out of buffer pointers (%u bytes left)\n", sz); + printf("out of buffer pointers (%u bytes left)\n", sz); return -1; } @@ -207,8 +207,8 @@ static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) { - static struct QH qh __attribute__((aligned(32))); - static struct qTD qtd[3] __attribute__((aligned (32))); + ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN); + ALLOC_ALIGN_BUFFER(struct qTD, qtd, 3, USB_DMA_MINALIGN); int qtd_counter = 0; volatile struct qTD *vtd; @@ -229,8 +229,8 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, le16_to_cpu(req->value), le16_to_cpu(req->value), le16_to_cpu(req->index)); - memset(&qh, 0, sizeof(struct QH)); - memset(qtd, 0, sizeof(qtd)); + memset(qh, 0, sizeof(struct QH)); + memset(qtd, 0, 3 * sizeof(*qtd)); toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); @@ -244,7 +244,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, * qh_overlay.qt_next ...... 13-10 H * - qh_overlay.qt_altnext */ - qh.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); + qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && usb_pipeendpoint(pipe) == 0) ? 1 : 0; endpt = (8 << 28) | @@ -255,14 +255,14 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, (usb_pipespeed(pipe) << 12) | (usb_pipeendpoint(pipe) << 8) | (0 << 7) | (usb_pipedevice(pipe) << 0); - qh.qh_endpt1 = cpu_to_hc32(endpt); + qh->qh_endpt1 = cpu_to_hc32(endpt); endpt = (1 << 30) | (dev->portnr << 23) | (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); - qh.qh_endpt2 = cpu_to_hc32(endpt); - qh.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + qh->qh_endpt2 = cpu_to_hc32(endpt); + qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); - tdp = &qh.qh_overlay.qt_next; + tdp = &qh->qh_overlay.qt_next; if (req != NULL) { /* @@ -281,7 +281,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); qtd[qtd_counter].qt_token = cpu_to_hc32(token); if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req)) != 0) { - debug("unable construct SETUP td\n"); + printf("unable construct SETUP td\n"); goto fail; } /* Update previous qTD! */ @@ -310,7 +310,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); qtd[qtd_counter].qt_token = cpu_to_hc32(token); if (ehci_td_buffer(&qtd[qtd_counter], buffer, length) != 0) { - debug("unable construct DATA td\n"); + printf("unable construct DATA td\n"); goto fail; } /* Update previous qTD! */ @@ -340,13 +340,16 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, tdp = &qtd[qtd_counter++].qt_next; } - qh_list.qh_link = cpu_to_hc32((uint32_t)&qh | QH_LINK_TYPE_QH); + qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH); /* Flush dcache */ - flush_dcache_range((uint32_t)&qh_list, - (uint32_t)&qh_list + sizeof(struct QH)); - flush_dcache_range((uint32_t)&qh, (uint32_t)&qh + sizeof(struct QH)); - flush_dcache_range((uint32_t)qtd, (uint32_t)qtd + sizeof(qtd)); + flush_dcache_range((uint32_t)qh_list, + ALIGN_END_ADDR(struct QH, qh_list, 1)); + flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1)); + flush_dcache_range((uint32_t)qtd, ALIGN_END_ADDR(struct qTD, qtd, 3)); + + /* Set async. queue head pointer. */ + ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list); usbsts = ehci_readl(&hcor->or_usbsts); ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); @@ -369,12 +372,12 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, timeout = USB_TIMEOUT_MS(pipe); do { /* Invalidate dcache */ - invalidate_dcache_range((uint32_t)&qh_list, - (uint32_t)&qh_list + sizeof(struct QH)); - invalidate_dcache_range((uint32_t)&qh, - (uint32_t)&qh + sizeof(struct QH)); + invalidate_dcache_range((uint32_t)qh_list, + ALIGN_END_ADDR(struct QH, qh_list, 1)); + invalidate_dcache_range((uint32_t)qh, + ALIGN_END_ADDR(struct QH, qh, 1)); invalidate_dcache_range((uint32_t)qtd, - (uint32_t)qtd + sizeof(qtd)); + ALIGN_END_ADDR(struct qTD, qtd, 3)); token = hc32_to_cpu(vtd->qt_token); if (!(token & 0x80)) @@ -382,9 +385,17 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, WATCHDOG_RESET(); } while (get_timer(ts) < timeout); - /* Invalidate the memory area occupied by buffer */ - invalidate_dcache_range(((uint32_t)buffer & ~31), - ((uint32_t)buffer & ~31) + roundup(length, 32)); + /* + * Invalidate the memory area occupied by buffer + * Don't try to fix the buffer alignment, if it isn't properly + * aligned it's upper layer's fault so let invalidate_dcache_range() + * vow about it. But we have to fix the length as it's actual + * transfer length and can be unaligned. This is potentially + * dangerous operation, it's responsibility of the calling + * code to make sure enough space is reserved. + */ + invalidate_dcache_range((uint32_t)buffer, + ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN)); /* Check that the TD processing happened */ if (token & 0x80) { @@ -403,9 +414,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, goto fail; } - qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); - - token = hc32_to_cpu(qh.qh_overlay.qt_token); + token = hc32_to_cpu(qh->qh_overlay.qt_token); if (!(token & 0x80)) { debug("TOKEN=%#x\n", token); switch (token & 0xfc) { @@ -733,16 +742,13 @@ int usb_lowlevel_init(void) #endif /* Set head of reclaim list */ - memset(&qh_list, 0, sizeof(qh_list)); - qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); - qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); - qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); - qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); - qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); - qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40); - - /* Set async. queue head pointer. */ - ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list); + memset(qh_list, 0, sizeof(*qh_list)); + qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH); + qh_list->qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); + qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); + qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qh_list->qh_overlay.qt_token = cpu_to_hc32(0x40); reg = ehci_readl(&hccr->cr_hcsparams); descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 1ed77107eb..292673bf00 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -246,7 +246,6 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata) if (is_ehci_phy_mode(usbhs_pdata->port_mode[i])) omap_ehci_soft_phy_reset(i); - dcache_disable(); hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index a7e105b992..4646b29508 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009 NVIDIA Corporation + * Copyright (c) 2009-2012 NVIDIA Corporation * * See file CREDITS for list of people who contributed to this * project. @@ -29,6 +29,22 @@ #include <asm/errno.h> #include <asm/arch/usb.h> +/* + * A known hardware issue where Connect Status Change bit of PORTSC register + * of USB1 controller will be set after Port Reset. + * We have to clear it in order for later device enumeration to proceed. + * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup + * in "ehci-hcd.c". + */ +void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) +{ + mdelay(50); + if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE) + return; + /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */ + if (ehci_readl(status_reg) & EHCI_PS_CSC) + *reg |= EHCI_PS_CSC; +} /* * Create the appropriate control structures to manage diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index a8adcce00f..e914369297 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -145,7 +145,7 @@ struct musb_regs { struct musb_epN_regs epN; } ep[16]; -} __attribute__((packed, aligned(32))); +} __attribute__((packed, aligned(USB_DMA_MINALIGN))); #endif /* diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 44b7feb987..2f8e2b521a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -42,7 +42,7 @@ COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o -COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 92fa77d27f..19d061f6cb 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -164,7 +164,7 @@ /* * Defines for the i.MX31 driver (mx3fb.c) */ -#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_MX5) +#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_IPUV3) #define VIDEO_FB_16BPP_WORD_SWAP #endif diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c index a2981b18eb..30c19b3a43 100644 --- a/drivers/video/da8xx-fb.c +++ b/drivers/video/da8xx-fb.c @@ -121,7 +121,6 @@ struct da8xx_lcd_regs { #define LOWER_MARGIN 32 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP) -#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); }) static struct da8xx_lcd_regs *da8xx_fb_reg_base; diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 92be4ead36..49fdfec763 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -44,9 +44,6 @@ short console_row; static unsigned int panel_width, panel_height; -/* LCD Panel data */ -vidinfo_t panel_info; - static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) { unsigned long palette_size; diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 9d20c864ba..2020da98d2 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -163,6 +163,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent) static int clk_ipu_enable(struct clk *clk) { +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) u32 reg; reg = __raw_readl(clk->enable_reg); @@ -178,12 +179,13 @@ static int clk_ipu_enable(struct clk *clk) reg = __raw_readl(&mxc_ccm->clpcr); reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; __raw_writel(reg, &mxc_ccm->clpcr); - +#endif return 0; } static void clk_ipu_disable(struct clk *clk) { +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) u32 reg; reg = __raw_readl(clk->enable_reg); @@ -202,13 +204,14 @@ static void clk_ipu_disable(struct clk *clk) reg = __raw_readl(&mxc_ccm->clpcr); reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS; __raw_writel(reg, &mxc_ccm->clpcr); +#endif } static struct clk ipu_clk = { .name = "ipu_clk", - .rate = 133000000, - .enable_reg = (u32 *)(MXC_CCM_BASE + + .rate = CONFIG_IPUV3_CLK, + .enable_reg = (u32 *)(CCM_BASE_ADDR + offsetof(struct mxc_ccm_reg, CCGR5)), .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET, .enable = clk_ipu_enable, @@ -216,8 +219,15 @@ static struct clk ipu_clk = { .usecount = 0, }; +static struct clk ldb_clk = { + .name = "ldb_clk", + .rate = 65000000, + .usecount = 0, +}; + /* Globals */ struct clk *g_ipu_clk; +struct clk *g_ldb_clk; unsigned char g_ipu_clk_enabled; struct clk *g_di_clk[2]; struct clk *g_pixel_clk[2]; @@ -340,7 +350,7 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) if (parent == g_ipu_clk) di_gen &= ~DI_GEN_DI_CLK_EXT; - else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id]) + else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk) di_gen |= DI_GEN_DI_CLK_EXT; else return -EINVAL; @@ -401,6 +411,7 @@ void ipu_reset(void) int ipu_probe(void) { unsigned long ipu_base; +#if defined CONFIG_MX51 u32 temp; u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR; @@ -414,6 +425,7 @@ int ipu_probe(void) temp = __raw_readl(reg_hsc_mxt_conf); __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); +#endif ipu_base = IPU_CTRL_BASE_ADDR; ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE); @@ -424,7 +436,8 @@ int ipu_probe(void) g_ipu_clk = &ipu_clk; debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk)); - + g_ldb_clk = &ldb_clk; + debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk)); ipu_reset(); clk_set_parent(g_pixel_clk[0], g_ipu_clk); diff --git a/drivers/video/ipu_disp.c b/drivers/video/ipu_disp.c index fa8fb2c357..b4116df8ca 100644 --- a/drivers/video/ipu_disp.c +++ b/drivers/video/ipu_disp.c @@ -64,6 +64,7 @@ static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23; int g_di1_tvout; extern struct clk *g_ipu_clk; +extern struct clk *g_ldb_clk; extern struct clk *g_di_clk[2]; extern struct clk *g_pixel_clk[2]; @@ -941,7 +942,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, udelay(10000); } } - clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]); + clk_set_parent(g_pixel_clk[disp], g_ldb_clk); } else { if (clk_get_usecount(g_pixel_clk[disp]) != 0) clk_set_parent(g_pixel_clk[disp], g_ipu_clk); diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h index 93b195f2ce..a43aa03735 100644 --- a/drivers/video/ipu_regs.h +++ b/drivers/video/ipu_regs.h @@ -47,14 +47,24 @@ #define IPU_SMFC_REG_BASE 0x00050000 #define IPU_DC_REG_BASE 0x00058000 #define IPU_DMFC_REG_BASE 0x00060000 +#define IPU_VDI_REG_BASE 0x00680000 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #define IPU_CPMEM_REG_BASE 0x01000000 #define IPU_LUT_REG_BASE 0x01020000 #define IPU_SRM_REG_BASE 0x01040000 #define IPU_TPM_REG_BASE 0x01060000 #define IPU_DC_TMPL_REG_BASE 0x01080000 #define IPU_ISP_TBPR_REG_BASE 0x010C0000 -#define IPU_VDI_REG_BASE 0x00680000 +#elif defined(CONFIG_MX6Q) +#define IPU_CPMEM_REG_BASE 0x00100000 +#define IPU_LUT_REG_BASE 0x00120000 +#define IPU_SRM_REG_BASE 0x00140000 +#define IPU_TPM_REG_BASE 0x00160000 +#define IPU_DC_TMPL_REG_BASE 0x00180000 +#define IPU_ISP_TBPR_REG_BASE 0x001C0000 +#endif +#define IPU_CTRL_BASE_ADDR (IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET) extern u32 *ipu_dc_tmpl_reg; diff --git a/dts/Makefile b/dts/Makefile index b1f47a1910..055b8ac599 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -52,7 +52,7 @@ $(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts { { $(DTC) -R 4 -p 0x1000 -O dtb -o ${DT_BIN} - 2>&1 ; \ echo $$? >&3 ; } | \ grep -v '^DTC: dts->dtb on file' ; \ - } 3>&1 ) ; \ + } 3>&1 1>&2 ) ; \ exit $$rc process_lds = \ diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c index f1fce48a39..182f0acaca 100644 --- a/fs/ext2/ext2fs.c +++ b/fs/ext2/ext2fs.c @@ -438,7 +438,7 @@ int ext2fs_read_file } /* grab middle blocks in one go */ - if (i != pos / blocksize && i != blockcnt - 1 && blockcnt > 3) { + if (i != pos / blocksize && i < blockcnt - 1 && blockcnt > 3) { int oldblk = blknr; int blocknxt; while (i < blockcnt - 1) { diff --git a/include/addr_map.h b/include/addr_map.h index d55f5f64e1..dda4d6e710 100644 --- a/include/addr_map.h +++ b/include/addr_map.h @@ -22,7 +22,7 @@ #include <asm/types.h> extern phys_addr_t addrmap_virt_to_phys(void *vaddr); -extern unsigned long addrmap_phys_to_virt(phys_addr_t paddr); +extern void *addrmap_phys_to_virt(phys_addr_t paddr); extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, phys_size_t size, int idx); diff --git a/include/common.h b/include/common.h index 7cf15c53b7..39859d323f 100644 --- a/include/common.h +++ b/include/common.h @@ -760,6 +760,16 @@ char * strmhz(char *buf, unsigned long hz); /* lib/crc32.c */ #include <u-boot/crc.h> +/* lib/rand.c */ +#if defined(CONFIG_RANDOM_MACADDR) || \ + defined(CONFIG_BOOTP_RANDOM_DELAY) || \ + defined(CONFIG_CMD_LINK_LOCAL) +#define RAND_MAX -1U +void srand(unsigned int seed); +unsigned int rand(void); +unsigned int rand_r(unsigned int *seedp); +#endif + /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ int console_init_r(void); /* After relocation; uses the console stuff */ @@ -934,11 +944,25 @@ int cpu_release(int nr, int argc, char * const argv[]); * of a function scoped static buffer. It can not be used to create a cache * line aligned global buffer. */ +#define ALLOC_ALIGN_BUFFER(type, name, size, align) \ + char __##name[ROUND(size * sizeof(type), align) + (align - 1)]; \ + \ + type *name = (type *) ALIGN((uintptr_t)__##name, align) #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \ - char __##name[ROUND(size * sizeof(type), ARCH_DMA_MINALIGN) + \ - ARCH_DMA_MINALIGN - 1]; \ + ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) + +/* + * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's + * purpose is to allow allocating aligned buffers outside of function scope. + * Usage of this macro shall be avoided or used with extreme care! + */ +#define DEFINE_ALIGN_BUFFER(type, name, size, align) \ + static char __##name[roundup(size * sizeof(type), align)] \ + __attribute__((aligned(align))); \ \ - type *name = (type *) ALIGN((uintptr_t)__##name, ARCH_DMA_MINALIGN) + static type *name = (type *)__##name +#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size) \ + DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN) /* Pull in stuff for the build system */ #ifdef DO_DEPS_ONLY diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h new file mode 100644 index 0000000000..fd076e09a2 --- /dev/null +++ b/include/configs/BSC9131RDB.h @@ -0,0 +1,428 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * BSC9131 RDB board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_BSC9131RDB +#define CONFIG_BSC9131 +#define CONFIG_NAND_FSL_IFC +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_TSEC_ENET +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* enable branch predition */ + +#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01ffffff + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#undef CONFIG_SYS_DDR_RAW_TIMING +#undef CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#ifndef __ASSEMBLY__ +extern unsigned long get_sdram_size(void); +#endif +#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ + /* CONFIG_SYS_IMMR */ + +/* + * Memory map + * + * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable + * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M + * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K + * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K + * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M + * + */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NO_FLASH + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ + | FTIM0_NAND_TWP(0x06) \ + | FTIM0_NAND_TWCHT(0x03) \ + | FTIM0_NAND_TWH(0x04)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ + | FTIM1_NAND_TWBE(0x23) \ + | FTIM1_NAND_TRR(0x08) \ + | FTIM1_NAND_TRP(0x05)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ + | FTIM2_NAND_TREH(0x04) \ + | FTIM2_NAND_TWHRE(0x3f)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NAND */ +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +/* I2C EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_CMD_I2C + + +#define CONFIG_FSL_ESPI +/* eSPI - Enhanced SPI */ +#ifdef CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 + +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x400 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_HOSTNAME BSC9131rdb +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "loadaddr=1000000\0" \ + "bootfile=uImage\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=bsc9131rdb.dtb\0" \ + "bdev=sda1\0" \ + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ + "othbootargs=ramdisk_size=600000 \0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index ddee1ae092..8c027f9756 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -156,7 +156,7 @@ /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index ac08ce3604..e5529c7007 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -240,7 +240,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Local Bus LCRR and LBCR regs diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 03873b8a34..7ecb089a35 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -349,7 +349,7 @@ boards, we say we have two, but don't display a message if we find only one. */ /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Local Bus LCRR and LBCR regs diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 9c7aae3d90..a1fbd5e4a4 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -205,7 +205,7 @@ /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 5aad4fd614..fc0095281a 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -170,7 +170,7 @@ #endif #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 134352baef..33ded71160 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009,2010-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -711,6 +711,8 @@ /* * USB */ +#define CONFIG_HAS_FSL_MPH_USB +#ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -719,6 +721,7 @@ #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE #endif +#endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) #define CONFIG_CMD_EXT2 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 920edad0e9..50d3f8d703 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> * Timur Tabi <timur@freescale.com> * @@ -433,6 +433,8 @@ /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -442,6 +444,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_CMD_FAT #endif +#endif /* * Miscellaneous configurable options @@ -487,35 +490,30 @@ #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#define CONFIG_BOOTARGS #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "perf_mode=stable\0" \ - "memctl_intlv_ctl=2\0" \ - "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=uramdisk\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=p1022ds.dtb\0" \ - "bdev=sda3\0" \ - "diuregs=md e002c000 1d\0" \ - "dium=mw e002c01c\0" \ - "diuerr=md e002c014 1\0" \ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p1022ds.dtb\0" \ + "bdev=sda3\0" \ "hwconfig=esdhc;audclk:12\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ + "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" @@ -524,14 +522,14 @@ "setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ + "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ + "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index cdb56bb8f4..800d666ab2 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -1,5 +1,5 @@ /* - * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2010-2012 Freescale Semiconductor, Inc. * * Authors: Roy Zang <tie-fei.zang@freescale.com> * Chunhe Lan <b25806@freescale.com> @@ -441,6 +441,8 @@ extern unsigned long get_clock_freq(void); /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -453,6 +455,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif +#endif /* * Miscellaneous configurable options diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index 121e357753..d323fb5e09 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2010,2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -396,6 +396,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #endif /* CONFIG_MMC */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -403,7 +405,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE -#define CONFIG_HAS_FSL_DR_USB +#endif #endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index d7d64d2936..5fc956305d 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -128,7 +128,6 @@ #else #define CONFIG_FSL_DDR3 1 #endif -#undef CONFIG_FSL_DDR_INTERACTIVE /* ECC will be enabled based on perf_mode environment variable */ /* #define CONFIG_DDR_ECC */ @@ -207,8 +206,6 @@ * */ -#undef CONFIG_CLOCKS_IN_MHZ - /* * Memory map * @@ -251,7 +248,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ @@ -373,7 +369,7 @@ #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) @@ -391,7 +387,6 @@ /* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 @@ -526,17 +521,6 @@ #define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP -#define CONFIG_RTL8139 - -#ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS - #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #define CONFIG_SCSI_AHCI @@ -563,7 +547,6 @@ #define CONFIG_TSEC3 1 #define CONFIG_TSEC3_NAME "eTSEC3" -#define CONFIG_PIXIS_SGMII_CMD #define CONFIG_FSL_SGMII_RISER 1 #define SGMII_RISER_PHY_OFFSET 0x1b @@ -643,6 +626,8 @@ /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI @@ -651,8 +636,7 @@ #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#endif /* * SDHC/MMC @@ -729,7 +713,6 @@ #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 23a32bcf6c..1251b5c569 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -570,11 +570,17 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif + #define CONFIG_CMD_EXT2 #define CONFIG_MMC diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 07b1968070..ef25fa5e0c 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -187,7 +187,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -201,7 +201,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -230,6 +230,7 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE /* * Size of malloc() pool diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 6fd0b832fe..014437b5e0 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -189,7 +189,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -203,7 +203,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xD0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) " \ @@ -232,6 +232,7 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE /* * Size of malloc() pool diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 61a622a843..4309f71f16 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -33,7 +33,11 @@ */ #include <asm/hardware.h> +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH #define CONFIG_SYS_TEXT_BASE 0x21F00000 +#else +#define CONFIG_SYS_TEXT_BASE 0x0000000 +#endif /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ @@ -147,11 +151,11 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) /* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE 0x10000 #define xstr(s) str(s) #define str(s) #s @@ -314,7 +318,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) "\ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index f8b3095b49..1d5fc8f73e 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -59,17 +59,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP ATMEL_ID_UHPHS - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP - /* LCD */ #define CONFIG_LCD #define LCD_BPP LCD_COLOR8 @@ -147,13 +136,10 @@ #define CONFIG_RESET_PHY_R /* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 #define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 45f8baff05..c5952e9319 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -155,7 +155,7 @@ #define CONFIG_ENV_OFFSET 0x4200 #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) #define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ "mtdparts=atmel_nand:-(root) "\ @@ -182,6 +182,7 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_AUTO_COMPLETE /* * Size of malloc() pool diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index d80eac22db..7b51b53dc5 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -156,6 +156,15 @@ #ifdef CONFIG_BF527_EZKIT_REV_2_1 # define CONFIG_LQ035Q1_SPI_BUS 0 # define CONFIG_LQ035Q1_SPI_CS 7 +# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI +#else +# define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI +#endif + +#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI +# define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h> +#else +# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h> #endif diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h index 89adfefee3..e6b05db09d 100644 --- a/include/configs/bf548-ezkit.h +++ b/include/configs/bf548-ezkit.h @@ -188,6 +188,7 @@ /* Don't waste time transferring a logo over the UART */ # if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) # define CONFIG_VIDEO +# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h> # endif # define CONFIG_DEB_DMA_URGENT #endif diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h index a6d2fa8ae4..3c9eeb58a3 100644 --- a/include/configs/cm-bf548.h +++ b/include/configs/cm-bf548.h @@ -122,6 +122,7 @@ /* Don't waste time transferring a logo over the UART */ # if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) # define CONFIG_VIDEO +# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h> # endif # define CONFIG_DEB_DMA_URGENT #endif diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 782d28c55d..ee4bce5d34 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -77,7 +77,7 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ /* Sector */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) @@ -174,7 +174,7 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_ECC_LP_x8_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ @@ -315,7 +315,6 @@ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index a3705cb512..52a5ba9828 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -656,13 +656,17 @@ /* * USB */ +#define CONFIG_HAS_FSL_DR_USB +#define CONFIG_HAS_FSL_MPH_USB + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_CMD_EXT2 -#define CONFIG_HAS_FSL_DR_USB +#endif #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index c1a0f6a770..3fc07e672a 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -102,6 +102,14 @@ #define CONFIG_SYS_DTT_HYSTERESIS 3 /* + * SPI Configuration + */ +#define CONFIG_DAVINCI_SPI +#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CONFIG_CMD_SPI + +/* * Flash & Environment */ #ifdef CONFIG_USE_NAND @@ -225,9 +233,9 @@ "key_magic_2=2\0" \ "key_magic_3=3\0" \ "magic_keys=0123\0" \ - "hwconfig=switch:lan=on,pwl=off\0" \ + "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs} davinci_mmc.use_dma=0\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "logversion=2\0" \ @@ -336,6 +344,11 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_MMC +/* GPIO */ +#define CONFIG_ENBW_CMC_BOARD_TYPE 57 +#define CONFIG_ENBW_CMC_HW_ID_BIT0 39 +#define CONFIG_ENBW_CMC_HW_ID_BIT1 38 +#define CONFIG_ENBW_CMC_HW_ID_BIT2 35 /* FDT support */ #define CONFIG_OF_LIBFDT @@ -438,7 +451,8 @@ #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) #define CONFIG_POST (CONFIG_SYS_POST_MEMORY) -#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0 +#define CONFIG_POST_EXTERNAL_WORD_FUNCS +#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE #define CONFIG_LOGBUFFER #define CONFIG_SYS_CONSOLE_IS_IN_ENV diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 6c5fcac6c1..e8e3c6a03d 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -66,7 +66,7 @@ */ #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX35_PORT3 +#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_SPI diff --git a/include/configs/harmony.h b/include/configs/harmony.h index ce0ae9fe1f..df5265a5a0 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2012 * NVIDIA Corporation <www.nvidia.com> * * See file CREDITS for list of people who contributed to this @@ -27,8 +27,12 @@ #include <asm/sizes.h> #include "tegra2-common.h" +/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-harmony +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (Harmony) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony" @@ -44,14 +48,13 @@ #endif #define CONFIG_MACH_TYPE MACH_TYPE_HARMONY -#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION @@ -61,4 +64,22 @@ /* Environment not stored */ #define CONFIG_ENV_IS_NOWHERE + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h index c6e8859f63..c6e9ce5576 100644 --- a/include/configs/hawkboard.h +++ b/include/configs/hawkboard.h @@ -123,6 +123,7 @@ #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_NAND_DAVINCI #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST /* SPL nand driver configuration */ #define CFG_DAVINCI_STD_NAND_LAYOUT #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1728358211..a412cf61ee 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -54,9 +54,9 @@ #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX31_PORT2 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR +#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 011f838106..3aa5ca152c 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -57,6 +57,13 @@ #define CONFIG_CMD_SF #define CONFIG_SOFT_I2C /* I2C bit-banged */ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 5000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_3 +#endif + #include "asm/arch/config.h" #define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */ @@ -81,7 +88,7 @@ "boot=bootm ${load_addr_r} - -\0" \ "cramfsloadfdt=true\0" \ "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \ - CONFIG_KM_DEF_ENV_UPDATE \ + CONFIG_KM_UPDATE_UBOOT \ "" #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ @@ -159,12 +166,12 @@ */ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_CMD_MII /* to debug mdio phy config */ #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */ /* * UBI related stuff @@ -185,6 +192,7 @@ int get_sda(void); int get_scl(void); #define KM_KIRKWOOD_SDA_PIN 8 #define KM_KIRKWOOD_SCL_PIN 9 +#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 #define KM_KIRKWOOD_ENV_WP 38 #define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) @@ -211,6 +219,15 @@ int get_scl(void); /* * Environment variables configurations */ +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_ENV_IS_IN_SPI_FLASH /* use SPI-Flash for environment vars */ +#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */ +#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ +#else #define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */ #define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 #define CONFIG_ENV_EEPROM_IS_ON_I2C @@ -218,16 +235,20 @@ int get_scl(void); #define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ #define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) #define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0" - -/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO +/* SPI bus claim MPP configuration */ +#define CONFIG_SYS_KW_SPI_MPP 0x0 + #define FLASH_GPIO_PIN 0x00010000 +#define KM_FLASH_GPIO_PIN 16 #ifndef MTDIDS_DEFAULT # define MTDIDS_DEFAULT "nand0=orion_nand" @@ -239,23 +260,32 @@ int get_scl(void); "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" #endif /* MTDPARTS_DEFAULT */ -#define CONFIG_KM_DEF_ENV_UPDATE \ +#define CONFIG_KM_UPDATE_UBOOT \ "update=" \ - "spi on;sf probe 0;sf erase 0 50000;" \ - "sf write ${load_addr_r} 0 ${filesize};" \ - "spi off\0" + "sf probe 0;sf erase 0 +${filesize};" \ + "sf write ${load_addr_r} 0 ${filesize};\0" + +#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_NEW_ENV \ + "newenv=sf probe 0;" \ + "sf erase " xstr(CONFIG_ENV_OFFSET) " " \ + xstr(CONFIG_ENV_TOTAL_SIZE)"\0" +#else +#define CONFIG_KM_NEW_ENV \ + "newenv=setenv addr 0x100000 && " \ + "i2c dev 1; mw.b ${addr} 0 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ + "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ + " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" +#endif /* * Default environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_KM_DEF_ENV \ - "newenv=setenv addr 0x100000 && " \ - "i2c dev 1; mw.b ${addr} 0 4 && " \ - "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ - " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \ - "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \ - " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \ + CONFIG_KM_NEW_ENV \ "arch=arm\0" \ "EEprom_ivm=" KM_IVM_BUS "\0" \ "" @@ -284,4 +314,7 @@ int get_scl(void); #define CONFIG_POST_EXTERNAL_WORD_FUNCS #define CONFIG_CMD_DIAG +/* we do the whole PCIe FPGA config stuff here */ +#define BOARD_LATE_INIT + #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index ed36124156..fba181fffa 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -6,8 +6,9 @@ * (C) Copyright 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de + * (C) Copyright 2011-2012 + * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com + * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com * * See file CREDITS for list of people who contributed to this * project. @@ -36,25 +37,139 @@ #ifndef _CONFIG_KM_KIRKWOOD_H #define _CONFIG_KM_KIRKWOOD_H +/* KM_KIRKWOOD */ +#if defined(CONFIG_KM_KIRKWOOD) +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" +#define CONFIG_HOSTNAME km_kirkwood +#define CONFIG_KM_DISABLE_PCIE +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ + +/* KM_KIRKWOOD_PCI */ +#elif defined(CONFIG_KM_KIRKWOOD_PCI) +#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define CONFIG_HOSTNAME km_kirkwood_pci +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_FPGA_CONFIG + +/* KM_NUSA */ +#elif defined(CONFIG_KM_NUSA) +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_IDENT_STRING "\nKeymile NUSA" +#define CONFIG_HOSTNAME kmnusa +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_FPGA_CONFIG +#define CONFIG_KM_PIGGY4_88E6352 + +/* KM_MGCOGE3UN */ +#elif defined(CONFIG_KM_MGCOGE3UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE3UN" +#define CONFIG_HOSTNAME mgcoge3un +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg +#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_KM_DISABLE_PCIE +#define CONFIG_KM_PIGGY4_88E6061 + +/* KMCOGE5UN */ +#elif defined(CONFIG_KM_COGE5UN) +#define CONFIG_IDENT_STRING "\nKeymile COGE5UN" +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#undef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 +#define CONFIG_HOSTNAME kmcoge5un +#define CONFIG_KM_DISABLE_PCIE +#define CONFIG_KM_PIGGY4_88E6352 + +/* KM_PORTL2 */ +#elif defined(CONFIG_KM_PORTL2) +#define CONFIG_IDENT_STRING "\nKeymile Port-L2" +#define CONFIG_HOSTNAME portl2 +#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_KM_PIGGY4_88E6061 + +#else +#error ("Board unsupported") +#endif + /* include common defines/options for all arm based Keymile boards */ #include "km/km_arm.h" +#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR +#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ +#endif + +#if defined(CONFIG_KM_PIGGY4_88E6352) /* - * Version number information + * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via + * an Marvell 88E6352 simple switch. + * In this case we have to change the default settings for the etherent mac. + * There is NO ethernet phy. The ARM and Switch are conencted directly over + * RGMII in MAC-MAC mode + * In this case 1GBit full duplex and autoneg off */ -#ifdef CONFIG_KM_DISABLE_PCI -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood" -#undef CONFIG_KIRKWOOD_PCIE_INIT -#else -#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_1000 |\ + MVGBE_SET_MII_SPEED_TO_100) + #endif -#define CONFIG_HOSTNAME km_kirkwood +#ifdef CONFIG_KM_PIGGY4_88E6061 +/* + * Some keymile boards like mgcoge3un have their PIGGY4 connected via + * an Marvell 88E6061 simple switch. + * In this case we have to change the default settings for the + * ethernet phy connected to the kirkwood. + * In this case 100MB full duplex and autoneg off + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) +#endif -#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ -#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ +#ifdef CONFIG_KM_DISABLE_PCI +#undef CONFIG_KIRKWOOD_PCIE_INIT +#endif -/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ -#define KM_XLX_PROGRAM_B_PIN 39 #endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index cd8d59f9af..c35c2db30c 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -66,15 +66,11 @@ /* * SDRAM configuration */ -#if defined(CONFIG_NET2BIG_V2) -#define CONFIG_NR_DRAM_BANKS 2 -#else #define CONFIG_NR_DRAM_BANKS 1 -#endif #ifdef CONFIG_INETSPACE_V2 /* Different SDRAM configuration and size for Internet Space v2 */ -#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg) +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg #endif /* diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h new file mode 100644 index 0000000000..0db559cf6c --- /dev/null +++ b/include/configs/lsxl.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2012 Michael Walle + * Michael Walle <michael@walle.cc> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_LSXL_H +#define _CONFIG_LSXL_H + +/* + * Version number information + */ +#if defined(CONFIG_LSCHLV2) +#define CONFIG_IDENT_STRING " LS-CHLv2" +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lschl.cfg +#define CONFIG_MACH_TYPE 3006 +#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ +#elif defined(CONFIG_LSXHL) +#define CONFIG_IDENT_STRING " LS-XHL" +#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg +#define CONFIG_MACH_TYPE 2663 +/* CONFIG_SYS_TCLK is 200000000 by default */ +#else +#error "unknown board" +#endif + +/* + * General configuration options + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SOC Family Name */ +#define CONFIG_KW88F6281 /* SOC Name */ + +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_MISC_INIT_R +#define CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_RANDOM_MACADDR +#define CONFIG_KIRKWOOD_GPIO +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +/* + * Enable u-boot API for standalone programs. + */ +#define CONFIG_API + +/* + * Commands configuration + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_PING +#define CONFIG_CMD_PING +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_USB + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* ST M25P40 */ +#undef CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_STMICRO +#undef CONFIG_ENV_SPI_MAX_HZ +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#undef CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SF_DEFAULT_SPEED 25000000 + + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Environment variables configurations + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 8 +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x10000 /* 64k */ +#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_LOADADDR 0x00800000 +#define CONFIG_BOOTCOMMAND "run bootcmd_${bootsource}" +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/sda2" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootsource=hdd\0" \ + "hdpart=0:1\0" \ + "bootcmd_net=bootp 0x00100000 uImage " \ + "&& tftpboot 0x00800000 uInitrd " \ + "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_hdd=ide reset " \ + "&& ext2load ide ${hdpart} 0x00100000 /uImage " \ + "&& ext2load ide ${hdpart} 0x00800000 /uInitrd " \ + "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_usb=usb start " \ + "&& fatload usb 0:1 0x00100000 /uImage " \ + "&& fatload usb 0:1 0x00800000 /uInitrd " \ + "&& bootm 0x00100000 0x00800000\0" \ + "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ + "eraseenv=sf probe 0 " \ + "&& sf erase " MK_STR(CONFIG_ENV_OFFSET) \ + " +" MK_STR(CONFIG_ENV_SIZE) "\0" \ + "config_nc_dhcp=setenv autoload_old ${autoload}; " \ + "setenv autoload no " \ + "&& bootp " \ + "&& setenv ncip ${serverip} " \ + "&& setenv autoload ${autoload_old}; " \ + "setenv autoload_old\0" \ + "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ + "setenv ncip; setenv gatewayip; setenv ethact; " \ + "setenv bootfile; setenv dnsip; " \ + "setenv bootsource hdd; run ser\0" \ + "restore_env=run standard_env; saveenv; reset\0" \ + "ser=setenv stdin serial; setenv stdout serial; " \ + "setenv stderr serial\0" \ + "nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */ +#define CONFIG_PHY_BASE_ADR 7 +#undef CONFIG_RESET_PHY_R +#endif /* CONFIG_CMD_NET */ + +#ifdef CONFIG_CMD_IDE +#undef CONFIG_IDE_LED +#undef CONFIG_SYS_IDE_MAXBUS +#define CONFIG_SYS_IDE_MAXBUS 1 +#undef CONFIG_SYS_IDE_MAXDEVICE +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif + +#endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 3abaadc877..f12d927e03 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -17,8 +17,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef __M28_H__ -#define __M28_H__ +#ifndef __M28EVK_CONFIG_H__ +#define __M28EVK_CONFIG_H__ #include <asm/arch/regs-base.h> @@ -40,11 +40,8 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT -#define CONFIG_OF_LIBFDT - /* * SPL */ @@ -88,7 +85,7 @@ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ @@ -325,4 +322,4 @@ "fi ; " \ "fi\0" -#endif /* __M28_H__ */ +#endif /* __M28EVK_CONFIG_H__ */ diff --git a/include/configs/medcom.h b/include/configs/medcom.h index 2dc350762d..c84db03e76 100644 --- a/include/configs/medcom.h +++ b/include/configs/medcom.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2010,2011 * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011 + * (C) Copyright 2011-2012 * Avionic Design GmbH <www.avionic-design.de> * * See file CREDITS for list of people who contributed to this @@ -28,11 +28,14 @@ #include "tegra2-common.h" +/* Enable fdt support for Medcom. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-medcom +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M" #define V_PROMPT "Tegra2 (Medcom) # " #define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom" -#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI @@ -46,9 +49,23 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC +/* USB host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION #define CONFIG_CMD_EXT2 @@ -61,4 +78,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h deleted file mode 100644 index 797b0dfcd3..0000000000 --- a/include/configs/mgcoge3un.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar <prafulla@marvell.com> - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_MGCOGE3UN_H -#define _CONFIG_MGCOGE3UN_H - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN" -#define CONFIG_HOSTNAME mgcoge3un -#define CONFIG_MGCOGE3UN - -#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ -#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/ - -/* we use a new RAM type on mgcoge3un board */ -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg - -/* - * mgcoge3un has a fixed link to the marvell switch - * with 100MB full duplex and autoneg off, for this - * reason we have to change the default settings - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) - -#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" - -/* - * PCIe port not used on mgcoge3un - */ -#undef CONFIG_KIRKWOOD_PCIE_INIT - -#endif /* _CONFIG_MGCOGE3UN_H */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 51b172ddb4..54d21e687a 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -16,8 +16,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __MX28EVK_CONFIG_H__ +#define __MX28EVK_CONFIG_H__ #include <asm/arch/regs-base.h> @@ -34,7 +34,6 @@ #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MISC_INIT /* @@ -54,11 +53,11 @@ #include <config_cmd_default.h> #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION -#define CONFIG_CMD_FAT #define CONFIG_CMD_CACHE #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT #define CONFIG_CMD_GPIO #define CONFIG_CMD_MII #define CONFIG_CMD_MMC @@ -69,6 +68,7 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_USB #define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_I2C /* * Memory configurations @@ -189,6 +189,13 @@ #define CONFIG_USB_STORAGE #endif +/* I2C */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MXS +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#endif + /* * SPI */ @@ -250,4 +257,4 @@ "run netargs; " \ "dhcp ${uimage}; bootm\0" \ -#endif /* __CONFIG_H */ +#endif /* __MX28EVK_CONFIG_H__ */ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index 016864a658..f930ed0a67 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -57,9 +57,8 @@ */ #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX35_PORT1 +#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_SPI #define CONFIG_MXC_GPIO diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index bd04c02789..6af5ed7fe4 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -126,13 +126,14 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT #define CONFIG_VIDEO -#define CONFIG_VIDEO_MX5 +#define CONFIG_VIDEO_IPUV3 #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 133000000 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index f4512ffff2..0a928afc82 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -50,9 +50,8 @@ #define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX53_PORT2 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* MMC Configs */ #define CONFIG_FSL_ESDHC @@ -68,7 +67,6 @@ /* Eth Configs */ #define CONFIG_HAS_ETH1 #define CONFIG_MII -#define CONFIG_MII_GASKET #define CONFIG_DISCOVER_PHY #define CONFIG_CMD_PING diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index a5f32e317d..67def93f63 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -53,9 +53,8 @@ #define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX53_PORT2 1 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* PMIC Configs */ #define CONFIG_PMIC diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 8b4e00855d..0a25c7d079 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -41,7 +41,6 @@ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO #define CONFIG_REVISION_TAG @@ -90,9 +89,8 @@ /* I2C Configs */ #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX53_PORT1 +#define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* PMIC Controller */ #define CONFIG_PMIC @@ -221,12 +219,13 @@ /* Framebuffer and LCD */ #define CONFIG_PREBOOT #define CONFIG_VIDEO -#define CONFIG_VIDEO_MX5 +#define CONFIG_VIDEO_IPUV3 #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 133000000 #endif /* __CONFIG_H */ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 0d7086dde8..760014fce5 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -50,9 +50,8 @@ #define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_I2C_MXC -#define CONFIG_SYS_I2C_MX53_PORT2 +#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe /* MMC Configs */ #define CONFIG_FSL_ESDHC diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index a155c77234..a9c1b1545e 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -37,7 +37,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 5b566a8f2b..e42fe6b00b 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -40,7 +40,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO @@ -59,6 +58,14 @@ #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #endif +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_BASE I2C3_BASE_ADDR +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + /* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC @@ -97,6 +104,7 @@ #define CONFIG_FEC_MXC_PHYADDR 6 #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 /* USB Configs */ #define CONFIG_CMD_USB diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index a383fa465c..69ff3efb50 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -117,10 +117,9 @@ /* * MEMORY ORGANIZATION - * -Monitor at top of sdram. - * -The heap is placed below the monitor - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -Monitor at top of sdram. + * -The heap is placed below the monitor + * -The stack is placed below the heap (&grows down). */ #define CONFIG_MONITOR_IS_IN_RAM #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ @@ -130,10 +129,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000) #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \ CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - \ - GENERATED_GBL_DATA_SIZE - \ - GENERATED_BD_INFO_SIZE) -#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP CONFIG_SYS_MALLOC_BASE /* * MISC diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 268215cb86..657780edcf 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -146,6 +146,8 @@ /* commands to include */ #include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV + #define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ @@ -213,7 +215,7 @@ /* partition */ /* Environment information */ -#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 1fcb7af9fe..632a13fa9f 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -42,6 +42,8 @@ */ #include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV + #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_JFFS2 @@ -134,7 +136,7 @@ * Default environment * ----------------------------------------------------------------------------- */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 3 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 84481420e4..2192c2b899 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -120,9 +120,6 @@ /* Flash */ #define CONFIG_SYS_NO_FLASH 1 -/* clocks */ -#define CONFIG_SYS_CLOCKS_ENABLE_ALL - /* commands to include */ #include <config_cmd_default.h> @@ -281,9 +278,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" - -#define CONFIG_SYS_ENABLE_PADS_ALL +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SYS_THUMB_BUILD diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_evm.h index 60c7a291c0..c5874bbf67 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_evm.h @@ -50,8 +50,6 @@ /* Clock Defines */ #define V_OSCK 19200000 /* Clock output from T2 */ #define V_SCLK V_OSCK -#define CONFIG_SYS_CLOCKS_ENABLE_ALL 1 /* Enable all clocks */ -#define CONFIG_SYS_ENABLE_PADS_ALL 1 /* Enable all PADS for now */ #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R @@ -261,7 +259,7 @@ #define CONFIG_SPL_FAT_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds" +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* * 64 bytes before this address should be set aside for u-boot.img's diff --git a/include/configs/paz00.h b/include/configs/paz00.h index f53f20eb97..0dd1e83a50 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010,2011, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. * * See file CREDITS for list of people who contributed to this * project. @@ -20,8 +20,12 @@ #include <asm/sizes.h> #include "tegra2-common.h" +/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-paz00 +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=512M@0M" #define V_PROMPT "Tegra2 (Paz00) MOD # " #define CONFIG_TEGRA2_BOARD_STRING "Compal Paz00" @@ -31,14 +35,13 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 -#define CONFIG_SYS_BOARD_ODMDATA 0x800c0085 /* lp1, 512MB */ #define CONFIG_BOARD_EARLY_INIT_F /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION @@ -46,6 +49,25 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index f869191f34..9870590bd6 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -1,7 +1,7 @@ /* * (C) Copyright 2010,2011 * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011 + * (C) Copyright 2011-2012 * Avionic Design GmbH <www.avionic-design.de> * * See file CREDITS for list of people who contributed to this @@ -28,11 +28,14 @@ #include "tegra2-common.h" +/* Enable fdt support for Plutux. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-plutux +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M" #define V_PROMPT "Tegra2 (Plutux) # " #define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux" -#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011 /* Board-specific serial config */ #define CONFIG_SERIAL_MULTI @@ -46,9 +49,23 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC +/* USB host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + #define CONFIG_DOS_PARTITION #define CONFIG_EFI_PARTITION #define CONFIG_CMD_EXT2 @@ -61,4 +78,6 @@ "ext2load mmc 0 0x17000000 /boot/uImage;" \ "bootm" +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/portl2.h b/include/configs/portl2.h deleted file mode 100644 index e436cfea41..0000000000 --- a/include/configs/portl2.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar <prafulla@marvell.com> - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com. - * Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -/* for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */ - -#ifndef _CONFIG_PORTL2_H -#define _CONFIG_PORTL2_H - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nKeymile Port-L2" -#define CONFIG_HOSTNAME portl2 -#define CONFIG_PORTL2 - -#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ -/* - * Note: This is only valid for HW > P1A if you got an outdated P1A - * use KM_ENV_BUS "pca9544a:70:a" - */ -#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ - -/* - * portl2 has a fixed link to the XMPP backplane - * with 100MB full duplex and autoneg off, for this - * reason we have to change the default settings - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) - -/* - * portl2 does use the PCIe Port0 - */ -#define CONFIG_KIRKWOOD_PCIE_INIT - -#endif /* _CONFIG_PORTL2_H */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 7d0dda72a9..478d0d8f9d 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -194,7 +194,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Local Bus LCRR and LBCR regs diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 46d42281b7..f661583fed 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -41,7 +41,6 @@ #define CONFIG_OF_SEPARATE /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (SeaBoard) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard" @@ -54,19 +53,9 @@ #define CONFIG_UART_DISABLE_GPIO GPIO_PI3 #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD -#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F -/* SPI */ -#define CONFIG_TEGRA2_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - /* I2C */ #define CONFIG_TEGRA_I2C #define CONFIG_SYS_I2C_INIT_BOARD @@ -78,7 +67,7 @@ /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION @@ -86,13 +75,10 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment in SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_MAX_HZ 48000000 -#define CONFIG_ENV_SPI_MODE SPI_MODE_0 - -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE) +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USB Host support */ #define CONFIG_USB_EHCI @@ -100,6 +86,14 @@ #define CONFIG_USB_STORAGE #define CONFIG_CMD_USB +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + /* Enable keyboard */ #define CONFIG_TEGRA2_KEYBOARD #define CONFIG_KEYBOARD @@ -108,4 +102,7 @@ #define TEGRA2_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \ "stdout=serial\0" \ "stderr=serial\0" + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 2360a8f780..d47881bcb2 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -102,6 +102,12 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS +#define CONFIG_USB_STORAGE + /* MMC SPL */ #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index ab1b33209e..a6d1cfbcb0 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -27,18 +27,33 @@ * Common configurations used for both spear3xx as well as spear6xx */ +/* U-boot Load Address */ +#define CONFIG_SYS_TEXT_BASE 0x00700000 + +/* Ethernet driver configuration */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_DW0_PHY 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ +#define CONFIG_DW_AUTONEG +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + /* USBD driver configuration */ +#if defined(CONFIG_SPEAR_USBTTY) #define CONFIG_DW_UDC #define CONFIG_USB_DEVICE +#define CONFIG_USBD_HS #define CONFIG_USB_TTY #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" #define CONFIG_USBD_MANUFACTURER "ST Microelectronics" -#if defined(CONFIG_USB_TTY) -#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" #endif +#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" + /* I2C driver configuration */ #define CONFIG_HARD_I2C #define CONFIG_DW_I2C @@ -48,27 +63,25 @@ #define CONFIG_I2C_CHIPADDRESS 0x50 /* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ (1000) -#define CONFIG_SYS_HZ_CLOCK (8300000) +#define CONFIG_SYS_HZ 1000 /* Flash configuration */ #if defined(CONFIG_FLASH_PNOR) -#define CONFIG_SPEAR_EMI 1 +#define CONFIG_SPEAR_EMI #else -#define CONFIG_SPEARSMI 1 +#define CONFIG_ST_SMI #endif -#if defined(CONFIG_SPEARSMI) +#if defined(CONFIG_ST_SMI) #define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BASE (0xF8000000) -#define CONFIG_SYS_CS1_FLASH_BASE (0xF9000000) -#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_BASE 0xF8000000 +#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000 +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_CS1_FLASH_BASE} #define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_EMPTY_INFO 1 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) @@ -88,11 +101,13 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* NAND FLASH Configuration */ +#define CONFIG_SYS_NAND_SELF_INIT #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_NAND_SPEAR 1 +#define CONFIG_NAND_FSMC #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_QUIET_TEST /* * Command support defines @@ -103,11 +118,13 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_RUN #define CONFIG_CMD_SAVES +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <config_cmd_default.h> -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS /* * Default Environment Varible definitions @@ -124,13 +141,13 @@ * U-Boot Environment placing definitions. */ #if defined(CONFIG_ENV_IS_IN_FLASH) -#ifdef CONFIG_SPEARSMI +#ifdef CONFIG_ST_SMI /* * Environment is in serial NOR flash */ #define CONFIG_SYS_MONITOR_LEN 0x00040000 #define CONFIG_ENV_SECT_SIZE 0x00010000 -#define CONFIG_FSMTDBLK "/dev/mtdblock8 " +#define CONFIG_FSMTDBLK "/dev/mtdblock3 " #define CONFIG_BOOTCOMMAND "bootm 0xf8050000" @@ -146,8 +163,7 @@ "0x4C0000; bootm 0x1600000" #endif -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ CONFIG_SYS_MONITOR_LEN) #elif defined(CONFIG_ENV_IS_IN_NAND) /* @@ -156,28 +172,46 @@ #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_RANGE 0x10000 -#define CONFIG_FSMTDBLK "/dev/mtdblock12 " +#define CONFIG_FSMTDBLK "/dev/mtdblock7 " #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ "0x80000 0x4C0000; " \ "bootm 0x1600000" #endif -#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ - "console=ttyS0 init=/bin/sh" -#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \ +#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \ + "mem=128M " \ "root="CONFIG_FSMTDBLK \ "rootfstype=jffs2" +#define CONFIG_NFSBOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off " \ + "console=ttyAMA0,115200 $(othbootargs);" \ + "bootm; " + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=ttyAMA0,115200 $(othbootargs);" \ + CONFIG_BOOTCOMMAND + + #define CONFIG_ENV_SIZE 0x02000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_ZERO_BOOTDELAY_CHECK 1 -#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_MISC_INIT_R +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT_KEYED #define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_PROMPT \ "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay @@ -195,9 +229,9 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LOAD_ADDR 0x00800000 -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY +#define CONFIG_SYS_FLASH_EMPTY_INFO /* Stack sizes */ #define CONFIG_STACKSIZE (128*1024) diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx_evb.h index 37bdebb392..3cd56dc487 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx_evb.h @@ -29,18 +29,44 @@ * (easy to change) */ #if defined(CONFIG_spear300) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR300 1 +#define CONFIG_SPEAR3XX +#define CONFIG_SPEAR300 #elif defined(CONFIG_spear310) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR310 1 +#define CONFIG_SPEAR3XX +#define CONFIG_SPEAR310 #elif defined(CONFIG_spear320) -#define CONFIG_SPEAR3XX 1 -#define CONFIG_SPEAR320 1 +#define CONFIG_SPEAR3XX +#define CONFIG_SPEAR320 +#endif + +#if defined(CONFIG_usbtty) +#define CONFIG_SPEAR_USBTTY +#endif + +#if defined(CONFIG_nand) +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_FLASH #endif #include <configs/spear-common.h> +/* Ethernet driver configuration */ +#define CONFIG_DW_ALTDESCRIPTOR + +#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB +#define CONFIG_MACB0_PHY 0x01 + +#endif + /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000 @@ -85,6 +111,7 @@ #define CONFIG_FLASH_CFI_DRIVER #if defined(CONFIG_SPEAR310) +#define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_BASE 0x50000000 #define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 #define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 @@ -100,6 +127,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 6 #elif defined(CONFIG_SPEAR320) +#define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_FLASH_BASE 0x44000000 #define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 #define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 @@ -113,19 +141,33 @@ #endif #define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) -#define CONFIG_SYS_FLASH_QUIET_TEST 1 +#define CONFIG_SYS_FLASH_QUIET_TEST #endif +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT + #if defined(CONFIG_SPEAR300) -#define CONFIG_SYS_NAND_BASE (0x80000000) +#define CONFIG_SYS_NAND_BASE 0x80000000 #elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_NAND_BASE (0x40000000) +#define CONFIG_SYS_NAND_BASE 0x40000000 #elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_NAND_BASE (0x50000000) +#define CONFIG_SYS_NAND_BASE 0x50000000 + +#endif + +/* Environment Settings */ +#if defined(CONFIG_SPEAR300) +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY +#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320) +#define CONFIG_EXTRA_ENV_UNLOCK "unlock=yes\0" +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY \ + CONFIG_EXTRA_ENV_UNLOCK #endif #endif /* __CONFIG_H */ diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx_evb.h index 2ad5beb82c..31b872552c 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx_evb.h @@ -28,7 +28,17 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SPEAR600 1 +#define CONFIG_SPEAR600 + +#if defined(CONFIG_usbtty) +#define CONFIG_SPEAR_USBTTY +#endif + +#if defined(CONFIG_nand) +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_FLASH +#endif #include <configs/spear-common.h> @@ -38,6 +48,12 @@ #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1 } -#define CONFIG_SYS_NAND_BASE (0xD2000000) +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP +#define CONFIG_SYS_FSMC_NAND_8BIT +#define CONFIG_SYS_NAND_BASE 0xD2000000 + +/* Environment Settings */ +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY #endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h new file mode 100644 index 0000000000..3d0a78825b --- /dev/null +++ b/include/configs/tec.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011-2012 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra2-common.h" + +/* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-tec +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra2 (TEC) # " +#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" +#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_ENV_IS_NOWHERE + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* USB host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +#define CONFIG_FIT + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan;" \ + "ext2load mmc 0 0x17000000 /boot/uImage;" \ + "bootm" + +#endif /* __CONFIG_H */ diff --git a/include/configs/tegra2-common-post.h b/include/configs/tegra2-common-post.h new file mode 100644 index 0000000000..c21fc28dfe --- /dev/null +++ b/include/configs/tegra2-common-post.h @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TEGRA2_COMMON_POST_H +#define __TEGRA2_COMMON_POST_H + +#ifdef CONFIG_BOOTCOMMAND + +#define BOOTCMDS_COMMON "" + +#else + +#ifdef CONFIG_CMD_EXT2 +#define BOOT_FSTYPE_EXT2 "ext2 " +#else +#define BOOT_FSTYPE_EXT2 "" +#endif + +#ifdef CONFIG_CMD_FAT +#define BOOT_FSTYPE_FAT "fat" +#else +#define BOOT_FSTYPE_FAT "" +#endif + +#ifdef CONFIG_CMD_MMC +#define BOOTCMDS_MMC \ + "mmc_boot=" \ + "setenv devtype mmc; " \ + "if mmc dev ${devnum}; then " \ + "run scan_boot; " \ + "fi\0" \ + "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" \ + "bootcmd_mmc1=setenv devnum 1; run mmc_boot;\0" +#define BOOT_TARGETS_MMC "mmc1 mmc0" +#else +#define BOOTCMDS_MMC "" +#define BOOT_TARGETS_MMC "" +#endif + +#ifdef CONFIG_CMD_USB +#define BOOTCMD_INIT_USB "run usb_init; " +#define BOOTCMDS_USB \ + "usb_init=" \ + "if ${usb_need_init}; then " \ + "set usb_need_init false; " \ + "usb start 0; " \ + "fi\0" \ + \ + "usb_boot=" \ + "setenv devtype usb; " \ + BOOTCMD_INIT_USB \ + "if usb dev ${devnum}; then " \ + "run scan_boot; " \ + "fi\0" \ + \ + "bootcmd_usb0=setenv devnum 0; run usb_boot;\0" +#define BOOT_TARGETS_USB "usb0" +#else +#define BOOTCMD_INIT_USB "" +#define BOOTCMDS_USB "" +#define BOOT_TARGETS_USB "" +#endif + +#ifdef CONFIG_CMD_DHCP +#define BOOTCMDS_DHCP \ + "bootcmd_dhcp=" \ + BOOTCMD_INIT_USB \ + "if dhcp ${scriptaddr} boot.scr.uimg; then "\ + "source ${scriptaddr}; " \ + "fi\0" +#define BOOT_TARGETS_DHCP "dhcp" +#else +#define BOOTCMDS_DHCP "" +#define BOOT_TARGETS_DHCP "" +#endif + +#define BOOTCMDS_COMMON \ + "scriptaddr=0x400000\0" \ + \ + "rootpart=1\0" \ + \ + "script_boot=" \ + "if ${fs}load ${devtype} ${devnum}:${rootpart} " \ + "${scriptaddr} ${prefix}${script}; then " \ + "echo ${script} found! Executing ...;" \ + "source ${scriptaddr};" \ + "fi;\0" \ + \ + "scan_boot=" \ + "echo Scanning ${devtype} ${devnum}...; " \ + "for fs in ${boot_fstypes}; do " \ + "for prefix in ${boot_prefixes}; do " \ + "for script in ${boot_scripts}; do " \ + "run script_boot; " \ + "done; " \ + "done; " \ + "done;\0" \ + \ + "boot_targets=" \ + BOOT_TARGETS_MMC " " \ + BOOT_TARGETS_USB " " \ + BOOT_TARGETS_DHCP " " \ + "\0" \ + \ + "boot_fstypes=" \ + BOOT_FSTYPE_EXT2 " " \ + BOOT_FSTYPE_FAT " " \ + "\0" \ + \ + "boot_prefixes=/ /boot/\0" \ + \ + "boot_scripts=boot.scr.uimg boot.scr\0" \ + \ + BOOTCMDS_MMC \ + BOOTCMDS_USB \ + BOOTCMDS_DHCP + +#define CONFIG_BOOTCOMMAND \ + "for target in ${boot_targets}; do run bootcmd_${target}; done" + +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + TEGRA2_DEVICE_SETTINGS \ + "fdt_load=0x01000000\0" \ + "fdt_high=01100000\0" \ + BOOTCMDS_COMMON + +#endif /* __TEGRA2_COMMON_POST_H */ diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 52dc38e60e..680776270b 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2012 * NVIDIA Corporation <www.nvidia.com> * * See file CREDITS for list of people who contributed to this @@ -68,6 +68,7 @@ #endif /* Environment */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ /* @@ -139,12 +140,6 @@ "stdout=serial\0" \ "stderr=serial\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttyS0,115200n8\0" \ - "mem=" TEGRA2_SYSMEM "\0" \ - "smpflag=smp\0" \ - TEGRA2_DEVICE_SETTINGS - #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ @@ -196,6 +191,8 @@ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) -#define CONFIG_TEGRA2_GPIO +#define CONFIG_TEGRA_GPIO #define CONFIG_CMD_GPIO +#define CONFIG_CMD_ENTERRCM +#define CONFIG_CMD_BOOTZ #endif /* __TEGRA2_COMMON_H */ diff --git a/include/configs/tk71.h b/include/configs/tk71.h new file mode 100644 index 0000000000..f929f203ab --- /dev/null +++ b/include/configs/tk71.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2012 Marek Vasut <marex@denx.de> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __CONFIG_TK71_H__ +#define __CONFIG_TK71_H__ + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKa-Ro TK71" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define MACH_TYPE_TK71 2399 +#define CONFIG_MACH_TYPE MACH_TYPE_TK71 + +/* + * Commands configuration + */ +#define CONFIG_SYS_HUSH_PARSER + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * NAND flash + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "nand0,3" +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} +#define CONFIG_PHY_BASE_ADR 0x08 +#endif + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_KIRKWOOD +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_ADDR 0x80000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;" +#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \ + "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \ + "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \ + "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \ + "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0" +#define MTDIDS_DEFAULT "nand0=orion_nand" +#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS + +#define PHYS_SDRAM_1 0x00000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ + +#endif /* __CONFIG_TK71_H__ */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h new file mode 100644 index 0000000000..34be8a98a1 --- /dev/null +++ b/include/configs/trimslice.h @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> +#include "tegra2-common.h" + +/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-trimslice +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra2 (TrimSlice) # " +#define CONFIG_TEGRA2_BOARD_STRING "Compulab Trimslice" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA +#define CONFIG_TEGRA2_UARTA_GPU +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* SPI */ +#define CONFIG_TEGRA_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* Environment in SPI */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ 48000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (512 * 1024) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra2-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 3e55fe5d1a..5e4d53861c 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -28,12 +28,11 @@ #include "tegra2-common.h" /* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */ -#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-ventana #define CONFIG_OF_CONTROL #define CONFIG_OF_SEPARATE /* High-level configuration options */ -#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (Ventana) # " #define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Ventana" @@ -43,14 +42,13 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #define CONFIG_MACH_TYPE MACH_TYPE_VENTANA -#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -#define CONFIG_TEGRA2_MMC +#define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION @@ -58,6 +56,25 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT -/* Environment not stored */ -#define CONFIG_ENV_IS_NOWHERE +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 1024 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra2-common-post.h" + #endif /* __CONFIG_H */ diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 24905a0129..0ed53d2e04 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -212,12 +212,13 @@ */ #define CONFIG_PREBOOT #define CONFIG_VIDEO -#define CONFIG_VIDEO_MX5 +#define CONFIG_VIDEO_IPUV3 #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP +#define CONFIG_IPUV3_CLK 133000000 #endif /* __CONFIG_H */ diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h new file mode 100644 index 0000000000..24f89c98e4 --- /dev/null +++ b/include/configs/vl_ma2sc.h @@ -0,0 +1,463 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig <esw@bus-elekronik.de> + * BuS Elektronik GmbH & Co. KG + * + * Configuation settings for the VL_MA2SC board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*--------------------------------------------------------------------------*/ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ +#define CONFIG_AT91FAMILY +#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_MISC_INIT_R + +#include <asm/hardware.h> + +#define MACH_TYPE_VL_MA2SC 2412 +#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC + +#define CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_RAMLOAD +#define CONFIG_SYS_TEXT_BASE 0x21000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#endif +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_IDENT_STRING " on MiS Activ 2" +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AT91_GPIO + +#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) +#define CONFIG_SYS_USE_NORFLASH +#define CONFIG_SYS_USE_BOOT_NORFLASH +#endif + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * Hardware drivers + */ + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_WATCHDOG + +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* LCD */ +#define CONFIG_LCD +#define CONFIG_ATMEL_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SYS_BLACK_ON_WHITE +#define LCD_BPP LCD_COLOR8 +#define CONFIG_ATMEL_LCD_BGR555 + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_BMP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_SHA1SUM +/* +#define CONFIG_CMD_SPI +*/ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_LONGHELP +#define CONFIG_MD5 +#define CONFIG_SHA1 + +/*---------------------------------------------------------------------------- + * Hardware confuguration + *---------------------------------------------------------------------------*/ + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_AT91C_PQFP_UHPBUG + +/* I2C-Bus */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ + +#ifndef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C + +/* Software I2C driver configuration */ + +#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) + +#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ +#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ + +#define I2C_INIT i2c_init_board(); +#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); +#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); +#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SDA, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SDA, &pio->piob.codr); \ + } while (0); +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SCL, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SCL, &pio->piob.codr); \ + } while (0); +#endif + +/* I2C-RTC */ + +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#endif + +/* EEPROM */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 + +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_MR_URSTEN | \ + AT91_RSTC_MR_ERSTL(15)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xFFF) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xFFF)) + +/* clocks */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define MHZ180 +#if defined(MHZ199) +/* 199,8994 MHZ */ +#define MASTER_PLL_MUL 911 +#define MASTER_PLL_DIV 56 +#define MASTER_PLL_OUT 2 +#elif defined(MHZ180) +/* 180 MHZ */ +#define MASTER_PLL_MUL 1875 +#define MASTER_PLL_DIV 128 +#define MASTER_PLL_OUT 2 +#elif defined(MHZTEST) +/* Test MHZ */ +#define CONFIG_DISPLAY_CPUINFO +#define MASTER_PLL_MUL 8 +#define MASTER_PLL_DIV 1 +#define MASTER_PLL_OUT 2 +#else +/* 176.9472 MHZ */ +#define MASTER_PLL_MUL 72 +#define MASTER_PLL_DIV 5 +#define MASTER_PLL_OUT 2 +#endif + +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) + +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | \ + AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ + AT91_PMC_PLLXR_PLLCOUNT(63) | \ + AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ + +#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CONFIG_SYS_SDRC_TR_VAL1 700 +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* NOR flash */ + +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +/* Address and size of Primary Environment Sector */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ + 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifndef CONFIG_RAMLOAD +#define CONFIG_BOOTCOMMAND "run nfsboot" +#endif +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 15 + +#define CONFIG_NFSBOOTCOMMAND \ + "dhcp $(copy_addr) $(kernelname);" \ + "run bootargsdefaults;" \ + "set bootargs $(bootargs) boot=nfs " \ + ";echo $(bootargs)" \ + ";bootm" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubootaddr=10000000\0" \ + "splashimage=10080000\0" \ + "kerneladdr=100A0000\0" \ + "kernelsize=00800000\0" \ + "minifsaddr=108A0000\0" \ + "minifssize=00060000\0" \ + "rootfsaddr=10900000\0" \ + "copy_addr=20200000\0" \ + "rootfssize=01700000\0" \ + "kernelname=uImage_vl_ma2sc\0" \ + "bootargsdefaults=set bootargs " \ + "console=ttyS0,115200 " \ + "video=atmel_lcdfb " \ + "mem=62M " \ + "panic=10 " \ + "boardrevison=\\\"${revision}\\\" " \ + "uboot=\\\"${ver}\\\" " \ + "\0" \ + "update_all=run update_kernel;run update_root;" \ + "run update_splash; run update_uboot\0" \ + "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ + "dhcp $(copy_addr) $(kernelname);" \ + "erase $(kerneladdr) +$(kernelsize);" \ + "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ + "protect on $(kerneladdr) +$(kernelsize)" \ + "\0" \ + "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ + "dhcp $(copy_addr) vl_ma2sc.root;" \ + "erase $(rootfsaddr) +$(rootfssize);" \ + "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ + "\0" \ + "update_splash=protect off $(splashimage) +20000;" \ + "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ + "erase $(splashimage) +20000;" \ + "cp.b $(fileaddr) 10080000 $(filesize);" \ + "protect on $(splashimage) +20000\0" \ + "update_uboot=protect off 10000000 1005FFFF;" \ + "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ + "erase 10000000 1005FFFF;" \ + "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ + "protect on 10000000 1005FFFF;reset\0" \ + "emergency=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(kerneladdr)\0" \ + "netemergency=run bootargsdefaults;" \ + "dhcp $(copy_addr) $(kernelname);" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(copy_addr)\0" \ + "norboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=local quiet " \ + ";bootm $(kerneladdr)\0" \ + "nandboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=nand " \ + ";bootm $(kerneladdr)\0" \ + "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ + "clearenv=protect off 10060000 1007FFFF;" \ + "erase 10060000 1007FFFF;reset\0" \ + " " + +/*--------------------------------------------------------------------------*/ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 059a53abc8..61e02e6077 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -198,7 +198,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ /* * Local Bus LCRR and LBCR regs diff --git a/include/configs/whistler.h b/include/configs/whistler.h new file mode 100644 index 0000000000..f2952d5f45 --- /dev/null +++ b/include/configs/whistler.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2010-2012 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> +#include "tegra2-common.h" + +/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-whistler +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra2 (Whistler) # " +#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Whistler" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTA +#define CONFIG_TEGRA2_UARTA_UAA_UAB +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE + +#define CONFIG_MACH_TYPE MACH_TYPE_WHISTLER + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes + * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If + * they didn't, the boot sector layout may be different. However, use of that + * particular card is standard practice as far as I know. + */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET ((2 * 512 * 1024) - CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra2-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index a330bd01a4..8e6377019b 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -32,6 +32,7 @@ #undef CONFIG_BOARD_LATE_INIT #undef CONFIG_USE_IRQ #undef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_PREBOOT /* * Environment settings diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h new file mode 100644 index 0000000000..3a61cea662 --- /dev/null +++ b/include/linux/mtd/fsmc_nand.h @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSMC_NAND_H__ +#define __FSMC_NAND_H__ + +#include <linux/mtd/nand.h> + +struct fsmc_regs { + u32 ctrl; /* 0x00 */ + u8 reserved_1[0x40 - 0x04]; + u32 pc; /* 0x40 */ + u32 sts; /* 0x44 */ + u32 comm; /* 0x48 */ + u32 attrib; /* 0x4c */ + u32 ioata; /* 0x50 */ + u32 ecc1; /* 0x54 */ + u32 ecc2; /* 0x58 */ + u32 ecc3; /* 0x5c */ + u8 reserved_2[0xfe0 - 0x60]; + u32 peripid0; /* 0xfe0 */ + u32 peripid1; /* 0xfe4 */ + u32 peripid2; /* 0xfe8 */ + u32 peripid3; /* 0xfec */ + u32 pcellid0; /* 0xff0 */ + u32 pcellid1; /* 0xff4 */ + u32 pcellid2; /* 0xff8 */ + u32 pcellid3; /* 0xffc */ +}; + +/* ctrl register definitions */ +#define FSMC_WP (1 << 7) + +/* pc register definitions */ +#define FSMC_RESET (1 << 0) +#define FSMC_WAITON (1 << 1) +#define FSMC_ENABLE (1 << 2) +#define FSMC_DEVTYPE_NAND (1 << 3) +#define FSMC_DEVWID_8 (0 << 4) +#define FSMC_DEVWID_16 (1 << 4) +#define FSMC_ECCEN (1 << 6) +#define FSMC_ECCPLEN_512 (0 << 7) +#define FSMC_ECCPLEN_256 (1 << 7) +#define FSMC_TCLR_1 (1 << 9) +#define FSMC_TAR_1 (1 << 13) + +/* sts register definitions */ +#define FSMC_CODE_RDY (1 << 15) + +/* comm register definitions */ +#define FSMC_TSET_0 (0 << 0) +#define FSMC_TWAIT_6 (6 << 8) +#define FSMC_THOLD_4 (4 << 16) +#define FSMC_THIZ_1 (1 << 24) + +/* peripid2 register definitions */ +#define FSMC_REVISION_MSK (0xf) +#define FSMC_REVISION_SHFT (0x4) + +#define FSMC_VER8 0x8 + +/* + * There are 13 bytes of ecc for every 512 byte block and it has to be read + * consecutively and immediately after the 512 byte data block for hardware to + * generate the error bit offsets + * Managing the ecc bytes in the following way is easier. This way is similar to + * oobfree structure maintained already in u-boot nand driver + */ +#define FSMC_MAX_ECCPLACE_ENTRIES 32 + +struct fsmc_nand_eccplace { + u32 offset; + u32 length; +}; + +struct fsmc_eccplace { + struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES]; +}; + +extern int fsmc_nand_init(struct nand_chip *nand); +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/include/linux/mtd/st_smi.h index 06df74557f..04f81ea5b0 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/include/linux/mtd/st_smi.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef SPR_SMI_H -#define SPR_SMI_H +#ifndef ST_SMI_H +#define ST_SMI_H /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ @@ -109,7 +109,9 @@ struct flash_dev { }; #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ +#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ +#define WMODE_TOUT 15 /* write enable timeout(in ms) */ + +extern void smi_init(void); #endif diff --git a/include/net.h b/include/net.h index a092f291bb..6d2d6cd849 100644 --- a/include/net.h +++ b/include/net.h @@ -122,6 +122,23 @@ extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr); extern int eth_getenv_enetaddr_by_index(const char *base_name, int index, uchar *enetaddr); +#ifdef CONFIG_RANDOM_MACADDR +/* + * The u-boot policy does not allow hardcoded ethernet addresses. Under the + * following circumstances a random generated address is allowed: + * - in emergency cases, where you need a working network connection to set + * the ethernet address. + * Eg. you want a rescue boot and don't have a serial port to access the + * CLI to set environment variables. + * + * In these cases, we generate a random locally administered ethernet address. + * + * Args: + * enetaddr - returns 6 byte hardware address + */ +extern void eth_random_enetaddr(uchar *enetaddr); +#endif + extern int usb_eth_initialize(bd_t *bi); extern int eth_init(bd_t *bis); /* Initialize the device */ extern int eth_send(void *packet, int length); /* Send a packet */ diff --git a/include/netdev.h b/include/netdev.h index 4724717d99..d1aaf0cd2d 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -52,7 +52,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr); +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); diff --git a/include/usb.h b/include/usb.h index 6da91e7232..ba3d169ea8 100644 --- a/include/usb.h +++ b/include/usb.h @@ -29,6 +29,16 @@ #include <usb_defs.h> #include <usbdescriptors.h> +/* + * The EHCI spec says that we must align to at least 32 bytes. However, + * some platforms require larger alignment. + */ +#if ARCH_DMA_MINALIGN > 32 +#define USB_DMA_MINALIGN ARCH_DMA_MINALIGN +#else +#define USB_DMA_MINALIGN 32 +#endif + /* Everything is aribtrary */ #define USB_ALTSETTINGALLOC 4 #define USB_MAXALTSETTING 128 /* Hard limit */ diff --git a/lib/Makefile b/lib/Makefile index 1e8478f031..c60c380361 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -37,7 +37,6 @@ COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o COBJS-$(CONFIG_USB_TTY) += circbuf.o COBJS-y += crc7.o COBJS-y += crc16.o -COBJS-y += crc32.o COBJS-y += display_options.o COBJS-y += errno.o COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o @@ -60,14 +59,18 @@ endif ifdef CONFIG_SPL_BUILD COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o endif +COBJS-y += crc32.o COBJS-y += ctype.o COBJS-y += div64.o COBJS-y += string.o COBJS-y += time.o COBJS-$(CONFIG_BOOTP_PXE) += uuid.o COBJS-y += vsprintf.o +COBJS-$(CONFIG_RANDOM_MACADDR) += rand.o +COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o +COBJS-$(CONFIG_CMD_LINK_LOCAL) += rand.o -COBJS := $(COBJS-y) +COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/lib/addr_map.c b/lib/addr_map.c index ff8532cf15..31384d1398 100644 --- a/lib/addr_map.c +++ b/lib/addr_map.c @@ -47,26 +47,29 @@ phys_addr_t addrmap_virt_to_phys(void * vaddr) return (phys_addr_t)(~0); } -unsigned long addrmap_phys_to_virt(phys_addr_t paddr) +void *addrmap_phys_to_virt(phys_addr_t paddr) { int i; for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++) { - u64 base, upper, addr; + phys_addr_t base, upper; if (address_map[i].size == 0) continue; - addr = (u64)paddr; - base = (u64)(address_map[i].paddr); - upper = (u64)(address_map[i].size) + base - 1; + base = address_map[i].paddr; + upper = address_map[i].size + base - 1; - if (addr >= base && addr <= upper) { - return paddr - address_map[i].paddr + address_map[i].vaddr; + if (paddr >= base && paddr <= upper) { + phys_addr_t offset; + + offset = address_map[i].paddr - address_map[i].vaddr; + + return (void *)(unsigned long)(paddr - offset); } } - return (unsigned long)(~0); + return (void *)(~0); } void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr, diff --git a/board/avionic-design/medcom/medcom.c b/lib/rand.c index 42c80940c1..c9764f5c1a 100644 --- a/board/avionic-design/medcom/medcom.c +++ b/lib/rand.c @@ -1,8 +1,9 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011 - * Avionic Design GmbH <www.avionic-design.de> + * Simple xorshift PRNG + * see http://www.jstatsoft.org/v08/i14/paper + * + * Copyright (c) 2012 Michael Walle + * Michael Walle <michael@walle.cc> * * See file CREDITS for list of people who contributed to this * project. @@ -24,22 +25,24 @@ */ #include <common.h> -#include <asm/io.h> -#include <asm/gpio.h> -#include <asm/arch/tegra2.h> -#ifdef CONFIG_TEGRA2_MMC -#include <mmc.h> -#endif -#ifdef CONFIG_TEGRA2_MMC -/* - * Routine: gpio_config_mmc - * Description: Set GPIOs for SD card - */ -void gpio_config_mmc(void) +static unsigned int y = 1U; + +unsigned int rand_r(unsigned int *seedp) +{ + *seedp ^= (*seedp << 13); + *seedp ^= (*seedp >> 17); + *seedp ^= (*seedp << 5); + + return *seedp; +} + +unsigned int rand(void) +{ + return rand_r(&y); +} + +void srand(unsigned int seed) { - /* configure pin as input for card detect */ - gpio_request(GPIO_PH2, "SD4 CD"); - gpio_direction_input(GPIO_PH2); + y = seed; } -#endif @@ -161,6 +161,14 @@ for i in ${TARGETS} ; do echo "#define CONFIG_${i}" >>config.h ; done +echo "#define CONFIG_SYS_ARCH \"${arch}\"" >> config.h +echo "#define CONFIG_SYS_CPU \"${cpu}\"" >> config.h +echo "#define CONFIG_SYS_BOARD \"${board}\"" >> config.h + +[ "${vendor}" ] && echo "#define CONFIG_SYS_VENDOR \"${vendor}\"" >> config.h + +[ "${soc}" ] && echo "#define CONFIG_SYS_SOC \"${soc}\"" >> config.h + cat << EOF >> config.h #define CONFIG_BOARDDIR board/$BOARDDIR #include <config_cmd_defaults.h> diff --git a/net/Makefile b/net/Makefile index 526468718a..e7764ce932 100644 --- a/net/Makefile +++ b/net/Makefile @@ -34,8 +34,6 @@ COBJS-$(CONFIG_CMD_DNS) += dns.o COBJS-$(CONFIG_CMD_NET) += eth.o COBJS-$(CONFIG_CMD_LINK_LOCAL) += link_local.o COBJS-$(CONFIG_CMD_NET) += net.o -COBJS-$(CONFIG_BOOTP_RANDOM_DELAY) += net_rand.o -COBJS-$(CONFIG_CMD_LINK_LOCAL) += net_rand.o COBJS-$(CONFIG_CMD_NFS) += nfs.o COBJS-$(CONFIG_CMD_PING) += ping.o COBJS-$(CONFIG_CMD_RARP) += rarp.o @@ -194,7 +194,7 @@ void ArpReceive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len) #ifdef CONFIG_KEEP_SERVERADDR if (NetServerIP == NetArpWaitPacketIP) { char buf[20]; - sprintf(buf, "%pM", arp->ar_sha); + sprintf(buf, "%pM", &arp->ar_sha); setenv("serveraddr", buf); } #endif diff --git a/net/bootp.c b/net/bootp.c index 0f0867b1c4..c9b8349b36 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -12,12 +12,14 @@ #include <command.h> #include <net.h> #include "bootp.h" -#include "net_rand.h" #include "tftp.h" #include "nfs.h" #ifdef CONFIG_STATUS_LED #include <status_led.h> #endif +#ifdef CONFIG_BOOTP_RANDOM_DELAY +#include "net_rand.h" +#endif #define BOOTP_VENDOR_MAGIC 0x63825363 /* RFC1048 Magic Cookie */ @@ -328,7 +330,7 @@ BootpTimeout(void) if (BootpTry >= TIMEOUT_COUNT) { #ifdef CONFIG_BOOTP_MAY_FAIL puts("\nRetry count exceeded\n"); - NetSetState(NETLOOP_FAIL); + net_set_state(NETLOOP_FAIL); #else puts("\nRetry count exceeded; starting again\n"); NetStartAgain(); @@ -62,6 +62,15 @@ int eth_getenv_enetaddr_by_index(const char *base_name, int index, return eth_getenv_enetaddr(enetvar, enetaddr); } +static inline int eth_setenv_enetaddr_by_index(const char *base_name, int index, + uchar *enetaddr) +{ + char enetvar[32]; + sprintf(enetvar, index ? "%s%daddr" : "%saddr", base_name, index); + return eth_setenv_enetaddr(enetvar, enetaddr); +} + + static int eth_mac_skip(int index) { char enetvar[15]; @@ -70,6 +79,28 @@ static int eth_mac_skip(int index) return ((skip_state = getenv(enetvar)) != NULL); } +#ifdef CONFIG_RANDOM_MACADDR +void eth_random_enetaddr(uchar *enetaddr) +{ + uint32_t rval; + + srand(get_timer(0)); + + rval = rand(); + enetaddr[0] = rval & 0xff; + enetaddr[1] = (rval >> 8) & 0xff; + enetaddr[2] = (rval >> 16) & 0xff; + + rval = rand(); + enetaddr[3] = rval & 0xff; + enetaddr[4] = (rval >> 8) & 0xff; + enetaddr[5] = (rval >> 16) & 0xff; + + /* make sure it's local and unicast */ + enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01; +} +#endif + /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on @@ -183,6 +214,11 @@ int eth_write_hwaddr(struct eth_device *dev, const char *base_name, } memcpy(dev->enetaddr, env_enetaddr, 6); + } else if (is_valid_ether_addr(dev->enetaddr)) { + eth_setenv_enetaddr_by_index(base_name, eth_number, + dev->enetaddr); + printf("\nWarning: %s using MAC address from net device\n", + dev->name); } if (dev->write_hwaddr && diff --git a/net/link_local.c b/net/link_local.c index 336286395b..d52f13adb4 100644 --- a/net/link_local.c +++ b/net/link_local.c @@ -56,6 +56,7 @@ static unsigned conflicts; static unsigned nprobes; static unsigned nclaims; static int ready; +static unsigned int seed; static void link_local_timeout(void); @@ -68,7 +69,7 @@ static IPaddr_t pick(void) unsigned tmp; do { - tmp = rand() & IN_CLASSB_HOST; + tmp = rand_r(&seed) & IN_CLASSB_HOST; } while (tmp > (IN_CLASSB_HOST - 0x0200)); return (IPaddr_t) htonl((LINKLOCAL_ADDR + 0x0100) + tmp); } @@ -78,7 +79,7 @@ static IPaddr_t pick(void) */ static inline unsigned random_delay_ms(unsigned secs) { - return rand() % (secs * 1000); + return rand_r(&seed) % (secs * 1000); } static void configure_wait(void) @@ -109,7 +110,7 @@ void link_local_start(void) } NetOurSubnetMask = IN_CLASSB_NET; - srand_mac(); + seed = seed_mac(); if (ip == 0) ip = pick(); @@ -224,12 +225,13 @@ void link_local_receive_arp(struct arp_hdr *arp, int len) timeout_ms = diff | 1; /* never 0 */ } } -/* - * XXX Don't bother with ethernet link just yet +#if 0 + /* XXX Don't bother with ethernet link just yet */ if ((fds[0].revents & POLLIN) == 0) { if (fds[0].revents & POLLERR) { - // FIXME: links routinely go down; - // this shouldn't necessarily exit. + /* + * FIXME: links routinely go down; + */ bb_error_msg("iface %s is down", eth_get_name()); if (ready) { run(argv, "deconfig", &ip); @@ -238,7 +240,7 @@ void link_local_receive_arp(struct arp_hdr *arp, int len) } continue; } -*/ +#endif debug_cond(DEBUG_INT_STATE, "%s recv arp type=%d, op=%d,\n", eth_get_name(), ntohs(arp->ar_pro), @@ -256,6 +256,7 @@ static void NetInitLoop(void) #endif env_changed_id = env_id; } + memcpy(NetOurEther, eth_get_dev()->enetaddr, 6); return; } @@ -322,8 +323,6 @@ int NetLoop(enum proto_t protocol) } restart: - memcpy(NetOurEther, eth_get_dev()->enetaddr, 6); - net_set_state(NETLOOP_CONTINUE); /* diff --git a/net/net_rand.c b/net/net_rand.c deleted file mode 100644 index 5387abadcf..0000000000 --- a/net/net_rand.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Based on LiMon - BOOTP. - * - * Copyright 1994, 1995, 2000 Neil Russell. - * (See License) - * Copyright 2000 Roland Borde - * Copyright 2000 Paolo Scaffardi - * Copyright 2000-2004 Wolfgang Denk, wd@denx.de - */ - -#include <common.h> -#include <net.h> -#include "net_rand.h" - -static ulong seed1, seed2; - -void srand_mac(void) -{ - ulong tst1, tst2, m_mask; - ulong m_value = 0; - int reg; - unsigned char bi_enetaddr[6]; - - /* get our mac */ - eth_getenv_enetaddr("ethaddr", bi_enetaddr); - - debug("BootpRequest => Our Mac: "); - for (reg = 0; reg < 6; reg++) - debug("%x%c", bi_enetaddr[reg], reg == 5 ? '\n' : ':'); - - /* Mac-Manipulation 2 get seed1 */ - tst1 = 0; - tst2 = 0; - for (reg = 2; reg < 6; reg++) { - tst1 = tst1 << 8; - tst1 = tst1 | bi_enetaddr[reg]; - } - for (reg = 0; reg < 2; reg++) { - tst2 = tst2 | bi_enetaddr[reg]; - tst2 = tst2 << 8; - } - - seed1 = tst1^tst2; - - /* Mirror seed1*/ - m_mask = 0x1; - for (reg = 1; reg <= 32; reg++) { - m_value |= (m_mask & seed1); - seed1 = seed1 >> 1; - m_value = m_value << 1; - } - seed1 = m_value; - seed2 = 0xb78d0945; -} - -unsigned long rand(void) -{ - ulong sum; - - /* Random Number Generator */ - sum = seed1 + seed2; - if (sum < seed1 || sum < seed2) - sum++; - seed2 = seed1; - seed1 = sum; - - return sum; -} diff --git a/net/net_rand.h b/net/net_rand.h index c98db64280..ba9d0642cf 100644 --- a/net/net_rand.h +++ b/net/net_rand.h @@ -9,18 +9,35 @@ #ifndef __NET_RAND_H__ #define __NET_RAND_H__ -#define RAND_MAX 0xffffffff +#include <common.h> /* - * Seed the random number generator using the eth0 MAC address + * Return a seed for the PRNG derived from the eth0 MAC address. */ -void srand_mac(void); +static inline unsigned int seed_mac(void) +{ + unsigned char enetaddr[6]; + unsigned int seed; + + /* get our mac */ + eth_getenv_enetaddr("ethaddr", enetaddr); + + seed = enetaddr[5]; + seed ^= enetaddr[4] << 8; + seed ^= enetaddr[3] << 16; + seed ^= enetaddr[2] << 24; + seed ^= enetaddr[1]; + seed ^= enetaddr[0] << 8; + + return seed; +} /* - * Get a random number (after seeding with MAC address) - * - * @return random number + * Seed the random number generator using the eth0 MAC address. */ -unsigned long rand(void); +static inline void srand_mac(void) +{ + srand(seed_mac()); +} #endif /* __NET_RAND_H__ */ @@ -31,7 +31,11 @@ #define HASHES_PER_LINE 65 /* Number of "loading" hashes per line */ #define NFS_RETRY_COUNT 30 -#define NFS_TIMEOUT 2000UL +#ifndef CONFIG_NFS_TIMEOUT +# define NFS_TIMEOUT 2000UL +#else +# define NFS_TIMEOUT CONFIG_NFS_TIMEOUT +#endif static int fs_mounted; static unsigned long rpc_id; diff --git a/net/tftp.c b/net/tftp.c index b2e08b4bfb..59a8ebb3cf 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -156,7 +156,7 @@ mcast_cleanup(void) #endif /* CONFIG_MCAST_TFTP */ static inline void -store_block(unsigned block, uchar *src, unsigned len) +store_block(int block, uchar *src, unsigned len) { ulong offset = block * TftpBlkSize + TftpBlockWrapOffset; ulong newsize = offset + len; diff --git a/tools/.gitignore b/tools/.gitignore index e4d2c2f55e..3557a75b9e 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -9,7 +9,7 @@ /ncb /ncp /ubsha1 -/inca-swap-bytes +/xway-swap-bytes /*.exe /easylogo/easylogo /env/crc32.c diff --git a/tools/Makefile b/tools/Makefile index 8993fdd7b2..a7d1e18fe2 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -72,6 +72,7 @@ BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) +BIN_FILES-$(CONFIG_KIRKWOOD) += kwboot$(SFX) # Source files which exist outside the tools directory EXT_OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += common/env_embedded.o @@ -101,6 +102,7 @@ OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o NOPED_OBJ_FILES-y += ublimage.o +OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o # Don't build by default #ifeq ($(ARCH),ppc) @@ -194,7 +196,8 @@ $(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ -$(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o +$(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o \ + $(obj)os_support.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ @@ -234,6 +237,10 @@ $(obj)ncb$(SFX): $(obj)ncb.o $(obj)ubsha1$(SFX): $(obj)os_support.o $(obj)sha1.o $(obj)ubsha1.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ +$(obj)kwboot$(SFX): $(obj)kwboot.o + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ + $(HOSTSTRIP) $@ + # Some of the tool objects need to be accessed from outside the tools directory $(obj)%.o: $(SRCTREE)/common/%.c $(HOSTCC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< diff --git a/tools/kwboot.c b/tools/kwboot.c new file mode 100644 index 0000000000..e773f01df3 --- /dev/null +++ b/tools/kwboot.c @@ -0,0 +1,742 @@ +/* + * Boot a Marvell Kirkwood SoC, with Xmodem over UART0. + * + * (c) 2012 Daniel Stodden <daniel.stodden@gmail.com> + * + * References: marvell.com, "88F6180, 88F6190, 88F6192, and 88F6281 + * Integrated Controller: Functional Specifications" December 2, + * 2008. Chapter 24.2 "BootROM Firmware". + */ + +#include <stdlib.h> +#include <stdio.h> +#include <string.h> +#include <stdarg.h> +#include <libgen.h> +#include <fcntl.h> +#include <errno.h> +#include <unistd.h> +#include <stdint.h> +#include <termios.h> +#include <sys/mman.h> +#include <sys/stat.h> + +#include "kwbimage.h" + +#ifdef __GNUC__ +#define PACKED __attribute((packed)) +#else +#define PACKED +#endif + +/* + * Marvell BootROM UART Sensing + */ + +static unsigned char kwboot_msg_boot[] = { + 0xBB, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 +}; + +#define KWBOOT_MSG_REQ_DELAY 10 /* ms */ +#define KWBOOT_MSG_RSP_TIMEO 50 /* ms */ + +/* + * Xmodem Transfers + */ + +#define SOH 1 /* sender start of block header */ +#define EOT 4 /* sender end of block transfer */ +#define ACK 6 /* target block ack */ +#define NAK 21 /* target block negative ack */ +#define CAN 24 /* target/sender transfer cancellation */ + +struct kwboot_block { + uint8_t soh; + uint8_t pnum; + uint8_t _pnum; + uint8_t data[128]; + uint8_t csum; +} PACKED; + +#define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */ + +static int kwboot_verbose; + +static void +kwboot_printv(const char *fmt, ...) +{ + va_list ap; + + if (kwboot_verbose) { + va_start(ap, fmt); + vprintf(fmt, ap); + va_end(ap); + fflush(stdout); + } +} + +static void +__spinner(void) +{ + const char seq[] = { '-', '\\', '|', '/' }; + const int div = 8; + static int state, bs; + + if (state % div == 0) { + fputc(bs, stdout); + fputc(seq[state / div % sizeof(seq)], stdout); + fflush(stdout); + } + + bs = '\b'; + state++; +} + +static void +kwboot_spinner(void) +{ + if (kwboot_verbose) + __spinner(); +} + +static void +__progress(int pct, char c) +{ + const int width = 70; + static const char *nl = ""; + static int pos; + + if (pos % width == 0) + printf("%s%3d %% [", nl, pct); + + fputc(c, stdout); + + nl = "]\n"; + pos++; + + if (pct == 100) { + while (pos++ < width) + fputc(' ', stdout); + fputs(nl, stdout); + } + + fflush(stdout); + +} + +static void +kwboot_progress(int _pct, char c) +{ + static int pct; + + if (_pct != -1) + pct = _pct; + + if (kwboot_verbose) + __progress(pct, c); +} + +static int +kwboot_tty_recv(int fd, void *buf, size_t len, int timeo) +{ + int rc, nfds; + fd_set rfds; + struct timeval tv; + ssize_t n; + + rc = -1; + + FD_ZERO(&rfds); + FD_SET(fd, &rfds); + + tv.tv_sec = 0; + tv.tv_usec = timeo * 1000; + if (tv.tv_usec > 1000000) { + tv.tv_sec += tv.tv_usec / 1000000; + tv.tv_usec %= 1000000; + } + + do { + nfds = select(fd + 1, &rfds, NULL, NULL, &tv); + if (nfds < 0) + goto out; + if (!nfds) { + errno = ETIMEDOUT; + goto out; + } + + n = read(fd, buf, len); + if (n < 0) + goto out; + + buf = (char *)buf + n; + len -= n; + } while (len > 0); + + rc = 0; +out: + return rc; +} + +static int +kwboot_tty_send(int fd, const void *buf, size_t len) +{ + int rc; + ssize_t n; + + rc = -1; + + do { + n = write(fd, buf, len); + if (n < 0) + goto out; + + buf = (char *)buf + n; + len -= n; + } while (len > 0); + + rc = tcdrain(fd); +out: + return rc; +} + +static int +kwboot_tty_send_char(int fd, unsigned char c) +{ + return kwboot_tty_send(fd, &c, 1); +} + +static speed_t +kwboot_tty_speed(int baudrate) +{ + switch (baudrate) { + case 115200: + return B115200; + case 57600: + return B57600; + case 38400: + return B38400; + case 19200: + return B19200; + case 9600: + return B9600; + } + + return -1; +} + +static int +kwboot_open_tty(const char *path, speed_t speed) +{ + int rc, fd; + struct termios tio; + + rc = -1; + + fd = open(path, O_RDWR|O_NOCTTY|O_NDELAY); + if (fd < 0) + goto out; + + memset(&tio, 0, sizeof(tio)); + + tio.c_iflag = 0; + tio.c_cflag = CREAD|CLOCAL|CS8; + + tio.c_cc[VMIN] = 1; + tio.c_cc[VTIME] = 10; + + cfsetospeed(&tio, speed); + cfsetispeed(&tio, speed); + + rc = tcsetattr(fd, TCSANOW, &tio); + if (rc) + goto out; + + rc = fd; +out: + if (rc < 0) { + if (fd >= 0) + close(fd); + } + + return rc; +} + +static int +kwboot_bootmsg(int tty, void *msg) +{ + int rc; + char c; + + kwboot_printv("Sending boot message. Please reboot the target..."); + + do { + rc = tcflush(tty, TCIOFLUSH); + if (rc) + break; + + rc = kwboot_tty_send(tty, msg, 8); + if (rc) { + usleep(KWBOOT_MSG_REQ_DELAY * 1000); + continue; + } + + rc = kwboot_tty_recv(tty, &c, 1, KWBOOT_MSG_RSP_TIMEO); + + kwboot_spinner(); + + } while (rc || c != NAK); + + kwboot_printv("\n"); + + return rc; +} + +static int +kwboot_xm_makeblock(struct kwboot_block *block, const void *data, + size_t size, int pnum) +{ + const size_t blksz = sizeof(block->data); + size_t n; + int i; + + block->pnum = pnum; + block->_pnum = ~block->pnum; + + n = size < blksz ? size : blksz; + memcpy(&block->data[0], data, n); + memset(&block->data[n], 0, blksz - n); + + block->csum = 0; + for (i = 0; i < n; i++) + block->csum += block->data[i]; + + return n; +} + +static int +kwboot_xm_sendblock(int fd, struct kwboot_block *block) +{ + int rc, retries; + char c; + + retries = 16; + do { + rc = kwboot_tty_send(fd, block, sizeof(*block)); + if (rc) + break; + + rc = kwboot_tty_recv(fd, &c, 1, KWBOOT_BLK_RSP_TIMEO); + if (rc) + break; + + if (c != ACK) + kwboot_progress(-1, '+'); + + } while (c == NAK && retries-- > 0); + + rc = -1; + + switch (c) { + case ACK: + rc = 0; + break; + case NAK: + errno = EBADMSG; + break; + case CAN: + errno = ECANCELED; + break; + default: + errno = EPROTO; + break; + } + + return rc; +} + +static int +kwboot_xmodem(int tty, const void *_data, size_t size) +{ + const uint8_t *data = _data; + int rc, pnum, N, err; + + pnum = 1; + N = 0; + + kwboot_printv("Sending boot image...\n"); + + do { + struct kwboot_block block; + int n; + + n = kwboot_xm_makeblock(&block, + data + N, size - N, + pnum++); + if (n < 0) + goto can; + + if (!n) + break; + + rc = kwboot_xm_sendblock(tty, &block); + if (rc) + goto out; + + N += n; + kwboot_progress(N * 100 / size, '.'); + } while (1); + + rc = kwboot_tty_send_char(tty, EOT); + +out: + return rc; + +can: + err = errno; + kwboot_tty_send_char(tty, CAN); + errno = err; + goto out; +} + +static int +kwboot_term_pipe(int in, int out, char *quit, int *s) +{ + ssize_t nin, nout; + char _buf[128], *buf = _buf; + + nin = read(in, buf, sizeof(buf)); + if (nin < 0) + return -1; + + if (quit) { + int i; + + for (i = 0; i < nin; i++) { + if (*buf == quit[*s]) { + (*s)++; + if (!quit[*s]) + return 0; + buf++; + nin--; + } else + while (*s > 0) { + nout = write(out, quit, *s); + if (nout <= 0) + return -1; + (*s) -= nout; + } + } + } + + while (nin > 0) { + nout = write(out, buf, nin); + if (nout <= 0) + return -1; + nin -= nout; + } + + return 0; +} + +static int +kwboot_terminal(int tty) +{ + int rc, in, s; + char *quit = "\34c"; + struct termios otio, tio; + + rc = -1; + + in = STDIN_FILENO; + if (isatty(in)) { + rc = tcgetattr(in, &otio); + if (!rc) { + tio = otio; + cfmakeraw(&tio); + rc = tcsetattr(in, TCSANOW, &tio); + } + if (rc) { + perror("tcsetattr"); + goto out; + } + + kwboot_printv("[Type Ctrl-%c + %c to quit]\r\n", + quit[0]|0100, quit[1]); + } else + in = -1; + + rc = 0; + s = 0; + + do { + fd_set rfds; + int nfds = 0; + + FD_SET(tty, &rfds); + nfds = nfds < tty ? tty : nfds; + + if (in >= 0) { + FD_SET(in, &rfds); + nfds = nfds < in ? in : nfds; + } + + nfds = select(nfds + 1, &rfds, NULL, NULL, NULL); + if (nfds < 0) + break; + + if (FD_ISSET(tty, &rfds)) { + rc = kwboot_term_pipe(tty, STDOUT_FILENO, NULL, NULL); + if (rc) + break; + } + + if (FD_ISSET(in, &rfds)) { + rc = kwboot_term_pipe(in, tty, quit, &s); + if (rc) + break; + } + } while (quit[s] != 0); + + tcsetattr(in, TCSANOW, &otio); +out: + return rc; +} + +static void * +kwboot_mmap_image(const char *path, size_t *size, int prot) +{ + int rc, fd, flags; + struct stat st; + void *img; + + rc = -1; + fd = -1; + img = NULL; + + fd = open(path, O_RDONLY); + if (fd < 0) + goto out; + + rc = fstat(fd, &st); + if (rc) + goto out; + + flags = (prot & PROT_WRITE) ? MAP_PRIVATE : MAP_SHARED; + + img = mmap(NULL, st.st_size, prot, flags, fd, 0); + if (img == MAP_FAILED) { + img = NULL; + goto out; + } + + rc = 0; + *size = st.st_size; +out: + if (rc && img) { + munmap(img, st.st_size); + img = NULL; + } + if (fd >= 0) + close(fd); + + return img; +} + +static uint8_t +kwboot_img_csum8(void *_data, size_t size) +{ + uint8_t *data = _data, csum; + + for (csum = 0; size-- > 0; data++) + csum += *data; + + return csum; +} + +static int +kwboot_img_patch_hdr(void *img, size_t size) +{ + int rc; + bhr_t *hdr; + uint8_t csum; + const size_t hdrsz = sizeof(*hdr); + + rc = -1; + hdr = img; + + if (size < hdrsz) { + errno = EINVAL; + goto out; + } + + csum = kwboot_img_csum8(hdr, hdrsz) - hdr->checkSum; + if (csum != hdr->checkSum) { + errno = EINVAL; + goto out; + } + + if (hdr->blockid == IBR_HDR_UART_ID) { + rc = 0; + goto out; + } + + hdr->blockid = IBR_HDR_UART_ID; + + hdr->nandeccmode = IBR_HDR_ECC_DISABLED; + hdr->nandpagesize = 0; + + hdr->srcaddr = hdr->ext + ? sizeof(struct kwb_header) + : sizeof(*hdr); + + hdr->checkSum = kwboot_img_csum8(hdr, hdrsz) - csum; + + rc = 0; +out: + return rc; +} + +static void +kwboot_usage(FILE *stream, char *progname) +{ + fprintf(stream, + "Usage: %s -b <image> [ -p ] [ -t ] " + "[-B <baud> ] <TTY>\n", progname); + fprintf(stream, "\n"); + fprintf(stream, " -b <image>: boot <image>\n"); + fprintf(stream, " -p: patch <image> to type 0x69 (uart boot)\n"); + fprintf(stream, "\n"); + fprintf(stream, " -t: mini terminal\n"); + fprintf(stream, "\n"); + fprintf(stream, " -B <baud>: set baud rate\n"); + fprintf(stream, "\n"); +} + +int +main(int argc, char **argv) +{ + const char *ttypath, *imgpath; + int rv, rc, tty, term, prot, patch; + void *bootmsg; + void *img; + size_t size; + speed_t speed; + + rv = 1; + tty = -1; + bootmsg = NULL; + imgpath = NULL; + img = NULL; + term = 0; + patch = 0; + size = 0; + speed = B115200; + + kwboot_verbose = isatty(STDOUT_FILENO); + + do { + int c = getopt(argc, argv, "hb:ptB:"); + if (c < 0) + break; + + switch (c) { + case 'b': + bootmsg = kwboot_msg_boot; + imgpath = optarg; + break; + + case 'p': + patch = 1; + break; + + case 't': + term = 1; + break; + + case 'B': + speed = kwboot_tty_speed(atoi(optarg)); + if (speed == -1) + goto usage; + break; + + case 'h': + rv = 0; + default: + goto usage; + } + } while (1); + + if (!bootmsg && !term) + goto usage; + + if (patch && !imgpath) + goto usage; + + if (argc - optind < 1) + goto usage; + + ttypath = argv[optind++]; + + tty = kwboot_open_tty(ttypath, speed); + if (tty < 0) { + perror(ttypath); + goto out; + } + + if (imgpath) { + prot = PROT_READ | (patch ? PROT_WRITE : 0); + + img = kwboot_mmap_image(imgpath, &size, prot); + if (!img) { + perror(imgpath); + goto out; + } + } + + if (patch) { + rc = kwboot_img_patch_hdr(img, size); + if (rc) { + fprintf(stderr, "%s: Invalid image.\n", imgpath); + goto out; + } + } + + if (bootmsg) { + rc = kwboot_bootmsg(tty, bootmsg); + if (rc) { + perror("bootmsg"); + goto out; + } + } + + if (img) { + rc = kwboot_xmodem(tty, img, size); + if (rc) { + perror("xmodem"); + goto out; + } + } + + if (term) { + rc = kwboot_terminal(tty); + if (rc && !(errno == EINTR)) { + perror("terminal"); + goto out; + } + } + + rv = 0; +out: + if (tty >= 0) + close(tty); + + if (img) + munmap(img, size); + + return rv; + +usage: + kwboot_usage(rv ? stderr : stdout, basename(argv[0])); + goto out; +} diff --git a/tools/mingw_support.h b/tools/mingw_support.h index ee07290b5a..48b8010f0b 100644 --- a/tools/mingw_support.h +++ b/tools/mingw_support.h @@ -34,6 +34,14 @@ #define MAP_SHARED 0x01 /* Share changes */ #define MAP_PRIVATE 0x02 /* Changes are private */ +/* File perms */ +#ifndef S_IRGRP +# define S_IRGRP 0 +#endif +#ifndef S_IWGRP +# define S_IWGRP 0 +#endif + /* Windows 64-bit access macros */ #define LODWORD(x) ((DWORD)((DWORDLONG)(x))) #define HIDWORD(x) ((DWORD)(((DWORDLONG)(x) >> 32) & 0xffffffff)) diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index bfc4eb636b..55212687e1 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -35,6 +35,7 @@ #include <stdint.h> #include <string.h> #include <unistd.h> +#include <libgen.h> #include <sys/types.h> #include <sys/stat.h> #include <sys/mman.h> |
