diff options
36 files changed, 2709 insertions, 646 deletions
@@ -3100,6 +3100,9 @@ Low Level (hardware related) configuration options: parameters are extracted from datasheet and hard-coded into header files or board specific files. +- CONFIG_FSL_DDR_INTERACTIVE + Enable interactive DDR debugging. See doc/README.fsl-ddr. + - CONFIG_SYS_83XX_DDR_USES_CS0 Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h index 78b8976ca3..2295d0a460 100644 --- a/arch/microblaze/include/asm/processor.h +++ b/arch/microblaze/include/asm/processor.h @@ -1 +1,31 @@ -/* FIXME: Implement this! */ +/* + * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_MICROBLAZE_PROCESSOR_H +#define __ASM_MICROBLAZE_PROCESSOR_H + +/* References to section boundaries */ + +extern char __end[]; +extern char __text_start[]; + +#endif /* __ASM_MICROBLAZE_PROCESSOR_H */ diff --git a/arch/microblaze/include/asm/unaligned.h b/arch/microblaze/include/asm/unaligned.h index 785c2e9157..6cecbbb211 100644 --- a/arch/microblaze/include/asm/unaligned.h +++ b/arch/microblaze/include/asm/unaligned.h @@ -1,16 +1 @@ -#ifndef _ASM_MICROBLAZE_UNALIGNED_H -#define _ASM_MICROBLAZE_UNALIGNED_H - -#ifdef __KERNEL__ - -/* - * The Microblaze can do unaligned accesses itself in big endian mode. - */ -#include <linux/unaligned/access_ok.h> -#include <linux/unaligned/generic.h> - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif /* __KERNEL__ */ -#endif /* _ASM_MICROBLAZE_UNALIGNED_H */ +#include <asm-generic/unaligned.h> diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index d97543b2d8..ca5882dd0d 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -31,6 +31,7 @@ #include <watchdog.h> #include <stdio_dev.h> #include <net.h> +#include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -68,6 +69,7 @@ typedef int (init_fnc_t) (void); init_fnc_t *init_sequence[] = { env_init, serial_init, + console_init_f, #ifdef CONFIG_SYS_GPIO_0 gpio_init, #endif @@ -83,6 +85,8 @@ init_fnc_t *init_sequence[] = { NULL, }; +unsigned long monitor_flash_len; + void board_init (void) { bd_t *bd; @@ -104,6 +108,8 @@ void board_init (void) bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + monitor_flash_len = __end - __text_start; + /* * The Malloc area is immediately below the monitor copy in DRAM * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off @@ -160,6 +166,12 @@ void board_init (void) /* Initialize stdio devices */ stdio_init (); + /* Initialize the jump table for applications */ + jumptable_init(); + + /* Initialize the console (after the relocation and devices init) */ + console_init_r(); + if ((s = getenv ("loadaddr")) != NULL) { load_addr = simple_strtoul (s, NULL, 16); } @@ -174,6 +186,10 @@ void board_init (void) uchar enetaddr[6]; eth_getenv_enetaddr("ethaddr", enetaddr); printf("MAC: %pM\n", enetaddr); + + s = getenv("bootfile"); + if (s != NULL) + copy_filename(BootFile, s, sizeof(BootFile)); #endif /* main_loop */ diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c index 802202478a..0375df26f9 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc86xx/cpu_init.c @@ -35,7 +35,6 @@ #include <asm/mp.h> extern void srio_init(void); -void setup_bats(void); DECLARE_GLOBAL_DATA_PTR; @@ -91,33 +90,6 @@ int cpu_init_r(void) return 0; } -/* Set up BAT registers */ -void setup_bats(void) -{ -#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) - write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); -#endif -#if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) - write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); -#endif - write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); - write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); - write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); - write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); - write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); - write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); - write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); - write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); - write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); - write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); - write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); - write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); - write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); - write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); - - return; -} - #ifdef CONFIG_ADDR_MAP /* Initialize address mapping array */ void init_addr_map(void) diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S index 32896d49e1..ef80ecf6e5 100644 --- a/arch/powerpc/cpu/mpc86xx/start.S +++ b/arch/powerpc/cpu/mpc86xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007, 2011 Freescale Semiconductor. * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -322,6 +322,73 @@ invalidate_bats: sync blr +#define CONFIG_BAT_PAIR(n) \ + lis r4, CONFIG_SYS_IBAT##n##L@h; \ + ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \ + lis r3, CONFIG_SYS_IBAT##n##U@h; \ + ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \ + mtspr IBAT##n##L, r4; \ + mtspr IBAT##n##U, r3; \ + lis r4, CONFIG_SYS_DBAT##n##L@h; \ + ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \ + lis r3, CONFIG_SYS_DBAT##n##U@h; \ + ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \ + mtspr DBAT##n##L, r4; \ + mtspr DBAT##n##U, r3; + +/* + * setup_bats: + * + * Set up the final BAT registers now that setup is done. + * + * Assumes that: + * 1) Address translation is enabled upon entry + * 2) The boot rom is still accessible via 1:1 translation + */ + .globl setup_bats +setup_bats: + mflr r5 + sync + + /* + * When we disable address translation, we will get 1:1 (VA==PA) + * translation. The only place we know for sure is safe for that is + * the bootrom where we originally started out. Pop back into there. + */ + lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h + ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l + addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET + + /* disable address translation */ + mfmsr r3 + rlwinm r3, r3, 0, 28, 25 + mtspr SRR0, r4 + mtspr SRR1, r3 + rfi + +trans_disabled: +#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \ + && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) + CONFIG_BAT_PAIR(0) +#endif + CONFIG_BAT_PAIR(1) + CONFIG_BAT_PAIR(2) + CONFIG_BAT_PAIR(3) + CONFIG_BAT_PAIR(4) + CONFIG_BAT_PAIR(5) + CONFIG_BAT_PAIR(6) + CONFIG_BAT_PAIR(7) + + sync + isync + + /* Turn translation back on and return */ + mfmsr r3 + ori r3, r3, (MSR_IR | MSR_DR) + mtspr SPRN_SRR0,r5 + mtspr SPRN_SRR1,r3 + rfi + /* * early_bats: * diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile index d1b4c4b470..29523aa913 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2008 Freescale Semiconductor, Inc. +# Copyright 2008-2011 Freescale Semiconductor, Inc. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License @@ -30,6 +30,7 @@ COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o endif +COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index f59aa33b22..c8b0f91676 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -56,32 +56,46 @@ typedef struct { #define STEP_PROGRAM_REGS (1 << 6) #define STEP_ALL 0xFFF -extern unsigned long long +unsigned long long fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only); -extern const char * step_to_string(unsigned int step); +const char *step_to_string(unsigned int step); -extern unsigned int -compute_fsl_memctl_config_regs(const memctl_options_t *popts, +unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, unsigned int dbw_capacity_adjust, unsigned int size_only); -extern unsigned int -compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms); -extern unsigned int populate_memctl_options(int all_DIMMs_registered, +unsigned int compute_lowest_common_dimm_parameters( + const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms); +unsigned int populate_memctl_options(int all_DIMMs_registered, memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num); -extern void check_interleaving_options(fsl_ddr_info_t *pinfo); +void check_interleaving_options(fsl_ddr_info_t *pinfo); -extern unsigned int mclk_to_picos(unsigned int mclk); -extern unsigned int get_memory_clk_period_ps(void); -extern unsigned int picos_to_mclk(unsigned int picos); +unsigned int mclk_to_picos(unsigned int mclk); +unsigned int get_memory_clk_period_ps(void); +unsigned int picos_to_mclk(unsigned int picos); +void fsl_ddr_set_lawbar( + const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); + +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo); +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); + +/* processor specific function */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num); /* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c new file mode 100644 index 0000000000..d7d66ef491 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -0,0 +1,1691 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or any later versionas published by the Free Software Foundation. + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + * York Sun [at freescale.com] + */ + +#include <common.h> +#include <linux/ctype.h> +#include <asm/types.h> + +#include <asm/fsl_ddr_sdram.h> +#include "ddr.h" + +/* Option parameter Structures */ +struct options_string { + const char *option_name; + size_t offset; + unsigned int size; + const char printhex; +}; + +static unsigned int picos_to_mhz(unsigned int picos) +{ + return 1000000 / picos; +} + +static void print_option_table(const struct options_string *table, + int table_size, + const void *base) +{ + unsigned int i; + unsigned int *ptr; + unsigned long long *ptr_l; + + for (i = 0; i < table_size; i++) { + switch (table[i].size) { + case 4: + ptr = (unsigned int *) (base + table[i].offset); + if (table[i].printhex) { + printf("%s = 0x%08X\n", + table[i].option_name, *ptr); + } else { + printf("%s = %u\n", + table[i].option_name, *ptr); + } + break; + case 8: + ptr_l = (unsigned long long *) (base + table[i].offset); + printf("%s = %llu\n", + table[i].option_name, *ptr_l); + break; + default: + printf("Unrecognized size!\n"); + break; + } + } +} + +static int handle_option_table(const struct options_string *table, + int table_size, + void *base, + const char *opt, + const char *val) +{ + unsigned int i; + unsigned int value, *ptr; + unsigned long long value_l, *ptr_l; + + for (i = 0; i < table_size; i++) { + if (strcmp(table[i].option_name, opt) != 0) + continue; + switch (table[i].size) { + case 4: + value = simple_strtoul(val, NULL, 0); + ptr = base + table[i].offset; + *ptr = value; + break; + case 8: + value_l = simple_strtoull(val, NULL, 0); + ptr_l = base + table[i].offset; + *ptr_l = value_l; + break; + default: + printf("Unrecognized size!\n"); + break; + } + return 1; + } + + return 0; +} + +static void fsl_ddr_generic_edit(void *pdata, + void *pend, + unsigned int element_size, + unsigned int element_num, + unsigned int value) +{ + char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */ + + pcdata += element_num * element_size; + if ((pcdata + element_size) > (char *) pend) { + printf("trying to write past end of data\n"); + return; + } + + switch (element_size) { + case 1: + __raw_writeb(value, pcdata); + break; + case 2: + __raw_writew(value, pcdata); + break; + case 4: + __raw_writel(value, pcdata); + break; + default: + printf("unexpected element size %u\n", element_size); + break; + } +} + +static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + unsigned int dimm_num, + unsigned int element_num, + unsigned int value) +{ + generic_spd_eeprom_t *pspd; + + pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); + fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value); +} + +#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \ + sizeof((common_timing_params_t *)0)->x, 0} + +static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + const char *optname_str, + const char *value_str) +{ + common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; + + static const struct options_string options[] = { + COMMON_TIMING(tCKmin_X_ps), + COMMON_TIMING(tCKmax_ps), + COMMON_TIMING(tCKmax_max_ps), + COMMON_TIMING(tRCD_ps), + COMMON_TIMING(tRP_ps), + COMMON_TIMING(tRAS_ps), + COMMON_TIMING(tWR_ps), + COMMON_TIMING(tWTR_ps), + COMMON_TIMING(tRFC_ps), + COMMON_TIMING(tRRD_ps), + COMMON_TIMING(tRC_ps), + COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(tIS_ps), + COMMON_TIMING(tIH_ps), + COMMON_TIMING(tDS_ps), + COMMON_TIMING(tDH_ps), + COMMON_TIMING(tRTP_ps), + COMMON_TIMING(tDQSQ_max_ps), + COMMON_TIMING(tQHS_ps), + COMMON_TIMING(ndimms_present), + COMMON_TIMING(lowest_common_SPD_caslat), + COMMON_TIMING(highest_common_derated_caslat), + COMMON_TIMING(additive_latency), + COMMON_TIMING(all_DIMMs_burst_lengths_bitmask), + COMMON_TIMING(all_DIMMs_registered), + COMMON_TIMING(all_DIMMs_unbuffered), + COMMON_TIMING(all_DIMMs_ECC_capable), + COMMON_TIMING(total_mem), + COMMON_TIMING(base_address), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, optname_str, value_str)) + return; + + printf("Error: couldn't find option string %s\n", optname_str); +} + +#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ + sizeof((dimm_params_t *)0)->x, 0} + +static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + unsigned int dimm_num, + const char *optname_str, + const char *value_str) +{ + dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); + + static const struct options_string options[] = { + DIMM_PARM(n_ranks), + DIMM_PARM(data_width), + DIMM_PARM(primary_sdram_width), + DIMM_PARM(ec_sdram_width), + DIMM_PARM(registered_dimm), + + DIMM_PARM(n_row_addr), + DIMM_PARM(n_col_addr), + DIMM_PARM(edc_config), + DIMM_PARM(n_banks_per_sdram_device), + DIMM_PARM(burst_lengths_bitmask), + DIMM_PARM(row_density), + + DIMM_PARM(tCKmin_X_ps), + DIMM_PARM(tCKmin_X_minus_1_ps), + DIMM_PARM(tCKmin_X_minus_2_ps), + DIMM_PARM(tCKmax_ps), + + DIMM_PARM(caslat_X), + DIMM_PARM(caslat_X_minus_1), + DIMM_PARM(caslat_X_minus_2), + + DIMM_PARM(caslat_lowest_derated), + + DIMM_PARM(tRCD_ps), + DIMM_PARM(tRP_ps), + DIMM_PARM(tRAS_ps), + DIMM_PARM(tWR_ps), + DIMM_PARM(tWTR_ps), + DIMM_PARM(tRFC_ps), + DIMM_PARM(tRRD_ps), + DIMM_PARM(tRC_ps), + DIMM_PARM(refresh_rate_ps), + + DIMM_PARM(tIS_ps), + DIMM_PARM(tIH_ps), + DIMM_PARM(tDS_ps), + DIMM_PARM(tDH_ps), + DIMM_PARM(tRTP_ps), + DIMM_PARM(tDQSQ_max_ps), + DIMM_PARM(tQHS_ps), + + DIMM_PARM(rank_density), + DIMM_PARM(capacity), + DIMM_PARM(base_address), + }; + + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, optname_str, value_str)) + return; + + printf("couldn't find option string %s\n", optname_str); +} + +static void print_dimm_parameters(const dimm_params_t *pdimm) +{ + static const struct options_string options[] = { + DIMM_PARM(n_ranks), + DIMM_PARM(data_width), + DIMM_PARM(primary_sdram_width), + DIMM_PARM(ec_sdram_width), + DIMM_PARM(registered_dimm), + + DIMM_PARM(n_row_addr), + DIMM_PARM(n_col_addr), + DIMM_PARM(edc_config), + DIMM_PARM(n_banks_per_sdram_device), + + DIMM_PARM(tCKmin_X_ps), + DIMM_PARM(tCKmin_X_minus_1_ps), + DIMM_PARM(tCKmin_X_minus_2_ps), + DIMM_PARM(tCKmax_ps), + + DIMM_PARM(caslat_X), + DIMM_PARM(tAA_ps), + DIMM_PARM(caslat_X_minus_1), + DIMM_PARM(caslat_X_minus_2), + DIMM_PARM(caslat_lowest_derated), + + DIMM_PARM(tRCD_ps), + DIMM_PARM(tRP_ps), + DIMM_PARM(tRAS_ps), + DIMM_PARM(tWR_ps), + DIMM_PARM(tWTR_ps), + DIMM_PARM(tRFC_ps), + DIMM_PARM(tRRD_ps), + DIMM_PARM(tRC_ps), + DIMM_PARM(refresh_rate_ps), + + DIMM_PARM(tIS_ps), + DIMM_PARM(tIH_ps), + DIMM_PARM(tDS_ps), + DIMM_PARM(tDH_ps), + DIMM_PARM(tRTP_ps), + DIMM_PARM(tDQSQ_max_ps), + DIMM_PARM(tQHS_ps), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (pdimm->n_ranks == 0) { + printf("DIMM not present\n"); + return; + } + printf("DIMM organization parameters:\n"); + printf("module part name = %s\n", pdimm->mpart); + printf("rank_density = %llu bytes (%llu megabytes)\n", + pdimm->rank_density, pdimm->rank_density / 0x100000); + printf("capacity = %llu bytes (%llu megabytes)\n", + pdimm->capacity, pdimm->capacity / 0x100000); + printf("burst_lengths_bitmask = %02X\n", + pdimm->burst_lengths_bitmask); + printf("base_addresss = %llu (%08llX %08llX)\n", + pdimm->base_address, + (pdimm->base_address >> 32), + pdimm->base_address & 0xFFFFFFFF); + print_option_table(options, n_opts, pdimm); +} + +static void print_lowest_common_dimm_parameters( + const common_timing_params_t *plcd_dimm_params) +{ + static const struct options_string options[] = { + COMMON_TIMING(tCKmax_max_ps), + COMMON_TIMING(tRCD_ps), + COMMON_TIMING(tRP_ps), + COMMON_TIMING(tRAS_ps), + COMMON_TIMING(tWR_ps), + COMMON_TIMING(tWTR_ps), + COMMON_TIMING(tRFC_ps), + COMMON_TIMING(tRRD_ps), + COMMON_TIMING(tRC_ps), + COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(tIS_ps), + COMMON_TIMING(tDS_ps), + COMMON_TIMING(tDH_ps), + COMMON_TIMING(tRTP_ps), + COMMON_TIMING(tDQSQ_max_ps), + COMMON_TIMING(tQHS_ps), + COMMON_TIMING(lowest_common_SPD_caslat), + COMMON_TIMING(highest_common_derated_caslat), + COMMON_TIMING(additive_latency), + COMMON_TIMING(ndimms_present), + COMMON_TIMING(all_DIMMs_registered), + COMMON_TIMING(all_DIMMs_unbuffered), + COMMON_TIMING(all_DIMMs_ECC_capable), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + /* Clock frequencies */ + printf("tCKmin_X_ps = %u (%u MHz)\n", + plcd_dimm_params->tCKmin_X_ps, + picos_to_mhz(plcd_dimm_params->tCKmin_X_ps)); + printf("tCKmax_ps = %u (%u MHz)\n", + plcd_dimm_params->tCKmax_ps, + picos_to_mhz(plcd_dimm_params->tCKmax_ps)); + printf("all_DIMMs_burst_lengths_bitmask = %02X\n", + plcd_dimm_params->all_DIMMs_burst_lengths_bitmask); + + print_option_table(options, n_opts, plcd_dimm_params); + + printf("total_mem = %llu (%llu megabytes)\n", + plcd_dimm_params->total_mem, + plcd_dimm_params->total_mem / 0x100000); + printf("base_address = %llu (%llu megabytes)\n", + plcd_dimm_params->base_address, + plcd_dimm_params->base_address / 0x100000); +} + +#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \ + sizeof((memctl_options_t *)0)->x, 0} +#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \ + offsetof(memctl_options_t, cs_local_opts[x].y), \ + sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0} + +static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, + unsigned int ctl_num, + const char *optname_str, + const char *value_str) +{ + memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); + /* + * This array all on the stack and *computed* each time this + * function is rung. + */ + static const struct options_string options[] = { + CTRL_OPTIONS_CS(0, odt_rd_cfg), + CTRL_OPTIONS_CS(0, odt_wr_cfg), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rd_cfg), + CTRL_OPTIONS_CS(1, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rd_cfg), + CTRL_OPTIONS_CS(2, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(3, odt_rd_cfg), + CTRL_OPTIONS_CS(3, odt_wr_cfg), +#endif +#if defined(CONFIG_FSL_DDR3) + CTRL_OPTIONS_CS(0, odt_rtt_norm), + CTRL_OPTIONS_CS(0, odt_rtt_wr), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rtt_norm), + CTRL_OPTIONS_CS(1, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rtt_norm), + CTRL_OPTIONS_CS(2, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(3, odt_rtt_norm), + CTRL_OPTIONS_CS(3, odt_rtt_wr), +#endif +#endif + CTRL_OPTIONS(memctl_interleaving), + CTRL_OPTIONS(memctl_interleaving_mode), + CTRL_OPTIONS(ba_intlv_ctl), + CTRL_OPTIONS(ECC_mode), + CTRL_OPTIONS(ECC_init_using_memctl), + CTRL_OPTIONS(DQS_config), + CTRL_OPTIONS(self_refresh_in_sleep), + CTRL_OPTIONS(dynamic_power), + CTRL_OPTIONS(data_bus_width), + CTRL_OPTIONS(burst_length), + CTRL_OPTIONS(cas_latency_override), + CTRL_OPTIONS(cas_latency_override_value), + CTRL_OPTIONS(use_derated_caslat), + CTRL_OPTIONS(additive_latency_override), + CTRL_OPTIONS(additive_latency_override_value), + CTRL_OPTIONS(clk_adjust), + CTRL_OPTIONS(cpo_override), + CTRL_OPTIONS(write_data_delay), + CTRL_OPTIONS(half_strength_driver_enable), + + /* + * These can probably be changed to 2T_EN and 3T_EN + * (using a leading numerical character) without problem + */ + CTRL_OPTIONS(twoT_en), + CTRL_OPTIONS(threeT_en), + CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(bstopre), + CTRL_OPTIONS(wrlvl_override), + CTRL_OPTIONS(wrlvl_sample), + CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(rcw_override), + CTRL_OPTIONS(rcw_1), + CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS(tCKE_clock_pulse_width_ps), + CTRL_OPTIONS(tFAW_window_four_activates_ps), + CTRL_OPTIONS(trwt_override), + CTRL_OPTIONS(trwt), + }; + + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, + optname_str, value_str)) + return; + + printf("couldn't find option string %s\n", optname_str); +} + +#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \ + sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1} +#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \ + offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \ + sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1} + +static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int i; + static const struct options_string options[] = { + CFG_REGS_CS(0, bnds), + CFG_REGS_CS(0, config), + CFG_REGS_CS(0, config_2), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CFG_REGS_CS(1, bnds), + CFG_REGS_CS(1, config), + CFG_REGS_CS(1, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(2, bnds), + CFG_REGS_CS(2, config), + CFG_REGS_CS(2, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(3, bnds), + CFG_REGS_CS(3, config), + CFG_REGS_CS(3, config_2), +#endif + CFG_REGS(timing_cfg_3), + CFG_REGS(timing_cfg_0), + CFG_REGS(timing_cfg_1), + CFG_REGS(timing_cfg_2), + CFG_REGS(ddr_sdram_cfg), + CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_mode), + CFG_REGS(ddr_sdram_mode_2), + CFG_REGS(ddr_sdram_mode_3), + CFG_REGS(ddr_sdram_mode_4), + CFG_REGS(ddr_sdram_mode_5), + CFG_REGS(ddr_sdram_mode_6), + CFG_REGS(ddr_sdram_mode_7), + CFG_REGS(ddr_sdram_mode_8), + CFG_REGS(ddr_sdram_interval), + CFG_REGS(ddr_data_init), + CFG_REGS(ddr_sdram_clk_cntl), + CFG_REGS(ddr_init_addr), + CFG_REGS(ddr_init_ext_addr), + CFG_REGS(timing_cfg_4), + CFG_REGS(timing_cfg_5), + CFG_REGS(ddr_zq_cntl), + CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_sr_cntr), + CFG_REGS(ddr_sdram_rcw_1), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_cdr1), + CFG_REGS(ddr_cdr2), + CFG_REGS(err_disable), + CFG_REGS(err_int_en), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + print_option_table(options, n_opts, ddr); + + for (i = 0; i < 32; i++) + printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); +} + +static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + const char *regname, + const char *value_str) +{ + unsigned int i; + fsl_ddr_cfg_regs_t *ddr; + char buf[20]; + static const struct options_string options[] = { + CFG_REGS_CS(0, bnds), + CFG_REGS_CS(0, config), + CFG_REGS_CS(0, config_2), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CFG_REGS_CS(1, bnds), + CFG_REGS_CS(1, config), + CFG_REGS_CS(1, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(2, bnds), + CFG_REGS_CS(2, config), + CFG_REGS_CS(2, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CFG_REGS_CS(3, bnds), + CFG_REGS_CS(3, config), + CFG_REGS_CS(3, config_2), +#endif + CFG_REGS(timing_cfg_3), + CFG_REGS(timing_cfg_0), + CFG_REGS(timing_cfg_1), + CFG_REGS(timing_cfg_2), + CFG_REGS(ddr_sdram_cfg), + CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_mode), + CFG_REGS(ddr_sdram_mode_2), + CFG_REGS(ddr_sdram_mode_3), + CFG_REGS(ddr_sdram_mode_4), + CFG_REGS(ddr_sdram_mode_5), + CFG_REGS(ddr_sdram_mode_6), + CFG_REGS(ddr_sdram_mode_7), + CFG_REGS(ddr_sdram_mode_8), + CFG_REGS(ddr_sdram_interval), + CFG_REGS(ddr_data_init), + CFG_REGS(ddr_sdram_clk_cntl), + CFG_REGS(ddr_init_addr), + CFG_REGS(ddr_init_ext_addr), + CFG_REGS(timing_cfg_4), + CFG_REGS(timing_cfg_5), + CFG_REGS(ddr_zq_cntl), + CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_sr_cntr), + CFG_REGS(ddr_sdram_rcw_1), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_cdr1), + CFG_REGS(ddr_cdr2), + CFG_REGS(err_disable), + CFG_REGS(err_int_en), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_sdram_rcw_2), + + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + debug("fsl_ddr_regs_edit: ctrl_num = %u, " + "regname = %s, value = %s\n", + ctrl_num, regname, value_str); + if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS) + return; + + ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); + + if (handle_option_table(options, n_opts, ddr, regname, value_str)) + return; + + for (i = 0; i < 32; i++) { + unsigned int value = simple_strtoul(value_str, NULL, 0); + sprintf(buf, "debug_%u", i + 1); + if (strcmp(buf, regname) == 0) { + ddr->debug[i] = value; + return; + } + } + printf("Error: couldn't find register string %s\n", regname); +} + +#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \ + sizeof((memctl_options_t *)0)->x, 1} + +static void print_memctl_options(const memctl_options_t *popts) +{ + static const struct options_string options[] = { + CTRL_OPTIONS_CS(0, odt_rd_cfg), + CTRL_OPTIONS_CS(0, odt_wr_cfg), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rd_cfg), + CTRL_OPTIONS_CS(1, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rd_cfg), + CTRL_OPTIONS_CS(2, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CTRL_OPTIONS_CS(3, odt_rd_cfg), + CTRL_OPTIONS_CS(3, odt_wr_cfg), +#endif +#if defined(CONFIG_FSL_DDR3) + CTRL_OPTIONS_CS(0, odt_rtt_norm), + CTRL_OPTIONS_CS(0, odt_rtt_wr), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rtt_norm), + CTRL_OPTIONS_CS(1, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rtt_norm), + CTRL_OPTIONS_CS(2, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CTRL_OPTIONS_CS(3, odt_rtt_norm), + CTRL_OPTIONS_CS(3, odt_rtt_wr), +#endif +#endif + CTRL_OPTIONS(memctl_interleaving), + CTRL_OPTIONS(memctl_interleaving_mode), + CTRL_OPTIONS_HEX(ba_intlv_ctl), + CTRL_OPTIONS(ECC_mode), + CTRL_OPTIONS(ECC_init_using_memctl), + CTRL_OPTIONS(DQS_config), + CTRL_OPTIONS(self_refresh_in_sleep), + CTRL_OPTIONS(dynamic_power), + CTRL_OPTIONS(data_bus_width), + CTRL_OPTIONS(burst_length), + CTRL_OPTIONS(cas_latency_override), + CTRL_OPTIONS(cas_latency_override_value), + CTRL_OPTIONS(use_derated_caslat), + CTRL_OPTIONS(additive_latency_override), + CTRL_OPTIONS(additive_latency_override_value), + CTRL_OPTIONS(clk_adjust), + CTRL_OPTIONS(cpo_override), + CTRL_OPTIONS(write_data_delay), + CTRL_OPTIONS(half_strength_driver_enable), + /* + * These can probably be changed to 2T_EN and 3T_EN + * (using a leading numerical character) without problem + */ + CTRL_OPTIONS(twoT_en), + CTRL_OPTIONS(threeT_en), + CTRL_OPTIONS(registered_dimm_en), + CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(bstopre), + CTRL_OPTIONS(wrlvl_override), + CTRL_OPTIONS(wrlvl_sample), + CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(rcw_override), + CTRL_OPTIONS(rcw_1), + CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS(tCKE_clock_pulse_width_ps), + CTRL_OPTIONS(tFAW_window_four_activates_ps), + CTRL_OPTIONS(trwt_override), + CTRL_OPTIONS(trwt), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + print_option_table(options, n_opts, popts); +} + +#ifdef CONFIG_FSL_DDR1 +void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", 5, spd->nrows, + " spd->nrows * 5 # of DIMM Banks *"); + printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, + " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); + printf("%-3d : %02x %s\n", 7, spd->dataw_msb, + " spd->dataw_msb, * 7 Data Width msb of this assembly *"); + printf("%-3d : %02x %s\n", 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", 15, spd->min_delay, + " spd->min_delay, * 15 Back to Back Random Access *"); + printf("%-3d : %02x %s\n", 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", 19, spd->cs_lat, + " spd->cs_lat, * 19 Chip Select Latency *"); + printf("%-3d : %02x %s\n", 20, spd->write_lat, + " spd->write_lat, * 20 Write Latency/Recovery *"); + printf("%-3d : %02x %s\n", 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", 31, spd->bank_dens, + " spd->bank_dens, * 31 Density of each bank on module *"); + printf("%-3d : %02x %s\n", 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], + " spd->res_36_40[0], * 36 Reserved / tWR *"); + printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], + " spd->res_36_40[1], * 37 Reserved / tWTR *"); + printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], + " spd->res_36_40[2], * 38 Reserved / tRTP *"); + printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], + " spd->res_36_40[3], * 39 Reserved / mem_probe *"); + printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], + " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); + printf("%-3d : %02x %s\n", 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", 46, spd->res_46, + " spd->res_46, * 46 Reserved/ PLL Relock time *"); + printf("%-3d : %02x %s\n", 47, spd->dimm_height, + " spd->dimm_height * 47 SDRAM DIMM Height *"); + + printf("%-3d-%3d: ", 48, 61); + + for (i = 0; i < 14; i++) + printf("%02x", spd->res_48_61[i]); + + printf(" * 48-61 IDD in SPD and Reserved space *\n"); + + printf("%-3d : %02x %s\n", 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) + printf("%02x", spd->mid[i]); + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + printf("%-3d : %02x %s\n", 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + + for (i = 0; i < 18; i++) + printf("%c", spd->mpart[i]); + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) + printf("%02x", spd->sernum[i]); + + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + + for (i = 0; i < 27; i++) + printf("%02x", spd->mspec[i]); + + printf("* 99 Manufacturer Specific Data *\n"); +} +#endif + +#ifdef CONFIG_FSL_DDR2 +void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", 5, spd->mod_ranks, + " spd->mod_ranks * 5 # of Module Rows on this assembly *"); + printf("%-3d : %02x %s\n", 6, spd->dataw, + " spd->dataw, * 6 Data Width of this assembly *"); + printf("%-3d : %02x %s\n", 7, spd->res_7, + " spd->res_7, * 7 Reserved *"); + printf("%-3d : %02x %s\n", 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", 15, spd->res_15, + " spd->res_15, * 15 Reserved *"); + printf("%-3d : %02x %s\n", 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", 19, spd->mech_char, + " spd->mech_char, * 19 Mechanical Characteristics *"); + printf("%-3d : %02x %s\n", 20, spd->dimm_type, + " spd->dimm_type, * 20 DIMM type *"); + printf("%-3d : %02x %s\n", 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", 31, spd->rank_dens, + " spd->rank_dens, * 31 Density of each rank on module *"); + printf("%-3d : %02x %s\n", 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", 36, spd->twr, + " spd->twr, * 36 Write Recovery time tWR *"); + printf("%-3d : %02x %s\n", 37, spd->twtr, + " spd->twtr, * 37 Int write to read delay tWTR *"); + printf("%-3d : %02x %s\n", 38, spd->trtp, + " spd->trtp, * 38 Int read to precharge delay tRTP *"); + printf("%-3d : %02x %s\n", 39, spd->mem_probe, + " spd->mem_probe, * 39 Mem analysis probe characteristics *"); + printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, + " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); + printf("%-3d : %02x %s\n", 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", 46, spd->pll_relock, + " spd->pll_relock, * 46 PLL Relock time *"); + printf("%-3d : %02x %s\n", 47, spd->Tcasemax, + " spd->Tcasemax, * 47 Tcasemax *"); + printf("%-3d : %02x %s\n", 48, spd->psiTAdram, + " spd->psiTAdram, * 48 Thermal Resistance of DRAM Package " + "from Top (Case) to Ambient (Psi T-A DRAM) *"); + printf("%-3d : %02x %s\n", 49, spd->dt0_mode, + " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " + "Ambient due to Activate-Precharge/Mode Bits " + "(DT0/Mode Bits) *)"); + printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, + " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " + "Ambient due to Precharge/Quiet Standby " + "(DT2N/DT2Q) *"); + printf("%-3d : %02x %s\n", 51, spd->dt2p, + " spd->dt2p, * 51 DRAM Case Temperature Rise from " + "Ambient due to Precharge Power-Down (DT2P) *"); + printf("%-3d : %02x %s\n", 52, spd->dt3n, + " spd->dt3n, * 52 DRAM Case Temperature Rise from " + "Ambient due to Active Standby (DT3N) *"); + printf("%-3d : %02x %s\n", 53, spd->dt3pfast, + " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " + "Ambient due to Active Power-Down with Fast PDN Exit " + "(DT3Pfast) *"); + printf("%-3d : %02x %s\n", 54, spd->dt3pslow, + " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " + "Ambient due to Active Power-Down with Slow PDN Exit " + "(DT3Pslow) *"); + printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, + " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " + "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " + "(DT4R/DT4R4W Mode Bit) *"); + printf("%-3d : %02x %s\n", 56, spd->dt5b, + " spd->dt5b, * 56 DRAM Case Temperature Rise from " + "Ambient due to Burst Refresh (DT5B) *"); + printf("%-3d : %02x %s\n", 57, spd->dt7, + " spd->dt7, * 57 DRAM Case Temperature Rise from " + "Ambient due to Bank Interleave Reads with " + "Auto-Precharge (DT7) *"); + printf("%-3d : %02x %s\n", 58, spd->psiTApll, + " spd->psiTApll, * 58 Thermal Resistance of PLL Package form" + " Top (Case) to Ambient (Psi T-A PLL) *"); + printf("%-3d : %02x %s\n", 59, spd->psiTAreg, + " spd->psiTAreg, * 59 Thermal Reisitance of Register Package" + " from Top (Case) to Ambient (Psi T-A Register) *"); + printf("%-3d : %02x %s\n", 60, spd->dtpllactive, + " spd->dtpllactive, * 60 PLL Case Temperature Rise from " + "Ambient due to PLL Active (DT PLL Active) *"); + printf("%-3d : %02x %s\n", 61, spd->dtregact, + " spd->dtregact, " + "* 61 Register Case Temperature Rise from Ambient due to " + "Register Active/Mode Bit (DT Register Active/Mode Bit) *"); + printf("%-3d : %02x %s\n", 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) + printf("%02x", spd->mid[i]); + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + + printf("%-3d : %02x %s\n", 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + for (i = 0; i < 18; i++) + printf("%c", spd->mpart[i]); + + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) + printf("%02x", spd->sernum[i]); + + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + for (i = 0; i < 27; i++) + printf("%02x", spd->mspec[i]); + + + printf("* 99 Manufacturer Specific Data *\n"); +} +#endif + +#ifdef CONFIG_FSL_DDR3 +void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) +{ + unsigned int i; + + /* General Section: Bytes 0-59 */ + +#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, y); +#define PRINT_NNXXS(n0, n1, x0, x1, s) \ + printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); + + PRINT_NXS(0, spd->info_size_crc, + "info_size_crc bytes written into serial memory, " + "CRC coverage"); + PRINT_NXS(1, spd->spd_rev, + "spd_rev SPD Revision"); + PRINT_NXS(2, spd->mem_type, + "mem_type Key Byte / DRAM Device Type"); + PRINT_NXS(3, spd->module_type, + "module_type Key Byte / Module Type"); + PRINT_NXS(4, spd->density_banks, + "density_banks SDRAM Density and Banks"); + PRINT_NXS(5, spd->addressing, + "addressing SDRAM Addressing"); + PRINT_NXS(6, spd->module_vdd, + "module_vdd Module Nominal Voltage, VDD"); + PRINT_NXS(7, spd->organization, + "organization Module Organization"); + PRINT_NXS(8, spd->bus_width, + "bus_width Module Memory Bus Width"); + PRINT_NXS(9, spd->ftb_div, + "ftb_div Fine Timebase (FTB) Dividend / Divisor"); + PRINT_NXS(10, spd->mtb_dividend, + "mtb_dividend Medium Timebase (MTB) Dividend"); + PRINT_NXS(11, spd->mtb_divisor, + "mtb_divisor Medium Timebase (MTB) Divisor"); + PRINT_NXS(12, spd->tCK_min, + "tCK_min SDRAM Minimum Cycle Time"); + PRINT_NXS(13, spd->res_13, + "res_13 Reserved"); + PRINT_NXS(14, spd->caslat_lsb, + "caslat_lsb CAS Latencies Supported, LSB"); + PRINT_NXS(15, spd->caslat_msb, + "caslat_msb CAS Latencies Supported, MSB"); + PRINT_NXS(16, spd->tAA_min, + "tAA_min Min CAS Latency Time"); + PRINT_NXS(17, spd->tWR_min, + "tWR_min Min Write REcovery Time"); + PRINT_NXS(18, spd->tRCD_min, + "tRCD_min Min RAS# to CAS# Delay Time"); + PRINT_NXS(19, spd->tRRD_min, + "tRRD_min Min Row Active to Row Active Delay Time"); + PRINT_NXS(20, spd->tRP_min, + "tRP_min Min Row Precharge Delay Time"); + PRINT_NXS(21, spd->tRAS_tRC_ext, + "tRAS_tRC_ext Upper Nibbles for tRAS and tRC"); + PRINT_NXS(22, spd->tRAS_min_lsb, + "tRAS_min_lsb Min Active to Precharge Delay Time, LSB"); + PRINT_NXS(23, spd->tRC_min_lsb, + "tRC_min_lsb Min Active to Active/Refresh Delay Time, LSB"); + PRINT_NXS(24, spd->tRFC_min_lsb, + "tRFC_min_lsb Min Refresh Recovery Delay Time LSB"); + PRINT_NXS(25, spd->tRFC_min_msb, + "tRFC_min_msb Min Refresh Recovery Delay Time MSB"); + PRINT_NXS(26, spd->tWTR_min, + "tWTR_min Min Internal Write to Read Command Delay Time"); + PRINT_NXS(27, spd->tRTP_min, + "tRTP_min " + "Min Internal Read to Precharge Command Delay Time"); + PRINT_NXS(28, spd->tFAW_msb, + "tFAW_msb Upper Nibble for tFAW"); + PRINT_NXS(29, spd->tFAW_min, + "tFAW_min Min Four Activate Window Delay Time"); + PRINT_NXS(30, spd->opt_features, + "opt_features SDRAM Optional Features"); + PRINT_NXS(31, spd->therm_ref_opt, + "therm_ref_opt SDRAM Thermal and Refresh Opts"); + PRINT_NXS(32, spd->therm_sensor, + "therm_sensor SDRAM Thermal Sensor"); + PRINT_NXS(33, spd->device_type, + "device_type SDRAM Device Type"); + + printf("%-3d-%3d: ", 34, 59); /* Reserved, General Section */ + + for (i = 34; i <= 59; i++) + printf("%02x ", spd->res_34_59[i - 34]); + + puts("\n"); + + switch (spd->module_type) { + case 0x02: /* UDIMM */ + case 0x03: /* SO-DIMM */ + case 0x04: /* Micro-DIMM */ + case 0x06: /* Mini-UDIMM */ + PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, + "mod_height (Unbuffered) Module Nominal Height"); + PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, + "mod_thickness (Unbuffered) Module Maximum Thickness"); + PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, + "ref_raw_card (Unbuffered) Reference Raw Card Used"); + PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, + "addr_mapping (Unbuffered) Address mapping from " + "Edge Connector to DRAM"); + break; + case 0x01: /* RDIMM */ + case 0x05: /* Mini-RDIMM */ + PRINT_NXS(60, spd->mod_section.registered.mod_height, + "mod_height (Registered) Module Nominal Height"); + PRINT_NXS(61, spd->mod_section.registered.mod_thickness, + "mod_thickness (Registered) Module Maximum Thickness"); + PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, + "ref_raw_card (Registered) Reference Raw Card Used"); + PRINT_NXS(63, spd->mod_section.registered.modu_attr, + "modu_attr (Registered) DIMM Module Attributes"); + PRINT_NXS(64, spd->mod_section.registered.thermal, + "thermal (Registered) Thermal Heat " + "Spreader Solution"); + PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, + "reg_id_lo (Registered) Register Manufacturer ID " + "Code, LSB"); + PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, + "reg_id_hi (Registered) Register Manufacturer ID " + "Code, MSB"); + PRINT_NXS(67, spd->mod_section.registered.reg_rev, + "reg_rev (Registered) Register " + "Revision Number"); + PRINT_NXS(68, spd->mod_section.registered.reg_type, + "reg_type (Registered) Register Type"); + for (i = 69; i <= 76; i++) { + printf("%-3d : %02x rcw[%d]\n", i, + spd->mod_section.registered.rcw[i-69], i-69); + } + break; + default: + /* Module-specific Section, Unsupported Module Type */ + printf("%-3d-%3d: ", 60, 116); + + for (i = 60; i <= 116; i++) + printf("%02x", spd->mod_section.uc[i - 60]); + + break; + } + + /* Unique Module ID: Bytes 117-125 */ + PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); + PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); + PRINT_NXS(119, spd->mloc, "Mfg Location"); + PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); + + printf("%-3d-%3d: ", 122, 125); + + for (i = 122; i <= 125; i++) + printf("%02x ", spd->sernum[i - 122]); + printf(" Module Serial Number\n"); + + /* CRC: Bytes 126-127 */ + PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); + + /* Other Manufacturer Fields and User Space: Bytes 128-255 */ + printf("%-3d-%3d: ", 128, 145); + for (i = 128; i <= 145; i++) + printf("%02x ", spd->mpart[i - 128]); + printf(" Mfg's Module Part Number\n"); + + PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], + "Module Revision code"); + + PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); + PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); + + printf("%-3d-%3d: ", 150, 175); + for (i = 150; i <= 175; i++) + printf("%02x ", spd->msd[i - 150]); + printf(" Mfg's Specific Data\n"); + + printf("%-3d-%3d: ", 176, 255); + for (i = 176; i <= 255; i++) + printf("%02x", spd->cust[i - 176]); + printf(" Mfg's Specific Data\n"); + +} +#endif + +static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) +{ +#if defined(CONFIG_FSL_DDR1) + ddr1_spd_dump(spd); +#elif defined(CONFIG_FSL_DDR2) + ddr2_spd_dump(spd); +#elif defined(CONFIG_FSL_DDR3) + ddr3_spd_dump(spd); +#endif +} + +static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo, + unsigned int ctrl_mask, + unsigned int dimm_mask, + unsigned int do_mask) +{ + unsigned int i, j, retval; + + /* STEP 1: DIMM SPD data */ + if (do_mask & STEP_GET_SPD) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + if (!(dimm_mask & (1 << j))) + continue; + + printf("SPD info: Controller=%u " + "DIMM=%u\n", i, j); + generic_spd_dump( + &(pinfo->spd_installed_dimms[i][j])); + printf("\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 2: DIMM Parameters */ + if (do_mask & STEP_COMPUTE_DIMM_PARMS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + if (!(dimm_mask & (1 << j))) + continue; + printf("DIMM parameters: Controller=%u " + "DIMM=%u\n", i, j); + print_dimm_parameters( + &(pinfo->dimm_params[i][j])); + printf("\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 3: Common Parameters */ + if (do_mask & STEP_COMPUTE_COMMON_PARMS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("\"lowest common\" DIMM parameters: " + "Controller=%u\n", i); + print_lowest_common_dimm_parameters( + &pinfo->common_timing_params[i]); + printf("\n"); + } + printf("\n"); + } + + /* STEP 4: User Configuration Options */ + if (do_mask & STEP_GATHER_OPTS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("User Config Options: Controller=%u\n", i); + print_memctl_options(&pinfo->memctl_opts[i]); + printf("\n"); + } + printf("\n"); + } + + /* STEP 5: Address assignment */ + if (do_mask & STEP_ASSIGN_ADDRESSES) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + printf("Address Assignment: Controller=%u " + "DIMM=%u\n", i, j); + printf("Don't have this functionality yet\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 6: computed controller register values */ + if (do_mask & STEP_COMPUTE_REGS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("Computed Register Values: Controller=%u\n", i); + print_fsl_memctl_config_regs( + &pinfo->fsl_ddr_config_reg[i]); + retval = check_fsl_memctl_config_regs( + &pinfo->fsl_ddr_config_reg[i]); + if (retval) { + printf("check_fsl_memctl_config_regs " + "result = %u\n", retval); + } + printf("\n"); + } + printf("\n"); + } +} + +struct data_strings { + const char *data_name; + unsigned int step_mask; + unsigned int dimm_number_required; +}; + +#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm} + +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo) +{ + unsigned long long ddrsize; + const char *prompt = "FSL DDR>"; + unsigned int len; + char buffer[CONFIG_SYS_CBSIZE]; + char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ + int argc; + unsigned int next_step = STEP_GET_SPD; + static const struct data_strings options[] = { + DATA_OPTIONS(spd, STEP_GET_SPD, 1), + DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1), + DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0), + DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0), + DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0), + DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + const char *usage = { + "commands:\n" + "print print SPD and intermediate computed data\n" + "reset reboot machine\n" + "recompute reload SPD and options to default and recompute regs\n" + "edit modify spd, parameter, or option\n" + "compute recompute registers from current next_step to end\n" + "next_step shows current next_step\n" + "help this message\n" + "go program the memory controller and continue with u-boot\n" + }; + + /* + * The strategy for next_step is that it points to the next + * step in the computation process that needs to be done. + */ + while (1) { + /* + * No need to worry for buffer overflow here in + * this function; readline() maxes out at CFG_CBSIZE + */ + len = readline_into_buffer(prompt, buffer); + argc = parse_line(buffer, argv); + if (argc == 0) + continue; + + + if (strcmp(argv[0], "help") == 0) { + puts(usage); + continue; + } + + if (strcmp(argv[0], "next_step") == 0) { + printf("next_step = 0x%02X (%s)\n", + next_step, + step_to_string(next_step)); + continue; + } + + if (strcmp(argv[0], "edit") == 0) { + unsigned int i, j; + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int ctlr_mask = 0; + unsigned int dimm_mask = 0; + char *p_element = NULL; + char *p_value = NULL; + unsigned int dimm_number_required = 0; + unsigned int ctrl_num; + unsigned int dimm_num; + unsigned int matched = 0; + + if (argc == 1) { + /* Only the element and value must be last */ + printf("edit <c#> <d#> " + "<spd|dimmparms|commonparms|opts|" + "addresses|regs> <element> <value>\n"); + printf("for spd, specify byte number for " + "element\n"); + continue; + } + + for (i = 1; i < argc - 2; i++) { + for (j = 0; j < n_opts; j++) { + if (strcmp(options[j].data_name, + argv[i]) != 0) + continue; + step_mask |= options[j].step_mask; + dimm_number_required = + options[j].dimm_number_required; + matched = 1; + break; + } + + if (matched) + continue; + + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) + ctlr_mask |= 1 << (c - '0'); + continue; + } + + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) + dimm_mask |= 1 << (c - '0'); + continue; + } + + printf("unknown arg %s\n", argv[i]); + step_mask = 0; + error = 1; + break; + } + + + if (error) + continue; + + + /* Check arguments */ + + /* ERROR: If no steps were found */ + if (step_mask == 0) { + printf("Error: No valid steps were specified " + "in argument.\n"); + continue; + } + + /* ERROR: If multiple steps were found */ + if (step_mask & (step_mask - 1)) { + printf("Error: Multiple steps specified in " + "argument.\n"); + continue; + } + + /* ERROR: Controller not specified */ + if (ctlr_mask == 0) { + printf("Error: controller number not " + "specified or no element and " + "value specified\n"); + continue; + } + + if (ctlr_mask & (ctlr_mask - 1)) { + printf("Error: multiple controllers " + "specified, %X\n", ctlr_mask); + continue; + } + + /* ERROR: DIMM number not specified */ + if (dimm_number_required && dimm_mask == 0) { + printf("Error: DIMM number number not " + "specified or no element and " + "value specified\n"); + continue; + } + + if (dimm_mask & (dimm_mask - 1)) { + printf("Error: multipled DIMMs specified\n"); + continue; + } + + p_element = argv[argc - 2]; + p_value = argv[argc - 1]; + + ctrl_num = __ilog2(ctlr_mask); + dimm_num = __ilog2(dimm_mask); + + switch (step_mask) { + case STEP_GET_SPD: + { + unsigned int element_num; + unsigned int value; + + element_num = simple_strtoul(p_element, + NULL, 0); + value = simple_strtoul(p_value, + NULL, 0); + fsl_ddr_spd_edit(pinfo, + ctrl_num, + dimm_num, + element_num, + value); + next_step = STEP_COMPUTE_DIMM_PARMS; + } + break; + + case STEP_COMPUTE_DIMM_PARMS: + fsl_ddr_dimm_parameters_edit( + pinfo, ctrl_num, dimm_num, + p_element, p_value); + next_step = STEP_COMPUTE_COMMON_PARMS; + break; + + case STEP_COMPUTE_COMMON_PARMS: + lowest_common_dimm_parameters_edit(pinfo, + ctrl_num, p_element, p_value); + next_step = STEP_GATHER_OPTS; + break; + + case STEP_GATHER_OPTS: + fsl_ddr_options_edit(pinfo, ctrl_num, + p_element, p_value); + next_step = STEP_ASSIGN_ADDRESSES; + break; + + case STEP_ASSIGN_ADDRESSES: + printf("editing of address assignment " + "not yet implemented\n"); + break; + + case STEP_COMPUTE_REGS: + { + fsl_ddr_regs_edit(pinfo, + ctrl_num, + p_element, + p_value); + next_step = STEP_PROGRAM_REGS; + } + break; + + default: + printf("programming error\n"); + while (1) + ; + break; + } + continue; + } + + if (strcmp(argv[0], "reset") == 0) { + /* + * Reboot machine. + * Args don't seem to matter because this + * doesn't return + */ + do_reset(NULL, 0, 0, NULL); + } + + if (strcmp(argv[0], "recompute") == 0) { + /* + * Recalculate everything, starting with + * loading SPD EEPROM from DIMMs + */ + next_step = STEP_GET_SPD; + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + continue; + } + + if (strcmp(argv[0], "compute") == 0) { + /* + * Compute rest of steps starting at + * the current next_step/ + */ + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + continue; + } + + if (strcmp(argv[0], "print") == 0) { + unsigned int i, j; + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int ctlr_mask = 0; + unsigned int dimm_mask = 0; + unsigned int matched = 0; + + if (argc == 1) { + printf("print [c<n>] [d<n>] [spd] [dimmparms] " + "[commonparms] [opts] [addresses] [regs]\n"); + continue; + } + + for (i = 1; i < argc; i++) { + for (j = 0; j < n_opts; j++) { + if (strcmp(options[j].data_name, + argv[i]) != 0) + continue; + step_mask |= options[j].step_mask; + matched = 1; + break; + } + + if (matched) + continue; + + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) + ctlr_mask |= 1 << (c - '0'); + continue; + } + + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) + dimm_mask |= 1 << (c - '0'); + continue; + } + + printf("unknown arg %s\n", argv[i]); + step_mask = 0; + error = 1; + break; + } + + if (error) + continue; + + /* If no particular controller was found, print all */ + if (ctlr_mask == 0) + ctlr_mask = 0xFF; + + /* If no particular dimm was found, print all dimms. */ + if (dimm_mask == 0) + dimm_mask = 0xFF; + + /* If no steps were found, print all steps. */ + if (step_mask == 0) + step_mask = STEP_ALL; + + fsl_ddr_printinfo(pinfo, ctlr_mask, + dimm_mask, step_mask); + continue; + } + + if (strcmp(argv[0], "go") == 0) { + if (next_step) + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + break; + } + + printf("unknown command %s\n", argv[0]); + } + + debug("end of memory = %llu\n", (u64)ddrsize); + + return ddrsize; +} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 5699b0c2cc..f52ad9f691 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -135,7 +135,6 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, * | interleaving */ -#ifdef DEBUG const char *step_string_tbl[] = { "STEP_GET_SPD", "STEP_COMPUTE_DIMM_PARMS", @@ -156,7 +155,6 @@ const char * step_to_string(unsigned int step) { return step_string_tbl[s]; } -#endif int step_assign_addresses(fsl_ddr_info_t *pinfo, unsigned int dbw_cap_adj[], @@ -499,7 +497,12 @@ phys_size_t fsl_ddr_sdram(void) memset(&info, 0, sizeof(fsl_ddr_info_t)); /* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); +#ifdef CONFIG_FSL_DDR_INTERACTIVE + if (getenv("ddr_interactive")) + total_memory = fsl_ddr_interactive(&info); + else +#endif + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); /* Check for memory controller interleaving. */ memctl_interleaved = 0; diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h index fddc0cc8cb..2c0c9bc2f2 100644 --- a/arch/powerpc/include/asm/fsl_fman.h +++ b/arch/powerpc/include/asm/fsl_fman.h @@ -405,7 +405,14 @@ typedef struct fm_dtesc { } fm_dtsec_t; typedef struct fm_mdio { - u8 res[4*1024]; + u8 res0[0x120]; + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u8 res1[0x1000 - 0x138]; } fm_mdio_t; typedef struct fm_10gec { diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index fb5ef916cc..a29fe35cd3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1934,7 +1934,12 @@ typedef struct ccsr_gur { u8 res1[8]; u32 gpporcr; /* General-purpose POR configuration */ u8 res2[12]; +#if defined(CONFIG_MPC8536) + u32 gencfgr; /* General Configuration Register */ +#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 +#else u32 gpiocr; /* GPIO control */ +#endif u8 res3[12]; #if defined(CONFIG_MPC8569) u32 plppar1; /* Platform port pin assignment 1 */ diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 3b4dfa3f8c..4a53b8d933 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -107,166 +107,138 @@ phys_size_t fixed_sdram(void) return ddr_size; } -typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; +struct board_specific_parameters { u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; u32 wrlvl_start; u32 cpo; u32 write_data_delay; u32 force_2T; -} board_specific_parameters_t; +}; -const board_specific_parameters_t board_specific_parameters_udimm[][30] = { - { +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | |delay | + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | */ - { 0, 850, 4, 4, 6, 0xff, 2, 0}, - {851, 950, 4, 5, 7, 0xff, 2, 0}, - {951, 1050, 4, 5, 8, 0xff, 2, 0}, - {1051, 1250, 4, 5, 10, 0xff, 2, 0}, - {1251, 1350, 4, 5, 11, 0xff, 2, 0}, - {1351, 1666, 4, 5, 12, 0xff, 2, 0}, - { 0, 850, 2, 5, 6, 0xff, 2, 0}, - {851, 950, 2, 5, 7, 0xff, 2, 0}, - {951, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 4, 6, 0xff, 2, 0}, - {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - {1351, 1666, 2, 5, 8, 0xff, 2, 0}, - { 0, 850, 1, 4, 5, 0xff, 2, 0}, - {851, 950, 1, 4, 7, 0xff, 2, 0}, - {951, 1050, 1, 4, 8, 0xff, 2, 0}, - {1051, 1250, 1, 4, 8, 0xff, 2, 0}, - {1251, 1350, 1, 4, 8, 0xff, 2, 0}, - {1351, 1666, 1, 4, 8, 0xff, 2, 0}, - }, + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 5, 6, 0xff, 2, 0}, + {2, 1050, 5, 7, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; - { - /* - * memory controller 1 - * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | |delay | - */ - { 0, 850, 4, 4, 6, 0xff, 2, 0}, - {851, 950, 4, 5, 7, 0xff, 2, 0}, - {951, 1050, 4, 5, 8, 0xff, 2, 0}, - {1051, 1250, 4, 5, 10, 0xff, 2, 0}, - {1251, 1350, 4, 5, 11, 0xff, 2, 0}, - {1351, 1666, 4, 5, 12, 0xff, 2, 0}, - { 0, 850, 2, 5, 6, 0xff, 2, 0}, - {851, 950, 2, 5, 7, 0xff, 2, 0}, - {951, 1050, 2, 5, 7, 0xff, 2, 0}, - {1051, 1250, 2, 4, 6, 0xff, 2, 0}, - {1251, 1350, 2, 5, 7, 0xff, 2, 0}, - {1351, 1666, 2, 5, 8, 0xff, 2, 0}, - { 0, 850, 1, 4, 5, 0xff, 2, 0}, - {851, 950, 1, 4, 7, 0xff, 2, 0}, - {951, 1050, 1, 4, 8, 0xff, 2, 0}, - {1051, 1250, 1, 4, 8, 0xff, 2, 0}, - {1251, 1350, 1, 4, 8, 0xff, 2, 0}, - {1351, 1666, 1, 4, 8, 0xff, 2, 0}, - } +/* + * The two slots have slightly different timing. The center values are good + * for both slots. We use identical speed tables for them. In future use, if + * DIMMs have fewer center values that require two separated tables, copy the + * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm0, }; -const board_specific_parameters_t board_specific_parameters_rdimm[][30] = { - { +static const struct board_specific_parameters rdimm0[] = { /* * memory controller 0 - * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | |delay | + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | */ - { 0, 850, 4, 4, 6, 0xff, 2, 0}, - {851, 950, 4, 5, 7, 0xff, 2, 0}, - {951, 1050, 4, 5, 8, 0xff, 2, 0}, - {1051, 1250, 4, 5, 10, 0xff, 2, 0}, - {1251, 1350, 4, 5, 11, 0xff, 2, 0}, - {1351, 1666, 4, 5, 12, 0xff, 2, 0}, - { 0, 850, 2, 4, 6, 0xff, 2, 0}, - {851, 950, 2, 4, 7, 0xff, 2, 0}, - {951, 1050, 2, 4, 7, 0xff, 2, 0}, - {1051, 1250, 2, 4, 8, 0xff, 2, 0}, - {1251, 1350, 2, 4, 8, 0xff, 2, 0}, - {1351, 1666, 2, 4, 8, 0xff, 2, 0}, - { 0, 850, 1, 4, 5, 0xff, 2, 0}, - {851, 950, 1, 4, 7, 0xff, 2, 0}, - {951, 1050, 1, 4, 8, 0xff, 2, 0}, - {1051, 1250, 1, 4, 8, 0xff, 2, 0}, - {1251, 1350, 1, 4, 8, 0xff, 2, 0}, - {1351, 1666, 1, 4, 8, 0xff, 2, 0}, - }, + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 4, 6, 0xff, 2, 0}, + {2, 1050, 4, 7, 0xff, 2, 0}, + {2, 1666, 4, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; - { - /* - * memory controller 1 - * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | |delay | - */ - { 0, 850, 4, 4, 6, 0xff, 2, 0}, - {851, 950, 4, 5, 7, 0xff, 2, 0}, - {951, 1050, 4, 5, 8, 0xff, 2, 0}, - {1051, 1250, 4, 5, 10, 0xff, 2, 0}, - {1251, 1350, 4, 5, 11, 0xff, 2, 0}, - {1351, 1666, 4, 5, 12, 0xff, 2, 0}, - { 0, 850, 2, 4, 6, 0xff, 2, 0}, - {851, 950, 2, 4, 7, 0xff, 2, 0}, - {951, 1050, 2, 4, 7, 0xff, 2, 0}, - {1051, 1250, 2, 4, 8, 0xff, 2, 0}, - {1251, 1350, 2, 4, 8, 0xff, 2, 0}, - {1351, 1666, 2, 4, 8, 0xff, 2, 0}, - { 0, 850, 1, 4, 5, 0xff, 2, 0}, - {851, 950, 1, 4, 7, 0xff, 2, 0}, - {951, 1050, 1, 4, 8, 0xff, 2, 0}, - {1051, 1250, 1, 4, 8, 0xff, 2, 0}, - {1251, 1350, 1, 4, 8, 0xff, 2, 0}, - {1351, 1666, 1, 4, 8, 0xff, 2, 0}, - } +/* + * The two slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm0, }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp; - u32 num_params; - u32 i; + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - if (popts->registered_dimm_en) { - pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]); - num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) / - sizeof(board_specific_parameters_rdimm[0][0]); - } else { - pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); - num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / - sizeof(board_specific_parameters_udimm[0][0]); + if (ctrl_num > 1) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (i = 0; i < num_params; i++) { - if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm[0].n_ranks == pbsp->n_ranks) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; - break; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; } pbsp++; } - if (i == num_params) { - printf("Warning: board specific timing not found " - "for data rate %lu MT/s!\n", ddr_freq); + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); } - +found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c index 0209c1eca9..1d9d9959bd 100644 --- a/board/freescale/mpc8349emds/ddr.c +++ b/board/freescale/mpc8349emds/ddr.c @@ -26,40 +26,42 @@ #include <asm/fsl_ddr_dimm_params.h> struct board_specific_parameters { - u32 datarate_mhz_low; - u32 datarate_mhz_high; u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; u32 cpo; u32 write_data_delay; u32 force_2T; }; -const struct board_specific_parameters board_specific_parameters_udimm[][20] = { - { +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { /* - * memory controller 0 - * lo| hi| num| clk| cpo|wrdata|2T - * mhz| mhz|ranks|adjst| | delay| + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| */ - { 0, 300, 2, 4, 4, 2, 0}, - {301, 365, 2, 4, 6, 2, 0}, - {366, 450, 2, 4, 7, 2, 0}, - {451, 850, 2, 4, 31, 2, 0}, - { 0, 300, 1, 4, 4, 2, 0}, - {301, 365, 1, 4, 6, 2, 0}, - {366, 450, 1, 4, 7, 2, 0}, - {451, 850, 1, 4, 31, 2, 0} - } + {2, 300, 4, 4, 2, 0}, + {2, 365, 4, 6, 2, 0}, + {2, 450, 4, 7, 2, 0}, + {2, 850, 4, 31, 2, 0}, + {1, 300, 4, 4, 2, 0}, + {1, 365, 4, 6, 2, 0}, + {1, 450, 4, 7, 2, 0}, + {1, 850, 4, 31, 2, 0}, + {} }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const struct board_specific_parameters *pbsp; - u32 num_params; - u32 i, dimm_num; + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + unsigned int i; ulong ddr_freq; if (ctrl_num != 0) /* we have only one controller */ @@ -71,33 +73,41 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ return; - dimm_num = i; - pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); - num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / - sizeof(board_specific_parameters_udimm[0][0]); + pbsp = udimm0; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (i = 0; i < num_params; i++) { - if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm[dimm_num].n_ranks == pbsp->n_ranks) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; - break; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm[i].n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; } pbsp++; } - if (i == num_params) { - printf("Warning: board specific timing not found " - "for data rate %lu MT/s!\n", ddr_freq); + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); } +found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index b292e13541..c9f85c857b 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -49,10 +49,16 @@ int board_early_init_f (void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SD_DATA | - MPC85xx_PMUXCR_SDHC_CD | + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); + /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118, + * however, this erratum only applies to MPC8536 Rev1.0. + * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ + if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) && + (SVR_MIN(get_svr()) >= 0x1)) + || (SVR_MAJ(get_svr() & 0x7) > 0x1)) + setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); #endif return 0; } diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index adcbd58545..a7ff668b1b 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -11,155 +11,156 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> -typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; +struct board_specific_parameters { u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; u32 cpo; u32 write_data_delay; u32 force_2T; -} board_specific_parameters_t; +}; /* - * CPO value doesn't matter if workaround for errata 111 and 134 enabled. + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. * * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G. * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1. + * + * CPO value doesn't matter if workaround for errata 111 and 134 enabled. */ -const board_specific_parameters_t board_specific_parameters_udimm[][20] = { - { +static const struct board_specific_parameters udimm0[] = { /* - * memory controller 0 - * lo| hi| num| clk| cpo|wrdata|2T - * mhz| mhz|ranks|adjst| | delay| + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| */ - { 0, 333, 2, 8, 7, 5, 0}, - {334, 400, 2, 8, 9, 5, 0}, - {401, 549, 2, 8, 11, 5, 0}, - {550, 680, 2, 8, 10, 5, 0}, - {681, 850, 2, 8, 12, 5, 1}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 10, 5, 0}, - {681, 850, 1, 1, 12, 5, 0} - }, + {2, 333, 8, 7, 5, 0}, + {2, 400, 8, 9, 5, 0}, + {2, 549, 8, 11, 5, 0}, + {2, 680, 8, 10, 5, 0}, + {2, 850, 8, 12, 5, 1}, + {1, 333, 6, 7, 3, 0}, + {1, 400, 6, 9, 3, 0}, + {1, 549, 6, 11, 3, 0}, + {1, 680, 1, 10, 5, 0}, + {1, 850, 1, 12, 5, 0}, + {} +}; - { +static const struct board_specific_parameters udimm1[] = { /* - * memory controller 1 - * lo| hi| num| clk| cpo|wrdata|2T - * mhz| mhz|ranks|adjst| | delay| + * memory controller 1 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| */ - { 0, 333, 2, 8, 7, 5, 0}, - {334, 400, 2, 8, 9, 5, 0}, - {401, 549, 2, 8, 11, 5, 0}, - {550, 680, 2, 8, 11, 5, 0}, - {681, 850, 2, 8, 13, 5, 1}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 11, 6, 0}, - {681, 850, 1, 1, 13, 6, 0} - } + {2, 333, 8, 7, 5, 0}, + {2, 400, 8, 9, 5, 0}, + {2, 549, 8, 11, 5, 0}, + {2, 680, 8, 11, 5, 0}, + {2, 850, 8, 13, 5, 1}, + {1, 333, 6, 7, 3, 0}, + {1, 400, 6, 9, 3, 0}, + {1, 549, 6, 11, 3, 0}, + {1, 680, 1, 11, 6, 0}, + {1, 850, 1, 13, 6, 0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, + udimm1, }; -const board_specific_parameters_t board_specific_parameters_rdimm[][20] = { - { +static const struct board_specific_parameters rdimm0[] = { /* - * memory controller 0 - * lo| hi| num| clk| cpo|wrdata|2T - * mhz| mhz|ranks|adjst| | delay| + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| */ - { 0, 333, 2, 4, 7, 3, 0}, - {334, 400, 2, 4, 9, 3, 0}, - {401, 549, 2, 4, 11, 3, 0}, - {550, 680, 2, 4, 10, 3, 0}, - {681, 850, 2, 4, 12, 3, 1}, - }, + {2, 333, 4, 7, 3, 0}, + {2, 400, 4, 9, 3, 0}, + {2, 549, 4, 11, 3, 0}, + {2, 680, 4, 10, 3, 0}, + {2, 850, 4, 12, 3, 1}, + {} +}; - { +static const struct board_specific_parameters rdimm1[] = { /* - * memory controller 1 - * lo| hi| num| clk| cpo|wrdata|2T - * mhz| mhz|ranks|adjst| | delay| + * memory controller 1 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| */ - { 0, 333, 2, 4, 7, 3, 0}, - {334, 400, 2, 4, 9, 3, 0}, - {401, 549, 2, 4, 11, 3, 0}, - {550, 680, 2, 4, 11, 3, 0}, - {681, 850, 2, 4, 13, 3, 1}, - } + {2, 333, 4, 7, 3, 0}, + {2, 400, 4, 9, 3, 0}, + {2, 549, 4, 11, 3, 0}, + {2, 680, 4, 11, 3, 0}, + {2, 850, 4, 13, 3, 1}, + {} +}; + +static const struct board_specific_parameters *rdimms[] = { + rdimm0, + rdimm1, }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp; - u32 num_params; - u32 i; + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - if (!pdimm->n_ranks) + if (ctrl_num > 1) { + printf("Wrong parameter for controller number %d", ctrl_num); return; - - if (popts->registered_dimm_en) { - pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]); - num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) / - sizeof(board_specific_parameters_rdimm[0][0]); - } else { - pbsp = &(board_specific_parameters_udimm[ctrl_num][0]); - num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) / - sizeof(board_specific_parameters_udimm[0][0]); } + if (!pdimm->n_ranks) + return; - /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in - * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If - * there are two dimms in the controller, set odt_rd_cfg to 3 and - * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. - */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i&1) { /* odd CS */ - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 0; - } else { /* even CS */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 4; - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - popts->cs_local_opts[i].odt_rd_cfg = 3; - popts->cs_local_opts[i].odt_wr_cfg = 3; - } - } - } + if (popts->registered_dimm_en) + pbsp = rdimms[ctrl_num]; + else + pbsp = udimms[ctrl_num]; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (i = 0; i < num_params; i++) { - if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm->n_ranks == pbsp->n_ranks) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; - break; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; } pbsp++; } - if (i == num_params) { - printf("Warning: board specific timing not found " - "for data rate %lu MT/s!\n", ddr_freq); + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + } else { + panic("DIMM is not supported by this board"); } +found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 4f2e853cd1..5d3575738a 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008,2011 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -11,127 +11,100 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> -typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; +struct board_specific_parameters { u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; u32 cpo; u32 write_data_delay; -} board_specific_parameters_t; - -/* XXX: these values need to be checked for all interleaving modes. */ -const board_specific_parameters_t board_specific_parameters[2][16] = { - { - /* memory controller 0 */ - /* lo| hi| num| clk| cpo|wrdata */ - /* mhz| mhz|ranks|adjst| | delay */ - { 0, 333, 4, 7, 7, 3}, - {334, 400, 4, 7, 9, 3}, - {401, 549, 4, 7, 9, 3}, - {550, 650, 4, 7, 10, 4}, - - { 0, 333, 3, 7, 7, 3}, - {334, 400, 3, 7, 9, 3}, - {401, 549, 3, 7, 9, 3}, - {550, 650, 3, 7, 10, 4}, - - { 0, 333, 2, 7, 7, 3}, - {334, 400, 2, 7, 9, 3}, - {401, 549, 2, 7, 9, 3}, - {550, 650, 2, 7, 10, 4}, - - { 0, 333, 1, 7, 7, 3}, - {334, 400, 1, 7, 9, 3}, - {401, 549, 1, 7, 9, 3}, - {550, 650, 1, 7, 10, 4} - }, - - { - /* memory controller 1 */ - /* lo| hi| num| clk| cpo|wrdata */ - /* mhz| mhz|ranks|adjst| | delay */ - { 0, 333, 4, 7, 7, 3}, - {334, 400, 4, 7, 9, 3}, - {401, 549, 4, 7, 9, 3}, - {550, 650, 4, 7, 10, 4}, - - { 0, 333, 3, 7, 7, 3}, - {334, 400, 3, 7, 9, 3}, - {401, 549, 3, 7, 9, 3}, - {550, 650, 3, 7, 10, 4}, +}; - { 0, 333, 2, 7, 7, 3}, - {334, 400, 2, 7, 9, 3}, - {401, 549, 2, 7, 9, 3}, - {550, 650, 2, 7, 10, 4}, +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +const struct board_specific_parameters dimm0[] = { + /* + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| + */ + {4, 333, 7, 7, 3}, + {4, 549, 7, 9, 3}, + {4, 650, 7, 10, 4}, + {2, 333, 7, 7, 3}, + {2, 549, 7, 9, 3}, + {2, 650, 7, 10, 4}, + {1, 333, 7, 7, 3}, + {1, 549, 7, 9, 3}, + {1, 650, 7, 10, 4}, + {} +}; - { 0, 333, 1, 7, 7, 3}, - {334, 400, 1, 7, 9, 3}, - {401, 549, 1, 7, 9, 3}, - {550, 650, 1, 7, 10, 4} - } +/* + * The two slots have slightly different timing. The center values are good + * for both slots. We use identical speed tables for them. In future use, if + * DIMMs have fewer center values that require two separated tables, copy the + * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start. + */ +const struct board_specific_parameters *dimms[] = { + dimm0, + dimm0, }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp = - &(board_specific_parameters[ctrl_num][0]); - u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / - sizeof(board_specific_parameters[0][0]); - u32 i; - u32 j; + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + unsigned int i; ulong ddr_freq; - /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in - * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If - * there are two dimms in the controller, set odt_rd_cfg to 3 and - * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. - */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i&1) { /* odd CS */ - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 0; - } else { /* even CS */ - if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) && - (pdimm[i/2].n_ranks != 0)) { - popts->cs_local_opts[i].odt_rd_cfg = 3; - popts->cs_local_opts[i].odt_wr_cfg = 3; - } else { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 4; - } - } + if (ctrl_num > 1) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; } + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (pdimm[i].n_ranks) + break; + } + if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */ + return; + + pbsp = dimms[ctrl_num]; /* Get clk_adjust, cpo, write_data_delay, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - if (pdimm[j].n_ranks > 0) { - for (i = 0; i < num_params; i++) { - if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm[j].n_ranks == pbsp->n_ranks) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - break; - } - pbsp++; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm[i].n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; } + pbsp_highest = pbsp; } + pbsp++; } - if (i == num_params) { - printf("Warning: board specific timing not found " - "for data rate %lu MT/s!\n", ddr_freq); + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + } else { + panic("DIMM is not supported by this board"); } +found: /* 2T timing enable */ popts->twoT_en = 1; } diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index 20b996e52a..455e5e725f 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -14,62 +14,89 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> -typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; +struct board_specific_parameters { u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; /* Range: 0-8 */ u32 cpo; /* Range: 2-31 */ u32 write_data_delay; /* Range: 0-6 */ u32 force_2T; -} board_specific_parameters_t; +}; -static const board_specific_parameters_t bsp[] = { /* - * lo| hi| num| clk| cpo|wrdata|2T - * mhz| mhz|ranks|adjst| | delay| + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. */ - { 0, 333, 1, 5, 31, 3, 0}, - {334, 400, 1, 5, 31, 3, 0}, - {401, 549, 1, 5, 31, 3, 0}, - {550, 680, 1, 5, 31, 5, 0}, - {681, 850, 1, 5, 31, 5, 0}, - { 0, 333, 2, 5, 31, 3, 0}, - {334, 400, 2, 5, 31, 3, 0}, - {401, 549, 2, 5, 31, 3, 0}, - {550, 680, 2, 5, 31, 5, 0}, - {681, 850, 2, 5, 31, 5, 0}, +static const struct board_specific_parameters dimm0[] = { + /* + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| + */ + {1, 549, 5, 31, 3, 0}, + {1, 850, 5, 31, 5, 0}, + {2, 549, 5, 31, 3, 0}, + {2, 850, 5, 31, 5, 0}, + {} }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; unsigned long ddr_freq; unsigned int i; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + /* set odt_rd_cfg and odt_wr_cfg. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = 0; popts->cs_local_opts[i].odt_wr_cfg = 1; } + pbsp = dimm0; /* * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (i = 0; i < ARRAY_SIZE(bsp); i++) { - if (ddr_freq >= bsp[i].datarate_mhz_low && - ddr_freq <= bsp[i].datarate_mhz_high && - pdimm->n_ranks == bsp[i].n_ranks) { - popts->clk_adjust = bsp[i].clk_adjust; - popts->cpo_override = bsp[i].cpo; - popts->write_data_delay = bsp[i].write_data_delay; - popts->twoT_en = bsp[i].force_2T; - break; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + } else { + panic("DIMM is not supported by this board"); } +found: popts->half_strength_driver_enable = 1; /* Per AN4039, enable ZQ calibration. */ diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 926fd19271..c43f874c92 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -11,88 +11,95 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> -typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; +struct board_specific_parameters { u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; u32 cpo; u32 write_data_delay; u32 force_2T; -} board_specific_parameters_t; +}; -/* ranges for parameters: + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + * + * ranges for parameters: * wr_data_delay = 0-6 * clk adjust = 0-8 * cpo 2-0x1E (30) */ - -const board_specific_parameters_t board_specific_parameters[][20] = { - { - /* memory controller 0 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ +static const struct board_specific_parameters dimm0[] = { + /* + * memory controller 0 + * num| hi| clk| cpo|wrdata|2T + * ranks| mhz|adjst| | delay| + */ #ifdef CONFIG_FSL_DDR2 - { 0, 333, 2, 4, 0x1f, 2, 0}, - {334, 400, 2, 4, 0x1f, 2, 0}, - {401, 549, 2, 4, 0x1f, 2, 0}, - {550, 680, 2, 4, 0x1f, 3, 0}, - {681, 850, 2, 4, 0x1f, 4, 0}, - { 0, 333, 1, 4, 0x1f, 2, 0}, - {334, 400, 1, 4, 0x1f, 2, 0}, - {401, 549, 1, 4, 0x1f, 2, 0}, - {550, 680, 1, 4, 0x1f, 3, 0}, - {681, 850, 1, 4, 0x1f, 4, 0} + {2, 549, 4, 0x1f, 2, 0}, + {2, 680, 4, 0x1f, 3, 0}, + {2, 850, 4, 0x1f, 4, 0}, + {1, 549, 4, 0x1f, 2, 0}, + {1, 680, 4, 0x1f, 3, 0}, + {1, 850, 4, 0x1f, 4, 0}, #else - { 0, 850, 2, 6, 0x1f, 4, 0}, - { 0, 850, 1, 4, 0x1f, 4, 0} + {2, 850, 6, 0x1f, 4, 0}, + {1, 850, 4, 0x1f, 4, 0}, #endif - }, + {} }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp = - &(board_specific_parameters[ctrl_num][0]); - u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / - sizeof(board_specific_parameters[0][0]); - u32 i; + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; - /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in - * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If - * there are two dimms in the controller, set odt_rd_cfg to 3 and - * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. - */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 1; + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; } + if (!pdimm->n_ranks) + return; + + pbsp = dimm0; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (i = 0; i < num_params; i++) { - if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm->n_ranks == pbsp->n_ranks) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->twoT_en = pbsp->force_2T; - break; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; } pbsp++; } - if (i == num_params) { - printf("Warning: board specific timing not found " - "for data rate %lu MT/s!\n", ddr_freq); + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); } +found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index 36370933b4..6d9a5de1c5 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -14,69 +14,91 @@ #include <asm/fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> -typedef struct { - u32 datarate_mhz_low; - u32 datarate_mhz_high; +struct board_specific_parameters { u32 n_ranks; + u32 datarate_mhz_high; u32 clk_adjust; u32 wrlvl_start; u32 cpo; u32 write_data_delay; u32 force_2T; -} board_specific_parameters_t; +}; /* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + * * ranges for parameters: * wr_data_delay = 0-6 * clk adjust = 0-8 * cpo 2-0x1E (30) */ -const board_specific_parameters_t board_specific_parameters[] = { +static const struct board_specific_parameters dimm0[] = { /* * memory controller 0 - * lo| hi| num| clk| wrlvl | cpo |wrdata|2T - * mhz| mhz|ranks|adjst| start | delay| + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | delay| */ - { 0, 750, 2, 3, 5, 0xff, 2, 0}, - { 751, 1250, 2, 4, 6, 0xff, 2, 0}, - { 1251, 1350, 2, 5, 7, 0xff, 2, 0}, - { 1351, 1666, 2, 5, 8, 0xff, 2, 0}, + {2, 750, 3, 5, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {} }; void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { - const board_specific_parameters_t *pbsp = - &board_specific_parameters[0]; - u32 num_params = ARRAY_SIZE(board_specific_parameters); - u32 i; + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = dimm0; + /* * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ ddr_freq = get_ddr_freq(0) / 1000000; - for (i = 0; i < num_params; i++) { - if (ddr_freq >= pbsp->datarate_mhz_low && - ddr_freq <= pbsp->datarate_mhz_high && - pdimm[0].n_ranks == pbsp->n_ranks) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->twoT_en = pbsp->force_2T; - break; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; } pbsp++; } - if (i == num_params) { - printf("Warning: board specific timing not found " - "for data rate %lu MT/s!\n", ddr_freq); + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); } +found: /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index abfb7f192d..1d50153d58 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -222,3 +222,153 @@ Single slot system Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf + +Interactive DDR debugging +=========================== + +For DDR parameter tuning up and debugging, the interactive DDR debugging can +be activated by saving an environment variable "ddr_interactive". The value +doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR +controller. The available commands can be seen by typing "help". + +The example flow of using interactive debugging is +type command "compute" to calculate the parameters from the default +type command "print" with arguments to show SPD, options, registers +type command "edit" with arguments to change any if desired +type command "go" to continue calculation and enable DDR controller +type command "reset" to reset the board +type command "recompute" to reload SPD and start over + +Note, check "next_step" to show the flow. For example, after edit opts, the +next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is +STEP_PROGRAM_REGS. Upon issuing command "go", DDR controller will be enabled +with current setting without further calculation. + +The detail syntax for each commands are + +print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] + c<n> - the controller number, eg. c0, c1 + d<n> - the DIMM number, eg. d0, d1 + spd - print SPD data + dimmparms - DIMM paramaters, calcualted from SPD + commonparms - lowest common parameters for all DIMMs + opts - options + addresses - address assignment (not implemented yet) + regs - controller registers + +edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value> + c<n> - the controller number, eg. c0, c1 + d<n> - the DIMM number, eg. d0, d1 + spd - print SPD data + dimmparms - DIMM paramaters, calcualted from SPD + commonparms - lowest common parameters for all DIMMs + opts - options + addresses - address assignment (not implemented yet) + regs - controller registers + <element> - name of the modified element + byte number if the object is SPD + <value> - decimal or heximal (prefixed with 0x) numbers + +reset + no arguement - reset the board + +recompute + no argument - reload SPD and start over + +compute + no argument - recompute from current next_step + +next_step + no argument - show current next_step + +help + no argument - print a list of all commands + +go + no argument - program memory controller(s) and continue with U-boot + +Examples of debugging flow + + FSL DDR>compute + Detected UDIMM UG51U6400N8SU-ACF + SL DDR>print + print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs] + FSL DDR>print dimmparms + DIMM parameters: Controller=0 DIMM=0 + DIMM organization parameters: + module part name = UG51U6400N8SU-ACF + rank_density = 2147483648 bytes (2048 megabytes) + capacity = 4294967296 bytes (4096 megabytes) + burst_lengths_bitmask = 0C + base_addresss = 0 (00000000 00000000) + n_ranks = 2 + data_width = 64 + primary_sdram_width = 64 + ec_sdram_width = 0 + registered_dimm = 0 + n_row_addr = 15 + n_col_addr = 10 + edc_config = 0 + n_banks_per_sdram_device = 8 + tCKmin_X_ps = 1500 + tCKmin_X_minus_1_ps = 0 + tCKmin_X_minus_2_ps = 0 + tCKmax_ps = 0 + caslat_X = 960 + tAA_ps = 13125 + caslat_X_minus_1 = 0 + caslat_X_minus_2 = 0 + caslat_lowest_derated = 0 + tRCD_ps = 13125 + tRP_ps = 13125 + tRAS_ps = 36000 + tWR_ps = 15000 + tWTR_ps = 7500 + tRFC_ps = 160000 + tRRD_ps = 6000 + tRC_ps = 49125 + refresh_rate_ps = 7800000 + tIS_ps = 0 + tIH_ps = 0 + tDS_ps = 0 + tDH_ps = 0 + tRTP_ps = 7500 + tDQSQ_max_ps = 0 + tQHS_ps = 0 + FSL DDR>edit c0 opts ECC_mode 0 + FSL DDR>edit c0 regs cs0_bnds 0x000000FF + FSL DDR>go + 2 GiB left unmapped + 4 GiB (DDR3, 64-bit, CL=9, ECC off) + DDR Chip-Select Interleaving Mode: CS0+CS1 + Testing 0x00000000 - 0x7fffffff + Testing 0x80000000 - 0xffffffff + Remap DDR 2 GiB left unmapped + + POST memory PASSED + Flash: 128 MiB + L2: 128 KB enabled + Corenet Platform Cache: 1024 KB enabled + SERDES: timeout resetting bank 3 + SRIO1: disabled + SRIO2: disabled + MMC: FSL_ESDHC: 0 + EEPROM: Invalid ID (ff ff ff ff) + PCIe1: disabled + PCIe2: Root Complex, x1, regs @ 0xfe201000 + 01:00.0 - 8086:10d3 - Network controller + PCIe2: Bus 00 - 01 + PCIe3: disabled + In: serial + Out: serial + Err: serial + Net: Initializing Fman + Fman1: Uploading microcode version 101.8.0 + e1000: 00:1b:21:81:d2:e0 + FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME] + Warning: e1000#0 MAC addresses don't match: + Address in SROM is 00:1b:21:81:d2:e0 + Address in environment is 00:e0:0c:00:ea:05 + + Hit any key to stop autoboot: 0 + => diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index 4b97a0e226..b101bd7640 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -700,7 +700,7 @@ u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write int ncq_channel; u64 block; - if (sata_dev_desc[dev].lba48 != 1) { + if (sata->lba48 != 1) { printf("execute FPDMA command on non-LBA48 hard disk\n\r"); return -1; } @@ -854,8 +854,9 @@ u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_ ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer) { u32 rc; + fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; - if (sata_dev_desc[dev].lba48) + if (sata->lba48) rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD); else rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD); @@ -865,8 +866,9 @@ ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer) ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer) { u32 rc; + fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv; - if (sata_dev_desc[dev].lba48) { + if (sata->lba48) { rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD); if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev)) fsl_sata_flush_cache_ext(dev); @@ -916,11 +918,14 @@ int scan_sata(int dev) n_sectors = ata_id_n_sectors(id); sata_dev_desc[dev].lba = (u32)n_sectors; +#ifdef CONFIG_LBA48 /* Check if support LBA48 */ if (ata_id_has_lba48(id)) { - sata_dev_desc[dev].lba48 = 1; + sata->lba48 = 1; debug("Device support LBA48\n\r"); - } + } else + debug("Device supports LBA28\n\r"); +#endif /* Get the NCQ queue depth from device */ sata->queue_depth = ata_id_queue_depth(id); diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d41579c9ce..e8506ddd9b 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -176,35 +176,35 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, #ifdef CONFIG_SYS_NAND_HW_ECC -static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) +static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) { - u_int32_t val; + u_int32_t ecc = 0; - (void)__raw_readl(&(davinci_emif_regs->nandfecc[ + ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ CONFIG_SYS_NAND_CS - 2])); - val = __raw_readl(&davinci_emif_regs->nandfcr); - val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); - val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); - __raw_writel(val, &davinci_emif_regs->nandfcr); + return ecc; } -static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) +static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - u_int32_t ecc = 0; + u_int32_t val; - ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1])); + /* reading the ECC result register resets the ECC calculation */ + nand_davinci_readecc(mtd); - return ecc; + val = __raw_readl(&davinci_emif_regs->nandfcr); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + __raw_writel(val, &davinci_emif_regs->nandfcr); } static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { u_int32_t tmp; - const int region = 1; - tmp = nand_davinci_readecc(mtd, region); + tmp = nand_davinci_readecc(mtd); /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */ diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 3ea0e6c8d1..d144ac29bc 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -476,21 +476,21 @@ static int attach_by_scanning(struct ubi_device *ubi) if (err) goto out_si; - err = ubi_wl_init_scan(ubi, si); - if (err) - goto out_vtbl; - err = ubi_eba_init_scan(ubi, si); if (err) goto out_wl; + err = ubi_wl_init_scan(ubi, si); + if (err) + goto out_vtbl; + ubi_scan_destroy_si(si); return 0; -out_wl: - ubi_wl_close(ubi); out_vtbl: vfree(ubi->vtbl); +out_wl: + ubi_wl_close(ubi); out_si: ubi_scan_destroy_si(si); return err; diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c index a77ee20f3b..7dd78f2e9d 100644 --- a/drivers/net/fm/dtsec.c +++ b/drivers/net/fm/dtsec.c @@ -171,7 +171,7 @@ void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs, int max_rx_len) { mac->base = base; - mac->phyregs = NULL; + mac->phyregs = phyregs; mac->max_rx_len = max_rx_len; mac->init_mac = dtsec_init_mac; mac->enable_mac = dtsec_enable_mac; diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 308d610a78..f7ed850c91 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -537,6 +537,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) /* Get the mac registers base address */ if (fm_eth->type == FM_ETH_1G_E) { base = ®->mac_1g[num].fm_dtesc; + phyregs = ®->mac_1g[num].fm_mdio.miimcfg; } else { base = ®->mac_10g[num].fm_10gec; phyregs = ®->mac_10g[num].fm_10gec_mdio; @@ -552,7 +553,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) fm_eth->mac = mac; if (fm_eth->type == FM_ETH_1G_E) - init_dtsec(mac, base, NULL, MAX_RXBUF_LEN); + init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN); else init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index a771791b76..a13b48cee6 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -41,6 +41,25 @@ int tn2020_config(struct phy_device *phydev) return 0; } +int tn2020_startup(struct phy_device *phydev) +{ + if (phydev->port != PORT_FIBRE) + return gen10g_startup(phydev); + + /* + * The TN2020 only pretends to support fiber. + * It works, but it doesn't look like it works, + * so the link status reports no link. + */ + phydev->link = 1; + + /* For now just lie and say it's 10G all the time */ + phydev->speed = SPEED_10000; + phydev->duplex = DUPLEX_FULL; + + return 0; +} + struct phy_driver tn2020_driver = { .name = "Teranetics TN2020", .uid = 0x00a19410, @@ -50,7 +69,7 @@ struct phy_driver tn2020_driver = { MDIO_DEVS_PHYXS | MDIO_DEVS_AN | MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), .config = &tn2020_config, - .startup = &gen10g_startup, + .startup = &tn2020_startup, .shutdown = &gen10g_shutdown, }; diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index 63b2164d30..26b48f029e 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -848,8 +848,10 @@ void ubifs_umount(struct ubifs_info *c) ubifs_debugging_exit(c); /* Finally free U-Boot's global copy of superblock */ - free(ubifs_sb->s_fs_info); - free(ubifs_sb); + if (ubifs_sb != NULL) { + free(ubifs_sb->s_fs_info); + free(ubifs_sb); + } } /** diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 3efe9373fd..4b8cba24b2 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -77,6 +77,7 @@ #define CONFIG_MPC8536DS 1 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ +#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -458,6 +459,19 @@ #define CONFIG_SYS_EEPROM_BUS_NUM 1 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_HARD_SPI +#define CONFIG_FSL_ESPI + +#if defined(CONFIG_SPI_FLASH) +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ @@ -630,10 +644,24 @@ #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) - #define CONFIG_ENV_IS_IN_NAND 1 - #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) +#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0xF0000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 @@ -680,6 +708,21 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC +#endif + +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 63e23c276e..ab887c1b9c 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -86,6 +86,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -162,6 +163,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_HWCONFIG /* enable hwconfig */ /* * SDRAM on the Local Bus @@ -276,7 +278,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -381,8 +383,9 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ @@ -423,8 +426,12 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -524,20 +531,21 @@ extern unsigned long get_clock_freq(void); #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=mpc8548cds.dtb\0" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ecc=off\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ + "consoledev=ttyS1\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8548cds.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 2bd67c3e11..93b360a2ba 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -99,9 +99,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL +#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f #else -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 +#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 #endif /* @@ -114,14 +114,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Physical addresses */ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf -#define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) -#else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#endif +#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH +#define CONFIG_SYS_CCSRBAR_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ @@ -181,8 +177,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ -#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} @@ -204,12 +202,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * required for the smallest BAT mapping, so there's a 64k hole. */ #define CONFIG_SYS_LBC_BASE 0xffde0000 -#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) -#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) +#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) +#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define PIXIS_SIZE 0x00008000 /* 32k */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -315,10 +314,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c #else -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE +#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 #endif +#define CONFIG_SYS_SRIO1_MEM_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ /* @@ -330,16 +334,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c #else #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 #endif +#define CONFIG_SYS_PCIE1_MEM_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ - | CONFIG_SYS_PHYS_ADDR_HIGH) +#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT +#define CONFIG_SYS_PCIE1_IO_PHYS \ + PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ #ifdef CONFIG_PHYS_64BIT @@ -355,12 +366,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ + CONFIG_SYS_PCIE1_MEM_SIZE) #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ + + CONFIG_SYS_PCIE1_IO_SIZE) #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ + CONFIG_SYS_PCIE1_IO_SIZE) #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE @@ -455,21 +471,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TSEC_ENET */ -/* Contort an addr into the format needed for BATs */ -#ifdef CONFIG_PHYS_64BIT -#define BAT_PHYS_ADDR(x) ((unsigned long) \ - ((x & 0x00000000ffffffffULL) | \ - ((x & 0x0000000e00000000ULL) >> 24) | \ - ((x & 0x0000000100000000ULL) >> 30))) -#else -#define BAT_PHYS_ADDR(x) (x) -#endif - -/* Put high physical address bits into the BAT format */ +#ifdef CONFIG_PHYS_64BIT #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) +/* Put physical address into the BAT format */ +#define BAT_PHYS_ADDR(low, high) \ + (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) +/* Convert high/low pairs to actual 64-bit value */ +#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) +#else +/* 32-bit systems just ignore the "high" bits */ +#define BAT_PHYS_ADDR(low, high) (low) +#define PAIRED_PHYS_TO_PHYS(low, high) (low) +#endif + /* * BAT0 DDR */ @@ -479,12 +496,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT1 LBC (PIXIS/CF) */ -#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ +#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ +#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U @@ -494,45 +513,40 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * BAT2 Rapidio Memory */ #ifdef CONFIG_PCI -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ + CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ + CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) - -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #endif /* * BAT3 CCSR Space - * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs - * instead. The assembler chokes on ULL. */ -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ +#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ - | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ +#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ + CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U @@ -550,12 +564,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT4 PCIE1_IO and PCIE2_IO */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ +#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ +#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U @@ -570,12 +586,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * BAT6 FLASH */ -#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ | BATU_VP) -#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ + CONFIG_SYS_PHYS_ADDR_HIGH) \ | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index d892b6701b..9620370874 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -43,8 +43,9 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#ifdef CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h index 4fc5262bc1..146819712d 100644 --- a/include/configs/dlvision-10g.h +++ b/include/configs/dlvision-10g.h @@ -34,7 +34,7 @@ * Include common defines/options for all AMCC eval boards */ #define CONFIG_HOSTNAME dlvsion-10g -#define CONFIG_IDENT_STRING " dlvision-10g 0.01" +#define CONFIG_IDENT_STRING " dlvision-10g 0.02" #include "amcc-common.h" #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ @@ -117,8 +117,8 @@ #define CONFIG_DTT_LM63 1 /* National LM63 */ #define CONFIG_DTT_SENSORS { 0x4c, 0x4e } /* Sensor addresses */ #define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 43, 13 }, { 46, 16 }, \ - { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } } + { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\ + { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } #define CONFIG_DTT_TACH_LIMIT 0xa10 /* EBC peripherals */ diff --git a/include/configs/intip.h b/include/configs/intip.h index 3ff4a86ab9..92b65af7c9 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -37,10 +37,10 @@ #define CONFIG_460EX 1 /* Specific PPC460EX */ #ifdef CONFIG_DEVCONCENTER #define CONFIG_HOSTNAME devconcenter -#define CONFIG_IDENT_STRING " devconcenter 0.02" +#define CONFIG_IDENT_STRING " devconcenter 0.05" #else #define CONFIG_HOSTNAME intip -#define CONFIG_IDENT_STRING " intip 0.02" +#define CONFIG_IDENT_STRING " intip 0.05" #endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ @@ -63,6 +63,10 @@ #define CONFIG_FIT #define CFG_ALT_MEMTEST +#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ +#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ +#define CONFIG_AUTOBOOT_STOP_STR " " + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -196,13 +200,13 @@ #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 #define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002 -#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 +#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552 #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 -#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 +#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452 #define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382 #define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 @@ -212,11 +216,11 @@ #define CONFIG_SYS_SDRAM0_RDCC 0x40000000 #define CONFIG_SYS_SDRAM0_DLCR 0x00000000 #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 -#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823 +#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 #define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15 -#define CONFIG_SYS_SDRAM0_MMODE 0x00000442 +#define CONFIG_SYS_SDRAM0_MMODE 0x00000452 #define CONFIG_SYS_SDRAM0_MEMODE 0x00000002 #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index b9b89cfa5d..b3d981f3e4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -204,9 +204,8 @@ #define CONFIG_BTB #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ -#ifdef CONFIG_PHYS_64BIT + #define CONFIG_ENABLE_36BIT_PHYS -#endif #ifdef CONFIG_PHYS_64BIT #define CONFIG_ADDR_MAP 1 @@ -232,7 +231,7 @@ #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_FSL_DDR_INTERACTIVE #ifdef CONFIG_P1020MBG #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G diff --git a/include/mpc86xx.h b/include/mpc86xx.h index eb85d60cad..31e83f2cc9 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -84,6 +84,7 @@ static __inline__ unsigned long get_l2cr (void) } void setup_ddr_bat(phys_addr_t dram_size); +extern void setup_bats(void); #endif /* _ASMLANGUAGE */ #endif /* __MPC86xx_H__ */ |
