diff options
58 files changed, 1340 insertions, 1147 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 9734b1d095..48db504dad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -36,6 +36,7 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com> mecp5200 MPC5200 pf5200 MPC5200 + caddy2 MPC8349 vme8349 MPC8349 CPCI750 PPC750FX/GX @@ -358,10 +358,12 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ + caddy2 \ kmeter1 \ MPC8313ERDB_33 \ MPC8313ERDB_NAND_66 \ MPC8315ERDB \ + MPC8315ERDB_NAND \ MPC8323ERDB \ MPC832XEMDS \ MPC832XEMDS_ATM \ @@ -2261,8 +2261,12 @@ MPC8313ERDB_NAND_66_config: unconfig echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \ fi ; +MPC8315ERDB_NAND_config \ MPC8315ERDB_config: unconfig - @$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale + @if [ "$(findstring _NAND_,$@)" ] ; then \ + ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \ + fi ; + @$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale MPC8323ERDB_config: unconfig @$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale @@ -2396,8 +2400,9 @@ SIMPC8313_SP_config: unconfig TQM834x_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc +caddy2_config \ vme8349_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd + @$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd ######################################################################### ## MPC85xx Systems diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index a220ad4d7a..da6cf47433 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -170,22 +170,26 @@ static struct pci_controller pci2_hose; static struct pci_controller pcie1_hose; #endif -int first_free_busno=0; - -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */ - gur->clkocr |= MPC85xx_ATUM_CLKOCR; + setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR); if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) @@ -199,145 +203,79 @@ pci_init_board(void) } #ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE2, + pci_set_region(&pcie1_hose.regions[0], + CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie1_hose.region_count = 1; +#endif + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); - uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ + pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - (uint)pci - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); + pci_info[num].regs); - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { - printf (" PCI1: disabled\n"); + printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCI2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; - struct pci_controller *hose = &pci2_hose; - struct pci_region *r = hose->regions; - if (!(devdisr & MPC85xx_DEVDISR_PCI2)) { - pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BASE, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, - PCI_REGION_MEM); + SET_STD_PCI_INFO(pci_info[num], 2); + pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs); - pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BASE, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + puts (" PCI2\n"); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI2: disabled\n"); } -} + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI2; + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif } diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c index d15203c145..94fd32a6fa 100644 --- a/board/esd/vme8349/pci.c +++ b/board/esd/vme8349/pci.c @@ -2,6 +2,9 @@ * pci.c -- esd VME8349 PCI board support. * Copyright (c) 2006 Wind River Systems, Inc. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (c) 2009 esd gmbh. + * + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> * * Based on MPC8349 PCI support but w/o PIB related code. * @@ -32,6 +35,7 @@ #include <pci.h> #include <i2c.h> #include <asm/fsl_i2c.h> +#include "vme8349pin.h" DECLARE_GLOBAL_DATA_PTR; @@ -93,17 +97,22 @@ pci_init_board(void) udelay(2000); /* - * Assert/deassert PCI reset + * Assert/deassert VME reset */ - setbits_be32(&immr->gpio[0].dat, 0x00800000); - setbits_be32(&immr->gpio[0].dir, 0x00800000); - setbits_be32(&immr->gpio[1].dir, 0x08800000); + clrsetbits_be32(&immr->gpio[1].dat, + GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N, + GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N); + setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N | + GPIO2_TSI_POWERUP_RESET_N | + GPIO2_VME_RESET_N | + GPIO2_L_RESET_EN_N); + clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON); udelay(200); - setbits_be32(&immr->gpio[1].dat, 0x08000000); + setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N); udelay(200); - setbits_be32(&immr->gpio[1].dat, 0x08800000); + setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N); udelay(600000); - clrbits_be32(&immr->gpio[1].dat, 0x00100000); + clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N); /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; @@ -114,6 +123,14 @@ pci_init_board(void) udelay(2000); - if (monarch == 0) + if (monarch == 0) { mpc83xx_pci_init(1, reg, 0); + } else { + /* + * Release PCI RST Output signal + */ + out_be32(&immr->pci_ctrl[0].gcr, 0); + udelay(2000); + out_be32(&immr->pci_ctrl[0].gcr, 1); + } } diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index e3bc15112d..b0ebad72b2 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -38,63 +38,13 @@ #endif #include <asm/io.h> #include <asm/mmu.h> +#include <spd.h> +#include <spd_sdram.h> +#include <i2c.h> +#include <netdev.h> void ddr_enable_ecc(unsigned int dram_size); -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - -#if (CONFIG_SYS_DDR_SIZE == 512) - im->ddr.csbnds[0].csbnds = 0x0000001f; -#else -#warning Currently any DDR size other than 512MiB is not supported -#endif - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000; - - /* currently we use only one CS, so disable the other banks */ - im->ddr.csbnds[1].csbnds = 0x00000000; - im->ddr.csbnds[2].csbnds = 0x00000000; - im->ddr.csbnds[3].csbnds = 0x00000000; - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[2] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - sync(); - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} - phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -103,10 +53,10 @@ phys_size_t initdram(int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - /* DDR SDRAM - Main SODIMM */ + /* DDR SDRAM - Main memory */ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); + msize = spd_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* @@ -124,17 +74,148 @@ phys_size_t initdram(int board_type) int checkboard(void) { - puts("Board: esd VME8349\n"); +#ifdef VME_CADDY2 + puts("Board: esd VME-CADDY/2\n"); +#else + puts("Board: esd VME-CPU/8349\n"); +#endif return 0; } +#ifdef VME_CADDY2 +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif } #endif + +int misc_init_r() +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0); + + return 0; +} + +/* + * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 + * and VME-CADDY/2) have different SDRAM configurations. + */ +#ifdef VME_CADDY2 +#define SMALL_RAM 0xff +#define LARGE_RAM 0x00 +#else +#define SMALL_RAM 0x00 +#define LARGE_RAM 0xff +#endif + +#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM)) + +static spd_eeprom_t default_spd_eeprom = { + SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */ + SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */ + SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */ + SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */ + SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */ + SPD_VAL(0x00, 0x00), /* 05 */ + SPD_VAL(0x40, 0x40), /* 06 */ + SPD_VAL(0x00, 0x00), /* 07 */ + SPD_VAL(0x05, 0x05), /* 08 */ + SPD_VAL(0x30, 0x30), /* 09 */ + SPD_VAL(0x45, 0x45), /* 10 */ + SPD_VAL(0x02, 0x02), /* 11 ecc used */ + SPD_VAL(0x82, 0x82), /* 12 */ + SPD_VAL(0x10, 0x10), /* 13 */ + SPD_VAL(0x08, 0x08), /* 14 */ + SPD_VAL(0x00, 0x00), /* 15 */ + SPD_VAL(0x0c, 0x0c), /* 16 */ + SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */ + SPD_VAL(0x38, 0x38), /* 18 */ + SPD_VAL(0x00, 0x00), /* 19 */ + SPD_VAL(0x02, 0x02), /* 20 */ + SPD_VAL(0x00, 0x00), /* 21 */ + SPD_VAL(0x03, 0x03), /* 22 */ + SPD_VAL(0x3d, 0x3d), /* 23 */ + SPD_VAL(0x45, 0x45), /* 24 */ + SPD_VAL(0x50, 0x50), /* 25 */ + SPD_VAL(0x45, 0x45), /* 26 */ + SPD_VAL(0x3c, 0x3c), /* 27 */ + SPD_VAL(0x28, 0x28), /* 28 */ + SPD_VAL(0x3c, 0x3c), /* 29 */ + SPD_VAL(0x2d, 0x2d), /* 30 */ + SPD_VAL(0x20, 0x80), /* 31 */ + SPD_VAL(0x20, 0x20), /* 32 */ + SPD_VAL(0x27, 0x27), /* 33 */ + SPD_VAL(0x10, 0x10), /* 34 */ + SPD_VAL(0x17, 0x17), /* 35 */ + SPD_VAL(0x3c, 0x3c), /* 36 */ + SPD_VAL(0x1e, 0x1e), /* 37 */ + SPD_VAL(0x1e, 0x1e), /* 38 */ + SPD_VAL(0x00, 0x00), /* 39 */ + SPD_VAL(0x00, 0x06), /* 40 */ + SPD_VAL(0x37, 0x37), /* 41 */ + SPD_VAL(0x4b, 0x7f), /* 42 */ + SPD_VAL(0x80, 0x80), /* 43 */ + SPD_VAL(0x18, 0x18), /* 44 */ + SPD_VAL(0x22, 0x22), /* 45 */ + SPD_VAL(0x00, 0x00), /* 46 */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + SPD_VAL(0x10, 0x10), /* 62 */ + SPD_VAL(0x7e, 0x1d), /* 63 */ + { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, + SPD_VAL(0x00, 0x00), /* 72 */ +#ifdef VME_CADDY2 + { "vme-caddy/2 ram " } +#else + { "vme-cpu/2 ram " } +#endif +}; + +int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int old_bus = I2C_GET_BUS(); + unsigned int l, sum; + int valid = 0; + + I2C_SET_BUS(0); + + if (i2c_read(chip, addr, alen, buffer, len) == 0) + if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) { + sum = 0; + for (l = 0; l < 63; l++) + sum = (sum + buffer[l]) & 0xff; + if (sum == buffer[63]) + valid = 1; + else + printf("Invalid checksum in EEPROM %02x %02x\n", + sum, buffer[63]); + } + + if (valid == 0) { + memcpy(buffer, (void *)&default_spd_eeprom, len); + sum = 0; + for (l = 0; l < 63; l++) + sum = (sum + buffer[l]) & 0xff; + if (sum != buffer[63]) + printf("Invalid checksum in FLASH %02x %02x\n", + sum, buffer[63]); + buffer[63] = sum; + } + + I2C_SET_BUS(old_bus); + + return 0; +} diff --git a/board/esd/vme8349/vme8349pin.h b/board/esd/vme8349/vme8349pin.h new file mode 100644 index 0000000000..d1fd1b203f --- /dev/null +++ b/board/esd/vme8349/vme8349pin.h @@ -0,0 +1,36 @@ +/* + * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition. + * Copyright (c) 2009 esd gmbh. + * + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __VME8349PIN_H__ +#define __VME8349PIN_H__ + +#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */ +#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */ +#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */ +#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */ +#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/ + +#endif /* of ifndef __VME8349PIN_H__ */ diff --git a/board/freescale/mpc8315erdb/config.mk b/board/freescale/mpc8315erdb/config.mk index f76826495e..bf972fbe56 100644 --- a/board/freescale/mpc8315erdb/config.mk +++ b/board/freescale/mpc8315erdb/config.mk @@ -1 +1,9 @@ +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +endif +endif + +ifndef TEXT_BASE TEXT_BASE = 0xFE000000 +endif diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index dea4d6fe7a..d5e71dc522 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -32,6 +32,8 @@ #include <mpc83xx.h> #include <netdev.h> #include <asm/io.h> +#include <ns16550.h> +#include <nand.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,6 +47,8 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_NAND_SPL + static u8 read_board_info(void) { u8 val8; @@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); /* Initialize TSECs first */ return pci_eth_init(bis); } + +#else /* CONFIG_NAND_SPL */ + +int checkboard(void) +{ + puts("Board: Freescale MPC8315ERDB\n"); + return 0; +} + +void board_init_f(ulong bootflag) +{ + board_early_init_f(); + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); +} + +#endif /* CONFIG_NAND_SPL */ diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index ead7b1e0de..fe8ec1eab8 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -54,6 +54,7 @@ static void resume_from_sleep(void) * This is useful for faster booting in configs where the RAM is unlikely * to be changed, or for things like NAND booting where space is tight. */ +#ifndef CONFIG_SYS_RAMBOOT static long fixed_sdram(void) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -68,7 +69,7 @@ static long fixed_sdram(void) * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], * or the DDR2 controller may fail to initialize correctly. */ - udelay(50000); + __udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; @@ -100,6 +101,12 @@ static long fixed_sdram(void) return msize; } +#else +static long fixed_sdram(void) +{ + return CONFIG_SYS_DDR_SIZE * 1024 * 1024; +} +#endif /* CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) { diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index da729166b1..f8292cf378 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -189,20 +189,26 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno=0; - -void -pci_init_board(void) +#ifdef CONFIG_PCI +void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint sdrs2_io_sel = - (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[4]; + u32 devdisr, pordevsr, io_sel, sdrs2_io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; - debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ - host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; + + debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n", + devdisr, sdrs2_io_sel, io_sel); if (sdrs2_io_sel == 7) printf(" Serdes2 disalbed\n"); @@ -212,233 +218,102 @@ pci_init_board(void) } else if (sdrs2_io_sel == 6) printf(" eTSEC1 is in sgmii mode.\n"); + puts("\n"); #ifdef CONFIG_PCIE3 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - struct pci_controller *hose = &pcie3_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); + printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCIE3 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); } else { printf (" PCIE3: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS2, - CONFIG_SYS_PCIE1_MEM_PHYS2, - CONFIG_SYS_PCIE1_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCIE2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS2, - CONFIG_SYS_PCIE2_MEM_PHYS2, - CONFIG_SYS_PCIE2_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf (" PCIE2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); } else { printf (" PCIE2: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); - uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ - uint pci_32 = 1; - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - (uint)pci - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCI1_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS2, - CONFIG_SYS_PCI1_MEM_PHYS2, - CONFIG_SYS_PCI1_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; + pci_info[num].regs); - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif } +#endif int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 1; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 244a197049..35a8063c9b 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -101,18 +101,23 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno=0; - -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct fsl_pci_info pci_info[4]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) @@ -120,55 +125,29 @@ pci_init_board(void) if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf (" eTSEC3 is in sgmii mode.\n"); } + puts("\n"); #ifdef CONFIG_PCIE3 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - struct pci_controller *hose = &pcie3_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE3 connected to ULI as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, + pci_set_region(&pcie3_hose.regions[0], CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCIE3 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie3_hose.region_count = 1; +#endif + printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); /* * Activate ULI1575 legacy chip by performing a fake @@ -178,187 +157,99 @@ pci_init_board(void) } else { printf (" PCIE3: disabled\n"); } - - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, + pci_set_region(&pcie1_hose.regions[0], CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie1_hose.region_count = 1; +#endif + printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCIE2 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, + pci_set_region(&pcie2_hose.regions[0], CONFIG_SYS_PCIE2_MEM_BUS2, CONFIG_SYS_PCIE2_MEM_PHYS2, CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf (" PCIE2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie2_hose.region_count = 1; +#endif + printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); } else { printf (" PCIE2: disabled\n"); } - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif - #ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); - uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ - uint pci_32 = 1; - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - (uint)pci - ); + pci_info[num].regs); - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS2, - CONFIG_SYS_PCIE3_MEM_PHYS2, - CONFIG_SYS_PCIE3_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif } diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 73e7c21093..38cbc8bac1 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -262,62 +262,47 @@ static struct pci_controller pci2_hose; static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno=0; - -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - - -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; + struct fsl_pci_info pci_info[4]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + int pcie_ep, pcie_configured; - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", +#ifdef CONFIG_PCI1 + pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + pci_arb ? "arbiter" : "external-arbiter", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); + #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { + if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); @@ -330,14 +315,15 @@ pci_init_board(void) } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCI2 { - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { printf (" PCI2: 32 bit, 66 MHz, %s\n", @@ -347,60 +333,29 @@ pci_init_board(void) } } #else - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif /* CONFIG_PCI2 */ #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } - } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif - } int last_stage_init(void) diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index e2dc69ea93..60e22de4b9 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -311,8 +311,6 @@ static struct pci_controller pci1_hose = { static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno = 0; - /* * pib_init() -- Initialize the PCA9555 IO expander on the PIB board */ @@ -356,117 +354,72 @@ pib_init(void) } #ifdef CONFIG_PCI -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - -#ifdef CONFIG_PCI1 -{ - pib_init(); - - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; - uint pci_32 = 1; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + int pcie_ep, pcie_configured; - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint pci_speed = 66666000; + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", +#ifdef CONFIG_PCI1 + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno = hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + pci_arb ? "arbiter" : "external-arbiter", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index cdd7813011..56854caa8d 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -437,6 +437,11 @@ int board_mmc_init(bd_t *bd) console_assign(stdin, "eserial1"); printf("Switched to UART1 (initial log has been printed to " "UART0).\n"); + + clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, + PLPPAR1_ESDHC_4BITS_VAL); + clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, + PLPDIR1_ESDHC_4BITS_VAL); bcsr6 |= BCSR6_SD_CARD_4BITS; } else { printf("should be disabled.\n"); @@ -483,6 +488,15 @@ static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) break; } } + + if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { + off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); + if (off < 0) { + printf("WARNING: could not find esdhc node\n"); + return; + } + fdt_delprop(blob, off, "sdhci,1-bit-only"); + } } #else static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} @@ -514,77 +528,43 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno = 0; - #ifdef CONFIG_PCI -void -pci_init_board(void) -{ - volatile ccsr_gur_t *gur; - uint io_sel; - uint host_agent; - - gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - -#ifdef CONFIG_PCIE1 +void pci_init_board(void) { - volatile ccsr_fsl_pci_t *pci; - struct pci_controller *hose; - int pcie_ep; - struct pci_region *r; - int pcie_configured; - - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - hose = &pcie1_hose; - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - r = hose->regions; - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[1]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; - hose->region_count = r - hose->regions; + int pcie_ep, pcie_configured; - hose->first_busno=first_free_busno; + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - first_free_busno=hose->last_busno+1; +#ifdef CONFIG_PCIE1 + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif + } #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 933dd127ec..64e164b1a0 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Freescale Semiconductor, Inc. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -165,7 +165,7 @@ void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel, host_agent, temp32; + u32 devdisr, pordevsr, io_sel, temp32; int first_free_busno = 0; int num = 0; @@ -174,10 +174,8 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) printf (" eTSEC1 is in sgmii mode.\n"); @@ -190,11 +188,11 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE3 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -222,11 +220,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -242,11 +240,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -266,7 +264,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index d832f89742..6a2a0b57f5 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index f42c316722..2d4b9addb6 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -224,158 +224,83 @@ static struct pci_controller pcie1_hose; static struct pci_controller pcie2_hose; #endif -int first_free_busno = 0; - void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) - >> MPC8610_PORDEVSR_IO_SEL_SHIFT; - uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) - >> MPC8610_PORBMSR_HA_SHIFT; + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; + + int pci_agent, pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL) + >> MPC8610_PORDEVSR_IO_SEL_SHIFT; - printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { - printf(" PCIe 1 connected to Uli as %s (base address %x)\n", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) - pci->pme_msg_det = 0xffffffff; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno + 1; - printf(" PCI-Express 1 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - - } else - puts(" PCI-Express 1: Disabled\n"); - } -#else - puts("PCI-Express 1: Disabled\n"); -#endif /* CONFIG_PCIE1 */ + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf (" PCIE1: disabled\n"); + } + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */ +#endif #ifdef CONFIG_PCIE2 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - struct pci_region *r = hose->regions; - - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { - printf(" PCI-Express 2 connected to slot as %s" \ - " (base address %x)\n", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) - pci->pme_msg_det = 0xffffffff; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno + 1; - printf(" PCI-Express 2 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - } else - puts(" PCI-Express 2: Disabled\n"); - } -#else - puts("PCI-Express 2: Disabled\n"); -#endif /* CONFIG_PCIE2 */ + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf (" PCIE2 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf (" PCIE2: disabled\n"); + } + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */ +#endif #ifdef CONFIG_PCI1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); - struct pci_region *r = hose->regions; - - if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { + if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf(" PCI connected to PCI slots as %s" \ - " (base address %x)\n", + " (base address %lx)\n", pci_agent ? "Agent" : "Host", - (uint)pci); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno + 1; - printf(" PCI on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); + } else { + printf (" PCI: disabled\n"); + } - } else - puts(" PCI: Disabled\n"); - } -#endif /* CONFIG_PCI1 */ + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ +#endif } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 4c03468a24..3af660e775 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -131,7 +131,7 @@ int checkboard (void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 4c08f9efa0..6fd6963f0c 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -43,7 +43,7 @@ void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[2]; - u32 devdisr, pordevsr, io_sel, host_agent; + u32 devdisr, pordevsr, io_sel; int first_free_busno = 0; int num = 0; @@ -52,21 +52,19 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); puts("\n"); #ifdef CONFIG_PCIE2 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -81,11 +79,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 0009913eaa..93d0bf7bc7 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index e38c0145ed..599caa235d 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -197,7 +197,7 @@ void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel, host_agent; + u32 devdisr, pordevsr, io_sel; int first_free_busno = 0; int num = 0; @@ -206,10 +206,8 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf(" eTSEC2 is in sgmii mode.\n"); @@ -218,11 +216,11 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE2 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -258,11 +256,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE3 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -277,11 +275,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -300,7 +298,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c index b2e562aeb1..36ad086d08 100644 --- a/board/freescale/p2020ds/tlb.c +++ b/board/freescale/p2020ds/tlb.c @@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 3931ec5036..aa7827e1ec 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -549,7 +549,6 @@ static inline void init_pci1(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCI1 - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; @@ -561,7 +560,7 @@ static inline void init_pci1(void) /* PORPLLSR[16] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); + int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR); uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ @@ -626,14 +625,15 @@ static inline void init_pcie1(void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCIE1 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_ep; struct pci_region *r = hose->regions; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR); + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("PCIe: %s, base address %x", pcie_ep ? "End point" : "Root complex", (uint)pci); diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 0d6a5fec97..75b45222bd 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -70,6 +70,12 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | #endif +#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ + (ACR_APARK << ACR_APARK_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ + (ACR_PARKM << ACR_PARKM_SHIFT) | +#endif 0; __be32 acr_val = #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ @@ -78,6 +84,12 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | #endif +#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ + (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ + (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) | +#endif 0; __be32 spcr_mask = #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 0f611804a0..44aaa9abc2 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -29,6 +29,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <i2c.h> #include <spd.h> #include <asm/mmu.h> @@ -150,6 +151,14 @@ long int spd_sdram() unsigned int ddrc_ecc_enable; unsigned int pvr = get_pvr(); + /* + * First disable the memory controller (could be enabled + * by the debugger) + */ + clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); + sync(); + isync(); + /* Read SPD parameters with I2C */ CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0041a60df9..e0126d331a 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -246,6 +246,7 @@ void cpu_init_f (void) #ifdef CONFIG_FSL_CORENET corenet_tb_init(); #endif + init_used_tlb_cams(); } @@ -357,6 +358,11 @@ int cpu_init_r(void) while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + mtspr(SPRN_L2CSR1, (32 + 1)); +#endif + /* enable the cache */ mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index de2dcac816..af0e78e07f 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -197,6 +197,15 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } +#ifdef CONFIG_SYS_CACHE_STASHING + { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + if (reg) + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg * 2) + 32 + 1); + } +#endif + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); fdt_setprop_cell(blob, l2_off, "cache-size", size); @@ -252,6 +261,15 @@ static inline void ft_fixup_cache(void *blob) fdt_setprop_cell(blob, off, "d-cache-size", dsize); fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); +#ifdef CONFIG_SYS_CACHE_STASHING + { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + if (reg) + fdt_setprop_cell(blob, off, "cache-stash-id", + (*reg * 2) + 32 + 0); + } +#endif + /* i-side config */ isize = (l1cfg1 & 0x7ff) * 1024; inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; @@ -279,6 +297,40 @@ void fdt_add_enet_stashing(void *fdt) do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); } +#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) +static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq) +{ + const char *path = fdt_get_alias(blob, alias); + + int off = fdt_path_offset(blob, path); + + if (off >= 0) { + off = fdt_setprop_cell(blob, off, "clock-frequency", freq); + if (off > 0) + printf("WARNING enable to set clock-frequency " + "for %s: %s\n", alias, fdt_strerror(off)); + } +} + +static void ft_fixup_dpaa_clks(void *blob) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]); + +#if (CONFIG_SYS_NUM_FMAN == 2) + ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]); +#endif + +#ifdef CONFIG_SYS_DPAA_PME + ft_fixup_clks(blob, "pme", sysinfo.freqPME); +#endif +} +#else +#define ft_fixup_dpaa_clks(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -342,4 +394,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif + + ft_fixup_dpaa_clks(blob); } diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 7626eb8e72..6530cb176b 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -165,6 +165,9 @@ static void plat_mp_up(unsigned long bootpg) e = find_law(bootpg); out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); + /* readback to sync write */ + in_be32(&ccm->bstrar); + /* disable time base at the platform */ out_be32(&rcpm->ctbenrl, cpu_up_mask); @@ -309,7 +312,7 @@ void setup_mp(void) disable_tlb(i); set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 433ff02544..00c4c547fd 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -99,6 +99,13 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8 +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync @@ -110,6 +117,12 @@ __secondary_start_page: and. r1,r3,r2 bne 1b +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + addi r3,r8,1 + mtspr SPRN_L2CSR1,r3 +#endif + lis r3,CONFIG_SYS_INIT_L2CSR0@h ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 @@ -153,8 +166,8 @@ __secondary_start_page: lis r11,(MAS1_VALID|MAS1_IPROT)@h ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr SPRN_MAS1,r11 - oris r11,r13,(MAS2_I)@h - ori r11,r13,(MAS2_I)@l + oris r11,r13,(MAS2_I|MAS2_G)@h + ori r11,r13,(MAS2_I|MAS2_G)@l mtspr SPRN_MAS2,r11 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 7959082404..2103e2edf1 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else sysInfo->freqPME = sysInfo->freqSystemBus / 2; + else + sysInfo->freqPME = freqCC_PLL[2] / 2; #endif #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + else + sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + else + sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; #endif #endif diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 6a865283d4..7e60e67c3a 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -102,6 +102,12 @@ _start_e500: * */ +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + li r2,(32 + 0) + mtspr L1CSR2,r2 +#endif + lis r2,L1CSR0_CPE@H /* enable parity */ ori r2,r2,L1CSR0_DCE mtspr L1CSR0,r2 /* enable L1 Dcache */ diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index ea5deb2971..b3037aceaf 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -56,12 +56,74 @@ void init_tlbs(void) } #ifndef CONFIG_NAND_SPL +static inline void use_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->used_tlb_cams[i] |= (1 << bit); +} + +static inline void free_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->used_tlb_cams[i] &= ~(1 << bit); +} + +void init_used_tlb_cams(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) + gd->used_tlb_cams[i] = 0; + + /* walk all the entries */ + for (i = 0; i < num_cam; i++) { + u32 _mas1; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); + + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + /* if the entry isn't valid skip it */ + if ((_mas1 & MAS1_VALID)) + use_tlb_cam(i); + } +} + +int find_free_tlbcam(void) +{ + int i; + u32 idx; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) { + idx = ffz(gd->used_tlb_cams[i]); + + if (idx != 32) + break; + } + + idx += i * 32; + + if (idx >= CONFIG_SYS_NUM_TLBCAMS) + return -1; + + return idx; +} + void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, u8 ts, u8 esel, u8 tsize, u8 iprot) { u32 _mas0, _mas1, _mas2, _mas3, _mas7; + if (tlb == 1) + use_tlb_cam(esel); + _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); _mas2 = FSL_BOOKE_MAS2(epn, wimge); @@ -80,6 +142,8 @@ void disable_tlb(u8 esel) { u32 _mas0, _mas1, _mas2, _mas3, _mas7; + free_tlb_cam(esel); + _mas0 = FSL_BOOKE_MAS0(1, esel, 0); _mas1 = 0; _mas2 = 0; @@ -163,14 +227,10 @@ void init_addr_map(void) } #endif -#ifndef CONFIG_SYS_DDR_TLB_START -#define CONFIG_SYS_DDR_TLB_START 8 -#endif - unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { + int i; unsigned int tlb_size; - unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20; @@ -180,10 +240,14 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) /* Convert (4^max) kB to (2^max) bytes */ max_cam = max_cam * 2 + 10; - for (; size && ram_tlb_index < 16; ram_tlb_index++) { + for (i = 0; size && i < 8; i++) { + int ram_tlb_index = find_free_tlbcam(); u32 camsize = __ilog2_u64(size) & ~1U; u32 align = __ilog2(ram_tlb_address) & ~1U; + if (ram_tlb_index == -1) + break; + if (align == -2) align = max_cam; if (camsize > align) camsize = align; diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 2505041450..adc4f6ee37 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -188,12 +188,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) * The DDR3 spec has not tXARD, * we use the tXP instead of it. * tXP=max(3nCK, 7.5ns) for DDR3. - * we use the tXP=6 * spec has not the tAXPD, we use * tAXPD=8, need design to confirm. */ - act_pd_exit_mclk = 6; - pre_pd_exit_mclk = 6; + int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + act_pd_exit_mclk = picos_to_mclk(tXP); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 8; tmrd_mclk = 4; #else /* CONFIG_FSL_DDR2 */ @@ -575,18 +576,22 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr) +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ #if defined(CONFIG_FSL_DDR3) - unsigned int rtt_wr = 2; /* 120 ohm Rtt_WR */ + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ unsigned int cwl = compute_cas_write_latency() - 5; unsigned int pasr = 0; /* partial array self refresh disable */ + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + esdmode2 = (0 | ((rtt_wr & 0x3) << 9) | ((srt & 0x1) << 7) @@ -1001,8 +1006,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) } /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, - unsigned int wrlvl_en) +static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, + const memctl_options_t *popts) { /* * First DQS pulse rising edge after margining mode @@ -1029,8 +1034,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, /* tWL_DQSEN min = 25 nCK, we set it 32 */ wrlvl_dqsen = 0x5; /* - * Write leveling sample time at least need 14 clocks - * due to tWLO = 9, we set it 15 clocks + * Write leveling sample time at least need 6 clocks + * higher than tWLO to allow enough time for progagation + * delay and sampling the prime data bits. */ wrlvl_smpl = 0xf; /* @@ -1043,9 +1049,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, * Write leveling start time * The value use for the DQS_ADJUST for the first sample * when write leveling is enabled. - * we set it 1 clock delay */ wrlvl_start = 0x8; + /* + * Override the write leveling sample and start time + * according to specific board + */ + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; + } } ddr->ddr_wrlvl_cntl = (0 @@ -1184,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* Don't set up boundaries for other CS * other than CS0, if bank interleaving * is enabled and not CS2+CS3 interleaved. + * But we need to set the ODT_RD_CFG and + * ODT_WR_CFG for CS1_CONFIG here. */ + set_csn_config(i, ddr, popts, dimm_params); break; } @@ -1321,7 +1337,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_cfg_2(ddr, popts); set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency); - set_ddr_sdram_mode_2(ddr); + set_ddr_sdram_mode_2(ddr, popts); set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); @@ -1331,7 +1347,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_5(ddr); set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en); + set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); set_ddr_sr_cntr(ddr, sr_it); diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 2e030c11a3..3dcd33ddf2 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; + popts->wrlvl_override = 0; #endif /* diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c index 9c7d92c4d9..d53781b62b 100644 --- a/cpu/mpc8xxx/pci_cfg.c +++ b/cpu/mpc8xxx/pci_cfg.c @@ -25,19 +25,14 @@ #include <pci.h> struct pci_info { - u16 agent; u16 cfg; }; -/* The agent field is a bit mask in which each bit represents the value of - * cfg_host_agt[] signal and the bit is set of the given interface would be - * in agent/end-point mode for the given interface. - * - * The same idea is true of the cfg field. The bit will be set if the - * interface would be enabled based on the value of cfg_IO_ports[] signal +/* The cfg field is a bit mask in which each bit represents the value of + * cfg_IO_ports[] signal and the bit is set if the interface would be + * enabled based on the value of cfg_IO_ports[] signal * * On MPC86xx/PQ3 based systems: - * we extract cfg_host_agt from GUTS register PORBMSR * we extract cfg_IO_ports from GUTS register PORDEVSR * * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems @@ -48,7 +43,6 @@ struct pci_info { static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 0) | (1 << 2), .cfg = 0, }, }; @@ -56,7 +50,6 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 0), .cfg = 0, }, }; @@ -64,19 +57,15 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 5), .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 3), .cfg = (1 << 5) | (1 << 7), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 1), .cfg = (1 << 7), }, }; @@ -84,20 +73,16 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 5), .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 3), .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 1), .cfg = (1 << 6) | (1 << 7), }, }; @@ -105,16 +90,13 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI_1] = { - .agent = (1 << 4) | (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCI_2] = { - .agent = (1 << 4) | (1 << 6), .cfg = 0, }, /* PCI_2 is always host and we dont use iosel to determine enable/disable */ [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 2), .cfg = (1 << 3) | (1 << 4) | (1 << 7), }, }; @@ -122,11 +104,9 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 0) | (1 << 4) | (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 2) | (1 << 4), .cfg = (1 << 3) | (1 << 4) | (1 << 7), }, }; @@ -134,7 +114,6 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 6), .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 0xc) | (1 << 0xf), }, @@ -143,16 +122,13 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), .cfg = (1 << 2) | (1 << 3) | (1 << 7) | (1 << 0xb) | (1 << 0xc) | (1 << 0xf), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), .cfg = (1 << 3) | (1 << 7), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), .cfg = (1 << 7), }, }; @@ -160,15 +136,12 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI_1] = { - .agent = (1 << 4) | (1 << 5) | (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 2) | (1 << 5), .cfg = (1 << 1) | (1 << 4), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 1) | (1 << 4), .cfg = (1 << 0) | (1 << 4), }, }; @@ -176,7 +149,6 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = 0, /* we dont use agent on 8641 */ .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 0xe) | (1 << 0xf), }, @@ -185,11 +157,9 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 1), .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 2), .cfg = (1 << 0xe), }, }; @@ -197,29 +167,24 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | (1 << 0xd) | (1 << 0xe) | (1 << 0xf), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), .cfg = (1 << 2) | (1 << 0xe), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), .cfg = (1 << 2) | (1 << 4), }, }; +#elif defined(CONFIG_FSL_CORENET) #else #error Need to define pci_config_info for processor #endif -int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent) -{ - return ((1 << host_agent) & pci_config_info[trgt].agent); -} - +#ifndef CONFIG_FSL_CORENET int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) { return ((1 << io_sel) & pci_config_info[trgt].cfg); } +#endif diff --git a/doc/README.mpc8315erdb b/doc/README.mpc8315erdb index 7d476d0018..b32132d053 100644 --- a/doc/README.mpc8315erdb +++ b/doc/README.mpc8315erdb @@ -15,6 +15,18 @@ Freescale MPC8315ERDB Board 4321 4321 (where the '*' indicates the position of the tab of the switch.) + To boot the image at the beginning of NAND flash, use these + DIP switch settings for S3 S4: + + +------+ +------+ + | * | | *** | + | *** | | * | + +------+ ON +------+ ON + 4321 4321 + (where the '*' indicates the position of the tab of the switch.) + + When booting from NAND, use u-boot-nand.bin, not u-boot.bin. + 2. Memory Map The memory map looks like this: @@ -26,6 +38,9 @@ Freescale MPC8315ERDB Board 0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M + When booting from NAND, NAND flash is CS0 and NOR flash + is CS1. + 3. Definitions 3.1 Explanation of NEW definitions in: @@ -43,13 +58,15 @@ Freescale MPC8315ERDB Board export CROSS_COMPILE=your-cross-compiler-prefix- make distclean - make MPC8315ERDB_config + make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin) make all 5. Downloading and Flashing Images 5.1 Reflash U-boot Image using U-boot + NOR flash: + tftp 40000 u-boot.bin protect off all erase fe000000 fe1fffff @@ -60,6 +77,15 @@ Freescale MPC8315ERDB Board You have to supply the correct byte count with 'xxxx' from the TFTP result log. + NAND flash: + + =>tftpboot $loadaddr <filename> + =>nand erase 0 0x80000 + =>nand write $loadaddr 0 0x80000 + + ...where 0x80000 is the filesize rounded up to + the next 0x20000 increment. + 5.2 Downloading and Booting Linux Kernel Ensure that all networking-related environment variables are set @@ -76,5 +102,4 @@ Freescale MPC8315ERDB Board 6 Notes - Booting from NAND flash is not yet supported. The console baudrate for MPC8315ERDB is 115200bps. diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3f74118dbe..d8b6619ae0 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -80,7 +80,7 @@ static struct tsec_info_struct tsec_info[] = { #ifdef CONFIG_MPC85XX_FEC { .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), - .miiregs = (tsec_t *)(TSEC_BASE_ADDR), + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS @@ -133,6 +133,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs = tsec_info->miiregs; + priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; priv->flags = tsec_info->flags; @@ -219,7 +220,7 @@ int tsec_init(struct eth_device *dev, bd_t * bd) } /* Writes the given phy's reg with value, using the specified MDIO regs */ -static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, +static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr, uint reg, uint value) { int timeout = 1000000; @@ -242,7 +243,7 @@ static void tsec_local_mdio_write(volatile tsec_t *phyregs, uint addr, * notvalid bit cleared), and the bus to cease activity (miimind * busy bit cleared), and then returns the value */ -uint tsec_local_mdio_read(volatile tsec_t *phyregs, uint phyid, uint regnum) +uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs, uint phyid, uint regnum) { uint value; @@ -287,11 +288,11 @@ static void tsec_configure_serdes(struct tsec_private *priv) { /* Access TBI PHY registers at given TSEC register offset as opposed to the * register offset used for external PHY accesses */ - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_ANA, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA, TBIANA_SETTINGS); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_TBICON, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON, TBICON_CLK_SELECT); - tsec_local_mdio_write(priv->regs, priv->regs->tbipa, TBI_CR, + tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR, TBICR_SETTINGS); } @@ -303,12 +304,10 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_info *curphy; - volatile tsec_t *phyregs = priv->phyregs; volatile tsec_t *regs = priv->regs; /* Assign a Physical address to the TBI */ regs->tbipa = CONFIG_SYS_TBIPA_VALUE; - phyregs->tbipa = CONFIG_SYS_TBIPA_VALUE; asm("sync"); /* Reset MII (due to new addresses) */ @@ -733,7 +732,7 @@ uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv) uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv) { uint phyid; - volatile tsec_t *regbase = priv->phyregs; + volatile tsec_mdio_t *regbase = priv->phyregs; int timeout = 1000000; for (phyid = 0; phyid < 4; phyid++) { @@ -1766,7 +1765,7 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) { int i; uint result; - volatile tsec_t *phyregs = priv->phyregs; + volatile tsec_mdio_t *phyregs = priv->phyregs; phyregs->miimcfg = MIIMCFG_RESET; diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 170cc257cd..fe57926d7e 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -86,6 +86,15 @@ static void set_inbound_window(volatile pit_t *pi, out_be32(&pi->piwar, flag | sz); } +int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; + + pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + + return fsl_is_pci_agent(hose); +} + static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, u64 out_lo, u8 pcie_cap, volatile pit_t *pi) diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index af0853b0d7..796707eaf7 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -57,6 +57,19 @@ #endif #endif +/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ +#if defined(CONFIG_TSEC_ENET) && \ + (defined(CONFIG_P1020) || defined(CONFIG_P1011)) +#define CONFIG_TSECV2 +#endif + +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500MC) +#define CONFIG_SYS_NUM_TLBCAMS 64 +#elif defined(CONFIG_E500) +#define CONFIG_SYS_NUM_TLBCAMS 16 +#endif + /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 69b857b41c..3216a50633 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -177,6 +177,11 @@ typedef struct memctl_options_s { unsigned int clk_adjust; /* */ unsigned int cpo_override; unsigned int write_data_delay; /* DQS adjust */ + + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int half_strength_driver_enable; unsigned int twoT_en; unsigned int threeT_en; @@ -187,6 +192,7 @@ typedef struct memctl_options_s { /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ /* Automatic self refresh */ unsigned int auto_self_refresh_en; diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index 31bb7545b5..34c56a259a 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -46,6 +46,8 @@ enum law_size { LAW_SIZE_32G, }; +#define law_size_bits(sz) (__ilog2_u64(sz) - 1) + #ifdef CONFIG_FSL_CORENET enum law_trgt_if { LAW_TRGT_IF_PCIE_1 = 0x00, @@ -78,6 +80,7 @@ enum law_trgt_if { LAW_TRGT_IF_CCSR = 0x08, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, + LAW_TRGT_IF_RIO_2 = 0x0d, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ }; diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index a5f72f5cd5..db61e7e9cb 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -1,4 +1,5 @@ -/* (C) Copyright 2007 Freescale Semiconductor, Inc. +/* + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,9 +23,9 @@ #include <asm/fsl_law.h> -int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent); int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); +int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 55e7e2066d..3f11918746 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { #if defined(CONFIG_FSL_LAW) u32 used_laws; #endif +#if defined(CONFIG_E500) + u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; +#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index c60a7d21c3..6b42a73f3f 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2009 Freescale Semiconductor, Inc. * * MPC83xx Internal Memory Map * @@ -868,4 +868,10 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) + +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_MDIO1_OFFSET 0x24000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 41942954b8..957ad76a79 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -6,6 +6,23 @@ * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __IMMAP_85xx__ @@ -1545,6 +1562,78 @@ typedef struct par_io { u8 res[8]; } par_io_t; +#ifdef CONFIG_SYS_FSL_CPC +/* + * Define a single offset that is the start of all the CPC register + * blocks - if there is more than one CPC, we expect these to be + * contiguous 4k regions + */ + +typedef struct cpc_corenet { + u32 cpccsr0; /* Config/status reg */ + u32 res1; + u32 cpccfg0; /* Configuration register */ + u32 res2; + u32 cpcewcr0; /* External Write reg 0 */ + u32 cpcewabr0; /* External write base reg 0 */ + u32 res3[2]; + u32 cpcewcr1; /* External Write reg 1 */ + u32 cpcewabr1; /* External write base reg 1 */ + u32 res4[54]; + u32 cpcsrcr1; /* SRAM control reg 1 */ + u32 cpcsrcr0; /* SRAM control reg 0 */ + u32 res5[62]; + struct { + u32 id; /* partition ID */ + u32 res; + u32 alloc; /* partition allocation */ + u32 way; /* partition way */ + } partition_regs[16]; + u32 res6[704]; + u32 cpcerrinjhi; /* Error injection high */ + u32 cpcerrinjlo; /* Error injection lo */ + u32 cpcerrinjctl; /* Error injection control */ + u32 res7[5]; + u32 cpccaptdatahi; /* capture data high */ + u32 cpccaptdatalo; /* capture data low */ + u32 cpcaptecc; /* capture ECC */ + u32 res8[5]; + u32 cpcerrdet; /* error detect */ + u32 cpcerrdis; /* error disable */ + u32 cpcerrinten; /* errir interrupt enable */ + u32 cpcerrattr; /* error attribute */ + u32 cpcerreaddr; /* error extended address */ + u32 cpcerraddr; /* error address */ + u32 cpcerrctl; /* error control */ + u32 res9[105]; /* pad out to 4k */ +} cpc_corenet_t; + +#define CPC_CSR0_CE 0x80000000 /* Cache Enable */ +#define CPC_CSR0_PE 0x40000000 /* Enable ECC */ +#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ +#define CPC_CSR0_WT 0x00080000 /* Write-through mode */ +#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ +#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ +#define CPC_CFG0_SZ_MASK 0x00003fff +#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) +#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) +#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) +#define CPC_SRCR1_SRBARU_MASK 0x0000ffff +#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ + & CPC_SRCR1_SRBARU_MASK) +#define CPC_SRCR0_SRBARL_MASK 0xffff8000 +#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) +#define CPC_SRCR0_INTLVEN 0x00000100 +#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 +#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 +#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 +#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 +#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 +#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a +#define CPC_SRCR0_SRAMEN 0x00000001 +#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#endif /* CONFIG_SYS_FSL_CPC */ + /* Global Utilities Block */ #ifdef CONFIG_FSL_CORENET typedef struct ccsr_gur { @@ -1847,17 +1936,86 @@ typedef struct ccsr_gur { } ccsr_gur_t; #endif +typedef struct serdes_corenet { + struct { + u32 rstctl; /* Reset Control Register */ +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 + u32 pllcr0; /* PLL Control Register 0 */ + u32 pllcr1; /* PLL Control Register 1 */ +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + u32 res[5]; + } bank[3]; + u32 res1[12]; + u32 srdstcalcr; /* TX Calibration Control */ + u32 res2[3]; + u32 srdsrcalcr; /* RX Calibration Control */ + u32 res3[3]; + u32 srdsgr0; /* General Register 0 */ + u32 res4[11]; + u32 srdspccr0; /* Protocol Converter Config 0 */ + u32 srdspccr1; /* Protocol Converter Config 1 */ + u32 srdspccr2; /* Protocol Converter Config 2 */ +#define SRDS_PCCR2_RST_XGMII1 0x00800000 +#define SRDS_PCCR2_RST_XGMII2 0x00400000 + u32 res5[197]; + struct { + u32 gcr0; /* General Control Register 0 */ +#define SRDS_GCR0_RRST 0x00400000 +#define SRDS_GCR0_1STLANE 0x00010000 + u32 gcr1; /* General Control Register 1 */ +#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 +#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 +#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 +#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 +#define SRDS_GCR1_OPAD_CTL 0x04000000 + u32 res1[4]; + u32 tecr0; /* TX Equalization Control Reg 0 */ +#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 +#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 + u32 res3; + u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ + u32 res4[7]; + } lane[24]; + u32 res6[384]; +} serdes_corenet_t; + +enum { + FSL_SRDS_B1_LANE_A = 0, + FSL_SRDS_B1_LANE_B = 1, + FSL_SRDS_B1_LANE_C = 2, + FSL_SRDS_B1_LANE_D = 3, + FSL_SRDS_B1_LANE_E = 4, + FSL_SRDS_B1_LANE_F = 5, + FSL_SRDS_B1_LANE_G = 6, + FSL_SRDS_B1_LANE_H = 7, + FSL_SRDS_B1_LANE_I = 8, + FSL_SRDS_B1_LANE_J = 9, + FSL_SRDS_B2_LANE_A = 16, + FSL_SRDS_B2_LANE_B = 17, + FSL_SRDS_B2_LANE_C = 18, + FSL_SRDS_B2_LANE_D = 19, + FSL_SRDS_B3_LANE_A = 20, + FSL_SRDS_B3_LANE_B = 21, + FSL_SRDS_B3_LANE_C = 22, + FSL_SRDS_B3_LANE_D = 23, +}; + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 +#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #else @@ -1874,6 +2032,12 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#ifdef CONFIG_TSECV2 +#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#else +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#endif +#define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 @@ -1883,6 +2047,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_CPC_ADDR \ + (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ @@ -1929,7 +2095,12 @@ typedef struct ccsr_gur { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index fdfc654f29..098f25384b 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1,7 +1,7 @@ /* * MPC86xx Internal Memory Map * - * Copyright(c) 2004 Freescale Semiconductor + * Copyright 2004 Freescale Semiconductor * Jeff Brown (Jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -1298,4 +1298,10 @@ extern immap_t *immr; #define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_MDIO1_OFFSET 0x24000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index ec22a5058e..fd1024947d 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -479,6 +479,8 @@ extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); extern int find_tlb_idx(void *addr, u8 tlbsel); +extern void init_used_tlb_cams(void); +extern int find_free_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f61778f864..c6da411630 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -992,6 +992,9 @@ #endif #endif +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) + /* * SVR_SOC_VER() Version Values */ diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 91369a71e1..49a86fd4cc 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -243,27 +243,27 @@ */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #endif #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 79376b3c57..cfed4ca9f8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -25,6 +25,11 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000 +#endif + /* * High Level Configuration Options */ @@ -51,20 +56,29 @@ HRCWL_SVCOD_DIV_2 |\ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_3X1) -#define CONFIG_SYS_HRCW_HIGH (\ +#define CONFIG_SYS_HRCW_HIGH_BASE (\ HRCWH_PCI_HOST |\ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ HRCWH_TSEC1M_IN_RGMII |\ HRCWH_TSEC2M_IN_RGMII |\ HRCWH_BIG_ENDIAN |\ HRCWH_LALE_NORMAL) +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_ROM_LOC_NAND_SP_8BIT |\ + HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) +#endif + /* * System IO Config */ @@ -79,6 +93,10 @@ */ #define CONFIG_SYS_IMMR 0xE0000000 +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + /* * Arbiter Setup */ @@ -161,12 +179,6 @@ */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -200,10 +212,10 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ -#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ +#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -223,18 +235,31 @@ /* * NAND Flash on the Local Bus */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE0600000 +#endif + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -243,9 +268,31 @@ | OR_FCM_EHTR ) /* 0xFFFF8396 */ +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#endif + #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ + !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + /* * Serial Port */ @@ -254,7 +301,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -408,7 +455,16 @@ /* * Environment */ -#ifndef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_NAND_U_BOOT) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_RANGE) +#elif !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ @@ -442,7 +498,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -504,7 +560,8 @@ /* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 1e659e27a7..e16f0e147b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -277,6 +277,10 @@ extern unsigned long get_clock_freq(void); #define PLPDIR1_I2C_BIT_MASK 0x0000000F #define PLPDIR1_I2C2_VAL 0x0000000F #define PLPDIR1_ESDHC_VAL 0x00000006 +#define PLPPAR1_UART0_BIT_MASK 0x00000fc0 +#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 +#define PLPDIR1_UART0_BIT_MASK 0x00000fc0 +#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 /* * General PCI diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 41e4a6e8a5..78b73695bc 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -98,7 +98,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ -#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index ddfe7aabdc..15bfeefa46 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -149,8 +149,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 #define CONFIG_SYS_DDR_SBE 0x00FF0000 -#define CONFIG_SYS_DDR_TLB_START 9 - /* * Memory map * diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index df9ab34e80..f4509bd090 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -101,7 +101,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ -#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR3 1 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index bec08dab1f..b023326505 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -72,6 +72,14 @@ #define CONFIG_SYS_IMMR 0xE0000000 /* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* * DDR Setup */ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index f9db73b2dc..dbc15b297f 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -35,6 +35,13 @@ #define __CONFIG_H /* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_caddy2 +#define VME_CADDY2 +#endif + +/* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ @@ -43,6 +50,8 @@ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ +#define CONFIG_MISC_INIT_R + #define CONFIG_PCI /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ @@ -75,7 +84,9 @@ */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ /* @@ -96,54 +107,40 @@ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING - -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ - -#if (CONFIG_SYS_DDR_SIZE == 512) -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_BANK_BIT_3) -#endif - -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x39377322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x07940242 -#define CONFIG_SYS_DDR_MODE2 0x00000000 -/* autocharge,no open page */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000 +#define CONFIG_SYS_DDRCDR 0x80080001 /* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ +#ifdef VME_CADDY2 +#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 32bit */ \ + BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */ +#else +#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ (2 << BR_PS_SHIFT) | /* 32bit */ \ BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */ +#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */ +#endif +/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ #define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) -#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200) +#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200) #define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e) +#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ @@ -157,7 +154,7 @@ #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT #else -#undef CONFIG_SYS_RAMBOOT +#undef CONFIG_SYS_RAMBOOT #endif #define CONFIG_SYS_INIT_RAM_LOCK 1 @@ -174,11 +171,10 @@ /* * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 + * LCRR: no DLL bypass, Clock divider is 4 * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 @@ -268,10 +264,10 @@ #undef PCI_ONE_PCI1 #endif -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - +#ifndef VME_CADDY2 #define CONFIG_NET_MULTI +#endif +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -282,19 +278,26 @@ #define PCI_IDSEL_NUMBER 0xFIXME #endif +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + #endif /* CONFIG_PCI */ /* * TSEC configuration */ +#ifdef VME_CADDY2 +#define CONFIG_E1000 +#else #define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#endif #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI #endif -#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_GMII /* MII PHY management */ #define CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 @@ -312,6 +315,12 @@ #endif /* CONFIG_TSEC_ENET */ +#if defined(CONFIG_E1000) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif +#endif + /* * Environment */ @@ -560,7 +569,7 @@ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 9600 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -605,4 +614,9 @@ #define CONFIG_BOOTCOMMAND "run flash_self" +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + #endif /* __CONFIG_H */ diff --git a/include/tsec.h b/include/tsec.h index 0ac3034060..f56723a153 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming @@ -20,22 +20,15 @@ #include <net.h> #include <config.h> -#ifndef CONFIG_SYS_TSEC1_OFFSET - #define CONFIG_SYS_TSEC1_OFFSET (0x24000) -#endif - -#define TSEC_SIZE 0x01000 - -/* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ - || defined(CONFIG_MPC83xx) - #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#endif +#define TSEC_SIZE 0x01000 +#define TSEC_MDIO_OFFSET 0x01000 #define STD_TSEC_INFO(num) \ { \ .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \ + .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ + + (num - 1) * TSEC_MDIO_OFFSET), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ .flags = TSEC##num##_FLAGS \ @@ -44,7 +37,9 @@ #define SET_STD_TSEC_INFO(x, num) \ { \ x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ + x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \ + x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ + + (num - 1) * TSEC_MDIO_OFFSET); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ @@ -461,6 +456,22 @@ typedef struct tsec_hash_regs uint res2[24]; } tsec_hash_t; +typedef struct tsec_mdio { + uint res1[4]; + uint ieventm; + uint imaskm; + uint res2; + uint emapm; + uint res3[320]; + uint miimcfg; /* MII Management: Configuration */ + uint miimcom; /* MII Management: Command */ + uint miimadd; /* MII Management: Address */ + uint miimcon; /* MII Management: Control */ + uint miimstat; /* MII Management: Status */ + uint miimind; /* MII Management: Indicators */ + uint res4[690]; +} tsec_mdio_t; + typedef struct tsec { /* General Control and Status Registers (0x2_n000) */ @@ -526,12 +537,7 @@ typedef struct tsec uint res51c; - uint miimcfg; /* MII Management: Configuration */ - uint miimcom; /* MII Management: Command */ - uint miimadd; /* MII Management: Address */ - uint miimcon; /* MII Management: Control */ - uint miimstat; /* MII Management: Status */ - uint miimind; /* MII Management: Indicators */ + uint resmdio[6]; uint res538; @@ -571,7 +577,8 @@ typedef struct tsec struct tsec_private { volatile tsec_t *regs; - volatile tsec_t *phyregs; + volatile tsec_mdio_t *phyregs; + volatile tsec_mdio_t *phyregs_sgmii; struct phy_info *phyinfo; uint phyaddr; u32 flags; @@ -630,7 +637,8 @@ struct phy_info { struct tsec_info_struct { tsec_t *regs; - tsec_t *miiregs; + tsec_mdio_t *miiregs; + tsec_mdio_t *miiregs_sgmii; char *devname; unsigned int phyaddr; u32 flags; |
