diff options
283 files changed, 11982 insertions, 2631 deletions
diff --git a/.gitignore b/.gitignore index ff4bae0081..e4e95e2d34 100644 --- a/.gitignore +++ b/.gitignore @@ -35,6 +35,7 @@ /u-boot.dis /u-boot.lds /u-boot.ubl +/u-boot.ais /u-boot.dtb /u-boot.sb diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10f3f..8c4fe2df8d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -41,6 +41,10 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com> CPCI750 PPC750FX/GX +Peter Barada <peter.barada@logicpd.com> + + omap3_logic ARM ARMV7 (Logic OMAP35xx/DM37xx) + Yuli Barcohen <yuli@arabellasw.com> Adder MPC87x/MPC852T @@ -436,11 +440,13 @@ Heiko Schocher <hs@denx.de> municse MPC5200 sc3 PPC405GP suvd3 MPC8321 - tuda1 MPC8321 - tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 +Holger Brunck <holger.brunck@keymile.com> + tuge1 MPC8321 + tuxx1 MPC8321 + Peter De Schrijver <p2@mind.be> ML2 PPC4xx @@ -572,6 +578,7 @@ Stefano Babic <sbabic@denx.de> mx51evk i.MX51 polaris xscale/pxa trizepsiv xscale/pxa + twister omap3 vision2 i.MX51 Jason Liu <r64343@freescale.com> @@ -579,6 +586,7 @@ Jason Liu <r64343@freescale.com> mx53evk i.MX53 mx53loco i.MX53 mx6qarm2 i.MX6Q + mx6qsabrelite i.MX6Q Enric Balletbo i Serra <eballetbo@iseebcn.com> @@ -639,6 +647,7 @@ Kristoffer Ericson <kristoffer.ericson@gmail.com> Fabio Estevam <fabio.estevam@freescale.com> mx25pdk i.MX25 + mx28evk i.MX28 mx31pdk i.MX31 mx53ard i.MX53 mx53smd i.MX53 @@ -782,6 +791,11 @@ Stelian Pop <stelian@popies.net> at91sam9263ek ARM926EJS (AT91SAM9263 SoC) at91sam9rlek ARM926EJS (AT91SAM9RL SoC) +Thierry Reding <thierry.reding@avionic-design.de> + + plutux Tegra2 (ARM7 & A9 Dual Core) + medcom Tegra2 (ARM7 & A9 Dual Core) + Tom Rini <trini@ti.com> omap3_evm ARM ARMV7 (OMAP3xx SoC) @@ -1161,5 +1175,16 @@ Macpaul Lin <macpaul@andestech.com> ADP-AG101P N1213 (AG101P XC5 FPGA) ######################################################################### +# OpenRISC Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + + openrisc-generic OpenRISC + +######################################################################### # End of MAINTAINERS list # ######################################################################### @@ -409,6 +409,11 @@ LIST_mips_el=" \ ${LIST_xburst_el} \ ${LIST_au1xx0_el} \ " +######################################################################### +## OpenRISC Systems +######################################################################### + +LIST_openrisc="$(boards_by_arch openrisc)" ######################################################################### ## x86 Systems @@ -294,7 +294,7 @@ LIBS += lib/libfdt/libfdt.o LIBS += api/libapi.o LIBS += post/libpost.o -ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS += $(CPUDIR)/omap-common/libomap-common.o endif @@ -429,6 +429,18 @@ $(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin rm $(obj)u-boot-ubl.bin rm $(obj)spl/u-boot-spl-pad.bin +$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin + $(obj)tools/mkimage -s -n /dev/null -T aisimage \ + -e $(CONFIG_SPL_TEXT_BASE) \ + -d $(obj)spl/u-boot-spl.bin \ + $(obj)spl/u-boot-spl.ais + $(OBJCOPY) ${OBJCFLAGS} -I binary \ + --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \ + $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais + cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \ + $(obj)u-boot.ais + rm $(obj)spl/u-boot-spl{,-pad}.ais + $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \ -o $(obj)u-boot.sb @@ -762,6 +774,7 @@ clobber: tidy @rm -f $(obj)u-boot.kwb @rm -f $(obj)u-boot.imx @rm -f $(obj)u-boot.ubl + @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb @rm -f $(obj)u-boot.sb @rm -f $(obj)tools/inca-swap-bytes @@ -1029,6 +1029,9 @@ The following options need to be configured: If this defined, the driver is quiet. The driver doen't show link status messages. + CONFIG_CALXEDA_XGMAC + Support for the Calxeda XGMAC device + CONFIG_DRIVER_LAN91C96 Support for SMSC's LAN91C96 chips. diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index ac4838f034..d41613e57f 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -393,7 +393,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk) /* * The MX35 has no fuse for MAC, return a NULL MAC */ -void imx_get_mac_from_fuse(unsigned char *mac) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { memset(mac, 0, 6); } diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 5ae89df5db..da7efac085 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -38,7 +38,8 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o ifdef CONFIG_SPL_BUILD COBJS-y += spl.o -COBJS-y += dm365_lowlevel.o +COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o +COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o endif SOBJS = reset.o diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index d9b9398b7e..f475f9ba75 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -26,6 +26,17 @@ #include <nand.h> #include <asm/arch/dm365_lowlevel.h> #include <ns16550.h> +#include <malloc.h> +#include <spi_flash.h> + +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + +DECLARE_GLOBAL_DATA_PTR; +/* Define global data structure pointer to it*/ +static gd_t gdata __attribute__ ((section(".data"))); +static bd_t bdata __attribute__ ((section(".data"))); + +#else void puts(const char *str) { @@ -41,6 +52,8 @@ void putc(char c) NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c); } +#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ + inline void hang(void) { puts("### ERROR ### Please RESET the board ###\n"); @@ -50,14 +63,34 @@ inline void hang(void) void board_init_f(ulong dummy) { +#ifdef CONFIG_SOC_DM365 dm36x_lowlevel_init(0); +#endif +#ifdef CONFIG_SOC_DA8XX + arch_cpu_init(); +#endif relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE); } void board_init_r(gd_t *id, ulong dummy) { - +#ifdef CONFIG_SOC_DM365 nand_init(); puts("Nand boot...\n"); nand_boot(); +#endif +#ifdef CONFIG_SOC_DA8XX + mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN, + CONFIG_SYS_MALLOC_LEN); + + gd = &gdata; + gd->bd = &bdata; + gd->flags |= GD_FLG_RELOC; + gd->baudrate = CONFIG_BAUDRATE; + serial_init(); /* serial communications setup */ + gd->have_console = 1; + + puts("SPI boot...\n"); + spi_boot(); +#endif } diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index c045a0bc58..9cadb7c34c 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -312,7 +312,7 @@ void mx25_fec_init_pins(void) } -void imx_get_mac_from_fuse(unsigned char *mac) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { int i; struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c index 222a8e95ea..34c20e1bae 100644 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ b/arch/arm/cpu/arm926ejs/mx27/generic.c @@ -314,7 +314,7 @@ void mx27_fec_init_pins(void) imx_gpio_mode(mode[i]); } -void imx_get_mac_from_fuse(unsigned char *mac) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { int i; struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c index 088c019b7b..da903605a2 100644 --- a/arch/arm/cpu/arm926ejs/mx28/mx28.c +++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c @@ -214,6 +214,73 @@ int cpu_eth_init(bd_t *bis) } #endif +static void __mx28_adjust_mac(int dev_id, unsigned char *mac) +{ + mac[0] = 0x00; + mac[1] = 0x04; /* Use FSL vendor MAC address by default */ + + if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */ + mac[5] += 1; +} + +void mx28_adjust_mac(int dev_id, unsigned char *mac) + __attribute__((weak, alias("__mx28_adjust_mac"))); + +#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP + +#define MXS_OCOTP_MAX_TIMEOUT 1000000 +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + struct mx28_ocotp_regs *ocotp_regs = + (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; + uint32_t data; + + memset(mac, 0, 6); + + writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); + + if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, + MXS_OCOTP_MAX_TIMEOUT)) { + printf("MXS FEC: Can't get MAC from OCOTP\n"); + return; + } + + data = readl(&ocotp_regs->hw_ocotp_cust0); + + mac[2] = (data >> 24) & 0xff; + mac[3] = (data >> 16) & 0xff; + mac[4] = (data >> 8) & 0xff; + mac[5] = data & 0xff; + mx28_adjust_mac(dev_id, mac); +} +#else +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + memset(mac, 0, 6); +} +#endif + +#define HW_DIGCTRL_SCRATCH0 0x8001c280 +#define HW_DIGCTRL_SCRATCH1 0x8001c290 +int mx28_dram_init(void) +{ + uint32_t sz[2]; + + sz[0] = readl(HW_DIGCTRL_SCRATCH0); + sz[1] = readl(HW_DIGCTRL_SCRATCH1); + + if (sz[0] != sz[1]) { + printf("MX28:\n" + "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" + "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" + "verify these two registers contain valid RAM size!\n"); + hang(); + } + + gd->ram_size = sz[0]; + return 0; +} + U_BOOT_CMD( clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks, "display clocks", diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index a4dc2a31b7..380b120dc9 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -240,8 +240,8 @@ void mx28_enable_4p2_dcdc_input(int xfer) clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) - clrbits_le32(&power_regs->hw_power_ctrl, - POWER_CTRL_VBUS_VALID_IRQ); + writel(POWER_CTRL_VBUS_VALID_IRQ, + &power_regs->hw_power_ctrl_clr); if (prev_5v_brnout) { writel(POWER_5VCTRL_PWDN_5VBRNOUT, @@ -256,8 +256,8 @@ void mx28_enable_4p2_dcdc_input(int xfer) } while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) - clrbits_le32(&power_regs->hw_power_ctrl, - POWER_CTRL_VDD5V_DROOP_IRQ); + writel(POWER_CTRL_VDD5V_DROOP_IRQ, + &power_regs->hw_power_ctrl_clr); if (prev_5v_droop) clrbits_le32(&power_regs->hw_power_ctrl, diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S b/arch/arm/cpu/arm926ejs/mx28/start.S index 94696d6cdc..2cd4d73354 100644 --- a/arch/arm/cpu/arm926ejs/mx28/start.S +++ b/arch/arm/cpu/arm926ejs/mx28/start.S @@ -40,12 +40,6 @@ #include <common.h> #include <version.h> -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#elif defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - /* ************************************************************************* * diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 6beafbbece..7768912603 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -16,8 +16,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -SOBJS := lowlevel_init.o - COBJS += clock.o COBJS += sys_info.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 2d6d359e5f..d64ae6936c 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -19,19 +19,31 @@ #include <common.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> +#include <asm/arch/omap.h> #include <asm/arch/ddr_defs.h> #include <asm/arch/clock.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/common_def.h> #include <asm/io.h> +#include <asm/omap_common.h> DECLARE_GLOBAL_DATA_PTR; struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE; +struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; +struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + +/* UART Defines */ +#ifdef CONFIG_SPL_BUILD +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) +#endif /* * early system init of muxing and clocks. */ -void s_init(u32 in_ddr) +void s_init(void) { /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets @@ -43,24 +55,62 @@ void s_init(u32 in_ddr) while (readl(&wdtimer->wdtwwps) != 0x0) ; +#ifdef CONFIG_SPL_BUILD /* Setup the PLLs and the clocks for the peripherals */ -#ifdef CONFIG_SETUP_PLL pll_init(); + + /* UART softreset */ + u32 regVal; + + enable_uart0_pin_mux(); + + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_RESET; + writel(regVal, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_SMART_IDLE_EN; + writel(regVal, &uart_base->uartsyscfg); + + /* Initialize the Timer */ + init_timer(); + + preloader_console_init(); + + config_ddr(); #endif - if (!in_ddr) - config_ddr(); + + /* Enable MMC0 */ + enable_mmc0_pin_mux(); } /* Initialize timer */ void init_timer(void) { /* Reset the Timer */ - writel(0x2, (&timerreg->tsicrreg)); + writel(0x2, (&timer_base->tscir)); /* Wait until the reset is done */ - while (readl(&timerreg->tiocpcfgreg) & 1) + while (readl(&timer_base->tiocp_cfg) & 1) ; /* Start the Timer */ - writel(0x1, (&timerreg->tclrreg)); + writel(0x1, (&timer_base->tclr)); +} + +#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif + +void setup_clocks_for_console(void) +{ + /* Not yet implemented */ + return; } diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index 4ca6c45349..98cfd93814 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -101,10 +101,18 @@ static void enable_per_clocks(void) while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN) ; + /* Select the Master osc 24 MHZ as Timer2 clock source */ + writel(0x1, &cmdpll->clktimer2clk); + /* UART0 */ writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl); while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN) ; + + /* MMC0*/ + writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); + while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) + ; } static void mpu_pll_config(void) diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk new file mode 100644 index 0000000000..5750bbdcb6 --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/config.mk @@ -0,0 +1,18 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/MLO +else +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 1318365a4a..2f4164df82 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -46,7 +46,7 @@ void dram_init_banksize(void) } -#ifdef CONFIG_AM335X_CONFIG_DDR +#ifdef CONFIG_SPL_BUILD static void data_macro_config(int dataMacroNum) { struct ddr_data data; diff --git a/arch/arm/cpu/armv7/am33xx/lowlevel_init.S b/arch/arm/cpu/armv7/am33xx/lowlevel_init.S deleted file mode 100644 index 17c962ff71..0000000000 --- a/arch/arm/cpu/armv7/am33xx/lowlevel_init.S +++ /dev/null @@ -1,72 +0,0 @@ -/* - * lowlevel_init.S - * - * AM33XX low level initialization. - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * Initial Code by: - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <config.h> -#include <asm/arch/hardware.h> - -_mark1: - .word mark1 -_lowlevel_init1: - .word lowlevel_init -_s_init_start: - .word s_init_start - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -/***************************************************************************** - * lowlevel_init: - Platform low level init. - ****************************************************************************/ -.globl lowlevel_init -lowlevel_init: - - /* The link register is saved in ip by start.S */ - mov r6, ip - /* check if we are already running from RAM */ - ldr r2, _lowlevel_init1 - ldr r3, _TEXT_BASE - sub r4, r2, r3 - sub r0, pc, r4 - ldr sp, SRAM_STACK -mark1: - ldr r5, _mark1 - sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */ - sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */ - mov r10, #0x0 /* r10 has in_ddr used by s_init() */ - - ands r0, r0, #0xC0000000 - /* MSB 2 bits <> 0 then we are in ocmc or DDR */ - cmp r0, #0x80000000 - bne s_init_start - mov r10, #0x01 - b s_init_start - -s_init_start: - mov r0, r10 /* passing in_ddr in r0 */ - bl s_init - /* back to arch calling code */ - mov pc, r6 - /* the literal pools origin */ - .ltorg - -SRAM_STACK: - /* Place stack at the top */ - .word LOW_LEVEL_SRAM_STACK diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index b143535972..fa3a124807 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -285,6 +285,11 @@ u32 imx_get_uartclk(void) return get_uart_clk(); } +u32 imx_get_fecclk(void) +{ + return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index dff5e4efd7..2ac74b5945 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -40,18 +40,35 @@ u32 get_cpu_rev(void) #ifdef CONFIG_ARCH_CPU_INIT void init_aips(void) { - u32 reg = AIPS1_BASE_ADDR; + struct aipstz_regs *aips1, *aips2; + + aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; + aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ - writel(0x77777777, reg + 0x00); - writel(0x77777777, reg + 0x04); + writel(0x77777777, &aips1->mprot0); + writel(0x77777777, &aips1->mprot1); + writel(0x77777777, &aips2->mprot0); + writel(0x77777777, &aips2->mprot1); - reg = AIPS2_BASE_ADDR; - writel(0x77777777, reg + 0x00); - writel(0x77777777, reg + 0x04); + /* + * Set all OPACRx to be non-bufferable, not require + * supervisor privilege level for access,allow for + * write access and untrusted master access. + */ + writel(0x00000000, &aips1->opacr0); + writel(0x00000000, &aips1->opacr1); + writel(0x00000000, &aips1->opacr2); + writel(0x00000000, &aips1->opacr3); + writel(0x00000000, &aips1->opacr4); + writel(0x00000000, &aips2->opacr0); + writel(0x00000000, &aips2->opacr1); + writel(0x00000000, &aips2->opacr2); + writel(0x00000000, &aips2->opacr3); + writel(0x00000000, &aips2->opacr4); } int arch_cpu_init(void) @@ -63,20 +80,22 @@ int arch_cpu_init(void) #endif #if defined(CONFIG_FEC_MXC) -void imx_get_mac_from_fuse(unsigned char *mac) +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; struct fuse_bank *bank = &iim->bank[4]; struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs; - u32 mac_lo = readl(&fuse->mac_addr_low); - u32 mac_hi = readl(&fuse->mac_addr_high); - - *(u32 *)mac = mac_lo; + u32 value = readl(&fuse->mac_addr_high); + mac[0] = (value >> 8); + mac[1] = value ; - mac[4] = mac_hi & 0xff; - mac[5] = (mac_hi >> 8) & 0xff; + value = readl(&fuse->mac_addr_low); + mac[2] = value >> 24 ; + mac[3] = value >> 16 ; + mac[4] = value >> 8 ; + mac[5] = value ; } #endif diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index a684611265..3f7a0b25f0 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -37,6 +37,10 @@ ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) COBJS += hwinit-common.o COBJS += clocks-common.o COBJS += emif-common.o +endif + +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +COBJS += boot-common.o SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c new file mode 100644 index 0000000000..f211f7670c --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -0,0 +1,49 @@ +/* + * boot-common.c + * + * Common bootmode functions for omap based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/omap_common.h> +#include <asm/arch/omap.h> + +/* + * This is used to verify if the configuration header + * was executed by rom code prior to control of transfer + * to the bootloader. SPL is responsible for saving and + * passing the boot_params pointer to the u-boot. + */ +struct omap_boot_parameters boot_params __attribute__ ((section(".data"))); + +#ifdef CONFIG_SPL_BUILD +/* + * We use static variables because global data is not ready yet. + * Initialized data is available in SPL right from the beginning. + * We would not typically need to save these parameters in regular + * U-Boot. This is needed only in SPL at the moment. + */ +u32 omap_bootmode = MMCSD_MODE_FAT; + +u32 omap_boot_device(void) +{ + return (u32) (boot_params.omap_bootdevice); +} + +u32 omap_boot_mode(void) +{ + return omap_bootmode; +} +#endif diff --git a/arch/arm/cpu/armv7/omap-common/gpio.c b/arch/arm/cpu/armv7/omap-common/gpio.c index 75a02da877..fc89f2a42b 100644 --- a/arch/arm/cpu/armv7/omap-common/gpio.c +++ b/arch/arm/cpu/armv7/omap-common/gpio.c @@ -36,7 +36,7 @@ * published by the Free Software Foundation. */ #include <common.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/errno.h> @@ -56,17 +56,17 @@ static inline int get_gpio_index(int gpio) static inline int gpio_valid(int gpio) { if (gpio < 0) - return -EINVAL; + return -1; if (gpio < 192) return 0; - return -EINVAL; + return -1; } static int check_gpio(int gpio) { if (gpio_valid(gpio) < 0) { printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); - return -EINVAL; + return -1; } return 0; } @@ -106,7 +106,7 @@ static int _get_gpio_direction(const struct gpio_bank *bank, int gpio) reg += OMAP_GPIO_OE; break; default: - return -EINVAL; + return -1; } v = __raw_readl(reg); @@ -142,27 +142,29 @@ static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio, /** * Set value of the specified gpio */ -void gpio_set_value(int gpio, int value) +int gpio_set_value(unsigned gpio, int value) { const struct gpio_bank *bank; if (check_gpio(gpio) < 0) - return; + return -1; bank = get_gpio_bank(gpio); _set_gpio_dataout(bank, get_gpio_index(gpio), value); + + return 0; } /** * Get value of the specified gpio */ -int gpio_get_value(int gpio) +int gpio_get_value(unsigned gpio) { const struct gpio_bank *bank; void *reg; int input; if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; bank = get_gpio_bank(gpio); reg = bank->base; switch (bank->method) { @@ -176,11 +178,11 @@ int gpio_get_value(int gpio) reg += OMAP_GPIO_DATAOUT; break; default: - return -EINVAL; + return -1; } break; default: - return -EINVAL; + return -1; } return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0; @@ -194,7 +196,7 @@ int gpio_direction_input(unsigned gpio) const struct gpio_bank *bank; if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; bank = get_gpio_bank(gpio); _set_gpio_direction(bank, get_gpio_index(gpio), 1); @@ -210,7 +212,7 @@ int gpio_direction_output(unsigned gpio, int value) const struct gpio_bank *bank; if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; bank = get_gpio_bank(gpio); _set_gpio_dataout(bank, get_gpio_index(gpio), value); @@ -224,10 +226,10 @@ int gpio_direction_output(unsigned gpio, int value) * * NOTE: Argument 'label' is unused. */ -int gpio_request(int gpio, const char *label) +int gpio_request(unsigned gpio, const char *label) { if (check_gpio(gpio) < 0) - return -EINVAL; + return -1; return 0; } @@ -235,6 +237,7 @@ int gpio_request(int gpio, const char *label) /** * Reset and free the gpio after using it. */ -void gpio_free(unsigned gpio) +int gpio_free(unsigned gpio) { + return 0; } diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index f65705db12..49cdc3936e 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -35,34 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * This is used to verify if the configuration header - * was executed by rom code prior to control of transfer - * to the bootloader. SPL is responsible for saving and - * passing the boot_params pointer to the u-boot. - */ -struct omap_boot_parameters boot_params __attribute__ ((section(".data"))); - -#ifdef CONFIG_SPL_BUILD -/* - * We use static variables because global data is not ready yet. - * Initialized data is available in SPL right from the beginning. - * We would not typically need to save these parameters in regular - * U-Boot. This is needed only in SPL at the moment. - */ -u32 omap_bootmode = MMCSD_MODE_FAT; - -u32 omap_boot_device(void) -{ - return (u32) (boot_params.omap_bootdevice); -} - -u32 omap_boot_mode(void) -{ - return omap_bootmode; -} -#endif - void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) { int i; @@ -104,14 +76,14 @@ u32 cortex_rev(void) return rev; } -void omap_rev_string(char *omap_rev_string) +void omap_rev_string(void) { u32 omap_rev = omap_revision(); u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; u32 major_rev = (omap_rev & 0x00000F00) >> 8; u32 minor_rev = (omap_rev & 0x000000F0) >> 4; - sprintf(omap_rev_string, "OMAP%x ES%x.%x", omap_variant, major_rev, + printf("OMAP%x ES%x.%x\n", omap_variant, major_rev, minor_rev); } @@ -251,10 +223,8 @@ u32 get_device_type(void) */ int print_cpuinfo(void) { - char rev_string_buffer[50]; - - omap_rev_string(rev_string_buffer); - printf("CPU : %s\n", rev_string_buffer); + puts("CPU : "); + omap_rev_string(); return 0; } diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 9c35a09038..9c1f7e3eda 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -35,6 +35,7 @@ #include <i2c.h> #include <image.h> #include <malloc.h> +#include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -115,8 +116,6 @@ void board_init_r(gd_t *id, ulong dummy) mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); - timer_init(); - #ifdef CONFIG_SPL_BOARD_INIT spl_board_init(); #endif @@ -156,7 +155,6 @@ void board_init_r(gd_t *id, ulong dummy) void preloader_console_init(void) { const char *u_boot_rev = U_BOOT_VERSION; - char rev_string_buffer[50]; gd = &gdata; gd->bd = &bdata; @@ -172,14 +170,10 @@ void preloader_console_init(void) printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, U_BOOT_TIME); - omap_rev_string(rev_string_buffer); - printf("Texas Instruments %s\n", rev_string_buffer); + omap_rev_string(); } -void __omap_rev_string(char *str) +void __weak omap_rev_string() { - sprintf(str, "Revision detection unimplemented"); + printf("Texas Instruments Revision detection unimplemented\n"); } - -void omap_rev_string(char *str) - __attribute__((weak, alias("__omap_rev_string"))); diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 1f33c6398c..871aa37df8 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -230,6 +230,8 @@ void s_init(void) #ifdef CONFIG_SPL_BUILD preloader_console_init(); + + timer_init(); #endif if (!in_sdram) diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 22887aec05..3c80113502 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -30,6 +30,7 @@ #include <asm/arch/mem.h> /* get mem tables */ #include <asm/arch/sys_proto.h> #include <i2c.h> +#include <linux/compiler.h> extern omap3_sysinfo sysinfo; static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; @@ -197,7 +198,7 @@ u32 get_gpmc0_width(void) * get_board_rev() - setup to pass kernel board revision information * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) *************************************************************************/ -u32 get_board_rev(void) +u32 __weak get_board_rev(void) { return 0x20; } diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 37a86b4c2f..91f83205ed 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -110,10 +110,10 @@ void do_io_settings(void) * i. unconditionally for all 4430 * ii. only if un-trimmed for 4460 */ - if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_1)) + if (!readl(&ctrl->control_efuse_1)) writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); - if (!readl(&ctrl->control_efuse_2)) + if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2)) writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); } #endif diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index 955c3b6dc4..f668a818fb 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -33,7 +33,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := ap20.o board.o clock.o pinmux.o sys_info.o timer.o +COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 59dce8f8de..ea06570bfa 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -24,12 +24,22 @@ #include <common.h> #include <asm/io.h> #include "ap20.h" +#include <asm/arch/clock.h> +#include <asm/arch/funcmux.h> #include <asm/arch/sys_proto.h> #include <asm/arch/tegra2.h> #include <asm/arch/pmc.h> DECLARE_GLOBAL_DATA_PTR; +enum { + /* UARTs which we can enable */ + UARTA = 1 << 0, + UARTB = 1 << 1, + UARTD = 1 << 3, + UART_COUNT = 4, +}; + /* * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0, * so we are using this value to identify memory size. @@ -80,6 +90,54 @@ int arch_cpu_init(void) { /* Fire up the Cortex A9 */ tegra2_start(); + + /* We didn't do this init in start.S, so do it now */ + cpu_init_cp15(); + + /* Initialize essential common plls */ + clock_early_init(); + return 0; } #endif + +/** + * Set up the specified uarts + * + * @param uarts_ids Mask containing UARTs to init (UARTx) + */ +static void setup_uarts(int uart_ids) +{ + static enum periph_id id_for_uart[] = { + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_UART4, + }; + size_t i; + + for (i = 0; i < UART_COUNT; i++) { + if (uart_ids & (1 << i)) { + enum periph_id id = id_for_uart[i]; + + funcmux_select(id, 0); + clock_ll_start_uart(id); + } + } +} + +void board_init_uart_f(void) +{ + int uart_ids = 0; /* bit mask of which UART ids to enable */ + +#ifdef CONFIG_TEGRA2_ENABLE_UARTA + uart_ids |= UARTA; +#endif +#ifdef CONFIG_TEGRA2_ENABLE_UARTB + uart_ids |= UARTB; +#endif +#ifdef CONFIG_TEGRA2_ENABLE_UARTD + uart_ids |= UARTD; +#endif + setup_uarts(uart_ids); +} diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c index 03ac1e3ed0..11d2346d83 100644 --- a/arch/arm/cpu/armv7/tegra2/clock.c +++ b/arch/arm/cpu/armv7/tegra2/clock.c @@ -904,6 +904,20 @@ static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) return 0; } +void clock_ll_start_uart(enum periph_id periph_id) +{ + /* Assert UART reset and enable clock */ + reset_set_enable(periph_id, 1); + clock_enable(periph_id); + clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ + + /* wait for 2us */ + udelay(2); + + /* De-assert reset to UART */ + reset_set_enable(periph_id, 0); +} + int clock_verify(void) { struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH); diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index 8f9bdc9ff0..2303dba079 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -29,3 +29,5 @@ ifdef CONFIG_TEGRA2 CFLAGS_arch/arm/lib/board.o += -march=armv4t endif + +USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c new file mode 100644 index 0000000000..0878f51110 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/funcmux.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra2 high-level function multiplexing */ +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/pinmux.h> + +int funcmux_select(enum periph_id id, int config) +{ + if (config != 0) { + debug("%s: invalid config %d for periph_id %d", __func__, + config, id); + return -1; + } + switch (id) { + case PERIPH_ID_UART1: + pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); + pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PINGRP_IRRX); + pinmux_tristate_disable(PINGRP_IRTX); + break; + + case PERIPH_ID_UART2: + pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA); + pinmux_tristate_disable(PINGRP_UAD); + break; + + case PERIPH_ID_UART4: + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); + pinmux_tristate_disable(PINGRP_GMC); + break; + + default: + debug("%s: invalid periph_id %d", __func__, id); + return -1; + } + + return 0; +} diff --git a/board/ti/am335x/common_def.h b/arch/arm/include/asm/arch-am33xx/common_def.h index 1696d6093d..767932daea 100644 --- a/board/ti/am335x/common_def.h +++ b/arch/arm/include/asm/arch-am33xx/common_def.h @@ -17,8 +17,6 @@ #define __COMMON_DEF_H__ extern void enable_uart0_pin_mux(void); -extern void configure_evm_pin_mux(unsigned char daughter_board_id, - unsigned short daughter_board_profile, - unsigned char daughter_board_flag); +extern void enable_mmc0_pin_mux(void); #endif/*__COMMON_DEF_H__ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index ad9156eb44..25558a2b2c 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -51,7 +51,7 @@ | BIT(3) | BIT(4)) /* Reset control */ -#ifdef CONFIG_AM335X +#ifdef CONFIG_AM33XX #define PRM_RSTCTRL 0x44E00F00 #endif #define PRM_RSTCTRL_RESET 0x01 @@ -108,22 +108,36 @@ struct cm_perpll { unsigned int l3sclkstctrl; /* offset 0x04 */ unsigned int l4fwclkstctrl; /* offset 0x08 */ unsigned int l3clkstctrl; /* offset 0x0c */ - unsigned int resv1[6]; + unsigned int resv1; + unsigned int cpgmac0clkctrl; /* offset 0x14 */ + unsigned int resv2[4]; unsigned int emifclkctrl; /* offset 0x28 */ unsigned int ocmcramclkctrl; /* offset 0x2c */ - unsigned int resv2[12]; + unsigned int gpmcclkctrl; /* offset 0x30 */ + unsigned int resv3[2]; + unsigned int mmc0clkctrl; /* offset 0x3C */ + unsigned int elmclkctrl; /* offset 0x40 */ + unsigned int i2c2clkctrl; /* offset 0x44 */ + unsigned int i2c1clkctrl; /* offset 0x48 */ + unsigned int spi0clkctrl; /* offset 0x4C */ + unsigned int spi1clkctrl; /* offset 0x50 */ + unsigned int resv4[3]; unsigned int l4lsclkctrl; /* offset 0x60 */ unsigned int l4fwclkctrl; /* offset 0x64 */ - unsigned int resv3[6]; + unsigned int resv5[6]; unsigned int timer2clkctrl; /* offset 0x80 */ - unsigned int resv4[19]; + unsigned int resv6[11]; + unsigned int gpio2clkctrl; /* offset 0xB0 */ + unsigned int resv7[7]; unsigned int emiffwclkctrl; /* offset 0xD0 */ - unsigned int resv5[2]; + unsigned int resv8[2]; unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ - unsigned int resv6[14]; + unsigned int resv9[14]; unsigned int l4hsclkstctrl; /* offset 0x11C */ unsigned int l4hsclkctrl; /* offset 0x120 */ + unsigned int resv10[8]; + unsigned int cpswclkctrl; /* offset 0x144 */ }; /* Encapsulating Display pll registers */ @@ -158,24 +172,12 @@ struct wd_timer { unsigned int wdt_unfr; /* offset 0x100 */ }; -/* Timer Registers */ -struct timer_reg { - unsigned int resv1[4]; - unsigned int tiocpcfgreg; /* offset 0x10 */ - unsigned int resv2[9]; - unsigned int tclrreg; /* offset 0x38 */ - unsigned int tcrrreg; /* offset 0x3C */ - unsigned int tldrreg; /* offset 0x40 */ - unsigned int resv3[4]; - unsigned int tsicrreg; /* offset 0x54 */ -}; - /* Timer 32 bit registers */ struct gptimer { unsigned int tidr; /* offset 0x00 */ - unsigned int res1[0xc]; + unsigned char res1[12]; unsigned int tiocp_cfg; /* offset 0x10 */ - unsigned int res2[0xc]; + unsigned char res2[12]; unsigned int tier; /* offset 0x20 */ unsigned int tistatr; /* offset 0x24 */ unsigned int tistat; /* offset 0x28 */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 9638b4caa3..ba6b59b89f 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -76,7 +76,7 @@ struct emif_regs { unsigned int sdrmcsr; /* offset 0x3C */ unsigned int res2[8]; unsigned int sdritr; /* offset 0x60 */ - unsigned int res3[20]; + unsigned int res3[32]; unsigned int ddrphycr; /* offset 0xE4 */ unsigned int ddrphycsr; /* offset 0xE8 */ unsigned int ddrphycr2; /* offset 0xEC */ @@ -161,10 +161,10 @@ struct ddr_regs { unsigned int dt0wiratio1; /* offset 0x0F4 */ unsigned int dt0giratio0; /* offset 0x0FC */ unsigned int dt0giratio1; /* offset 0x100 */ - unsigned int resv6[2]; + unsigned int resv6[1]; unsigned int dt0fwsratio0; /* offset 0x108 */ unsigned int dt0fwsratio1; /* offset 0x10C */ - unsigned int resv7[5]; + unsigned int resv7[4]; unsigned int dt0wrsratio0; /* offset 0x120 */ unsigned int dt0wrsratio1; /* offset 0x124 */ unsigned int resv8[3]; diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h new file mode 100644 index 0000000000..5d7dd4b388 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -0,0 +1,164 @@ +/* + * mmc_host_def.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC1_BASE 0x48060100 +#define OMAP_HSMMC2_BASE 0x481D8000 +#define OMAP_HSMMC3_BASE 0x47C24000 + +typedef struct hsmmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned char res3[0xD4]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x8]; + unsigned int capa; /* 0x140 */ +} hsmmc_t; + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define BCE_ENABLE (0x1 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define MSBS_MULTIBLK (0x1 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) + +/* Clock Configurations and Macros */ +#define MMC_CLOCK_REFERENCE 96 /* MHz */ + +#define mmc_reg_out(addr, mask, val)\ + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) + +int omap_mmc_init(int dev_index); + +#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h new file mode 100644 index 0000000000..fc2b7a5a28 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -0,0 +1,59 @@ +/* + * omap.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * Author: + * Chandan Nath <chandan.nath@ti.com> + * + * Derived from OMAP4 work by + * Aneesh V <aneesh@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _OMAP_H_ +#define _OMAP_H_ + +/* + * Non-secure SRAM Addresses + * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE + * at 0x40304000(EMU base) so that our code works for both EMU and GP + */ +#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_END 0x4030E000 +#define LOW_LEVEL_SRAM_STACK 0x4030B7FC + +/* ROM code defines */ +/* Boot device */ +#define BOOT_DEVICE_MASK 0xFF +#define BOOT_DEVICE_OFFSET 0x8 +#define DEV_DESC_PTR_OFFSET 0x4 +#define DEV_DATA_PTR_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 +#define RESET_REASON_OFFSET 0x9 +#define CH_FLAGS_OFFSET 0xA + +#define CH_FLAGS_CHSETTINGS (0x1 << 0) +#define CH_FLAGS_CHRAM (0x1 << 1) +#define CH_FLAGS_CHFLASH (0x1 << 2) +#define CH_FLAGS_CHMMCSD (0x1 << 3) + +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + char *boot_message; + unsigned int mem_boot_descriptor; + unsigned char omap_bootdevice; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif +#endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 09ed6508b9..6c58f1b30f 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -29,4 +29,5 @@ int print_cpuinfo(void); #endif u32 get_device_type(void); +void setup_clocks_for_console(void); #endif diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index dd89e84413..1c71540e48 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -622,8 +622,8 @@ struct davinci_rtc { #define RTC_STATE_BUSY 0x01 #define RTC_STATE_RUN 0x02 -#define RTC_KICK0R_WE 0x130be783 -#define RTC_KICK1R_WE 0xe0f1a495 +#define RTC_KICK0R_WE 0x83e70b13 +#define RTC_KICK1R_WE 0x95a4f1e0 #define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h index be1f7db2ae..f10149477a 100644 --- a/arch/arm/include/asm/arch-mx28/sys_proto.h +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h @@ -35,4 +35,6 @@ void mx28_common_spl_init(const iomux_cfg_t *iomux_setup, const unsigned int iomux_size); #endif +int mx28_dram_init(void); + #endif /* __MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 85d55b751d..5227b44fbf 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -167,7 +167,7 @@ #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> -extern void imx_get_mac_from_fuse(unsigned char *mac); +extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /* System Reset Controller (SRC) */ struct src { @@ -214,7 +214,7 @@ struct iim_regs { u32 crc_value; u32 rsvd6[3]; u32 version; - u32 rsvd7[0xd8]; + u32 rsvd7[0xdb]; struct fuse_bank { u32 fuse_regs[0x20]; @@ -232,5 +232,16 @@ struct fuse_bank4_regs { u32 rsvd3[0x13]; }; +struct aipstz_regs { + u32 mprot0; + u32 mprot1; + u32 rsvd[0xe]; + u32 opacr0; + u32 opacr1; + u32 opacr2; + u32 opacr3; + u32 opacr4; +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 5fd02d4dfc..4ca929edea 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -123,6 +123,32 @@ enum { V_MCFG_BANKALLOCATION_RBC | \ V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR +/* Hynix part of Overo (165MHz optimized) 6.06ns */ +#define HYNIX_TDAL_165 6 +#define HYNIX_TDPL_165 3 +#define HYNIX_TRRD_165 2 +#define HYNIX_TRCD_165 3 +#define HYNIX_TRP_165 3 +#define HYNIX_TRAS_165 7 +#define HYNIX_TRC_165 10 +#define HYNIX_TRFC_165 21 +#define HYNIX_V_ACTIMA_165 \ + ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ + HYNIX_TRAS_165, HYNIX_TRP_165, \ + HYNIX_TRCD_165, HYNIX_TRRD_165, \ + HYNIX_TDPL_165, HYNIX_TDAL_165) + +#define HYNIX_TWTR_165 1 +#define HYNIX_TCKE_165 1 +#define HYNIX_TXP_165 2 +#define HYNIX_XSR_165 24 +#define HYNIX_V_ACTIMB_165 \ + ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ + HYNIX_TXP_165, HYNIX_XSR_165) + +#define HYNIX_RASWIDTH_165 0x2 +#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) + /* Hynix part of AM/DM37xEVM (200MHz optimized) */ #define HYNIX_TDAL_200 6 #define HYNIX_TDPL_200 3 diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 4d8c89ffbd..416c6de314 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -116,7 +116,7 @@ #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 -#define CONTROL_EFUSE_2_OVERRIDE 0x00084000 +#define CONTROL_EFUSE_2_OVERRIDE 0x99084000 /* LPDDR2 IO regs */ #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 4146e21818..b8dbc2c9a2 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -42,7 +42,7 @@ void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); -void omap_rev_string(char *omap_rev_string); +void omap_rev_string(void); void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 *const base); diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index c31e18ca22..40a7c57489 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -42,7 +42,7 @@ void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void omap_rev_string(char *omap_rev_string); +void omap_rev_string(void); void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 *const base); diff --git a/arch/arm/include/asm/arch-tegra2/board.h b/arch/arm/include/asm/arch-tegra2/board.h new file mode 100644 index 0000000000..a90d36c708 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/board.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_BOARD_H_ +#define _TEGRA_BOARD_H_ + +/* Setup UARTs for the board according to the selected config */ +void board_init_uart_f(void); + +#endif diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h index 49e9904b57..080ef18e81 100644 --- a/arch/arm/include/asm/arch-tegra2/clock.h +++ b/arch/arm/include/asm/arch-tegra2/clock.h @@ -344,6 +344,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, */ unsigned clock_get_rate(enum clock_id clkid); +/** + * Start up a UART using low-level calls + * + * Prior to relocation clock_start_periph_pll() cannot be called. This + * function provides a way to set up a UART using low-level calls which + * do not require BSS. + * + * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) + */ +void clock_ll_start_uart(enum periph_id periph_id); + /* * Checks that clocks are valid and prints a warning if not * diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h new file mode 100644 index 0000000000..2d724a2872 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/funcmux.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Tegra2 high-level function multiplexing */ + +#ifndef __FUNCMUX_H +#define __FUNCMUX_H + +/** + * Select a config for a particular peripheral. + * + * Each peripheral can operate through a number of configurations, + * which are sets of pins that it uses to bring out its signals. + * The basic config is 0, and higher numbers indicate different + * pinmux settings to bring the peripheral out on other pins, + * + * @param id Peripheral id + * @param config Configuration to use (generally 0) + * @return 0 if ok, -1 on error (e.g. incorrect id or config) + */ +int funcmux_select(enum periph_id id, int config); + +#endif diff --git a/arch/arm/include/asm/arch-tegra2/mmc.h b/arch/arm/include/asm/arch-tegra2/mmc.h new file mode 100644 index 0000000000..c1f12dbe49 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/mmc.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2011, Google Inc. All rights reserved. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA2_MMC_H_ +#define _TEGRA2_MMC_H_ + +int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); + +#endif /* TEGRA2_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index 742a75a0da..8941443ad8 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -38,6 +38,7 @@ #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) +#define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) #define NV_PA_PMC_BASE 0x7000E400 #define NV_PA_CSITE_BASE 0x70040000 diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h new file mode 100644 index 0000000000..ceec4287a3 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h @@ -0,0 +1,76 @@ +/* + * NVIDIA Tegra2 SPI-FLASH controller + * + * Copyright 2010-2011 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA2_SPI_H_ +#define _TEGRA2_SPI_H_ + +#include <asm/types.h> + +struct spi_tegra { + u32 command; /* SPI_COMMAND_0 register */ + u32 status; /* SPI_STATUS_0 register */ + u32 rx_cmp; /* SPI_RX_CMP_0 register */ + u32 dma_ctl; /* SPI_DMA_CTL_0 register */ + u32 tx_fifo; /* SPI_TX_FIFO_0 register */ + u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ + u32 rx_fifo; /* SPI_RX_FIFO_0 register */ +}; + +#define SPI_CMD_GO (1 << 30) +#define SPI_CMD_ACTIVE_SCLK_SHIFT 26 +#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) +#define SPI_CMD_CK_SDA (1 << 21) +#define SPI_CMD_ACTIVE_SDA_SHIFT 18 +#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) +#define SPI_CMD_CS_POL (1 << 16) +#define SPI_CMD_TXEN (1 << 15) +#define SPI_CMD_RXEN (1 << 14) +#define SPI_CMD_CS_VAL (1 << 13) +#define SPI_CMD_CS_SOFT (1 << 12) +#define SPI_CMD_CS_DELAY (1 << 9) +#define SPI_CMD_CS3_EN (1 << 8) +#define SPI_CMD_CS2_EN (1 << 7) +#define SPI_CMD_CS1_EN (1 << 6) +#define SPI_CMD_CS0_EN (1 << 5) +#define SPI_CMD_BIT_LENGTH (1 << 4) +#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F + +#define SPI_STAT_BSY (1 << 31) +#define SPI_STAT_RDY (1 << 30) +#define SPI_STAT_RXF_FLUSH (1 << 29) +#define SPI_STAT_TXF_FLUSH (1 << 28) +#define SPI_STAT_RXF_UNR (1 << 27) +#define SPI_STAT_TXF_OVF (1 << 26) +#define SPI_STAT_RXF_EMPTY (1 << 25) +#define SPI_STAT_RXF_FULL (1 << 24) +#define SPI_STAT_TXF_EMPTY (1 << 23) +#define SPI_STAT_TXF_FULL (1 << 22) +#define SPI_STAT_SEL_TXRX_N (1 << 16) +#define SPI_STAT_CUR_BLKCNT (1 << 15) + +#define SPI_TIMEOUT 1000 +#define TEGRA2_SPI_MAX_FREQ 52000000 + + +#endif /* _TEGRA2_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h new file mode 100644 index 0000000000..e4503b15b0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _UART_SPI_SWITCH_H +#define _UART_SPI_SWITCH_H + +#if defined(CONFIG_SPI_UART_SWITCH) +/* + * Signal that we are about to use the UART. This unfortunate hack is + * required by Seaboard, which cannot use its console and SPI at the same + * time! If the board file provides this, the board config will declare it. + * Let this be a lesson for others. + */ +void pinmux_select_uart(NS16550_t regs); + +/* + * Signal that we are about the use the SPI bus. + */ +void pinmux_select_spi(void); + +#else /* not CONFIG_SPI_UART_SWITCH */ + +static inline void pinmux_select_uart(NS16550_t regs) {} +static inline void pinmux_select_spi(void) {} + +#endif + +#endif diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index eb071d1824..d49ad080e2 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,38 +1,2 @@ -/* - * Copyright (c) 2011, NVIDIA Corp. All rights reserved. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _GPIO_H_ -#define _GPIO_H_ - #include <asm/arch/gpio.h> -/* - * Generic GPIO API - */ - -int gpio_request(int gp, const char *label); -void gpio_free(int gp); -void gpio_toggle_value(int gp); -int gpio_direction_input(int gp); -int gpio_direction_output(int gp, int value); -int gpio_get_value(int gp); -void gpio_set_value(int gp, int value); - -#endif /* _GPIO_H_ */ +#include <asm-generic/gpio.h> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 1ec651b353..34bec4568d 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -62,6 +62,11 @@ void preloader_console_init(void); #define BOOT_DEVICE_MMC2 5 /*emmc*/ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_XIPWAIT 7 +#elif defined(CONFIG_AM33XX) /* AM33XX */ +#define BOOT_DEVICE_NAND 5 +#define BOOT_DEVICE_MMC1 8 +#define BOOT_DEVICE_MMC2 0 +#define BOOT_DEVICE_UART 65 #endif /* Boot type */ @@ -86,7 +91,7 @@ u32 omap_boot_mode(void); /* SPL common function s*/ void spl_parse_image_header(const struct image_header *header); -void omap_rev_string(char *omap_rev_string); +void omap_rev_string(void); /* NAND SPL functions */ void spl_nand_load_image(void); diff --git a/board/overo/config.mk b/arch/openrisc/config.mk index e7c471cc20..521e73aae6 100644 --- a/board/overo/config.mk +++ b/arch/openrisc/config.mk @@ -1,8 +1,6 @@ # -# Overo uses OMAP3 (ARM-CortexA8) cpu -# -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2011 +# Julius Baxter <julius@opencores.org> # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -19,10 +17,11 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) -CONFIG_SYS_TEXT_BASE = 0x80008000 +CROSS_COMPILE ?= or32-elf- + +# r10 used for global object pointer, already set in OR32 GCC but just to be +# clear +PLATFORM_CPPFLAGS += -DCONFIG_OPENRISC -D__OR1K__ -ffixed-r10 + +CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 diff --git a/arch/openrisc/cpu/Makefile b/arch/openrisc/cpu/Makefile new file mode 100644 index 0000000000..b3b1a243c3 --- /dev/null +++ b/arch/openrisc/cpu/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2011 +# Julius Baxter <julius@opencores.org> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +START = start.o +COBJS-y = cache.o cpu.o exceptions.o interrupts.o + +SRCS := $(START:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c new file mode 100644 index 0000000000..2a73a4f2cb --- /dev/null +++ b/arch/openrisc/cpu/cache.c @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/system.h> + +void flush_dcache_range(unsigned long addr, unsigned long stop) +{ + ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16; + + while (addr < stop) { + mtspr(SPR_DCBFR, addr); + addr += block_size; + } +} + +void invalidate_dcache_range(unsigned long addr, unsigned long stop) +{ + ulong block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16; + + while (addr < stop) { + mtspr(SPR_DCBIR, addr); + addr += block_size; + } +} + +static void invalidate_icache_range(unsigned long addr, unsigned long stop) +{ + ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16; + + while (addr < stop) { + mtspr(SPR_ICBIR, addr); + addr += block_size; + } +} + +void flush_cache(unsigned long addr, unsigned long size) +{ + flush_dcache_range(addr, addr + size); + invalidate_icache_range(addr, addr + size); +} + +int icache_status(void) +{ + return mfspr(SPR_SR) & SPR_SR_ICE; +} + +int checkicache(void) +{ + unsigned long iccfgr; + unsigned long cache_set_size; + unsigned long cache_ways; + unsigned long cache_block_size; + + iccfgr = mfspr(SPR_ICCFGR); + cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); + cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); + cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16; + + return cache_set_size * cache_ways * cache_block_size; +} + +int dcache_status(void) +{ + return mfspr(SPR_SR) & SPR_SR_DCE; +} + +int checkdcache(void) +{ + unsigned long dccfgr; + unsigned long cache_set_size; + unsigned long cache_ways; + unsigned long cache_block_size; + + dccfgr = mfspr(SPR_DCCFGR); + cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW); + cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); + cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; + + return cache_set_size * cache_ways * cache_block_size; +} + +void dcache_enable(void) +{ + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); +} + +void dcache_disable(void) +{ + mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE); +} + +void icache_enable(void) +{ + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); + asm volatile("l.nop"); +} + +void icache_disable(void) +{ + mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE); +} + +int cache_init(void) +{ + if (mfspr(SPR_UPR) & SPR_UPR_ICP) { + icache_disable(); + invalidate_icache_range(0, checkicache()); + icache_enable(); + } + + if (mfspr(SPR_UPR) & SPR_UPR_DCP) { + dcache_disable(); + invalidate_dcache_range(0, checkdcache()); + dcache_enable(); + } + + return 0; +} diff --git a/arch/openrisc/cpu/cpu.c b/arch/openrisc/cpu/cpu.c new file mode 100644 index 0000000000..25cd6249d2 --- /dev/null +++ b/arch/openrisc/cpu/cpu.c @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/system.h> +#include <asm/openrisc_exc.h> + +static volatile int illegal_instruction; + +static void illegal_instruction_handler(void) +{ + ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE); + + /* skip over the illegal instruction */ + mtspr(SPR_EPCR_BASE, (ulong)(++epcr)); + illegal_instruction = 1; +} + +static void checkinstructions(void) +{ + ulong ra = 1, rb = 1, rc; + + exception_install_handler(EXC_ILLEGAL_INSTR, + illegal_instruction_handler); + + illegal_instruction = 0; + asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb)); + printf(" Hardware multiplier: %s\n", + illegal_instruction ? "no" : "yes"); + + illegal_instruction = 0; + asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb)); + printf(" Hardware divider: %s\n", + illegal_instruction ? "no" : "yes"); + + exception_free_handler(EXC_ILLEGAL_INSTR); +} + +int checkcpu(void) +{ + ulong upr = mfspr(SPR_UPR); + ulong vr = mfspr(SPR_VR); + ulong iccfgr = mfspr(SPR_ICCFGR); + ulong dccfgr = mfspr(SPR_DCCFGR); + ulong immucfgr = mfspr(SPR_IMMUCFGR); + ulong dmmucfgr = mfspr(SPR_DMMUCFGR); + ulong cpucfgr = mfspr(SPR_CPUCFGR); + uint ver = (vr & SPR_VR_VER) >> 24; + uint rev = vr & SPR_VR_REV; + uint block_size; + uint ways; + uint sets; + + printf("CPU: OpenRISC-%x00 (rev %d) @ %d MHz\n", + ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000)); + + if (upr & SPR_UPR_DCP) { + block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; + ways = 1 << (dccfgr & SPR_DCCFGR_NCW); + printf(" D-Cache: %d bytes, %d bytes/line, %d way(s)\n", + checkdcache(), block_size, ways); + } else { + printf(" D-Cache: no\n"); + } + + if (upr & SPR_UPR_ICP) { + block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16; + ways = 1 << (iccfgr & SPR_ICCFGR_NCW); + printf(" I-Cache: %d bytes, %d bytes/line, %d way(s)\n", + checkicache(), block_size, ways); + } else { + printf(" I-Cache: no\n"); + } + + if (upr & SPR_UPR_DMP) { + sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2); + ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1; + printf(" DMMU: %d sets, %d way(s)\n", + sets, ways); + } else { + printf(" DMMU: no\n"); + } + + if (upr & SPR_UPR_IMP) { + sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2); + ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1; + printf(" IMMU: %d sets, %d way(s)\n", + sets, ways); + } else { + printf(" IMMU: no\n"); + } + + printf(" MAC unit: %s\n", + (upr & SPR_UPR_MP) ? "yes" : "no"); + printf(" Debug unit: %s\n", + (upr & SPR_UPR_DUP) ? "yes" : "no"); + printf(" Performance counters: %s\n", + (upr & SPR_UPR_PCUP) ? "yes" : "no"); + printf(" Power management: %s\n", + (upr & SPR_UPR_PMP) ? "yes" : "no"); + printf(" Interrupt controller: %s\n", + (upr & SPR_UPR_PICP) ? "yes" : "no"); + printf(" Timer: %s\n", + (upr & SPR_UPR_TTP) ? "yes" : "no"); + printf(" Custom unit(s): %s\n", + (upr & SPR_UPR_CUP) ? "yes" : "no"); + + printf(" Supported instructions:\n"); + printf(" ORBIS32: %s\n", + (cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no"); + printf(" ORBIS64: %s\n", + (cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no"); + printf(" ORFPX32: %s\n", + (cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no"); + printf(" ORFPX64: %s\n", + (cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no"); + + checkinstructions(); + + return 0; +} + +int cleanup_before_linux(void) +{ + disable_interrupts(); + return 0; +} + +extern void __reset(void); + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + disable_interrupts(); + __reset(); + /* not reached, __reset does not return */ + return 0; +} diff --git a/arch/openrisc/cpu/exceptions.c b/arch/openrisc/cpu/exceptions.c new file mode 100644 index 0000000000..5d9f117df0 --- /dev/null +++ b/arch/openrisc/cpu/exceptions.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <stdio_dev.h> +#include <asm/system.h> + +static const char * const excp_table[] = { + "Unknown exception", + "Reset", + "Bus Error", + "Data Page Fault", + "Instruction Page Fault", + "Tick Timer", + "Alignment", + "Illegal Instruction", + "External Interrupt", + "D-TLB Miss", + "I-TLB Miss", + "Range", + "System Call", + "Floating Point", + "Trap", +}; + +static void (*handlers[32])(void); + +void exception_install_handler(int exception, void (*handler)(void)) +{ + if (exception < 0 || exception > 31) + return; + + handlers[exception] = handler; +} + +void exception_free_handler(int exception) +{ + if (exception < 0 || exception > 31) + return; + + handlers[exception] = 0; +} + +static void exception_hang(int vect) +{ + printf("Unhandled exception at 0x%x ", vect & 0xff00); + + vect = ((vect >> 8) & 0xff); + if (vect < ARRAY_SIZE(excp_table)) + printf("(%s)\n", excp_table[vect]); + else + printf("(%s)\n", excp_table[0]); + + printf("EPCR: 0x%08lx\n", mfspr(SPR_EPCR_BASE)); + printf("EEAR: 0x%08lx\n", mfspr(SPR_EEAR_BASE)); + printf("ESR: 0x%08lx\n", mfspr(SPR_ESR_BASE)); + hang(); +} + +void exception_handler(int vect) +{ + int exception = vect >> 8; + + if (handlers[exception]) + handlers[exception](); + else + exception_hang(vect); +} diff --git a/arch/openrisc/cpu/interrupts.c b/arch/openrisc/cpu/interrupts.c new file mode 100644 index 0000000000..8f06724279 --- /dev/null +++ b/arch/openrisc/cpu/interrupts.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/types.h> +#include <asm/ptrace.h> +#include <asm/system.h> +#include <asm/openrisc_exc.h> + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + int count; +}; + +static struct irq_action handlers[32]; + +void interrupt_handler(void) +{ + int irq; + + while ((irq = ffs(mfspr(SPR_PICSR)))) { + if (handlers[--irq].handler) { + handlers[irq].handler(handlers[irq].arg); + handlers[irq].count++; + } else { + /* disable the interrupt */ + mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1 << irq)); + printf("Unhandled interrupt: %d\n", irq); + } + /* clear the interrupt */ + mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1 << irq)); + } +} + +int interrupt_init(void) +{ + /* install handler for external interrupt exception */ + exception_install_handler(EXC_EXT_IRQ, interrupt_handler); + /* Enable interrupts in supervisor register */ + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); + + return 0; +} + +void enable_interrupts(void) +{ + /* Set interrupt enable bit in supervisor register */ + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE); + /* Enable timer exception */ + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE); +} + +int disable_interrupts(void) +{ + /* Clear interrupt enable bit in supervisor register */ + mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE); + /* Disable timer exception */ + mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_TEE); + + return 0; +} + +void irq_install_handler(int irq, interrupt_handler_t *handler, void *arg) +{ + if (irq < 0 || irq > 31) + return; + + handlers[irq].handler = handler; + handlers[irq].arg = arg; +} + +void irq_free_handler(int irq) +{ + if (irq < 0 || irq > 31) + return; + + handlers[irq].handler = 0; + handlers[irq].arg = 0; +} + +#if defined(CONFIG_CMD_IRQ) +int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + + printf("\nInterrupt-Information:\n\n"); + printf("Nr Routine Arg Count\n"); + printf("-----------------------------\n"); + + for (i = 0; i < 32; i++) { + if (handlers[i].handler) { + printf("%02d %08lx %08lx %d\n", + i, + (ulong)handlers[i].handler, + (ulong)handlers[i].arg, + handlers[i].count); + } + } + printf("\n"); + + return 0; +} +#endif diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S new file mode 100644 index 0000000000..3a4271750e --- /dev/null +++ b/arch/openrisc/cpu/start.S @@ -0,0 +1,335 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm-offsets.h> +#include <asm/spr-defs.h> + +#define EXCEPTION_STACK_SIZE (128+128) + +#define HANDLE_EXCEPTION \ + l.addi r1, r1, -EXCEPTION_STACK_SIZE ;\ + l.sw 0x1c(r1), r9 ;\ + l.jal _exception_handler ;\ + l.nop ;\ + l.lwz r9, 0x1c(r1) ;\ + l.addi r1, r1, EXCEPTION_STACK_SIZE ;\ + l.rfe ;\ + l.nop + + .section .vectors, "ax" + .global __reset + + /* reset */ + .org 0x100 +__reset: + /* there is no guarantee r0 is hardwired to zero, clear it here */ + l.andi r0, r0, 0 + /* reset stack and frame pointers */ + l.andi r1, r0, 0 + l.andi r2, r0, 0 + + /* set supervisor mode */ + l.ori r3,r0,SPR_SR_SM + l.mtspr r0,r3,SPR_SR + + /* Relocate u-boot */ + l.movhi r3,hi(__start) /* source start address */ + l.ori r3,r3,lo(__start) + l.movhi r4,hi(_stext) /* dest start address */ + l.ori r4,r4,lo(_stext) + l.movhi r5,hi(__end) /* dest end address */ + l.ori r5,r5,lo(__end) + +.L_reloc: + l.lwz r6,0(r3) + l.sw 0(r4),r6 + l.addi r3,r3,4 + l.sfltu r4,r5 + l.bf .L_reloc + l.addi r4,r4,4 /* delay slot */ + +#ifdef CONFIG_SYS_RELOCATE_VECTORS + /* Relocate vectors from 0xf0000000 to 0x00000000 */ + l.movhi r4, 0xf000 /* source */ + l.movhi r5, 0 /* destination */ + l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */ +.L_relocvectors: + l.lwz r7, 0(r4) + l.sw 0(r5), r7 + l.addi r5, r5, 4 + l.sfeq r5,r6 + l.bnf .L_relocvectors + l.addi r4,r4, 4 +#endif + + l.j _start + l.nop + + /* bus error */ + .org 0x200 + HANDLE_EXCEPTION + + /* data page fault */ + .org 0x300 + HANDLE_EXCEPTION + + /* instruction page fault */ + .org 0x400 + HANDLE_EXCEPTION + + /* tick timer */ + .org 0x500 + HANDLE_EXCEPTION + + /* alignment */ + .org 0x600 + HANDLE_EXCEPTION + + /* illegal instruction */ + .org 0x700 + HANDLE_EXCEPTION + + /* external interrupt */ + .org 0x800 + HANDLE_EXCEPTION + + /* D-TLB miss */ + .org 0x900 + HANDLE_EXCEPTION + + /* I-TLB miss */ + .org 0xa00 + HANDLE_EXCEPTION + + /* range */ + .org 0xb00 + HANDLE_EXCEPTION + + /* system call */ + .org 0xc00 + HANDLE_EXCEPTION + + /* floating point */ + .org 0xd00 + HANDLE_EXCEPTION + + /* trap */ + .org 0xe00 + HANDLE_EXCEPTION + + /* reserved */ + .org 0xf00 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1100 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1200 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1300 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1400 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1500 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1600 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1700 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1800 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1900 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1a00 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1b00 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1c00 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1d00 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1e00 + HANDLE_EXCEPTION + + /* reserved */ + .org 0x1f00 + HANDLE_EXCEPTION + + /* Startup routine */ + .text + .global _start +_start: + /* Init stack and frame pointers */ + l.movhi r1, hi(CONFIG_SYS_INIT_SP_ADDR) + l.ori r1, r1, lo(CONFIG_SYS_INIT_SP_ADDR) + l.or r2, r0, r1 + + /* clear BSS segments */ + l.movhi r4, hi(_bss_start) + l.ori r4, r4, lo(_bss_start) + l.movhi r5, hi(_bss_end) + l.ori r5, r5, lo(_bss_end) +.L_clear_bss: + l.sw 0(r4), r0 + l.sfltu r4,r5 + l.bf .L_clear_bss + l.addi r4,r4,4 + + /* Reset registers before jumping to board_init */ + l.andi r3, r0, 0 + l.andi r4, r0, 0 + l.andi r5, r0, 0 + l.andi r6, r0, 0 + l.andi r7, r0, 0 + l.andi r8, r0, 0 + l.andi r9, r0, 0 + l.andi r10, r0, 0 + l.andi r11, r0, 0 + l.andi r12, r0, 0 + l.andi r13, r0, 0 + l.andi r14, r0, 0 + l.andi r15, r0, 0 + l.andi r17, r0, 0 + l.andi r18, r0, 0 + l.andi r19, r0, 0 + l.andi r20, r0, 0 + l.andi r21, r0, 0 + l.andi r22, r0, 0 + l.andi r23, r0, 0 + l.andi r24, r0, 0 + l.andi r25, r0, 0 + l.andi r26, r0, 0 + l.andi r27, r0, 0 + l.andi r28, r0, 0 + l.andi r29, r0, 0 + l.andi r30, r0, 0 + l.andi r31, r0, 0 + + l.j board_init + l.nop + + .size _start, .-_start + +/* + * Store state onto stack and call the real exception handler + */ + .section .text + .extern exception_handler + .type _exception_handler,@function + +_exception_handler: + /* Store state (r9 already saved)*/ + l.sw 0x00(r1), r2 + l.sw 0x04(r1), r3 + l.sw 0x08(r1), r4 + l.sw 0x0c(r1), r5 + l.sw 0x10(r1), r6 + l.sw 0x14(r1), r7 + l.sw 0x18(r1), r8 + l.sw 0x20(r1), r10 + l.sw 0x24(r1), r11 + l.sw 0x28(r1), r12 + l.sw 0x2c(r1), r13 + l.sw 0x30(r1), r14 + l.sw 0x34(r1), r15 + l.sw 0x38(r1), r16 + l.sw 0x3c(r1), r17 + l.sw 0x40(r1), r18 + l.sw 0x44(r1), r19 + l.sw 0x48(r1), r20 + l.sw 0x4c(r1), r21 + l.sw 0x50(r1), r22 + l.sw 0x54(r1), r23 + l.sw 0x58(r1), r24 + l.sw 0x5c(r1), r25 + l.sw 0x60(r1), r26 + l.sw 0x64(r1), r27 + l.sw 0x68(r1), r28 + l.sw 0x6c(r1), r29 + l.sw 0x70(r1), r30 + l.sw 0x74(r1), r31 + + /* Save return address */ + l.or r14, r0, r9 + /* Call exception handler with the link address as argument */ + l.jal exception_handler + l.or r3, r0, r14 + /* Load return address */ + l.or r9, r0, r14 + + /* Restore state */ + l.lwz r2, 0x00(r1) + l.lwz r3, 0x04(r1) + l.lwz r4, 0x08(r1) + l.lwz r5, 0x0c(r1) + l.lwz r6, 0x10(r1) + l.lwz r7, 0x14(r1) + l.lwz r8, 0x18(r1) + l.lwz r10, 0x20(r1) + l.lwz r11, 0x24(r1) + l.lwz r12, 0x28(r1) + l.lwz r13, 0x2c(r1) + l.lwz r14, 0x30(r1) + l.lwz r15, 0x34(r1) + l.lwz r16, 0x38(r1) + l.lwz r17, 0x3c(r1) + l.lwz r18, 0x40(r1) + l.lwz r19, 0x44(r1) + l.lwz r20, 0x48(r1) + l.lwz r21, 0x4c(r1) + l.lwz r22, 0x50(r1) + l.lwz r23, 0x54(r1) + l.lwz r24, 0x58(r1) + l.lwz r25, 0x5c(r1) + l.lwz r26, 0x60(r1) + l.lwz r27, 0x64(r1) + l.lwz r28, 0x68(r1) + l.lwz r29, 0x6c(r1) + l.lwz r30, 0x70(r1) + l.lwz r31, 0x74(r1) + l.jr r9 + l.nop diff --git a/arch/openrisc/include/asm/bitops.h b/arch/openrisc/include/asm/bitops.h new file mode 100644 index 0000000000..c001a5d1f6 --- /dev/null +++ b/arch/openrisc/include/asm/bitops.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_OPENRISC_BITOPS_H +#define __ASM_OPENRISC_BITOPS_H + +#define PLATFORM_FLS +#include <asm/bitops/fls.h> +#define PLATFORM_FFS +#include <asm/bitops/ffs.h> + +#endif /* __ASM_GENERIC_BITOPS_H */ diff --git a/arch/openrisc/include/asm/bitops/ffs.h b/arch/openrisc/include/asm/bitops/ffs.h new file mode 100644 index 0000000000..1de5295816 --- /dev/null +++ b/arch/openrisc/include/asm/bitops/ffs.h @@ -0,0 +1,26 @@ +/* + * OpenRISC Linux + * + * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_OPENRISC_FFS_H +#define __ASM_OPENRISC_FFS_H + +static inline int ffs(int x) +{ + int ret; + + __asm__ ("l.ff1 %0,%1" + : "=r" (ret) + : "r" (x)); + + return ret; +} + +#endif /* __ASM_OPENRISC_FFS_H */ diff --git a/arch/openrisc/include/asm/bitops/fls.h b/arch/openrisc/include/asm/bitops/fls.h new file mode 100644 index 0000000000..8c77c13776 --- /dev/null +++ b/arch/openrisc/include/asm/bitops/fls.h @@ -0,0 +1,26 @@ +/* + * OpenRISC Linux + * + * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_OPENRISC_FLS_H +#define __ASM_OPENRISC_FLS_H + +static inline int fls(int x) +{ + int ret; + + __asm__ ("l.fl1 %0,%1" + : "=r" (ret) + : "r" (x)); + + return ret; +} + +#endif /* __ASM_OPENRISC_FLS_H */ diff --git a/arch/openrisc/include/asm/byteorder.h b/arch/openrisc/include/asm/byteorder.h new file mode 100644 index 0000000000..60d14f7e14 --- /dev/null +++ b/arch/openrisc/include/asm/byteorder.h @@ -0,0 +1 @@ +#include <linux/byteorder/big_endian.h> diff --git a/arch/openrisc/include/asm/cache.h b/arch/openrisc/include/asm/cache.h new file mode 100644 index 0000000000..0faaec725a --- /dev/null +++ b/arch/openrisc/include/asm/cache.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_OPENRISC_CACHE_H_ +#define __ASM_OPENRISC_CACHE_H_ + +/* + * Valid L1 data cache line sizes for the OpenRISC architecture are + * 16 and 32 bytes. + * If the board configuration has not specified one we default to the + * largest of these values for alignment of DMA buffers. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + +#endif /* __ASM_OPENRISC_CACHE_H_ */ diff --git a/arch/openrisc/include/asm/config.h b/arch/openrisc/include/asm/config.h new file mode 100644 index 0000000000..049c44eaf8 --- /dev/null +++ b/arch/openrisc/include/asm/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/arch/openrisc/include/asm/errno.h b/arch/openrisc/include/asm/errno.h new file mode 100644 index 0000000000..4c82b503d9 --- /dev/null +++ b/arch/openrisc/include/asm/errno.h @@ -0,0 +1 @@ +#include <asm-generic/errno.h> diff --git a/arch/openrisc/include/asm/global_data.h b/arch/openrisc/include/asm/global_data.h new file mode 100644 index 0000000000..36de9d0a4d --- /dev/null +++ b/arch/openrisc/include/asm/global_data.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Yasushi SHOJI <yashi@atmark-techno.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GBL_DATA_H +#define __ASM_GBL_DATA_H +/* + * The following data structure is placed in some memory wich is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) + */ + +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long have_console; /* serial_init() was called */ + phys_size_t ram_size; /* RAM size */ + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + unsigned long fb_base; /* base address of frame buffer */ + void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ +} gd_t; + +/* + * Global Data Flags + */ +/* Code was relocated to RAM */ +#define GD_FLG_RELOC 0x00001 +/* Devices have been initialized */ +#define GD_FLG_DEVINIT 0x00002 +/* Silent mode */ +#define GD_FLG_SILENT 0x00004 +/* Critical POST test failed */ +#define GD_FLG_POSTFAIL 0x00008 +/* POST seqeunce aborted */ +#define GD_FLG_POSTSTOP 0x00010 +/* Log Buffer has been initialized */ +#define GD_FLG_LOGINIT 0x00020 +/* Disable console (in & out) */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 +/* Environment imported into hash table */ +#define GD_FLG_ENV_READY 0x00080 + +/* OR32 GCC already has r10 set as fixed-use */ +#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r10") + +#endif /* __ASM_GBL_DATA_H */ diff --git a/arch/openrisc/include/asm/gpio.h b/arch/openrisc/include/asm/gpio.h new file mode 100644 index 0000000000..8c0cc8049e --- /dev/null +++ b/arch/openrisc/include/asm/gpio.h @@ -0,0 +1,84 @@ +/* + * OpenRISC gpio driver + * + * Copyright (C) 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * + * based on nios2 gpio driver + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * when CONFIG_SYS_GPIO_BASE is not defined, board may provide + * its own driver. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef CONFIG_SYS_GPIO_BASE +#include <asm/io.h> + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline int gpio_free(unsigned gpio) +{ + return 0; +} + +static inline int gpio_get_value(unsigned gpio) +{ + return (readb(CONFIG_SYS_GPIO_BASE + gpio/8) >> gpio%8) & 0x1; +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + u8 tmp = readb(CONFIG_SYS_GPIO_BASE + gpio/8); + + if (value) + tmp |= (1 << gpio%8); + else + tmp &= ~(1 << gpio%8); + writeb(tmp, CONFIG_SYS_GPIO_BASE + gpio/8); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 0); + + return 0; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + gpio_set_value(gpio + CONFIG_SYS_GPIO_WIDTH, 1); + gpio_set_value(gpio, value); + + return 0; +} + +static inline int gpio_is_valid(int number) +{ + return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH; +} +#else +extern int gpio_request(unsigned gpio, const char *label); +extern int gpio_free(unsigned gpio); +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); +extern int gpio_get_value(unsigned gpio); +extern void gpio_set_value(unsigned gpio, int value); +extern int gpio_is_valid(int number); +#endif /* CONFIG_SYS_GPIO_BASE */ diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h new file mode 100644 index 0000000000..3524f91f35 --- /dev/null +++ b/arch/openrisc/include/asm/io.h @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_OPENRISC_IO_H +#define __ASM_OPENRISC_IO_H + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ + +} + +/* + * Change virtual addresses to physical addresses + */ +static inline phys_addr_t virt_to_phys(void *vaddr) +{ + return (phys_addr_t)(vaddr); +} + + +/* + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the openrisc architecture, we just read/write the + * memory location directly. + */ +#define readb(addr) (*(volatile unsigned char *) (addr)) +#define readw(addr) (*(volatile unsigned short *) (addr)) +#define readl(addr) (*(volatile unsigned int *) (addr)) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +#define writeb(b, addr) ((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b, addr) ((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b, addr) ((*(volatile unsigned int *) (addr)) = (b)) +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define memset_io(a, b, c) memset((void *)(a), (b), (c)) +#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) +#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) + +/* + * Again, OpenRISC does not require mem IO specific function. + */ + + +#define IO_BASE 0x0 +#define IO_SPACE_LIMIT 0xffffffff + +#define inb(port) readb((port + IO_BASE)) +#define outb(value, port) writeb((value), (port + IO_BASE)) +#define inb_p(port) inb((port)) +#define outb_p(value, port) outb((value), (port)) + +/* + * Convert a physical pointer to a virtual kernel pointer for /dev/mem + * access + */ +#define xlate_dev_mem_ptr(p) __va(p) + +/* + * Convert a virtual cached pointer to an uncached pointer + */ +#define xlate_dev_kmem_ptr(p) p + +#define ioread8(addr) readb(addr) +#define ioread16(addr) readw(addr) +#define ioread32(addr) readl(addr) + +#define iowrite8(v, addr) writeb((v), (addr)) +#define iowrite16(v, addr) writew((v), (addr)) +#define iowrite32(v, addr) writel((v), (addr)) + +#endif diff --git a/arch/openrisc/include/asm/openrisc_exc.h b/arch/openrisc/include/asm/openrisc_exc.h new file mode 100644 index 0000000000..33f64538f8 --- /dev/null +++ b/arch/openrisc/include/asm/openrisc_exc.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OPENRISC_EXC_H_ +#define _OPENRISC_EXC_H_ + +#define EXC_RESET 0x01 +#define EXC_BUS_ERROR 0x02 +#define EXC_DATA_PAGE_FAULT 0x03 +#define EXC_INSTR_PAGE_FAULT 0x04 +#define EXC_TIMER 0x05 +#define EXC_ALIGNMENT 0x06 +#define EXC_ILLEGAL_INSTR 0x07 +#define EXC_EXT_IRQ 0x08 +#define EXC_DTLB_MISS 0x09 +#define EXC_ITLB_MISS 0x0a +#define EXC_RANGE 0x0b +#define EXC_SYSCALL 0x0c +#define EXC_FLOAT_POINT 0x0d +#define EXC_TRAP 0x0e + +void exception_install_handler(int exception, void (*handler)(void)); +void exception_free_handler(int exception); + +#endif diff --git a/arch/openrisc/include/asm/posix_types.h b/arch/openrisc/include/asm/posix_types.h new file mode 100644 index 0000000000..d1fffe0374 --- /dev/null +++ b/arch/openrisc/include/asm/posix_types.h @@ -0,0 +1,72 @@ +/* + * Based on microblaze implementation: + * Copyright (C) 2003 John Williams <jwilliams@itee.uq.edu.au> + * Copyright (C) 2001,2002 NEC Corporation + * Copyright (C) 2001,2002 Miles Bader <miles@gnu.org> + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file COPYING in the main directory of this + * archive for more details. + * + * Written by Miles Bader <miles@gnu.org> + * Microblaze port by John Williams + */ + +#ifndef __ASM_OPENRISC_POSIX_TYPES_H +#define __ASM_OPENRISC_POSIX_TYPES_H + +typedef unsigned int __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned long long __kernel_ino64_t; +typedef unsigned int __kernel_mode_t; +typedef unsigned int __kernel_nlink_t; +typedef long __kernel_off_t; +typedef long long __kernel_loff_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char *__kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fd_set) \ + __set_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_CLR +#define __FD_CLR(fd, fd_set) \ + __clear_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_ISSET +#define __FD_ISSET(fd, fd_set) \ + __test_bit(fd, (void *)&((__kernel_fd_set *)fd_set)->fds_bits) +#undef __FD_ZERO +#define __FD_ZERO(fd_set) \ + memset(fd_set, 0, sizeof(*(fd_set *)fd_set)) + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __ASM_OPENRISC_POSIX_TYPES_H */ diff --git a/arch/openrisc/include/asm/processor.h b/arch/openrisc/include/asm/processor.h new file mode 100644 index 0000000000..304c95fb3a --- /dev/null +++ b/arch/openrisc/include/asm/processor.h @@ -0,0 +1,4 @@ +#ifndef __ASM_OPENRISC_PROCESSOR_H +#define __ASM_OPENRISC_PROCESSOR_H + +#endif diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h new file mode 100644 index 0000000000..ffdea52925 --- /dev/null +++ b/arch/openrisc/include/asm/ptrace.h @@ -0,0 +1,131 @@ +/* + * OpenRISC Linux + * + * Linux architectural port borrowing liberally from similar works of + * others. All original copyrights apply as per the original source + * declaration. + * + * OpenRISC implementation: + * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> + * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> + * et al. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __ASM_OPENRISC_PTRACE_H +#define __ASM_OPENRISC_PTRACE_H + +#include <asm/spr-defs.h> + +#ifndef __ASSEMBLY__ +/* + * This is the layout of the regset returned by the GETREGSET ptrace call + */ +struct user_regs_struct { + /* GPR R0-R31... */ + unsigned long gpr[32]; + unsigned long pc; + unsigned long sr; + unsigned long pad1; + unsigned long pad2; +}; +#endif + +#ifdef __KERNEL__ + +/* + * Make kernel PTrace/register structures opaque to userspace... userspace can + * access thread state via the regset mechanism. This allows us a bit of + * flexibility in how we order the registers on the stack, permitting some + * optimizations like packing call-clobbered registers together so that + * they share a cacheline (not done yet, though... future optimization). + */ + +#ifndef __ASSEMBLY__ +/* + * This struct describes how the registers are laid out on the kernel stack + * during a syscall or other kernel entry. + * + * This structure should always be cacheline aligned on the stack. + * FIXME: I don't think that's the case right now. The alignment is + * taken care of elsewhere... head.S, process.c, etc. + */ + +struct pt_regs { + union { + struct { + /* Named registers */ + long sr; /* Stored in place of r0 */ + long sp; /* r1 */ + }; + struct { + /* Old style */ + long offset[2]; + long gprs[30]; + }; + struct { + /* New style */ + long gpr[32]; + }; + }; + long pc; + long orig_gpr11; /* For restarting system calls */ + long syscallno; /* Syscall number (used by strace) */ + long dummy; /* Cheap alignment fix */ +}; +#endif /* __ASSEMBLY__ */ + +/* TODO: Rename this to REDZONE because that's what it is */ +#define STACK_FRAME_OVERHEAD 128 /* size of minimum stack frame */ + +#define instruction_pointer(regs) ((regs)->pc) +#define user_mode(regs) (((regs)->sr & SPR_SR_SM) == 0) +#define user_stack_pointer(regs) ((unsigned long)(regs)->sp) +#define profile_pc(regs) instruction_pointer(regs) + +/* + * Offsets used by 'ptrace' system call interface. + */ +#define PT_SR 0 +#define PT_SP 4 +#define PT_GPR2 8 +#define PT_GPR3 12 +#define PT_GPR4 16 +#define PT_GPR5 20 +#define PT_GPR6 24 +#define PT_GPR7 28 +#define PT_GPR8 32 +#define PT_GPR9 36 +#define PT_GPR10 40 +#define PT_GPR11 44 +#define PT_GPR12 48 +#define PT_GPR13 52 +#define PT_GPR14 56 +#define PT_GPR15 60 +#define PT_GPR16 64 +#define PT_GPR17 68 +#define PT_GPR18 72 +#define PT_GPR19 76 +#define PT_GPR20 80 +#define PT_GPR21 84 +#define PT_GPR22 88 +#define PT_GPR23 92 +#define PT_GPR24 96 +#define PT_GPR25 100 +#define PT_GPR26 104 +#define PT_GPR27 108 +#define PT_GPR28 112 +#define PT_GPR29 116 +#define PT_GPR30 120 +#define PT_GPR31 124 +#define PT_PC 128 +#define PT_ORIG_GPR11 132 +#define PT_SYSCALLNO 136 + +#endif /* __KERNEL__ */ + +#endif /* __ASM_OPENRISC_PTRACE_H */ diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h new file mode 100644 index 0000000000..cb0cdfa7fe --- /dev/null +++ b/arch/openrisc/include/asm/spr-defs.h @@ -0,0 +1,567 @@ +/* + * SPR Definitions + * + * Copyright (C) 2000 Damjan Lampret + * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> + * Copyright (C) 2008, 2010 Embecosm Limited + * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> + * et al. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file is part of OpenRISC 1000 Architectural Simulator. + */ + +#ifndef SPR_DEFS__H +#define SPR_DEFS__H + +/* Definition of special-purpose registers (SPRs) */ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) +#define SPR_SR (SPRGROUP_SYS + 17) +#define SPR_PPC (SPRGROUP_SYS + 18) +#define SPR_FPCSR (SPRGROUP_SYS + 20) +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) +#define SPR_GPR_BASE (SPRGROUP_SYS + 1024) + +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBEIR (SPRGROUP_DMMU + 2) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBEIR (SPRGROUP_IMMU + 2) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) + +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + */ +#define SPR_VR_VER 0xff000000 /* Processor version */ +#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */ +#define SPR_VR_RES 0x0000ffc0 /* Reserved */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +#define SPR_VR_VER_OFF 24 +#define SPR_VR_CFG_OFF 16 +#define SPR_VR_REV_OFF 0 + +/* + * Bit definitions for the Unit Present Register + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_MP 0x00000020 /* MAC present */ +#define SPR_UPR_DUP 0x00000040 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00000100 /* Power management present */ +#define SPR_UPR_PICP 0x00000200 /* PIC present */ +#define SPR_UPR_TTP 0x00000400 /* Tick timer present */ +#define SPR_UPR_RES 0x00fe0000 /* Reserved */ +#define SPR_UPR_CUP 0xff000000 /* Context units present */ + +/* + * Bit definitions for the CPU configuration register + */ +#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */ +#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */ +#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */ +#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */ +#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ +#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ +#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ +#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ + +/* + * Bit definitions for the Debug configuration register and other + * constants. + */ + +#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */ +#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */ +#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */ +#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */ +#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */ +#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */ +#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */ +#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */ +#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */ +#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */ + +#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \ + 2 == n ? SPR_DCFGR_NDP2 : \ + 3 == n ? SPR_DCFGR_NDP3 : \ + 4 == n ? SPR_DCFGR_NDP4 : \ + 5 == n ? SPR_DCFGR_NDP5 : \ + 6 == n ? SPR_DCFGR_NDP6 : \ + 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8) +#define MAX_MATCHPOINTS 8 +#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2) + +/* + * Bit definitions for the Supervision Register + */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ +#define SPR_SR_RES 0x0ffe0000 /* Reserved */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ + +/* + * Bit definitions for the Data MMU Control Register + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for the Instruction TLB Match Register + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for Data Cache Control register + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Data Cache Configuration Register + */ + +#define SPR_DCCFGR_NCW 0x00000007 +#define SPR_DCCFGR_NCS 0x00000078 +#define SPR_DCCFGR_CBS 0x00000080 +#define SPR_DCCFGR_CWS 0x00000100 +#define SPR_DCCFGR_CCRI 0x00000200 +#define SPR_DCCFGR_CBIRI 0x00000400 +#define SPR_DCCFGR_CBPRI 0x00000800 +#define SPR_DCCFGR_CBLRI 0x00001000 +#define SPR_DCCFGR_CBFRI 0x00002000 +#define SPR_DCCFGR_CBWBRI 0x00004000 + +#define SPR_DCCFGR_NCW_OFF 0 +#define SPR_DCCFGR_NCS_OFF 3 +#define SPR_DCCFGR_CBS_OFF 7 + +/* + * Bit definitions for Instruction Cache Configuration Register + */ +#define SPR_ICCFGR_NCW 0x00000007 +#define SPR_ICCFGR_NCS 0x00000078 +#define SPR_ICCFGR_CBS 0x00000080 +#define SPR_ICCFGR_CCRI 0x00000200 +#define SPR_ICCFGR_CBIRI 0x00000400 +#define SPR_ICCFGR_CBPRI 0x00000800 +#define SPR_ICCFGR_CBLRI 0x00001000 + +#define SPR_ICCFGR_NCW_OFF 0 +#define SPR_ICCFGR_NCS_OFF 3 +#define SPR_ICCFGR_CBS_OFF 7 + +/* + * Bit definitions for Data MMU Configuration Register + */ +#define SPR_DMMUCFGR_NTW 0x00000003 +#define SPR_DMMUCFGR_NTS 0x0000001C +#define SPR_DMMUCFGR_NAE 0x000000E0 +#define SPR_DMMUCFGR_CRI 0x00000100 +#define SPR_DMMUCFGR_PRI 0x00000200 +#define SPR_DMMUCFGR_TEIRI 0x00000400 +#define SPR_DMMUCFGR_HTR 0x00000800 + +#define SPR_DMMUCFGR_NTW_OFF 0 +#define SPR_DMMUCFGR_NTS_OFF 2 + +/* + * Bit definitions for Instruction MMU Configuration Register + */ +#define SPR_IMMUCFGR_NTW 0x00000003 +#define SPR_IMMUCFGR_NTS 0x0000001C +#define SPR_IMMUCFGR_NAE 0x000000E0 +#define SPR_IMMUCFGR_CRI 0x00000100 +#define SPR_IMMUCFGR_PRI 0x00000200 +#define SPR_IMMUCFGR_TEIRI 0x00000400 +#define SPR_IMMUCFGR_HTR 0x00000800 + +#define SPR_IMMUCFGR_NTW_OFF 0 +#define SPR_IMMUCFGR_NTS_OFF 2 + +/* + * Bit definitions for Debug Control registers + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000002 +#define SPR_DCR_CC_LESS 0x00000004 +#define SPR_DCR_CC_LESSE 0x00000006 +#define SPR_DCR_CC_GREAT 0x00000008 +#define SPR_DCR_CC_GREATE 0x0000000a +#define SPR_DCR_CC_NEQUAL 0x0000000c + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 +#define SPR_DCR_CT_LSD 0x000000e0 + +/* + * Bit definitions for Debug Mode 1 register + */ +#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */ +#define SPR_DMR1_CW0_AND 0x00000001 +#define SPR_DMR1_CW0_OR 0x00000002 +#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR) +#define SPR_DMR1_CW1_AND 0x00000004 +#define SPR_DMR1_CW1_OR 0x00000008 +#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR) +#define SPR_DMR1_CW2_AND 0x00000010 +#define SPR_DMR1_CW2_OR 0x00000020 +#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR) +#define SPR_DMR1_CW3_AND 0x00000040 +#define SPR_DMR1_CW3_OR 0x00000080 +#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR) +#define SPR_DMR1_CW4_AND 0x00000100 +#define SPR_DMR1_CW4_OR 0x00000200 +#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR) +#define SPR_DMR1_CW5_AND 0x00000400 +#define SPR_DMR1_CW5_OR 0x00000800 +#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR) +#define SPR_DMR1_CW6_AND 0x00001000 +#define SPR_DMR1_CW6_OR 0x00002000 +#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR) +#define SPR_DMR1_CW7_AND 0x00004000 +#define SPR_DMR1_CW7_OR 0x00008000 +#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR) +#define SPR_DMR1_CW8_AND 0x00010000 +#define SPR_DMR1_CW8_OR 0x00020000 +#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR) +#define SPR_DMR1_CW9_AND 0x00040000 +#define SPR_DMR1_CW9_OR 0x00080000 +#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR) +#define SPR_DMR1_RES1 0x00300000 /* Reserved */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_RES2 0xff000000 /* Reserved */ + +/* + * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */ +#define SPR_DMR2_WGB 0x003ff000 /* Watch generating breakpoint */ +#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */ +#define SPR_DMR2_WBS 0xffc00000 /* Watchpoint status */ +#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */ + +/* + * Bit definitions for Debug watchpoint counter registers + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ +#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */ +#define SPR_DRR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit definitions for Tick Timer Control Register + */ +#define SPR_TTCR_CNT 0xffffffff /* Count, time period */ +#define SPR_TTMR_TP 0x0fffffff /* Time period */ +#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ +#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ +#define SPR_TTMR_DI 0x00000000 /* Disabled */ +#define SPR_TTMR_RT 0x40000000 /* Restart tick */ +#define SPR_TTMR_SR 0x80000000 /* Single run */ +#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ +#define SPR_TTMR_M 0xc0000000 /* Tick mode */ + +/* + * Bit definitions for the FP Control Status Register + */ +#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */ +#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */ +#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */ +#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */ +#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */ +#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */ +#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */ +#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */ +#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */ +#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */ +#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */ +#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \ + SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \ + SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF) + +#define FPCSR_RM_RN (0<<1) +#define FPCSR_RM_RZ (1<<1) +#define FPCSR_RM_RIP (2<<1) +#define FPCSR_RM_RIN (3<<1) + +/* + * l.nop constants + */ +#define NOP_NOP 0x0000 /* Normal nop instruction */ +#define NOP_EXIT 0x0001 /* End of simulation */ +#define NOP_REPORT 0x0002 /* Simple report */ +#define NOP_PUTC 0x0004 /* Simputc instruction */ +#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ +#define NOP_GET_TICKS 0x0006 /* Get # ticks running */ +#define NOP_GET_PS 0x0007 /* Get picosecs/cycle */ +#define NOP_REPORT_FIRST 0x0400 /* Report with number */ +#define NOP_REPORT_LAST 0x03ff /* Report with number */ + +#endif /* SPR_DEFS__H */ diff --git a/arch/openrisc/include/asm/string.h b/arch/openrisc/include/asm/string.h new file mode 100644 index 0000000000..73e265564a --- /dev/null +++ b/arch/openrisc/include/asm/string.h @@ -0,0 +1,4 @@ +#ifndef __ASM_OPENRISC_STRING_H +#define __ASM_OPENRISC_STRING_H + +#endif diff --git a/arch/openrisc/include/asm/system.h b/arch/openrisc/include/asm/system.h new file mode 100644 index 0000000000..d68036325a --- /dev/null +++ b/arch/openrisc/include/asm/system.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_OPENRISC_SYSTEM_H +#define __ASM_OPENRISC_SYSTEM_H + +#include <asm/spr-defs.h> + +static inline unsigned long mfspr(unsigned long add) +{ + unsigned long ret; + + __asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add)); + + return ret; +} + +static inline void mtspr(unsigned long add, unsigned long val) +{ + __asm__ __volatile__ ("l.mtspr r0,%1,%0" : : "K" (add), "r" (val)); +} + +#endif /* __ASM_OPENRISC_SYSTEM_H */ diff --git a/arch/openrisc/include/asm/types.h b/arch/openrisc/include/asm/types.h new file mode 100644 index 0000000000..01867bbd81 --- /dev/null +++ b/arch/openrisc/include/asm/types.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_TYPES_H +#define _ASM_TYPES_H + +/* + * This file is never included by application software unless + * explicitly requested (e.g., via linux/types.h) in which case the + * application is Linux specific so (user-) name space pollution is + * not a major issue. However, for interoperability, libraries still + * need to be careful to avoid a name clashes. + */ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) +__extension__ typedef __signed__ long long __s64; +__extension__ typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif /* __KERNEL__ */ + +#endif /* _ASM_TYPES_H */ diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h new file mode 100644 index 0000000000..2913994932 --- /dev/null +++ b/arch/openrisc/include/asm/u-boot.h @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _U_BOOT_H_ +#define _U_BOOT_H_ + +typedef struct bd_info { + unsigned long bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned long bi_arch_number; /* unique id for this board */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ +} bd_t; + +#define IH_ARCH_DEFAULT IH_ARCH_OPENRISC + +#endif /* _U_BOOT_H_ */ diff --git a/arch/openrisc/include/asm/unaligned.h b/arch/openrisc/include/asm/unaligned.h new file mode 100644 index 0000000000..6cecbbb211 --- /dev/null +++ b/arch/openrisc/include/asm/unaligned.h @@ -0,0 +1 @@ +#include <asm-generic/unaligned.h> diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile new file mode 100644 index 0000000000..db3c657070 --- /dev/null +++ b/arch/openrisc/lib/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(ARCH).o + +SOBJS-y += + +COBJS-y += board.o +COBJS-y += bootm.o +COBJS-y += timer.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c new file mode 100644 index 0000000000..85aa1899be --- /dev/null +++ b/arch/openrisc/lib/board.c @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2011 + * Julius Baxter, julius@opencores.org + * + * (C) Copyright 2003, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <stdio_dev.h> +#include <watchdog.h> +#include <malloc.h> +#include <mmc.h> +#include <net.h> +#ifdef CONFIG_STATUS_LED +#include <status_led.h> +#endif +#ifdef CONFIG_CMD_NAND +#include <nand.h> /* cannot even include nand.h if it isnt configured */ +#endif + +#include <timestamp.h> +#include <version.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * All attempts to come up with a "common" initialization sequence + * that works for all boards and architectures failed: some of the + * requirements are just _too_ different. To get rid of the resulting + * mess of board dependend #ifdef'ed code we now make the whole + * initialization sequence configurable to the user. + * + * The requirements for any new initalization function is simple: it + * receives a pointer to the "global data" structure as it's only + * argument, and returns an integer return code, where 0 means + * "continue" and != 0 means "fatal error, hang the system". + */ + +extern int cache_init(void); + +/* + * Initialization sequence + */ +static int (* const init_sequence[])(void) = { + cache_init, + timer_init, /* initialize timer */ + env_init, + serial_init, + console_init_f, + display_options, + checkcpu, + checkboard, +}; + + +/***********************************************************************/ +void board_init(void) +{ + bd_t *bd; + int i; + + gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR; + + memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); + + gd->bd = (bd_t *)(gd+1); /* At end of global data */ + gd->baudrate = CONFIG_BAUDRATE; + gd->cpu_clk = CONFIG_SYS_CLK_FREQ; + + bd = gd->bd; + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; +#ifndef CONFIG_SYS_NO_FLASH + bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#endif +#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) + bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; + bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; +#endif + bd->bi_baudrate = CONFIG_BAUDRATE; + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + WATCHDOG_RESET(); + if (init_sequence[i]()) + hang(); + } + + WATCHDOG_RESET(); + + /* The Malloc area is immediately below the monitor copy in RAM */ + mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); + +#ifndef CONFIG_SYS_NO_FLASH + WATCHDOG_RESET(); + bd->bi_flashsize = flash_init(); +#endif + +#ifdef CONFIG_CMD_NAND + puts("NAND: "); + nand_init(); +#endif + +#ifdef CONFIG_GENERIC_MMC + puts("MMC: "); + mmc_initialize(bd); +#endif + + WATCHDOG_RESET(); + env_relocate(); + + WATCHDOG_RESET(); + stdio_init(); + jumptable_init(); + console_init_r(); + + WATCHDOG_RESET(); + interrupt_init(); + +#if defined(CONFIG_BOARD_LATE_INIT) + board_late_init(); +#endif + +#if defined(CONFIG_CMD_NET) + puts("NET: "); + eth_initialize(bd); +#endif + + /* main_loop */ + for (;;) { + WATCHDOG_RESET(); + main_loop(); + } +} + + +/***********************************************************************/ + +void hang(void) +{ + disable_interrupts(); + puts("### ERROR ### Please reset board ###\n"); + + for (;;) + ; +} diff --git a/arch/openrisc/lib/bootm.c b/arch/openrisc/lib/bootm.c new file mode 100644 index 0000000000..2c5d9aea99 --- /dev/null +++ b/arch/openrisc/lib/bootm.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2011 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * + * Based on microblaze implementation by: + * (C) Copyright 2007 Michal Simek + * (C) Copyright 2004 Atmark Techno, Inc. + * + * Michal SIMEK <monstr@monstr.eu> + * Yasushi SHOJI <yashi@atmark-techno.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <image.h> +#include <u-boot/zlib.h> +#include <asm/byteorder.h> + +DECLARE_GLOBAL_DATA_PTR; + +int do_bootm_linux(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*kernel) (unsigned int); + ulong rd_data_start, rd_data_end; + + if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) + return 1; + + int ret; + + char *of_flat_tree = NULL; +#if defined(CONFIG_OF_LIBFDT) + /* did generic code already find a device tree? */ + if (images->ft_len) + of_flat_tree = images->ft_addr; +#endif + + kernel = (void (*)(unsigned int))images->ep; + + /* find ramdisk */ + ret = boot_get_ramdisk(argc, argv, images, IH_ARCH_OPENRISC, + &rd_data_start, &rd_data_end); + if (ret) + return 1; + + show_boot_progress(15); + + if (!of_flat_tree && argc > 3) + of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); +#ifdef DEBUG + printf("## Transferring control to Linux (at address 0x%08lx) " \ + "ramdisk 0x%08lx, FDT 0x%08lx...\n", + (ulong) kernel, rd_data_start, (ulong) of_flat_tree); +#endif + if (dcache_status() || icache_status()) + flush_cache((ulong)kernel, max(checkdcache(), checkicache())); + + /* + * Linux Kernel Parameters (passing device tree): + * r3: pointer to the fdt, followed by the board info data + */ + kernel((unsigned int) of_flat_tree); + /* does not return */ + + return 1; +} diff --git a/arch/openrisc/lib/timer.c b/arch/openrisc/lib/timer.c new file mode 100644 index 0000000000..4e92a31159 --- /dev/null +++ b/arch/openrisc/lib/timer.c @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> + * (C) Copyright 2011, Julius Baxter <julius@opencores.org> + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/system.h> +#include <asm/openrisc_exc.h> + +static ulong timestamp; + +/* how many counter cycles in a jiffy */ +#define TIMER_COUNTER_CYCLES (CONFIG_SYS_CLK_FREQ/CONFIG_SYS_OPENRISC_TMR_HZ) +/* how many ms elapses between each timer interrupt */ +#define TIMER_TIMESTAMP_INC (1000/CONFIG_SYS_OPENRISC_TMR_HZ) +/* how many cycles per ms */ +#define TIMER_CYCLES_MS (CONFIG_SYS_CLK_FREQ/1000) +/* how many cycles per us */ +#define TIMER_CYCLES_US (CONFIG_SYS_CLK_FREQ/1000000uL) + +void timer_isr(void) +{ + timestamp += TIMER_TIMESTAMP_INC; + mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | + (TIMER_COUNTER_CYCLES & SPR_TTMR_TP)); +} + +int timer_init(void) +{ + /* Install timer exception handler */ + exception_install_handler(EXC_TIMER, timer_isr); + + /* Set up the timer for the first expiration. */ + timestamp = 0; + + mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | + (TIMER_COUNTER_CYCLES & SPR_TTMR_TP)); + + /* Enable tick timer exception in supervisor register */ + mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE); + + return 0; +} + +void reset_timer(void) +{ + timestamp = 0; + + mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | + (TIMER_COUNTER_CYCLES & SPR_TTMR_TP)); +} + +/* + * The timer value in ms is calculated by taking the + * value accumulated by full timer revolutions plus the value + * accumulated in this period + */ +ulong get_timer(ulong base) +{ + return timestamp + mfspr(SPR_TTCR)/TIMER_CYCLES_MS - base; +} + +void set_timer(ulong t) +{ + reset_timer(); + timestamp = t; +} + +void __udelay(ulong usec) +{ + ulong elapsed = 0; + ulong tick; + ulong last_tick; + + last_tick = mfspr(SPR_TTCR); + while ((elapsed / TIMER_CYCLES_US) < usec) { + tick = mfspr(SPR_TTCR); + if (tick >= last_tick) + elapsed += (tick - last_tick); + else + elapsed += TIMER_COUNTER_CYCLES - (last_tick - tick); + last_tick = tick; + } +} diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c index 587576bacf..023ac9ab30 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c @@ -28,6 +28,8 @@ void print_lbc_regs(void) printf("BR%d\t0x%08X\tOR%d\t0x%08X\n", i, get_lbc_br(i), i, get_lbc_or(i)); } + printf("LBCR\t0x%08X\tLCRR\t0x%08X\n", + get_lbc_lbcr(), get_lbc_lcrr()); } void init_early_memctl_regs(void) diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h new file mode 100644 index 0000000000..036f51e448 --- /dev/null +++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h @@ -0,0 +1,38 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MPC83XX_GPIO_H_ +#define _MPC83XX_GPIO_H_ + +/* + * The MCP83xx's 1-2 GPIO controllers each with 32 bits. + */ +#if defined(CONFIG_MPC8313) || defined(CONFIG_MPC8308) || \ + defined(CONFIG_MPC8315) +#define MPC83XX_GPIO_CTRLRS 1 +#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) +#define MPC83XX_GPIO_CTRLRS 2 +#else +#define MPC83XX_GPIO_CTRLRS 0 +#endif + +#define MAX_NUM_GPIOS (32 * MPC83XX_GPIO_CTRLRS) + +void mpc83xx_gpio_init_f(void); +void mpc83xx_gpio_init_r(void); + +#endif /* MPC83XX_GPIO_H_ */ diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index bf572b78e1..2a23d84cba 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -475,6 +475,8 @@ extern void init_early_memctl_regs(void); extern void upmconfig(uint upm, uint *table, uint size); #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr)) +#define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr)) #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) #define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or)) #define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v)) diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/gpio.h new file mode 100644 index 0000000000..d49ad080e2 --- /dev/null +++ b/arch/powerpc/include/asm/gpio.h @@ -0,0 +1,2 @@ +#include <asm/arch/gpio.h> +#include <asm-generic/gpio.h> diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c new file mode 100644 index 0000000000..97e59fb324 --- /dev/null +++ b/board/avionic-design/common/tamonten.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/board.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/uart.h> +#include <asm/arch/mmc.h> +#include "tamonten.h" + +#ifdef CONFIG_TEGRA2_MMC +#include <mmc.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +const struct tegra2_sysinfo sysinfo = { + CONFIG_TEGRA2_BOARD_STRING +}; + +/* + * Routine: timer_init + * Description: init the timestamp and lastinc value + */ +int timer_init(void) +{ + return 0; +} + +#ifdef CONFIG_TEGRA2_MMC +/* + * Routine: pin_mux_mmc + * Description: setup the pin muxes/tristate values for the SDMMC(s) + */ +static void pin_mux_mmc(void) +{ + /* SDMMC4: config 3, x8 on 2nd set of pins */ + pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4); + pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4); + pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4); + + pinmux_tristate_disable(PINGRP_ATB); + pinmux_tristate_disable(PINGRP_GMA); + pinmux_tristate_disable(PINGRP_GME); +} +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + clock_init(); + clock_verify(); + + /* boot param addr */ + gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); + + return 0; +} + +#ifdef CONFIG_TEGRA2_MMC +/* this is a weak define that we are overriding */ +int board_mmc_init(bd_t *bd) +{ + debug("board_mmc_init called\n"); + /* Enable muxes, etc. for SDMMC controllers */ + pin_mux_mmc(); + gpio_config_mmc(); + + debug("board_mmc_init: init eMMC\n"); + /* init dev 0, eMMC chip, with 4-bit bus */ + tegra2_mmc_init(0, 4, -1, GPIO_PH2); + + return 0; +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + /* Initialize selected UARTs */ + board_init_uart_f(); + return 0; +} +#endif /* EARLY_INIT */ diff --git a/board/avionic-design/common/tamonten.h b/board/avionic-design/common/tamonten.h new file mode 100644 index 0000000000..0e60b0fadc --- /dev/null +++ b/board/avionic-design/common/tamonten.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TAMONTEN_H_ +#define _TAMONTEN_H_ + +void tegra2_start(void); +void gpio_config_mmc(void); + +#endif /* TAMONTEN_H */ diff --git a/board/avionic-design/medcom/Makefile b/board/avionic-design/medcom/Makefile new file mode 100644 index 0000000000..b0c318c439 --- /dev/null +++ b/board/avionic-design/medcom/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# (C) Copyright 2011 +# Avionic Design GmbH <www.avionic-design.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +COBJS += ../common/tamonten.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/avionic-design/medcom/medcom.c b/board/avionic-design/medcom/medcom.c new file mode 100644 index 0000000000..42c80940c1 --- /dev/null +++ b/board/avionic-design/medcom/medcom.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/tegra2.h> +#ifdef CONFIG_TEGRA2_MMC +#include <mmc.h> +#endif + +#ifdef CONFIG_TEGRA2_MMC +/* + * Routine: gpio_config_mmc + * Description: Set GPIOs for SD card + */ +void gpio_config_mmc(void) +{ + /* configure pin as input for card detect */ + gpio_request(GPIO_PH2, "SD4 CD"); + gpio_direction_input(GPIO_PH2); +} +#endif diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile new file mode 100644 index 0000000000..b0c318c439 --- /dev/null +++ b/board/avionic-design/plutux/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# (C) Copyright 2011 +# Avionic Design GmbH <www.avionic-design.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +COBJS += ../common/tamonten.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/avionic-design/plutux/plutux.c b/board/avionic-design/plutux/plutux.c new file mode 100644 index 0000000000..42c80940c1 --- /dev/null +++ b/board/avionic-design/plutux/plutux.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/tegra2.h> +#ifdef CONFIG_TEGRA2_MMC +#include <mmc.h> +#endif + +#ifdef CONFIG_TEGRA2_MMC +/* + * Routine: gpio_config_mmc + * Description: Set GPIOs for SD card + */ +void gpio_config_mmc(void) +{ + /* configure pin as input for card detect */ + gpio_request(GPIO_PH2, "SD4 CD"); + gpio_direction_input(GPIO_PH2); +} +#endif diff --git a/board/cm_t35/Makefile b/board/cm_t35/Makefile index 27693f07ac..894fa097e1 100644 --- a/board/cm_t35/Makefile +++ b/board/cm_t35/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := cm_t35.o leds.o +COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o + +COBJS := cm_t35.o leds.o $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 420cd70dee..0a049944d7 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -1,6 +1,5 @@ /* - * (C) Copyright 2011 - * CompuLab, Ltd. <www.compulab.co.il> + * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il> * * Authors: Mike Rapoport <mike@compulab.co.il> * Igor Grinberg <grinberg@compulab.co.il> @@ -34,6 +33,7 @@ #include <net.h> #include <i2c.h> #include <twl4030.h> +#include <linux/compiler.h> #include <asm/io.h> #include <asm/arch/mem.h> @@ -42,6 +42,8 @@ #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> +#include "eeprom.h" + DECLARE_GLOBAL_DATA_PTR; const omap3_sysinfo sysinfo = { @@ -316,8 +318,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); - return 0; + return omap_mmc_init(0); } #endif @@ -370,6 +371,7 @@ static void reset_net_chip(void) static inline void reset_net_chip(void) {} #endif +#ifdef CONFIG_SMC911X /* * Routine: handle_mac_address * Description: prepare MAC address for on-board Ethernet. @@ -383,11 +385,9 @@ static int handle_mac_address(void) if (rc) return 0; -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - rc = i2c_read(0x50, 0, 1, enetaddr, 6); + rc = cm_t3x_eeprom_read_mac_addr(enetaddr); if (rc) return rc; -#endif if (!is_valid_ether_addr(enetaddr)) return -1; @@ -404,7 +404,6 @@ int board_eth_init(bd_t *bis) { int rc = 0, rc1 = 0; -#ifdef CONFIG_SMC911X setup_net_chip_gmpc(); reset_net_chip(); @@ -419,7 +418,17 @@ int board_eth_init(bd_t *bis) rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); if (rc1 > 0) rc++; -#endif return rc; } +#endif + +void __weak get_board_serial(struct tag_serialnr *serialnr) +{ + /* + * This corresponds to what happens when we can communicate with the + * eeprom but don't get a valid board serial value. + */ + serialnr->low = 0; + serialnr->high = 0; +}; diff --git a/board/cm_t35/eeprom.c b/board/cm_t35/eeprom.c new file mode 100644 index 0000000000..dfa171d233 --- /dev/null +++ b/board/cm_t35/eeprom.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Nikita Kiryanov <nikita@compulab.co.il> + * Igor Grinberg <grinberg@compulab.co.il> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <i2c.h> + +#define EEPROM_LAYOUT_VER_OFFSET 44 +#define BOARD_SERIAL_OFFSET 20 +#define BOARD_SERIAL_OFFSET_LEGACY 8 +#define BOARD_REV_OFFSET 0 +#define BOARD_REV_OFFSET_LEGACY 6 +#define BOARD_REV_SIZE 4 +#define BOARD_REV_SIZE_LEGACY 2 +#define MAC_ADDR_OFFSET 4 +#define MAC_ADDR_OFFSET_LEGACY 0 + +#define LAYOUT_INVALID 0 +#define LAYOUT_LEGACY 0xff + +static int eeprom_layout; /* Implicitly LAYOUT_INVALID */ + +static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len) +{ + return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); +} + +static int eeprom_setup_layout(void) +{ + int res; + + if (eeprom_layout != LAYOUT_INVALID) + return 0; + + res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, + (uchar *)&eeprom_layout, 1); + if (res) { + eeprom_layout = LAYOUT_INVALID; + return res; + } + + if (eeprom_layout == 0 || eeprom_layout >= 0x20) + eeprom_layout = LAYOUT_LEGACY; + + return 0; +} + +void get_board_serial(struct tag_serialnr *serialnr) +{ + u32 serial[2]; + uint offset; + + memset(serialnr, 0, sizeof(*serialnr)); + if (eeprom_setup_layout()) + return; + + offset = (eeprom_layout != LAYOUT_LEGACY) ? + BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; + if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8)) + return; + + if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) { + serialnr->low = serial[0]; + serialnr->high = serial[1]; + } +} + +/* + * Routine: cm_t3x_eeprom_read_mac_addr + * Description: read mac address and store it in buf. + */ +int cm_t3x_eeprom_read_mac_addr(uchar *buf) +{ + uint offset; + + if (eeprom_setup_layout()) + return 0; + + offset = (eeprom_layout != LAYOUT_LEGACY) ? + MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY; + return cm_t3x_eeprom_read(offset, buf, 6); +} + +/* + * Routine: get_board_rev + * Description: read system revision + */ +u32 get_board_rev(void) +{ + u32 rev = 0; + uint offset = BOARD_REV_OFFSET_LEGACY; + int len = BOARD_REV_SIZE_LEGACY; + + if (eeprom_setup_layout()) + return 0; + + if (eeprom_layout != LAYOUT_LEGACY) { + offset = BOARD_REV_OFFSET; + len = BOARD_REV_SIZE; + } + + if (cm_t3x_eeprom_read(offset, (uchar *)&rev, len)) + return 0; + + return rev; +}; diff --git a/board/cm_t35/eeprom.h b/board/cm_t35/eeprom.h new file mode 100644 index 0000000000..ec772c6710 --- /dev/null +++ b/board/cm_t35/eeprom.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2011 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Nikita Kiryanov <nikita@compulab.co.il> + * Igor Grinberg <grinberg@compulab.co.il> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#ifndef _EEPROM_ +#define _EEPROM_ + +#ifdef CONFIG_DRIVER_OMAP34XX_I2C +int cm_t3x_eeprom_read_mac_addr(uchar *buf); +#else +static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) +{ + return 1; +} +#endif + +#endif diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 9c0eadea90..9bd3e7146c 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -108,7 +108,7 @@ static const struct pinmux_config gpio_pins[] = { #endif }; -static const struct pinmux_resource pinmuxes[] = { +const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_DRIVER_TI_EMAC PINMUX_ITEM(emac_pins_mdio), #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII @@ -135,6 +135,8 @@ static const struct pinmux_resource pinmuxes[] = { PINMUX_ITEM(gpio_pins), }; +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + static const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ diff --git a/board/davinci/da8xxevm/u-boot-spl.lds b/board/davinci/da8xxevm/u-boot-spl.lds new file mode 100644 index 0000000000..6f6e065a9f --- /dev/null +++ b/board/davinci/da8xxevm/u-boot-spl.lds @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __start = .; + arch/arm/cpu/arm926ejs/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } >.sram + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sram + + __image_copy_end = .; + _end = .; +} diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile index aa16c7d156..1fb56d8b8d 100644 --- a/board/denx/m28evk/Makefile +++ b/board/denx/m28evk/Makefile @@ -37,8 +37,6 @@ OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) -all: $(ALL) - ######################################################################### # defines $(obj).depend target diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index fcee046e1d..53df4761f6 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -70,25 +70,9 @@ int board_init(void) return 0; } -#define HW_DIGCTRL_SCRATCH0 0x8001c280 -#define HW_DIGCTRL_SCRATCH1 0x8001c290 int dram_init(void) { - uint32_t sz[2]; - - sz[0] = readl(HW_DIGCTRL_SCRATCH0); - sz[1] = readl(HW_DIGCTRL_SCRATCH1); - - if (sz[0] != sz[1]) { - printf("MX28:\n" - "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" - "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" - "verify these two registers contain valid RAM size!\n"); - hang(); - } - - gd->ram_size = sz[0]; - return 0; + return mx28_dram_init(); } #ifdef CONFIG_CMD_MMC @@ -178,39 +162,4 @@ int board_eth_init(bd_t *bis) return ret; } -#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP - -#define MXS_OCOTP_MAX_TIMEOUT 1000000 -void imx_get_mac_from_fuse(char *mac) -{ - struct mx28_ocotp_regs *ocotp_regs = - (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; - uint32_t data; - - memset(mac, 0, 6); - - writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); - - if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, - MXS_OCOTP_MAX_TIMEOUT)) { - printf("MXS FEC: Can't get MAC from OCOTP\n"); - return; - } - - data = readl(&ocotp_regs->hw_ocotp_cust0); - - mac[0] = 0x00; - mac[1] = 0x04; - mac[2] = (data >> 24) & 0xff; - mac[3] = (data >> 16) & 0xff; - mac[4] = (data >> 8) & 0xff; - mac[5] = data & 0xff; -} -#else -void imx_get_mac_from_fuse(char *mac) -{ - memset(mac, 0, 6); -} -#endif - #endif diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index 1f6c457e99..e88b2edfa1 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -314,17 +314,18 @@ static inline uint32_t efika_mmc_cd(void) return MX51_PIN_EIM_CS2; } -int board_mmc_getcd(u8 *absent, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; uint32_t cd = efika_mmc_cd(); + int ret; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *absent = gpio_get_value(IOMUX_TO_GPIO(cd)); + ret = !gpio_get_value(IOMUX_TO_GPIO(cd)); else - *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - return 0; + return ret; } int board_mmc_init(bd_t *bis) diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c index 6f5662a96d..e0b4cf2c33 100644 --- a/board/emk/top9000/top9000.c +++ b/board/emk/top9000/top9000.c @@ -108,17 +108,9 @@ int board_mmc_init(bd_t *bd) } /* this is a weak define that we are overriding */ -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { - /* - * the only currently existing use of this function - * (fsl_esdhc.c) suggests this function must return - * *cs = TRUE if a card is NOT detected -> in most - * cases the value of the pin when the detect switch - * closes to GND - */ - *cd = at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; - return 0; + return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); } #endif diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index 5cd5357bcd..98dda1eada 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -526,8 +526,8 @@ void bootcount_store(ulong a) * for RTC Scratch registers. Cratch0 and 1 are * used for bootcount values. */ - out_be32(®->kick0r, RTC_KICK0R_WE); - out_be32(®->kick1r, RTC_KICK1R_WE); + writel(RTC_KICK0R_WE, ®->kick0r); + writel(RTC_KICK1R_WE, ®->kick1r); out_be32(®->scratch0, a); out_be32(®->scratch1, BOOTCOUNT_MAGIC); } diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index 08f873d7e4..730ec4e734 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -31,6 +31,9 @@ #include <vsc7385.h> #include <ns16550.h> #include <nand.h> +#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL) +#include <asm/gpio.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +45,18 @@ int board_early_init_f(void) if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) gd->flags |= GD_FLG_SILENT; #endif +#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL) + mpc83xx_gpio_init_f(); +#endif + + return 0; +} + +int board_early_init_r(void) +{ +#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL) + mpc83xx_gpio_init_r(); +#endif return 0; } diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index d127137ddb..532d32ac7c 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -275,7 +275,7 @@ local_bus_init(void) lbc->lcrr &= (~0x80000000); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 48ede9840f..3361614de5 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -273,7 +273,7 @@ local_bus_init(void) lbc->lcrr &= (~0x80000000); /* DLL Enabled */ } else { - lbc->lcrr &= (~0x8000000); /* DLL Enabled */ + lbc->lcrr &= (~0x80000000); /* DLL Enabled */ udelay(200); /* diff --git a/board/freescale/mx28evk/Makefile b/board/freescale/mx28evk/Makefile new file mode 100644 index 0000000000..02ce1082b3 --- /dev/null +++ b/board/freescale/mx28evk/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifndef CONFIG_SPL_BUILD +COBJS := mx28evk.o +else +COBJS := iomux.o +endif + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c new file mode 100644 index 0000000000..904e3f38b7 --- /dev/null +++ b/board/freescale/mx28evk/iomux.c @@ -0,0 +1,138 @@ +/* + * Freescale MX28EVK IOMUX setup + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + /* write protect */ + MX28_PAD_SSP1_SCK__GPIO_2_12, + /* MMC0 slot power enable */ + MX28_PAD_PWM3__GPIO_3_28 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* FEC0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + /* FEC0 Enable */ + MX28_PAD_SSP1_DATA3__GPIO_2_15 | + (MXS_PAD_12MA | MXS_PAD_3V3), + /* FEC0 Reset */ + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* FEC1 */ + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, +}; + +void board_init_ll(void) +{ + mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c new file mode 100644 index 0000000000..0d04d447ad --- /dev/null +++ b/board/freescale/mx28evk/mx28evk.c @@ -0,0 +1,169 @@ +/* + * Freescale MX28EVK board + * + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * Based on m28evk.c: + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + + return 0; +} + +int dram_init(void) +{ + return mx28_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_MMC +static int mx28evk_mmc_wp(int id) +{ + if (id != 0) { + printf("MXS MMC: Invalid card selected (card id = %d)\n", id); + return 1; + } + + return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12); +} + +int board_mmc_init(bd_t *bis) +{ + /* Configure WP as input */ + gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12); + + /* Configure MMC0 Power Enable */ + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); + + return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp); +} +#endif + +#ifdef CONFIG_CMD_NET + +#define MII_OPMODE_STRAP_OVERRIDE 0x16 +#define MII_PHY_CTRL1 0x1e +#define MII_PHY_CTRL2 0x1f + +int fecmxc_mii_postcall(int phy) +{ + miiphy_write("FEC1", phy, MII_BMCR, 0x9000); + miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); + if (phy == 3) + miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + + /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, + &clkctrl_regs->hw_clkctrl_enet); + + /* Power-on FECs */ + gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); + + /* Reset FEC PHYs */ + gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); + udelay(200); + gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + puts("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); + if (ret) { + puts("FEC MXS: Unable to init FEC1\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC0"); + if (!dev) { + puts("FEC MXS: Unable to get FEC0 device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + puts("FEC MXS: Unable to register FEC0 mii postcall\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC1"); + if (!dev) { + puts("FEC MXS: Unable to get FEC1 device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + puts("FEC MXS: Unable to register FEC1 mii postcall\n"); + return ret; + } + + return ret; +} + +#endif diff --git a/board/freescale/mx28evk/u-boot.bd b/board/freescale/mx28evk/u-boot.bd new file mode 100644 index 0000000000..c60615a456 --- /dev/null +++ b/board/freescale/mx28evk/u-boot.bd @@ -0,0 +1,14 @@ +sources { + u_boot_spl="spl/u-boot-spl.bin"; + u_boot="u-boot.bin"; +} + +section (0) { + load u_boot_spl > 0x0000; + load ivt (entry = 0x0014) > 0x8000; + hab call 0x8000; + + load u_boot > 0x40000100; + load ivt (entry = 0x40000100) > 0x8000; + hab call 0x8000; +} diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index e43aaf726e..8d1f6a33ce 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -321,19 +321,20 @@ static void power_init(void) } #ifdef CONFIG_FSL_ESDHC -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = gpio_get_value(0); + ret = !gpio_get_value(0); else - *cd = gpio_get_value(6); + ret = !gpio_get_value(6); - return 0; + return ret; } int board_mmc_init(bd_t *bis) diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index e5a11429f2..40b5c1967f 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -83,19 +83,20 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC2_BASE_ADDR, 1 }, }; -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = gpio_get_value(1); /*GPIO1_1*/ + ret = !gpio_get_value(1); /* GPIO1_1 */ else - *cd = gpio_get_value(4); /*GPIO1_4*/ + ret = !gpio_get_value(4); /* GPIO1_4 */ - return 0; + return ret; } int board_mmc_init(bd_t *bis) diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index aa4a2c93dd..e976ae1c08 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -208,19 +208,20 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC3_BASE_ADDR, 1}, }; -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = gpio_get_value(77); /*GPIO3_13*/ + ret = !gpio_get_value(77); /* GPIO3_13 */ else - *cd = gpio_get_value(75); /*GPIO3_11*/ + ret = !gpio_get_value(75); /* GPIO3_11 */ - return 0; + return ret; } int board_mmc_init(bd_t *bis) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index ea4d354311..e6345e7e5c 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -147,19 +147,20 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC3_BASE_ADDR, 1}, }; -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = gpio_get_value(77); /*GPIO3_13*/ + ret = !gpio_get_value(77); /* GPIO3_13 */ else - *cd = gpio_get_value(75); /*GPIO3_11*/ + ret = !gpio_get_value(75); /* GPIO3_11 */ - return 0; + return ret; } int board_mmc_init(bd_t *bis) diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 55af4e480c..e273192cac 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -132,12 +132,10 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { {MMC_SDHC1_BASE_ADDR, 1}, }; -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); - *cd = gpio_get_value(77); /*GPIO3_13*/ - - return 0; + return !gpio_get_value(77); /* GPIO3_13 */ } int board_mmc_init(bd_t *bis) diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index ffac1b424e..5f0ee0d190 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -164,4 +164,4 @@ DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300 DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FC +DATA 4 0x020c4080 0x000003FF diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 89e0e768e5..98942454a0 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -29,6 +29,8 @@ #include <asm/gpio.h> #include <mmc.h> #include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -40,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -79,11 +85,35 @@ iomux_v3_cfg_t usdhc4_pads[] = { MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +iomux_v3_cfg_t enet_pads[] = { + MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); } +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR, 1}, @@ -132,9 +162,69 @@ int board_mmc_init(bd_t *bis) } #endif +#define MII_MMD_ACCESS_CTRL_REG 0xd +#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe +#define MII_DBG_PORT_REG 0x1d +#define MII_DBG_PORT2_REG 0x1e + +int fecmxc_mii_postcall(int phy) +{ + unsigned short val; + + /* + * Due to the i.MX6Q Armadillo2 board HW design,there is + * no 125Mhz clock input from SOC. In order to use RGMII, + * We need enable AR8031 ouput a 125MHz clk from CLK_25M + */ + miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); + miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); + miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); + miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); + val &= 0xffe3; + val |= 0x18; + miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); + + /* For the RGMII phy, we need enable tx clock delay */ + miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); + miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); + val |= 0x0100; + miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); + + miiphy_write("FEC", phy, MII_BMCR, 0xa100); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + return ret; + } + + dev = eth_get_dev_by_name("FEC"); + if (!dev) { + printf("FEC MXC: Unable to get FEC device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXC: Unable to register FEC mii postcall\n"); + return ret; + } + + return 0; +} + int board_early_init_f(void) { setup_iomux_uart(); + setup_iomux_enet(); return 0; } diff --git a/board/freescale/mx6qsabrelite/Makefile b/board/freescale/mx6qsabrelite/Makefile new file mode 100644 index 0000000000..53c26e7ba6 --- /dev/null +++ b/board/freescale/mx6qsabrelite/Makefile @@ -0,0 +1,42 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := mx6qsabrelite.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg new file mode 100644 index 0000000000..83dee6f3b4 --- /dev/null +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -0,0 +1,170 @@ +# Copyright (C) 2011 Freescale Semiconductor, Inc. +# Jason Liu <r64343@freescale.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 + +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 + +DATA 4 0x020e05ac 0x00020030 +DATA 4 0x020e05b4 0x00020030 +DATA 4 0x020e0528 0x00020030 +DATA 4 0x020e0520 0x00020030 + +DATA 4 0x020e0514 0x00020030 +DATA 4 0x020e0510 0x00020030 +DATA 4 0x020e05bc 0x00020030 +DATA 4 0x020e05c4 0x00020030 + +DATA 4 0x020e056c 0x00020030 +DATA 4 0x020e0578 0x00020030 +DATA 4 0x020e0588 0x00020030 +DATA 4 0x020e0594 0x00020030 + +DATA 4 0x020e057c 0x00020030 +DATA 4 0x020e0590 0x00003000 +DATA 4 0x020e0598 0x00003000 +DATA 4 0x020e058c 0x00000000 + +DATA 4 0x020e059c 0x00003030 +DATA 4 0x020e05a0 0x00003030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 + +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 + +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0750 0x00020000 + +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0798 0x000C0000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b0018 0x00081740 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b000c 0x555A7975 +DATA 4 0x021b0010 0xFF538E64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b002c 0x000026D2 + +DATA 4 0x021b0030 0x005B0E21 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 + +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x0408803A +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x0000803B +DATA 4 0x021b001c 0x00428031 +DATA 4 0x021b001c 0x00428039 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x09408038 + +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b001c 0x04008048 +DATA 4 0x021b0800 0xA1380003 +DATA 4 0x021b4800 0xA1380003 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b4818 0x00022227 + +DATA 4 0x021b083c 0x434B0350 +DATA 4 0x021b0840 0x034C0359 +DATA 4 0x021b483c 0x434B0350 +DATA 4 0x021b4840 0x03650348 +DATA 4 0x021b0848 0x4436383B +DATA 4 0x021b4848 0x39393341 +DATA 4 0x021b0850 0x35373933 +DATA 4 0x021b4850 0x48254A36 + +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F + +DATA 4 0x021b480c 0x00440044 +DATA 4 0x021b4810 0x00440044 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b0404 0x00011006 + +# set the default clock gate to save power +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +# enable AXI cache for VDOA/VPU/IPU +DATA 4 0x020e0010 0xF00000FF +# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c new file mode 100644 index 0000000000..4028789f4e --- /dev/null +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx6x_pins.h> +#include <asm/arch/iomux-v3.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <mmc.h> +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +iomux_v3_cfg_t uart2_pads[] = { + MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t usdhc3_pads[] = { + MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t usdhc4_pads[] = { + MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC3_BASE_ADDR, 1}, + {USDHC4_BASE_ADDR, 1}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + if (cfg->esdhc_base == USDHC3_BASE_ADDR) { + gpio_direction_input(192); /*GPIO7_0*/ + ret = !gpio_get_value(192); + } else { + gpio_direction_input(38); /*GPIO2_6*/ + ret = !gpio_get_value(38); + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + switch (index) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index + 1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6Q-Sabre Lite\n"); + + return 0; +} diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index a997571f0b..177141dcc3 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -249,6 +249,7 @@ int last_stage_init(void) char str_serdes[] = "Start SERDES blocks"; char str_channels[] = "Start FPGA channels"; char str_locks[] = "Verify SERDES locks"; + char str_hicb[] = "Verify HICB status"; char str_status[] = "Verify PHY status -"; char slash[] = "\\|/-\\|/-"; @@ -312,6 +313,21 @@ int last_stage_init(void) } blank_string(strlen(str_locks)); + /* verify hicb_status */ + puts(str_hicb); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int; + for (k = 0; k < 32; ++k) { + u16 status = in_le16(ch0_hicb_status_int + 4*k); + if (status) + printf("fpga %d hicb %d: hicb status %04x\n", + fpga, k, status); + /* reset events */ + out_le16(ch0_hicb_status_int + 4*k, status); + } + } + blank_string(strlen(str_hicb)); + /* verify phy status */ puts(str_status); for (k = 0; k < 32; ++k) { diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 8db8a2bb2c..b0aa182a81 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -33,6 +33,18 @@ int board_init(void) return 0; } +/* We know all the init functions have been run now */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_CALXEDA_XGMAC + rc += calxedaxgmac_initialize(0, 0xfff50000); + rc += calxedaxgmac_initialize(1, 0xfff51000); +#endif + return rc; +} + int misc_init_r(void) { ahci_init(0xffe08000); diff --git a/board/logicpd/omap3som/Makefile b/board/logicpd/omap3som/Makefile new file mode 100644 index 0000000000..75e237b062 --- /dev/null +++ b/board/logicpd/omap3som/Makefile @@ -0,0 +1,42 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := omap3logic.o + +COBJS := $(sort $(COBJS-y)) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c new file mode 100644 index 0000000000..4f5fa8d25f --- /dev/null +++ b/board/logicpd/omap3som/omap3logic.c @@ -0,0 +1,247 @@ +/* + * (C) Copyright 2011 + * Logic Product Development <www.logicpd.com> + * + * Author : + * Peter Barada <peter.barada@logicpd.com> + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <netdev.h> +#include <flash.h> +#include <nand.h> +#include <i2c.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-types.h> +#include "omap3logic.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * two dimensional array of strucures containining board name and Linux + * machine IDs; row it selected based on CPU column is slected based + * on hsusb0_data5 pin having a pulldown resistor + */ +static struct board_id { + char *name; + int machine_id; +} boards[2][2] = { + { + { + .name = "OMAP35xx SOM LV", + .machine_id = MACH_TYPE_OMAP3530_LV_SOM, + }, + { + .name = "OMAP35xx Torpedo", + .machine_id = MACH_TYPE_OMAP3_TORPEDO, + }, + }, + { + { + .name = "DM37xx SOM LV", + .machine_id = MACH_TYPE_DM3730_SOM_LV, + }, + { + .name = "DM37xx Torpedo", + .machine_id = MACH_TYPE_DM3730_TORPEDO, + }, + }, +}; + +/* + * BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV + */ +#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */ + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + struct board_id *board; + unsigned int val; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + /* + * To identify between a SOM LV and Torpedo module, + * a pulldown resistor is on hsusb0_data5 for the SOM LV module. + * Drive the pin (and let it soak), then read it back. + * If the pin is still high its a Torpedo. If low its a SOM LV + */ + + /* Mux hsusb0_data5 as a GPIO */ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)); + + if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) { + + /* + * Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV + * will drain the voltage. + */ + gpio_direction_output(BOARD_ID_GPIO, 0); + gpio_set_value(BOARD_ID_GPIO, 1); + + /* Let it soak for a bit */ + sdelay(0x100); + + /* + * Read state of BOARD_ID_GPIO as an input and if its set. + * If so the board is a Torpedo + */ + gpio_direction_input(BOARD_ID_GPIO); + val = gpio_get_value(BOARD_ID_GPIO); + gpio_free(BOARD_ID_GPIO); + + board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val]; + printf("Board: %s\n", board->name); + + /* Set the machine_id passed to Linux */ + gd->bd->bi_arch_number = board->machine_id; + } + + /* restore hsusb0_data5 pin as hsusb0_data5 */ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); + + return 0; +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif + +/* + * Routine: misc_init_r + * Description: display die ID register + */ +int misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + +#ifdef CONFIG_SMC911X +/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ +static const u32 gpmc_lan92xx_config[] = { + NET_LAN92XX_GPMC_CONFIG1, + NET_LAN92XX_GPMC_CONFIG2, + NET_LAN92XX_GPMC_CONFIG3, + NET_LAN92XX_GPMC_CONFIG4, + NET_LAN92XX_GPMC_CONFIG5, + NET_LAN92XX_GPMC_CONFIG6, +}; + +int board_eth_init(bd_t *bis) +{ + enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); + + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +} +#endif + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + /*GPMC*/ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M4)); + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | DIS | M1)); /*GPMC_IO_DIR*/ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); + + /*Expansion card */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); + + /* Serial Console */ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); + + /* I2C */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); + + MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); + + /*Control and debug */ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); +} diff --git a/board/logicpd/omap3som/omap3logic.h b/board/logicpd/omap3som/omap3logic.h new file mode 100644 index 0000000000..94f6b2eaf7 --- /dev/null +++ b/board/logicpd/omap3som/omap3logic.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2011 + * Logic Product Development <www.logicpd.com> + * + * Author: + * Peter Barada <peter.barada@logicpd.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP3LOGIC_H_ +#define _OMAP3LOGIC_H_ + +/* + * OMAP3 GPMC register settings for CS1 LAN922x + */ +#define NET_LAN92XX_GPMC_CONFIG1 0x00001000 +#define NET_LAN92XX_GPMC_CONFIG2 0x00080801 +#define NET_LAN92XX_GPMC_CONFIG3 0x00000000 +#define NET_LAN92XX_GPMC_CONFIG4 0x08010801 +#define NET_LAN92XX_GPMC_CONFIG5 0x00080a0a +#define NET_LAN92XX_GPMC_CONFIG6 0x03000280 + + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "Logic DM37x/OMAP35x reference board", + "NAND", +}; + + +#endif diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index d3300ed681..a61a98cf77 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -53,13 +53,156 @@ extern int mem_test(ulong start, ulong ramsize, int quiet); #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ #define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */ -extern flash_info_t flash_info[]; /* info for FLASH chips */ +#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) +/*----------------------------------------------------------------------- + * On PIP/MIP405 we have 3 (4) possible boot mode + * + * - Boot from Flash (Flash CS = CS0, MPS CS = CS1) + * - Boot from MPS (Flash CS = CS1, MPS CS = CS0) + * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1) + * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0) + * The flash init is the first board specific routine which is called + * after code relocation (running from SDRAM) + * The first thing we do is to map the Flash CS to the Flash area and + * the MPS CS to the MPS area. Since the flash size is unknown at this + * point, we use the max flash size and the lowest flash address as base. + * + * After flash detection we adjust the size of the CS area accordingly. + * update_flash_size() will fix in wrong values in the flash_info structure, + * misc_init_r() will fix the values in the board info structure + */ +int get_boot_mode(void) +{ + unsigned long pbcr; + int res = 0; + pbcr = mfdcr(CPC0_PSR); + if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) + /* boot via MPS or MPS mapping */ + res = BOOT_MPS; + if (pbcr & PSR_ROM_LOC) + /* boot via PCI.. */ + res |= BOOT_PCI; + return res; +} + +/* Map the flash high (in boot area) + This code can only be executed from SDRAM (after relocation). +*/ +void setup_cs_reloc(void) +{ + int mode; + /* + * since we are relocated, we can set-up the CS finaly + * but first of all, switch off PCI mapping (in case it + * was a PCI boot) + */ + out32r(PMM0MA, 0L); + /* get boot mode */ + mode = get_boot_mode(); + /* + * we map the flash high in every case + * first find out to which CS the flash is attached to + */ + if (mode & BOOT_MPS) { + /* map flash high on CS1 and MPS on CS0 */ + mtdcr(EBC0_CFGADDR, PB0AP); + mtdcr(EBC0_CFGDATA, MPS_AP); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, MPS_CR); + /* + * we use the default values (max values) for the flash + * because its real size is not yet known + */ + mtdcr(EBC0_CFGADDR, PB1AP); + mtdcr(EBC0_CFGDATA, FLASH_AP); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, FLASH_CR_B); + } else { + /* map flash high on CS0 and MPS on CS1 */ + mtdcr(EBC0_CFGADDR, PB1AP); + mtdcr(EBC0_CFGDATA, MPS_AP); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, MPS_CR); + /* + * we use the default values (max values) for the flash + * because its real size is not yet known + */ + mtdcr(EBC0_CFGADDR, PB0AP); + mtdcr(EBC0_CFGDATA, FLASH_AP); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, FLASH_CR_B); + } +} +#endif /* #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) */ + +#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE +/* adjust flash start and protection info */ +int update_flash_size(int flash_size) +{ + int i = 0, mode; + flash_info_t *info = &flash_info[0]; + unsigned long flashcr; + unsigned long flash_base = (0 - flash_size) & 0xFFF00000; + + if (flash_size > 128*1024*1024) { + printf("\n ### ERROR, wrong flash size: %X, reset board ###\n", + flash_size); + hang(); + } + + if ((flash_size >> 20) != 0) + i = __ilog2(flash_size >> 20); + + /* set up flash CS according to the size */ + mode = get_boot_mode(); + if (mode & BOOT_MPS) { + /* flash is on CS1 */ + mtdcr(EBC0_CFGADDR, PB1CR); + flashcr = mfdcr(EBC0_CFGDATA); + /* we map the flash high in every case */ + flashcr &= 0x0001FFFF; /* mask out address bits */ + flashcr |= flash_base; /* start addr */ + flashcr |= (i << 17); /* size addr */ + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, flashcr); + } else { + /* flash is on CS0 */ + mtdcr(EBC0_CFGADDR, PB0CR); + flashcr = mfdcr(EBC0_CFGDATA); + /* we map the flash high in every case */ + flashcr &= 0x0001FFFF; /* mask out address bits */ + flashcr |= flash_base; /* start addr */ + flashcr |= (i << 17); /* size addr */ + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, flashcr); + } + + for (i = 0; i < info->sector_count; i++) + /* adjust sector start address */ + info->start[i] = flash_base + + (info->start[i] - CONFIG_SYS_FLASH_BASE); + + /* unprotect all sectors */ + flash_protect(FLAG_PROTECT_CLEAR, + info->start[0], + 0xFFFFFFFF, + info); + flash_protect_default(); + /* protect reset vector too*/ + flash_protect(FLAG_PROTECT_SET, + info->start[info->sector_count-1], + 0xFFFFFFFF, + info); + + return 0; +} +#endif static int mpl_prg(uchar *src, ulong size) { ulong start; - flash_info_t *info; + flash_info_t *info = &flash_info[0]; int i, rc; #if defined(CONFIG_PATI) int start_sect; @@ -69,8 +212,6 @@ mpl_prg(uchar *src, ulong size) ulong *magic = (ulong *)src; #endif - info = &flash_info[0]; - #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) || defined(CONFIG_PATI) if (uimage_to_cpu (magic[0]) != IH_MAGIC) { puts("Bad Magic number\n"); @@ -96,12 +237,18 @@ mpl_prg(uchar *src, ulong size) } #if !defined(CONFIG_PATI) start = 0 - size; - for (i = info->sector_count-1; i > 0; i--) { - info->protect[i] = 0; /* unprotect this sector */ + + /* unprotect sectors used by u-boot */ + flash_protect(FLAG_PROTECT_CLEAR, + start, + 0xFFFFFFFF, + info); + + /* search start sector */ + for (i = info->sector_count-1; i > 0; i--) if (start >= info->start[i]) break; - } - /* set-up flash location */ + /* now erase flash */ printf("Erasing at %lx (sector %d) (start %lx)\n", start,i,info->start[i]); @@ -114,22 +261,24 @@ mpl_prg(uchar *src, ulong size) #else /* #if !defined(CONFIG_PATI */ start = FIRM_START; start_sect = -1; - for (i = 0; i < info->sector_count; i++) { - if (start < info->start[i]) { - start_sect = i - 1; + + /* search start sector */ + for (i = info->sector_count-1; i > 0; i--) + if (start >= info->start[i]) break; - } - } - info->protect[i - 1] = 0; /* unprotect this sector */ - for (; i < info->sector_count; i++) { - if ((start + size) < info->start[i]) + start_sect = i; + + for (i = info->sector_count-1; i > 0; i--) + if ((start + size) >= info->start[i]) break; - info->protect[i] = 0; /* unprotect this sector */ - } - i--; - /* set-up flash location */ + /* unprotect sectors used by u-boot */ + flash_protect(FLAG_PROTECT_CLEAR, + start, + start + size, + info); + /* now erase flash */ printf ("Erasing at %lx to %lx (sector %d to %d) (%lx to %lx)\n", start, start + size, start_sect, i, @@ -143,12 +292,17 @@ mpl_prg(uchar *src, ulong size) #elif defined(CONFIG_VCMA9) start = 0; - for (i = 0; i <info->sector_count; i++) { - info->protect[i] = 0; /* unprotect this sector */ + + /* search end sector */ + for (i = 0; i < info->sector_count; i++) if (size < info->start[i]) break; - } - /* set-up flash location */ + + flash_protect(FLAG_PROTECT_CLEAR, + start, + size, + info); + /* now erase flash */ printf("Erasing at %lx (sector %d) (start %lx)\n", start,0,info->start[0]); diff --git a/board/mpl/common/common_util.h b/board/mpl/common/common_util.h index 29cd14fa6c..a0ea239740 100644 --- a/board/mpl/common/common_util.h +++ b/board/mpl/common/common_util.h @@ -30,11 +30,15 @@ typedef struct { char eth_addr[21]; /* "00:60:C2:0a:00:00" */ } backup_t; +extern flash_info_t flash_info[]; /* info for FLASH chips */ + void get_backup_values(backup_t *buf); #if defined(CONFIG_PIP405) || defined(CONFIG_MIP405) #define BOOT_MPS 0x01 #define BOOT_PCI 0x02 +int get_boot_mode(void); +void setup_cs_reloc(void); #endif void check_env(void); diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c deleted file mode 100644 index d5b63c0196..0000000000 --- a/board/mpl/common/flash.c +++ /dev/null @@ -1,872 +0,0 @@ -/* - * (C) Copyright 2000, 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -/* - * Modified 3/7/2001 - * - adapted for pip405, Denis Peter, MPL AG Switzerland - * TODO: - * clean-up - */ - -#include <common.h> - -#if !defined(CONFIG_PATI) -#include <asm/ppc4xx.h> -#include <asm/processor.h> -#include "common_util.h" -#if defined(CONFIG_MIP405) -#include "../mip405/mip405.h" -#endif -#if defined(CONFIG_PIP405) -#include "../pip405/pip405.h" -#endif -#include <asm/4xx_pci.h> -#else /* defined(CONFIG_PATI) */ -#include <mpc5xx.h> -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); - -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned short - -#define FALSE 0 -#define TRUE 1 - -#if !defined(CONFIG_PATI) - -/*----------------------------------------------------------------------- - * Some CS switching routines: - * - * On PIP/MIP405 we have 3 (4) possible boot mode - * - * - Boot from Flash (Flash CS = CS0, MPS CS = CS1) - * - Boot from MPS (Flash CS = CS1, MPS CS = CS0) - * - Boot from PCI with Flash map (Flash CS = CS0, MPS CS = CS1) - * - Boot from PCI with MPS map (Flash CS = CS1, MPS CS = CS0) - * The flash init is the first board specific routine which is called - * after code relocation (running from SDRAM) - * The first thing we do is to map the Flash CS to the Flash area and - * the MPS CS to the MPS area. Since the flash size is unknown at this - * point, we use the max flash size and the lowest flash address as base. - * - * After flash detection we adjust the size of the CS area accordingly. - * The board_init_r will fill in wrong values in the board init structure, - * but this will be fixed in the misc_init_r routine: - * bd->bi_flashstart=0-flash_info[0].size - * bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN - * bd->bi_flashoffset=0 - * - */ -int get_boot_mode(void) -{ - unsigned long pbcr; - int res = 0; - pbcr = mfdcr (CPC0_PSR); - if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) - /* boot via MPS or MPS mapping */ - res = BOOT_MPS; - if(pbcr & PSR_ROM_LOC) - /* boot via PCI.. */ - res |= BOOT_PCI; - return res; -} - -/* Map the flash high (in boot area) - This code can only be executed from SDRAM (after relocation). -*/ -void setup_cs_reloc(void) -{ - int mode; - /* Since we are relocated, we can set-up the CS finaly - * but first of all, switch off PCI mapping (in case it was a PCI boot) */ - out32r(PMM0MA,0L); - icache_enable (); /* we are relocated */ - /* get boot mode */ - mode=get_boot_mode(); - /* we map the flash high in every case */ - /* first findout on which cs the flash is */ - if(mode & BOOT_MPS) { - /* map flash high on CS1 and MPS on CS0 */ - mtdcr (EBC0_CFGADDR, PB0AP); - mtdcr (EBC0_CFGDATA, MPS_AP); - mtdcr (EBC0_CFGADDR, PB0CR); - mtdcr (EBC0_CFGDATA, MPS_CR); - /* we use the default values (max values) for the flash - * because its real size is not yet known */ - mtdcr (EBC0_CFGADDR, PB1AP); - mtdcr (EBC0_CFGDATA, FLASH_AP); - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, FLASH_CR_B); - } - else { - /* map flash high on CS0 and MPS on CS1 */ - mtdcr (EBC0_CFGADDR, PB1AP); - mtdcr (EBC0_CFGDATA, MPS_AP); - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, MPS_CR); - /* we use the default values (max values) for the flash - * because its real size is not yet known */ - mtdcr (EBC0_CFGADDR, PB0AP); - mtdcr (EBC0_CFGDATA, FLASH_AP); - mtdcr (EBC0_CFGADDR, PB0CR); - mtdcr (EBC0_CFGDATA, FLASH_CR_B); - } -} - -#endif /* #if !defined(CONFIG_PATI) */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - -#if !defined(CONFIG_PATI) - unsigned long flashcr,size_reg; - int mode; - extern char version_string; - char *p = &version_string; - - /* Since we are relocated, we can set-up the CS finally */ - setup_cs_reloc(); - /* get and display boot mode */ - mode=get_boot_mode(); - if(mode & BOOT_PCI) - printf("(PCI Boot %s Map) ",(mode & BOOT_MPS) ? - "MPS" : "Flash"); - else - printf("(%s Boot) ",(mode & BOOT_MPS) ? - "MPS" : "Flash"); -#endif /* #if !defined(CONFIG_PATI) */ - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_MONITOR_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - /* protect the bootloader */ - /* Monitor protection ON by default */ -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif -#if !defined(CONFIG_PATI) - /* protect reset vector */ - flash_info[0].protect[flash_info[0].sector_count-1] = 1; - flash_info[0].size = size_b0; - /* set up flash cs according to the size */ - size_reg=(flash_info[0].size >>20); - switch (size_reg) { - case 0: - case 1: i=0; break; /* <= 1MB */ - case 2: i=1; break; /* = 2MB */ - case 4: i=2; break; /* = 4MB */ - case 8: i=3; break; /* = 8MB */ - case 16: i=4; break; /* = 16MB */ - case 32: i=5; break; /* = 32MB */ - case 64: i=6; break; /* = 64MB */ - case 128: i=7; break; /*= 128MB */ - default: - printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg); - while(1); - } - if(mode & BOOT_MPS) { - /* flash is on CS1 */ - mtdcr(EBC0_CFGADDR, PB1CR); - flashcr = mfdcr (EBC0_CFGDATA); - /* we map the flash high in every case */ - flashcr&=0x0001FFFF; /* mask out address bits */ - flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ - flashcr|= (i << 17); /* size addr */ - mtdcr(EBC0_CFGADDR, PB1CR); - mtdcr(EBC0_CFGDATA, flashcr); - } - else { - /* flash is on CS0 */ - mtdcr(EBC0_CFGADDR, PB0CR); - flashcr = mfdcr (EBC0_CFGDATA); - /* we map the flash high in every case */ - flashcr&=0x0001FFFF; /* mask out address bits */ - flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ - flashcr|= (i << 17); /* size addr */ - mtdcr(EBC0_CFGADDR, PB0CR); - mtdcr(EBC0_CFGDATA, flashcr); - } -#if 0 - /* enable this (PIP405/MIP405 only) if you want to test if - the relocation has be done ok. - This will disable both Chipselects */ - mtdcr (EBC0_CFGADDR, PB0CR); - mtdcr (EBC0_CFGDATA, 0L); - mtdcr (EBC0_CFGADDR, PB1CR); - mtdcr (EBC0_CFGDATA, 0L); - printf("CS0 & CS1 switched off for test\n"); -#endif - /* patch version_string */ - for(i=0;i<0x100;i++) { - if(*p=='\n') { - *p=0; - break; - } - p++; - } -#else /* #if !defined(CONFIG_PATI) */ -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif /* #if !defined(CONFIG_PATI) */ - return (size_b0); -} - - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_INTEL: printf ("Intel "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - case FLASH_INTEL320T: printf ("TE28F320C3 (32 Mbit, top sector size)\n"); - break; - case FLASH_AM640U: printf ("AM29LV640U (64 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - -*/ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - - value = addr2[0]; - /* printf("flash_get_size value: %x\n",value); */ - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - value = addr2[1]; /* device ID */ - /* printf("Device value %x\n",value); */ - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - case (FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - case (FLASH_WORD_SIZE)AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000; - break; /* => 8 MB */ -#if 0 /* enable when device IDs are available */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - case (FLASH_WORD_SIZE)INTEL_ID_28F320C3T: - info->flash_id += FLASH_INTEL320T; - info->sector_count = 71; - info->size = 0x00400000; - break; /* => 4 MB */ - - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /* base address calculation */ - base=0-info->size; - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040) || - (info->flash_id == FLASH_AM640U)){ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } - else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - if(info->sector_count==71) { - - info->start[i--] = base + info->size - 0x00002000; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000A000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x0000E000; - for (; i >= 0; i--) - info->start[i] = base + i * 0x000010000; - } - else { - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - } - return (info->size); -} - - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return ERR_OK; -} - -int intel_wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last, status; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return ERR_TIMOUT; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - status = addr[0] & (FLASH_WORD_SIZE)0x00280028; - /* clear status register */ - addr[0] = (FLASH_WORD_SIZE)0x00500050; - /* check status for block erase fail and VPP low */ - return (status == 0 ? ERR_OK : ERR_NOT_ERASED); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect; - int i, rcode = 0; - - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - /* printf("Erasing sector %p\n", addr2); */ /* CLH */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - rcode |= wait_for_DQ7(info, sect); - } - else { - if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector */ - addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ - intel_wait_for_DQ7(info, sect); - addr2[0] = (FLASH_WORD_SIZE)0x00200020; /* sector erase */ - addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* sector erase */ - rcode |= intel_wait_for_DQ7(info, sect); - } - else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - rcode |= wait_for_DQ7(info, sect); - } - } - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - /* wait_for_DQ7(info, sect); */ - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - if (!rcode) - printf (" done\n"); - - return rcode; -} - - -void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt) -{ - int i; - volatile FLASH_WORD_SIZE *addr2; - long c; - c= (long)cnt; - for(i=info->sector_count-1;i>0;i--) - { - if(addr>=info->start[i]) - break; - } - do { - addr2 = (FLASH_WORD_SIZE *)(info->start[i]); - addr2[0] = (FLASH_WORD_SIZE)0x00600060; /* unlock sector setup */ - addr2[0] = (FLASH_WORD_SIZE)0x00D000D0; /* unlock sector */ - intel_wait_for_DQ7(info, i); - i++; - c-=(info->start[i]-info->start[i-1]); - }while(c>0); -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - unlock_intel_sectors(info,addr,cnt); - } - wp = (addr & ~3); /* get lower word aligned address */ - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - if((wp % 0x10000)==0) - printf("."); /* show Progress */ - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - rc=write_word(info, wp, data); - return rc; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static FLASH_WORD_SIZE *read_val = (FLASH_WORD_SIZE *)0x200000; - -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (volatile FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (volatile FLASH_WORD_SIZE *)dest; - volatile FLASH_WORD_SIZE *data2; - ulong start; - ulong *data_p; - int flag; - int i; - - data_p = &data; - data2 = (volatile FLASH_WORD_SIZE *)data_p; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *)dest) & - (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) - { - if((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - /* intel style writting */ - dest2[i] = (FLASH_WORD_SIZE)0x00500050; - dest2[i] = (FLASH_WORD_SIZE)0x00400040; - *read_val++ = data2[i]; - dest2[i] = data2[i]; - if (flag) - enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - udelay(10); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) - { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) - return (1); - } - dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ - udelay(10); - dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ - if(dest2[i]!=data2[i]) - printf("Error at %p 0x%04X != 0x%04X\n",&dest2[i],dest2[i],data2[i]); - } - else { - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; - dest2[i] = data2[i]; - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 5dd0b2f8e5..9921545bfa 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -28,8 +28,10 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o ../common/flash.o cmd_mip405.o ../common/pci.o \ - ../common/usb_uhci.o ../common/common_util.o +COBJS = $(BOARD).o cmd_mip405.o \ + ../common/pci.o \ + ../common/usb_uhci.o \ + ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 9d0db64462..56a84e9afa 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -498,6 +498,27 @@ int board_early_init_f (void) return 0; } +int board_early_init_r(void) +{ + int mode; + + /* + * since we are relocated, we can finally enable i-cache + * and set up the flash CS correctly + */ + icache_enable(); + setup_cs_reloc(); + /* get and display boot mode */ + mode = get_boot_mode(); + if (mode & BOOT_PCI) + printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? + "MPS" : "Flash"); + else + printf("%s Boot\n", (mode & BOOT_MPS) ? + "MPS" : "Flash"); + + return 0; +} /* * Get some PLD Registers @@ -671,7 +692,6 @@ static int test_dram (unsigned long ramsize) /* used to check if the time in RTC is valid */ static unsigned long start; static struct rtc_time tm; -extern flash_info_t flash_info[]; /* info for FLASH chips */ int misc_init_r (void) { diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index dae381d32f..0fe508c1b9 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -28,8 +28,8 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS := pati.o ../common/flash.o cmd_pati.o ../common/common_util.o -#### cmd_pati.o +COBJS := $(BOARD).o cmd_pati.o \ + ../common/common_util.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 9aebb9a717..48fe7501e0 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -28,11 +28,12 @@ endif LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o \ - ../common/flash.o cmd_pip405.o ../common/pci.o \ - ../common/isa.o ../common/kbd.o \ - ../common/usb_uhci.o \ - ../common/common_util.o +COBJS = $(BOARD).o cmd_pip405.o \ + ../common/pci.o \ + ../common/isa.o \ + ../common/kbd.o \ + ../common/usb_uhci.o \ + ../common/common_util.o SOBJS = init.o diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index a1f0b656d4..75f57ad8ee 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -566,7 +566,27 @@ int board_early_init_f (void) return 0; } +int board_early_init_r(void) +{ + int mode; + + /* + * since we are relocated, we can finally enable i-cache + * and set up the flash CS correctly + */ + icache_enable(); + setup_cs_reloc(); + /* get and display boot mode */ + mode = get_boot_mode(); + if (mode & BOOT_PCI) + printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ? + "MPS" : "Flash"); + else + printf("%s Boot\n", (mode & BOOT_MPS) ? + "MPS" : "Flash"); + return 0; +} /* ------------------------------------------------------------------------- */ /* @@ -660,9 +680,6 @@ static int test_dram (unsigned long ramsize) return (1); } - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - int misc_init_r (void) { /* adjust flash start and size as well as the offset */ diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile new file mode 100644 index 0000000000..3e748fdd20 --- /dev/null +++ b/board/nvidia/common/Makefile @@ -0,0 +1,47 @@ +# Copyright (c) 2011 The Chromium OS Authors. +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).o + +COBJS-y += board.o +COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index c806a6b3cb..e8253a083d 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -27,10 +27,12 @@ #include <asm/arch/tegra2.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/board.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart.h> +#include <spi.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -48,63 +50,22 @@ int timer_init(void) return 0; } -static void enable_uart(enum periph_id pid) -{ - /* Assert UART reset and enable clock */ - reset_set_enable(pid, 1); - clock_enable(pid); - clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */ - - /* wait for 2us */ - udelay(2); - - /* De-assert reset to UART */ - reset_set_enable(pid, 0); -} - -/* - * Routine: clock_init_uart - * Description: init the PLL and clock for the UART(s) - */ -static void clock_init_uart(void) -{ -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) - enable_uart(PERIPH_ID_UART1); -#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ -#if defined(CONFIG_TEGRA2_ENABLE_UARTD) - enable_uart(PERIPH_ID_UART4); -#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ -} - -/* - * Routine: pin_mux_uart - * Description: setup the pin muxes/tristate values for the UART(s) - */ -static void pin_mux_uart(void) -{ -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) - pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA); - - pinmux_tristate_disable(PINGRP_IRRX); - pinmux_tristate_disable(PINGRP_IRTX); -#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ -#if defined(CONFIG_TEGRA2_ENABLE_UARTD) - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD); - - pinmux_tristate_disable(PINGRP_GMC); -#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ -} - /* * Routine: board_init * Description: Early hardware init. */ int board_init(void) { + /* Do clocks and UART first so that printf() works */ clock_init(); clock_verify(); +#ifdef CONFIG_SPI_UART_SWITCH + gpio_config_uart(); +#endif +#ifdef CONFIG_TEGRA2_SPI + spi_init(); +#endif /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); @@ -114,20 +75,14 @@ int board_init(void) #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { - /* We didn't do this init in start.S, so do it now */ - cpu_init_cp15(); - - /* Initialize essential common plls */ - clock_early_init(); - - /* Initialize UART clocks */ - clock_init_uart(); - - /* Initialize periph pinmuxes */ - pin_mux_uart(); + board_init_uart_f(); /* Initialize periph GPIOs */ +#ifdef CONFIG_SPI_UART_SWITCH + gpio_early_init_uart(); +#else gpio_config_uart(); +#endif return 0; } #endif /* EARLY_INIT */ diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index 1f57086602..a638af2041 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -25,6 +25,6 @@ #define _BOARD_H_ void gpio_config_uart(void); -int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); +void gpio_early_init_uart(void); #endif /* BOARD_H */ diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c new file mode 100644 index 0000000000..23aa0b9d19 --- /dev/null +++ b/board/nvidia/common/uart-spi-switch.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/uart-spi-switch.h> +#include <asm/arch/tegra2.h> +#include <asm/arch/tegra2_spi.h> + + +/* position of the UART/SPI select switch */ +enum spi_uart_switch { + SWITCH_UNKNOWN, + SWITCH_SPI, + SWITCH_UART, + SWITCH_BOTH +}; + +/* Information about the spi/uart switch */ +struct spi_uart { + int gpio; /* GPIO to control switch */ + NS16550_t regs; /* Address of UART affected */ + u32 port; /* Port number of UART affected */ +}; + +static struct spi_uart local; +static enum spi_uart_switch switch_pos; /* Current switch position */ + + +static void get_config(struct spi_uart *config) +{ +#if defined CONFIG_SPI_CORRUPTS_UART + config->gpio = CONFIG_UART_DISABLE_GPIO; + config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART; + config->port = CONFIG_SPI_CORRUPTS_UART_NR; +#else + config->gpio = -1; +#endif +} + +/* + * Init the UART / SPI switch. This can be called before relocation so we must + * not access BSS. + */ +void gpio_early_init_uart(void) +{ + struct spi_uart config; + + get_config(&config); + if (config.gpio != -1) { + /* Cannot provide a label prior to relocation */ + gpio_request(config.gpio, NULL); + gpio_direction_output(config.gpio, 0); + } +} + +/* + * Configure the UART / SPI switch. + */ +void gpio_config_uart(void) +{ + get_config(&local); + if (local.gpio != -1) { + gpio_direction_output(local.gpio, 0); + switch_pos = SWITCH_UART; + } else { + /* + * If we're here we don't have a SPI switch; go ahead and + * enable the SPI now. We didn't in spi_init() so we wouldn't + * kill the UART. + */ + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); + switch_pos = SWITCH_BOTH; + } +} + +static void spi_uart_switch(struct spi_uart *config, + enum spi_uart_switch new_pos) +{ + if (switch_pos == SWITCH_BOTH || new_pos == switch_pos) + return; + + /* if the UART was selected, allow it to drain */ + if (switch_pos == SWITCH_UART) + NS16550_drain(config->regs, config->port); + + /* We need to dynamically change the pinmux, shared w/UART RXD/CTS */ + pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ? + PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD); + + /* + * On Seaboard, MOSI/MISO are shared w/UART. + * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. + * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. + */ + gpio_direction_output(config->gpio, new_pos == SWITCH_SPI); + switch_pos = new_pos; + + /* if the SPI was selected, clear any junk bytes in the UART */ + if (switch_pos == SWITCH_UART) { + /* TODO: What if it is part-way through clocking in junk? */ + udelay(100); + NS16550_clear(config->regs, config->port); + } +} + +void pinmux_select_uart(NS16550_t regs) +{ + /* Also prevents calling spi_uart_switch() before relocation */ + if (regs == local.regs) + spi_uart_switch(&local, SWITCH_UART); +} + +void pinmux_select_spi(void) +{ + spi_uart_switch(&local, SWITCH_SPI); +} diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile index f6599ded80..b6efa1c29a 100644 --- a/board/nvidia/harmony/Makefile +++ b/board/nvidia/harmony/Makefile @@ -31,7 +31,6 @@ endif LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o -COBJS += ../common/board.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c index 3cbe820c95..d5e147d269 100644 --- a/board/nvidia/harmony/harmony.c +++ b/board/nvidia/harmony/harmony.c @@ -25,11 +25,11 @@ #include <asm/io.h> #include <asm/arch/tegra2.h> #include <asm/arch/pinmux.h> +#include <asm/arch/mmc.h> #include <asm/gpio.h> #ifdef CONFIG_TEGRA2_MMC #include <mmc.h> #endif -#include "../common/board.h" /* * Routine: gpio_config_uart diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile index f6599ded80..b6efa1c29a 100644 --- a/board/nvidia/seaboard/Makefile +++ b/board/nvidia/seaboard/Makefile @@ -31,7 +31,6 @@ endif LIB = $(obj)lib$(BOARD).o COBJS := $(BOARD).o -COBJS += ../common/board.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 7f2827b8be..56acd6156f 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -25,12 +25,14 @@ #include <asm/io.h> #include <asm/arch/tegra2.h> #include <asm/arch/pinmux.h> +#include <asm/arch/mmc.h> #include <asm/gpio.h> #ifdef CONFIG_TEGRA2_MMC #include <mmc.h> #endif -#include "../common/board.h" +/* TODO: Remove this code when the SPI switch is working */ +#ifndef CONFIG_SPI_UART_SWITCH /* * Routine: gpio_config_uart_seaboard * Description: Force GPIO_PI3 low on Seaboard so UART4 works. @@ -48,6 +50,7 @@ void gpio_config_uart(void) return; gpio_config_uart_seaboard(); } +#endif #ifdef CONFIG_TEGRA2_MMC /* diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile index d5140c8135..e3b7435530 100644 --- a/board/nvidia/ventana/Makefile +++ b/board/nvidia/ventana/Makefile @@ -25,14 +25,12 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../seaboard) -$(shell mkdir -p $(obj)../common) +$(shell mkdir -p $(obj)../common $(obj)../seaboard) endif LIB = $(obj)lib$(BOARD).o -COBJS += ../seaboard/seaboard.o -COBJS += ../common/board.o +COBJS = ../seaboard/seaboard.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/openrisc/openrisc-generic/Makefile b/board/openrisc/openrisc-generic/Makefile new file mode 100644 index 0000000000..4890aac7dd --- /dev/null +++ b/board/openrisc/openrisc-generic/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/openrisc/openrisc-generic/config.mk b/board/openrisc/openrisc-generic/config.mk new file mode 100644 index 0000000000..c3dc232b5f --- /dev/null +++ b/board/openrisc/openrisc-generic/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2011, Julius Baxter <julius@opencores.org> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_CPPFLAGS += -mhard-mul -mhard-div + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/openrisc/openrisc-generic/openrisc-generic.c b/board/openrisc/openrisc-generic/openrisc-generic.c new file mode 100644 index 0000000000..cdbbfa58e0 --- /dev/null +++ b/board/openrisc/openrisc-generic/openrisc-generic.c @@ -0,0 +1,55 @@ +/* + * Based on nios2-generic.c: + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + printf("BOARD: %s\n", CONFIG_BOARD_NAME); + return 0; +} + +phys_size_t initdram(int board_type) +{ + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; + +#ifdef CONFIG_ETHOC + rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE); +#endif + return rc; +} +#endif diff --git a/board/openrisc/openrisc-generic/or1ksim.cfg b/board/openrisc/openrisc-generic/or1ksim.cfg new file mode 100644 index 0000000000..d44ba43cbf --- /dev/null +++ b/board/openrisc/openrisc-generic/or1ksim.cfg @@ -0,0 +1,882 @@ +/* sim.cfg -- Simulator configuration script file + Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org + +This file is part of OpenRISC 1000 Architectural Simulator. +It contains the default configuration and help about configuring +the simulator. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + + +/* INTRODUCTION + + The ork1sim has various parameters, that are set in configuration files + like this one. The user can switch between configurations at startup by + specifying the required configuration file with the -f <filename.cfg> option. + If no configuration file is specified or1ksim searches for the default + configuration file sim.cfg. First it searches for './sim.cfg'. If this + file is not found, it searches for '~/or1k/sim.cfg'. If this file is + not found too, it reverts to the built-in default configuration. + + NOTE: Users should not rely on the built-in configuration, since the + default configuration may differ between version. + Rather create a configuration file that sets all critical values. + + This file may contain (standard C) comments only - no // support. + + Configure files may be be included, using: + include "file_name_to_include" + + Like normal configuration files, the included file is divided into + sections. Each section is described in detail also. + + Some section have subsections. One example of such a subsection is: + + device <index> + instance specific parameters... + enddevice + + which creates a device instance. +*/ + + +/* MEMORY SECTION + + This section specifies how the memory is generated and the blocks + it consists of. + + type = random/unknown/pattern + Specifies the initial memory values. + 'random' generates random memory using seed 'random_seed'. + 'pattern' fills memory with 'pattern'. + 'unknown' does not specify how memory should be generated, + leaving the memory in a undefined state. This is the fastest + option. + + random_seed = <value> + random seed for randomizer, used if type = 'random'. + + pattern = <value> + pattern to fill memory, used if type = 'pattern'. + + nmemories = <value> + number of memory instances connected + + baseaddr = <hex_value> + memory start address + + size = <hex_value> + memory size + + name = "<string>" + memory block name + + ce = <value> + chip enable index of the memory instance + + mc = <value> + memory controller this memory is connected to + + delayr = <value> + cycles, required for read access, -1 if instance does not support reading + + delayw = <value> + cycles, required for write access, -1 if instance does not support writing + + log = "<filename>" + filename, where to log memory accesses to, no log, if log command is not specified +*/ + + +section memory + pattern = 0x00 + type = unknown /* Fastest */ + + name = "FLASH" + ce = 0 + mc = 0 + baseaddr = 0xf0000000 + size = 0x01000000 + delayr = 1 + delayw = -1 +end + +section memory + pattern = 0x00 + type = unknown /* Fastest */ + + name = "RAM" + ce = 1 + mc = 0 + baseaddr = 0x00000000 + size = 0x02000000 + delayr = 1 + delayw = 1 +end + +section memory + pattern = 0x00 + type = unknown /* Fastest */ + + name = "SRAM" + mc = 0 + ce = 2 + baseaddr = 0xa4000000 + size = 0x00100000 + delayr = 1 + delayw = 2 +end + + +/* IMMU SECTION + + This section configures the Instruction Memory Manangement Unit + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of ITLB sets; must be power of two + + nways = <value> + number of ITLB ways + + pagesize = <value> + instruction page size; must be power of two + + entrysize = <value> + instruction entry size in bytes + + ustates = <value> + number of ITLB usage states (2, 3, 4 etc., max is 4) + + hitdelay = <value> + number of cycles immu hit costs + + missdelay = <value> + number of cycles immu miss costs +*/ + +section immu + enabled = 1 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end + + +/* DMMU SECTION + + This section configures the Data Memory Manangement Unit + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of DTLB sets; must be power of two + + nways = <value> + number of DTLB ways + + pagesize = <value> + data page size; must be power of two + + entrysize = <value> + data entry size in bytes + + ustates = <value> + number of DTLB usage states (2, 3, 4 etc., max is 4) + + hitdelay = <value> + number of cycles dmmu hit costs + + missdelay = <value> + number of cycles dmmu miss costs +*/ + +section dmmu + enabled = 1 + nsets = 64 + nways = 1 + pagesize = 8192 + hitdelay = 0 + missdelay = 0 +end + + +/* IC SECTION + + This section configures the Instruction Cache + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of IC sets; must be power of two + + nways = <value> + number of IC ways + + blocksize = <value> + IC block size in bytes; must be power of two + + ustates = <value> + number of IC usage states (2, 3, 4 etc., max is 4) + + hitdelay = <value> + number of cycles ic hit costs + + missdelay = <value> + number of cycles ic miss costs +*/ + +section ic + enabled = 1 + nsets = 512 + nways = 1 + blocksize = 16 + hitdelay = 1 + missdelay = 1 +end + + +/* DC SECTION + + This section configures the Data Cache + + enabled = 0/1 + '0': disabled + '1': enabled + (NOTE: UPR bit is set) + + nsets = <value> + number of DC sets; must be power of two + + nways = <value> + number of DC ways + + blocksize = <value> + DC block size in bytes; must be power of two + + ustates = <value> + number of DC usage states (2, 3, 4 etc., max is 4) + + load_hitdelay = <value> + number of cycles dc load hit costs + + load_missdelay = <value> + number of cycles dc load miss costs + + store_hitdelay = <value> + number of cycles dc load hit costs + + store_missdelay = <value> + number of cycles dc load miss costs +*/ + +section dc + enabled = 1 + nsets = 512 + nways = 1 + blocksize = 16 + load_hitdelay = 1 + load_missdelay = 1 + store_hitdelay = 1 + store_missdelay = 1 +end + + +/* SIM SECTION + + This section specifies how or1ksim should behave. + + verbose = 0/1 + '0': don't print extra messages + '1': print extra messages + + debug = 0-9 + 0 : no debug messages + 1-9: debug message level. + higher numbers produce more messages + + profile = 0/1 + '0': don't generate profiling file 'sim.profile' + '1': don't generate profiling file 'sim.profile' + + prof_fn = "<filename>" + optional filename for the profiling file. + valid only if 'profile' is set + + mprofile = 0/1 + '0': don't generate memory profiling file 'sim.mprofile' + '1': generate memory profiling file 'sim.mprofile' + + mprof_fn = "<filename>" + optional filename for the memory profiling file. + valid only if 'mprofile' is set + + history = 0/1 + '0': don't track execution flow + '1': track execution flow + Execution flow can be tracked for the simulator's + 'hist' command. Useful for back-trace debugging. + + iprompt = 0/1 + '0': start in <not interactive prompt> (so what do we start in ???) + '1': start in interactive prompt. + + exe_log = 0/1 + '0': don't generate execution log. + '1': generate execution log. + + exe_log = default/hardware/simple/software + type of execution log, default is used when not specified + + exe_log_start = <value> + index of first instruction to start logging, default = 0 + + exe_log_end = <value> + index of last instruction to end logging; not limited, if omitted + + exe_log_marker = <value> + <value> specifies number of instructions before horizontal marker is + printed; if zero, markers are disabled (default) + + exe_log_fn = "<filename>" + filename for the exection log file. + valid only if 'exe_log' is set + + clkcycle = <value>[ps|ns|us|ms] + specifies time measurement for one cycle +*/ + +section sim + verbose = 1 + debug = 0 + profile = 0 + history = 0 + + clkcycle = 10ns +end + + +/* SECTION VAPI + + This section configures the Verification API, used for Advanced + Core Verification. + + enabled = 0/1 + '0': disbable VAPI server + '1': enable/start VAPI server + + server_port = <value> + TCP/IP port to start VAPI server on + + log_enabled = 0/1 + '0': disable VAPI requests logging + '1': enable VAPI requests logging + + hide_device_id = 0/1 + '0': don't log device id (for compatability with old version) + '1': log device id + + + vapi_fn = <filename> + filename for the log file. + valid only if log_enabled is set +*/ + +section VAPI + enabled = 0 + server_port = 9998 + log_enabled = 0 + vapi_log_fn = "vapi.log" +end + + +/* CPU SECTION + + This section specifies various CPU parameters. + + ver = <value> + rev = <value> + specifies version and revision of the CPU used + + upr = <value> + changes the upr register + + sr = <value> + sets the initial Supervision Register value + supervisor mode (SM) and fixed one (FO) set = 0x8001 + exception prefix high (EPH, vectors@0xf0000000) = 0x4000 + together, (SM | FO | EPH) = 0xc001 + superscalar = 0/1 + '0': CPU is scalar + '1': CPU is superscalar + (modify cpu/or32/execute.c to tune superscalar model) + + hazards = 0/1 + '0': don't track data hazards in superscalar CPU + '1': track data hazards in superscalar CPU + If tracked, data hazards can be displayed using the + simulator's 'r' command. + + dependstats = 0/1 + '0': don't calculate inter-instruction dependencies. + '1': calculate inter-instruction dependencies. + If calculated, inter-instruction dependencies can be + displayed using the simulator's 'stat' command. + + sbuf_len = <value> + length of store buffer (<= 256), 0 = disabled +*/ + +section cpu + ver = 0x12 + cfg = 0x00 + rev = 0x01 + sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */ + /* upr = */ + superscalar = 0 + hazards = 0 + dependstats = 0 + sbuf_len = 0 +end + + +/* PM SECTION + + This section specifies Power Management parameters + + enabled = 0/1 + '0': disable power management + '1': enable power management +*/ + +section pm + enabled = 0 +end + + +/* BPB SECTION + + This section specifies how branch prediction should behave. + + enabled = 0/1 + '0': disable branch prediction + '1': enable branch prediction + + btic = 0/1 + '0': disable branch target instruction cache model + '1': enable branch target instruction cache model + + sbp_bf_fwd = 0/1 + Static branch prediction for 'l.bf' + '0': don't use forward prediction + '1': use forward prediction + + sbp_bnf_fwd = 0/1 + Static branch prediction for 'l.bnf' + '0': don't use forward prediction + '1': use forward prediction + + hitdelay = <value> + number of cycles bpb hit costs + + missdelay = <value> + number of cycles bpb miss costs +*/ + +section bpb + enabled = 0 + btic = 0 + sbp_bf_fwd = 0 + sbp_bnf_fwd = 0 + hitdelay = 0 + missdelay = 0 +end + + +/* DEBUG SECTION + + This sections specifies how the debug unit should behave. + + enabled = 0/1 + '0': disable debug unit + '1': enable debug unit + + gdb_enabled = 0/1 + '0': don't start gdb server + '1': start gdb server at port 'server_port' + + server_port = <value> + TCP/IP port to start gdb server on + valid only if gdb_enabled is set + + vapi_id = <hex_value> + Used to create "fake" vapi log file containing the JTAG proxy messages. +*/ +section debug + enabled = 0 +/* gdb_enabled = 0 */ +/* server_port = 9999*/ + rsp_enabled = 1 + rsp_port = 50001 +end + + +/* MC SECTION + + This section configures the memory controller + + enabled = 0/1 + '0': disable memory controller + '1': enable memory controller + + baseaddr = <hex_value> + address of first MC register + + POC = <hex_value> + Power On Configuration register + + index = <value> + Index of this memory controller amongst all the memory controllers +*/ + +section mc + enabled = 0 + baseaddr = 0x93000000 + POC = 0x00000008 /* Power on configuration register */ + index = 0 +end + + +/* UART SECTION + + This section configures the UARTs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first UART register for this device + + + channel = <channeltype>:<args> + + The channel parameter indicates the source of received UART characters + and the sink for transmitted UART characters. + + The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty" + (without quotes). + + A) To send/receive characters from a pair of files, use a file + channel: + + channel=file:<rxfile>,<txfile> + + B) To create an interactive terminal window, use an xterm channel: + + channel=xterm:[<xterm_arg>]* + + C) To create a bidirectional tcp socket which one could, for example, + access via telnet, use a tcp channel: + + channel=tcp:<port number> + + D) To cause the UART to read/write from existing numeric file + descriptors, use an fd channel: + + channel=fd:<rx file descriptor num>,<tx file descriptor num> + + E) To connect the UART to a physical serial port, create a tty + channel: + + channel=tty:device=/dev/ttyS0,baud=9600 + + irq = <value> + irq number for this device + + 16550 = 0/1 + '0': this device is a UART16450 + '1': this device is a UART16550 + + jitter = <value> + in msecs... time to block, -1 to disable it + + vapi_id = <hex_value> + VAPI id of this instance +*/ + +section uart + enabled = 1 + baseaddr = 0x90000000 + irq = 2 + /* channel = "file:uart0.rx,uart0.tx" */ + /* channel = "tcp:10084" */ + channel = "xterm:" + jitter = -1 /* async behaviour */ + 16550 = 1 +end + + +/* DMA SECTION + + This section configures the DMAs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first DMA register for this device + + irq = <value> + irq number for this device + + vapi_id = <hex_value> + VAPI id of this instance +*/ + +section dma + enabled = 1 + baseaddr = 0x9a000000 + irq = 11 +end + + +/* ETHERNET SECTION + + This section configures the ETHERNETs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first ethernet register for this device + + dma = <value> + which controller is this ethernet "connected" to + + irq = <value> + ethernet mac IRQ level + + rtx_type = <value> + use 0 - file interface, 1 - socket interface + + rx_channel = <value> + DMA channel used for RX + + tx_channel = <value> + DMA channel used for TX + + rxfile = "<filename>" + filename, where to read data from + + txfile = "<filename>" + filename, where to write data to + + sockif = "<ifacename>" + interface name of ethernet socket + + vapi_id = <hex_value> + VAPI id of this instance +*/ + +section ethernet + enabled = 1 + baseaddr = 0x92000000 + /* dma = 0 */ + irq = 4 + rtx_type = "tap" + tap_dev = "tap0" + /* tx_channel = 0 */ + /* rx_channel = 1 */ + rxfile = "eth0.rx" + txfile = "eth0.tx" + sockif = "eth0" +end + + +/* GPIO SECTION + + This section configures the GPIOs + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first GPIO register for this device + + irq = <value> + irq number for this device + + base_vapi_id = <hex_value> + first VAPI id of this instance + GPIO uses 8 consecutive VAPI IDs +*/ + +section gpio + enabled = 0 + baseaddr = 0x91000000 + irq = 3 + base_vapi_id = 0x0200 +end + +/* VGA SECTION + + This section configures the VGA/LCD controller + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + address of first VGA register + + irq = <value> + irq number for this device + + refresh_rate = <value> + number of cycles between screen dumps + + filename = "<filename>" + template name for generated names (e.g. "primary" produces "primary0023.bmp") +*/ + +section vga + enabled = 0 + baseaddr = 0x97100000 + irq = 8 + refresh_rate = 100000 + filename = "primary" +end + + +/* TICK TIMER SECTION + + This section configures tick timer + + enabled = 0/1 + whether tick timer is enabled +*/ + +section pic + enabled = 1 + edge_trigger = 1 +end + +/* FB SECTION + + This section configures the frame buffer + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + baseaddr = <hex_value> + base address of frame buffer + + paladdr = <hex_value> + base address of first palette entry + + refresh_rate = <value> + number of cycles between screen dumps + + filename = "<filename>" + template name for generated names (e.g. "primary" produces "primary0023.bmp") +*/ + +section fb + enabled = 0 + baseaddr = 0x97000000 + refresh_rate = 1000000 + filename = "primary" +end + + +/* KBD SECTION + + This section configures the PS/2 compatible keyboard + + baseaddr = <hex_value> + base address of the keyboard device + + rxfile = "<filename>" + filename, where to read data from +*/ + +section kbd + enabled = 0 + irq = 5 + baseaddr = 0x94000000 + rxfile = "kbd.rx" +end + + +/* ATA SECTION + + This section configures the ATA/ATAPI host controller + + baseaddr = <hex_value> + address of first ATA register + + enabled = <0|1> + Enable/disable the peripheral. By default if it is enabled. + + irq = <value> + irq number for this device + + debug = <value> + debug level for ata models. + 0: no debug messages + 1: verbose messages + 3: normal messages (more messages than verbose) + 5: debug messages (normal debug messages) + 7: flow control messages (debug statemachine flows) + 9: low priority message (display everything the code does) + + dev_type0/1 = <value> + ata device 0 type + 0: NO_CONNeCT: none (not connected) + 1: FILE : simulated harddisk + 2: LOCAL : local system harddisk + + dev_file0/1 = "<filename>" + filename for simulated ATA device + valid only if dev_type0 == 1 + + dev_size0/1 = <value> + size of simulated hard-disk (in MBytes) + valid only if dev_type0 == 1 + + dev_packet0/1 = <value> + 0: simulated ATA device does NOT implement PACKET command feature set + 1: simulated ATA device does implement PACKET command feature set + + FIXME: irq number +*/ + +section ata + enabled = 0 + baseaddr = 0x9e000000 + irq = 15 + +end diff --git a/board/openrisc/openrisc-generic/u-boot.lds b/board/openrisc/openrisc-generic/u-boot.lds new file mode 100644 index 0000000000..1aed197bb9 --- /dev/null +++ b/board/openrisc/openrisc-generic/u-boot.lds @@ -0,0 +1,75 @@ +#include <config.h> +OUTPUT_ARCH(or32) +__DYNAMIC = 0; + +MEMORY +{ + vectors : ORIGIN = 0, LENGTH = 0x2000 + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, + LENGTH = CONFIG_SYS_MONITOR_LEN +} + +SECTIONS +{ + .vectors : + { + *(.vectors) + } > vectors + + __start = .; + .text : AT (__start) { + _stext = .; + *(.text) + _etext = .; + *(.lit) + *(.shdata) + _endtext = .; + } > ram + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } > ram + __u_boot_cmd_end = .; + + .rodata : { + *(.rodata); + *(.rodata.*) + } > ram + + .shbss : + { + *(.shbss) + } > ram + + .talias : + { + } > ram + + .data : { + sdata = .; + _sdata = .; + *(.data) + edata = .; + _edata = .; + } > ram + + .bss : + { + _bss_start = .; + *(.bss) + *(COMMON) + _bss_end = .; + } > ram + __end = .; + + /* No stack specification - done manually */ + + .stab 0 (NOLOAD) : + { + [ .stab ] + } + + .stabstr 0 (NOLOAD) : + { + [ .stabstr ] + } +} diff --git a/board/overo/overo.c b/board/overo/overo.c index 3c60b06ae7..7b4064cdb1 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -31,6 +31,7 @@ #include <common.h> #include <netdev.h> #include <twl4030.h> +#include <linux/mtd/nand.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> @@ -100,6 +101,16 @@ int board_init(void) } /* + * Routine: omap_rev_string + * Description: For SPL builds output board rev + */ +#ifdef CONFIG_SPL_BUILD +void omap_rev_string(void) +{ +} +#endif + +/* * Routine: get_board_revision * Description: Returns the board revision */ @@ -107,6 +118,20 @@ int get_board_revision(void) { int revision; +#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + + /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ + /* these boards should return a revision number of 0 */ + /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ + i2c_set_bus_num(TWL4030_I2C_BUS); + data = 0x01; + i2c_write(0x4B, 0x29, 1, &data, 1); + data = 0x0c; + i2c_write(0x4B, 0x2b, 1, &data, 1); + i2c_read(0x4B, 0x2a, 1, &data, 1); +#endif + if (!gpio_request(112, "") && !gpio_request(113, "") && !gpio_request(115, "")) { @@ -119,13 +144,51 @@ int get_board_revision(void) gpio_get_value(113) << 1 | gpio_get_value(112); } else { - printf("Error: unable to acquire board revision GPIOs\n"); + puts("Error: unable to acquire board revision GPIOs\n"); revision = -1; } return revision; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ + *mcfg = MICRON_V_MCFG_165(256 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ + *mcfg = HYNIX_V_MCFG_165(256 << 20); + *ctrla = HYNIX_V_ACTIMA_165; + *ctrlb = HYNIX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + default: + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} +#endif + /* * Routine: get_sdio2_config * Description: Return information about the wifi module connection @@ -151,7 +214,7 @@ int get_sdio2_config(void) gpio_direction_input(130); } else { - printf("Error: unable to acquire sdio2 clk GPIOs\n"); + puts("Error: unable to acquire sdio2 clk GPIOs\n"); sdio_direct = -1; } @@ -200,15 +263,15 @@ int misc_init_r(void) switch (get_sdio2_config()) { case 0: - printf("Tranceiver detected on mmc2\n"); + puts("Tranceiver detected on mmc2\n"); MUX_OVERO_SDIO2_TRANSCEIVER(); break; case 1: - printf("Direct connection on mmc2\n"); + puts("Direct connection on mmc2\n"); MUX_OVERO_SDIO2_DIRECT(); break; default: - printf("Unable to detect mmc2 connection type\n"); + puts("Unable to detect mmc2 connection type\n"); } switch (get_expansion_id()) { @@ -269,10 +332,10 @@ int misc_init_r(void) setenv("defaultdisplay", "dvi"); break; case GUMSTIX_NO_EEPROM: - printf("No EEPROM on expansion board\n"); + puts("No EEPROM on expansion board\n"); break; default: - printf("Unrecognized expansion board\n"); + puts("Unrecognized expansion board\n"); } if (expansion_config.content == 1) @@ -337,7 +400,7 @@ int board_eth_init(bd_t *bis) return rc; } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/overo/overo.h b/board/overo/overo.h index 915f15bf10..b41b628899 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -33,6 +33,11 @@ const omap3_sysinfo sysinfo = { #endif }; +/* overo revisions */ +#define REVISION_0 0x0 +#define REVISION_1 0x1 +#define REVISION_2 0x2 + /* * IEN - Input Enable * IDIS - Input Disable diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 996ffe206d..45ec485c50 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <i2c.h> #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> @@ -54,3 +55,79 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ popts->half_strength_driver_enable = 0; } + +#ifdef CONFIG_SPD_EEPROM +/* + * Workaround for hardware errata. An i2c address conflict + * existed on earlier boards; the workaround moved the DDR + * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and + * if that fails, then fall back to reading at 0x51. + */ +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret; + +#ifdef ALT_SPD_EEPROM_ADDRESS + if (i2c_address == SPD_EEPROM_ADDRESS) { + ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + if (ret == 0) + return; /* Good data at 0x53 */ + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +#endif + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + if (ret) { + printf("DDR: failed to read SPD from addr %u\n", i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +#else +/* + * fixed_sdram init -- doesn't use serial presence detect. + * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. + */ +phys_size_t fixed_sdram(void) +{ + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + out_be32(&ddr->cs0_bnds, 0x0000007f); + out_be32(&ddr->cs1_bnds, 0x008000ff); + out_be32(&ddr->cs2_bnds, 0x00000000); + out_be32(&ddr->cs3_bnds, 0x00000000); + + out_be32(&ddr->cs0_config, 0x80010101); + out_be32(&ddr->cs1_config, 0x80010101); + out_be32(&ddr->cs2_config, 0x00000000); + out_be32(&ddr->cs3_config, 0x00000000); + + out_be32(&ddr->timing_cfg_3, 0x00000000); + out_be32(&ddr->timing_cfg_0, 0x00220802); + out_be32(&ddr->timing_cfg_1, 0x38377322); + out_be32(&ddr->timing_cfg_2, 0x0fa044C7); + + out_be32(&ddr->sdram_cfg, 0x4300C000); + out_be32(&ddr->sdram_cfg_2, 0x24401000); + + out_be32(&ddr->sdram_mode, 0x23C00542); + out_be32(&ddr->sdram_mode_2, 0x00000000); + + out_be32(&ddr->sdram_interval, 0x05080100); + out_be32(&ddr->sdram_md_cntl, 0x00000000); + out_be32(&ddr->sdram_data_init, 0x00000000); + out_be32(&ddr->sdram_clk_cntl, 0x03800000); + asm("sync;isync;msync"); + udelay(500); + + #ifdef CONFIG_DDR_ECC + /* Enable ECC checking */ + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); + #else + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); + #endif + + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; +} +#endif diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index 5fa9db02f5..322af76d65 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -36,22 +36,36 @@ * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe27f_ffff PCI1 IO 8M * 0xe280_0000 0xe2ff_ffff PCIe IO 8M + * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf8b0_0000 0xf80f_ffff EEPROM 1M - * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M * + * If swapped CS0/CS6 via JP12+SW2.8: + * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */ struct law_entry law_table[] = { +#ifdef CONFIG_SYS_ALT_BOOT + SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC), +#else + SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#endif #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif +#ifdef CONFIG_SYS_LBC_SDRAM_BASE /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#else + /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */ + SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 26095a5455..371d07695e 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -76,11 +76,15 @@ local_bus_init(void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint clkdiv; + uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; + + lbc_mhz = sysinfo.freqLocalBus / 1000000; + clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus; + + debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { @@ -91,10 +95,38 @@ local_bus_init(void) out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); } - setbits_be32(&lbc->lcrr, 0x00030000); + /* + * Local Bus Clock > 83.3 MHz. According to timing + * specifications set LCRR[EADC] to 2 delay cycles. + */ + if (lbc_mhz > 83) { + lcrr &= ~LCRR_EADC; + lcrr |= LCRR_EADC_2; + } + + /* + * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 + * disable PLL bypass for Local Bus Clock > 83 MHz. + */ + if (lbc_mhz >= 66) + lcrr &= (~LCRR_DBYP); /* DLL Enabled */ + + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + out_be32(&lbc->lcrr, lcrr); asm("sync;isync;msync"); + /* + * According to MPC8548ERMAD Rev.1.3 read back LCRR + * and terminate with isync + */ + lcrr = in_be32(&lbc->lcrr); + asm ("isync;"); + + /* let DLL stabilize */ + udelay(500); + out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ } @@ -107,13 +139,14 @@ void lbc_sdram_init(void) #if defined(CONFIG_SYS_LBC_SDRAM_SIZE) uint idx; + const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint lsdmr_common; + uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2); puts(" SDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size(size, "\n"); /* * Setup SDRAM Base and Option Registers @@ -131,47 +164,49 @@ void lbc_sdram_init(void) asm("msync"); /* - * MPC8548 uses "new" 15-16 style addressing. - */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; - lsdmr_common |= LSDMR_BSMA1516; - - /* * Issue PRECHARGE ALL command. */ - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(100); /* * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(100); } /* * Issue 8 MODE-set command. */ - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(100); /* - * Issue NORMAL OP command. + * Issue RFEN command. */ - out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); + out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); + *sdram_addr2 = 0xff; + ppcDcbf((unsigned long) sdram_addr2); udelay(200); /* Overkill. Must wait > 200 bus cycles */ #endif /* enable SDRAM init */ @@ -216,50 +251,6 @@ testdram(void) } #endif -#if !defined(CONFIG_SPD_EEPROM) -#define CONFIG_SYS_DDR_CONTROL 0xc300c000 -/************************************************************************* - * fixed_sdram init -- doesn't use serial presence detect. - * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. - ************************************************************************/ -phys_size_t fixed_sdram(void) -{ - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - out_be32(&ddr->cs0_bnds, 0x0000007f); - out_be32(&ddr->cs1_bnds, 0x008000ff); - out_be32(&ddr->cs2_bnds, 0x00000000); - out_be32(&ddr->cs3_bnds, 0x00000000); - out_be32(&ddr->cs0_config, 0x80010101); - out_be32(&ddr->cs1_config, 0x80010101); - out_be32(&ddr->cs2_config, 0x00000000); - out_be32(&ddr->cs3_config, 0x00000000); - out_be32(&ddr->timing_cfg_3, 0x00000000); - out_be32(&ddr->timing_cfg_0, 0x00220802); - out_be32(&ddr->timing_cfg_1, 0x38377322); - out_be32(&ddr->timing_cfg_2, 0x0fa044C7); - out_be32(&ddr->sdram_cfg, 0x4300C000); - out_be32(&ddr->sdram_cfg_2, 0x24401000); - out_be32(&ddr->sdram_mode, 0x23C00542); - out_be32(&ddr->sdram_mode_2, 0x00000000); - out_be32(&ddr->sdram_interval, 0x05080100); - out_be32(&ddr->sdram_md_cntl, 0x00000000); - out_be32(&ddr->sdram_data_init, 0x00000000); - out_be32(&ddr->sdram_clk_cntl, 0x03800000); - asm("sync;isync;msync"); - udelay(500); - - #if defined (CONFIG_DDR_ECC) - /* Enable ECC checking */ - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); - #else - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); - #endif - - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -} -#endif - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif /* CONFIG_PCI1 */ diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index bb4c05210c..af927f165b 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -46,12 +46,14 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 56M 8MB -> 64MB of user flash + * 0xfc000000 56M unused * 0xff800000 8M boot FLASH + * .... or .... + * 0xfc000000 64M user flash + * * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000, - CONFIG_SYS_ALT_FLASH + 0x800000, + SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), @@ -74,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), +#ifdef CONFIG_SYS_LBC_SDRAM_BASE /* * TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half @@ -90,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_64M, 1), +#endif /* * TLB 5: 16M Cacheable, non-guarded @@ -102,9 +106,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_16M, 1), +#ifndef CONFIG_SYS_ALT_BOOT + /* + * TLB 6: 64M Non-cacheable, guarded + * 0xec000000 64M 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), +#else /* * TLB 6: 4M Non-cacheable, guarded - * 0xfb800000 4M 1st 4MB block of 64MB user FLASH + * 0xef800000 4M 1st 1/2 8MB soldered FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -112,12 +125,13 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 7: 4M Non-cacheable, guarded - * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH + * 0xefc00000 4M 2nd half 8MB soldered FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4M, 1), +#endif }; diff --git a/board/technexion/twister/Makefile b/board/technexion/twister/Makefile new file mode 100644 index 0000000000..38b7b14520 --- /dev/null +++ b/board/technexion/twister/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c new file mode 100644 index 0000000000..06fac7b583 --- /dev/null +++ b/board/technexion/twister/twister.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2009 TechNexion Ltd. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <i2c.h> +#include <asm/gpio.h> +#include "twister.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Timing definitions for Ethernet Controller */ +static const u32 gpmc_smc911[] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, +}; + +static const u32 gpmc_XR16L2751[] = { + XR16L2751_GPMC_CONFIG1, + XR16L2751_GPMC_CONFIG2, + XR16L2751_GPMC_CONFIG3, + XR16L2751_GPMC_CONFIG4, + XR16L2751_GPMC_CONFIG5, + XR16L2751_GPMC_CONFIG6, +}; + +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + /* Chip select 1 and 3 are used for XR16L2751 UART controller */ + enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1], + XR16L2751_UART1_BASE, GPMC_SIZE_16M); + + enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3], + XR16L2751_UART2_BASE, GPMC_SIZE_16M); + + gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET"); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1); + + return 0; +} + +int misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_TWISTER(); +} + +int board_eth_init(bd_t *bis) +{ + davinci_emac_initialize(); + + /* init cs for extern lan */ + enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); + if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0) + printf("\nError initializing SMC911x controlleri\n"); + + return 0; +} + +#if defined(CONFIG_OMAP_HSMMC) && \ + !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif diff --git a/board/technexion/twister/twister.h b/board/technexion/twister/twister.h new file mode 100644 index 0000000000..a2051c0044 --- /dev/null +++ b/board/technexion/twister/twister.h @@ -0,0 +1,411 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2010 TechNexion Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _TAM3517_H_ +#define _TAM3517_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "TAM3517 TWISTER Board", + "NAND", +}; + +#define XR16L2751_GPMC_CONFIG1 0x00000000 +#define XR16L2751_GPMC_CONFIG2 0x001e1e01 +#define XR16L2751_GPMC_CONFIG3 0x00080300 +#define XR16L2751_GPMC_CONFIG4 0x1c091c09 +#define XR16L2751_GPMC_CONFIG5 0x04181f1f +#define XR16L2751_GPMC_CONFIG6 0x00000FCF + +#define XR16L2751_UART1_BASE 0x21000000 +#define XR16L2751_UART2_BASE 0x23000000 + + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_TWISTER() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M2)) /*PWM9*/\ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \ + MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + /* CardDetect */\ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT5), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | EN | M4)) /*GPIO_116*/ \ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTD | EN | M4)) \ + \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_152*/\ + MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M4)) /*GPIO_155*/\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) /*GPIO_163*/ \ + MUX_VAL(CP(UART3_RTS_SD), (IEN | PTD | DIS | M4)) /*GPIO_164*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M4)) /*GPIO_176*/\ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M4)) \ + \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ + /* - GPIO30 */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ + /* - VIO_1V8*/\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(JTAG_EMU0), (IDIS | PTD | EN | M4)) /*GPIO_11*/ \ + MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | EN | M4)) /*GPIO_31*/ \ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_stp */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_clk */\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M3)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ + /* hsusb1_dir */\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ + /* hsusb1_nxt */\ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/board/ti/am335x/evm.c b/board/ti/am335x/evm.c index b4eddd8092..6a9f788299 100644 --- a/board/ti/am335x/evm.c +++ b/board/ti/am335x/evm.c @@ -16,7 +16,7 @@ #include <common.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> -#include "common_def.h" +#include <asm/arch/common_def.h> #include <serial.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 8f2740944b..4cb0cdf361 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -14,7 +14,7 @@ */ #include <config.h> -#include "common_def.h" +#include <asm/arch/common_def.h> #include <asm/arch/hardware.h> #include <asm/io.h> @@ -258,6 +258,20 @@ static struct module_pin_mux uart0_pin_mux[] = { {-1}, }; +#ifdef CONFIG_MMC +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ + {-1}, +}; +#endif + /* * Configure the pin mux for the module */ @@ -276,3 +290,10 @@ void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); } + +#ifdef CONFIG_MMC +void enable_mmc0_pin_mux(void) +{ + configure_module_pin_mux(mmc0_pin_mux); +} +#endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cbb5d..5c04b34e1a 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -71,6 +71,7 @@ extern volatile struct ehci_hcor *hcor; #define BBTOYS_WIFI 0x01000B00 #define BBTOYS_VGA 0x02000B00 #define BBTOYS_LCD 0x03000B00 +#define BCT_BRETTL3 0x01000F00 #define BEAGLE_NO_EEPROM 0xffffffff DECLARE_GLOBAL_DATA_PTR; @@ -379,6 +380,9 @@ int misc_init_r(void) case BBTOYS_LCD: printf("Recognized BeagleBoardToys LCD board\n"); break;; + case BCT_BRETTL3: + printf("Recognized bct electronic GmbH brettl3 board\n"); + break; case BEAGLE_NO_EEPROM: printf("No EEPROM on expansion board\n"); setenv("buddy", "none"); diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index b06aab6176..10f189eed4 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -48,6 +48,16 @@ DECLARE_GLOBAL_DATA_PTR; +static u32 gpmc_net_config[GPMC_MAX_REG] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, + 0 +}; + /* * Routine: board_init * Description: Early hardware init. @@ -82,13 +92,8 @@ int misc_init_r(void) #ifdef CONFIG_DRIVER_DM9000 /* Configure GPMC registers for DM9000 */ - writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1); - writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2); - writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[6].config3); - writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[6].config4); - writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[6].config5); - writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[6].config6); - writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7); + enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], + CONFIG_DM9000_BASE, GPMC_SIZE_16M); /* Use OMAP DIE_ID as MAC address */ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index f556d308e3..282de95e95 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -428,9 +428,8 @@ static void setup_gpios(void) gpio_direction_output(4, 1); gpio_direction_output(7, 0); - for (i = 65; i < 71; i++) { + for (i = 65; i < 71; i++) gpio_direction_output(i, 0); - } gpio_direction_output(94, 0); diff --git a/boards.cfg b/boards.cfg index 66c27a4c23..2f90dbf928 100644 --- a/boards.cfg +++ b/boards.cfg @@ -120,7 +120,7 @@ pm9263 arm arm926ejs pm9263 ronetix pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45 cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx da830evm arm arm926ejs da8xxevm davinci davinci -da850_am18xxevm arm arm926ejs da8xxevm davinci davinci +da850_am18xxevm arm arm926ejs da8xxevm davinci davinci da850evm:DA850_AM18X_EVM da850evm arm arm926ejs da8xxevm davinci davinci davinci_dm355evm arm arm926ejs dm355evm davinci davinci davinci_dm355leopard arm arm926ejs dm355leopard davinci davinci @@ -160,6 +160,7 @@ zmx25 arm arm926ejs zmx25 syteco imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 m28evk arm arm926ejs - denx mx28 +mx28evk arm arm926ejs - freescale mx28 nhk8815 arm arm926ejs nhk8815 st nomadik nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND omap1610h2 arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT @@ -193,6 +194,7 @@ mx53loco arm armv7 mx53loco freesca mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg +mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg cm_t35 arm armv7 cm_t35 - omap3 omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 @@ -202,6 +204,7 @@ igep0030 arm armv7 igep0030 isee am3517_evm arm armv7 am3517evm logicpd omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 omap3_zoom2 arm armv7 zoom2 logicpd omap3 +omap3_logic arm armv7 omap3som logicpd omap3 omap3_mvblx arm armv7 mvblx matrix_vision omap3 am3517_crane arm armv7 am3517crane ti omap3 omap3_beagle arm armv7 beagle ti omap3 @@ -210,6 +213,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +twister arm armv7 twister technexion omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 @@ -244,6 +248,8 @@ xaeniax arm pxa zipitz2 arm pxa colibri_pxa270 arm pxa - toradex jornada arm sa1100 +plutux arm armv7 plutux avionic-design tegra2 +medcom arm armv7 medcom avionic-design tegra2 atngw100 avr32 at32ap - atmel at32ap700x atstk1002 avr32 at32ap atstk1000 atmel at32ap700x atstk1003 avr32 at32ap atstk1000 atmel at32ap700x @@ -360,6 +366,7 @@ adp-ag101p nds32 n1213 adp-ag101p AndesTe nios2-generic nios2 nios2 nios2-generic altera PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent +openrisc-generic openrisc or1200 openrisc-generic openrisc - EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260 EVB64260_750CX powerpc 74xx_7xx evb64260 - - EVB64260 P3G4 powerpc 74xx_7xx evb64260 @@ -590,8 +597,8 @@ MPC837XERDB powerpc mpc83xx mpc837xerdb freesca kmeter1 powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile suvd3 powerpc mpc83xx km83xx keymile -tuda1 powerpc mpc83xx km83xx keymile -tuxa1 powerpc mpc83xx km83xx keymile +tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2 +tuxx1 powerpc mpc83xx km83xx keymile MERGERBOX powerpc mpc83xx mergerbox matrix_vision MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 67cb0dad83..97f29456f9 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -475,6 +475,28 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#elif defined(CONFIG_OPENRISC) + +int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + + print_num("mem start", (ulong)bd->bi_memstart); + print_lnum("mem size", (u64)bd->bi_memsize); + print_num("flash start", (ulong)bd->bi_flashstart); + print_num("flash size", (ulong)bd->bi_flashsize); + print_num("flash offset", (ulong)bd->bi_flashoffset); + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf("ip_addr = %pI4\n", &bd->bi_ip_addr); +#endif + + printf("baudrate = %ld bps\n", bd->bi_baudrate); + + return 0; +} + #else #error "a case for this architecture does not exist!" #endif diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 8946345f19..915a5c046c 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -33,16 +33,6 @@ #include <fpga.h> #include <malloc.h> -#if 0 -#define FPGA_DEBUG -#endif - -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - /* Local functions */ static int fpga_get_op (char *opstr); @@ -76,8 +66,9 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) length = (*dataptr << 8) + *(dataptr+1); dataptr+=2; if (*dataptr++ != 0x61) { - PRINTF ("%s: Design name identifier not recognized in bitstream\n", - __FUNCTION__ ); + debug("%s: Design name identifier not recognized " + "in bitstream\n", + __func__); return FPGA_FAIL; } @@ -90,8 +81,9 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) /* get part number (identifier, length, string) */ if (*dataptr++ != 0x62) { - printf("%s: Part number identifier not recognized in bitstream\n", - __FUNCTION__ ); + printf("%s: Part number identifier not recognized " + "in bitstream\n", + __func__); return FPGA_FAIL; } @@ -104,7 +96,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) /* get date (identifier, length, string) */ if (*dataptr++ != 0x63) { printf("%s: Date identifier not recognized in bitstream\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } @@ -116,7 +108,8 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) /* get time (identifier, length, string) */ if (*dataptr++ != 0x64) { - printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__); + printf("%s: Time identifier not recognized in bitstream\n", + __func__); return FPGA_FAIL; } @@ -129,7 +122,7 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) /* get fpga data length (identifier, length) */ if (*dataptr++ != 0x65) { printf("%s: Data length identifier not recognized in bitstream\n", - __FUNCTION__); + __func__); return FPGA_FAIL; } swapsize = ((unsigned int) *dataptr <<24) + @@ -183,39 +176,43 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) if (fit_parse_subimage (argv[3], (ulong)fpga_data, &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; - debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n", - fit_uname, fit_addr); + debug("* fpga: subimage '%s' from FIT image " + "at 0x%08lx\n", + fit_uname, fit_addr); } else #endif { fpga_data = (void *) simple_strtoul (argv[3], NULL, 16); - debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); + debug("* fpga: cmdline image address = 0x%08lx\n", + (ulong)fpga_data); } - PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data); + debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data); case 3: /* fpga <op> <dev | data addr> */ dev = (int) simple_strtoul (argv[2], NULL, 16); - PRINTF ("%s: device = %d\n", __FUNCTION__, dev); + debug("%s: device = %d\n", __func__, dev); /* FIXME - this is a really weak test */ if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */ - PRINTF ("%s: Assuming buffer pointer in arg 3\n", - __FUNCTION__); + debug("%s: Assuming buffer pointer in arg 3\n", + __func__); #if defined(CONFIG_FIT) if (fit_parse_subimage (argv[2], (ulong)fpga_data, &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; - debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n", - fit_uname, fit_addr); + debug("* fpga: subimage '%s' from FIT image " + "at 0x%08lx\n", + fit_uname, fit_addr); } else #endif { fpga_data = (void *) dev; - debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data); + debug("* fpga: cmdline image address = " + "0x%08lx\n", (ulong)fpga_data); } - PRINTF ("%s: fpga_data = 0x%x\n", - __FUNCTION__, (uint) fpga_data); + debug("%s: fpga_data = 0x%x\n", + __func__, (uint) fpga_data); dev = FPGA_INVALID_DEVICE; /* reset device num */ } @@ -224,8 +221,8 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) break; default: - PRINTF ("%s: Too many or too few args (%d)\n", - __FUNCTION__, argc); + debug("%s: Too many or too few args (%d)\n", + __func__, argc); op = FPGA_NONE; /* force usage display */ break; } diff --git a/common/env_common.c b/common/env_common.c index 8a7109645d..71811c4d2a 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -124,6 +124,13 @@ const uchar default_environment[] = { struct hsearch_data env_htab; +static uchar __env_get_char_spec(int index) +{ + return *((uchar *)(gd->env_addr + index)); +} +uchar env_get_char_spec(int) + __attribute__((weak, alias("__env_get_char_spec"))); + static uchar env_get_char_init(int index) { /* if crc was bad, use the default environment */ diff --git a/common/env_flash.c b/common/env_flash.c index a99f850e91..aa970d4400 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -73,11 +73,6 @@ static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1; #endif /* CONFIG_ENV_ADDR_REDUND */ -uchar env_get_char_spec(int index) -{ - return *((uchar *)(gd->env_addr + index)); -} - #ifdef CONFIG_ENV_ADDR_REDUND int env_init(void) { diff --git a/common/env_mgdisk.c b/common/env_mgdisk.c index 5dd92e709c..d00e141d5b 100644 --- a/common/env_mgdisk.c +++ b/common/env_mgdisk.c @@ -33,11 +33,6 @@ env_t *env_ptr; DECLARE_GLOBAL_DATA_PTR; -uchar env_get_char_spec(int index) -{ - return *((uchar *)(gd->env_addr + index)); -} - void env_relocate_spec(void) { char buf[CONFIG_ENV_SIZE]; diff --git a/common/env_mmc.c b/common/env_mmc.c index 8441c77ead..0c58ae19b2 100644 --- a/common/env_mmc.c +++ b/common/env_mmc.c @@ -54,11 +54,6 @@ static int __mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) __attribute__((weak, alias("__mmc_get_env_addr"))); -uchar env_get_char_spec(int index) -{ - return *((uchar *)(gd->env_addr + index)); -} - int env_init(void) { /* use default */ diff --git a/common/env_nand.c b/common/env_nand.c index 3cb75c8962..e8daec9712 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -66,11 +66,6 @@ env_t *env_ptr; DECLARE_GLOBAL_DATA_PTR; -uchar env_get_char_spec(int index) -{ - return *((uchar *)(gd->env_addr + index)); -} - /* * This is called before nand_init() so we can't read NAND to * validate env data. diff --git a/common/env_nowhere.c b/common/env_nowhere.c index 8a3ca1978f..18fcf2ca41 100644 --- a/common/env_nowhere.c +++ b/common/env_nowhere.c @@ -37,11 +37,6 @@ void env_relocate_spec(void) { } -uchar env_get_char_spec(int index) -{ - return *((uchar *)(gd->env_addr + index)); -} - /* * Initialize Environment use * diff --git a/common/env_nvram.c b/common/env_nvram.c index 726eaac55e..6483db39d3 100644 --- a/common/env_nvram.c +++ b/common/env_nvram.c @@ -59,18 +59,16 @@ env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; char *env_name_spec = "NVRAM"; +#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE uchar env_get_char_spec(int index) { -#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE uchar c; nvram_read(&c, CONFIG_ENV_ADDR + index, 1); return c; -#else - return *((uchar *)(gd->env_addr + index)); -#endif } +#endif void env_relocate_spec(void) { diff --git a/common/env_onenand.c b/common/env_onenand.c index 0ad2fc7a4c..652665a189 100644 --- a/common/env_onenand.c +++ b/common/env_onenand.c @@ -44,11 +44,6 @@ char *env_name_spec = "OneNAND"; DECLARE_GLOBAL_DATA_PTR; -uchar env_get_char_spec(int index) -{ - return *((uchar *)(gd->env_addr + index)); -} - void env_relocate_spec(void) { struct mtd_info *mtd = &onenand_mtd; diff --git a/common/env_sf.c b/common/env_sf.c index 592b87088e..bbd472fcf2 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -59,11 +59,6 @@ char *env_name_spec = "SPI Flash"; static struct spi_flash *env_flash; -uchar env_get_char_spec(int index) -{ - return *((uchar *)(gd->env_addr + index)); -} - #if defined(CONFIG_ENV_OFFSET_REDUND) int saveenv(void) { diff --git a/common/image.c b/common/image.c index 77ca6e4705..202c8a1ca8 100644 --- a/common/image.c +++ b/common/image.c @@ -94,6 +94,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_BLACKFIN, "blackfin", "Blackfin", }, { IH_ARCH_AVR32, "avr32", "AVR32", }, { IH_ARCH_NDS32, "nds32", "NDS32", }, + { IH_ARCH_OPENRISC, "or1k", "OpenRISC 1000",}, { -1, "", "", }, }; diff --git a/common/usb_storage.c b/common/usb_storage.c index d9a2585d58..de84c8d7d0 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -151,6 +151,7 @@ struct us_data { unsigned int irqpipe; /* pipe for release_irq */ unsigned char irqmaxp; /* max packed for irq Pipe */ unsigned char irqinterval; /* Intervall for IRQ Pipe */ + unsigned long max_xfer_blk; /* Max blocks per xfer */ ccb *srb; /* current srb */ trans_reset transport_reset; /* reset routine */ trans_cmnd transport; /* transport routine */ @@ -1041,14 +1042,13 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor, } #endif /* CONFIG_USB_BIN_FIXUP */ -#define USB_MAX_READ_BLK 20 - unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer) { unsigned long start, blks, buf_addr; unsigned short smallblks; struct usb_device *dev; + struct us_data *ss; int retry, i; ccb *srb = &usb_ccb; @@ -1066,13 +1066,14 @@ unsigned long usb_stor_read(int device, unsigned long blknr, if (dev->devnum == usb_dev_desc[device].target) break; } + ss = (struct us_data *)dev->privptr; usb_disable_asynch(1); /* asynch transfer not allowed */ srb->lun = usb_dev_desc[device].lun; buf_addr = (unsigned long)buffer; start = blknr; blks = blkcnt; - if (usb_test_unit_ready(srb, (struct us_data *)dev->privptr)) { + if (usb_test_unit_ready(srb, ss)) { printf("Device NOT ready\n Request Sense returned %02X %02X" " %02X\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); @@ -1086,19 +1087,18 @@ unsigned long usb_stor_read(int device, unsigned long blknr, /* XXX need some comment here */ retry = 2; srb->pdata = (unsigned char *)buf_addr; - if (blks > USB_MAX_READ_BLK) - smallblks = USB_MAX_READ_BLK; + if (blks > ss->max_xfer_blk) + smallblks = ss->max_xfer_blk; else smallblks = (unsigned short) blks; retry_it: - if (smallblks == USB_MAX_READ_BLK) + if (smallblks == ss->max_xfer_blk) usb_show_progress(); srb->datalen = usb_dev_desc[device].blksz * smallblks; srb->pdata = (unsigned char *)buf_addr; - if (usb_read_10(srb, (struct us_data *)dev->privptr, start, - smallblks)) { + if (usb_read_10(srb, ss, start, smallblks)) { USB_STOR_PRINTF("Read ERROR\n"); - usb_request_sense(srb, (struct us_data *)dev->privptr); + usb_request_sense(srb, ss); if (retry--) goto retry_it; blkcnt -= blks; @@ -1113,19 +1113,18 @@ retry_it: start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ - if (blkcnt >= USB_MAX_READ_BLK) + if (blkcnt >= ss->max_xfer_blk) debug("\n"); return blkcnt; } -#define USB_MAX_WRITE_BLK 20 - unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer) { unsigned long start, blks, buf_addr; unsigned short smallblks; struct usb_device *dev; + struct us_data *ss; int retry, i; ccb *srb = &usb_ccb; @@ -1143,6 +1142,7 @@ unsigned long usb_stor_write(int device, unsigned long blknr, if (dev->devnum == usb_dev_desc[device].target) break; } + ss = (struct us_data *)dev->privptr; usb_disable_asynch(1); /* asynch transfer not allowed */ @@ -1150,7 +1150,7 @@ unsigned long usb_stor_write(int device, unsigned long blknr, buf_addr = (unsigned long)buffer; start = blknr; blks = blkcnt; - if (usb_test_unit_ready(srb, (struct us_data *)dev->privptr)) { + if (usb_test_unit_ready(srb, ss)) { printf("Device NOT ready\n Request Sense returned %02X %02X" " %02X\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]); @@ -1166,19 +1166,18 @@ unsigned long usb_stor_write(int device, unsigned long blknr, */ retry = 2; srb->pdata = (unsigned char *)buf_addr; - if (blks > USB_MAX_WRITE_BLK) - smallblks = USB_MAX_WRITE_BLK; + if (blks > ss->max_xfer_blk) + smallblks = ss->max_xfer_blk; else smallblks = (unsigned short) blks; retry_it: - if (smallblks == USB_MAX_WRITE_BLK) + if (smallblks == ss->max_xfer_blk) usb_show_progress(); srb->datalen = usb_dev_desc[device].blksz * smallblks; srb->pdata = (unsigned char *)buf_addr; - if (usb_write_10(srb, (struct us_data *)dev->privptr, start, - smallblks)) { + if (usb_write_10(srb, ss, start, smallblks)) { USB_STOR_PRINTF("Write ERROR\n"); - usb_request_sense(srb, (struct us_data *)dev->privptr); + usb_request_sense(srb, ss); if (retry--) goto retry_it; blkcnt -= blks; @@ -1193,7 +1192,7 @@ retry_it: start, smallblks, buf_addr); usb_disable_asynch(0); /* asynch transfer allowed */ - if (blkcnt >= USB_MAX_WRITE_BLK) + if (blkcnt >= ss->max_xfer_blk) debug("\n"); return blkcnt; @@ -1419,6 +1418,12 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, USB_STOR_PRINTF(" address %d\n", dev_desc->target); USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type); + /* + * The U-Boot EHCI driver cannot handle more than 4096 * 5 bytes in a + * transfer without running itself out of qt_buffers. + */ + ss->max_xfer_blk = (4096 * 5) / dev_desc->blksz; + init_part(dev_desc); USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type); diff --git a/doc/README.SPL b/doc/README.SPL index 89d24a7205..f01a8bd911 100644 --- a/doc/README.SPL +++ b/doc/README.SPL @@ -65,3 +65,4 @@ CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o) CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o) CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o) CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o) +CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o) diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci index dee0cf0a9b..0cbd909829 100644 --- a/doc/README.atmel_mci +++ b/doc/README.atmel_mci @@ -59,17 +59,9 @@ int board_mmc_init(bd_t *bd) } /* this is a weak define that we are overriding */ -int board_mmc_getcd(u8 *cd, struct mmc *mmc) +int board_mmc_getcd(struct mmc *mmc) { - /* - * the only currently existing use of this function - * (fsl_esdhc.c) suggests this function must return - * *cs = TRUE if a card is NOT detected -> in most - * cases the value of the pin when the detect switch - * closes to GND - */ - *cd = at91_get_gpio_value (CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; - return 0; + return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); } #endif diff --git a/doc/README.davinci b/doc/README.davinci index 5f1bdc836c..aa7c85011a 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -95,6 +95,15 @@ into the RAM. The programmers and UBL are always released as part of any standard TI software release associated with an SOC. +Alternative boot method (DA850 EVM only): +For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL) +is provided to load U-Boot directly from SPI flash. In this case, the +SPL does the low level initialization that is otherwise done by the SPL. +To build U-Boot with this SPL, do +make da850evm_config +make u-boot.ais +and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM. + Environment Variables ===================== diff --git a/doc/README.mx6qsabrelite b/doc/README.mx6qsabrelite new file mode 100644 index 0000000000..4add2bf352 --- /dev/null +++ b/doc/README.mx6qsabrelite @@ -0,0 +1,67 @@ +U-Boot for the Freescale i.MX6q SabreLite board + +This file contains information for the port of U-Boot to the Freescale +i.MX6q SabreLite board. + +1. Boot source, boot from SD card +--------------------------------- + +The recent mainline U-Boot for the Freescale i.MX6q SabreLite board supports +boot from SD card only. However, by default, the early version of SabreLite +boards boot from the SPI NOR flash. These boards need to be reflashed with +a small SD card loader to support boot from SD card. This small SD card loader +will be flashed into the SPI NOR. The board will still boot from SPI NOR, but +the loader will in turn request the BootROM to load the U-Boot from SD card. +At the moment of writing, please check with Freescale on the availablity of +this small SD loader binary. + +To update the SPI-NOR on the SabreLite board without the Freescale +manufacturing tool use the following procedure: + +1. Write this SD card loader onto a large SD card using: + + sudo dd if=MX6_SPI_to_SD_loader.bin of=/dev/sXx + +Note: Replace sXx with the device representing the SD card in your system. + +Note: This writes SD card loader at address 0 + +2. Put this SD card into the slot for the large SD card (SD3 on the bottom of +the board) + +3. Power-up the SabreLite, press 'space' to enter command mode in the U-Boot +(the default one the board is shipped with, starting from the SPI NOR) and +enter the following commands: + + MX6Q SABRELITE U-Boot > mmc dev 0 + MX6Q SABRELITE U-Boot > mmc read 0x10800000 0 200 + MX6Q SABRELITE U-Boot > sf probe 1 + MX6Q SABRELITE U-Boot > sf erase 0 0x40000 + MX6Q SABRELITE U-Boot > sf write 0x10800000 0 0x40000 + +4. done. + +In case you somehow do not succeed with this procedure you will have to use +the Freescale manufacturing tool in order to reflash the SPI-NOR. + +Note: The board now boots from full size SD3 on the bottom of the board. NOT + the micro SD4/BOOT slot on the top of the board. I.e. you have to use + full size SD cards. + +This information is taken from + +https://wiki.linaro.org/Boards/MX6QSabreLite + +2. Build +-------- + +To build U-Boot for the SabreLite board: + + make mx6qsabrelite_config + make u-boot.imx + +To copy the resulting u-boot.imx to the SD card: + + sudo dd if=u-boot.imx of=/dev/sXx bs=512 seek=2&&sudo sync + +Note: Replace sXx with the device representing the SD card in your system. diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index 6cbe12f1f5..0f3f5432f2 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -62,6 +62,43 @@ a 33MHz PCI configuration is currently untested.) 02.00.00 0x1148 0x9e00 Network controller 0x00 => +Memory Size and using SPD: +========================== + +The default configuration uses hard coded memory configuration settings +for 256MB of DDR2 @400MHz. It does not by default use the DDR2 SPD +EEPROM data to read what memory is installed. + +There is a hardware errata, which causes the older local bus SDRAM +SPD EEPROM to land at the same address as the DDR2 SPD EEPROM, so +that the SPD data can not be read reliably. You can test if your +board has the errata fix by running "i2c probe". If you see 0x53 +as a valid device, it has been fixed. If you only see 0x50, 0x51 +then your board does not have the fix. + +You can also visually inspect the board to see if this hardware +fix has been applied: + + 1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on + the back of the PCB behind the DDR SDRAM SODIMM connector. + 2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad + to R313 pin 2. Pin 2 for each resistor is the end of the + resistor closest to the CPU. + +Boards without the mod will have R314 and R313 in parallel, like "||". +After the mod, they will be touching and form an "L" shape. + +If you want to upgrade to larger RAM size, you can simply enable + #define CONFIG_SPD_EEPROM + #define CONFIG_DDR_SPD +in include/configs/sbc8548.h file. (The lines are already there +but listed as #undef). + +If you did the i2c test, and your board does not have the errata +fix, then you will have to physically remove the LBC 128MB DIMM +from the board's socket to resolve the above i2c address overlap +issue and allow SPD autodetection of RAM to work. + Updating U-boot with U-boot: ============================ @@ -86,6 +123,33 @@ The "md" steps in the above are just a precautionary step that allow you to confirm the u-boot version that was downloaded, and then confirm that it was copied to flash. +The above assumes that you are using the default board settings which +have u-boot in the 8MB flash, tied to /CS0. + +If you are running the default 8MB /CS0 settings but want to store an +image in the SODIMM that is built with CONFIG_SYS_ALT_BOOT enabled, +(as a backup, etc) then the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era eff00000 efffffff + cp.b 200000 eff00000 100000 + md eff00000 10 + protect on all + +Finally, if you are running the alternate 64MB /CS0 settings and want +to update the in-use u-boot image, then (again with CONFIG_SYS_ALT_BOOT +enabled) the steps will become: + + tftp u-boot.bin + md 200000 10 + protect off all + era fff00000 ffffffff + cp.b 200000 fff00000 100000 + md fff00000 10 + protect on all + Hardware Reference: =================== @@ -100,6 +164,9 @@ Boot flash: Sodimm flash: intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + Note that this address reflects the default setting for + the JTAG debugging tools, but since the alignment is + rather inconvenient, u-boot puts it at 0xec00_0000. Jumpers: @@ -124,10 +191,9 @@ JP19 PCI mode PCI PCI-X onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the SODIMM flash and /CS6 is for the boot flash. Note that in this -alternate setting, you also need to switch SW2.8 to ON. Currently -u-boot doesn't support booting off the SODIMM in this alternate -setting without manually altering BR0/OR0 and BR6/OR6 in the -board config file appropriately. +alternate setting, you also need to switch SW2.8 to ON. +See the setting CONFIG_SYS_ALT_BOOT if you want to use this setting +and boot u-boot from the 64MB SODIMM Switches: @@ -187,9 +253,12 @@ start end CS<n> width Desc. 0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) f800_0000 f8b0_1fff CS5 - EPLD -fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) [*] ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) +[*] fb80 represents the default programmed by WR JTAG register files, + but u-boot places the flash at either ec00 or fc00 based on JP12. + The EPLD on CS5 demuxes the following devices at the following offsets: offset size width device diff --git a/doc/git-mailrc b/doc/git-mailrc index 4039e55f5c..96f1d86e2b 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -39,16 +39,17 @@ alias arches arch alias arm uboot, aaribaud alias at91 uboot, reinhardm -alias davinci omap +alias davinci ti alias imx uboot, sbabic alias kirkwood uboot, prafulla -alias omap uboot, Sandeep Paulraj <s-paulraj@ti.com> +alias omap ti alias pxa uboot, marex alias s3c samsung alias s5pc samsung alias samsung uboot, prom alias tegra uboot, Simon Glass <sjg@chromium.org>, Tom Warren <twarren@nvidia.com>, Stephen Warren <swarren@nvidia.com> alias tegra2 tegra +alias ti uboot, Sandeep Paulraj <s-paulraj@ti.com>, Tom Rini <trini@ti.com> alias avr32 uboot, reinhardm diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 9207391249..1633a7069d 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -38,7 +38,6 @@ #endif #undef CONFIG_SYS_FPGA_CHECK_BUSY -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index e22c09689d..4375a55267 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_S5P) += s5p_gpio.o COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o +COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/da8xx_gpio.c b/drivers/gpio/da8xx_gpio.c index 74b58e889f..84d2b77d92 100644 --- a/drivers/gpio/da8xx_gpio.c +++ b/drivers/gpio/da8xx_gpio.c @@ -23,7 +23,6 @@ #include <common.h> #include <asm/io.h> #include <asm/gpio.h> -#include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/davinci_misc.h> @@ -181,87 +180,93 @@ static const struct pinmux_config gpio_pinmux[] = { { pinmux(18), 8, 2 }, }; -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (gp >= MAX_NUM_GPIOS) + if (gpio >= MAX_NUM_GPIOS) return -1; - if (gpio_registry[gp].is_registered) + if (gpio_registry[gpio].is_registered) return -1; - gpio_registry[gp].is_registered = 1; - strncpy(gpio_registry[gp].name, label, GPIO_NAME_SIZE); - gpio_registry[gp].name[GPIO_NAME_SIZE - 1] = 0; + gpio_registry[gpio].is_registered = 1; + strncpy(gpio_registry[gpio].name, label, GPIO_NAME_SIZE); + gpio_registry[gpio].name[GPIO_NAME_SIZE - 1] = 0; - davinci_configure_pin_mux(&gpio_pinmux[gp], 1); + davinci_configure_pin_mux(&gpio_pinmux[gpio], 1); return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { - gpio_registry[gp].is_registered = 0; -} + if (gpio >= MAX_NUM_GPIOS) + return -1; -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); + if (!gpio_registry[gpio].is_registered) + return -1; + + gpio_registry[gpio].is_registered = 0; + gpio_registry[gpio].name[0] = '\0'; + /* Do not configure as input or change pin mux here */ + return 0; } -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { struct davinci_gpio *bank; - bank = GPIO_BANK(gp); - setbits_le32(&bank->dir, 1U << GPIO_BIT(gp)); + bank = GPIO_BANK(gpio); + setbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); return 0; } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { struct davinci_gpio *bank; - bank = GPIO_BANK(gp); - clrbits_le32(&bank->dir, 1U << GPIO_BIT(gp)); - gpio_set_value(gp, value); + bank = GPIO_BANK(gpio); + clrbits_le32(&bank->dir, 1U << GPIO_BIT(gpio)); + gpio_set_value(gpio, value); return 0; } -int gpio_get_value(int gp) +int gpio_get_value(unsigned gpio) { struct davinci_gpio *bank; unsigned int ip; - bank = GPIO_BANK(gp); - ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gp)); + bank = GPIO_BANK(gpio); + ip = in_le32(&bank->in_data) & (1U << GPIO_BIT(gpio)); return ip ? 1 : 0; } -void gpio_set_value(int gp, int value) +int gpio_set_value(unsigned gpio, int value) { struct davinci_gpio *bank; - bank = GPIO_BANK(gp); + bank = GPIO_BANK(gpio); if (value) - bank->set_data = 1U << GPIO_BIT(gp); + bank->set_data = 1U << GPIO_BIT(gpio); else - bank->clr_data = 1U << GPIO_BIT(gp); + bank->clr_data = 1U << GPIO_BIT(gpio); + + return 0; } void gpio_info(void) { - int gp, dir, val; + unsigned gpio, dir, val; struct davinci_gpio *bank; - for (gp = 0; gp < MAX_NUM_GPIOS; ++gp) { - bank = GPIO_BANK(gp); - dir = in_le32(&bank->dir) & (1U << GPIO_BIT(gp)); - val = gpio_get_value(gp); + for (gpio = 0; gpio < MAX_NUM_GPIOS; ++gpio) { + bank = GPIO_BANK(gpio); + dir = in_le32(&bank->dir) & (1U << GPIO_BIT(gpio)); + val = gpio_get_value(gpio); printf("% 4d: %s: %d [%c] %s\n", - gp, dir ? " in" : "out", val, - gpio_registry[gp].is_registered ? 'x' : ' ', - gpio_registry[gp].name); + gpio, dir ? " in" : "out", val, + gpio_registry[gpio].is_registered ? 'x' : ' ', + gpio_registry[gpio].name); } } diff --git a/drivers/gpio/mpc83xx_gpio.c b/drivers/gpio/mpc83xx_gpio.c new file mode 100644 index 0000000000..a9afcb2dd6 --- /dev/null +++ b/drivers/gpio/mpc83xx_gpio.c @@ -0,0 +1,199 @@ +/* + * Freescale MPC83xx GPIO handling. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc83xx.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#ifndef CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION +#define CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION +#define CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN +#define CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN +#define CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_0_INIT_VALUE +#define CONFIG_MPC83XX_GPIO_0_INIT_VALUE 0 +#endif +#ifndef CONFIG_MPC83XX_GPIO_1_INIT_VALUE +#define CONFIG_MPC83XX_GPIO_1_INIT_VALUE 0 +#endif + +static unsigned int gpio_output_value[MPC83XX_GPIO_CTRLRS]; + +/* + * Generic_GPIO primitives. + */ + +int gpio_request(unsigned gpio, const char *label) +{ + if (gpio >= MAX_NUM_GPIOS) + return -1; + + return 0; +} + +int gpio_free(unsigned gpio) +{ + /* Do not set to input */ + return 0; +} + +/* set GPIO pin 'gpio' as an input */ +int gpio_direction_input(unsigned gpio) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + clrbits_be32(&im->gpio[ctrlr].dir, line_mask); + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +int gpio_direction_output(unsigned gpio, int value) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + if (value != 0 && value != 1) { + printf("Error: Value parameter must be 0 or 1.\n"); + return -1; + } + + gpio_set_value(gpio, value); + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + /* Make the line output */ + setbits_be32(&im->gpio[ctrlr].dir, line_mask); + + return 0; +} + +/* read GPIO IN value of pin 'gpio' */ +int gpio_get_value(unsigned gpio) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + /* Read the value and mask off the bit */ + return (in_be32(&im->gpio[ctrlr].dat) & line_mask) != 0; +} + +/* write GPIO OUT value to pin 'gpio' */ +int gpio_set_value(unsigned gpio, int value) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + unsigned int ctrlr; + unsigned int line; + unsigned int line_mask; + + if (value != 0 && value != 1) { + printf("Error: Value parameter must be 0 or 1.\n"); + return -1; + } + + /* 32-bits per controller */ + ctrlr = gpio >> 5; + line = gpio & (0x1F); + + /* Big endian */ + line_mask = 1 << (31 - line); + + /* Update the local output buffer soft copy */ + gpio_output_value[ctrlr] = + (gpio_output_value[ctrlr] & ~line_mask) | \ + (value ? line_mask : 0); + + /* Write the output */ + out_be32(&im->gpio[ctrlr].dat, gpio_output_value[ctrlr]); + + return 0; +} + +/* Configure GPIO registers early */ +void mpc83xx_gpio_init_f() +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + +#if MPC83XX_GPIO_CTRLRS >= 1 + out_be32(&im->gpio[0].dir, CONFIG_MPC83XX_GPIO_0_INIT_DIRECTION); + out_be32(&im->gpio[0].odr, CONFIG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN); + out_be32(&im->gpio[0].dat, CONFIG_MPC83XX_GPIO_0_INIT_VALUE); + out_be32(&im->gpio[0].ier, 0xFFFFFFFF); /* Clear all events */ + out_be32(&im->gpio[0].imr, 0); + out_be32(&im->gpio[0].icr, 0); +#endif + +#if MPC83XX_GPIO_CTRLRS >= 2 + out_be32(&im->gpio[1].dir, CONFIG_MPC83XX_GPIO_1_INIT_DIRECTION); + out_be32(&im->gpio[1].odr, CONFIG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN); + out_be32(&im->gpio[1].dat, CONFIG_MPC83XX_GPIO_1_INIT_VALUE); + out_be32(&im->gpio[1].ier, 0xFFFFFFFF); /* Clear all events */ + out_be32(&im->gpio[1].imr, 0); + out_be32(&im->gpio[1].icr, 0); +#endif +} + +/* Initialize GPIO soft-copies */ +void mpc83xx_gpio_init_r() +{ +#if MPC83XX_GPIO_CTRLRS >= 1 + gpio_output_value[0] = CONFIG_MPC83XX_GPIO_0_INIT_VALUE; +#endif + +#if MPC83XX_GPIO_CTRLRS >= 2 + gpio_output_value[1] = CONFIG_MPC83XX_GPIO_1_INIT_VALUE; +#endif +} diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c index 276f206ccd..c80891cd50 100644 --- a/drivers/gpio/mvgpio.c +++ b/drivers/gpio/mvgpio.c @@ -35,81 +35,79 @@ #define MV_MAX_GPIO 128 #endif -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO requested %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO requested %d\n", __func__, gpio); + return -1; } return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { + return 0; } -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); -} - -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { struct gpio_reg *gpio_reg_bank; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gcdr); return 0; } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { struct gpio_reg *gpio_reg_bank; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr); - gpio_set_value(gp, value); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gsdr); + gpio_set_value(gpio, value); return 0; } -int gpio_get_value(int gp) +int gpio_get_value(unsigned gpio) { struct gpio_reg *gpio_reg_bank; - u32 gp_val; + u32 gpio_val; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return -EINVAL; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); - gp_val = readl(&gpio_reg_bank->gplr); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); + gpio_val = readl(&gpio_reg_bank->gplr); - return GPIO_VAL(gp, gp_val); + return GPIO_VAL(gpio, gpio_val); } -void gpio_set_value(int gp, int value) +int gpio_set_value(unsigned gpio, int value) { struct gpio_reg *gpio_reg_bank; - if (gp >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gp); - return; + if (gpio >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gpio); + return -1; } - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); if (value) - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpsr); else - writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr); + writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpcr); + + return 0; } diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 908808d50e..df6bbbbc4b 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -58,7 +58,7 @@ static int mxc_gpio_direction(unsigned int gpio, u32 l; if (port >= ARRAY_SIZE(gpio_ports)) - return -EINVAL; + return -1; gpio &= 0x1f; @@ -78,14 +78,14 @@ static int mxc_gpio_direction(unsigned int gpio, return 0; } -void gpio_set_value(int gpio, int value) +int gpio_set_value(unsigned gpio, int value) { unsigned int port = gpio >> 5; struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) - return; + return -1; gpio &= 0x1f; @@ -97,55 +97,53 @@ void gpio_set_value(int gpio, int value) else l &= ~(1 << gpio); writel(l, ®s->gpio_dr); + + return 0; } -int gpio_get_value(int gpio) +int gpio_get_value(unsigned gpio) { unsigned int port = gpio >> 5; struct gpio_regs *regs; - u32 l; + u32 val; if (port >= ARRAY_SIZE(gpio_ports)) - return -EINVAL; + return -1; gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; - l = (readl(®s->gpio_dr) >> gpio) & 0x01; + val = (readl(®s->gpio_dr) >> gpio) & 0x01; - return l; + return val; } -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - unsigned int port = gp >> 5; + unsigned int port = gpio >> 5; if (port >= ARRAY_SIZE(gpio_ports)) - return -EINVAL; + return -1; return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { + return 0; } -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); -} - -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { - return mxc_gpio_direction(gp, MXC_GPIO_DIRECTION_IN); + return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN); } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { - int ret = mxc_gpio_direction(gp, MXC_GPIO_DIRECTION_OUT); + int ret = mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT); if (ret < 0) return ret; - gpio_set_value(gp, value); + gpio_set_value(gpio, value); return 0; } diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 539738be9b..0365812c0a 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -69,68 +69,64 @@ void mxs_gpio_init(void) } } -int gpio_get_value(int gp) +int gpio_get_value(unsigned gpio) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DIN(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); - return (readl(®->reg) >> PAD_PIN(gp)) & 1; + return (readl(®->reg) >> PAD_PIN(gpio)) & 1; } -void gpio_set_value(int gp, int value) +void gpio_set_value(unsigned gpio, int value) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOUT(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); if (value) - writel(1 << PAD_PIN(gp), ®->reg_set); + writel(1 << PAD_PIN(gpio), ®->reg_set); else - writel(1 << PAD_PIN(gp), ®->reg_clr); + writel(1 << PAD_PIN(gpio), ®->reg_clr); } -int gpio_direction_input(int gp) +int gpio_direction_input(unsigned gpio) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); - writel(1 << PAD_PIN(gp), ®->reg_clr); + writel(1 << PAD_PIN(gpio), ®->reg_clr); return 0; } -int gpio_direction_output(int gp, int value) +int gpio_direction_output(unsigned gpio, int value) { - uint32_t bank = PAD_BANK(gp); + uint32_t bank = PAD_BANK(gpio); uint32_t offset = PINCTRL_DOE(bank); struct mx28_register *reg = (struct mx28_register *)(MXS_PINCTRL_BASE + offset); - writel(1 << PAD_PIN(gp), ®->reg_set); + writel(1 << PAD_PIN(gpio), ®->reg_set); - gpio_set_value(gp, value); + gpio_set_value(gpio, value); return 0; } -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (PAD_BANK(gp) >= PINCTRL_BANKS) - return -EINVAL; + if (PAD_BANK(gpio) >= PINCTRL_BANKS) + return -1; return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { -} - -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_value(gp)); + return 0; } diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 1edf9a26a2..47f3213927 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -20,7 +20,7 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/gpio.h> +#include <asm/gpio.h> #define CON_MASK(x) (0xf << ((x) << 2)) #define CON_SFR(x, v) ((v) << ((x) << 2)) @@ -142,46 +142,55 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -struct s5p_gpio_bank *s5p_gpio_get_bank(int nr) +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) { - int bank = nr / GPIO_PER_BANK; + int bank = gpio / GPIO_PER_BANK; bank *= sizeof(struct s5p_gpio_bank); - return (struct s5p_gpio_bank *) (s5p_gpio_base(nr) + bank); + return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); } -int s5p_gpio_get_pin(int nr) +int s5p_gpio_get_pin(unsigned gpio) { - return nr % GPIO_PER_BANK; + return gpio % GPIO_PER_BANK; } -int gpio_request(int gpio, const char *label) +/* Common GPIO API */ + +int gpio_request(unsigned gpio, const char *label) { return 0; } -int gpio_direction_input(int nr) +int gpio_free(unsigned gpio) { - s5p_gpio_direction_input(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr)); return 0; } -int gpio_direction_output(int nr, int value) +int gpio_direction_input(unsigned gpio) { - s5p_gpio_direction_output(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr), value); + s5p_gpio_direction_input(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio)); return 0; } -int gpio_get_value(int nr) +int gpio_direction_output(unsigned gpio, int value) { - return (int) s5p_gpio_get_value(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr)); + s5p_gpio_direction_output(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), value); + return 0; } -void gpio_set_value(int nr, int value) +int gpio_get_value(unsigned gpio) { - s5p_gpio_set_value(s5p_gpio_get_bank(nr), - s5p_gpio_get_pin(nr), value); + return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio)); +} + +int gpio_set_value(unsigned gpio, int value) +{ + s5p_gpio_set_value(s5p_gpio_get_bank(gpio), + s5p_gpio_get_pin(gpio), value); + + return 0; } diff --git a/drivers/gpio/tegra2_gpio.c b/drivers/gpio/tegra2_gpio.c index 22669b6160..70ca46fae5 100644 --- a/drivers/gpio/tegra2_gpio.c +++ b/drivers/gpio/tegra2_gpio.c @@ -49,188 +49,192 @@ static char *get_name(int i) return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN"; } -/* Return config of pin 'gp' as GPIO (1) or SFPIO (0) */ -static int get_config(int gp) +/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ +static int get_config(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; int type; - u = readl(&bank->gpio_config[GPIO_PORT(gp)]); - type = (u >> GPIO_BIT(gp)) & 1; + u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); + type = (u >> GPIO_BIT(gpio)) & 1; debug("get_config: port = %d, bit = %d is %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), type ? "GPIO" : "SFPIO"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); return type; } -/* Config pin 'gp' as GPIO or SFPIO, based on 'type' */ -static void set_config(int gp, int type) +/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ +static void set_config(unsigned gpio, int type) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; debug("set_config: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), type ? "GPIO" : "SFPIO"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - u = readl(&bank->gpio_config[GPIO_PORT(gp)]); + u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); if (type) /* GPIO */ - u |= 1 << GPIO_BIT(gp); + u |= 1 << GPIO_BIT(gpio); else - u &= ~(1 << GPIO_BIT(gp)); - writel(u, &bank->gpio_config[GPIO_PORT(gp)]); + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); } -/* Return GPIO pin 'gp' direction - 0 = input or 1 = output */ -static int get_direction(int gp) +/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ +static int get_direction(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; int dir; - u = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); - dir = (u >> GPIO_BIT(gp)) & 1; + u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); + dir = (u >> GPIO_BIT(gpio)) & 1; debug("get_direction: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), dir ? "OUT" : "IN"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); return dir; } -/* Config GPIO pin 'gp' as input or output (OE) as per 'output' */ -static void set_direction(int gp, int output) +/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ +static void set_direction(unsigned gpio, int output) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; debug("set_direction: port = %d, bit = %d, %s\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), output ? "OUT" : "IN"); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); - u = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]); + u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); if (output) - u |= 1 << GPIO_BIT(gp); + u |= 1 << GPIO_BIT(gpio); else - u &= ~(1 << GPIO_BIT(gp)); - writel(u, &bank->gpio_dir_out[GPIO_PORT(gp)]); + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); } -/* set GPIO pin 'gp' output bit as 0 or 1 as per 'high' */ -static void set_level(int gp, int high) +/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ +static void set_level(unsigned gpio, int high) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; u32 u; debug("set_level: port = %d, bit %d == %d\n", - GPIO_FULLPORT(gp), GPIO_BIT(gp), high); + GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); - u = readl(&bank->gpio_out[GPIO_PORT(gp)]); + u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); if (high) - u |= 1 << GPIO_BIT(gp); + u |= 1 << GPIO_BIT(gpio); else - u &= ~(1 << GPIO_BIT(gp)); - writel(u, &bank->gpio_out[GPIO_PORT(gp)]); + u &= ~(1 << GPIO_BIT(gpio)); + writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); } /* * Generic_GPIO primitives. */ -int gpio_request(int gp, const char *label) +int gpio_request(unsigned gpio, const char *label) { - if (gp >= MAX_NUM_GPIOS) + if (gpio >= MAX_NUM_GPIOS) return -1; if (label != NULL) { - strncpy(gpio_names[gp].name, label, GPIO_NAME_SIZE); - gpio_names[gp].name[GPIO_NAME_SIZE - 1] = '\0'; + strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE); + gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0'; } /* Configure as a GPIO */ - set_config(gp, 1); + set_config(gpio, 1); return 0; } -void gpio_free(int gp) +int gpio_free(unsigned gpio) { + if (gpio >= MAX_NUM_GPIOS) + return -1; + + gpio_names[gpio].name[0] = '\0'; + /* Do not configure as input or change pin mux here */ + return 0; } -/* read GPIO OUT value of pin 'gp' */ -static int gpio_get_output_value(int gp) +/* read GPIO OUT value of pin 'gpio' */ +static int gpio_get_output_value(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; int val; debug("gpio_get_output_value: pin = %d (port %d:bit %d)\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - val = readl(&bank->gpio_out[GPIO_PORT(gp)]); + val = readl(&bank->gpio_out[GPIO_PORT(gpio)]); - return (val >> GPIO_BIT(gp)) & 1; + return (val >> GPIO_BIT(gpio)) & 1; } -void gpio_toggle_value(int gp) -{ - gpio_set_value(gp, !gpio_get_output_value(gp)); -} - -/* set GPIO pin 'gp' as an input */ -int gpio_direction_input(int gp) +/* set GPIO pin 'gpio' as an input */ +int gpio_direction_input(unsigned gpio) { debug("gpio_direction_input: pin = %d (port %d:bit %d)\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); /* Configure GPIO direction as input. */ - set_direction(gp, 0); + set_direction(gpio, 0); return 0; } -/* set GPIO pin 'gp' as an output, with polarity 'value' */ -int gpio_direction_output(int gp, int value) +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +int gpio_direction_output(unsigned gpio, int value) { debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp), value ? "HIGH" : "LOW"); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), + value ? "HIGH" : "LOW"); /* Configure GPIO output value. */ - set_level(gp, value); + set_level(gpio, value); /* Configure GPIO direction as output. */ - set_direction(gp, 1); + set_direction(gpio, 1); return 0; } -/* read GPIO IN value of pin 'gp' */ -int gpio_get_value(int gp) +/* read GPIO IN value of pin 'gpio' */ +int gpio_get_value(unsigned gpio) { - struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)]; + struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; int val; debug("gpio_get_value: pin = %d (port %d:bit %d)\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp)); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - val = readl(&bank->gpio_in[GPIO_PORT(gp)]); + val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); - return (val >> GPIO_BIT(gp)) & 1; + return (val >> GPIO_BIT(gpio)) & 1; } -/* write GPIO OUT value to pin 'gp' */ -void gpio_set_value(int gp, int value) +/* write GPIO OUT value to pin 'gpio' */ +int gpio_set_value(unsigned gpio, int value) { debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", - gp, GPIO_FULLPORT(gp), GPIO_BIT(gp), value); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); /* Configure GPIO output value. */ - set_level(gp, value); + set_level(gpio, value); + + return 0; } /* @@ -238,7 +242,8 @@ void gpio_set_value(int gp, int value) */ void gpio_info(void) { - int c, type; + unsigned c; + int type; for (c = 0; c < MAX_NUM_GPIOS; c++) { type = get_config(c); /* GPIO, not SFPIO */ diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 4ae237aa8e..a7ffd95d5d 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -35,10 +35,15 @@ static void wait_for_bb(void); static u16 wait_for_pin(void); static void flush_fifo(void); -static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE; - -static unsigned int bus_initialized[I2C_BUS_MAX]; -static unsigned int current_bus; +/* + * For SPL boot some boards need i2c before SDRAM is initialised so force + * variables to live in SRAM + */ +static struct i2c __attribute__((section (".data"))) *i2c_base = + (struct i2c *)I2C_DEFAULT_BASE; +static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = + { [0 ... (I2C_BUS_MAX-1)] = 0 }; +static unsigned int __attribute__((section (".data"))) current_bus = 0; void i2c_init(int speed, int slaveadd) { @@ -73,7 +78,7 @@ void i2c_init(int speed, int slaveadd) fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { - printf("Error : I2C initializing first phase clock\n"); + puts("Error : I2C initializing first phase clock\n"); return; } @@ -84,7 +89,7 @@ void i2c_init(int speed, int slaveadd) hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { - printf("Error : I2C initializing second phase clock\n"); + puts("Error : I2C initializing second phase clock\n"); return; } @@ -99,7 +104,7 @@ void i2c_init(int speed, int slaveadd) fssclh -= I2C_FASTSPEED_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { - printf("Error : I2C initializing clock\n"); + puts("Error : I2C initializing clock\n"); return; } @@ -118,7 +123,7 @@ void i2c_init(int speed, int slaveadd) writew(I2C_CON_EN, &i2c_base->con); while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { if (timeout <= 0) { - printf("ERROR: Timeout in soft-reset\n"); + puts("ERROR: Timeout in soft-reset\n"); return; } udelay(1000); @@ -284,13 +289,13 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } if (addr + len > 256) { - printf("I2C read: address out of range\n"); + puts("I2C read: address out of range\n"); return 1; } for (i = 0; i < len; i++) { if (i2c_read_byte(chip, addr + i, &buffer[i])) { - printf("I2C read: I/O error\n"); + puts("I2C read: I/O error\n"); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); return 1; } diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index e6467a2d18..09d443ee39 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -385,6 +385,7 @@ static int arm_pl180_mmci_host_init(struct mmc *dev) dev->send_cmd = host_request; dev->set_ios = host_set_ios; dev->init = mmc_host_reset; + dev->getcd = NULL; dev->host_caps = 0; dev->voltages = VOLTAGE_WINDOW_MMC; dev->f_min = dev->clock; diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index bc9057fa9a..08fc5c1d3e 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -250,6 +250,7 @@ int bfin_mmc_init(bd_t *bis) mmc->send_cmd = bfin_sdh_request; mmc->set_ios = bfin_sdh_set_ios; mmc->init = bfin_sdh_init; + mmc->getcd = NULL; mmc->host_caps = MMC_MODE_4BIT; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index ce96736942..ee8f2614de 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -387,6 +387,7 @@ int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host) mmc->send_cmd = dmmc_send_cmd; mmc->set_ios = dmmc_set_ios; mmc->init = dmmc_init; + mmc->getcd = NULL; mmc->f_min = 200000; mmc->f_max = 25000000; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index ec953f07d7..a2f35e3e99 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -58,7 +58,8 @@ struct fsl_esdhc { uint autoc12err; uint hostcapblt; uint wml; - char reserved1[8]; + uint mixctrl; + char reserved1[4]; uint fevt; char reserved2[168]; uint hostver; @@ -113,7 +114,8 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) static void esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) { - struct fsl_esdhc *regs = mmc->priv; + struct fsl_esdhc_cfg *cfg = mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; uint blocks; char *buffer; uint databuf; @@ -298,8 +300,13 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Send the command */ esdhc_write32(®s->cmdarg, cmd->cmdarg); +#if defined(CONFIG_FSL_USDHC) + esdhc_write32(®s->mixctrl, + (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); + esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); +#else esdhc_write32(®s->xfertyp, xfertyp); - +#endif /* Wait for the command to complete */ while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) ; @@ -412,8 +419,6 @@ static int esdhc_init(struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000; - int ret = 0; - u8 card_absent; /* Reset the entire host controller */ esdhc_write32(®s->sysctl, SYSCTL_RSTA); @@ -440,21 +445,19 @@ static int esdhc_init(struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); - /* Check if there is a callback for detecting the card */ - if (board_mmc_getcd(&card_absent, mmc)) { - timeout = 1000; - while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && - --timeout) - udelay(1000); + return 0; +} - if (timeout <= 0) - ret = NO_CARD_ERR; - } else { - if (card_absent) - ret = NO_CARD_ERR; - } +static int esdhc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + int timeout = 1000; + + while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) + udelay(1000); - return ret; + return timeout > 0; } static void esdhc_reset(struct fsl_esdhc *regs) @@ -482,7 +485,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc = malloc(sizeof(struct mmc)); - sprintf(mmc->name, "FSL_ESDHC"); + sprintf(mmc->name, "FSL_SDHC"); regs = (struct fsl_esdhc *)cfg->esdhc_base; /* First reset the eSDHC controller */ @@ -492,6 +495,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc->send_cmd = esdhc_send_cmd; mmc->set_ios = esdhc_set_ios; mmc->init = esdhc_init; + mmc->getcd = esdhc_getcd; voltage_caps = 0; caps = regs->hostcapblt; diff --git a/drivers/mmc/ftsdc010_esdhc.c b/drivers/mmc/ftsdc010_esdhc.c index e38dd87f18..f1702fe33b 100644 --- a/drivers/mmc/ftsdc010_esdhc.c +++ b/drivers/mmc/ftsdc010_esdhc.c @@ -90,8 +90,13 @@ static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int siz while (size) { status = readl(&host->reg->status); + debug("%s: size: %08x\n", __func__, size); if (status & FTSDC010_STATUS_FIFO_ORUN) { + + debug("%s: FIFO OVERRUN: sta: %08x\n", + __func__, status); + fifo = host->fifo_len > size ? size : host->fifo_len; @@ -146,7 +151,7 @@ static void ftsdc010_pio_write(struct mmc_host *host, const char *buf, while (size) { status = readl(&host->reg->status); - if (status & FTSDC010_STATUS_FIFO_ORUN) { + if (status & FTSDC010_STATUS_FIFO_URUN) { fifo = host->fifo_len > size ? size : host->fifo_len; @@ -158,7 +163,6 @@ static void ftsdc010_pio_write(struct mmc_host *host, const char *buf, writel(*ptr, &host->reg->dwr); ptr++; } - } else { udelay(1); if (++retry >= FTSDC010_PIO_RETRY) { @@ -169,56 +173,19 @@ static void ftsdc010_pio_write(struct mmc_host *host, const char *buf, } } -static int ftsdc010_pio_check_status(struct mmc *mmc, struct mmc_cmd *cmd, +static int ftsdc010_check_rsp(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct mmc_host *host = mmc->priv; - unsigned int sta, clear; - unsigned int i; - - /* check response and hardware status */ - clear = 0; - - /* chech CMD_SEND */ - for (i = 0; i < FTSDC010_CMD_RETRY; i++) { - sta = readl(&host->reg->status); - /* Command Complete */ - if (sta & FTSDC010_STATUS_CMD_SEND) { - if (!data) - clear |= FTSDC010_CLR_CMD_SEND; - break; - } - } - - if (i > FTSDC010_CMD_RETRY) { - printf("%s: send command timeout\n", __func__); - return TIMEOUT; - } - - /* debug: print status register and command index*/ - debug("sta: %08x cmd %d\n", sta, cmd->cmdidx); - /* handle data FIFO */ - if ((sta & FTSDC010_STATUS_FIFO_ORUN) || - (sta & FTSDC010_STATUS_FIFO_URUN)) { - - /* Wrong DATA FIFO Flag */ - if (data == NULL) - printf("%s, data fifo wrong: sta: %08x cmd %d\n", - __func__, sta, cmd->cmdidx); - - if (sta & FTSDC010_STATUS_FIFO_ORUN) - clear |= FTSDC010_STATUS_FIFO_ORUN; - if (sta & FTSDC010_STATUS_FIFO_URUN) - clear |= FTSDC010_STATUS_FIFO_URUN; - } + sta = readl(&host->reg->status); + debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx); /* check RSP TIMEOUT or FAIL */ if (sta & FTSDC010_STATUS_RSP_TIMEOUT) { /* RSP TIMEOUT */ - debug("%s: RSP timeout: sta: %08x cmd %d\n", - __func__, sta, cmd->cmdidx); + debug("%s: RSP timeout: sta: %08x\n", __func__, sta); clear |= FTSDC010_CLR_RSP_TIMEOUT; writel(clear, &host->reg->clr); @@ -226,47 +193,62 @@ static int ftsdc010_pio_check_status(struct mmc *mmc, struct mmc_cmd *cmd, return TIMEOUT; } else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) { /* clear response fail bit */ - debug("%s: RSP CRC FAIL: sta: %08x cmd %d\n", - __func__, sta, cmd->cmdidx); + debug("%s: RSP CRC FAIL: sta: %08x\n", __func__, sta); clear |= FTSDC010_CLR_RSP_CRC_FAIL; writel(clear, &host->reg->clr); - return 0; + return COMM_ERR; } else if (sta & FTSDC010_STATUS_RSP_CRC_OK) { /* clear response CRC OK bit */ clear |= FTSDC010_CLR_RSP_CRC_OK; } + writel(clear, &host->reg->clr); + return 0; +} + +static int ftsdc010_check_data(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc_host *host = mmc->priv; + unsigned int sta, clear; + + sta = readl(&host->reg->status); + debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx); + /* check DATA TIMEOUT or FAIL */ if (data) { + + /* Transfer Complete */ + if (sta & FTSDC010_STATUS_DATA_END) + clear |= FTSDC010_STATUS_DATA_END; + + /* Data CRC_OK */ + if (sta & FTSDC010_STATUS_DATA_CRC_OK) + clear |= FTSDC010_STATUS_DATA_CRC_OK; + + /* DATA TIMEOUT or DATA CRC FAIL */ if (sta & FTSDC010_STATUS_DATA_TIMEOUT) { /* DATA TIMEOUT */ - debug("%s: DATA TIMEOUT: sta: %08x\n", - __func__, sta); + debug("%s: DATA TIMEOUT: sta: %08x\n", __func__, sta); clear |= FTSDC010_STATUS_DATA_TIMEOUT; - writel(sta, &host->reg->clr); + writel(clear, &host->reg->clr); + return TIMEOUT; } else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) { - /* Error Interrupt */ - debug("%s: DATA CRC FAIL: sta: %08x\n", - __func__, sta); + /* DATA CRC FAIL */ + debug("%s: DATA CRC FAIL: sta: %08x\n", __func__, sta); clear |= FTSDC010_STATUS_DATA_CRC_FAIL; writel(clear, &host->reg->clr); - return 0; - } else if (sta & FTSDC010_STATUS_DATA_END) { - /* Transfer Complete */ - clear |= FTSDC010_STATUS_DATA_END; + return COMM_ERR; } + writel(clear, &host->reg->clr); } - - /* transaction is success and clear status register */ - writel(clear, &host->reg->clr); - return 0; } @@ -281,6 +263,9 @@ static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, unsigned int ccon; unsigned int mask, tmpmask; unsigned int ret; + unsigned int sta, i; + + ret = 0; if (data) mask = FTSDC010_INT_MASK_RSP_TIMEOUT; @@ -290,13 +275,9 @@ static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, mask = FTSDC010_INT_MASK_CMD_SEND; /* write argu reg */ - debug("%s: cmd->arg: %08x\n", __func__, cmd->cmdarg); + debug("%s: argu: %08x\n", __func__, host->reg->argu); writel(cmd->cmdarg, &host->reg->argu); - /* setup cmd reg */ - debug("cmd: %d\n", cmd->cmdidx); - debug("resp: %08x\n", cmd->resp_type); - /* setup commnad */ ccon = FTSDC010_CMD_IDX(cmd->cmdidx); @@ -340,7 +321,51 @@ static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, /* write cmd reg */ debug("%s: ccon: %08x\n", __func__, ccon); writel(ccon, &host->reg->cmd); - udelay(4*FTSDC010_DELAY_UNIT); + + /* check CMD_SEND */ + for (i = 0; i < FTSDC010_CMD_RETRY; i++) { + /* + * If we read status register too fast + * will lead hardware error and the RSP_TIMEOUT + * flag will be raised incorrectly. + */ + udelay(16*FTSDC010_DELAY_UNIT); + sta = readl(&host->reg->status); + + /* Command Complete */ + /* + * Note: + * Do not clear FTSDC010_CLR_CMD_SEND flag. + * (by writing FTSDC010_CLR_CMD_SEND bit to clear register) + * It will make the driver becomes very slow. + * If the operation hasn't been finished, hardware will + * clear this bit automatically. + * In origin, the driver will clear this flag if there is + * no data need to be read. + */ + if (sta & FTSDC010_STATUS_CMD_SEND) + break; + } + + if (i > FTSDC010_CMD_RETRY) { + printf("%s: send command timeout\n", __func__); + return TIMEOUT; + } + + /* check rsp status */ + ret = ftsdc010_check_rsp(mmc, cmd, data); + if (ret) + return ret; + + /* read response if we have RSP_OK */ + if (ccon & FTSDC010_CMD_LONG_RSP) { + cmd->response[0] = readl(&host->reg->rsp3); + cmd->response[1] = readl(&host->reg->rsp2); + cmd->response[2] = readl(&host->reg->rsp1); + cmd->response[3] = readl(&host->reg->rsp0); + } else { + cmd->response[0] = readl(&host->reg->rsp0); + } /* read/write data */ if (data && (data->flags & MMC_DATA_READ)) { @@ -351,19 +376,11 @@ static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, data->blocksize * data->blocks); } - /* pio check response status */ - ret = ftsdc010_pio_check_status(mmc, cmd, data); - if (!ret) { - /* if it is long response */ - if (ccon & FTSDC010_CMD_LONG_RSP) { - cmd->response[0] = readl(&host->reg->rsp3); - cmd->response[1] = readl(&host->reg->rsp2); - cmd->response[2] = readl(&host->reg->rsp1); - cmd->response[3] = readl(&host->reg->rsp0); - - } else { - cmd->response[0] = readl(&host->reg->rsp0); - } + /* check data status */ + if (data) { + ret = ftsdc010_check_data(mmc, cmd, data); + if (ret) + return ret; } udelay(FTSDC010_DELAY_UNIT); @@ -431,8 +448,6 @@ static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data) /* always reset fifo since last transfer may fail */ dcon |= FTSDC010_DCR_FIFO_RST; - /* handle sdio */ - dcon = data->blocksize | data->blocks << 15; if (data->blocks > 1) dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE; #endif @@ -497,7 +512,7 @@ static void ftsdc010_set_clk(struct mmc *mmc) { struct mmc_host *host = mmc->priv; unsigned char clk_div; - unsigned char real_rate; + unsigned int real_rate; unsigned int clock; debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock); @@ -518,7 +533,7 @@ static void ftsdc010_set_clk(struct mmc *mmc) break; } - debug("%s: computed real_rete: %x, clk_div: %x\n", + debug("%s: computed real_rate: %x, clk_div: %x\n", __func__, real_rate, clk_div); if (clk_div > 127) @@ -579,6 +594,7 @@ static void ftsdc010_set_ios(struct mmc *mmc) static void ftsdc010_reset(struct mmc_host *host) { unsigned int timeout; + unsigned int sta; /* Do SDC_RST: Software reset for all register */ writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd); @@ -598,6 +614,10 @@ static void ftsdc010_reset(struct mmc_host *host) timeout--; udelay(10*FTSDC010_DELAY_UNIT); } + + sta = readl(&host->reg->status); + if (sta & FTSDC010_STATUS_CARD_CHANGE) + writel(FTSDC010_CLR_CARD_CHANGE, &host->reg->clr); } static int ftsdc010_core_init(struct mmc *mmc) @@ -645,13 +665,12 @@ int ftsdc010_mmc_init(int dev_index) mmc->send_cmd = ftsdc010_request; mmc->set_ios = ftsdc010_set_ios; mmc->init = ftsdc010_core_init; + mmc->getcd = NULL; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; - mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; - mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128); mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2; diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index f346b244be..4968c5e491 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -337,6 +337,7 @@ int atmel_mci_init(void *regs) mmc->send_cmd = mci_send_cmd; mmc->set_ios = mci_set_ios; mmc->init = mci_init; + mmc->getcd = NULL; /* need to be able to pass these in on a board by board basis */ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 21665ecc5b..6db37b1fc5 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -40,11 +40,11 @@ static struct list_head mmc_devices; static int cur_dev_num = -1; -int __board_mmc_getcd(u8 *cd, struct mmc *mmc) { +int __board_mmc_getcd(struct mmc *mmc) { return -1; } -int board_mmc_getcd(u8 *cd, struct mmc *mmc)__attribute__((weak, +int board_mmc_getcd(struct mmc *mmc)__attribute__((weak, alias("__board_mmc_getcd"))); int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) @@ -674,6 +674,18 @@ int mmc_switch_part(int dev_num, unsigned int part_num) | (part_num & PART_ACCESS_MASK)); } +int mmc_getcd(struct mmc *mmc) +{ + int cd; + + cd = board_mmc_getcd(mmc); + + if ((cd < 0) && mmc->getcd) + cd = mmc->getcd(mmc); + + return cd; +} + int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) { struct mmc_cmd cmd; @@ -785,6 +797,16 @@ retry_scr: if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) return 0; + /* + * If the host doesn't support SD_HIGHSPEED, do not switch card to + * HIGHSPEED mode even if the card support SD_HIGHSPPED. + * This can avoid furthur problem when the card runs in different + * mode between the host. + */ + if (!((mmc->host_caps & MMC_MODE_HS_52MHz) && + (mmc->host_caps & MMC_MODE_HS))) + return 0; + err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); if (err) @@ -1192,6 +1214,12 @@ int mmc_init(struct mmc *mmc) { int err; + if (mmc_getcd(mmc) == 0) { + mmc->has_init = 0; + printf("MMC: no card present\n"); + return NO_CARD_ERR; + } + if (mmc->has_init) return 0; diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index 49fb9e02a9..de43a85355 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -272,6 +272,7 @@ struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode) mmc->send_cmd = mmc_spi_request; mmc->set_ios = mmc_spi_set_ios; mmc->init = mmc_spi_init_p; + mmc->getcd = NULL; mmc->host_caps = MMC_MODE_SPI; mmc->voltages = MMC_SPI_VOLTAGE; diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 1501974e2f..2fe34b6993 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -44,8 +44,7 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) host->quirks = quirks; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS memset(&mv_ops, 0, sizeof(struct sdhci_ops)); - if (mv_sdhci_writeb != NULL) - mv_ops.write_b = mv_sdhci_writeb; + mv_ops.write_b = mv_sdhci_writeb; host->ops = &mv_ops; #endif if (quirks & SDHCI_QUIRK_REG32_RW) diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index ab1fc82fbb..8afb22159a 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -500,6 +500,7 @@ static int mxcmci_initialize(bd_t *bis) mmc->send_cmd = mxcmci_request; mmc->set_ios = mxcmci_set_ios; mmc->init = mxcmci_init; + mmc->getcd = NULL; mmc->host_caps = MMC_MODE_4BIT; host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE; diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 2a9949eb94..5f87a1efd6 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -329,6 +329,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)) mmc->send_cmd = mxsmmc_send_cmd; mmc->set_ios = mxsmmc_set_ios; mmc->init = mxsmmc_init; + mmc->getcd = NULL; mmc->priv = priv; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index c38b9e6038..ef64e37411 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -472,6 +472,7 @@ int omap_mmc_init(int dev_index) mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_init_setup; + mmc->getcd = NULL; switch (dev_index) { case 0: diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c index 4a7c67a6bd..2c5bf17bb3 100644 --- a/drivers/mmc/pxa_mmc_gen.c +++ b/drivers/mmc/pxa_mmc_gen.c @@ -411,6 +411,7 @@ int pxa_mmc_register(int card_index) mmc->send_cmd = pxa_mmc_request; mmc->set_ios = pxa_mmc_set_ios; mmc->init = pxa_mmc_init; + mmc->getcd = NULL; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->f_max = PXAMMC_MAX_SPEED; diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c index 7786ecf2be..4ae3aaf773 100644 --- a/drivers/mmc/s5p_mmc.c +++ b/drivers/mmc/s5p_mmc.c @@ -463,6 +463,7 @@ static int s5p_mmc_initialize(int dev_index, int bus_width) mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_core_init; + mmc->getcd = NULL; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; if (bus_width == 8) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index fce0ef0911..fc904b5308 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -390,6 +390,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) mmc->send_cmd = sdhci_send_command; mmc->set_ios = sdhci_set_ios; mmc->init = sdhci_init; + mmc->getcd = NULL; caps = sdhci_readl(host, SDHCI_CAPABILITIES); #ifdef CONFIG_MMC_SDMA diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 567e2cb61d..2835e242f8 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -598,6 +598,7 @@ int mmcif_mmc_init(void) mmc->send_cmd = sh_mmcif_request; mmc->set_ios = sh_mmcif_set_ios; mmc->init = sh_mmcif_init; + mmc->getcd = NULL; host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR; host->clk = CONFIG_SH_MMCIF_CLK; mmc->priv = host; diff --git a/drivers/mmc/tegra2_mmc.c b/drivers/mmc/tegra2_mmc.c index 035a8687df..5b4c9f69a1 100644 --- a/drivers/mmc/tegra2_mmc.c +++ b/drivers/mmc/tegra2_mmc.c @@ -474,6 +474,18 @@ static int mmc_core_init(struct mmc *mmc) return 0; } +int tegra2_mmc_getcd(struct mmc *mmc) +{ + struct mmc_host *host = (struct mmc_host *)mmc->priv; + + debug("tegra2_mmc_getcd called\n"); + + if (host->cd_gpio >= 0) + return !gpio_get_value(host->cd_gpio); + + return 1; +} + int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) { struct mmc_host *host; @@ -512,6 +524,7 @@ int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_core_init; + mmc->getcd = tegra2_mmc_getcd; mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; if (bus_width == 8) @@ -535,22 +548,3 @@ int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) return 0; } - -/* this is a weak define that we are overriding */ -int board_mmc_getcd(u8 *cd, struct mmc *mmc) -{ - struct mmc_host *host = (struct mmc_host *)mmc->priv; - - debug("board_mmc_getcd called\n"); - - *cd = 1; /* Assume card is inserted, or eMMC */ - - if (IS_SD(mmc)) { - if (host->cd_gpio >= 0) { - if (gpio_get_value(host->cd_gpio)) - *cd = 0; - } - } - - return 0; -} diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h index b2f6c5baad..67c00db9de 100644 --- a/drivers/mmc/tegra2_mmc.h +++ b/drivers/mmc/tegra2_mmc.h @@ -127,7 +127,5 @@ struct mmc_host { int cd_gpio; /* Change Detect GPIO */ }; -int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio); - #endif /* __ASSEMBLY__ */ #endif /* __TEGRA2_MMC_H_ */ diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 57112af66f..90f83924e2 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -25,6 +25,10 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi_flash.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o +endif + COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c new file mode 100644 index 0000000000..1aa30aca7e --- /dev/null +++ b/drivers/mtd/spi/spi_spl_load.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 OMICRON electronics GmbH + * + * based on drivers/mtd/nand/nand_spl_load.c + * + * Copyright (C) 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spi_flash.h> + +/* + * The main entry for SPI booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from SPI into SDRAM and starts it from there. + */ +void spi_boot(void) +{ + struct spi_flash *flash; + void (*uboot)(void) __noreturn; + + /* + * Load U-Boot image from SPI flash into RAM + */ + + flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS, + CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3); + if (!flash) { + puts("failed.\n"); + hang(); + } + + spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, + CONFIG_SYS_SPI_U_BOOT_SIZE, + (void *) CONFIG_SYS_TEXT_BASE); + + /* + * Jump to U-Boot image + */ + uboot = (void *) CONFIG_SYS_TEXT_BASE; + (*uboot)(); +} diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d3df82ee39..f4f7ea36f2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o +COBJS-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o COBJS-$(CONFIG_CS8900) += cs8900.o COBJS-$(CONFIG_TULIP) += dc2114x.o COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c new file mode 100644 index 0000000000..01b2eeeaee --- /dev/null +++ b/drivers/net/calxedaxgmac.c @@ -0,0 +1,553 @@ +/* + * Copyright 2010-2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ +#include <common.h> +#include <malloc.h> +#include <linux/err.h> +#include <asm/io.h> + +#define TX_NUM_DESC 1 +#define RX_NUM_DESC 32 + +#define MAC_TIMEOUT (5*CONFIG_SYS_HZ) + +#define ETH_BUF_SZ 2048 +#define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC) +#define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC) + +#define RXSTART 0x00000002 +#define TXSTART 0x00002000 + +#define RXENABLE 0x00000004 +#define TXENABLE 0x00000008 + +#define XGMAC_CONTROL_SPD 0x40000000 +#define XGMAC_CONTROL_SPD_MASK 0x60000000 +#define XGMAC_CONTROL_SARC 0x10000000 +#define XGMAC_CONTROL_SARK_MASK 0x18000000 +#define XGMAC_CONTROL_CAR 0x04000000 +#define XGMAC_CONTROL_CAR_MASK 0x06000000 +#define XGMAC_CONTROL_CAR_SHIFT 25 +#define XGMAC_CONTROL_DP 0x01000000 +#define XGMAC_CONTROL_WD 0x00800000 +#define XGMAC_CONTROL_JD 0x00400000 +#define XGMAC_CONTROL_JE 0x00100000 +#define XGMAC_CONTROL_LM 0x00001000 +#define XGMAC_CONTROL_IPC 0x00000400 +#define XGMAC_CONTROL_ACS 0x00000080 +#define XGMAC_CONTROL_DDIC 0x00000010 +#define XGMAC_CONTROL_TE 0x00000008 +#define XGMAC_CONTROL_RE 0x00000004 + +#define XGMAC_DMA_BUSMODE_RESET 0x00000001 +#define XGMAC_DMA_BUSMODE_DSL 0x00000004 +#define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c +#define XGMAC_DMA_BUSMODE_DSL_SHIFT 2 +#define XGMAC_DMA_BUSMODE_ATDS 0x00000080 +#define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00 +#define XGMAC_DMA_BUSMODE_PBL_SHIFT 8 +#define XGMAC_DMA_BUSMODE_FB 0x00010000 +#define XGMAC_DMA_BUSMODE_USP 0x00800000 +#define XGMAC_DMA_BUSMODE_8PBL 0x01000000 +#define XGMAC_DMA_BUSMODE_AAL 0x02000000 + +#define XGMAC_DMA_AXIMODE_ENLPI 0x80000000 +#define XGMAC_DMA_AXIMODE_MGK 0x40000000 +#define XGMAC_DMA_AXIMODE_WROSR 0x00100000 +#define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000 +#define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20 +#define XGMAC_DMA_AXIMODE_RDOSR 0x00010000 +#define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000 +#define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16 +#define XGMAC_DMA_AXIMODE_AAL 0x00001000 +#define XGMAC_DMA_AXIMODE_BLEN256 0x00000080 +#define XGMAC_DMA_AXIMODE_BLEN128 0x00000040 +#define XGMAC_DMA_AXIMODE_BLEN64 0x00000020 +#define XGMAC_DMA_AXIMODE_BLEN32 0x00000010 +#define XGMAC_DMA_AXIMODE_BLEN16 0x00000008 +#define XGMAC_DMA_AXIMODE_BLEN8 0x00000004 +#define XGMAC_DMA_AXIMODE_BLEN4 0x00000002 +#define XGMAC_DMA_AXIMODE_UNDEF 0x00000001 + +#define XGMAC_CORE_OMR_RTC_SHIFT 3 +#define XGMAC_CORE_OMR_RTC_MASK 0x00000018 +#define XGMAC_CORE_OMR_RTC 0x00000010 +#define XGMAC_CORE_OMR_RSF 0x00000020 +#define XGMAC_CORE_OMR_DT 0x00000040 +#define XGMAC_CORE_OMR_FEF 0x00000080 +#define XGMAC_CORE_OMR_EFC 0x00000100 +#define XGMAC_CORE_OMR_RFA_SHIFT 9 +#define XGMAC_CORE_OMR_RFA_MASK 0x00000E00 +#define XGMAC_CORE_OMR_RFD_SHIFT 12 +#define XGMAC_CORE_OMR_RFD_MASK 0x00007000 +#define XGMAC_CORE_OMR_TTC_SHIFT 16 +#define XGMAC_CORE_OMR_TTC_MASK 0x00030000 +#define XGMAC_CORE_OMR_TTC 0x00020000 +#define XGMAC_CORE_OMR_FTF 0x00100000 +#define XGMAC_CORE_OMR_TSF 0x00200000 + +#define FIFO_MINUS_1K 0x0 +#define FIFO_MINUS_2K 0x1 +#define FIFO_MINUS_3K 0x2 +#define FIFO_MINUS_4K 0x3 +#define FIFO_MINUS_6K 0x4 +#define FIFO_MINUS_8K 0x5 +#define FIFO_MINUS_12K 0x6 +#define FIFO_MINUS_16K 0x7 + +#define XGMAC_CORE_FLOW_PT_SHIFT 16 +#define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000 +#define XGMAC_CORE_FLOW_PT 0x00010000 +#define XGMAC_CORE_FLOW_DZQP 0x00000080 +#define XGMAC_CORE_FLOW_PLT_SHIFT 4 +#define XGMAC_CORE_FLOW_PLT_MASK 0x00000030 +#define XGMAC_CORE_FLOW_PLT 0x00000010 +#define XGMAC_CORE_FLOW_UP 0x00000008 +#define XGMAC_CORE_FLOW_RFE 0x00000004 +#define XGMAC_CORE_FLOW_TFE 0x00000002 +#define XGMAC_CORE_FLOW_FCB 0x00000001 + +/* XGMAC Descriptor Defines */ +#define MAX_DESC_BUF_SZ (0x2000 - 8) + +#define RXDESC_EXT_STATUS 0x00000001 +#define RXDESC_CRC_ERR 0x00000002 +#define RXDESC_RX_ERR 0x00000008 +#define RXDESC_RX_WDOG 0x00000010 +#define RXDESC_FRAME_TYPE 0x00000020 +#define RXDESC_GIANT_FRAME 0x00000080 +#define RXDESC_LAST_SEG 0x00000100 +#define RXDESC_FIRST_SEG 0x00000200 +#define RXDESC_VLAN_FRAME 0x00000400 +#define RXDESC_OVERFLOW_ERR 0x00000800 +#define RXDESC_LENGTH_ERR 0x00001000 +#define RXDESC_SA_FILTER_FAIL 0x00002000 +#define RXDESC_DESCRIPTOR_ERR 0x00004000 +#define RXDESC_ERROR_SUMMARY 0x00008000 +#define RXDESC_FRAME_LEN_OFFSET 16 +#define RXDESC_FRAME_LEN_MASK 0x3fff0000 +#define RXDESC_DA_FILTER_FAIL 0x40000000 + +#define RXDESC1_END_RING 0x00008000 + +#define RXDESC_IP_PAYLOAD_MASK 0x00000003 +#define RXDESC_IP_PAYLOAD_UDP 0x00000001 +#define RXDESC_IP_PAYLOAD_TCP 0x00000002 +#define RXDESC_IP_PAYLOAD_ICMP 0x00000003 +#define RXDESC_IP_HEADER_ERR 0x00000008 +#define RXDESC_IP_PAYLOAD_ERR 0x00000010 +#define RXDESC_IPV4_PACKET 0x00000040 +#define RXDESC_IPV6_PACKET 0x00000080 +#define TXDESC_UNDERFLOW_ERR 0x00000001 +#define TXDESC_JABBER_TIMEOUT 0x00000002 +#define TXDESC_LOCAL_FAULT 0x00000004 +#define TXDESC_REMOTE_FAULT 0x00000008 +#define TXDESC_VLAN_FRAME 0x00000010 +#define TXDESC_FRAME_FLUSHED 0x00000020 +#define TXDESC_IP_HEADER_ERR 0x00000040 +#define TXDESC_PAYLOAD_CSUM_ERR 0x00000080 +#define TXDESC_ERROR_SUMMARY 0x00008000 +#define TXDESC_SA_CTRL_INSERT 0x00040000 +#define TXDESC_SA_CTRL_REPLACE 0x00080000 +#define TXDESC_2ND_ADDR_CHAINED 0x00100000 +#define TXDESC_END_RING 0x00200000 +#define TXDESC_CSUM_IP 0x00400000 +#define TXDESC_CSUM_IP_PAYLD 0x00800000 +#define TXDESC_CSUM_ALL 0x00C00000 +#define TXDESC_CRC_EN_REPLACE 0x01000000 +#define TXDESC_CRC_EN_APPEND 0x02000000 +#define TXDESC_DISABLE_PAD 0x04000000 +#define TXDESC_FIRST_SEG 0x10000000 +#define TXDESC_LAST_SEG 0x20000000 +#define TXDESC_INTERRUPT 0x40000000 + +#define DESC_OWN 0x80000000 +#define DESC_BUFFER1_SZ_MASK 0x00001fff +#define DESC_BUFFER2_SZ_MASK 0x1fff0000 +#define DESC_BUFFER2_SZ_OFFSET 16 + +struct xgmac_regs { + u32 config; + u32 framefilter; + u32 resv_1[4]; + u32 flow_control; + u32 vlantag; + u32 version; + u32 vlaninclude; + u32 resv_2[2]; + u32 pacestretch; + u32 vlanhash; + u32 resv_3; + u32 intreg; + struct { + u32 hi; /* 0x40 */ + u32 lo; /* 0x44 */ + } macaddr[16]; + u32 resv_4[0xd0]; + u32 core_opmode; /* 0x400 */ + u32 resv_5[0x2bf]; + u32 busmode; /* 0xf00 */ + u32 txpoll; + u32 rxpoll; + u32 rxdesclist; + u32 txdesclist; + u32 dma_status; + u32 dma_opmode; + u32 intenable; + u32 resv_6[2]; + u32 axi_mode; /* 0xf28 */ +}; + +struct xgmac_dma_desc { + __le32 flags; + __le32 buf_size; + __le32 buf1_addr; /* Buffer 1 Address Pointer */ + __le32 buf2_addr; /* Buffer 2 Address Pointer */ + __le32 ext_status; + __le32 res[3]; +}; + +/* XGMAC Descriptor Access Helpers */ +static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz) +{ + if (buf_sz > MAX_DESC_BUF_SZ) + p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ | + (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET); + else + p->buf_size = cpu_to_le32(buf_sz); +} + +static inline int desc_get_buf_len(struct xgmac_dma_desc *p) +{ + u32 len = le32_to_cpu(p->buf_size); + return (len & DESC_BUFFER1_SZ_MASK) + + ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET); +} + +static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size, + int buf_sz) +{ + struct xgmac_dma_desc *end = p + ring_size - 1; + + memset(p, 0, sizeof(*p) * ring_size); + + for (; p <= end; p++) + desc_set_buf_len(p, buf_sz); + + end->buf_size |= cpu_to_le32(RXDESC1_END_RING); +} + +static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size) +{ + memset(p, 0, sizeof(*p) * ring_size); + p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING); +} + +static inline int desc_get_owner(struct xgmac_dma_desc *p) +{ + return le32_to_cpu(p->flags) & DESC_OWN; +} + +static inline void desc_set_rx_owner(struct xgmac_dma_desc *p) +{ + /* Clear all fields and set the owner */ + p->flags = cpu_to_le32(DESC_OWN); +} + +static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags) +{ + u32 tmpflags = le32_to_cpu(p->flags); + tmpflags &= TXDESC_END_RING; + tmpflags |= flags | DESC_OWN; + p->flags = cpu_to_le32(tmpflags); +} + +static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p) +{ + return (void *)le32_to_cpu(p->buf1_addr); +} + +static inline void desc_set_buf_addr(struct xgmac_dma_desc *p, + void *paddr, int len) +{ + p->buf1_addr = cpu_to_le32(paddr); + if (len > MAX_DESC_BUF_SZ) + p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ); +} + +static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p, + void *paddr, int len) +{ + desc_set_buf_len(p, len); + desc_set_buf_addr(p, paddr, len); +} + +static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p) +{ + u32 data = le32_to_cpu(p->flags); + u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET; + if (data & RXDESC_FRAME_TYPE) + len -= 4; + + return len; +} + +struct calxeda_eth_dev { + struct xgmac_dma_desc rx_chain[RX_NUM_DESC]; + struct xgmac_dma_desc tx_chain[TX_NUM_DESC]; + char rxbuffer[RX_BUF_SZ]; + + u32 tx_currdesc; + u32 rx_currdesc; + + struct eth_device *dev; +} __aligned(32); + +/* + * Initialize a descriptor ring. Calxeda XGMAC is configured to use + * advanced descriptors. + */ + +static void init_rx_desc(struct calxeda_eth_dev *priv) +{ + struct xgmac_dma_desc *rxdesc = priv->rx_chain; + struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; + void *rxbuffer = priv->rxbuffer; + int i; + + desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ); + writel((ulong)rxdesc, ®s->rxdesclist); + + for (i = 0; i < RX_NUM_DESC; i++) { + desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ), + ETH_BUF_SZ); + desc_set_rx_owner(rxdesc + i); + } +} + +static void init_tx_desc(struct calxeda_eth_dev *priv) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; + + desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC); + writel((ulong)priv->tx_chain, ®s->txdesclist); +} + +static int xgmac_reset(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + int timeout = MAC_TIMEOUT; + u32 value; + + value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK; + + writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode); + while ((timeout-- >= 0) && + (readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET)) + udelay(1); + + writel(value, ®s->config); + + return timeout; +} + +static void xgmac_hwmacaddr(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + u32 macaddr[2]; + + memcpy(macaddr, dev->enetaddr, 6); + writel(macaddr[1], ®s->macaddr[0].hi); + writel(macaddr[0], ®s->macaddr[0].lo); +} + +static int xgmac_init(struct eth_device *dev, bd_t * bis) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + int value; + + if (xgmac_reset(dev) < 0) + return -1; + + /* set the hardware MAC address */ + xgmac_hwmacaddr(dev); + + /* set the AXI bus modes */ + value = XGMAC_DMA_BUSMODE_ATDS | + (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) | + XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL; + writel(value, ®s->busmode); + + value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 | + XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4; + writel(value, ®s->axi_mode); + + /* set flow control parameters and store and forward mode */ + value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) | + (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) | + XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF; + writel(value, ®s->core_opmode); + + /* enable pause frames */ + value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) | + (1 << XGMAC_CORE_FLOW_PLT_SHIFT) | + XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE; + writel(value, ®s->flow_control); + + /* Initialize the descriptor chains */ + init_rx_desc(priv); + init_tx_desc(priv); + + /* must set to 0, or when started up will cause issues */ + priv->tx_currdesc = 0; + priv->rx_currdesc = 0; + + /* set default core values */ + value = readl(®s->config); + value &= XGMAC_CONTROL_SPD_MASK; + value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS | + XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR; + + /* Everything is ready enable both mac and DMA */ + value |= RXENABLE | TXENABLE; + writel(value, ®s->config); + + value = readl(®s->dma_opmode); + value |= RXSTART | TXSTART; + writel(value, ®s->dma_opmode); + + return 0; +} + +static int xgmac_tx(struct eth_device *dev, volatile void *packet, int length) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + u32 currdesc = priv->tx_currdesc; + struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc]; + int timeout; + + desc_set_buf_addr_and_size(txdesc, (void *)packet, length); + desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG | + TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND); + + /* write poll demand */ + writel(1, ®s->txpoll); + + timeout = 1000000; + while (desc_get_owner(txdesc)) { + if (timeout-- < 0) { + printf("xgmac: TX timeout\n"); + return -ETIMEDOUT; + } + udelay(1); + } + + priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1); + return 0; +} + +static int xgmac_rx(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + u32 currdesc = priv->rx_currdesc; + struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc]; + int length = 0; + + /* check if the host has the desc */ + if (desc_get_owner(rxdesc)) + return -1; /* something bad happened */ + + length = desc_get_rx_frame_len(rxdesc); + + NetReceive((volatile unsigned char *)desc_get_buf_addr(rxdesc), length); + + /* set descriptor back to owned by XGMAC */ + desc_set_rx_owner(rxdesc); + writel(1, ®s->rxpoll); + + priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1); + + return length; +} + +static void xgmac_halt(struct eth_device *dev) +{ + struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct calxeda_eth_dev *priv = dev->priv; + int value; + + /* Disable TX/RX */ + value = readl(®s->config); + value &= ~(RXENABLE | TXENABLE); + writel(value, ®s->config); + + /* Disable DMA */ + value = readl(®s->dma_opmode); + value &= ~(RXSTART | TXSTART); + writel(value, ®s->dma_opmode); + + /* must set to 0, or when started up will cause issues */ + priv->tx_currdesc = 0; + priv->rx_currdesc = 0; +} + +int calxedaxgmac_initialize(u32 id, ulong base_addr) +{ + struct eth_device *dev; + struct calxeda_eth_dev *priv; + struct xgmac_regs *regs; + u32 macaddr[2]; + + regs = (struct xgmac_regs *)base_addr; + + /* check hardware version */ + if (readl(®s->version) != 0x1012) + return -1; + + dev = malloc(sizeof(*dev)); + if (!dev) + return 0; + memset(dev, 0, sizeof(*dev)); + + /* Structure must be aligned, because it contains the descriptors */ + priv = memalign(32, sizeof(*priv)); + if (!priv) { + free(dev); + return 0; + } + + dev->iobase = (int)base_addr; + dev->priv = priv; + priv->dev = dev; + sprintf(dev->name, "xgmac%d", id); + + /* The MAC address is already configured, so read it from registers. */ + macaddr[1] = readl(®s->macaddr[0].hi); + macaddr[0] = readl(®s->macaddr[0].lo); + memcpy(dev->enetaddr, macaddr, 6); + + dev->init = xgmac_init; + dev->send = xgmac_tx; + dev->recv = xgmac_rx; + dev->halt = xgmac_halt; + + eth_register(dev); + + return 1; +} diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index b05a4c0c9a..ed733535d5 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -345,9 +345,10 @@ static void fec_rbd_clean(int last, struct fec_bd *pRbd) writew(0, &pRbd->data_length); } -static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) +static int fec_get_hwaddr(struct eth_device *dev, int dev_id, + unsigned char *mac) { - imx_get_mac_from_fuse(mac); + imx_get_mac_from_fuse(dev_id, mac); return !is_valid_ether_addr(mac); } @@ -384,6 +385,14 @@ static int fec_open(struct eth_device *edev) writel(1 << 2, &fec->eth->x_cntrl); fec->rbd_index = 0; +#if defined(CONFIG_MX6Q) + /* Enable ENET HW endian SWAP */ + writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, + &fec->eth->ecntrl); + /* Enable ENET store and forward mode */ + writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, + &fec->eth->x_wmrk); +#endif /* * Enable FEC-Lite controller */ @@ -485,6 +494,8 @@ static int fec_init(struct eth_device *dev, bd_t* bd) rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; if (fec->xcv_type == SEVENWIRE) rcntrl |= FEC_RCNTRL_FCE; + else if (fec->xcv_type == RGMII) + rcntrl |= FEC_RCNTRL_RGMII; else if (fec->xcv_type == RMII) rcntrl |= FEC_RCNTRL_RMII; else /* MII mode */ @@ -812,8 +823,8 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) eth_register(edev); - if (fec_get_hwaddr(edev, ethaddr) == 0) { - debug("got MAC address from fuse: %pM\n", ethaddr); + if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { + debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); memcpy(edev->enetaddr, ethaddr, 6); } diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 8b26645173..9825eab291 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -32,7 +32,7 @@ #ifndef __FEC_MXC_H #define __FEC_MXC_H -void imx_get_mac_from_fuse(unsigned char *mac); +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /** * Layout description of the FEC @@ -196,6 +196,7 @@ struct ethernet_regs { #define FEC_RCNTRL_PROM 0x00000008 #define FEC_RCNTRL_BC_REJ 0x00000010 #define FEC_RCNTRL_FCE 0x00000020 +#define FEC_RCNTRL_RGMII 0x00000040 #define FEC_RCNTRL_RMII 0x00000100 #define FEC_TCNTRL_GTS 0x00000001 @@ -206,6 +207,9 @@ struct ethernet_regs { #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */ #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */ +#define FEC_ECNTRL_DBSWAP 0x00000100 + +#define FEC_X_WMRK_STRFWD 0x00000100 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) /* defines for MIIGSK */ @@ -261,7 +265,8 @@ enum xceiver_type { SEVENWIRE, /* 7-wire */ MII10, /* MII 10Mbps */ MII100, /* MII 100Mbps */ - RMII /* RMII */ + RMII, /* RMII */ + RGMII, /* RGMII */ }; /** diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 6f389f0934..c967d87834 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -43,6 +43,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o +COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c new file mode 100644 index 0000000000..56cb22963d --- /dev/null +++ b/drivers/spi/tegra2_spi.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2010-2011 NVIDIA Corporation + * With help from the mpc8xxx SPI driver + * With more help from omap3_spi SPI driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <ns16550.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/uart-spi-switch.h> +#include <asm/arch/tegra2_spi.h> + +struct tegra_spi_slave { + struct spi_slave slave; + struct spi_tegra *regs; + unsigned int freq; + unsigned int mode; +}; + +static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) +{ + return container_of(slave, struct tegra_spi_slave, slave); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Tegra2 SPI-Flash - only 1 device ('bus/cs') */ + if (bus != 0 || cs != 0) + return 0; + else + return 1; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct tegra_spi_slave *spi; + + if (!spi_cs_is_valid(bus, cs)) { + printf("SPI error: unsupported bus %d / chip select %d\n", + bus, cs); + return NULL; + } + + if (max_hz > TEGRA2_SPI_MAX_FREQ) { + printf("SPI error: unsupported frequency %d Hz. Max frequency" + " is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ); + return NULL; + } + + spi = malloc(sizeof(struct tegra_spi_slave)); + if (!spi) { + printf("SPI error: malloc of SPI structure failed\n"); + return NULL; + } + spi->slave.bus = bus; + spi->slave.cs = cs; + spi->freq = max_hz; + spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE; + spi->mode = mode; + + return &spi->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + free(spi); +} + +void spi_init(void) +{ + /* do nothing */ +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_tegra *regs = spi->regs; + u32 reg; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq); + + /* Clear stale status here */ + reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ + SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; + writel(reg, ®s->status); + debug("spi_init: STATUS = %08x\n", readl(®s->status)); + + /* + * Use sw-controlled CS, so we can clock in data after ReadID, etc. + */ + reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; + if (spi->mode & 2) + reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; + clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | + SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); + debug("spi_init: COMMAND = %08x\n", readl(®s->command)); + + /* + * SPI pins on Tegra2 are muxed - change pinmux later due to UART + * issue. + */ + pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); + pinmux_tristate_disable(PINGRP_LSPI); + +#ifndef CONFIG_SPI_UART_SWITCH + /* + * NOTE: + * Only set PinMux bits 3:2 to SPI here on boards that don't have the + * SPI UART switch or subsequent UART data won't go out! See + * spi_uart_switch(). + */ + /* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */ +#endif + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* + * We can't release UART_DISABLE and set pinmux to UART4 here since + * some code (e,g, spi_flash_probe) uses printf() while the SPI + * bus is held. That is arguably bad, but it has the advantage of + * already being in the source tree. + */ +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + pinmux_select_spi(); + + /* CS is negated on Tegra, so drive a 1 to get a 0 */ + setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + /* CS is negated on Tegra, so drive a 0 to get a 1 */ + clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_tegra *regs = spi->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes; + int ret; + + debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + reg = readl(®s->status); + writel(reg, ®s->status); /* Clear all SPI events via R/W */ + debug("spi_xfer entry: STATUS = %08x\n", reg); + + reg = readl(®s->command); + reg |= SPI_CMD_TXEN | SPI_CMD_RXEN; + writel(reg, ®s->command); + debug("spi_xfer: COMMAND = %08x\n", readl(®s->command)); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + int is_read = 0; + int tm, i; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + for (i = 0; i < bytes; ++i) + tmpdout = (tmpdout << 8) | dout[i]; + } + + num_bytes -= bytes; + if (dout) + dout += bytes; + + clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK, + bytes * 8 - 1); + writel(tmpdout, ®s->tx_fifo); + setbits_le32(®s->command, SPI_CMD_GO); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { + u32 status; + + status = readl(®s->status); + + /* We can exit when we've had both RX and TX activity */ + if (is_read && (status & SPI_STAT_TXF_EMPTY)) + break; + + if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) != + SPI_STAT_RDY) + tm++; + + else if (!(status & SPI_STAT_RXF_EMPTY)) { + tmpdin = readl(®s->rx_fifo); + is_read = 1; + + /* swap bytes read in */ + if (din != NULL) { + for (i = bytes - 1; i >= 0; --i) { + din[i] = tmpdin & 0xff; + tmpdin >>= 8; + } + din += bytes; + } + } + } + + if (tm >= SPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(®s->status), ®s->status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n", + tmpdin, readl(®s->status)); + + if (ret) { + printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret); + return -1; + } + + return 0; +} diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index a6add6abcd..15e9afcacd 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -181,6 +181,20 @@ gd_t *global_data; " lwi $r16, [$r16 + (%1)]\n" \ " jr $r16\n" \ : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16"); +#elif defined(CONFIG_OPENRISC) +/* + * r10 holds the pointer to the global_data, r13 is a call-clobbered + * register + */ +#define EXPORT_FUNC(x) \ + asm volatile ( \ +" .globl " #x "\n" \ +#x ":\n" \ +" l.lwz r13, %0(r10)\n" \ +" l.lwz r13, %1(r13)\n" \ +" l.jr r13\n" \ +" l.nop\n" \ + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13"); #else /*" addi $sp, $sp, -24\n" \ " br $r16\n" \*/ diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c index e119e1388f..f621741e40 100644 --- a/fs/ext2/ext2fs.c +++ b/fs/ext2/ext2fs.c @@ -265,7 +265,8 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { /* Indirect. */ else if (fileblock < (INDIRECT_BLOCKS + (blksz / 4))) { if (indir1_block == NULL) { - indir1_block = (uint32_t *) malloc (blksz); + indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, + blksz); if (indir1_block == NULL) { printf ("** ext2fs read block (indir 1) malloc failed. **\n"); return (-1); @@ -278,7 +279,8 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { indir1_block = NULL; indir1_size = 0; indir1_blkno = -1; - indir1_block = (uint32_t *) malloc (blksz); + indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, + blksz); if (indir1_block == NULL) { printf ("** ext2fs read block (indir 1) malloc failed. **\n"); return (-1); @@ -309,7 +311,8 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { + blksz / 4); if (indir1_block == NULL) { - indir1_block = (uint32_t *) malloc (blksz); + indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, + blksz); if (indir1_block == NULL) { printf ("** ext2fs read block (indir 2 1) malloc failed. **\n"); return (-1); @@ -322,7 +325,8 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { indir1_block = NULL; indir1_size = 0; indir1_blkno = -1; - indir1_block = (uint32_t *) malloc (blksz); + indir1_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, + blksz); if (indir1_block == NULL) { printf ("** ext2fs read block (indir 2 1) malloc failed. **\n"); return (-1); @@ -343,7 +347,8 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { } if (indir2_block == NULL) { - indir2_block = (uint32_t *) malloc (blksz); + indir2_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, + blksz); if (indir2_block == NULL) { printf ("** ext2fs read block (indir 2 2) malloc failed. **\n"); return (-1); @@ -356,7 +361,8 @@ static int ext2fs_read_block (ext2fs_node_t node, int fileblock) { indir2_block = NULL; indir2_size = 0; indir2_blkno = -1; - indir2_block = (uint32_t *) malloc (blksz); + indir2_block = (uint32_t *) memalign(ARCH_DMA_MINALIGN, + blksz); if (indir2_block == NULL) { printf ("** ext2fs read block (indir 2 2) malloc failed. **\n"); return (-1); diff --git a/fs/fat/fat.c b/fs/fat/fat.c index dbb8db92f0..1f95eb4caf 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -43,50 +43,30 @@ static void downcase (char *str) } } -static block_dev_desc_t *cur_dev = NULL; +static block_dev_desc_t *cur_dev; +static unsigned int cur_part_nr; +static disk_partition_t cur_part_info; -static unsigned long part_offset = 0; - -static int cur_part = 1; - -#define DOS_PART_TBL_OFFSET 0x1be -#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_BOOT_MAGIC_OFFSET 0x1fe #define DOS_FS_TYPE_OFFSET 0x36 #define DOS_FS32_TYPE_OFFSET 0x52 -static int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) +static int disk_read(__u32 block, __u32 nr_blocks, void *buf) { - if (cur_dev == NULL) + if (!cur_dev || !cur_dev->block_read) return -1; - startblock += part_offset; - - if (cur_dev->block_read) { - return cur_dev->block_read(cur_dev->dev, startblock, getsize, - (unsigned long *) bufptr); - } - return -1; + return cur_dev->block_read(cur_dev->dev, + cur_part_info.start + block, nr_blocks, buf); } int fat_register_device (block_dev_desc_t * dev_desc, int part_no) { unsigned char buffer[dev_desc->blksz]; - if (!dev_desc->block_read) - return -1; + /* First close any currently found FAT filesystem */ + cur_dev = NULL; - cur_dev = dev_desc; - /* check if we have a MBR (on floppies we have only a PBR) */ - if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *)buffer) != 1) { - printf("** Can't read from device %d **\n", - dev_desc->dev); - return -1; - } - if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || - buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) { - /* no signature found */ - return -1; - } #if (defined(CONFIG_CMD_IDE) || \ defined(CONFIG_CMD_MG_DISK) || \ defined(CONFIG_CMD_SATA) || \ @@ -94,45 +74,54 @@ int fat_register_device (block_dev_desc_t * dev_desc, int part_no) defined(CONFIG_CMD_USB) || \ defined(CONFIG_MMC) || \ defined(CONFIG_SYSTEMACE) ) - { - disk_partition_t info; - - /* First we assume there is a MBR */ - if (!get_partition_info(dev_desc, part_no, &info)) { - part_offset = info.start; - cur_part = part_no; - } else if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], - "FAT", 3) == 0) || - (strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET], - "FAT32", 5) == 0)) { - /* ok, we assume we are on a PBR only */ - cur_part = 1; - part_offset = 0; - } else { + + /* Read the partition table, if present */ + if (!get_partition_info(dev_desc, part_no, &cur_part_info)) { + cur_dev = dev_desc; + cur_part_nr = part_no; + } +#endif + + /* Otherwise it might be a superfloppy (whole-disk FAT filesystem) */ + if (!cur_dev) { + if (part_no != 1) { printf("** Partition %d not valid on device %d **\n", - part_no, dev_desc->dev); + part_no, dev_desc->dev); return -1; } + + cur_dev = dev_desc; + cur_part_nr = 1; + cur_part_info.start = 0; + cur_part_info.size = dev_desc->lba; + cur_part_info.blksz = dev_desc->blksz; + memset(cur_part_info.name, 0, sizeof(cur_part_info.name)); + memset(cur_part_info.type, 0, sizeof(cur_part_info.type)); } -#else - if ((strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3) == 0) || - (strncmp((char *)&buffer[DOS_FS32_TYPE_OFFSET], "FAT32", 5) == 0)) { - /* ok, we assume we are on a PBR only */ - cur_part = 1; - part_offset = 0; - } else { - /* FIXME we need to determine the start block of the - * partition where the DOS FS resides. This can be done - * by using the get_partition_info routine. For this - * purpose the libpart must be included. - */ - part_offset = 32; - cur_part = 1; + + /* Make sure it has a valid FAT header */ + if (disk_read(0, 1, buffer) != 1) { + cur_dev = NULL; + return -1; } -#endif - return 0; + + /* Check if it's actually a DOS volume */ + if (memcmp(buffer + DOS_BOOT_MAGIC_OFFSET, "\x55\xAA", 2)) { + cur_dev = NULL; + return -1; + } + + /* Check for FAT12/FAT16/FAT32 filesystem */ + if (!memcmp(buffer + DOS_FS_TYPE_OFFSET, "FAT", 3)) + return 0; + if (!memcmp(buffer + DOS_FS32_TYPE_OFFSET, "FAT32", 5)) + return 0; + + cur_dev = NULL; + return -1; } + /* * Get the first occurence of a directory delimiter ('/' or '\') in a string. * Return index into string if found, -1 otherwise. @@ -285,6 +274,8 @@ get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer, { __u32 idx = 0; __u32 startsect; + __u32 nr_sect; + int ret; if (clustnum > 0) { startsect = mydata->data_begin + @@ -295,16 +286,19 @@ get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer, debug("gc - clustnum: %d, startsect: %d\n", clustnum, startsect); - if (disk_read(startsect, size / mydata->sect_size, buffer) < 0) { - debug("Error reading data\n"); + nr_sect = size / mydata->sect_size; + ret = disk_read(startsect, nr_sect, buffer); + if (ret != nr_sect) { + debug("Error reading data (got %d)\n", ret); return -1; } if (size % mydata->sect_size) { __u8 tmpbuf[mydata->sect_size]; idx = size / mydata->sect_size; - if (disk_read(startsect + idx, 1, tmpbuf) < 0) { - debug("Error reading data\n"); + ret = disk_read(startsect + idx, 1, tmpbuf); + if (ret != 1) { + debug("Error reading data (got %d)\n", ret); return -1; } buffer += idx * mydata->sect_size; @@ -633,6 +627,7 @@ static dir_entry *get_dentfromdir (fsdata *mydata, int startsect, } #ifdef CONFIG_SUPPORT_VFAT if (dols && mkcksum(dentptr->name) == prevcksum) { + prevcksum = 0xffff; dentptr++; continue; } @@ -813,6 +808,11 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0]; mydata->clust_size = bs.cluster_size; + if (mydata->sect_size != cur_part_info.blksz) { + printf("Error: FAT sector size mismatch (fs=%hu, dev=%lu)\n", + mydata->sect_size, cur_part_info.blksz); + return -1; + } if (mydata->fatsize == 32) { mydata->data_begin = mydata->rootdir_sect - @@ -963,6 +963,7 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, #ifdef CONFIG_SUPPORT_VFAT else if (dols == LS_ROOT && mkcksum(dentptr->name) == prevcksum) { + prevcksum = 0xffff; dentptr++; continue; } @@ -1170,7 +1171,7 @@ int file_fat_detectfs (void) vol_label[11] = '\0'; volinfo.fs_type[5] = '\0'; - printf("Partition %d: Filesystem: %s \"%s\"\n", cur_part, + printf("Partition %d: Filesystem: %s \"%s\"\n", cur_part_nr, volinfo.fs_type, vol_label); return 0; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 3542b0bcbd..3bfc1c4b32 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -112,6 +112,7 @@ static void set_name(dir_entry *dirent, const char *filename) debug("ext : %s\n", dirent->ext); } +static __u8 num_of_fats; /* * Write fat buffer into block device */ @@ -134,6 +135,15 @@ static int flush_fat_buffer(fsdata *mydata) return -1; } + if (num_of_fats == 2) { + /* Update corresponding second FAT blocks */ + startblock += mydata->fatlength; + if (disk_write(startblock, getsize, bufptr) < 0) { + debug("error: writing second FAT blocks\n"); + return -1; + } + } + return 0; } @@ -950,6 +960,7 @@ static int do_fat_write(const char *filename, void *buffer, cursect = mydata->rootdir_sect = mydata->fat_sect + mydata->fatlength * bs.fats; + num_of_fats = bs.fats; mydata->sect_size = (bs.sector_size[1] << 8) + bs.sector_size[0]; mydata->clust_size = bs.cluster_size; diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index a1ebb28aec..c19e16cd21 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2011, NVIDIA Corp. All rights reserved. * See file CREDITS for list of people who contributed to this * project. * @@ -19,6 +20,9 @@ * MA 02111-1307 USA */ +#ifndef _ASM_GENERIC_GPIO_H_ +#define _ASM_GENERIC_GPIO_H_ + /* * Generic GPIO API for U-Boot * @@ -38,37 +42,56 @@ */ /** + * Request ownership of a GPIO. + * + * @param gpio GPIO number + * @param label Name given to the GPIO + * @return 0 if ok, -1 on error + */ +int gpio_request(unsigned gpio, const char *label); + +/** + * Stop using the GPIO. This function should not alter pin configuration. + * + * @param gpio GPIO number + * @return 0 if ok, -1 on error + */ +int gpio_free(unsigned gpio); + +/** * Make a GPIO an input. * - * @param gp GPIO number + * @param gpio GPIO number * @return 0 if ok, -1 on error */ -int gpio_direction_input(int gp); +int gpio_direction_input(unsigned gpio); /** * Make a GPIO an output, and set its value. * - * @param gp GPIO number + * @param gpio GPIO number * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_direction_output(int gp, int value); +int gpio_direction_output(unsigned gpio, int value); /** * Get a GPIO's value. This will work whether the GPIO is an input * or an output. * - * @param gp GPIO number + * @param gpio GPIO number * @return 0 if low, 1 if high, -1 on error */ -int gpio_get_value(int gp); +int gpio_get_value(unsigned gpio); /** - * Set an output GPIO's value. The GPIO must already be an output of + * Set an output GPIO's value. The GPIO must already be an output or * this function may have no effect. * - * @param gp GPIO number + * @param gpio GPIO number * @param value GPIO value (0 for low or 1 for high) * @return 0 if ok, -1 on error */ -int gpio_set_value(int gp, int value); +int gpio_set_value(unsigned gpio, int value); + +#endif /* _ASM_GENERIC_GPIO_H_ */ diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h index c7a835bbda..01597b965b 100644 --- a/include/configs/HWW1U1A.h +++ b/include/configs/HWW1U1A.h @@ -240,7 +240,29 @@ /* Turn off RTC square-wave output to save battery */ #define CONFIG_SYS_RTC_DS1337_NOOSC -/* PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554) */ +/* + * AT24C128N EEPROM at I2C0-0x53. + * + * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages + * of 64 bytes per page. The chip uses 2-byte addresses and has a max write + * cycle time of 20ms according to the datasheet. + * + * NOTE: Our environment is stored on regular direct-attached FLASH, this + * chip is only used as a write-protected backup for certain key settings + * such as the serial# and macaddr values. (EG: "env import") + */ +#define CONFIG_CMD_EEPROM +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21 + +/* + * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554). You + * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command + * will not be able to access the chip. + */ #define CONFIG_PCA953X #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO @@ -438,14 +460,20 @@ const char *hww1u1a_get_ps1(void); /* Extra environment parameters */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "preboot=setenv bootargs \"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ + "ethprime=e1000#0\0" \ + "ethrotate=no\0" \ + "setbootargs=setenv bootargs " \ + "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \ "perf_mode=performance\0" \ "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=ulpi\0" \ - "flkernel=0xe8020000\0" \ + "flkernel=0xe8000000\0" \ "flinitramfs=0xe8800000\0" \ "fldevicetree=0xeff20000\0" \ "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \ - "flboot=run preboot; run flbootm\0" + "flboot=run preboot; run flbootm\0" \ + "restore_eeprom=i2c dev 0 && " \ + "eeprom read $loadaddr 0x0000 0x2000 && " \ + "env import -c $loadaddr 0x2000\0" #endif /* __CONFIG_H */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 247cd2ff6e..9961fb55ca 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -239,11 +239,17 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_UPDATE_FLASH_SIZE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#define CONFIG_FLASH_SHOW_PROGRESS 45 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* * JFFS2 partitions @@ -291,6 +297,7 @@ #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ #define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_BOARD_EARLY_INIT_R /* Peripheral Bus Mapping */ #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 31503af5d2..863c9b9ec0 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -82,7 +82,8 @@ #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r */ #define CONFIG_SYS_IMMR 0xE0000000 @@ -266,7 +267,7 @@ #define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=e2800000.flash" #define MTDPARTS_DEFAULT \ - "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + "mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE @@ -363,6 +364,9 @@ #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CONFIG_MPC83XX_GPIO 1 +#define CONFIG_CMD_GPIO 1 + /* * Serial Port */ @@ -581,7 +585,8 @@ /* System IO Config */ #define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ -#define CONFIG_SYS_SICRL SICRL_USBDR_10 /* Enable Internal USB Phy */ + /* Enable Internal USB Phy and GPIO on LCD Connector */ +#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) #define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ diff --git a/include/configs/PATI.h b/include/configs/PATI.h index da2d602506..bf39d0040e 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -168,11 +168,16 @@ * */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#define CONFIG_FLASH_SHOW_PROGRESS 45 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 #define CONFIG_ENV_IS_IN_EEPROM #ifdef CONFIG_ENV_IS_IN_EEPROM diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 07415f4b57..242aa314a1 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -113,6 +113,8 @@ #define SPD_EEPROM_ADDRESS 0x50 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + /************************************************************** * Environment definitions **************************************************************/ @@ -230,11 +232,17 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_UPDATE_FLASH_SIZE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_EMPTY_INFO + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* * Init Memory Controller: diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 26a3c964ba..2cea1f4612 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -16,7 +16,7 @@ #ifndef __CONFIG_AM335X_EVM_H #define __CONFIG_AM335X_EVM_H -#define CONFIG_AM335X +#define CONFIG_AM33XX #define CONFIG_CMD_MEMORY /* for mtest */ #undef CONFIG_GZIP #undef CONFIG_ZLIB @@ -26,11 +26,9 @@ #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> -#define CONFIG_SETUP_PLL -#define CONFIG_AM335X_CONFIG_DDR #define CONFIG_ENV_SIZE 0x400 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 * 1024)) -#define CONFIG_SYS_PROMPT "AM335X# " +#define CONFIG_SYS_PROMPT "U-Boot# " #define CONFIG_SYS_NO_FLASH #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */ #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM @@ -48,14 +46,12 @@ /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) +#define V_SCLK (V_OSCK) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for - initial data */ #define CONFIG_CMD_ECHO /* max number of command args */ -#define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_MAXARGS 16 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 @@ -75,10 +71,17 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + (8 * 1024 * 1024)) -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ #define CONFIG_SYS_HZ 1000 /* 1ms clock */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ @@ -89,7 +92,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ GENERATED_GBL_DATA_SIZE) /* Platform/Board specific defs */ -#define CONFIG_SYS_CLK_FREQ 24000000 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ #define CONFIG_SYS_HZ 1000 @@ -100,7 +102,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM4 0x481A6000 /* UART3 on IA BOard */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ @@ -115,7 +116,44 @@ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_TEXT_BASE 0x402f0400 +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (46 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* Unsupported features */ #undef CONFIG_USE_IRQ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index a06a89d414..fe91c10409 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -1,6 +1,5 @@ /* - * (C) Copyright 2011 - * CompuLab, Ltd. + * (C) Copyright 2011 CompuLab, Ltd. * Mike Rapoport <mike@compulab.co.il> * Igor Grinberg <grinberg@compulab.co.il> * @@ -36,9 +35,9 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_CM_T3X 1 /* working with CM-T35 and CM-T3730 */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_SYS_TEXT_BASE 0x80008000 @@ -50,8 +49,8 @@ /* * Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ @@ -69,17 +68,18 @@ */ #define CONFIG_SYS_BOOTMAPSZ 0x4000 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* * Hardware drivers @@ -107,23 +107,21 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION /* USB */ -#define CONFIG_MUSB_UDC 1 -#define CONFIG_USB_OMAP3 1 -#define CONFIG_TWL4030_USB 1 +#define CONFIG_MUSB_UDC +#define CONFIG_USB_OMAP3 +#define CONFIG_TWL4030_USB /* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* commands to include */ #include <config_cmd_default.h> @@ -134,10 +132,10 @@ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ - "1920k(u-boot),128k(u-boot-env),"\ - "4m(kernel),-(fs)" +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ @@ -150,30 +148,32 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 +#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 #define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* * TWL4030 */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 +#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ @@ -247,7 +247,7 @@ #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING #define CONFIG_TIMESTAMP -#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_SYS_AUTOLOAD "no" #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " @@ -311,7 +311,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -336,8 +336,8 @@ GENERATED_GBL_DATA_SIZE) /* Status LED */ -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOARD_SPECIFIC_LED 1 +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED #define STATUS_LED_GREEN 0 #define STATUS_LED_BIT STATUS_LED_GREEN #define STATUS_LED_STATE STATUS_LED_ON @@ -347,7 +347,7 @@ /* GPIO banks */ #ifdef CONFIG_STATUS_LED -#define CONFIG_OMAP3_GPIO_6 1 /* GPIO186 is in GPIO bank 6 */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ #endif #endif /* __CONFIG_H */ diff --git a/include/configs/da850_am18xxevm.h b/include/configs/da850_am18xxevm.h deleted file mode 100644 index 9b7bf1e792..0000000000 --- a/include/configs/da850_am18xxevm.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_USE_SPIFLASH - - -/* - * SoC Configuration - */ -#define CONFIG_MACH_DAVINCI_DA850_EVM -#define CONFIG_ARM926EJS /* arm926ejs CPU core */ -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0xc1080000 -#define CONFIG_DA850_AM18X_EVM -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define CONFIG_STACKSIZE (256*1024) /* regular stack */ - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ -#define CONFIG_BAUDRATE 115200 /* Default baud rate */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED - -/* - * I2C Configuration - */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 25000 -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 - -/* - * Flash & Environment - */ -#ifdef CONFIG_USE_NAND -#undef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_CLE_MASK 0x10 -#define CONFIG_SYS_ALE_MASK 0x8 -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 -#endif - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_EMAC_MDIO_PHY_NUM 0 -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI -#endif - -#ifdef CONFIG_USE_NOR -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) -#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE -#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ -#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ - + 3) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ -#endif - -#ifdef CONFIG_USE_SPIFLASH -#undef CONFIG_ENV_IS_IN_FLASH -#undef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_OFFSET (256 << 10) -#define CONFIG_ENV_SECT_SIZE (64 << 10) -#define CONFIG_SYS_NO_FLASH -#endif - -/* - * U-Boot general configuration - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" -#define CONFIG_BOOTDELAY 3 -#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" - -/* - * U-Boot commands - */ -#include <config_cmd_default.h> -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MEMORY - -#ifndef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_PING -#endif - -#ifdef CONFIG_USE_NAND -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_NAND - -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define CONFIG_LZO -#define CONFIG_RBTREE -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#endif - -#ifdef CONFIG_USE_SPIFLASH -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_FLASH -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SAVEENV -#endif - -#if !defined(CONFIG_USE_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_SIZE (16 << 10) -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_ENV -#endif - -/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - /* Fix this */ GENERATED_GBL_DATA_SIZE) -#endif /* __CONFIG_H */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 2e2aa19a45..fcbbace1ca 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -44,9 +44,6 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_L2CACHE_OFF /* * Memory Info @@ -65,6 +62,75 @@ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ + DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ + DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ + DAVINCI_SYSCFG_SUSPSRC_UART2 | \ + DAVINCI_SYSCFG_SUSPSRC_EMAC | \ + DAVINCI_SYSCFG_SUSPSRC_I2C) + +/* + * PLL configuration + */ +#define CONFIG_SYS_DV_CLKMODE 0 +#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 +#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 +#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 +#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 + +#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 +#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 +#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 + +#define CONFIG_SYS_DA850_PLL0_PLLM 24 +#define CONFIG_SYS_DA850_PLL1_PLLM 21 + +/* + * DDR2 memory configuration + */ +#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ + DV_DDR_PHY_EXT_STRBEN | \ + (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ + (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ + (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ + (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ + (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ + (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ + (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) + +/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ +#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 + +#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ + (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ + (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ + (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ + (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ + (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ + (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ + (0 << DV_DDR_SDTMR1_WTR_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ + (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ + (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ + (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ + (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ + (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ + (0 << DV_DDR_SDTMR2_CKE_SHIFT)) + +#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 +#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 + /* * Serial Driver info */ @@ -76,6 +142,7 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2 #define CONFIG_SPI #define CONFIG_SPI_FLASH @@ -242,6 +309,23 @@ #undef CONFIG_CMD_ENV #endif +/* defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x8001ff00 +#define CONFIG_SPL_TEXT_BASE 0x80000000 +#define CONFIG_SPL_MAX_SIZE 32768 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 + /* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0xc0000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 42aab27fac..1626b0e625 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -109,9 +109,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR - /* library portions to compile in */ #define CONFIG_RBTREE #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 89e4911244..ce0ae9fe1f 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -58,4 +58,7 @@ #define CONFIG_EFI_PARTITION #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT + +/* Environment not stored */ +#define CONFIG_ENV_IS_NOWHERE #endif /* __CONFIG_H */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 9c85788353..5604733036 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -51,19 +51,27 @@ #define CONFIG_DOS_PARTITION +#define CONFIG_CALXEDA_XGMAC + +/* PXE support */ +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 +#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.highbank" + /* * Command line configuration. */ #include <config_cmd_default.h> -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS #define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADS #define CONFIG_CMD_SCSI #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_PXE +#define CONFIG_MENU #define CONFIG_BOOTDELAY 2 /* @@ -82,6 +90,12 @@ #define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdtaddr_r=0x600000\0" \ + "pxefile_addr_r=0x700000\0" \ + "kernel_addr_r=0x800000\0" \ + "ramdisk_addr_r=0x01000000\0" \ + /*----------------------------------------------------------------------- * Stack sizes * diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h index 56fd6de231..c2fcdffdae 100644 --- a/include/configs/igep0020.h +++ b/include/configs/igep0020.h @@ -78,9 +78,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR */ -#define CONFIG_OMAP3_NUMONYX_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h index 36346187f8..bf39ba56d7 100644 --- a/include/configs/igep0030.h +++ b/include/configs/igep0030.h @@ -78,9 +78,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR */ -#define CONFIG_OMAP3_NUMONYX_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index 902ae26e55..580b72f4e7 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -70,7 +70,8 @@ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN) + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -82,7 +83,7 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE 0x47860242 #define CONFIG_SYS_DDR_MODE2 0x8080c000 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ @@ -94,20 +95,20 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (2 << TIMING_CFG1_WRREC_SHIFT) | \ - (6 << TIMING_CFG1_REFREC_SHIFT) | \ - (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (2 << TIMING_CFG1_PRETOACT_SHIFT)) + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT)) #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ (5 << TIMING_CFG2_CPO_SHIFT)) @@ -122,7 +123,10 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 + #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 39c841f44c..b891b12fef 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -92,7 +92,14 @@ #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_SP_ADDR 0x00002000 + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000 +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* * We need to sacrifice first 4 bytes of RAM here to avoid triggering some * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot @@ -140,6 +147,7 @@ /* * NAND */ +#define CONFIG_ENV_SIZE (16 * 1024) #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_MXS #define CONFIG_APBH_DMA @@ -150,7 +158,6 @@ /* Environment is in NAND */ #define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_RANGE (512 * 1024) @@ -173,6 +180,8 @@ "512k(redundant-environment)," \ "4m(kernel)," \ "-(filesystem)" +#else +#define CONFIG_ENV_IS_NOWHERE #endif /* diff --git a/include/configs/medcom.h b/include/configs/medcom.h new file mode 100644 index 0000000000..2dc350762d --- /dev/null +++ b/include/configs/medcom.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra2-common.h" + +/* High-level configuration options */ +#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M" +#define V_PROMPT "Tegra2 (Medcom) # " +#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Medcom" +#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011 + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_ENV_IS_NOWHERE + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +#define CONFIG_FIT + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan;" \ + "ext2load mmc 0 0x17000000 /boot/uImage;" \ + "bootm" + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h new file mode 100644 index 0000000000..bea46e7267 --- /dev/null +++ b/include/configs/mx28evk.h @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * Based on m28evk.h: + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/regs-base.h> + +/* + * SoC configurations + */ +#define CONFIG_MX28 /* i.MX28 SoC */ +#define CONFIG_MXS_GPIO /* GPIO control */ +#define CONFIG_SYS_HZ 1000 /* Ticks per second */ + +#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_ARCH_MISC_INIT + +/* + * SPL + */ +#define CONFIG_SPL +#define CONFIG_SPL_NO_CPU_SUPPORT_CODE +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +/* + * U-Boot Commands + */ +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + +/* + * Memory configurations + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ +#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */ +#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ +#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ +#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +/* Point initial SP in SRAM so SPL can use it too. */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000 +#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * We need to sacrifice first 4 bytes of RAM here to avoid triggering some + * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot + * binary. In case there was more of this mess, 0x100 bytes are skipped. + */ +#define CONFIG_SYS_TEXT_BASE 0x40000100 + +#define CONFIG_ENV_OVERWRITE +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + /* Print buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Serial Driver + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * MMC Driver + */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_CMD_SAVEENV +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_MXS_MMC +#endif + +/* + * Ethernet on SOC (FEC) + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_NET_MULTI +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_MX28_FEC_MAC_IN_OCOTP +#endif + +/* + * Boot Linux + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTCOMMAND "run bootcmd_net" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* + * Extra Environments + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console_fsl=console=ttyAM0" \ + "console_mainline=console=ttyAMA0" \ + "netargs=setenv bootargs console=${console_mainline}" \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot}\0" \ + "bootcmd_net=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" \ + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index a7b363dbd4..124a7a63ae 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -56,6 +56,16 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -66,8 +76,6 @@ #include <config_cmd_default.h> #undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h new file mode 100644 index 0000000000..464f0ec650 --- /dev/null +++ b/include/configs/mx6qsabrelite.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6Q Sabre Lite board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX6Q +#define CONFIG_SYS_MX6_HCLK 24000000 +#define CONFIG_SYS_MX6_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#include <asm/arch/imx-regs.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x10800000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc3\0" \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "dhcp ${uimage}; bootm\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h new file mode 100644 index 0000000000..01360f6cbd --- /dev/null +++ b/include/configs/omap3_logic.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2011 Logic Product Development <www.logicpd.com> + * Peter Barada <peter.barada@logicpd.com> + * + * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo + * reference boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ + +#undef CONFIG_USE_IRQ /* no support for IRQs */ + +#define CONFIG_SYS_TEXT_BASE 0x80400000 + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */ + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SETECPR /* Evaluate expressions */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH + +/* + * I2C + */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_OMAP34XX_I2C + +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_I2C_MULTI_BUS + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 2 + +/* + * PREBOOT assumes the 4.3" display is attached. User can interrupt + * and modify display variable to suit their needs. + */ +#define CONFIG_PREBOOT \ + "echo ======================NOTICE============================;"\ + "echo \"The u-boot environment is not set.\";" \ + "echo \"If using a display a valid display varible for your panel\";" \ + "echo \"needs to be set.\";" \ + "echo \"Valid display options are:\";" \ + "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \ + "echo \" 3 == LQ036Q1DA01 TFT QVGA (3.6) Sharp w/ASIC\";" \ + "echo \" 5 == LQ064D343 TFT VGA (6.4) Sharp\";" \ + "echo \" 7 == LQ10D368 TFT VGA (10.4) Sharp\";" \ + "echo \" 15 == LQ043T1DG01 TFT WQVGA (4.3) Sharp (DEFAULT)\";" \ + "echo \" vga[-dvi or -hdmi] LCD VGA 640x480\";" \ + "echo \" svga[-dvi or -hdmi] LCD SVGA 800x600\";" \ + "echo \" xga[-dvi or -hdmi] LCD XGA 1024x768\";" \ + "echo \" 720p[-dvi or -hdmi] LCD 720P 1280x720\";" \ + "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \ + "setenv display 15;" \ + "setenv preboot;" \ + "saveenv;" + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x81000000\0" \ + "bootfile=uImage\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mmcdev=0\0" \ + "autoboot=if mmc rescan ${mmcdev}; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "run defaultboot;" \ + "fi; " \ + "else run defaultboot; fi\0" \ + "defaultboot=run mmcramboot\0" \ + "consoledevice=ttyO0\0" \ + "display=15\0" \ + "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \ + "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \ + "rotation=0\0" \ + "vrfb_arg=if itest ${rotation} -ne 0; then " \ + "setenv bootargs ${bootargs} omapfb.vrfb=y " \ + "omapfb.rotate=${rotation}; " \ + "fi\0" \ + "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \ + "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "common_bootargs=setenv bootargs ${bootargs} display=${display} " \ + "${otherbootargs};" \ + "run addmtdparts; " \ + "run vrfb_arg\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo 'Running bootscript from mmc ...'; " \ + "source ${loadaddr}\0" \ + "loaduimage=mmc rescan ${mmcdev}; " \ + "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "ramdisksize=64000\0" \ + "ramdiskaddr=0x82000000\0" \ + "ramdiskimage=rootfs.ext2.gz.uboot\0" \ + "ramargs=run setconsole; setenv bootargs console=${console} " \ + "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ + "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \ + "run ramargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "run loaduimage; " \ + "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\ + "bootm ${loadaddr} ${ramdiskaddr}\0" \ + "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ + "run ramargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "tftpboot ${loadaddr} ${bootfile}; "\ + "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\ + "bootm ${loadaddr} ${ramdiskaddr}\0" + +#define CONFIG_BOOTCOMMAND \ + "run autoboot" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "OMAP Logic # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * OMAP3 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#elif defined(CONFIG_CMD_ONENAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#endif + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#if defined(CONFIG_CMD_NAND) +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#endif + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * SMSC922x Ethernet + */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_BASE 0x08000000 + +#endif /* (CONFIG_CMD_NET) */ + +/* + * BOOTP fields + */ + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index eb51ea9f9b..a5746d160c 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -102,9 +102,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 79eb46683b..bfd4570cce 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -13,8 +13,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc. */ #ifndef __CONFIG_H @@ -23,41 +22,41 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_OVERO 1 /* working with overo */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_OVERO /* working with overo */ -#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_SDRC /* The chip has SDRC controller */ -#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> /* * Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#undef CONFIG_USE_IRQ /* no support for IRQs */ +#undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG -#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_LIBFDT /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* * Hardware drivers @@ -66,7 +65,7 @@ /* * NS16550 Configuration */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -85,13 +84,10 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION /* commands to include */ #include <config_cmd_default.h> @@ -113,31 +109,29 @@ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 +#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP34XX_I2C /* * TWL4030 */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED /* * Board NAND Info. */ -#define CONFIG_SYS_NAND_QUIET_TEST 1 +#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ @@ -249,7 +243,6 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /*----------------------------------------------------------------------- @@ -272,7 +265,7 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ @@ -286,12 +279,17 @@ *---------------------------------------------------------------------------- */ -#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 +#define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ +/* + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -301,4 +299,51 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 1a30454c7d..4df5f5dac5 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -104,9 +104,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* commands to include */ #include <config_cmd_default.h> diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 90f4b9036e..404aed2f5f 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -137,9 +137,6 @@ #define CONFIG_SYS_I2C_BUS_SELECT 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 -/* DDR - I use Infineon DDR */ -#define CONFIG_OMAP3_INFINEON_DDR 1 - /* OMITTED: single 1 Gbit MT29F1G NAND flash */ /* diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index b0e10c762b..17608f5f28 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -99,9 +99,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 8a37ebfa3a..b60ece3c53 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -99,9 +99,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* Status LED */ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED 1 diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h new file mode 100644 index 0000000000..5ff410dbdb --- /dev/null +++ b/include/configs/openrisc-generic.h @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2011, Stefan Kristiansson, stefan.kristianssons@saunalahti.fi + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * BOARD/CPU + */ + +#define CONFIG_SYS_CLK_FREQ 50000000 +#define CONFIG_SYS_RESET_ADDR 0x00000100 + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_SIZE 0x02000000 + +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#define CONFIG_SYS_UART_BASE 0x90000000 +#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_UART_BAUD 115200 + +#define CONFIG_BOARD_NAME "OpenRISC Generic" + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_MAX_FLASH_SECT 0 + +/* + * SERIAL + */ +# define CONFIG_SYS_NS16550 +# define CONFIG_SYS_NS16550_SERIAL +# define CONFIG_SYS_NS16550_REG_SIZE 1 +# define CONFIG_CONS_INDEX 1 +# define CONFIG_SYS_NS16550_COM1 (0x90000000) +# define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ + +#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD +#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE} +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ +#define CONSOLE_ARG "console=console=ttyS0,115200\0" + +/* + * Ethernet + */ +#define CONFIG_ETHOC +#define CONFIG_SYS_ETHOC_BASE 0x92000000 + +#define CONFIG_BOOTFILE "boot.img" +#define CONFIG_LOADADDR 0x100000 /* 1MB mark */ + +/* + * TIMER + */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_OPENRISC_TMR_HZ 100 + +/* + * Memory organisation: + * + * RAM start --------------------------- + * | ... | + * --------------------------- + * | Stack | + * --------------------------- + * | Global data | + * --------------------------- + * | Environment | + * --------------------------- + * | Monitor | + * RAM end --------------------------- + */ +/* We're running in RAM */ +#define CONFIG_MONITOR_IS_IN_RAM +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + CONFIG_SYS_MONITOR_LEN) + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment, 128KB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + +/* + * Global data object and stack pointer + */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_ENV_ADDR \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_ADDR CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_STACK_LENGTH 0x10000 /* 64KB */ +#define CONFIG_SYS_MALLOC_LEN 0x400000 /* 4MB */ +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_INIT_SP_OFFSET \ + - CONFIG_SYS_STACK_LENGTH \ + - CONFIG_SYS_MALLOC_LEN) +/* + * MISC + */ +#define CONFIG_SYS_LONGHELP /* Provide extended help */ +#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ +#define CONFIG_SYS_MAXARGS 16 /* Max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print buf size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x2000) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP_ADDR - 0x20000) +#define CONFIG_CMDLINE_EDITING + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_BSP + +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#define CONFIG_OF_LIBFDT +#define CONFIG_LMB + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +#endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h new file mode 100644 index 0000000000..f869191f34 --- /dev/null +++ b/include/configs/plutux.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011 + * Avionic Design GmbH <www.avionic-design.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra2-common.h" + +/* High-level configuration options */ +#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M" +#define V_PROMPT "Tegra2 (Plutux) # " +#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Plutux" +#define CONFIG_SYS_BOARD_ODMDATA 0x2b2d8011 + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA2_ENABLE_UARTD /* UARTD: debug UART */ +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_ENV_IS_NOWHERE + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA2_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +#define CONFIG_FIT + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan;" \ + "ext2load mmc 0 0x17000000 /boot/uImage;" \ + "bootm" + +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index ba7612c5a1..d87394c8d1 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -57,9 +57,19 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ +/* + * If you want to boot from the SODIMM flash, instead of the soldered + * on flash, set this, and change JP12, SW2:8 accordingly. + */ +#undef CONFIG_SYS_ALT_BOOT + #ifndef CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_SYS_ALT_BOOT +#define CONFIG_SYS_TEXT_BASE 0xfff00000 +#else #define CONFIG_SYS_TEXT_BASE 0xfffa0000 #endif +#endif #undef CONFIG_RIO @@ -109,9 +119,17 @@ /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +/* + * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD + * to collide, meaning you couldn't reliably read either. So + * physically remove the LBC PC100 SDRAM module from the board + * before enabling the two SPD options below, or check that you + * have the hardware fix on your board via "i2c probe" and looking + * for a device at 0x53. + */ #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_SPD -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef @@ -124,14 +142,20 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 -/* I2C addresses of SPD EEPROMs */ +/* + * The hardware fix for the I2C address collision puts the DDR + * SPD at 0x53, but if we are running on an older board w/o the + * fix, it will still be at 0x51. We check 0x53 1st. + */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ +#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ /* * Make sure required options are set */ #ifndef CONFIG_SPD_EEPROM #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ + #define CONFIG_SYS_DDR_CONTROL 0xc300c000 #endif #undef CONFIG_CLOCKS_IN_MHZ @@ -139,28 +163,54 @@ /* * FLASH on the Local Bus * Two banks, one 8MB the other 64MB, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff80_0000 - * Alternate BR6/OR6 bank at 0xfb80_0000 + * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have + * CS0 the 8MB boot flash, and CS6 the 64MB flash. + * + * Default: + * ec00_0000 efff_ffff 64MB SODIMM + * ff80_0000 ffff_ffff 8MB soldered flash + * + * Alternate: + * ef80_0000 efff_ffff 8MB soldered flash + * fc00_0000 ffff_ffff 64MB SODIMM * - * BR0: + * BR0_8M: * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 * Port Size = 8 bits = BRx[19:20] = 01 * Use GPCM = BRx[24:26] = 000 * Valid = BRx[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0 - * - * BR6: - * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0 + * BR0_64M: + * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 * Port Size = 32 bits = BRx[19:20] = 11 + * + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M + * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M + */ +#define CONFIG_SYS_BR0_8M 0xff800801 +#define CONFIG_SYS_BR0_64M 0xfc001801 + +/* + * BR6_8M: + * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 + * Port Size = 8 bits = BRx[19:20] = 01 * Use GPCM = BRx[24:26] = 000 * Valid = BRx[31] = 1 + + * BR6_64M: + * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 + * Port Size = 32 bits = BRx[19:20] = 11 * * 0 4 8 12 16 20 24 28 - * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6 - * - * OR0: + * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M + * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M + */ +#define CONFIG_SYS_BR6_8M 0xef800801 +#define CONFIG_SYS_BR6_64M 0xec001801 + +/* + * OR0_8M: * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 * XAM = OR0[17:18] = 11 * CSNT = OR0[20] = 1 @@ -169,11 +219,20 @@ * TRLX = use relaxed timing = OR0[29] = 1 * EAD = use external address latch delay = OR0[31] = 1 * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0 + * OR0_64M: + * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 + * * - * OR6: - * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0 + * 0 4 8 12 16 20 24 28 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M + */ +#define CONFIG_SYS_OR0_8M 0xff806e65 +#define CONFIG_SYS_OR0_64M 0xfc006e65 + +/* + * OR6_8M: + * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 * XAM = OR6[17:18] = 11 * CSNT = OR6[20] = 1 * ACS = half cycle delay = OR6[21:22] = 11 @@ -181,20 +240,37 @@ * TRLX = use relaxed timing = OR6[29] = 1 * EAD = use external address latch delay = OR6[31] = 1 * + * OR6_64M: + * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 + * * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6 + * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M + * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M */ +#define CONFIG_SYS_OR6_8M 0xff806e65 +#define CONFIG_SYS_OR6_64M 0xfc006e65 +#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ -#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ +#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ -#define CONFIG_SYS_BR0_PRELIM 0xff800801 -#define CONFIG_SYS_BR6_PRELIM 0xfb801801 +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M -#define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR6_PRELIM 0xf8006e65 +#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M +#else /* JP12 in alternate position */ +#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M + +#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M +#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M +#endif + +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ CONFIG_SYS_ALT_FLASH} #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ @@ -221,6 +297,10 @@ /* * SDRAM on the Local Bus (CS3 and CS4) + * Note that most boards have a hardware errata where both the + * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible + * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. + * A hardware workaround is also available, see README.sbc8548 file. */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ @@ -300,19 +380,26 @@ /* * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. */ #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_PRETOACT7 \ - | LSDMR_ACTTORW7 \ + | LSDMR_BSMA1516 \ + | LSDMR_PRETOACT3 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BUFCMD \ | LSDMR_BL8 \ - | LSDMR_WRC4 \ + | LSDMR_WRC2 \ | LSDMR_CL3 \ - | LSDMR_RFEN \ ) +#define CONFIG_SYS_LBC_LSDMR_PCHALL \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_ARFRSH \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_MRW \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_RFEN \ + (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) + #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ @@ -330,7 +417,7 @@ * thing for MONITOR_LEN in both cases. */ #define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 7d2914472a..261f9521ad 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -37,11 +37,23 @@ #define CONFIG_TEGRA2_ENABLE_UARTD #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */ +#define CONFIG_UART_DISABLE_GPIO GPIO_PI3 + #define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD #define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */ #define CONFIG_BOARD_EARLY_INIT_F +/* SPI */ +#define CONFIG_TEGRA2_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC @@ -52,4 +64,12 @@ #define CONFIG_EFI_PARTITION #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT + +/* Environment in SPI */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_MAX_HZ 48000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 + +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h new file mode 100644 index 0000000000..817d468a72 --- /dev/null +++ b/include/configs/tam3517-common.h @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2009 TechNexion Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __TAM3517_H +#define __TAM3517_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \ + 2 * 1024 * 1024) +/* + * DDR related + */ +#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 /* UART1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_STORAGE + +/* #define CONFIG_EHCI_DCACHE */ + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +#undef CONFIG_CMD_FLASH /* only NAND on the SOM */ +#undef CONFIG_CMD_IMLS + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C + + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_AUTO_COMPLETE + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ + +/* Redundant Environment */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + 2 * CONFIG_SYS_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* + * ethernet support, EMAC + * + */ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_EMAC_MDIO_PHY_NUM 0 +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_CONSOLE +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) /* 45 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +/* Setup MTD for NAND on the SOM */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ + "512k(u-boot),128k(env1)," \ + "128k(env2),6m(kernel),-(rootfs)" + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_TAM3517_SETTINGS \ + "netdev=eth0\0" \ + "nandargs=setenv bootargs root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip_sta=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ + "addip=if test -n ${ipdyn};then run addip_dyn;" \ + "else run addip_sta;fi\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttyO0,${baudrate}\0" \ + "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ + "loadaddr=82000000\0" \ + "kernel_addr_r=82000000\0" \ + "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ + "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "nandboot=run nandargs addip addtty addmtd addmisc;" \ + "nand read ${kernel_addr_r} kernel\0" \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r}\0" \ + "net_self=if run net_self_load;then " \ + "run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ + "else echo Images not loades;fi\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "loadmlo=tftp ${loadaddr} ${mlo}\0" \ + "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \ + "uboot_addr=0x80000\0" \ + "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ + "nand write ${loadaddr} ${uboot_addr} 80000\0" \ + "updatemlo=nandecc hw;nand erase 0 20000;" \ + "nand write ${loadaddr} 0 20000\0" \ + "upd=if run load;then echo Updating u-boot;if run update;" \ + "then echo U-Boot updated;" \ + "else echo Error updating u-boot !;" \ + "echo Board without bootloader !!;" \ + "fi;" \ + "else echo U-Boot not downloaded..exiting;fi\0" \ + +#endif /* __TAM3517_H */ diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index e233b1c83d..e6f385fac3 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -51,8 +51,7 @@ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ /* Environment */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */ +#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ /* * Size of malloc() pool @@ -152,7 +151,7 @@ #define PHYS_SDRAM_1 TEGRA2_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_TEXT_BASE 0x00E08000 +#define CONFIG_SYS_TEXT_BASE 0x00108000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h deleted file mode 100644 index 2d9af3f525..0000000000 --- a/include/configs/tuxa1.h +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu <daveliu@freescale.com> - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada <peterb@logicpd.com> - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010 - * Yan Bin, Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_TUXA1 /* TUXA1 board specific */ -#define CONFIG_HOSTNAME tuxa1 -#define CONFIG_KM_BOARD_NAME "tuxa1" - -#define CONFIG_SYS_TEXT_BASE 0xF0000000 - -/* include common defines/options for all 8321 Keymile boards */ -#include "km/km8321-common.h" - -#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */ -#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */ -#define CONFIG_SYS_PINC2_BASE 0xB0000000 /* PINC2 */ -#define CONFIG_SYS_PINC2_SIZE 256 /* Megabytes */ - -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local GPCM 8 bit 256MB LPXF - * 3 Local GPCM 8 bit 256MB PINC2 - * - */ - -/* - * LPXF on the local bus CS2 - * Window base at flash base - * Window size: 256 MB - */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR | \ - OR_GPCM_EAD) -/* - * PINC2 on the local bus CS3 - * Access window base at PINC2 base - * Window size: 256 MB - */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PINC2_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) - -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PINC2_BASE | \ - BR_PS_8 | \ - BR_MS_GPCM | \ - BR_V) - -#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX_SET | \ - OR_GPCM_EHTR_CLEAR) - -#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ - 0x0000c000 | \ - MxMR_WLFx_2X) - -/* - * MMU Setup - */ -/* LPXF: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -/* PINC2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ - BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ - BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - -#endif /* __CONFIG_H */ diff --git a/include/configs/tuda1.h b/include/configs/tuxx1.h index 577bbd01c6..f6d2b17a38 100644 --- a/include/configs/tuda1.h +++ b/include/configs/tuxx1.h @@ -13,6 +13,7 @@ * * (C) Copyright 2010-2011 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com + * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,9 +27,13 @@ /* * High Level Configuration Options */ -#define CONFIG_TUDA1 /* TUDA1 board specific */ -#define CONFIG_HOSTNAME tuda1 -#define CONFIG_KM_BOARD_NAME "tuda1" +#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */ +#define CONFIG_HOSTNAME tuxx1 +#ifdef CONFIG_KM_DISABLE_APP2 +#define CONFIG_KM_BOARD_NAME "tuge1" +#else +#define CONFIG_KM_BOARD_NAME "tuxx1" +#endif #define CONFIG_SYS_TEXT_BASE 0xF0000000 @@ -37,27 +42,23 @@ #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ +#ifndef CONFIG_KM_DISABLE_APP2 #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ - -/* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) -#define CONFIG_SYS_LBC_LBCR 0x00000000 +#endif /* * Init Local Bus Memory Controller: * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 2 Local GPCM 8 bit 256MB PAXG - * 3 Local GPCM 8 bit 256MB PINC3 + * Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1 + * ---- --- ------- ------ ----- ---------------------------- + * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI + * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused * */ /* - * PAXG on the local bus CS2 + * Configuration for C2 on the local bus */ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE @@ -76,8 +77,9 @@ OR_GPCM_TRLX_SET | \ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) +#ifndef CONFIG_KM_DISABLE_APP2 /* - * PINC3 on the local bus CS3 + * Configuration for C3 on the local bus */ /* Access window base at PINC3 base */ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE @@ -99,11 +101,12 @@ #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) +#endif /* * MMU Setup */ -/* PAXG: icache cacheable, but dcache-inhibit and guarded */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ BATL_PP_RW | \ BATL_MEMCOHERENCE) @@ -118,7 +121,12 @@ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -/* PINC3: icache cacheable, but dcache-inhibit and guarded */ +#ifdef CONFIG_KM_DISABLE_APP2 +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#else +/* APP2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ BATL_PP_RW | \ BATL_MEMCOHERENCE) @@ -130,6 +138,7 @@ BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) +#endif #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U #define CONFIG_SYS_IBAT7L (0) diff --git a/include/configs/twister.h b/include/configs/twister.h new file mode 100644 index 0000000000..64a886d3a4 --- /dev/null +++ b/include/configs/twister.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2009 TechNexion Ltd. + * + * Configuration for the Technexion twister board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tam3517-common.h" + +#define MACH_TYPE_TAM3517 2818 +#define CONFIG_MACH_TYPE MACH_TYPE_TAM3517 + +#define CONFIG_TAM3517_SW3_SETTINGS +#define CONFIG_XR16L2751 + +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_HOSTNAME twister + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_PROMPT "twister => " + +#define CONFIG_SMC911X +#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 +#define CONFIG_SMC911X_NO_EEPROM + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ + "bootcmd=run nandboot\0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index afd6ff610c..acc9b434bb 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -52,4 +52,7 @@ #define CONFIG_EFI_PARTITION #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT + +/* Environment not stored */ +#define CONFIG_ENV_IS_NOWHERE #endif /* __CONFIG_H */ diff --git a/include/environment.h b/include/environment.h index 3c145af938..1ef44f3cc6 100644 --- a/include/environment.h +++ b/include/environment.h @@ -22,7 +22,7 @@ */ #ifndef _ENVIRONMENT_H_ -#define _ENVIRONMENT_H_ 1 +#define _ENVIRONMENT_H_ /************************************************************************** * @@ -64,10 +64,10 @@ # if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \ (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= \ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -# define ENV_IS_EMBEDDED 1 +# define ENV_IS_EMBEDDED # endif # if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND) -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT 1 +# define CONFIG_SYS_REDUNDAND_ENVIRONMENT # endif # ifdef CONFIG_ENV_IS_EMBEDDED # error "do not define CONFIG_ENV_IS_EMBEDDED in your board config" @@ -120,7 +120,7 @@ extern unsigned long nand_env_oob_offset; * calculated automatically (i.e. NAND), take the board opt-in. */ #if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED) -# define ENV_IS_EMBEDDED 1 +# define ENV_IS_EMBEDDED #endif /* The build system likes to know if the env is embedded */ diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index e7a072bbe8..949864c0f2 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -82,7 +82,10 @@ typedef struct ihs_fpga { u16 reserved_1[502]; /* 0x0014 */ u16 ch0_status_int; /* 0x0400 */ u16 ch0_config_int; /* 0x0402 */ - u16 reserved_2[7677]; /* 0x0404 */ + u16 reserved_2[126]; /* 0x0404 */ + u16 ch0_hicb_status_int;/* 0x0500 */ + u16 ch0_hicb_config_int;/* 0x0502 */ + u16 reserved_3[7549]; /* 0x0504 */ u16 reflection_high; /* 0x3ffe */ } ihs_fpga_t; #endif diff --git a/include/i2c.h b/include/i2c.h index ee31034c7a..1f35acf675 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -78,7 +78,7 @@ # elif (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY) -# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; +# define I2C_SOFT_DECLARATIONS at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA; # else # define I2C_SOFT_DECLARATIONS # endif diff --git a/include/image.h b/include/image.h index 466c98018f..bbf80f0cac 100644 --- a/include/image.h +++ b/include/image.h @@ -108,6 +108,7 @@ #define IH_ARCH_ST200 18 /* STMicroelectronics ST200 */ #define IH_ARCH_SANDBOX 19 /* Sandbox architecture (test only) */ #define IH_ARCH_NDS32 20 /* ANDES Technology - NDS32 */ +#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ /* * Image Types diff --git a/include/mmc.h b/include/mmc.h index 015a7f36ae..8744604ead 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -302,6 +302,7 @@ struct mmc { struct mmc_cmd *cmd, struct mmc_data *data); void (*set_ios)(struct mmc *mmc); int (*init)(struct mmc *mmc); + int (*getcd)(struct mmc *mmc); uint b_max; }; @@ -314,8 +315,9 @@ struct mmc *find_mmc_device(int dev_num); int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); int get_mmc_num(void); -int board_mmc_getcd(u8 *cd, struct mmc *mmc); +int board_mmc_getcd(struct mmc *mmc); int mmc_switch_part(int dev_num, unsigned int part_num); +int mmc_getcd(struct mmc *mmc); #ifdef CONFIG_GENERIC_MMC int atmel_mci_init(void *regs); diff --git a/include/netdev.h b/include/netdev.h index 150fa8e4d5..b0c21d5336 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -48,6 +48,7 @@ int at91emac_register(bd_t *bis, unsigned long iobase); int au1x00_enet_initialize(bd_t*); int ax88180_initialize(bd_t *bis); int bfin_EMAC_initialize(bd_t *bis); +int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); diff --git a/include/phy.h b/include/phy.h index 095f41c43b..bc522d57c3 100644 --- a/include/phy.h +++ b/include/phy.h @@ -224,6 +224,7 @@ int phy_marvell_init(void); int phy_micrel_init(void); int phy_natsemi_init(void); int phy_realtek_init(void); +int phy_smsc_init(void); int phy_teranetics_init(void); int phy_vitesse_init(void); diff --git a/include/spartan3.h b/include/spartan3.h index 67ede4b1d6..89f115694d 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -80,6 +80,12 @@ typedef struct { #define XILINX_XC3S1200E_SIZE 3841184/8 #define XILINX_XC3S1600E_SIZE 5969696/8 +/* + * Spartan-6 : the Spartan-6 family can be programmed + * exactly as the Spartan-3 + */ +#define XILINK_XC6SLX4_SIZE (3713568/8) + /* Descriptor Macros *********************************************************************/ /* Spartan-III devices */ @@ -123,4 +129,7 @@ typedef struct { #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ { Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } +#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ +{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } + #endif /* _SPARTAN3_H_ */ diff --git a/include/spi_flash.h b/include/spi_flash.h index 2671ab5539..9da90624f2 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -25,6 +25,7 @@ #include <spi.h> #include <linux/types.h> +#include <linux/compiler.h> struct spi_flash { struct spi_slave *spi; @@ -68,4 +69,6 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, return flash->erase(flash, offset, len); } +void spi_boot(void) __noreturn; + #endif /* _SPI_FLASH_H_ */ diff --git a/lib/Makefile b/lib/Makefile index 54708c261c..35ba7ffe47 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -50,6 +50,8 @@ COBJS-$(CONFIG_SHA1) += sha1.o COBJS-$(CONFIG_SHA256) += sha256.o COBJS-y += strmhz.o COBJS-$(CONFIG_RBTREE) += rbtree.o +else +COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o endif COBJS-y += ctype.o diff --git a/post/Makefile b/post/Makefile index 200e2f1b9a..55b7d21142 100644 --- a/post/Makefile +++ b/post/Makefile @@ -32,7 +32,7 @@ COBJS-$(CONFIG_POST_STD_LIST) += tests.o SPLIB-$(CONFIG_HAS_POST) = drivers/libpostdrivers.o SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH) ]; then echo \ "lib_$(ARCH)/libpost$(ARCH).o"; fi) -SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d lib_$(ARCH)/fpu ]; then echo \ +SPLIB-$(CONFIG_SYS_POST_FPU) += $(shell if [ -d lib_$(ARCH)/fpu ]; then echo \ "lib_$(ARCH)/fpu/libpost$(ARCH)fpu.o"; fi) SPLIB-$(CONFIG_HAS_POST) += $(shell if [ -d cpu/$(CPU) ]; then echo \ "cpu/$(CPU)/libpost$(CPU).o"; fi) diff --git a/spl/Makefile b/spl/Makefile index 6ac42a2d67..3262e226ae 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -58,13 +58,7 @@ LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o -ifeq ($(SOC),omap3) -LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -endif -ifeq ($(SOC),omap4) -LIBS-y += $(CPUDIR)/omap-common/libomap-common.o -endif -ifeq ($(SOC),omap5) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif @@ -104,6 +98,11 @@ $(OBJTREE)/MLO: $(obj)u-boot-spl.bin $(OBJTREE)/tools/mkimage -T omapimage \ -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ endif +ifdef CONFIG_AM33XX +$(OBJTREE)/MLO: $(obj)u-boot-spl.bin + $(OBJTREE)/tools/mkimage -T omapimage \ + -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ +endif ALL-y += $(obj)u-boot-spl.bin diff --git a/tools/Makefile b/tools/Makefile index a5f989a671..64bcc4db47 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -194,6 +194,7 @@ $(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o $(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ + $(HOSTSTRIP) $@ $(obj)mkimage$(SFX): $(obj)aisimage.o \ $(obj)crc32.o \ diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 996682ebc7..e292d2ba1d 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -45,6 +45,8 @@ #include "fw_env.h" +#include <config.h> + #define WHITESPACE(c) ((c == '\t') || (c == ' ')) #define min(x, y) ({ \ @@ -390,15 +392,22 @@ int fw_env_write(char *name, char *value) * Delete any existing definition */ if (oldval) { +#ifndef CONFIG_ENV_OVERWRITE /* * Ethernet Address and serial# can be set only once */ - if ((strcmp (name, "ethaddr") == 0) || - (strcmp (name, "serial#") == 0)) { + if ( + (strcmp(name, "serial#") == 0) || + ((strcmp(name, "ethaddr") == 0) +#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) + && (strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0) +#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */ + ) ) { fprintf (stderr, "Can't overwrite \"%s\"\n", name); errno = EROFS; return -1; } +#endif /* CONFIG_ENV_OVERWRITE */ if (*++nxt == '\0') { *env = '\0'; diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h index 9258c796d8..2dcb373b62 100644 --- a/tools/env/fw_env.h +++ b/tools/env/fw_env.h @@ -34,8 +34,12 @@ #define DEVICE2_NAME "/dev/mtd2" #define DEVICE1_OFFSET 0x0000 #define ENV1_SIZE 0x4000 +#define DEVICE1_ESIZE 0x4000 +#define DEVICE1_ENVSECTORS 2 #define DEVICE2_OFFSET 0x0000 #define ENV2_SIZE 0x4000 +#define DEVICE2_ESIZE 0x4000 +#define DEVICE2_ENVSECTORS 2 #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ diff --git a/tools/envcrc.c b/tools/envcrc.c index 51e3f54a38..08d2a8f550 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -53,15 +53,15 @@ # endif # if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \ ((CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) -# define ENV_IS_EMBEDDED 1 +# define ENV_IS_EMBEDDED # endif # if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND) -# define CONFIG_SYS_REDUNDAND_ENVIRONMENT 1 +# define CONFIG_SYS_REDUNDAND_ENVIRONMENT # endif #endif /* CONFIG_ENV_IS_IN_FLASH */ #if defined(ENV_IS_EMBEDDED) && !defined(CONFIG_BUILD_ENVCRC) -# define CONFIG_BUILD_ENVCRC 1 +# define CONFIG_BUILD_ENVCRC #endif #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index c5ed373b99..f78173163f 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -122,11 +122,11 @@ int main(int argc, char **argv) return EXIT_SUCCESS; case ':': fprintf(stderr, "Missing argument for option -%c\n", - option); + optopt); usage(argv[0]); return EXIT_FAILURE; default: - fprintf(stderr, "Wrong option -%c\n", option); + fprintf(stderr, "Wrong option -%c\n", optopt); usage(prg); return EXIT_FAILURE; } @@ -213,18 +213,18 @@ int main(int argc, char **argv) /* Replace newlines separating variables with \0 */ for (fp = 0, ep = 0 ; fp < filesize ; fp++) { if (filebuf[fp] == '\n') { - if (fp == 0) { + if (ep == 0) { /* - * Newline at the beginning of the file ? - * Ignore it. + * Newlines at the beginning of the file ? + * Ignore them. */ continue; } else if (filebuf[fp-1] == '\\') { /* * Embedded newline in a variable. * - * The backslash was added to the envptr ; - * rewind and replace it with a newline + * The backslash was added to the envptr; rewind + * and replace it with a newline */ ep--; envptr[ep++] = '\n'; diff --git a/tools/mkimage.c b/tools/mkimage.c index 36e28ec923..eeb1b10668 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -383,65 +383,66 @@ NXTARG: ; exit (EXIT_FAILURE); } - if (!params.skipcpy && - (params.type == IH_TYPE_MULTI || - params.type == IH_TYPE_SCRIPT)) { - char *file = params.datafile; - uint32_t size; - - for (;;) { - char *sep = NULL; - - if (file) { - if ((sep = strchr(file, ':')) != NULL) { - *sep = '\0'; + if (!params.skipcpy) { + if (params.type == IH_TYPE_MULTI || + params.type == IH_TYPE_SCRIPT) { + char *file = params.datafile; + uint32_t size; + + for (;;) { + char *sep = NULL; + + if (file) { + if ((sep = strchr(file, ':')) != NULL) { + *sep = '\0'; + } + + if (stat (file, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + params.cmdname, file, strerror(errno)); + exit (EXIT_FAILURE); + } + size = cpu_to_uimage (sbuf.st_size); + } else { + size = 0; } - if (stat (file, &sbuf) < 0) { - fprintf (stderr, "%s: Can't stat %s: %s\n", - params.cmdname, file, strerror(errno)); + if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) { + fprintf (stderr, "%s: Write error on %s: %s\n", + params.cmdname, params.imagefile, + strerror(errno)); exit (EXIT_FAILURE); } - size = cpu_to_uimage (sbuf.st_size); - } else { - size = 0; - } - if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) { - fprintf (stderr, "%s: Write error on %s: %s\n", - params.cmdname, params.imagefile, - strerror(errno)); - exit (EXIT_FAILURE); - } + if (!file) { + break; + } - if (!file) { - break; + if (sep) { + *sep = ':'; + file = sep + 1; + } else { + file = NULL; + } } - if (sep) { - *sep = ':'; - file = sep + 1; - } else { - file = NULL; - } - } + file = params.datafile; - file = params.datafile; - - for (;;) { - char *sep = strchr(file, ':'); - if (sep) { - *sep = '\0'; - copy_file (ifd, file, 1); - *sep++ = ':'; - file = sep; - } else { - copy_file (ifd, file, 0); - break; + for (;;) { + char *sep = strchr(file, ':'); + if (sep) { + *sep = '\0'; + copy_file (ifd, file, 1); + *sep++ = ':'; + file = sep; + } else { + copy_file (ifd, file, 0); + break; + } } + } else { + copy_file (ifd, params.datafile, 0); } - } else { - copy_file (ifd, params.datafile, 0); } /* We're a bit of paranoid */ diff --git a/tools/mxsboot.c b/tools/mxsboot.c index 176753d2ce..8246831d8e 100644 --- a/tools/mxsboot.c +++ b/tools/mxsboot.c @@ -606,6 +606,9 @@ int parse_ops(int argc, char **argv) }; int type; + if (argc < 4) + return -1; + for (i = 1; i < argc; i++) { if (!strncmp(argv[i], "-w", 2)) type = PARAM_WRITE; |
