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-rwxr-xr-xMAKEALL2
-rw-r--r--Makefile1
-rw-r--r--README1
-rw-r--r--arch/arm/cpu/ixp/Makefile12
-rw-r--r--arch/arm/cpu/ixp/config.mk16
-rw-r--r--arch/arm/cpu/ixp/cpu.c100
-rw-r--r--arch/arm/cpu/ixp/interrupts.c66
-rw-r--r--arch/arm/cpu/ixp/start.S430
-rw-r--r--arch/arm/cpu/ixp/timer.c101
-rw-r--r--arch/arm/cpu/ixp/u-boot.lds91
-rw-r--r--arch/arm/include/asm/arch-ixp/ixp425.h548
-rw-r--r--arch/arm/include/asm/arch-ixp/ixp425pci.h174
-rw-r--r--arch/arm/include/asm/global_data.h3
-rw-r--r--board/actux1/Makefile8
-rw-r--r--board/actux1/actux1.c148
-rw-r--r--board/actux1/actux1_hw.h41
-rw-r--r--board/actux1/u-boot.lds99
-rw-r--r--board/actux2/Makefile8
-rw-r--r--board/actux2/actux2.c122
-rw-r--r--board/actux2/actux2_hw.h43
-rw-r--r--board/actux2/u-boot.lds99
-rw-r--r--board/actux3/Makefile8
-rw-r--r--board/actux3/actux3.c149
-rw-r--r--board/actux3/actux3_hw.h44
-rw-r--r--board/actux3/u-boot.lds99
-rw-r--r--board/actux4/Makefile8
-rw-r--r--board/actux4/actux4.c129
-rw-r--r--board/actux4/actux4_hw.h33
-rw-r--r--board/dvlhost/Makefile8
-rw-r--r--board/dvlhost/dvlhost.c112
-rw-r--r--board/dvlhost/dvlhost_hw.h31
-rw-r--r--board/dvlhost/u-boot.lds99
-rw-r--r--board/dvlhost/watchdog.c27
-rw-r--r--boards.cfg8
-rw-r--r--doc/README.scrapyard5
-rw-r--r--doc/driver-model/UDM-pci.txt4
-rw-r--r--doc/driver-model/UDM-serial.txt4
-rw-r--r--drivers/i2c/soft_i2c.c3
-rw-r--r--drivers/net/npe/IxEthAcc.c237
-rw-r--r--drivers/net/npe/IxEthAccCommon.c1025
-rw-r--r--drivers/net/npe/IxEthAccControlInterface.c509
-rw-r--r--drivers/net/npe/IxEthAccDataPlane.c2459
-rw-r--r--drivers/net/npe/IxEthAccMac.c2617
-rw-r--r--drivers/net/npe/IxEthAccMii.c386
-rw-r--r--drivers/net/npe/IxEthDBAPI.c424
-rw-r--r--drivers/net/npe/IxEthDBAPISupport.c651
-rw-r--r--drivers/net/npe/IxEthDBCore.c439
-rw-r--r--drivers/net/npe/IxEthDBEvents.c496
-rw-r--r--drivers/net/npe/IxEthDBFeatures.c638
-rw-r--r--drivers/net/npe/IxEthDBFirewall.c242
-rw-r--r--drivers/net/npe/IxEthDBHashtable.c618
-rw-r--r--drivers/net/npe/IxEthDBLearning.c125
-rw-r--r--drivers/net/npe/IxEthDBMem.c625
-rw-r--r--drivers/net/npe/IxEthDBNPEAdaptor.c695
-rw-r--r--drivers/net/npe/IxEthDBPortUpdate.c716
-rw-r--r--drivers/net/npe/IxEthDBReports.c628
-rw-r--r--drivers/net/npe/IxEthDBSearch.c303
-rw-r--r--drivers/net/npe/IxEthDBSpanningTree.c83
-rw-r--r--drivers/net/npe/IxEthDBUtil.c96
-rw-r--r--drivers/net/npe/IxEthDBVlan.c1155
-rw-r--r--drivers/net/npe/IxEthDBWiFi.c456
-rw-r--r--drivers/net/npe/IxEthMii.c473
-rw-r--r--drivers/net/npe/IxFeatureCtrl.c398
-rw-r--r--drivers/net/npe/IxNpeDl.c916
-rw-r--r--drivers/net/npe/IxNpeDlImageMgr.c663
-rw-r--r--drivers/net/npe/IxNpeDlNpeMgr.c907
-rw-r--r--drivers/net/npe/IxNpeDlNpeMgrUtils.c782
-rw-r--r--drivers/net/npe/IxNpeMh.c558
-rw-r--r--drivers/net/npe/IxNpeMhConfig.c584
-rw-r--r--drivers/net/npe/IxNpeMhReceive.c296
-rw-r--r--drivers/net/npe/IxNpeMhSend.c283
-rw-r--r--drivers/net/npe/IxNpeMhSolicitedCbMgr.c334
-rw-r--r--drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c222
-rw-r--r--drivers/net/npe/IxOsalBufferMgt.c776
-rw-r--r--drivers/net/npe/IxOsalIoMem.c307
-rw-r--r--drivers/net/npe/IxOsalOsCacheMMU.c43
-rw-r--r--drivers/net/npe/IxOsalOsMsgQ.c55
-rw-r--r--drivers/net/npe/IxOsalOsSemaphore.c209
-rw-r--r--drivers/net/npe/IxOsalOsServices.c227
-rw-r--r--drivers/net/npe/IxOsalOsThread.c74
-rw-r--r--drivers/net/npe/IxQMgrAqmIf.c939
-rw-r--r--drivers/net/npe/IxQMgrDispatcher.c1320
-rw-r--r--drivers/net/npe/IxQMgrInit.c209
-rw-r--r--drivers/net/npe/IxQMgrQAccess.c772
-rw-r--r--drivers/net/npe/IxQMgrQCfg.c519
-rw-r--r--drivers/net/npe/Makefile60
-rw-r--r--drivers/net/npe/include/IxAssert.h47
-rw-r--r--drivers/net/npe/include/IxAtmSch.h480
-rw-r--r--drivers/net/npe/include/IxAtmTypes.h385
-rw-r--r--drivers/net/npe/include/IxAtmdAcc.h1169
-rw-r--r--drivers/net/npe/include/IxAtmdAccCtrl.h1933
-rw-r--r--drivers/net/npe/include/IxAtmm.h771
-rw-r--r--drivers/net/npe/include/IxDmaAcc.h236
-rw-r--r--drivers/net/npe/include/IxEthAcc.h2488
-rw-r--r--drivers/net/npe/include/IxEthAccDataPlane_p.h221
-rw-r--r--drivers/net/npe/include/IxEthAccMac_p.h224
-rw-r--r--drivers/net/npe/include/IxEthAccMii_p.h73
-rw-r--r--drivers/net/npe/include/IxEthAccQueueAssign_p.h113
-rw-r--r--drivers/net/npe/include/IxEthAcc_p.h301
-rw-r--r--drivers/net/npe/include/IxEthDB.h2349
-rw-r--r--drivers/net/npe/include/IxEthDBLocks_p.h98
-rw-r--r--drivers/net/npe/include/IxEthDBLog_p.h203
-rw-r--r--drivers/net/npe/include/IxEthDBMessages_p.h234
-rw-r--r--drivers/net/npe/include/IxEthDBPortDefs.h139
-rw-r--r--drivers/net/npe/include/IxEthDBQoS.h130
-rw-r--r--drivers/net/npe/include/IxEthDB_p.h686
-rw-r--r--drivers/net/npe/include/IxEthMii.h246
-rw-r--r--drivers/net/npe/include/IxEthMii_p.h161
-rw-r--r--drivers/net/npe/include/IxEthNpe.h671
-rw-r--r--drivers/net/npe/include/IxFeatureCtrl.h718
-rw-r--r--drivers/net/npe/include/IxHssAcc.h1292
-rw-r--r--drivers/net/npe/include/IxI2cDrv.h843
-rw-r--r--drivers/net/npe/include/IxNpeA.h758
-rw-r--r--drivers/net/npe/include/IxNpeDl.h956
-rw-r--r--drivers/net/npe/include/IxNpeDlImageMgr_p.h339
-rw-r--r--drivers/net/npe/include/IxNpeDlMacros_p.h390
-rw-r--r--drivers/net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h869
-rw-r--r--drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h381
-rw-r--r--drivers/net/npe/include/IxNpeDlNpeMgr_p.h236
-rw-r--r--drivers/net/npe/include/IxNpeMh.h473
-rw-r--r--drivers/net/npe/include/IxNpeMhConfig_p.h531
-rw-r--r--drivers/net/npe/include/IxNpeMhMacros_p.h272
-rw-r--r--drivers/net/npe/include/IxNpeMhReceive_p.h115
-rw-r--r--drivers/net/npe/include/IxNpeMhSend_p.h139
-rw-r--r--drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h147
-rw-r--r--drivers/net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h145
-rw-r--r--drivers/net/npe/include/IxNpeMicrocode.h272
-rw-r--r--drivers/net/npe/include/IxOsBufLib.h31
-rw-r--r--drivers/net/npe/include/IxOsBuffMgt.h28
-rw-r--r--drivers/net/npe/include/IxOsBuffPoolMgt.h50
-rw-r--r--drivers/net/npe/include/IxOsCacheMMU.h36
-rw-r--r--drivers/net/npe/include/IxOsPrintf.h78
-rw-r--r--drivers/net/npe/include/IxOsServices.h31
-rw-r--r--drivers/net/npe/include/IxOsServicesComponents.h110
-rw-r--r--drivers/net/npe/include/IxOsServicesEndianess.h28
-rw-r--r--drivers/net/npe/include/IxOsServicesMemAccess.h28
-rw-r--r--drivers/net/npe/include/IxOsServicesMemMap.h30
-rw-r--r--drivers/net/npe/include/IxOsal.h1493
-rw-r--r--drivers/net/npe/include/IxOsalAssert.h57
-rw-r--r--drivers/net/npe/include/IxOsalBackward.h41
-rw-r--r--drivers/net/npe/include/IxOsalBackwardAssert.h30
-rw-r--r--drivers/net/npe/include/IxOsalBackwardBufferMgt.h135
-rw-r--r--drivers/net/npe/include/IxOsalBackwardCacheMMU.h45
-rw-r--r--drivers/net/npe/include/IxOsalBackwardMemMap.h117
-rw-r--r--drivers/net/npe/include/IxOsalBackwardOsServices.h101
-rw-r--r--drivers/net/npe/include/IxOsalBackwardOssl.h248
-rw-r--r--drivers/net/npe/include/IxOsalBufferMgt.h570
-rw-r--r--drivers/net/npe/include/IxOsalBufferMgtDefault.h64
-rw-r--r--drivers/net/npe/include/IxOsalConfig.h52
-rw-r--r--drivers/net/npe/include/IxOsalEndianess.h110
-rw-r--r--drivers/net/npe/include/IxOsalIoMem.h298
-rw-r--r--drivers/net/npe/include/IxOsalMemAccess.h470
-rw-r--r--drivers/net/npe/include/IxOsalOem.h73
-rw-r--r--drivers/net/npe/include/IxOsalOs.h30
-rw-r--r--drivers/net/npe/include/IxOsalOsAssert.h10
-rw-r--r--drivers/net/npe/include/IxOsalOsBufferMgt.h72
-rw-r--r--drivers/net/npe/include/IxOsalOsIxp400.h292
-rw-r--r--drivers/net/npe/include/IxOsalOsIxp400CustomizedMapping.h380
-rw-r--r--drivers/net/npe/include/IxOsalOsTypes.h60
-rw-r--r--drivers/net/npe/include/IxOsalOsUtilitySymbols.h4
-rw-r--r--drivers/net/npe/include/IxOsalTypes.h355
-rw-r--r--drivers/net/npe/include/IxOsalUtilitySymbols.h27
-rw-r--r--drivers/net/npe/include/IxParityENAcc.h761
-rw-r--r--drivers/net/npe/include/IxPerfProfAcc.h1334
-rw-r--r--drivers/net/npe/include/IxQMgr.h2186
-rw-r--r--drivers/net/npe/include/IxQMgrAqmIf_p.h903
-rw-r--r--drivers/net/npe/include/IxQMgrDefines_p.h31
-rw-r--r--drivers/net/npe/include/IxQMgrDispatcher_p.h82
-rw-r--r--drivers/net/npe/include/IxQMgrLog_p.h100
-rw-r--r--drivers/net/npe/include/IxQMgrQAccess_p.h72
-rw-r--r--drivers/net/npe/include/IxQMgrQCfg_p.h98
-rw-r--r--drivers/net/npe/include/IxQueueAssignments.h492
-rw-r--r--drivers/net/npe/include/IxSspAcc.h1247
-rw-r--r--drivers/net/npe/include/IxTimeSyncAcc.h759
-rw-r--r--drivers/net/npe/include/IxTimerCtrl.h239
-rw-r--r--drivers/net/npe/include/IxTypes.h62
-rw-r--r--drivers/net/npe/include/IxUART.h434
-rw-r--r--drivers/net/npe/include/IxVersionId.h131
-rw-r--r--drivers/net/npe/include/ix_error.h42
-rw-r--r--drivers/net/npe/include/ix_macros.h242
-rw-r--r--drivers/net/npe/include/ix_os_type.h41
-rw-r--r--drivers/net/npe/include/ix_ossl.h136
-rw-r--r--drivers/net/npe/include/ix_symbols.h82
-rw-r--r--drivers/net/npe/include/ix_types.h184
-rw-r--r--drivers/net/npe/include/npe.h74
-rw-r--r--drivers/net/npe/include/os_datatypes.h58
-rw-r--r--drivers/net/npe/miiphy.c101
-rw-r--r--drivers/net/npe/npe.c680
-rw-r--r--drivers/pci/Makefile1
-rw-r--r--drivers/pci/pci_ixp.c351
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial.c2
-rw-r--r--drivers/serial/serial_ixp.c130
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/ehci-ixp4xx.c37
-rw-r--r--include/configs/actux1.h226
-rw-r--r--include/configs/actux2.h206
-rw-r--r--include/configs/actux3.h205
-rw-r--r--include/configs/actux4.h204
-rw-r--r--include/configs/dvlhost.h222
200 files changed, 5 insertions, 70403 deletions
diff --git a/MAKEALL b/MAKEALL
index 54b0d893a6..8fedea242e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -398,8 +398,6 @@ LIST_at91="$(targets_by_soc at91)"
LIST_pxa="$(targets_by_cpu pxa)"
-LIST_ixp="$(targets_by_cpu ixp)"
-
#########################################################################
## SPEAr Systems
#########################################################################
diff --git a/Makefile b/Makefile
index 1687e2e90a..0e07aa5970 100644
--- a/Makefile
+++ b/Makefile
@@ -227,7 +227,6 @@ LIBS-y += $(CPUDIR)/
ifdef SOC
LIBS-y += $(CPUDIR)/$(SOC)/
endif
-LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/
LIBS-$(CONFIG_OF_EMBED) += dts/
LIBS-y += arch/$(ARCH)/lib/
LIBS-y += fs/
diff --git a/README b/README
index fe48ccd292..4376f280d4 100644
--- a/README
+++ b/README
@@ -141,7 +141,6 @@ Directory Hierarchy:
/s3c24x0 Files specific to Samsung S3C24X0 CPUs
/arm926ejs Files specific to ARM 926 CPUs
/arm1136 Files specific to ARM 1136 CPUs
- /ixp Files specific to Intel XScale IXP CPUs
/pxa Files specific to Intel XScale PXA CPUs
/sa1100 Files specific to Intel StrongARM SA1100 CPUs
/lib Architecture specific library files
diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile
deleted file mode 100644
index 4e66523c03..0000000000
--- a/arch/arm/cpu/ixp/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-
-obj-y += cpu.o
-obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
deleted file mode 100644
index 894861fb4f..0000000000
--- a/arch/arm/cpu/ixp/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-BIG_ENDIAN = y
-
-PLATFORM_RELFLAGS += -mbig-endian
-
-PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
-
-PLATFORM_LDFLAGS += -EB
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c
deleted file mode 100644
index 4387c18d3d..0000000000
--- a/arch/arm/cpu/ixp/cpu.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/arch/ixp425.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
- unsigned long id;
- int speed = 0;
-
- asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
- puts("CPU: Intel IXP425 at ");
- switch ((id & 0x000003f0) >> 4) {
- case 0x1c:
- speed = 533;
- break;
-
- case 0x1d:
- speed = 400;
- break;
-
- case 0x1f:
- speed = 266;
- break;
- }
-
- if (speed)
- printf("%d MHz\n", speed);
- else
- puts("unknown revision\n");
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * just disable everything that can disturb booting linux
- */
-
- disable_interrupts ();
-
- /* turn off I-cache */
- icache_disable();
- dcache_disable();
-
- /* flush I-cache */
- cache_flush();
-
- return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
- unsigned long i = 0;
-
- asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-/* FIXME */
-/*
-void pci_init(void)
-{
- return;
-}
-*/
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_IXP4XX_NPE
- npe_initialize(bis);
-#endif
- return 0;
-}
diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c
deleted file mode 100644
index 7694c6a6cc..0000000000
--- a/arch/arm/cpu/ixp/interrupts.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/proc-armv/ptrace.h>
-
-struct _irq_handler {
- void *m_data;
- void (*m_func)( void *data);
-};
-
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-
-static void default_isr(void *data)
-{
- printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n",
- (int)data, *IXP425_ICIP, *IXP425_ICIH);
-}
-
-static int next_irq(void)
-{
- return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
- int irq = next_irq();
-
- IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
-}
-
-void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
-{
- if (irq >= N_IRQS || !handle_irq)
- return;
-
- IRQ_HANDLER[irq].m_data = data;
- IRQ_HANDLER[irq].m_func = handle_irq;
-}
-
-int arch_interrupt_init (void)
-{
- int i;
-
- /* install default interrupt handlers */
- for (i = 0; i < N_IRQS; i++)
- irq_install_handler(i, default_isr, (void *)i);
-
- /* configure interrupts for IRQ mode */
- *IXP425_ICLR = 0x00000000;
-
- return (0);
-}
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
deleted file mode 100644
index 82c868a174..0000000000
--- a/arch/arm/cpu/ixp/start.S
+++ /dev/null
@@ -1,430 +0,0 @@
-/* vi: set ts=8 sw=8 noet: */
-/*
- * u-boot - Startup Code for XScale IXP
- *
- * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
- *
- * Based on startup code example contained in the
- * Intel IXP4xx Programmer's Guide and past u-boot Start.S
- * samples.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/arch/ixp425.h>
-
-#define MMU_Control_M 0x001 /* Enable MMU */
-#define MMU_Control_A 0x002 /* Enable address alignment faults */
-#define MMU_Control_C 0x004 /* Enable cache */
-#define MMU_Control_W 0x008 /* Enable write-buffer */
-#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
-#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
-#define MMU_Control_L 0x040 /* Compatability: */
-#define MMU_Control_B 0x080 /* Enable Big-Endian */
-#define MMU_Control_S 0x100 /* Enable system protection */
-#define MMU_Control_R 0x200 /* Enable ROM protection */
-#define MMU_Control_I 0x1000 /* Enable Instruction cache */
-#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
- /* Delay a bit */
- .macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
- .endm
-
- /* wait for coprocessor write complete */
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
-
-.globl _start
-_start:
- ldr pc, _reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_reset: .word reset
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * - relocate armboot to ram
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
- .word CONFIG_SPL_TEXT_BASE
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
- /* disable mmu, set big-endian */
- mov r0, #0xf8
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* disable write buffer coalescing */
- mrc p15, 0, r0, c1, c0, 1
- orr r0, r0, #1
- mcr p15, 0, r0, c1, c0, 1
- CPWAIT r0
-
- /* set EXP CS0 to the optimum timing */
- ldr r1, =CONFIG_SYS_EXP_CS0
- ldr r2, =IXP425_EXP_CS0
- str r1, [r2]
-
- /* make sure flash is visible at 0 */
- mov r1, #CONFIG_SYS_SDR_CONFIG
- ldr r2, =IXP425_SDR_CONFIG
- str r1, [r2]
-
- /* disable refresh cycles */
- mov r1, #0
- ldr r3, =IXP425_SDR_REFRESH
- str r1, [r3]
-
- /* send nop command */
- mov r1, #3
- ldr r4, =IXP425_SDR_IR
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* set SDRAM internal refresh val */
- ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
- str r1, [r3]
- DELAY_FOR 0x4000, r0
-
- /* send precharge-all command to close all open banks */
- mov r1, #2
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* provide 8 auto-refresh cycles */
- mov r1, #4
- mov r5, #8
-111: str r1, [r4]
- DELAY_FOR 0x100, r0
- subs r5, r5, #1
- bne 111b
-
- /* set mode register in sdram */
- mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* send normal operation command */
- mov r1, #6
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* invalidate I & D caches & BTB */
- mcr p15, 0, r0, c7, c7, 0
- CPWAIT r0
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* drain write and fill buffers */
- mcr p15, 0, r0, c7, c10, 4
- CPWAIT r0
-
- /* remove flash mirror at 0x00000000 */
- ldr r2, =IXP425_EXP_CFG0
- ldr r1, [r2]
- bic r1, r1, #0x80000000
- str r1, [r2]
-
- /* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
-
- /* enable I cache */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #MMU_Control_I
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
-
- mrs r0,cpsr /* set the cpu to SVC32 mode */
- bic r0,r0,#0x1f /* (superviser mode, M=10011) */
- orr r0,r0,#0x13
- msr cpsr,r0
-
- bl _main
-
-/*------------------------------------------------------------------------------*/
-
- .globl c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
- bx lr
-
-/****************************************************************************/
-/* */
-/* Interrupt handling */
-/* */
-/****************************************************************************/
-
-/* IRQ stack frame */
-
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-
- /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
-
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
- add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
- mov r0, sp
- .endm
-
-
- /* use irq_save_user_regs / irq_restore_user_regs for */
- /* IRQ/FIQ handling */
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} /* Calling r0-r12 */
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ /* Calling SP, LR */
- str lr, [r8, #0] /* Save calling PC */
- mrs r6, spsr
- str r6, [r8, #4] /* Save CPSR */
- str r0, [r8, #8] /* Save OLD_R0 */
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- msr spsr_c, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-
-/****************************************************************************/
-/* */
-/* exception handlers */
-/* */
-/****************************************************************************/
-
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- irq_save_user_regs /* someone ought to write a more */
- bl do_fiq /* effiction fiq_save_user_regs */
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-
-/****************************************************************************/
-/* */
-/* Reset function: Use Watchdog to reset */
-/* */
-/****************************************************************************/
-
- .align 5
-.globl reset_cpu
-
-reset_cpu:
- ldr r1, =0x482e
- ldr r2, =IXP425_OSWK
- str r1, [r2]
- ldr r1, =0x0fff
- ldr r2, =IXP425_OSWT
- str r1, [r2]
- ldr r1, =0x5
- ldr r2, =IXP425_OSWE
- str r1, [r2]
- b reset_endless
-
-reset_endless:
- b reset_endless
diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c
deleted file mode 100644
index 38e2e2879c..0000000000
--- a/arch/arm/cpu/ixp/timer.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
- * 33.333MHz crystal).
- */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, CONFIG_IXP425_TIMER_CLK);
- return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
- time *= CONFIG_IXP425_TIMER_CLK;
- do_div(time, CONFIG_SYS_HZ);
- return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
- us = us * CONFIG_IXP425_TIMER_CLK + 999999;
- do_div(us, 1000000);
- return us;
-}
-
-unsigned long long get_ticks(void)
-{
- ulong now = readl(IXP425_OSTS_B);
-
- if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
- /* rollover of timestamp timer register */
- gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
- writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
- } else {
- /* move stamp forward with absolut diff ticks */
- gd->arch.timestamp += (now - gd->arch.lastinc);
- }
- gd->arch.lastinc = now;
- return gd->arch.timestamp;
-}
-
-
-void reset_timer_masked(void)
-{
- /* capture current timestamp counter */
- gd->arch.lastinc = readl(IXP425_OSTS_B);
- /* start "advancing" time stamp from 0 */
- gd->arch.timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
-
- tmp = get_ticks() + us_to_tick(usec);
-
- while (get_ticks() < tmp)
- ;
-}
-
-int timer_init(void)
-{
- writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
- return 0;
-}
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
deleted file mode 100644
index 676ae2c4f9..0000000000
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h
deleted file mode 100644
index c2e9c82049..0000000000
--- a/arch/arm/include/asm/arch-ixp/ixp425.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
- * include/asm-arm/arch-ixp425/ixp425.h
- *
- * Register definitions for IXP425
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ASM_ARM_IXP425_H_
-#define _ASM_ARM_IXP425_H_
-
-#define BIT(x) (1<<(x))
-
-/* FIXME: Only this does work for u-boot... find out why... [RS] */
-#define UBOOT_REG_FIX 1
-#ifdef UBOOT_REG_FIX
-# undef io_p2v
-# undef __REG
-# ifndef __ASSEMBLY__
-# define io_p2v(PhAdd) (PhAdd)
-# define __REG(x) (*((volatile u32 *)io_p2v(x)))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
-# else
-# define __REG(x) (x)
-# endif
-#endif /* UBOOT_REG_FIX */
-
-/*
- *
- * IXP425 Memory map:
- *
- * Phy Phy Size Map Size Virt Description
- * =========================================================================
- *
- * 0x00000000 0x10000000 SDRAM 1
- *
- * 0x10000000 0x10000000 SDRAM 2
- *
- * 0x20000000 0x10000000 SDRAM 3
- *
- * 0x30000000 0x10000000 SDRAM 4
- *
- * The above four are aliases to the same memory location (0x00000000)
- *
- * 0x48000000 0x4000000 PCI Memory
- *
- * 0x50000000 0x10000000 Not Mapped EXP BUS
- *
- * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
- *
- * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
- *
- * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
- *
- * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
- *
- * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
- */
-
-/*
- * SDRAM
- */
-#define IXP425_SDRAM_BASE (0x00000000)
-#define IXP425_SDRAM_BASE_ALT (0x10000000)
-
-
-/*
- * PCI Configuration space
- */
-#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
-#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
-
-/*
- * Expansion BUS Configuration registers
- */
-#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
-#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
-
-/*
- * Peripheral space
- */
-#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
-#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
-
-/*
- * SDRAM configuration registers
- */
-#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000)
-
-/*
- * Q Manager space .. not static mapped
- */
-#define IXP425_QMGR_BASE_PHYS (0x60000000)
-#define IXP425_QMGR_REGION_SIZE (0x00004000)
-
-/*
- * Expansion BUS
- *
- * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
- * Exp Bus config registers:
- *
- * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
- * and The expansion bus to IXP425_EXP_BUS_BASE2
- */
-#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
-#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
-
-#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
-
-#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
-#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
-
-#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-
-#define IXP425_FLASH_WRITABLE (0x2)
-#define IXP425_FLASH_DEFAULT (0xbcd23c40)
-#define IXP425_FLASH_WRITE (0xbcd23c42)
-
-#define IXP425_EXP_CS0_OFFSET 0x00
-#define IXP425_EXP_CS1_OFFSET 0x04
-#define IXP425_EXP_CS2_OFFSET 0x08
-#define IXP425_EXP_CS3_OFFSET 0x0C
-#define IXP425_EXP_CS4_OFFSET 0x10
-#define IXP425_EXP_CS5_OFFSET 0x14
-#define IXP425_EXP_CS6_OFFSET 0x18
-#define IXP425_EXP_CS7_OFFSET 0x1C
-#define IXP425_EXP_CFG0_OFFSET 0x20
-#define IXP425_EXP_CFG1_OFFSET 0x24
-#define IXP425_EXP_CFG2_OFFSET 0x28
-#define IXP425_EXP_CFG3_OFFSET 0x2C
-
-/*
- * Expansion Bus Controller registers.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
-
-#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
-#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
-#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
-#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
-#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
-#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-
-#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
-#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
-
-/*
- * SDRAM Controller registers.
- */
-#define IXP425_SDR_CONFIG_OFFSET 0x00
-#define IXP425_SDR_REFRESH_OFFSET 0x04
-#define IXP425_SDR_IR_OFFSET 0x08
-
-#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x))
-
-#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET)
-#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET)
-#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
-
-/*
- * UART registers
- */
-#define IXP425_UART1 0
-#define IXP425_UART2 0x1000
-
-#define IXP425_UART_RBR_OFFSET 0x00
-#define IXP425_UART_THR_OFFSET 0x00
-#define IXP425_UART_DLL_OFFSET 0x00
-#define IXP425_UART_IER_OFFSET 0x04
-#define IXP425_UART_DLH_OFFSET 0x04
-#define IXP425_UART_IIR_OFFSET 0x08
-#define IXP425_UART_FCR_OFFSET 0x00
-#define IXP425_UART_LCR_OFFSET 0x0c
-#define IXP425_UART_MCR_OFFSET 0x10
-#define IXP425_UART_LSR_OFFSET 0x14
-#define IXP425_UART_MSR_OFFSET 0x18
-#define IXP425_UART_SPR_OFFSET 0x1c
-#define IXP425_UART_ISR_OFFSET 0x20
-
-#define IXP425_UART_CFG_BASE_PHYS (0xc8000000)
-
-#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
-#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
-#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
-#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
-#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
-#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
-#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
-#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
-#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
-#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
-#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
-#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
-#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
-
-#define IER_DMAE (1 << 7) /* DMA Requests Enable */
-#define IER_UUE (1 << 6) /* UART Unit Enable */
-#define IER_NRZE (1 << 5) /* NRZ coding Enable */
-#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
-#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
-#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
-#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
-#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
-#define IIR_TOD (1 << 3) /* Time Out Detected */
-#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
-#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
-#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
-
-#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
-#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
-#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
-#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
-#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1 (0)
-#define FCR_ITL_8 (FCR_ITL1)
-#define FCR_ITL_16 (FCR_ITL2)
-#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
-#define LCR_SB (1 << 6) /* Set Break */
-#define LCR_STKYP (1 << 5) /* Sticky Parity */
-#define LCR_EPS (1 << 4) /* Even Parity Select */
-#define LCR_PEN (1 << 3) /* Parity Enable */
-#define LCR_STB (1 << 2) /* Stop Bit */
-#define LCR_WLS1 (1 << 1) /* Word Length Select */
-#define LCR_WLS0 (1 << 0) /* Word Length Select */
-
-#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
-#define LSR_TEMT (1 << 6) /* Transmitter Empty */
-#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
-#define LSR_BI (1 << 4) /* Break Interrupt */
-#define LSR_FE (1 << 3) /* Framing Error */
-#define LSR_PE (1 << 2) /* Parity Error */
-#define LSR_OE (1 << 1) /* Overrun Error */
-#define LSR_DR (1 << 0) /* Data Ready */
-
-#define MCR_LOOP (1 << 4) */
-#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
-#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
-#define MCR_RTS (1 << 1) /* Request to Send */
-#define MCR_DTR (1 << 0) /* Data Terminal Ready */
-
-#define MSR_DCD (1 << 7) /* Data Carrier Detect */
-#define MSR_RI (1 << 6) /* Ring Indicator */
-#define MSR_DSR (1 << 5) /* Data Set Ready */
-#define MSR_CTS (1 << 4) /* Clear To Send */
-#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
-#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
-#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
-#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
-
-#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
-/*
- * Peripheral Space Registers
- */
-#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
-#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
-#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
-#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
-#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
-#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
-#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
-#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
-#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
-#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
-#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
-#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-
-/*
- * UART Register Definitions , Offsets only as there are 2 UARTS.
- * IXP425_UART1_BASE , IXP425_UART2_BASE.
- */
-
-#undef UART_NO_RX_INTERRUPT
-
-#define IXP425_UART_XTAL 14745600
-
-/*
- * Constants to make it easy to access Interrupt Controller registers
- */
-#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */
-#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */
-#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */
-#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */
-#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */
-#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
-#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
-
-#define N_IRQS 32
-#define IXP425_TIMER_2_IRQ 11
-
-/*
- * Interrupt Controller Register Definitions.
- */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
-
-#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET)
-#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET)
-#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET)
-#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET)
-#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET)
-#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET)
-#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP425_GPIO_GPOUTR_OFFSET 0x00
-#define IXP425_GPIO_GPOER_OFFSET 0x04
-#define IXP425_GPIO_GPINR_OFFSET 0x08
-#define IXP425_GPIO_GPISR_OFFSET 0x0C
-#define IXP425_GPIO_GPIT1R_OFFSET 0x10
-#define IXP425_GPIO_GPIT2R_OFFSET 0x14
-#define IXP425_GPIO_GPCLKR_OFFSET 0x18
-#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C
-
-/*
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
-
-#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
-#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
-#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
-#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
-#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
-#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
-#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
-#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
-
-#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \
- IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R)
-
-/*
- * Macros to make it easy to access the GPIO registers
- */
-#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line))
-#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line))
-#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line))
-#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line) \
- *IXP425_GPIO_GPITR(line) = \
- (*IXP425_GPIO_GPITR(line) & \
- ~(0x7 << (((line) & 0x7) * 3))) | \
- (0x1 << (((line) & 0x7) * 3)) \
-
-/*
- * Constants to make it easy to access Timer Control/Status registers
- */
-#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */
-#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
-#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
-#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
-#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
-#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */
-#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */
-#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */
-#define IXP425_OSST_OFFSET 0x20 /* Timer Status */
-
-/*
- * Operating System Timer Register Definitions.
- */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
-
-/* _B to avoid collision: also defined in npe/include/... */
-#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
-#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET)
-#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
-#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET)
-#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
-#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
-#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
-#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
-#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET)
-
-/*
- * Timer register values and bit definitions
- */
-#define IXP425_OST_ENABLE BIT(0)
-#define IXP425_OST_ONE_SHOT BIT(1)
-/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK (0x3)
-#define IXP425_OST_DISABLED (0x0)
-#define IXP425_OSST_TIMER_1_PEND BIT(0)
-#define IXP425_OSST_TIMER_2_PEND BIT(1)
-#define IXP425_OSST_TIMER_TS_PEND BIT(2)
-#define IXP425_OSST_TIMER_WDOG_PEND BIT(3)
-#define IXP425_OSST_TIMER_WARM_RESET BIT(4)
-
-/*
- * Constants to make it easy to access PCI Control/Status registers
- */
-#define PCI_NP_AD_OFFSET 0x00
-#define PCI_NP_CBE_OFFSET 0x04
-#define PCI_NP_WDATA_OFFSET 0x08
-#define PCI_NP_RDATA_OFFSET 0x0c
-#define PCI_CRP_AD_CBE_OFFSET 0x10
-#define PCI_CRP_WDATA_OFFSET 0x14
-#define PCI_CRP_RDATA_OFFSET 0x18
-#define PCI_CSR_OFFSET 0x1c
-#define PCI_ISR_OFFSET 0x20
-#define PCI_INTEN_OFFSET 0x24
-#define PCI_DMACTRL_OFFSET 0x28
-#define PCI_AHBMEMBASE_OFFSET 0x2c
-#define PCI_AHBIOBASE_OFFSET 0x30
-#define PCI_PCIMEMBASE_OFFSET 0x34
-#define PCI_AHBDOORBELL_OFFSET 0x38
-#define PCI_PCIDOORBELL_OFFSET 0x3C
-#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
-#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
-#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
-#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
-#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
-
-/*
- * PCI Control/Status Registers
- */
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
-
-#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
-#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
-#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
-#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
-#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
-#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
-#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET)
-#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET)
-#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET)
-#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
-#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
-#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
-#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
-#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
-#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
-#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
-#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
-#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
-#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
-#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
-#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
-
-/*
- * PCI register values and bit definitions
- */
-
-/* CSR bit definitions */
-#define PCI_CSR_HOST BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS BIT(2)
-#define PCI_CSR_PDS BIT(3)
-#define PCI_CSR_ABE BIT(4)
-#define PCI_CSR_DBT BIT(5)
-#define PCI_CSR_ASE BIT(8)
-#define PCI_CSR_IC BIT(15)
-
-/* ISR (Interrupt status) Register bit definitions */
-#define PCI_ISR_PSE BIT(0)
-#define PCI_ISR_PFE BIT(1)
-#define PCI_ISR_PPE BIT(2)
-#define PCI_ISR_AHBE BIT(3)
-#define PCI_ISR_APDC BIT(4)
-#define PCI_ISR_PADC BIT(5)
-#define PCI_ISR_ADB BIT(6)
-#define PCI_ISR_PDB BIT(7)
-
-/* INTEN (Interrupt Enable) Register bit definitions */
-#define PCI_INTEN_PSE BIT(0)
-#define PCI_INTEN_PFE BIT(1)
-#define PCI_INTEN_PPE BIT(2)
-#define PCI_INTEN_AHBE BIT(3)
-#define PCI_INTEN_APDC BIT(4)
-#define PCI_INTEN_PADC BIT(5)
-#define PCI_INTEN_ADB BIT(6)
-#define PCI_INTEN_PDB BIT(7)
-
-/*
- * Shift value for byte enable on NP cmd/byte enable register
- */
-#define IXP425_PCI_NP_CBE_BESL 4
-
-/*
- * PCI commands supported by NP access unit
- */
-#define NP_CMD_IOREAD 0x2
-#define NP_CMD_IOWRITE 0x3
-#define NP_CMD_CONFIGREAD 0xa
-#define NP_CMD_CONFIGWRITE 0xb
-#define NP_CMD_MEMREAD 0x6
-#define NP_CMD_MEMWRITE 0x7
-
-#if 0
-#ifndef __ASSEMBLY__
-extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data);
-extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
-extern void ixp425_pci_init(void *);
-#endif
-#endif
-
-/*
- * Constants for CRP access into local config space
- */
-#define CRP_AD_CBE_BESL 20
-#define CRP_AD_CBE_WRITE BIT(16)
-
-/*
- * Clock Speed Definitions.
- */
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
-
-
-#endif
diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h
deleted file mode 100644
index f499883936..0000000000
--- a/arch/arm/include/asm/arch-ixp/ixp425pci.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * IXP PCI Init
- * (C) Copyright 2004 eslab.whut.edu.cn
- * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _IXP425PCI_H
-#define _IXP425PCI_H
-
-#define OK 0
-#define ERROR -1
-
-struct pci_controller;
-extern void pci_ixp_init(struct pci_controller *hose);
-
-/* Mask definitions*/
-#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
-
-#define PCI_NP_CBE_BESL (4)
-#define PCI_NP_AD_FUNCSL (8)
-
-/*Register addressing definitions for PCI controller configuration
- and status registers*/
-
-#define PCI_CSR_BASE (0xC0000000)
-/*
-#define PCI_NP_AD_OFFSET (0x00)
-#define PCI_NP_CBE_OFFSET (0x04)
-#define PCI_NP_WDATA_OFFSET (0x08)
-#define PCI_NP_RDATA_OFFSET (0x0C)
-#define PCI_CRP_OFFSET (0x10)
-#define PCI_CRP_WDATA_OFFSET (0x14)
-#define PCI_CRP_RDATA_OFFSET (0x18)
-#define PCI_CSR_OFFSET (0x1C)
-#define PCI_ISR_OFFSET (0x20)
-#define PCI_INTEN_OFFSET (0x24)
-#define PCI_DMACTRL_OFFSET (0x28)
-#define PCI_AHBMEMBASE_OFFSET (0x2C)
-#define PCI_AHBIOBASE_OFFSET (0x30)
-#define PCI_PCIMEMBASE_OFFSET (0x34)
-#define PCI_AHBDOORBELL_OFFSET (0x38)
-#define PCI_PCIDOORBELL_OFFSET (0x3C)
-#define PCI_ATPDMA0_AHBADDR (0x40)
-#define PCI_ATPDMA0_PCIADDR (0x44)
-#define PCI_ATPDMA0_LENADDR (0x48)
-#define PCI_ATPDMA1_AHBADDR (0x4C)
-#define PCI_ATPDMA1_PCIADDR (0x50)
-#define PCI_ATPDMA1_LENADDR (0x54)
-#define PCI_PTADMA0_AHBADDR (0x58)
-#define PCI_PTADMA0_PCIADDR (0x5C)
-#define PCI_PTADMA0_LENADDR (0x60)
-#define PCI_PTADMA1_AHBADDR (0x64)
-#define PCI_PTADMA1_PCIADDR (0x68)
-#define PCI_PTADMA1_LENADDR (0x6C)
-*/
-/*Non prefetch registers bit definitions*/
-/*
-#define NP_CMD_INTACK (0x0)
-#define NP_CMD_SPECIAL (0x1)
-#define NP_CMD_IOREAD (0x2)
-#define NP_CMD_IOWRITE (0x3)
-#define NP_CMD_MEMREAD (0x6)
-#define NP_CMD_MEMWRITE (0x7)
-#define NP_CMD_CONFIGREAD (0xa)
-#define NP_CMD_CONFIGWRITE (0xb)
-*/
-
-/*Configuration Port register bit definitions*/
-#define PCI_CRP_WRITE BIT(16)
-
-/*ISR (Interrupt status) Register bit definitions*/
-#define PCI_ISR_PSE BIT(0)
-#define PCI_ISR_PFE BIT(1)
-#define PCI_ISR_PPE BIT(2)
-#define PCI_ISR_AHBE BIT(3)
-#define PCI_ISR_APDC BIT(4)
-#define PCI_ISR_PADC BIT(5)
-#define PCI_ISR_ADB BIT(6)
-#define PCI_ISR_PDB BIT(7)
-
-/*INTEN (Interrupt Enable) Register bit definitions*/
-#define PCI_INTEN_PSE BIT(0)
-#define PCI_INTEN_PFE BIT(1)
-#define PCI_INTEN_PPE BIT(2)
-#define PCI_INTEN_AHBE BIT(3)
-#define PCI_INTEN_APDC BIT(4)
-#define PCI_INTEN_PADC BIT(5)
-#define PCI_INTEN_ADB BIT(6)
-#define PCI_INTEN_PDB BIT(7)
-
-/*PCI configuration regs.*/
-
-#define PCI_CFG_VENDOR_ID 0x00
-#define PCI_CFG_DEVICE_ID 0x02
-#define PCI_CFG_COMMAND 0x04
-#define PCI_CFG_STATUS 0x06
-#define PCI_CFG_REVISION 0x08
-#define PCI_CFG_PROGRAMMING_IF 0x09
-#define PCI_CFG_SUBCLASS 0x0a
-#define PCI_CFG_CLASS 0x0b
-#define PCI_CFG_CACHE_LINE_SIZE 0x0c
-#define PCI_CFG_LATENCY_TIMER 0x0d
-#define PCI_CFG_HEADER_TYPE 0x0e
-#define PCI_CFG_BIST 0x0f
-#define PCI_CFG_BASE_ADDRESS_0 0x10
-#define PCI_CFG_BASE_ADDRESS_1 0x14
-#define PCI_CFG_BASE_ADDRESS_2 0x18
-#define PCI_CFG_BASE_ADDRESS_3 0x1c
-#define PCI_CFG_BASE_ADDRESS_4 0x20
-#define PCI_CFG_BASE_ADDRESS_5 0x24
-#define PCI_CFG_CIS 0x28
-#define PCI_CFG_SUB_VENDOR_ID 0x2c
-#define PCI_CFG_SUB_SYSTEM_ID 0x2e
-#define PCI_CFG_EXPANSION_ROM 0x30
-#define PCI_CFG_RESERVED_0 0x34
-#define PCI_CFG_RESERVED_1 0x38
-#define PCI_CFG_DEV_INT_LINE 0x3c
-#define PCI_CFG_DEV_INT_PIN 0x3d
-#define PCI_CFG_MIN_GRANT 0x3e
-#define PCI_CFG_MAX_LATENCY 0x3f
-#define PCI_CFG_SPECIAL_USE 0x41
-#define PCI_CFG_MODE 0x43
-
-#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
-#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
-#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
-#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
-#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
-#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
-#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
-#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
-#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
-#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
-
-
-/*CSR Register bit definitions*/
-#define PCI_CSR_HOST BIT(0)
-#define PCI_CSR_ARBEN BIT(1)
-#define PCI_CSR_ADS BIT(2)
-#define PCI_CSR_PDS BIT(3)
-#define PCI_CSR_ABE BIT(4)
-#define PCI_CSR_DBT BIT(5)
-#define PCI_CSR_ASE BIT(8)
-#define PCI_CSR_IC BIT(15)
-
-/*Configuration command bit definitions*/
-#define PCI_CFG_CMD_IOAE BIT(0)
-#define PCI_CFG_CMD_MAE BIT(1)
-#define PCI_CFG_CMD_BME BIT(2)
-#define PCI_CFG_CMD_MWIE BIT(4)
-#define PCI_CFG_CMD_SER BIT(8)
-#define PCI_CFG_CMD_FBBE BIT(9)
-#define PCI_CFG_CMD_MDPE BIT(24)
-#define PCI_CFG_CMD_STA BIT(27)
-#define PCI_CFG_CMD_RTA BIT(28)
-#define PCI_CFG_CMD_RMA BIT(29)
-#define PCI_CFG_CMD_SSE BIT(30)
-#define PCI_CFG_CMD_DPE BIT(31)
-
-/*DMACTRL DMA Control and status Register*/
-#define PCI_DMACTRL_APDCEN BIT(0)
-#define PCI_DMACTRL_APDC0 BIT(4)
-#define PCI_DMACTRL_APDE0 BIT(5)
-#define PCI_DMACTRL_APDC1 BIT(6)
-#define PCI_DMACTRL_APDE1 BIT(7)
-#define PCI_DMACTRL_PADCEN BIT(8)
-#define PCI_DMACTRL_PADC0 BIT(12)
-#define PCI_DMACTRL_PADE0 BIT(13)
-#define PCI_DMACTRL_PADC1 BIT(14)
-#define PCI_DMACTRL_PADE1 BIT(15)
-
-#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 60e872637f..63e4ad5a67 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -32,9 +32,6 @@ struct arch_global_data {
unsigned long tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#ifdef CONFIG_IXP425
- unsigned long timestamp;
-#endif
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
diff --git a/board/actux1/Makefile b/board/actux1/Makefile
deleted file mode 100644
index 05a8669113..0000000000
--- a/board/actux1/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux1.o
diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c
deleted file mode 100644
index 03ccd936b4..0000000000
--- a/board/actux1/actux1.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux1_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS5: Debug port */
- writel(0x9d520003, IXP425_EXP_CS5);
- /* CS6: HwRel */
- writel(0x81860001, IXP425_EXP_CS6);
- /* CS7: LEDs */
- writel(0x80900003, IXP425_EXP_CS7);
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
- /* Setup GPIOs for PCI INTA */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
-
- /* Setup GPIOs for 33MHz clock output */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
- ACTUX1_LED1(2);
- ACTUX1_LED2(2);
- ACTUX1_LED3(0);
- ACTUX1_LED4(0);
- ACTUX1_LED5(0);
- ACTUX1_LED6(0);
- ACTUX1_LED7(0);
-
- ACTUX1_HS(ACTUX1_HS_DCD);
-
- return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: AcTux-1 rev.");
- putc(ACTUX1_BOARDREL + 'A' - 1);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
- return ACTUX1_BOARDREL;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
- u16 id1, id2;
-
- /* initialize the PHY */
- miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
- miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
- miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
-
- id2 &= 0xFFF0; /* mask out revision bits */
-
- if (id1 == 0x13 && id2 == 0x78e0) {
- /*
- * LXT971/LXT972 PHY: set LED outputs:
- * LED1(green) = Link/ACT,
- * LED2 (unused) = LINK,
- * LED3(red) = Coll
- */
- miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
- } else if (id1 == 0x143 && id2 == 0xbc30) {
- /* BCM5241: default values are OK */
- } else
- printf("unknown ethernet PHY ID: %x %x\n", id1, id2);
-}
diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h
deleted file mode 100644
index 5627f24796..0000000000
--- a/board/actux1/actux1_hw.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-1 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX1_HW_H
-#define _ACTUX1_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-#define ACTUX1_HS_DCD 0x01
-#define ACTUX1_HS_DSR 0x02
-
-#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_PCI1_INTA 2
-#define CONFIG_SYS_GPIO_PCI2_INTA 3
-#define CONFIG_SYS_GPIO_I2C_SDA 4
-#define CONFIG_SYS_GPIO_I2C_SCL 5
-#define CONFIG_SYS_GPIO_DBGJUMPER 9
-#define CONFIG_SYS_GPIO_BUTTON1 10
-#define CONFIG_SYS_GPIO_DBGSENSE 11
-#define CONFIG_SYS_GPIO_DTR 12
-#define CONFIG_SYS_GPIO_IORST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
deleted file mode 100644
index 4716e4f0e0..0000000000
--- a/board/actux1/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/actux1/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/input/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
- . = ALIGN(4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/actux2/Makefile b/board/actux2/Makefile
deleted file mode 100644
index 24cbff1b47..0000000000
--- a/board/actux2/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux2.o
diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c
deleted file mode 100644
index e578cd0996..0000000000
--- a/board/actux2/actux2.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-
-#include <miiphy.h>
-
-#include "actux2_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS1: IPAC-X */
- writel(0x94d10013, IXP425_EXP_CS1);
- /* CS5: Debug port */
- writel(0x9d520003, IXP425_EXP_CS5);
- /* CS6: HW release register */
- writel(0x81860001, IXP425_EXP_CS6);
- /* CS7: LEDs */
- writel(0x80900003, IXP425_EXP_CS7);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
- /* Setup GPIOs for Interrupt inputs */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
- /* Setup GPIOs for 33MHz clock output */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
- ACTUX2_LED1(1);
- ACTUX2_LED2(0);
- ACTUX2_LED3(0);
- ACTUX2_LED4(0);
-
- return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: AcTux-2 rev.");
- putc(ACTUX2_BOARDREL + 'A' - 1);
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
- return ACTUX2_BOARDREL;
-}
-
-void reset_phy(void)
-{
- /* init IcPlus IP175C ethernet switch to native IP175C mode */
- miiphy_write("NPE0", 29, 31, 0x175C);
-}
diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h
deleted file mode 100644
index 57c6fa7076..0000000000
--- a/board/actux2/actux2_hw.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-2 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX2_HW_H
-#define _ACTUX2_HW_H
-
-/* 0 = LED off,1 = green, 2 = red, 3 = orange */
-#define ACTUX2_LED1(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX2_LED2(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX2_LED3(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX2_LED4(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-
-#define ACTUX2_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX2_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX2_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_DBGINT 0
-#define CONFIG_SYS_GPIO_ETHINT 1
-#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
-#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
-#define CONFIG_SYS_GPIO_UNUSED4 4
-#define CONFIG_SYS_GPIO_UNUSED5 5
-#define CONFIG_SYS_GPIO_DSR 6 /* Out */
-#define CONFIG_SYS_GPIO_DCD 7 /* Out */
-#define CONFIG_SYS_GPIO_IPAC_INT 8
-#define CONFIG_SYS_GPIO_DBGJUMPER 9
-#define CONFIG_SYS_GPIO_BUTTON1 10
-#define CONFIG_SYS_GPIO_DBGSENSE 11
-#define CONFIG_SYS_GPIO_DTR 12
-#define CONFIG_SYS_GPIO_IORST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
deleted file mode 100644
index f00d7c72b1..0000000000
--- a/board/actux2/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/actux2/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/input/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
- . = ALIGN(4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/actux3/Makefile b/board/actux3/Makefile
deleted file mode 100644
index f628f26449..0000000000
--- a/board/actux3/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux3.o
diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c
deleted file mode 100644
index 09c803ccd4..0000000000
--- a/board/actux3/actux3.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include "actux3_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS1: IPAC-X */
- writel(0x94d10013, IXP425_EXP_CS1);
- /* CS5: Debug port */
- writel(0x9d520003, IXP425_EXP_CS5);
- /* CS6: Release/Option register */
- writel(0x81860001, IXP425_EXP_CS6);
- /* CS7: LEDs */
- writel(0x80900003, IXP425_EXP_CS7);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
-
- /*
- * Setup GPIO's for Interrupt inputs
- */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
-
- /*
- * Setup GPIO's for 33MHz clock output
- */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
-
- /* we need a minimum PCI reset pulse width after enabling the clock */
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
-
- ACTUX3_LED1_RT(1);
- ACTUX3_LED1_GN(0);
- ACTUX3_LED2_RT(0);
- ACTUX3_LED2_GN(0);
- ACTUX3_LED3_RT(0);
- ACTUX3_LED3_GN(0);
- ACTUX3_LED4_GN(0);
- ACTUX3_LED5_RT(0);
-
- return 0;
-}
-
-/*
- * Check Board Identity
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-
- puts("Board: AcTux-3 rev.");
- putc(ACTUX3_BOARDREL + 'A' - 1);
-
- if (i > 0) {
- puts (", serial# ");
- puts (buf);
- }
- putc('\n');
-
- return 0;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * 0 = reserved
- * 1 = Rev. A
- * 2 = Rev. B
- *************************************************************************/
-u32 get_board_rev(void)
-{
- return ACTUX3_BOARDREL;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-void reset_phy(void)
-{
- int i;
-
- /* initialize the PHY */
- miiphy_reset("NPE0", CONFIG_PHY_ADDR);
-
- /* all LED outputs = Link/Act */
- miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
-
- /*
- * The Marvell 88E6060 switch comes up with all ports disabled.
- * set all ethernet switch ports to forwarding state
- */
- for (i = 1; i <= 5; i++)
- miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);
-
-}
diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h
deleted file mode 100644
index f8acb4d060..0000000000
--- a/board/actux3/actux3_hw.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-3 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX3_HW_H
-#define _ACTUX3_HW_H
-
-/* 0 = LED off,1 = ON */
-#define ACTUX3_LED1_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
-#define ACTUX3_LED1_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
-#define ACTUX3_LED2_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
-#define ACTUX3_LED2_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
-#define ACTUX3_LED3_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4)
-#define ACTUX3_LED3_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5)
-#define ACTUX3_LED4_GN(a) writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6)
-#define ACTUX3_LED5_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7)
-
-#define ACTUX3_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS
-#define ACTUX3_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
-#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
-
-/* GPIO settings */
-#define CONFIG_SYS_GPIO_DBGINT 0
-#define CONFIG_SYS_GPIO_ETHINT 1
-#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */
-#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */
-#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */
-#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */
-#define CONFIG_SYS_GPIO_DSR 6 /* Out */
-#define CONFIG_SYS_GPIO_DCD 7 /* Out */
-#define CONFIG_SYS_GPIO_DBGJUMPER 9
-#define CONFIG_SYS_GPIO_BUTTON1 10
-#define CONFIG_SYS_GPIO_DBGSENSE 11
-#define CONFIG_SYS_GPIO_DTR 12
-#define CONFIG_SYS_GPIO_IORST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
deleted file mode 100644
index 2de3ca60b5..0000000000
--- a/board/actux3/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/actux3/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/input/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
- . = ALIGN(4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/actux4/Makefile b/board/actux4/Makefile
deleted file mode 100644
index b949b608c6..0000000000
--- a/board/actux4/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := actux4.o
diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c
deleted file mode 100644
index 81c545884e..0000000000
--- a/board/actux4/actux4.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "actux4_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- writel(0xbd113c42, IXP425_EXP_CS1);
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
-
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
-
- /* led not populated on board*/
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
-
- /* middle LED */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
-
- /* right LED */
- /* weak pulldown = LED weak on */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
-
- /* Setup GPIO's for Interrupt inputs */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
-
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
- GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
-
- /* Setup GPIO's for 33MHz clock output */
- writel(0x011001FF, IXP425_GPIO_GPCLKR);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
-
- udelay(10000);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
- udelay(10000);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
- udelay(10000);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
-
- return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
- puts("Board: AcTux-4\n");
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_ixp_init(&hose);
-}
-#endif
-
-/*
- * Hardcoded flash setup:
- * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
- * Flash 1 is an Intel *16 flash using the CFI driver.
- */
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = 1;
- info->chipwidth = 1;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else
- return 0;
-}
diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h
deleted file mode 100644
index b936376de9..0000000000
--- a/board/actux4/actux4_hw.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2007
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the AcTux-4 board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ACTUX4_HW_H
-#define _ACTUX4_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_USBINTA 0
-#define CONFIG_SYS_GPIO_USBINTB 1
-#define CONFIG_SYS_GPIO_USBINTC 2
-#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */
-#define CONFIG_SYS_GPIO_I2C_SCL 4
-#define CONFIG_SYS_GPIO_I2C_SDA 5
-#define CONFIG_SYS_GPIO_PCI_INTB 6
-#define CONFIG_SYS_GPIO_BUTTON1 7
-#define CONFIG_SYS_GPIO_LED1 8 /* Out */
-#define CONFIG_SYS_GPIO_RTCINT 9
-#define CONFIG_SYS_GPIO_LED2 10 /* Out */
-#define CONFIG_SYS_GPIO_PCI_INTA 11
-#define CONFIG_SYS_GPIO_IORST 12 /* Out */
-#define CONFIG_SYS_GPIO_LED3 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#endif
diff --git a/board/dvlhost/Makefile b/board/dvlhost/Makefile
deleted file mode 100644
index 8b489362ce..0000000000
--- a/board/dvlhost/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := dvlhost.o watchdog.o
diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c
deleted file mode 100644
index 087070f40d..0000000000
--- a/board/dvlhost/dvlhost.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <malloc.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#include <asm/arch/ixp425pci.h>
-#endif
-
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* CS1: LED Latch */
- writel(0xBFFF0002, IXP425_EXP_CS1);
- return 0;
-}
-
-int board_init(void)
-{
- /* adress of boot parameters */
- gd->bd->bi_boot_params = 0x00000100;
-
- /* Setup GPIOs used as output */
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDGTRIGGER);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DLAN_PAIRING);
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PCIRST);
-
- /*
- * LED latch enable and watchdog enable are tied to the same GPIO,
- * so we need to trigger the watchdog if we want to enable the LEDs.
- */
-#ifdef CONFIG_HW_WATCHDOG
- GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_WDG_LED_EN);
-#else
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_WDG_LED_EN);
-#endif
-
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDGTRIGGER);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DLAN_PAIRING);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_WDG_LED_EN);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCIRST);
-
- /* Setup GPIOs for Interrupt inputs */
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_WLAN);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_PAIRING);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_BTN_RESET);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQA);
- GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_IRQB);
-
- /* Setup GPIO's for 33MHz clock output */
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
- GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
- writel(0x01FF01FF, IXP425_GPIO_GPCLKR);
-
- /* turn off all LEDs */
- writew(0x0000, DVLHOST_LED_LATCH);
-
- udelay(533);
- GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_PCIRST);
-
- return 0;
-}
-
-/* Check Board Identity */
-int checkboard(void)
-{
- char *s = getenv("serial#");
-
- puts("Board: dLAN 200AV (dvlhost)");
-
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
- putc('\n');
-
- return 0;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_ixp_init(&hose);
-}
-#endif
-
-void reset_phy(void)
-{
- /* init IcPlus IP175C ethernet switch to native IP175C mode */
- miiphy_write("NPE1", 29, 31, 0x175C);
-}
diff --git a/board/dvlhost/dvlhost_hw.h b/board/dvlhost/dvlhost_hw.h
deleted file mode 100644
index 545099e9ea..0000000000
--- a/board/dvlhost/dvlhost_hw.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * hardware register definitions for the
- * dLAN200 AV Wireless G ("dvlhost") board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DVLHOST_HW_H
-#define _DVLHOST_HW_H
-
-/*
- * GPIO settings
- */
-#define CONFIG_SYS_GPIO_WDGTRIGGER 0 /* Out */
-#define CONFIG_SYS_GPIO_BTN_WLAN 1
-#define CONFIG_SYS_GPIO_BTN_PAIRING 6
-#define CONFIG_SYS_GPIO_DLAN_PAIRING 7 /* Out */
-#define CONFIG_SYS_GPIO_BTN_RESET 9
-#define CONFIG_SYS_GPIO_IRQB 10
-#define CONFIG_SYS_GPIO_IRQA 11
-#define CONFIG_SYS_GPIO_WDG_LED_EN 12 /* Out */
-#define CONFIG_SYS_GPIO_PCIRST 13 /* Out */
-#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
-#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
-
-#define DVLHOST_LED_LATCH IXP425_EXP_BUS_CS1_BASE_PHYS
-
-#endif
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
deleted file mode 100644
index ebcaf447b8..0000000000
--- a/board/dvlhost/u-boot.lds
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
-OUTPUT_ARCH (arm)
-ENTRY (_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN (4);
- .text : {
- *(.__image_copy_start)
- arch/arm/cpu/ixp/start.o(.text*)
- net/built-in.o(.text*)
- board/dvlhost/built-in.o(.text*)
- arch/arm/cpu/ixp/built-in.o(.text*)
- drivers/serial/built-in.o(.text*)
-
- . = env_offset;
- common/env_embedded.o(.ppcenv)
- *(.text*)
- }
-
- . = ALIGN (4);
- .rodata : {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
- . = ALIGN (4);
- .data : {
- *(.data*)
- }
- . = ALIGN (4);
- .got : {
- *(.got)
- }
- . =.;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN (4);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rel.dyn : {
- *(.rel*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- .dynsym _end : { *(.dynsym) }
- .dynbss : { *(.dynbss) }
- .dynstr : { *(.dynstr*) }
- .dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
- .plt : { *(.plt*) }
- .interp : { *(.interp*) }
- .gnu : { *(.gnu*) }
- .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/board/dvlhost/watchdog.c b/board/dvlhost/watchdog.c
deleted file mode 100644
index 02ec35eb1a..0000000000
--- a/board/dvlhost/watchdog.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2009
- * Michael Schwingen, michael@schwingen.org
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include "dvlhost_hw.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#include <asm/arch/ixp425.h>
-
-void hw_watchdog_reset(void)
-{
- unsigned int x;
- x = readl(IXP425_GPIO_GPOUTR);
- x ^= (1 << (CONFIG_SYS_GPIO_WDGTRIGGER));
- writel(x, IXP425_GPIO_GPOUTR);
-}
-
-#endif /* CONFIG_HW_WATCHDOG */
diff --git a/boards.cfg b/boards.cfg
index 7a8688a627..0e663d93a2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -379,14 +379,6 @@ Active arm armv7:arm720t tegra20 toradex colibri_t20_iris
Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
-Active arm ixp - - - actux2 - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - - actux3 - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - - actux4 - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - - dvlhost - Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_4_16 actux1:FLASH2X2 Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael@schwingen.org>
-Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael@schwingen.org>
Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 2aed855993..6b41445faa 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,6 +11,11 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+dvl_host arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux4 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux3 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux2 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
+actux1 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
mx1ads arm arm920t - 2014-01-13
mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
omap730p2 arm arm926ejs 79c5c08d 2013-11-11
diff --git a/doc/driver-model/UDM-pci.txt b/doc/driver-model/UDM-pci.txt
index 059a4329fb..1dce99de3d 100644
--- a/doc/driver-model/UDM-pci.txt
+++ b/doc/driver-model/UDM-pci.txt
@@ -125,10 +125,6 @@ III) Analysis of in-tree drivers
Shared driver for indirect PCI bridges, several CONFIG macros - will
require significant cleanup.
- pci_ixp.c
- ---------
- Standard driver, specifies all read/write functions separately.
-
pci_sh4.c
---------
Shared init function for SH4 drivers, uses dword for read/write ops.
diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt
index 279e941fc0..ed804a8e7e 100644
--- a/doc/driver-model/UDM-serial.txt
+++ b/doc/driver-model/UDM-serial.txt
@@ -101,10 +101,6 @@ III) Analysis of in-tree drivers
No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver
might be removed in favor of serial_mxc.c .
- serial_ixp.c
- ------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
serial_ks8695.c
---------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index dfea54ae73..db9b4026b3 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -29,9 +29,6 @@
#include <asm/arch/gpio.h>
#endif
#endif
-#ifdef CONFIG_IXP425 /* only valid for IXP425 */
-#include <asm/arch/ixp425.h>
-#endif
#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
#include <asm/io.h>
#endif
diff --git a/drivers/net/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c
deleted file mode 100644
index 05a9e053ff..0000000000
--- a/drivers/net/npe/IxEthAcc.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/**
- * @file IxEthAcc.c
- *
- * @author Intel Corporation
- * @date 20-Feb-2001
- *
- * @brief This file contains the implementation of the IXP425 Ethernet Access Component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-
-#include "IxEthAcc.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxFeatureCtrl.h"
-
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAcc
- *@{
- */
-
-
-/**
- * @brief System-wide information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccInfo ixEthAccDataInfo;
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-/**
- * @brief System-wide information
- *
- * @ingroup IxEthAccPri
- *
- */
-BOOL ixEthAccServiceInit = false;
-
-/* global filtering bit mask */
-PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * @brief Per port information data strucure.
- *
- * @ingroup IxEthAccPri
- *
- */
-
-IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PUBLIC IxEthAccStatus ixEthAccInit()
-{
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /*
- * Initialize Control plane
- */
- if (ixEthDBInit() != IX_ETH_DB_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
- ixEthAccNewSrcMask = (~0); /* want all the bits */
- }
- else
- {
- ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */
- }
-
- /*
- * Initialize Data plane
- */
- if ( ixEthAccInitDataPlane() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
-
- if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize MII
- */
- if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS )
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize MAC I/O memory
- */
- if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Initialize control plane interface lock
- */
- if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* initialiasation is complete */
- ixEthAccServiceInit = true;
-
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-PUBLIC void ixEthAccUnload(void)
-{
- IxEthAccPortId portId;
-
- if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
- {
- /* check none of the port is still active */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
- {
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0);
- return;
- }
- }
- }
-
- /* unmap the memory areas */
- ixEthAccMiiUnload();
- ixEthAccMacUnload();
-
- /* set all ports as uninitialized */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- ixEthAccPortData[portId].portInitialized = false;
- }
-
- /* uninitialize the service */
- ixEthAccServiceInit = false;
- }
-}
-
-PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
-{
-
- IxEthAccStatus ret=IX_ETH_ACC_SUCCESS;
-
- if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
- {
- return(IX_ETH_ACC_FAIL);
- }
-
- /*
- * Check for valid port
- */
-
- if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) )
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
- {
- /* Already initialized */
- return(IX_ETH_ACC_FAIL);
- }
-
- if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set the port init flag.
- */
-
- ixEthAccPortData[portId].portInitialized = true;
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* init learning/filtering database structures for this port */
- ixEthDBPortInit(portId);
-#endif
-
- return(ret);
-}
-
-
diff --git a/drivers/net/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c
deleted file mode 100644
index 8249737b0c..0000000000
--- a/drivers/net/npe/IxEthAccCommon.c
+++ /dev/null
@@ -1,1025 +0,0 @@
-/**
- * @file IxEthAccCommon.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation common support routines for the component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-/*
- * Component header files
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxNpeMh.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAccMii_p.h"
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-extern IxEthAccInfo ixEthAccDataInfo;
-
-/**
- *
- * @brief Maximum number of RX queues set to be the maximum number
- * of traffic calsses.
- *
- */
-#define IX_ETHACC_MAX_RX_QUEUES \
- (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \
- - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \
- + 1)
-
-/**
- *
- * @brief Maximum number of 128 entry RX queues
- *
- */
-#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4
-
-/**
- *
- * @brief Data structure template for Default RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
- {
- IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */
- "Eth Rx Q",
- ixEthRxFrameQMCallback, /**< Functional callback */
- (IxQMgrCallbackId) 0, /**< Callback tag */
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- true, /**< Enable Q notification at startup */
- IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
- };
-
-/**
- *
- * @brief Data structure template for Small RX Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
- {
- IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */
- "Eth Rx Q",
- ixEthRxFrameQMCallback, /**< Functional callback */
- (IxQMgrCallbackId) 0, /**< Callback tag */
- IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- true, /**< Enable Q notification at startup */
- IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */
- };
-
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
-{
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q,
- "Eth Rx Fr Q 1",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_1,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q,
- "Eth Rx Fr Q 2",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_2,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#ifdef __ixp46X
- {
- IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q,
- "Eth Rx Fr Q 3",
- ixEthRxFreeQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_3,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#endif
- {
- IX_ETH_ACC_TX_FRAME_ENET0_Q,
- "Eth Tx Q 1",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_1,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-
- {
- IX_ETH_ACC_TX_FRAME_ENET1_Q,
- "Eth Tx Q 2",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_2,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- false, /**< Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */
- },
-#ifdef __ixp46X
- {
- IX_ETH_ACC_TX_FRAME_ENET2_Q,
- "Eth Tx Q 3",
- ixEthTxFrameQMCallback,
- (IxQMgrCallbackId) IX_ETH_PORT_3,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */
- false, /** Disable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */
- IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */
- },
-#endif
- {
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
- "Eth Tx Done Q",
- ixEthTxFrameDoneQMCallback,
- (IxQMgrCallbackId) 0,
- IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */
- IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */
- true, /**< Enable Q notification at startup */
- IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */
- IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */
- IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */
- },
-
- { /* Null Termination entry
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- }
-
-};
-
-/**
- *
- * @brief Data structure used to register & initialize the Queues
- *
- * The structure will be filled at run time depending on the NPE
- * image already loaded and the QoS configured in ethDB.
- *
- */
-IX_ETH_ACC_PRIVATE
-IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]=
-{
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* PlaceHolder for rx queues
- * depending on the QoS configured
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- },
-
- { /* Null Termination entry
- */
- (IxQMgrQId)0,
- (char *) NULL,
- (IxQMgrCallback) NULL,
- (IxQMgrCallbackId) 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- }
-
-};
-
-/* forward declarations */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes);
-
-/**
- * @fn ixEthAccQMgrQueueSetup(void)
- *
- * @brief Setup one queue and its event, and register the callback required
- * by this component to the QMgr
- *
- * @internal
- */
-IX_ETH_ACC_PRIVATE IxEthAccStatus
-ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes)
-{
- /*
- * Configure each Q.
- */
- if ( ixQMgrQConfig( qInfoDes->qName,
- qInfoDes->qId,
- qInfoDes->qSize,
- qInfoDes->qWords) != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- if ( ixQMgrWatermarkSet( qInfoDes->qId,
- qInfoDes->AlmostEmptyThreshold,
- qInfoDes->AlmostFullThreshold
- ) != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set dispatcher priority.
- */
- if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId,
- IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY)
- != IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Register callbacks for each Q.
- */
- if ( ixQMgrNotificationCallbackSet(qInfoDes->qId,
- qInfoDes->qCallback,
- qInfoDes->callbackTag)
- != IX_SUCCESS )
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*
- * Set notification condition for Q
- */
- if (qInfoDes->qNotificationEnableAtStartup == true)
- {
- if ( ixQMgrNotificationEnable(qInfoDes->qId,
- qInfoDes->qConditionSource)
- != IX_SUCCESS )
- {
- return IX_ETH_ACC_FAIL;
- }
- }
-
- return(IX_ETH_ACC_SUCCESS);
-}
-
-/**
- * @fn ixEthAccQMgrQueuesConfig(void)
- *
- * @brief Setup all the queues and register all callbacks required
- * by this component to the QMgr
- *
- * The RxFree queues, tx queues, rx queues are configured statically
- *
- * Rx queues configuration is driven by QoS setup.
- * Many Rx queues may be required when QoS is enabled (this depends
- * on IxEthDB setup and the images being downloaded). The configuration
- * of the rxQueues is done in many steps as follows:
- *
- * @li select all Rx queues as configured by ethDB for all ports
- * @li sort the queues by traffic class
- * @li build the priority dependency for all queues
- * @li fill the configuration for all rx queues
- * @li configure all statically configured queues
- * @li configure all dynamically configured queues
- *
- * @param none
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrQueuesConfig(void)
-{
- struct
- {
- int npeCount;
- UINT32 npeId;
- IxQMgrQId qId;
- IxEthDBProperty trafficClass;
- } rxQueues[IX_ETHACC_MAX_RX_QUEUES];
-
- UINT32 rxQueue = 0;
- UINT32 rxQueueCount = 0;
- IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES;
- IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS;
- IxEthDBPortId ixEthDbPortId = 0;
- IxEthAccPortId ixEthAccPortId = 0;
- UINT32 ixNpeId = 0;
- UINT32 ixHighestNpeId = 0;
- UINT32 sortIterations = 0;
- IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
- IxEthAccQregInfo *qInfoDes = NULL;
- IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;
- UINT32 ixEthDBParameter = 0;
- BOOL completelySorted = false;
-
- /* Fill the corspondance between ports and queues
- * This defines the mapping from port to queue Ids.
- */
-
- ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q;
- ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue
- = IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q;
-#endif
- ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET0_Q;
- ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET1_Q;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue
- = IX_ETH_ACC_TX_FRAME_ENET2_Q;
-#endif
- /* Fill the corspondance between ports and NPEs
- * This defines the mapping from port to npeIds.
- */
-
- ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB;
- ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC;
-#ifdef __ixp46X
- ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA;
-#endif
- /* set the default rx scheduling discipline */
- ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY;
-
- /*
- * Queue Selection step:
- *
- * The following code selects all the queues and build
- * a temporary array which contains for each queue
- * - the queue Id,
- * - the highest traffic class (in case of many
- * priorities configured for the same queue on different
- * ports)
- * - the number of different Npes which are
- * configured to write to this queue.
- *
- * The output of this loop is a temporary array of RX queues
- * in any order.
- *
- */
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- for (ixEthAccPortId = 0;
- (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS)
- && (ret == IX_ETH_ACC_SUCCESS);
- ixEthAccPortId++)
- {
- /* map between ethDb and ethAcc port Ids */
- ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId;
-
- /* map between npeId and ethAcc port Ids */
- ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
-
- /* Iterate thru the different priorities */
- for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY;
- ixEthDBTrafficClass++)
- {
- ixEthDBStatus = ixEthDBFeaturePropertyGet(
- ixEthDbPortId,
- IX_ETH_DB_VLAN_QOS,
- ixEthDBTrafficClass,
- &ixEthDBPropertyType,
- (void *)&ixEthDBParameter);
-
- if (ixEthDBStatus == IX_ETH_DB_SUCCESS)
- {
- /* This port and QoS class are mapped to
- * a RX queue.
- */
- if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY)
- {
- /* remember the highest npe Id supporting ethernet */
- if (ixNpeId > ixHighestNpeId)
- {
- ixHighestNpeId = ixNpeId;
- }
-
- /* search the queue in the list of queues
- * already used by an other port or QoS
- */
- for (rxQueue = 0;
- rxQueue < rxQueueCount;
- rxQueue++)
- {
- if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter)
- {
- /* found an existing setup, update the number of ports
- * for this queue if the port maps to
- * a different NPE.
- */
- if (rxQueues[rxQueue].npeId != ixNpeId)
- {
- rxQueues[rxQueue].npeCount++;
- rxQueues[rxQueue].npeId = ixNpeId;
- }
- /* get the highest traffic class for this queue */
- if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass)
- {
- rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass;
- }
- break;
- }
- }
- if (rxQueue == rxQueueCount)
- {
- /* new queue not found in the current list,
- * add a new entry.
- */
- IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES);
- rxQueues[rxQueueCount].qId = ixEthDBParameter;
- rxQueues[rxQueueCount].npeCount = 1;
- rxQueues[rxQueueCount].npeId = ixNpeId;
- rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass;
- rxQueueCount++;
- }
- }
- else
- {
- /* unexpected property type (not Integer) */
- ret = IX_ETH_ACC_FAIL;
-
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0);
-
- /* no point to continue to iterate */
- break;
- }
- }
- else
- {
- /* No Rx queue configured for this port
- * and this traffic class. Do nothing.
- */
- }
- }
-
- /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */
- ixEthDBFeaturePropertySet(ixEthDbPortId,
- IX_ETH_DB_VLAN_QOS,
- IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE,
- NULL /* ignored */);
- }
-
-#else
-
- ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId);
- rxQueues[0].qId = 4;
- rxQueues[0].npeCount = 1;
- rxQueues[0].npeId = ixNpeId;
- rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
- rxQueueCount++;
-
-#endif
-
- /* check there is at least 1 rx queue : there is no point
- * to continue if there is no rx queue configured
- */
- if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- /* Queue sort step:
- *
- * Re-order the array of queues by decreasing traffic class
- * using a bubble sort. (trafficClass 0 is the lowest
- * priority traffic, trafficClass 7 is the highest priority traffic)
- *
- * Primary sort order is traffic class
- * Secondary sort order is npeId
- *
- * Note that a bubble sort algorithm is not very efficient when
- * the number of queues grows . However, this is not a very bad choice
- * considering the very small number of entries to sort. Also, bubble
- * sort is extremely fast when the list is already sorted.
- *
- * The output of this loop is a sorted array of queues.
- *
- */
- sortIterations = 0;
- do
- {
- sortIterations++;
- completelySorted = true;
- for (rxQueue = 0;
- rxQueue < rxQueueCount - sortIterations;
- rxQueue++)
- {
- /* compare adjacent elements */
- if ((rxQueues[rxQueue].trafficClass <
- rxQueues[rxQueue+1].trafficClass)
- || ((rxQueues[rxQueue].trafficClass ==
- rxQueues[rxQueue+1].trafficClass)
- &&(rxQueues[rxQueue].npeId <
- rxQueues[rxQueue+1].npeId)))
- {
- /* swap adjacent elements */
- int npeCount = rxQueues[rxQueue].npeCount;
- UINT32 npeId = rxQueues[rxQueue].npeId;
- IxQMgrQId qId = rxQueues[rxQueue].qId;
- IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass;
- rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount;
- rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId;
- rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId;
- rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass;
- rxQueues[rxQueue+1].npeCount = npeCount;
- rxQueues[rxQueue+1].npeId = npeId;
- rxQueues[rxQueue+1].qId = qId;
- rxQueues[rxQueue+1].trafficClass = trafficClass;
- completelySorted = false;
- }
- }
- }
- while (!completelySorted);
-
- /* Queue traffic class list:
- *
- * Fill an array of rx queues linked by ascending traffic classes.
- *
- * If the queues are configured as follows
- * qId 6 -> traffic class 0 (lowest)
- * qId 7 -> traffic class 0
- * qId 8 -> traffic class 6
- * qId 12 -> traffic class 7 (highest)
- *
- * Then the output of this loop will be
- *
- * higherPriorityQueue[6] = 8
- * higherPriorityQueue[7] = 8
- * higherPriorityQueue[8] = 12
- * higherPriorityQueue[12] = Invalid queueId
- * higherPriorityQueue[...] = Invalid queueId
- *
- * Note that this queue ordering does not handle all possibilities
- * that could result from different rules associated with different
- * ports, and inconsistencies in the rules. In all cases, the
- * output of this algorithm is a simple linked list of queues,
- * without closed circuit.
-
- * This list is implemented as an array with invalid values initialized
- * with an "invalid" queue id which is the maximum number of queues.
- *
- */
-
- /*
- * Initialise the rx queue list.
- */
- for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++)
- {
- ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES;
- }
-
- /* build the linked list for this NPE.
- */
- for (ixNpeId = 0;
- ixNpeId <= ixHighestNpeId;
- ixNpeId++)
- {
- /* iterate thru the sorted list of queues
- */
- ixQId = IX_QMGR_MAX_NUM_QUEUES;
- for (rxQueue = 0;
- rxQueue < rxQueueCount;
- rxQueue++)
- {
- if (rxQueues[rxQueue].npeId == ixNpeId)
- {
- ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
- /* iterate thru queues with the same traffic class
- * than the current queue. (queues are ordered by descending
- * traffic classes and npeIds).
- */
- while ((rxQueue < rxQueueCount - 1)
- && (rxQueues[rxQueue].trafficClass
- == rxQueues[rxQueue+1].trafficClass)
- && (ixNpeId == rxQueues[rxQueue].npeId))
- {
- rxQueue++;
- ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId;
- }
- ixQId = rxQueues[rxQueue].qId;
- }
- }
- }
-
- /* point on the first dynamic queue description */
- qInfoDes = ixEthAccQmgrRxQueuesInfo;
-
- /* update the list of queues with the rx queues */
- for (rxQueue = 0;
- (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS);
- rxQueue++)
- {
- /* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues
- * with the full 128 entries. For the lower priority queues, use
- * a smaller number of entries. This ensures queue resources
- * remain available for other components.
- */
- if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) &&
- (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) )
- {
- /* add the small RX Queue setup template to the list of queues */
- memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes));
- } else {
- /* add the default RX Queue setup template to the list of queues */
- memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes));
- }
-
- /* setup the RxQueue ID */
- qInfoDes->qId = rxQueues[rxQueue].qId;
-
- /* setup the RxQueue watermark level
- *
- * Each queue can be filled by many NPEs. To avoid the
- * NPEs to write to a full queue, need to set the
- * high watermark level for nearly full condition.
- * (the high watermark level are a power of 2
- * starting from the top of the queue)
- *
- * Number of watermark
- * ports level
- * 1 0
- * 2 1
- * 3 2
- * 4 4
- * 5 4
- * 6 8
- * n approx. 2**ceil(log2(n))
- */
- if (rxQueues[rxQueue].npeCount == 1)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0;
- }
- else if (rxQueues[rxQueue].npeCount == 2)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1;
- }
- else if (rxQueues[rxQueue].npeCount == 3)
- {
- qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2;
- }
- else
- {
- /* reach the maximum number for CSR 2.0 */
- IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0);
- ret = IX_ETH_ACC_FAIL;
- break;
- }
-
- /* move to next queue entry */
- ++qInfoDes;
- }
-
- /* configure the static list (RxFree, Tx and TxDone queues) */
- for (qInfoDes = ixEthAccQmgrStaticInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- ret = ixEthAccQMgrQueueSetup(qInfoDes);
- }
-
- /* configure the dynamic list (Rx queues) */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- ret = ixEthAccQMgrQueueSetup(qInfoDes);
- }
-
- return(ret);
-}
-
-/**
- * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries)
- *
- * @brief Add and return the total number of entries in all Rx queues
- *
- * @param UINT32 rxQueueEntries[in] number of entries in all queues
- *
- * @return void
- *
- * @note Rx queues configuration is driven by Qos Setup. There is a
- * variable number of rx queues which are set at initialisation.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries)
-{
- UINT32 rxQueueLevel;
- IxEthAccQregInfo *qInfoDes;;
-
- *numRxQueueEntries = 0;
-
- /* iterate thru rx queues */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- qInfoDes->qCallback != (IxQMgrCallback)NULL;
- ++qInfoDes)
- {
- /* retrieve the rx queue level */
- rxQueueLevel = 0;
- ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel);
- (*numRxQueueEntries) += rxQueueLevel;
- }
-}
-
-/**
- * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
- *
- * @brief Change the callback registered to all rx queues.
- *
- * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register
- *
- * @return IxEthAccStatus
- *
- * @note The user may decide to use different Rx mechanisms
- * (e.g. receive many frames at the same time , or receive
- * one frame at a time, depending on the overall application
- * performances). A different QMgr callback is registered. This
- * way, there is no excessive pointer checks in the datapath.
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback)
-{
- IxEthAccQregInfo *qInfoDes;
- IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;
-
- /* parameter check */
- if (NULL == ixQMgrCallback)
- {
- ret = IX_ETH_ACC_FAIL;
- }
-
- /* iterate thru rx queues */
- for (qInfoDes = ixEthAccQmgrRxQueuesInfo;
- (qInfoDes->qCallback != (IxQMgrCallback) NULL )
- && (ret == IX_ETH_ACC_SUCCESS);
- ++qInfoDes)
- {
- /* register the rx callback for all queues */
- if (ixQMgrNotificationCallbackSet(qInfoDes->qId,
- ixQMgrCallback,
- qInfoDes->callbackTag
- ) != IX_SUCCESS)
- {
- ret = IX_ETH_ACC_FAIL;
- }
- }
- return(ret);
-}
-
-/**
- * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
- *
- * @brief Check the npe exists for this port
- *
- * @param IxEthAccPortId portId[in] port
- *
- * @return IxEthAccStatus
- *
- * @internal
- */
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId)
-{
-
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((IX_ETH_PORT_1 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- if ((IX_ETH_PORT_2 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- if ((IX_ETH_PORT_3 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_ENABLED))
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/**
- * @fn ixEthAccStatsShow(void)
- *
- * @brief Displays all EthAcc stats
- *
- * @return void
- *
- */
-void ixEthAccStatsShow(IxEthAccPortId portId)
-{
- ixEthAccMdioShow();
-
- printf("\nPort %u\nUnicast MAC : ", portId);
- ixEthAccPortUnicastAddressShow(portId);
- ixEthAccPortMulticastAddressShow(portId);
- printf("\n");
-
- ixEthAccDataPlaneShow();
-}
-
-
-
diff --git a/drivers/net/npe/IxEthAccControlInterface.c b/drivers/net/npe/IxEthAccControlInterface.c
deleted file mode 100644
index dbe32e133c..0000000000
--- a/drivers/net/npe/IxEthAccControlInterface.c
+++ /dev/null
@@ -1,509 +0,0 @@
-/**
- * @file IxEthAccControlInterface.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-
-PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex;
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId);
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- /* check the context is iinitialized */
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortEnabledQueryPriv(portId, enabled);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortPromiscuousModeClearPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortPromiscuousModeSetPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressJoinAllPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMulticastAddressLeaveAllPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortUnicastAddressShow(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortUnicastAddressShowPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC void
-ixEthAccPortMulticastAddressShow(IxEthAccPortId portId)
-{
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return;
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- ixEthAccPortMulticastAddressShowPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDuplexModeSetPriv(portId, mode);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortDuplexModeGetPriv(portId, mode);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccRxSchedulingDisciplineSetPriv(sched);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccNpeLoopbackEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxEnable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxEnablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccNpeLoopbackDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortTxDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortTxDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortRxDisable(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortRxDisablePriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
-
-IX_ETH_ACC_PUBLIC IxEthAccStatus
-ixEthAccPortMacReset(IxEthAccPortId portId)
-{
- IxEthAccStatus result;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER);
- result = ixEthAccPortMacResetPriv(portId);
- ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex);
- return result;
-}
diff --git a/drivers/net/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c
deleted file mode 100644
index c0b82d99b7..0000000000
--- a/drivers/net/npe/IxEthAccDataPlane.c
+++ /dev/null
@@ -1,2459 +0,0 @@
-/**
- * @file IxEthDataPlane.c
- *
- * @author Intel Corporation
- * @date 12-Feb-2002
- *
- * @brief This file contains the implementation of the IXPxxx
- * Ethernet Access Data plane component
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeMh.h"
-#include "IxEthAcc.h"
-#include "IxEthDB.h"
-#include "IxOsal.h"
-#include "IxEthDBPortDefs.h"
-#include "IxFeatureCtrl.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccQueueAssign_p.h"
-
-extern PUBLIC IxEthAccMacState ixEthAccMacState[];
-extern PUBLIC UINT32 ixEthAccNewSrcMask;
-
-/**
- * private functions prototype
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask);
-
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
- IxEthAccTxPriority *priorityPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
- IxEthAccTxPriority priority);
-
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId);
-
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId,
- UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId,
- UINT32 qBuffer);
-
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId,
- UINT32 qBuffer,
- UINT32 priority);
-
-/**
- * @addtogroup IxEthAccPri
- *@{
- */
-
-/* increment a counter only when stats are enabled */
-#define TX_STATS_INC(port,field) \
- IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field)
-#define RX_STATS_INC(port,field) \
- IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field)
-
-/* always increment the counter (mainly used for unexpected errors) */
-#define TX_INC(port,field) \
- ixEthAccPortData[port].ixEthAccTxData.stats.field++
-#define RX_INC(port,field) \
- ixEthAccPortData[port].ixEthAccRxData.stats.field++
-
-PRIVATE IxEthAccDataPlaneStats ixEthAccDataStats;
-
-extern IxEthAccPortDataInfo ixEthAccPortData[];
-extern IxEthAccInfo ixEthAccDataInfo;
-
-PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/**
- *
- * @brief Mbuf header conversion macros : they implement the
- * different conversions using a temporary value. They also double-check
- * that the parameters can be converted to/from NPE format.
- *
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define PTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
- do { void *temp; \
- IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
- (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \
- while(0)
-#else
-#define PTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#define PTR_NPE2VIRT(type,src,ptrDst) \
- do { void *temp; \
- IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \
- IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \
- temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \
- (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \
- while(0)
-#endif
-
-/**
- *
- * @brief Mbuf payload pointer conversion macros : Wince has its own
- * method to convert the buffer pointers
- */
-#if defined(__wince) && !defined(IN_KERNEL)
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) \
- do { UINT32 temp; \
- temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \
- (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \
- while(0)
-
-#else
-#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst)
-#endif
-
-
-/* Flush the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \
- do { \
- IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \
- sizeof(IxEthAccNe)); \
- } \
- while(0)
-
-/* Invalidate the shared part of the mbuf header */
-#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \
- do { \
- IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \
- sizeof(IxEthAccNe)); \
- } \
- while(0)
-
-/* Preload one cache line (shared mbuf headers are aligned
- * and their size is 1 cache line)
- *
- * IX_OSAL_CACHED is defined when the mbuf headers are
- * allocated from cached memory.
- *
- * Other processor on emulation environment may not implement
- * preload function
- */
-#ifdef IX_OSAL_CACHED
- #if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
- #define IX_ACC_DATA_CACHE_PRELOAD(ptr) \
- do { /* preload a cache line (Xscale Processor) */ \
- __asm__ (" pld [%0]\n": : "r" (ptr)); \
- } \
- while(0)
- #else
- /* preload not implemented on different processor */
- #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
- do { /* nothing */ } while (0)
- #endif
-#else
- /* preload not needed if cache is not enabled */
- #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \
- do { /* nothing */ } while (0)
-#endif
-
-/**
- *
- * @brief function to retrieve the correct pointer from
- * a queue entry posted by the NPE
- *
- * @param qEntry : entry from qmgr queue
- * mask : applicable mask for this queue
- * (4 most significant bits are used for additional informations)
- *
- * @return IX_OSAL_MBUF * pointer to mbuf header
- *
- * @internal
- */
-PRIVATE IX_OSAL_MBUF *
-ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask)
-{
- IX_OSAL_MBUF *mbufPtr;
-
- if (qEntry != 0)
- {
- /* mask NPE bits (e.g. priority, port ...) */
- qEntry &= mask;
-
-#if IX_ACC_DRAM_PHYS_OFFSET != 0
- /* restore the original address pointer (if PHYS_OFFSET is not 0) */
- qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-#endif
- /* get the mbuf pointer address from the npe-shared address */
- qEntry -= offsetof(IX_OSAL_MBUF,ix_ne);
-
- /* phys2virt mbuf */
- mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry);
-
- /* preload the cacheline shared with NPE */
- IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr));
-
- /* preload the cacheline used by xscale */
- IX_ACC_DATA_CACHE_PRELOAD(mbufPtr);
- }
- else
- {
- mbufPtr = NULL;
- }
-
- return mbufPtr;
-}
-
-/* Convert the mbuf header for NPE transmission */
-PRIVATE UINT32
-ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf)
-{
- UINT32 qbuf;
- UINT32 len;
-
- /* endianess swap for tci and flags
- note: this is done only once, even for chained buffers */
- IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
- IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
- /* test for unchained mbufs */
- if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
- {
- /* "best case" scenario : unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs);
-
- /* payload pointer conversion */
- DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
- /* unchained mbufs : the frame length is the mbuf length
- * and the 2 identical lengths are stored in the same
- * word.
- */
- len = IX_OSAL_MBUF_MLEN(mbuf);
-
- /* set the length in both length and pktLen 16-bits fields */
- len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* unchained mbufs : next contains 0 */
- IX_ETHACC_NE_NEXT(mbuf) = 0;
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(mbuf);
- }
- else
- {
- /* chained mbufs */
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
- UINT32 frmLen;
-
- /* get the frame length from the header of the first buffer */
- frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf);
-
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs);
-
- /* payload pointer */
- DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
- /* Buffer length and frame length are stored in the same word */
- len = IX_OSAL_MBUF_MLEN(ptr);
- len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* get the virtual next chain pointer */
- nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
- if (nextPtr != NULL)
- {
- /* shared pointer of the next buffer is chained */
- PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
- IX_ETHACC_NE_NEXT(ptr));
- }
- else
- {
- IX_ETHACC_NE_NEXT(ptr) = 0;
- }
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
- /* move to next buffer */
- ptr = nextPtr;
-
- /* the frame length field is set only in the first buffer
- * and is zeroed in the next buffers
- */
- frmLen = 0;
- }
- while(ptr != NULL);
-
- }
-
- /* virt2phys mbuf itself */
- qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
- IX_ETHACC_NE_SHARED(mbuf));
-
- /* Ensure the bits which are reserved to exchange information with
- * the NPE are cleared
- *
- * If the mbuf address is not correctly aligned, or from an
- * incompatible memory range, there is no point to continue
- */
- IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0),
- "Invalid address range");
-
- return qbuf;
-}
-
-/* Convert the mbuf header for NPE reception */
-PRIVATE UINT32
-ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf)
-{
- UINT32 len;
- UINT32 qbuf;
-
- if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL)
- {
- /* "best case" scenario : unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs);
-
- /* unchained mbufs : payload pointer */
- DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf));
-
- /* unchained mbufs : set the buffer length
- * and the frame length field is zeroed
- */
- len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* unchained mbufs : next pointer is null */
- IX_ETHACC_NE_NEXT(mbuf) = 0;
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(mbuf);
-
- /* remove shared header cache line */
- IX_ETHACC_NE_CACHE_INVALIDATE(mbuf);
- }
- else
- {
- /* chained mbufs */
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
-
- do
- {
- /* chained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs);
-
- /* we must save virtual next chain pointer */
- nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
-
- if (nextPtr != NULL)
- {
- /* chaining pointer for NPE */
- PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr),
- IX_ETHACC_NE_NEXT(ptr));
- }
- else
- {
- IX_ETHACC_NE_NEXT(ptr) = 0;
- }
-
- /* payload pointer */
- DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr));
-
- /* buffer length */
- len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET);
- IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len);
-
- /* flush shared header after all address conversions */
- IX_ETHACC_NE_CACHE_FLUSH(ptr);
-
- /* remove shared header cache line */
- IX_ETHACC_NE_CACHE_INVALIDATE(ptr);
-
- /* next mbuf in the chain */
- ptr = nextPtr;
- }
- while(ptr != NULL);
- }
-
- /* virt2phys mbuf itself */
- qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(
- IX_ETHACC_NE_SHARED(mbuf));
-
- /* Ensure the bits which are reserved to exchange information with
- * the NPE are cleared
- *
- * If the mbuf address is not correctly aligned, or from an
- * incompatible memory range, there is no point to continue
- */
- IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0),
- "Invalid address range");
-
- return qbuf;
-}
-
-/* Convert the mbuf header after NPE transmission
- * Since there is nothing changed by the NPE, there is no need
- * to process anything but the update of internal stats
- * when they are enabled
-*/
-PRIVATE void
-ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf)
-{
-#ifndef NDEBUG
- /* test for unchained mbufs */
- if (IX_ETHACC_NE_NEXT(mbuf) == 0)
- {
- /* unchained mbufs : update the stats */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs);
- }
- else
- {
- /* chained mbufs : walk the chain and update the stats */
- IX_OSAL_MBUF *ptr = mbuf;
-
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs);
- ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr);
- }
- while (ptr != NULL);
- }
-#endif
-}
-
-/* Convert the mbuf header after NPE reception */
-PRIVATE void
-ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
-{
- UINT32 len;
-
- /* endianess swap for tci and flags
- note: this is done only once, even for chained buffers */
- IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf));
- IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf));
-
- /* test for unchained mbufs */
- if (IX_ETHACC_NE_NEXT(mbuf) == 0)
- {
- /* unchained mbufs */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs);
-
- /* get the frame length. it is the same than the buffer length */
- len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
- len &= IX_ETHNPE_ACC_PKTLENGTH_MASK;
- IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len;
-
- /* clears the next packet field */
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL;
- }
- else
- {
- IX_OSAL_MBUF *ptr = mbuf;
- IX_OSAL_MBUF *nextPtr;
- UINT32 frmLen;
-
- /* convert the frame length */
- frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf));
- IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK);
-
- /* chained mbufs */
- do
- {
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs);
-
- /* convert the length */
- len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr));
- IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
-
- /* get the next pointer */
- PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
- if (nextPtr != NULL)
- {
- nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
- }
- /* set the next pointer */
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr;
-
- /* move to the next buffer */
- ptr = nextPtr;
- }
- while (ptr != NULL);
- }
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the tx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
- IX_STATUS qStatus;
- if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS)
- {
- qStatus = ixQMgrQWrite(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- &qBuffer);
-#ifndef NDEBUG
- if (qStatus != IX_SUCCESS)
- {
- TX_STATS_INC(portId, txOverflow);
- }
-#endif
- ixOsalFastMutexUnlock(&txWriteMutex[portId]);
- }
- else
- {
- TX_STATS_INC(portId, txLock);
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- return qStatus;
-}
-
-/* write to qmgr if possible and report an overflow if not possible
- * Use a fast lock to protect the queue write.
- * This way, the Rx feature is reentrant.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer)
-{
- IX_STATUS qStatus;
- if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS)
- {
- qStatus = ixQMgrQWrite(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
- &qBuffer);
-#ifndef NDEBUG
- if (qStatus != IX_SUCCESS)
- {
- RX_STATS_INC(portId, rxFreeOverflow);
- }
-#endif
- ixOsalFastMutexUnlock(&rxWriteMutex[portId]);
- }
- else
- {
- RX_STATS_INC(portId, rxFreeLock);
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- return qStatus;
-}
-
-/*
- * Set the priority and write to a qmgr queue.
- */
-PRIVATE IX_STATUS
-ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority)
-{
- /* fill the priority field */
- qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R);
-
- return ixEthAccQmgrLockTxWrite(portId, qBuffer);
-}
-
-/**
- *
- * @brief This function will discover the highest priority S/W Tx Q that
- * has entries in it
- *
- * @param portId - (in) the id of the port whose S/W Tx queues are to be searched
- * priorityPtr - (out) the priority of the highest priority occupied q will be written
- * here
- *
- * @return IX_ETH_ACC_SUCCESS if an occupied Q is found
- * IX_ETH_ACC_FAIL if no Q has entries
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId,
- IxEthAccTxPriority *priorityPtr)
-{
- if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline
- == FIFO_NO_PRIORITY)
- {
- if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY]))
- {
- return IX_ETH_ACC_FAIL;
- }
- else
- {
- *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
- TX_STATS_INC(portId,txPriority[*priorityPtr]);
- return IX_ETH_ACC_SUCCESS;
- }
- }
- else
- {
- IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7;
- while(1)
- {
- if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccTxData.txQ[highestPriority]))
- {
-
- *priorityPtr = highestPriority;
- TX_STATS_INC(portId,txPriority[highestPriority]);
- return IX_ETH_ACC_SUCCESS;
-
- }
- if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0)
- {
- return IX_ETH_ACC_FAIL;
- }
- highestPriority--;
- }
- }
-}
-
-/**
- *
- * @brief This function will take a buffer from a TX S/W Q and attempt
- * to add it to the relevant TX H/W Q
- *
- * @param portId - the port whose TX queue is to be written to
- * priority - identifies the queue from which the entry is to be read
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccTxFromSwQ(IxEthAccPortId portId,
- IxEthAccTxPriority priority)
-{
- IX_OSAL_MBUF *mbuf;
- IX_STATUS qStatus;
-
- IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority");
-
- IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- if (mbuf != NULL)
- {
- /*
- * Add the Tx buffer to the H/W Tx Q
- * We do not need to flush here as it is already done
- * in TxFrameSubmit().
- */
- qStatus = ixEthAccQmgrTxWrite(
- portId,
- IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)),
- priority);
-
- if (qStatus == IX_SUCCESS)
- {
- TX_STATS_INC(portId,txFromSwQOK);
- return IX_SUCCESS;
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * H/W Q overflow, need to save the buffer
- * back on the s/w Q.
- * we must put it back on the head of the q to avoid
- * reordering packet tx
- */
- TX_STATS_INC(portId,txFromSwQDelayed);
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- /*enable Q notification*/
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING)
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccTxFromSwQ:Unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
-
- /* recovery attempt */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccTxData.txQ[priority],
- mbuf);
-
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- /* sw queue is empty */
- }
- return IX_ETH_ACC_FAIL;
-}
-
-/**
- *
- * @brief This function will take a buffer from a RXfree S/W Q and attempt
- * to add it to the relevant RxFree H/W Q
- *
- * @param portId - the port whose RXFree queue is to be written to
- *
- * @internal
- */
-PRIVATE IxEthAccStatus
-ixEthAccRxFreeFromSwQ(IxEthAccPortId portId)
-{
- IX_OSAL_MBUF *mbuf;
- IX_STATUS qStatus = IX_SUCCESS;
-
- IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
- if (mbuf != NULL)
- {
- /*
- * Add The Rx Buffer to the H/W Free buffer Q if possible
- */
- qStatus = ixEthAccQmgrLockRxWrite(portId,
- IX_OSAL_MMU_VIRT_TO_PHYS(
- (UINT32)IX_ETHACC_NE_SHARED(mbuf)));
-
- if (qStatus == IX_SUCCESS)
- {
- RX_STATS_INC(portId,rxFreeRepFromSwQOK);
- /*
- * Buffer added to h/w Q.
- */
- return IX_SUCCESS;
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * H/W Q overflow, need to save the buffer back on the s/w Q.
- */
- RX_STATS_INC(portId,rxFreeRepFromSwQDelayed);
-
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
- }
- else
- {
- /* unexpected qmgr error */
- RX_INC(portId,rxUnexpectedError);
-
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- mbuf);
-
- IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- else
- {
- /* sw queue is empty */
- }
- return IX_ETH_ACC_FAIL;
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccInitDataPlane()
-{
- UINT32 portId;
-
- /*
- * Initialize the service and register callback to other services.
- */
-
- IX_ETH_ACC_MEMSET(&ixEthAccDataStats,
- 0,
- sizeof(ixEthAccDataStats));
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- ixOsalFastMutexInit(&txWriteMutex[portId]);
- ixOsalFastMutexInit(&rxWriteMutex[portId]);
-
- IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId],
- 0,
- sizeof(ixEthAccPortData[portId]));
-
- ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY;
- }
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortTxDoneCallback
- txCallbackFn,
- UINT32 callbackTag)
-{
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
-/* HACK: removing this code to enable NPE-A preliminary testing
- * if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- * {
- * IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0);
- * return IX_ETH_ACC_SUCCESS ;
- * }
- */
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- if (txCallbackFn == 0)
- /* Check for null function pointer here. */
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn;
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag;
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId,
- IxEthAccPortRxCallback
- rxCallbackFn,
- UINT32 callbackTag)
-{
- IxEthAccPortId port;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* Check for null function pointer here. */
- if (rxCallbackFn == NULL)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- /* Check the user is not changing the callback type
- * when the port is enabled.
- */
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
- {
- if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true))
- {
- /* one of the active ports has a different rx callback type.
- * Changing the callback type when the port is enabled
- * is not safe
- */
- return (IX_ETH_ACC_INVALID_ARG);
- }
- }
- }
-
- /* update the callback pointer : this is done before
- * registering the new qmgr callback
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn;
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag;
-
- /* update the qmgr callback for rx queues */
- if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback)
- != IX_ETH_ACC_SUCCESS)
- {
- /* unexpected qmgr error */
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \
- "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
- RX_INC(portId,rxUnexpectedError);
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister(
- IxEthAccPortId portId,
- IxEthAccPortMultiBufferRxCallback
- rxCallbackFn,
- UINT32 callbackTag)
-{
- IxEthAccPortId port;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* Check for null function pointer here. */
- if (rxCallbackFn == NULL)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- /* Check the user is not changing the callback type
- * when the port is enabled.
- */
- if (ixEthAccMacState[portId].portDisableState == ACTIVE)
- {
- for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++)
- {
- if ((ixEthAccMacState[port].portDisableState == ACTIVE)
- && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false))
- {
- /* one of the active ports has a different rx callback type.
- * Changing the callback type when the port is enabled
- * is not safe
- */
- return (IX_ETH_ACC_INVALID_ARG);
- }
- }
- }
-
- /* update the callback pointer : this is done before
- * registering the new qmgr callback
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn;
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag;
-
- /* update the qmgr callback for rx queues */
- if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback)
- != IX_ETH_ACC_SUCCESS)
- {
- /* unexpected qmgr error */
- RX_INC(portId,rxUnexpectedError);
-
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \
- "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0);
-
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer,
- IxEthAccTxPriority priority)
-{
- IX_STATUS qStatus = IX_SUCCESS;
- UINT32 qBuffer;
- IxEthAccTxPriority highestPriority;
- IxQMgrQStatus txQStatus;
-
-#ifndef NDEBUG
- if (buffer == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n",
- (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_PORT_UNINITIALIZED ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-#endif
-
- /*
- * Need to Flush the MBUF and its contents (data) as it may be
- * read from the NPE. Convert virtual addresses to physical addresses also.
- */
- qBuffer = ixEthAccMbufTxQPrepare(buffer);
-
- /*
- * If no fifo priority set on Xscale ...
- */
- if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_NO_PRIORITY)
- {
- /*
- * Add The Tx Buffer to the H/W Tx Q if possible
- * (the priority is passed to the NPE, because
- * the NPE is able to reorder the frames
- * before transmission to the underlying hardware)
- */
- qStatus = ixEthAccQmgrTxWrite(portId,
- qBuffer,
- IX_ETH_ACC_TX_DEFAULT_PRIORITY);
-
- if (qStatus == IX_SUCCESS)
- {
- TX_STATS_INC(portId,txQOK);
-
- /*
- * "best case" scenario : Buffer added to h/w Q.
- */
- return (IX_SUCCESS);
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- /*
- * We were unable to write the buffer to the
- * appropriate H/W Q, Save it in the sw Q.
- * (use the default priority queue regardless of
- * input parameter)
- */
- priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY;
- }
- else
- {
- /* unexpected qmgr error */
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n",
- (UINT32)qStatus, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
- }
- else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_PRIORITY)
- {
-
- /*
- * For priority transmission, put the frame directly on the H/W queue
- * if the H/W queue is empty, otherwise, put it in a S/W Q
- */
- ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus);
- if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0)
- {
- /*The tx queue is empty, check whether there are buffers on the s/w queues*/
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- /*there are buffers on the s/w queues, submit them*/
- ixEthAccTxFromSwQ(portId, highestPriority);
-
- /* the queue was empty, 1 buffer is already supplied
- * but is likely to be immediately transmitted and the
- * hw queue is likely to be empty again, so submit
- * more from the sw queues
- */
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- ixEthAccTxFromSwQ(portId, highestPriority);
- /*
- * and force the buffer supplied to be placed
- * on a priority queue
- */
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- else
- {
- /*there are no buffers in the s/w queues, submit directly*/
- qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
- }
- }
- else
- {
- /*there are no buffers in the s/w queues, submit directly*/
- qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority);
- }
- }
- else
- {
- qStatus = IX_QMGR_Q_OVERFLOW;
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n",
- 0, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- if(qStatus == IX_SUCCESS )
- {
- TX_STATS_INC(portId,txQOK);
- return IX_ETH_ACC_SUCCESS;
- }
- else if(qStatus == IX_QMGR_Q_OVERFLOW)
- {
- TX_STATS_INC(portId,txQDelayed);
- /*
- * We were unable to write the buffer to the
- * appropriate H/W Q, Save it in a s/w Q.
- */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
- ixEthAccPortData[portId].
- ixEthAccTxData.txQ[priority],
- buffer);
-
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS)
- {
- if (qStatus == IX_QMGR_WARNING)
- {
- /* notification is enabled for a queue
- * which is already empty (the condition is already met)
- * and there will be no more queue event to drain the sw queue
- */
- TX_STATS_INC(portId,txLateNotificationEnabled);
-
- /* pull a buffer from the sw queue */
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority)
- !=IX_ETH_ACC_FAIL)
- {
- /*there are buffers on the s/w queues, submit from them*/
- ixEthAccTxFromSwQ(portId, highestPriority);
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- }
- else
- {
- TX_INC(portId,txUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- return (IX_ETH_ACC_FAIL);
- }
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- *
- * @brief replenish: convert a chain of mbufs to the format
- * expected by the NPE
- *
- */
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId,
- IX_OSAL_MBUF *buffer)
-{
- IX_STATUS qStatus = IX_SUCCESS;
- UINT32 qBuffer;
-
- /*
- * Check buffer is valid.
- */
-
-#ifndef NDEBUG
- /* check parameter value */
- if (buffer == 0)
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- /* check initialisation is done */
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_PORT_UNINITIALIZED ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
- /* check boundaries and constraints */
- if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
- {
- return (IX_ETH_ACC_FAIL);
- }
-#endif
-
- qBuffer = ixEthAccMbufRxQPrepare(buffer);
-
- /*
- * Add The Rx Buffer to the H/W Free buffer Q if possible
- */
- qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer);
-
- if (qStatus == IX_SUCCESS)
- {
- RX_STATS_INC(portId,rxFreeRepOK);
- /*
- * Buffer added to h/w Q.
- */
- return (IX_SUCCESS);
- }
- else if (qStatus == IX_QMGR_Q_OVERFLOW)
- {
- RX_STATS_INC(portId,rxFreeRepDelayed);
- /*
- * We were unable to write the buffer to the approprate H/W Q,
- * Save it in a s/w Q.
- */
- IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(
- ixEthAccPortData[portId].ixEthAccRxData.freeBufferList,
- buffer);
-
- qStatus = ixQMgrNotificationEnable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId),
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId));
-
- if (qStatus != IX_SUCCESS)
- {
- if (qStatus == IX_QMGR_WARNING)
- {
- /* notification is enabled for a queue
- * which is already empty (the condition is already met)
- * and there will be no more queue event to drain the sw queue
- * move an entry from the sw queue to the hw queue */
- RX_STATS_INC(portId,rxFreeLateNotificationEnabled);
- ixEthAccRxFreeFromSwQ(portId);
- }
- else
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccRxPortFreeReplenish:Error: %u\n",
- qStatus, 0, 0, 0, 0, 0);
- }
- }
- }
- else
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n",
- (UINT32)qStatus, 0, 0, 0, 0, 0);
- return(IX_ETH_ACC_FAIL);
- }
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId,
- IxEthAccSchedulerDiscipline
- sched)
-{
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return (IX_ETH_ACC_INVALID_PORT);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched;
- return (IX_ETH_ACC_SUCCESS);
-}
-
-IX_ETH_ACC_PUBLIC
-IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline
- sched)
-{
- if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY)
- {
- return (IX_ETH_ACC_INVALID_ARG);
- }
-
- ixEthAccDataInfo.schDiscipline = sched;
-
- return (IX_ETH_ACC_SUCCESS);
-}
-
-
-/**
- * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
- *
- * @brief process incoming frame :
- *
- * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback
- *
- * @return none
- *
- * @internal
- *
- */
-IX_ETH_ACC_PRIVATE BOOL
-ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr)
-{
- UINT32 flags;
- IxEthDBStatus result;
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameProcess: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return false;
- }
-#endif
-
- /* convert fields from mbuf header */
- ixEthAccMbufFromRxQ(mbufPtr);
-
- /* check about any special processing for this frame */
- flags = IX_ETHACC_NE_FLAGS(mbufPtr);
- if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0)
- {
- /* "best case" scenario : nothing special to do for this frame */
- return true;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* if a new source MAC address is detected by the NPE,
- * update IxEthDB with the portId and the MAC address.
- */
- if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0)
- {
- result = ixEthDBFilteringDynamicEntryProvision(portId,
- (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr));
-
- if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE)
- {
- if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY))
- {
- RX_STATS_INC(portId, rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \
- to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0);
- }
- else
- {
- /* we expect this to fail during PortDisable, as EthDB is disabled for
- * that port and will refuse to learn new addresses
- */
- }
- }
- else
- {
- RX_STATS_INC(portId, rxUnlearnedMacAddress);
- }
- }
-#endif
-
- /* check if this frame should have been filtered
- * by the NPE and take the appropriate action
- */
- if (((flags & IX_ETHACC_NE_FILTERMASK) != 0)
- && (ixEthAccMacState[portId].portDisableState == ACTIVE))
- {
- /* If the mbuf was allocated with a small data size, or the current data pointer is not
- * within the allocated data area, then the buffer is non-standard and has to be
- * replenished with the minimum size only
- */
- if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN)
- || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr))
- || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) +
- IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr))
- < IX_OSAL_MBUF_MDATA(mbufPtr)) )
- {
- /* set to minimum length */
- IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
- IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN;
- }
- else
- {
- /* restore original length */
- IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) =
- ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) -
- (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) );
- }
-
- /* replenish from here */
- if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\
- on port %d\n", portId, 0, 0, 0, 0, 0);
- }
-
- RX_STATS_INC(portId, rxFiltered);
-
- /* indicate that frame should not be subjected to further processing */
- return false;
- }
-
- return true;
-}
-
-
-/**
- * @fn ixEthRxFrameQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed one-at-a-time to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- IX_OSAL_MBUF *nextMbufPtr;
- UINT32 qEntry;
- UINT32 nextQEntry;
- UINT32 *qEntryPtr;
- UINT32 portId;
- UINT32 destPortId;
- UINT32 npeId;
- UINT32 rxQReadStatus;
-
- /*
- * Design note : entries are read in a buffer, This buffer contains
- * an extra zeroed entry so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
-
- /*
- * Indication of the number of times the callback is used.
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
- do
- {
- /*
- * Indication of the number of times the queue is drained
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
- /* ensure the last entry of the array contains a zeroed value */
- qEntryPtr = rxQEntry;
- qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
- rxQReadStatus = ixQMgrQBurstRead(qId,
- IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
- && (rxQReadStatus != IX_SUCCESS))
- {
- ixEthAccDataStats.unexpectedError++;
- /*major error*/
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameQMCallback:Error: %u\n",
- (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert and preload the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *qEntryPtr;
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- while(nextQEntry != 0)
- {
- /* get the next entry */
- qEntry = nextQEntry;
- mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameQMCallback: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *(++qEntryPtr);
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- /*
- * Get Port and Npe ID from message.
- */
- npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
- qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
- /* process frame, check the return code and skip the remaining of
- * the loop if the frame is to be filtered out
- */
- if (ixEthRxFrameProcess(portId, mbufPtr))
- {
- /* destination portId for this packet */
- destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr);
-
- if (destPortId != IX_ETH_DB_UNKNOWN_PORT)
- {
- destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId);
- }
-
- /* test if QoS is enabled in ethAcc
- */
- if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
- {
- /* check if there is a higher priority queue
- * which may require processing and then process it.
- */
- if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
- {
- ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
- callbackId);
- }
- }
-
- /*
- * increment priority stats
- */
- RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
-
- /*
- * increment callback count stats
- */
- RX_STATS_INC(portId,rxFrameClientCallback);
-
- /*
- * Call user level callback.
- */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn(
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag,
- mbufPtr,
- destPortId);
- }
- }
- } while (rxQReadStatus == IX_SUCCESS);
-}
-
-/**
- * @fn ixEthRxMultiBufferQMCallback
- *
- * @brief receive callback for Frame receive Q from NPE
- *
- * Frames are passed as an array to the user
- *
- * @param @ref IxQMgrCallback
- *
- * @return none
- *
- * @internal
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- IX_OSAL_MBUF *nextMbufPtr;
- UINT32 qEntry;
- UINT32 nextQEntry;
- UINT32 *qEntryPtr;
- UINT32 portId;
- UINT32 npeId;
- UINT32 rxQReadStatus;
- /*
- * Design note : entries are read in a static buffer, This buffer contains
- * an extra zeroed entry so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
- static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1];
- IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS];
-
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- rxMbufPtr[portId] = rxMbufPortArray[portId];
- }
-
- /*
- * Indication of the number of times the callback is used.
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter);
-
- do
- {
- /*
- * Indication of the number of times the queue is drained
- */
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead);
-
- /* ensure the last entry of the array contains a zeroed value */
- qEntryPtr = rxQEntry;
- qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0;
-
- rxQReadStatus = ixQMgrQBurstRead(qId,
- IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW)
- && (rxQReadStatus != IX_SUCCESS))
- {
- ixEthAccDataStats.unexpectedError++;
- /*major error*/
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameMultiBufferQMCallback:Error: %u\n",
- (UINT32)rxQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert and preload the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *qEntryPtr;
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- while(nextQEntry != 0)
- {
- /* get the next entry */
- qEntry = nextQEntry;
- mbufPtr = nextMbufPtr;
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* convert the next entry
- * (the conversion function takes care about null pointers which
- * are used to mark the end of the loop)
- */
- nextQEntry = *(++qEntryPtr);
- nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry,
- IX_ETHNPE_QM_Q_RXENET_ADDR_MASK);
-
- /*
- * Get Port and Npe ID from message.
- */
- npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK &
- qEntry) >>
- IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
- /* skip the remaining of the loop if the frame is
- * to be filtered out
- */
- if (ixEthRxFrameProcess(portId, mbufPtr))
- {
- /* store a mbuf pointer in an array */
- *rxMbufPtr[portId]++ = mbufPtr;
-
- /*
- * increment priority stats
- */
- RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]);
- }
-
- /* test for QoS enabled in ethAcc */
- if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY)
- {
- /* check if there is a higher priority queue
- * which may require processing and then process it.
- */
- if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES)
- {
- ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId],
- callbackId);
- }
- }
- }
-
- /* check if any of the the arrays contains any entry */
- for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- if (rxMbufPtr[portId] != rxMbufPortArray[portId])
- {
- /* add a last NULL pointer at the end of the
- * array of mbuf pointers
- */
- *rxMbufPtr[portId] = NULL;
-
- /*
- * increment callback count stats
- */
- RX_STATS_INC(portId,rxFrameClientCallback);
-
- /*
- * Call user level callback with an array of
- * buffers (NULL terminated)
- */
- ixEthAccPortData[portId].ixEthAccRxData.
- rxMultiBufferCallbackFn(
- ixEthAccPortData[portId].ixEthAccRxData.
- rxMultiBufferCallbackTag,
- rxMbufPortArray[portId]);
-
- /* reset the buffer pointer to the beginning of
- * the array
- */
- rxMbufPtr[portId] = rxMbufPortArray[portId];
- }
- }
-
- } while (rxQReadStatus == IX_SUCCESS);
-}
-
-
-/**
- * @brief rxFree low event handler
- *
- */
-void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IxEthAccPortId portId = (IxEthAccPortId) callbackId;
- int lockVal;
- UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD;
- IX_STATUS qStatus = IX_SUCCESS;
-
- /*
- * We have reached a low threshold on one of the Rx Free Qs
- */
-
- /*note that due to the fact that we are working off an Empty threshold, this callback
- need only write a single entry to the Rx Free queue in order to re-arm the notification
- */
-
- RX_STATS_INC(portId,rxFreeLowCallback);
-
- /*
- * Get buffers from approprite S/W Rx freeBufferList Q.
- */
-
-#ifndef NDEBUG
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n",
- portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
- if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccRxData.freeBufferList))
- {
- /*
- * Turn off Q callback notification for Q in Question.
- */
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
-
-
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
- if (qStatus != IX_SUCCESS)
- {
- RX_INC(portId,rxUnexpectedError);
- IX_ETH_ACC_FATAL_LOG(
- "ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- return;
- }
- }
- else
- {
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- /*
- * Load the H/W Q with buffers from the s/w Q.
- */
-
- do
- {
- /*
- * Consume Q entries. - Note Q contains Physical addresss,
- * and have already been flushed to memory,
- * And endianess converted if required.
- */
- if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS)
- {
- /*
- * No more entries in s/w Q.
- * Turn off Q callback indication
- */
-
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
- if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId].
- ixEthAccRxData.freeBufferList))
- {
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId));
- }
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- break;
- }
- }
- while (--maxQWritesToPerform);
- }
-}
-/**
- * @fn Tx queue low event handler
- *
- */
-void
-ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IxEthAccPortId portId = (IxEthAccPortId) callbackId;
- int lockVal;
- UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK;
- IX_STATUS qStatus = IX_SUCCESS;
- IxEthAccTxPriority highestPriority;
-
-
- /*
- * We have reached a low threshold on the Tx Q, and are being asked to
- * supply a buffer for transmission from our S/W TX queues
- */
- TX_STATS_INC(portId,txLowThreshCallback);
-
- /*
- * Get buffers from approprite Q.
- */
-
-#ifndef NDEBUG
- if (!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n",
- portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- do
- {
- /*
- * Consume Q entries. - Note Q contains Physical addresss,
- * and have already been flushed to memory,
- * and endianess already sone if required.
- */
-
- IX_ETH_ACC_DATA_PLANE_LOCK(lockVal);
-
- if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) ==
- IX_ETH_ACC_FAIL)
- {
- /*
- * No more entries in s/w Q.
- * Turn off Q callback indication
- */
- qStatus = ixQMgrNotificationDisable(
- IX_ETH_ACC_PORT_TO_TX_Q_ID(portId));
-
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
-
- if (qStatus != IX_SUCCESS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n",
- qStatus, 0, 0, 0, 0, 0);
- }
-
- return;
- }
- else
- {
- IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal);
- if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS)
- {
- /* nothing left in the sw queue or the hw queues are
- * full. There is no point to continue to drain the
- * sw queues
- */
- return;
- }
- }
- }
- while (--maxQWritesToPerform);
-}
-
-/**
- * @brief TxDone event handler
- *
- * Design note : while processing the entry X, entry X+1 is preloaded
- * into memory to reduce the number of stall cycles
- *
- */
-
-void
-ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId)
-{
- IX_OSAL_MBUF *mbufPtr;
- UINT32 qEntry;
- UINT32 *qEntryPtr;
- UINT32 txDoneQReadStatus;
- UINT32 portId;
- UINT32 npeId;
-
- /*
- * Design note : entries are read in a static buffer, This buffer contains
- * an extra entyry (which is zeroed by the compiler), so the loop will
- * always terminate on a null entry, whatever the result of Burst read is.
- */
- static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1];
-
- /*
- * Indication that Tx frames have been transmitted from the NPE.
- */
-
- IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter);
-
- do{
- qEntryPtr = txDoneQEntry;
- txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,
- IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK,
- qEntryPtr);
-
-#ifndef NDEBUG
- if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW
- && (txDoneQReadStatus != IX_SUCCESS))
- {
- /*major error*/
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback:Error: %u\n",
- (UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- qEntry = *qEntryPtr;
-
- while(qEntry != 0)
- {
- mbufPtr = ixEthAccEntryFromQConvert(qEntry,
- IX_ETHNPE_QM_Q_TXENET_ADDR_MASK);
-
-#ifndef NDEBUG
- if (mbufPtr == NULL)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n",
- 0, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /* endianness conversions and stats updates */
- ixEthAccMbufFromTxQ(mbufPtr);
-
- /*
- * Get NPE id from message, then convert to portId.
- */
- npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK &
- qEntry) >>
- IX_ETHNPE_QM_Q_FIELD_NPEID_R);
- portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- ixEthAccDataStats.unexpectedError++;
- IX_ETH_ACC_FATAL_LOG(
- "ixEthTxFrameDoneQMCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- TX_STATS_INC(portId,txDoneClientCallback);
-
- /*
- * Call user level callback.
- */
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn(
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag,
- mbufPtr);
-
- /* move to next queue entry */
- qEntry = *(++qEntryPtr);
-
- }
- } while( txDoneQReadStatus == IX_SUCCESS );
-}
-
-IX_ETH_ACC_PUBLIC
-void ixEthAccDataPlaneShow(void)
-{
- UINT32 numTx0Entries;
- UINT32 numTx1Entries;
- UINT32 numTxDoneEntries;
- UINT32 numRxEntries;
- UINT32 numRxFree0Entries;
- UINT32 numRxFree1Entries;
- UINT32 portId;
-#ifdef __ixp46X
- UINT32 numTx2Entries;
- UINT32 numRxFree2Entries;
-#endif
-#ifndef NDEBUG
- UINT32 priority;
- UINT32 numBuffersInRx=0;
- UINT32 numBuffersInTx=0;
- UINT32 numBuffersInSwQ=0;
- UINT32 totalBuffers=0;
- UINT32 rxFreeCallbackCounter = 0;
- UINT32 txCallbackCounter = 0;
-#endif
- UINT32 key;
-
- /* snapshot of stats */
- IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS];
- IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS];
- IxEthAccDataPlaneStats stats;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return;
- }
-
- /* get a reliable snapshot */
- key = ixOsalIrqLock();
-
- numTx0Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries);
- numTx1Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries);
- numTxDoneEntries = 0;
- ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries);
- numRxEntries = 0;
- ixEthAccQMgrRxQEntryGet(&numRxEntries);
- numRxFree0Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries);
- numRxFree1Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries);
-
-#ifdef __ixp46X
- numTx2Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries);
- numRxFree2Entries = 0;
- ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries);
-#endif
-
- for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- memcpy(&tx[portId],
- &ixEthAccPortData[portId].ixEthAccTxData.stats,
- sizeof(tx[portId]));
- memcpy(&rx[portId],
- &ixEthAccPortData[portId].ixEthAccRxData.stats,
- sizeof(rx[portId]));
- }
- memcpy(&stats, &ixEthAccDataStats, sizeof(stats));
-
- ixOsalIrqUnlock(key);
-
-#ifdef NDEBUG
- printf("Detailed statistics collection not supported in this load\n");
-#endif
-
- /* print snapshot */
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((IX_ETH_PORT_1 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- if ((IX_ETH_PORT_2 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- if ((IX_ETH_PORT_3 == portId) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- continue ;
- }
- }
-
- printf("PORT %u --------------------------------\n",
- portId);
-#ifndef NDEBUG
- printf("Tx Done Frames : %u\n",
- tx[portId].txDoneClientCallback +
- tx[portId].txDoneSwQDuringDisable +
- tx[portId].txDoneDuringDisable);
- printf("Tx Frames : %u\n",
- tx[portId].txQOK + tx[portId].txQDelayed);
- printf("Tx H/W Q Added OK : %u\n",
- tx[portId].txQOK);
- printf("Tx H/W Q Delayed : %u\n",
- tx[portId].txQDelayed);
- printf("Tx From S/W Q Added OK : %u\n",
- tx[portId].txFromSwQOK);
- printf("Tx From S/W Q Delayed : %u\n",
- tx[portId].txFromSwQDelayed);
- printf("Tx Overflow : %u\n",
- tx[portId].txOverflow);
- printf("Tx Mutual Lock : %u\n",
- tx[portId].txLock);
- printf("Tx Late Ntf Enabled : %u\n",
- tx[portId].txLateNotificationEnabled);
- printf("Tx Low Thresh CB : %u\n",
- tx[portId].txLowThreshCallback);
- printf("Tx Done from H/W Q (Disable) : %u\n",
- tx[portId].txDoneDuringDisable);
- printf("Tx Done from S/W Q (Disable) : %u\n",
- tx[portId].txDoneSwQDuringDisable);
- for (priority = IX_ETH_ACC_TX_PRIORITY_0;
- priority <= IX_ETH_ACC_TX_PRIORITY_7;
- priority++)
- {
- if (tx[portId].txPriority[priority])
- {
- printf("Tx Priority %u : %u\n",
- priority,
- tx[portId].txPriority[priority]);
- }
- }
-#endif
- printf("Tx unexpected errors : %u (should be 0)\n",
- tx[portId].txUnexpectedError);
-
-#ifndef NDEBUG
- printf("Rx Frames : %u\n",
- rx[portId].rxFrameClientCallback +
- rx[portId].rxSwQDuringDisable+
- rx[portId].rxDuringDisable);
- printf("Rx Free Replenish : %u\n",
- rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed);
- printf("Rx Free H/W Q Added OK : %u\n",
- rx[portId].rxFreeRepOK);
- printf("Rx Free H/W Q Delayed : %u\n",
- rx[portId].rxFreeRepDelayed);
- printf("Rx Free From S/W Q Added OK : %u\n",
- rx[portId].rxFreeRepFromSwQOK);
- printf("Rx Free From S/W Q Delayed : %u\n",
- rx[portId].rxFreeRepFromSwQDelayed);
- printf("Rx Free Overflow : %u\n",
- rx[portId].rxFreeOverflow);
- printf("Rx Free Mutual Lock : %u\n",
- rx[portId].rxFreeLock);
- printf("Rx Free Late Ntf Enabled : %u\n",
- rx[portId].rxFreeLateNotificationEnabled);
- printf("Rx Free Low CB : %u\n",
- rx[portId].rxFreeLowCallback);
- printf("Rx From H/W Q (Disable) : %u\n",
- rx[portId].rxDuringDisable);
- printf("Rx From S/W Q (Disable) : %u\n",
- rx[portId].rxSwQDuringDisable);
- printf("Rx unlearned Mac Address : %u\n",
- rx[portId].rxUnlearnedMacAddress);
- printf("Rx Filtered (Rx => RxFree) : %u\n",
- rx[portId].rxFiltered);
-
- for (priority = IX_ETH_ACC_TX_PRIORITY_0;
- priority <= IX_ETH_ACC_TX_PRIORITY_7;
- priority++)
- {
- if (rx[portId].rxPriority[priority])
- {
- printf("Rx Priority %u : %u\n",
- priority,
- rx[portId].rxPriority[priority]);
- }
- }
-#endif
- printf("Rx unexpected errors : %u (should be 0)\n",
- rx[portId].rxUnexpectedError);
-
-#ifndef NDEBUG
- numBuffersInTx = tx[portId].txQOK +
- tx[portId].txQDelayed -
- tx[portId].txDoneClientCallback -
- tx[portId].txDoneSwQDuringDisable -
- tx[portId].txDoneDuringDisable;
-
- printf("# Tx Buffers currently for transmission : %u\n",
- numBuffersInTx);
-
- numBuffersInRx = rx[portId].rxFreeRepOK +
- rx[portId].rxFreeRepDelayed -
- rx[portId].rxFrameClientCallback -
- rx[portId].rxSwQDuringDisable -
- rx[portId].rxDuringDisable;
-
- printf("# Rx Buffers currently for reception : %u\n",
- numBuffersInRx);
-
- totalBuffers += numBuffersInRx + numBuffersInTx;
-#endif
- }
-
- printf("---------------------------------------\n");
-
-#ifndef NDEBUG
- printf("\n");
- printf("Mbufs :\n");
- printf("Tx Unchained mbufs : %u\n",
- stats.unchainedTxMBufs);
- printf("Tx Chained bufs : %u\n",
- stats.chainedTxMBufs);
- printf("TxDone Unchained mbufs : %u\n",
- stats.unchainedTxDoneMBufs);
- printf("TxDone Chained bufs : %u\n",
- stats.chainedTxDoneMBufs);
- printf("RxFree Unchained mbufs : %u\n",
- stats.unchainedRxFreeMBufs);
- printf("RxFree Chained bufs : %u\n",
- stats.chainedRxFreeMBufs);
- printf("Rx Unchained mbufs : %u\n",
- stats.unchainedRxMBufs);
- printf("Rx Chained bufs : %u\n",
- stats.chainedRxMBufs);
-
- printf("\n");
- printf("Software queue usage :\n");
- printf("Buffers added to S/W Q : %u\n",
- stats.addToSwQ);
- printf("Buffers removed from S/W Q : %u\n",
- stats.removeFromSwQ);
-
- printf("\n");
- printf("Hardware queues callbacks :\n");
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- rxFreeCallbackCounter += rx[portId].rxFreeLowCallback;
- txCallbackCounter += tx[portId].txLowThreshCallback;
- }
- printf("Tx Done QM Callback invoked : %u\n",
- stats.txDoneCallbackCounter);
- printf("Tx QM Callback invoked : %u\n",
- txCallbackCounter);
- printf("Rx QM Callback invoked : %u\n",
- stats.rxCallbackCounter);
- printf("Rx QM Callback burst read : %u\n",
- stats.rxCallbackBurstRead);
- printf("Rx Free QM Callback invoked : %u\n",
- rxFreeCallbackCounter);
-#endif
- printf("Unexpected errors in CB : %u (should be 0)\n",
- stats.unexpectedError);
- printf("\n");
-
- printf("Hardware queues levels :\n");
- printf("Transmit Port 1 Q : %u \n",numTx0Entries);
- printf("Transmit Port 2 Q : %u \n",numTx1Entries);
-#ifdef __ixp46X
- printf("Transmit Port 3 Q : %u \n",numTx2Entries);
-#endif
- printf("Transmit Done Q : %u \n",numTxDoneEntries);
- printf("Receive Q : %u \n",numRxEntries);
- printf("Receive Free Port 1 Q : %u \n",numRxFree0Entries);
- printf("Receive Free Port 2 Q : %u \n",numRxFree1Entries);
-#ifdef __ixp46X
- printf("Receive Free Port 3 Q : %u \n",numRxFree2Entries);
-#endif
-
-#ifndef NDEBUG
- printf("\n");
- printf("# Total Buffers accounted for : %u\n",
- totalBuffers);
-
- numBuffersInSwQ = ixEthAccDataStats.addToSwQ -
- ixEthAccDataStats.removeFromSwQ;
-
- printf(" Buffers in S/W Qs : %u\n",
- numBuffersInSwQ);
- printf(" Buffers in H/W Qs or NPEs : %u\n",
- totalBuffers - numBuffersInSwQ);
-#endif
-
- printf("Rx QoS Discipline : %s\n",
- (ixEthAccDataInfo.schDiscipline ==
- FIFO_PRIORITY ) ? "Enabled" : "Disabled");
-
- for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++)
- {
- printf("Tx QoS Discipline port %u : %s\n",
- portId,
- (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline ==
- FIFO_PRIORITY ) ? "Enabled" : "Disabled");
- }
- printf("\n");
-}
-
-
-
-
-
diff --git a/drivers/net/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c
deleted file mode 100644
index 65113448d2..0000000000
--- a/drivers/net/npe/IxEthAccMac.c
+++ /dev/null
@@ -1,2617 +0,0 @@
-/**
- * @file IxEthAccMac.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MAC control functions
- *
- * Design Notes:
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxNpeMh.h"
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
-#include "IxEthDB.h"
-#endif
-#include "IxEthDBPortDefs.h"
-#include "IxEthNpe.h"
-#include "IxEthAcc.h"
-#include "IxEthAccDataPlane_p.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-
-/* Maximum number of retries during ixEthAccPortDisable, which
- * is approximately 10 seconds
-*/
-#define IX_ETH_ACC_MAX_RETRY 500
-
-/* Maximum number of retries during ixEthAccPortDisable when expecting
- * timeout
- */
-#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5
-
-#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \
- do \
- { \
- if(!IX_ETH_ACC_IS_PORT_VALID(portId)) \
- { \
- return IX_ETH_ACC_INVALID_PORT; \
- } \
- } while(0)
-
-PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*Forward function declarations*/
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-
-PRIVATE void
-ixEthAccPortDisableTxDone (UINT32 cbTag,
- IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag,
- IX_OSAL_MBUF *mbuf);
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF * mBufPtr,
- UINT32 learnedPortId);
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF **mBufPtr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr);
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg);
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId);
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
- IxEthAccMacAddr *macAddr2);
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m);
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId);
-
-IxEthAccStatus
-ixEthAccMacMemInit(void)
-{
- ixEthAccMacBase[IX_ETH_PORT_1] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE,
- IX_OSAL_IXP400_ETHA_MAP_SIZE);
- ixEthAccMacBase[IX_ETH_PORT_2] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE,
- IX_OSAL_IXP400_ETHB_MAP_SIZE);
-#ifdef __ixp46X
- ixEthAccMacBase[IX_ETH_PORT_3] =
- (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE,
- IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE);
- if (ixEthAccMacBase[IX_ETH_PORT_3] == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MAC I/O memory\n",
- 0, 0, 0, 0, 0 ,0);
-
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- if (ixEthAccMacBase[IX_ETH_PORT_1] == 0
- || ixEthAccMacBase[IX_ETH_PORT_2] == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MAC I/O memory\n",
- 0, 0, 0, 0, 0 ,0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMacUnload(void)
-{
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]);
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]);
-#ifdef __ixp46X
- IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]);
- ixEthAccMacBase[IX_ETH_PORT_3] = 0;
-#endif
- ixEthAccMacBase[IX_ETH_PORT_2] = 0;
- ixEthAccMacBase[IX_ETH_PORT_1] = 0;
-}
-
-IxEthAccStatus
-ixEthAccPortEnablePriv(IxEthAccPortId portId)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL)
- {
- /* TxDone callback not registered */
- printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL)
- && (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL))
- {
- /* Receive callback not registered */
- printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if(!ixEthAccMacState[portId].initDone)
- {
- printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId);
- return (IX_ETH_ACC_MAC_UNINITIALIZED);
- }
-
- /* if the state is being set to what it is already at, do nothing*/
- if (ixEthAccMacState[portId].enabled)
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* enable ethernet database for this port */
- if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS)
- {
- printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId);
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- /* set the MAC core registers */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL2,
- IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RANDOM_SEED,
- IX_ETH_ACC_RANDOM_SEED_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_THRESH_P_EMPTY,
- IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_THRESH_P_FULL,
- IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_DEFER,
- IX_ETH_ACC_MAC_TX_DEFER_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_TWO_DEFER_1,
- IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_TWO_DEFER_2,
- IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_SLOT_TIME,
- IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_BUF_SIZE_TX,
- IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- IX_ETH_ACC_TX_CNTRL1_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- IX_ETH_ACC_RX_CNTRL1_DEFAULT);
-
- /* set the global state */
- ixEthAccMacState[portId].portDisableState = ACTIVE;
- ixEthAccMacState[portId].enabled = true;
-
- /* rewrite the setup (including mac filtering) depending
- * on current options
- */
- ixEthAccMacStateUpdate(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/*
- * PortDisable local variables. They contain the intermediate steps
- * while the port is being disabled and the buffers being drained out
- * of the NPE.
- */
-typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback);
-static IxEthAccPortRxCallback
-ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortMultiBufferRxCallback
-ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static IxEthAccPortDisableRx
-ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static IxEthAccPortTxDoneCallback
-ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS];
-static UINT32
-ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-static UINT32
-ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS];
-
-/*
- * PortDisable private callbacks functions. They handle the user
- * traffic, and the special buffers (one for tx, one for rx) used
- * in portDisable.
- */
-PRIVATE void
-ixEthAccPortDisableTxDone(UINT32 cbTag,
- IX_OSAL_MBUF *mbuf)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
- /* check for the special mbuf used in portDisable */
- if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr)
- {
- *txState = TRANSMIT_DONE;
- }
- else
- {
- /* increment the count of user traffic during portDisable */
- ixEthAccPortDisableUserBufferCount[portId]++;
-
- /* call client TxDone function */
- ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf);
- }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryTransmit(UINT32 portId)
-{
- int key;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
- /* transmit the special buffer again if it is transmitted
- * and update the txState
- * This section is protected because the portDisable context
- * run an identical code, so the system keeps transmitting at the
- * maximum rate.
- */
- key = ixOsalIrqLock();
- if (*txState == TRANSMIT_DONE)
- {
- IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr;
- *txState = TRANSMIT;
- status = ixEthAccPortTxFrameSubmit(portId,
- mbufTxPtr,
- IX_ETH_ACC_TX_DEFAULT_PRIORITY);
- }
- ixOsalIrqUnlock(key);
-
- return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag,
- IX_OSAL_MBUF *mbuf)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- /* call the callback which forwards the traffic to the client */
- ixEthAccPortDisableTxDone(cbTag, mbuf);
-
- /* try to transmit the buffer used in portDisable
- * if seen in TxDone
- */
- ixEthAccPortDisableTryTransmit(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRx (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback)
-{
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- IX_OSAL_MBUF *mNextPtr;
-
- while (mBufPtr)
- {
- mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr);
- IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL;
-
- /* check for the special mbuf used in portDisable */
- if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr)
- {
- *rxState = RECEIVE;
- }
- else
- {
- /* increment the count of user traffic during portDisable */
- ixEthAccPortDisableUserBufferCount[portId]++;
-
- /* reset the received payload length during portDisable */
- IX_OSAL_MBUF_MLEN(mBufPtr) = 0;
- IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0;
-
- if (useMultiBufferCallback)
- {
- /* call the user callback with one unchained
- * buffer, without payload. A small array is built
- * to be used as a parameter (the user callback expects
- * to receive an array ended by a NULL pointer.
- */
- IX_OSAL_MBUF *mBufPtrArray[2];
-
- mBufPtrArray[0] = mBufPtr;
- mBufPtrArray[1] = NULL;
- ixEthAccPortDisableMultiBufferFn[portId](
- ixEthAccPortDisableMultiBufferCbTag[portId],
- mBufPtrArray);
- }
- else
- {
- /* call the user callback with a unchained
- * buffer, without payload and the destination port is
- * unknown.
- */
- ixEthAccPortDisableFn[portId](
- ixEthAccPortDisableCbTag[portId],
- mBufPtr,
- IX_ETH_DB_UNKNOWN_PORT /* port not found */);
- }
- }
-
- mBufPtr = mNextPtr;
- }
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortDisableTryReplenish(UINT32 portId)
-{
- int key;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- /* replenish with the special buffer again if it is received
- * and update the rxState
- * This section is protected because the portDisable context
- * run an identical code, so the system keeps replenishing at the
- * maximum rate.
- */
- key = ixOsalIrqLock();
- if (*rxState == RECEIVE)
- {
- IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr;
- *rxState = REPLENISH;
- IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
- status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr);
- }
- ixOsalIrqUnlock(key);
-
- return status;
-}
-
-PRIVATE void
-ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId,
- IX_OSAL_MBUF * mBufPtr,
- BOOL useMultiBufferCallback)
-{
- /* call the callback which forwards the traffic to the client */
- ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback);
-
- /* try to replenish with the buffer used in portDisable
- * if seen in Rx
- */
- ixEthAccPortDisableTryReplenish(portId);
-}
-
-PRIVATE void
-ixEthAccPortDisableRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF * mBufPtr,
- UINT32 learnedPortId)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- /* call the portDisable receive callback */
- (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false);
-}
-
-PRIVATE void
-ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag,
- IX_OSAL_MBUF **mBufPtr)
-{
- IxEthAccPortId portId = (IxEthAccPortId)cbTag;
-
- while (*mBufPtr)
- {
- /* call the portDisable receive callback with one buffer at a time */
- (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true);
- }
-}
-
-IxEthAccStatus
-ixEthAccPortDisablePriv(IxEthAccPortId portId)
-{
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
- int key;
- int retry, retryTimeout;
- volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState;
- volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState;
- volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* if the state is being set to what it is already at, do nothing */
- if (!ixEthAccMacState[portId].enabled)
- {
- return IX_ETH_ACC_SUCCESS;
- }
-
- *state = DISABLED;
-
- /* disable MAC receive first */
- ixEthAccPortRxDisablePriv(portId);
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* disable ethernet database for this port - It is done now to avoid
- * issuing ELT maintenance after requesting 'port disable' in an NPE
- */
- if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0);
- }
-#endif
-
- /* enter the critical section */
- key = ixOsalIrqLock();
-
- /* swap the Rx and TxDone callbacks */
- ixEthAccPortDisableFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn;
- ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn;
- ixEthAccPortDisableCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag;
- ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag;
- ixEthAccPortDisableTxDoneFn[portId] = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn;
- ixEthAccPortDisableTxDoneCbTag[portId] = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag;
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx;
-
- /* register temporary callbacks */
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableRxCallback;
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = portId;
-
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback;
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId;
-
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDone;
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = portId;
-
- /* initialise the Rx state and Tx states */
- *txState = TRANSMIT_DONE;
- *rxState = RECEIVE;
-
- /* exit the critical section */
- ixOsalIrqUnlock(key);
-
- /* enable a NPE loopback */
- if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
-
- if (status == IX_ETH_ACC_SUCCESS)
- {
- retry = 0;
-
- /* Step 1 : Drain Tx traffic and TxDone queues :
- *
- * Transmit and replenish at least once with the
- * special buffers until both of them are seen
- * in the callback hook
- *
- * (the receive callback keeps replenishing, so once we see
- * the special Tx buffer, we can be sure that Tx drain is complete)
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRxAndReplenish;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDone;
-
- do
- {
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* keep transmitting */
- status = ixEthAccPortDisableTryTransmit(portId);
- }
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && (*txState == TRANSMIT));
-
- /* Step 2 : Drain Rx traffic, RxFree and Rx queues :
- *
- * Transmit and replenish at least once with the
- * special buffers until both of them are seen
- * in the callback hook
- * (the transmit callback keeps transmitting, and when we see
- * the special Rx buffer, we can be sure that rxFree drain
- * is complete)
- *
- * The nested loop helps to retry if the user was keeping
- * replenishing or transmitting during portDisable.
- *
- * The 2 nested loops ensure more retries if user traffic is
- * seen during portDisable : the user should not replenish
- * or transmit while portDisable is running. However, because of
- * the queueing possibilities in ethAcc dataplane, it is possible
- * that a lot of traffic is left in the queues (e.g. when
- * transmitting over a low speed link) and therefore, more
- * retries are allowed to help flushing the buffers out.
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRx;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDoneAndSubmit;
-
- do
- {
- do
- {
- ixEthAccPortDisableUserBufferCount[portId] = 0;
-
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* keep transmitting */
- status = ixEthAccPortDisableTryTransmit(portId);
- }
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && ((ixEthAccPortDisableUserBufferCount[portId] != 0)
- || (*rxState == REPLENISH)));
-
- /* After the first iteration, change the receive callbacks,
- * to process only 1 buffer at a time
- */
- ixEthAccPortDisableRxTable[portId]
- = ixEthAccPortDisableRx;
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn
- = ixEthAccPortDisableTxDone;
-
- /* repeat the whole process while user traffic is seen in TxDone
- *
- * The conditions to stop the loop are
- * - Xscale has both Rx and Tx special buffers
- * (txState = transmit, rxState = receive)
- * - any error in txSubmit or rxReplenish
- * - no user traffic seen
- * - an excessive amount of retries
- */
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry < IX_ETH_ACC_MAX_RETRY)
- && (*txState == TRANSMIT));
-
- /* check the loop exit conditions. The NPE should not hold
- * the special buffers.
- */
- if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
- {
- status = IX_ETH_ACC_FAIL;
- }
-
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* Step 3 : Replenish without transmitting until a timeout
- * occurs, in order to drain the internal NPE fifos
- *
- * we can expect a few frames srill held
- * in the NPE.
- *
- * The 2 nested loops take care about the NPE dropping traffic
- * (including loopback traffic) when the Rx queue is full.
- *
- * The timeout value is very conservative
- * since the loopback used keeps replenishhing.
- *
- */
- do
- {
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish;
- ixEthAccPortDisableUserBufferCount[portId] = 0;
- retryTimeout = 0;
- do
- {
- /* keep replenishing */
- status = ixEthAccPortDisableTryReplenish(portId);
- if (status == IX_ETH_ACC_SUCCESS)
- {
- /* wait for some traffic being processed */
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
-
- /* Step 4 : Transmit once. Stop replenish
- *
- * After the Rx timeout, we are sure that the NPE does not
- * hold any frame in its internal NPE fifos.
- *
- * At this point, the NPE still holds the last rxFree buffer.
- * By transmitting a single frame, this should unblock the
- * last rxFree buffer. This code just transmit once and
- * wait for both frames seen in TxDone and in rxFree.
- *
- */
- ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx;
- status = ixEthAccPortDisableTryTransmit(portId);
-
- /* the NPE should immediatelyt release
- * the last Rx buffer and the last transmitted buffer
- * unless the last Tx frame was dropped (rx queue full)
- */
- if (status == IX_ETH_ACC_SUCCESS)
- {
- retryTimeout = 0;
- do
- {
- ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS);
- }
- while ((*rxState == REPLENISH)
- && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT));
- }
-
- /* the NPE may have dropped the traffic because of Rx
- * queue being full. This code ensures that the last
- * Tx and Rx frames are both received.
- */
- }
- while ((status == IX_ETH_ACC_SUCCESS)
- && (retry++ < IX_ETH_ACC_MAX_RETRY)
- && ((*txState == TRANSMIT)
- || (*rxState == REPLENISH)
- || (ixEthAccPortDisableUserBufferCount[portId] != 0)));
-
- /* Step 5 : check the final states : the NPE has
- * no buffer left, nor in Tx , nor in Rx directions.
- */
- if ((*rxState == REPLENISH) || (*txState == TRANSMIT))
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- /* now all the buffers are drained, disable NPE loopback
- * This is done regardless of the logic to drain the queues and
- * the internal buffers held by the NPE.
- */
- if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- /* disable MAC Tx and Rx services */
- ixEthAccMacState[portId].enabled = false;
- ixEthAccMacStateUpdate(portId);
-
- /* restore the Rx and TxDone callbacks (within a critical section) */
- key = ixOsalIrqLock();
-
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableFn[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = ixEthAccPortDisableCbTag[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId];
- ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId];
- ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDoneFn[portId];
- ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = ixEthAccPortDisableTxDoneCbTag[portId];
-
- ixOsalIrqUnlock(key);
-
- /* the MAC core rx/tx disable may left the MAC hardware in an
- * unpredictable state. A hw reset is executed before resetting
- * all the MAC parameters to a known value.
- */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- /* rewrite all parameters to their current value */
- ixEthAccMacStateUpdate(portId);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0);
-
- /* Since Eth NPE is not available, port must be disabled */
- *enabled = false ;
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- /* Since Eth NPE is not available, port must be disabled */
- *enabled = false ;
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- *enabled = ixEthAccMacState[portId].enabled;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMacResetPriv(IxEthAccPortId portId)
-{
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- /* rewrite all parameters to their current value */
- ixEthAccMacStateUpdate(portId);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackEnable(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE void
-ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n",
- (UINT32) portId, 0, 0, 0, 0, 0);
-
- return;
- }
-#endif
-
- /* unlock message reception mutex */
- ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId)
-{
- IX_STATUS npeMhStatus;
- IxNpeMhMessage message;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* enable NPE loopback (lsb of the message contains the value 1) */
- message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL)
- | 0x01;
- message.data[1] = 0;
-
- npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_SETLOOPBACK_MODE_ACK,
- ixEthAccNpeLoopbackMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT);
-
- if (npeMhStatus != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- else
- {
- /* wait for NPE loopbackEnable response */
- if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock,
- IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
- != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxEnablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxEnablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortLoopbackDisable(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*disable MAC loopabck */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId)
-{
- IX_STATUS npeMhStatus;
- IxNpeMhMessage message;
- IxEthAccStatus status = IX_ETH_ACC_SUCCESS;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* disable NPE loopback (lsb of the message contains the value 0) */
- message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL);
- message.data[1] = 0;
-
- npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_SETLOOPBACK_MODE_ACK,
- ixEthAccNpeLoopbackMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT);
-
- if (npeMhStatus != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- else
- {
- /* wait for NPE loopbackEnable response */
- if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock,
- IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS)
- != IX_SUCCESS)
- {
- status = IX_ETH_ACC_FAIL;
- }
- }
-
- return status;
-}
-
-IxEthAccStatus
-ixEthAccPortTxDisablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxDisablePriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* read register */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- /* update register */
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN));
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /* Turn off promiscuous mode */
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*set bit 5 of Rx control 1 - enable address filtering*/
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
- ixEthAccMacState[portId].promiscuous = false;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*
- * Set bit 5 of Rx control 1 - We enable address filtering even in
- * promiscuous mode because we want the MAC to set the appropriate
- * bits in m_flags which doesn't happen if we turn off filtering.
- */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN);
-
- ixEthAccMacState[portId].promiscuous = true;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
-
- if (macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT )
- {
- /* This is a multicast/broadcast address cant set it ! */
- return IX_ETH_ACC_FAIL;
- }
-
- if ( macAddr->macAddress[0] == 0 &&
- macAddr->macAddress[1] == 0 &&
- macAddr->macAddress[2] == 0 &&
- macAddr->macAddress[3] == 0 &&
- macAddr->macAddress[4] == 0 &&
- macAddr->macAddress[5] == 0 )
- {
- /* This is an invalid mac address cant set it ! */
- return IX_ETH_ACC_FAIL;
- }
-
-#ifdef CONFIG_IXP425_COMPONENT_ETHDB
- /* update the MAC address in the ethernet database */
- if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-#endif
-
- /*Set the Unicast MAC to the specified value*/
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- ixEthAccMacState[portId].initDone = true;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Unicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- macAddr->macAddress[i] = 0;
- }
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if(!ixEthAccMacState[portId].initDone)
- {
- return (IX_ETH_ACC_MAC_UNINITIALIZED);
- }
-
- if (macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Multicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-PRIVATE IxEthAccStatus
-ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- /*Return the current value of the Multicast MAC from h/w
- for the specified port*/
- UINT32 i;
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_MASK_1 + i*sizeof(UINT32),
- macAddr->macAddress[i]);
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
- IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Check that the mac address is valid*/
- if(macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /* Check that this is a multicast address */
- if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT))
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /* We don't add the Broadcast address */
- if(ixEthAccMacEqual(&broadcastAddr, macAddr))
- {
- return IX_ETH_ACC_FAIL;
- }
-
- for (i = 0;
- i<ixEthAccMacState[portId].mcastAddrIndex;
- i++)
- {
- /*Check if the current entry already match an existing matches*/
- if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i], macAddr))
- {
- /* Address found in the list and already configured,
- * return a success status
- */
- return IX_ETH_ACC_SUCCESS;
- }
- }
-
- /* check for availability at the end of the current table */
- if(ixEthAccMacState[portId].mcastAddrIndex >= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- /*First add the address to the multicast table for the
- specified port*/
- i=ixEthAccMacState[portId].mcastAddrIndex;
-
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
- &macAddr->macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /*Increment the index into the table, this must be done here
- as MulticastAddressSet below needs to know about the latest
- entry.
- */
- ixEthAccMacState[portId].mcastAddrIndex++;
-
- /*Then calculate the new value to be written to the address and
- address mask registers*/
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId)
-{
- IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /* remove all entries from the database and
- * insert a multicast entry
- */
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0],
- &mcastMacAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- ixEthAccMacState[portId].mcastAddrIndex = 1;
- ixEthAccMacState[portId].joinAll = true;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId,
- IxEthAccMacAddr *macAddr)
-{
- UINT32 i;
- IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Check that the mac address is valid*/
- if(macAddr == NULL)
- {
- return IX_ETH_ACC_FAIL;
- }
- /* Remove this mac address from the mask for the specified port
- * we copy down all entries above the blanked entry, and
- * decrement the index
- */
- i=0;
-
- while(i<ixEthAccMacState[portId].mcastAddrIndex)
- {
- /*Check if the current entry matches*/
- if(ixEthAccMacEqual(&ixEthAccMacState[portId].mcastAddrsTable[i],
- macAddr))
- {
- if(ixEthAccMacEqual(macAddr, &mcastMacAddr))
- {
- ixEthAccMacState[portId].joinAll = false;
- }
- /*Decrement the index into the multicast address table
- for the current port*/
- ixEthAccMacState[portId].mcastAddrIndex--;
-
- /*Copy down all entries above the current entry*/
- while(i<ixEthAccMacState[portId].mcastAddrIndex)
- {
- memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i],
- &ixEthAccMacState[portId].mcastAddrsTable[i+1],
- IX_IEEE803_MAC_ADDRESS_SIZE);
- i++;
- }
- /*recalculate the mask and write it to the MAC*/
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
- }
- /* search the next entry */
- i++;
- }
- /* no matching entry found */
- return IX_ETH_ACC_NO_SUCH_ADDR;
-}
-
-IxEthAccStatus
-ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId)
-{
- /*Check that the port parameter is valid*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave all Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- ixEthAccMacState[portId].mcastAddrIndex = 0;
- ixEthAccMacState[portId].joinAll = false;
-
- ixEthAccMulticastAddressSet(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-IxEthAccStatus
-ixEthAccPortUnicastAddressShowPriv (IxEthAccPortId portId)
-{
- IxEthAccMacAddr macAddr;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Unicast Address.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- /*Get the MAC (UINICAST) address from hardware*/
- if(ixEthAccPortUnicastMacAddressGetPriv(portId, &macAddr) != IX_ETH_ACC_SUCCESS)
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: MAC address uninitialised port %u\n",
- (INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_MAC_UNINITIALIZED;
- }
-
- /*print it out*/
- ixEthAccMacPrint(&macAddr);
- printf("\n");
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-void
-ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId)
-{
- IxEthAccMacAddr macAddr;
- UINT32 i;
-
- if(!IX_ETH_ACC_IS_PORT_VALID(portId))
- {
- return;
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot show Multicast Address.\n",(INT32)portId,0,0,0,0,0);
- return ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return;
- }
-
- printf("Multicast MAC: ");
- /*Get the MAC (MULTICAST) address from hardware*/
- ixEthAccPortMulticastMacAddressGet(portId, &macAddr);
- /*print it out*/
- ixEthAccMacPrint(&macAddr);
- /*Get the MAC (MULTICAST) filter from hardware*/
- ixEthAccPortMulticastMacFilterGet(portId, &macAddr);
- /*print it out*/
- printf(" ( ");
- ixEthAccMacPrint(&macAddr);
- printf(" )\n");
- printf("Constituent Addresses:\n");
- for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
- {
- ixEthAccMacPrint(&ixEthAccMacState[portId].mcastAddrsTable[i]);
- printf("\n");
- }
- return;
-}
-
-/*Set the duplex mode*/
-IxEthAccStatus
-ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId,
- IxEthAccDuplexMode mode)
-{
- UINT32 txregval;
- UINT32 rxregval;
-
- /*This is bit 1 of the transmit control reg, set to 1 for half
- duplex, 0 for full duplex*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval);
-
- if (mode == IX_ETH_ACC_FULL_DUPLEX)
- {
- /*Clear half duplex bit in TX*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval & ~IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
- /*We must set the pause enable in the receive logic when in
- full duplex mode*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
- ixEthAccMacState[portId].fullDuplex = true;
-
- }
- else if (mode == IX_ETH_ACC_HALF_DUPLEX)
- {
- /*Set half duplex bit in TX*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- txregval | IX_ETH_ACC_TX_CNTRL1_DUPLEX);
-
- /*We must clear pause enable in the receive logic when in
- half duplex mode*/
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN);
-
- ixEthAccMacState[portId].fullDuplex = false;
- }
- else
- {
- return IX_ETH_ACC_FAIL;
- }
-
-
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortDuplexModeGetPriv (IxEthAccPortId portId,
- IxEthAccDuplexMode *mode)
-{
- /*Return the duplex mode for the specified port*/
- UINT32 regval;
-
- /*This is bit 1 of the transmit control reg, set to 1 for half
- duplex, 0 for full duplex*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Duplex Mode.\n",(INT32)portId,0,0,0,0,0);
- /* return hald duplex */
- *mode = IX_ETH_ACC_HALF_DUPLEX ;
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- if (mode == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- if( regval & IX_ETH_ACC_TX_CNTRL1_DUPLEX)
- {
- *mode = IX_ETH_ACC_HALF_DUPLEX;
- }
- else
- {
- *mode = IX_ETH_ACC_FULL_DUPLEX;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
- /*Enable FCS computation by the MAC and appending to the
- frame*/
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval |
- IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
- ixEthAccMacState[portId].txPADAppend = true;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*disable FCS computation and appending*/
- /*Set bit 4 of Tx control register one to zero*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disble Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);
-
- ixEthAccMacState[portId].txPADAppend = false;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*Enable FCS computation by the MAC and appending to the
- frame*/
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
- ixEthAccMacState[portId].txFCSAppend = true;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*disable FCS computation and appending*/
- /*Set bit 4 of Tx control register one to zero*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);
-
- ixEthAccMacState[portId].txFCSAppend = false;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId)
-{
- /*Set bit 2 of Rx control 1*/
- UINT32 regval;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
- ixEthAccMacState[portId].rxFCSAppend = true;
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId)
-{
- UINT32 regval;
-
- /*Clear bit 2 of Rx control 1*/
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);
-
- ixEthAccMacState[portId].rxFCSAppend = false;
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-
-PRIVATE void
-ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG(
- "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /*Unblock Stats Get call*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock);
-
-}
-
-PRIVATE void
-ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats)
-{
- /* endianness conversion */
-
- /* Rx stats */
- retStats->dot3StatsAlignmentErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors);
- retStats->dot3StatsFCSErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors);
- retStats->dot3StatsInternalMacReceiveErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors);
- retStats->RxOverrunDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards);
- retStats->RxLearnedEntryDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards);
- retStats->RxLargeFramesDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards);
- retStats->RxSTPBlockedDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards);
- retStats->RxVLANTypeFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards);
- retStats->RxVLANIdFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards);
- retStats->RxInvalidSourceDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards);
- retStats->RxBlackListDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards);
- retStats->RxWhiteListDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards);
- retStats->RxUnderflowEntryDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards);
-
- /* Tx stats */
- retStats->dot3StatsSingleCollisionFrames =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames);
- retStats->dot3StatsMultipleCollisionFrames =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames);
- retStats->dot3StatsDeferredTransmissions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions);
- retStats->dot3StatsLateCollisions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions);
- retStats->dot3StatsExcessiveCollsions =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions);
- retStats->dot3StatsInternalMacTransmitErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors);
- retStats->dot3StatsCarrierSenseErrors =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors);
- retStats->TxLargeFrameDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards);
- retStats->TxVLANIdFilterDiscards =
- IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards);
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsGet (IxEthAccPortId portId,
- IxEthEthObjStats *retStats )
-{
- IxNpeMhMessage message;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (retStats == NULL)
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId);
-
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
-
- /* Return all zero stats */
- IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
- message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
- message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
- /* Permit only one task to request MIB statistics Get operation
- at a time */
- ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER);
-
- if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_GETSTATS,
- ixEthAccMacNpeStatsMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT)
- != IX_SUCCESS)
- {
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- printf("EthAcc: (Mac) StatsGet failed to send NPE message\n");
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* Wait for callback invocation indicating response to
- this request - we need this mutex in order to ensure
- that the return from this function is synchronous */
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
- /* Permit other tasks to perform MIB statistics Get operation */
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- ixEthAccMibIIStatsEndianConvert (retStats);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-PRIVATE void
-ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,
- IxNpeMhMessage msg)
-{
- IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);
-
-#ifndef NDEBUG
- /* Prudent to at least check the port is within range */
- if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)
- {
- IX_ETH_ACC_FATAL_LOG(
- "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n",
- (UINT32)portId, 0, 0, 0, 0, 0);
- return;
- }
-#endif
-
- /*Unblock Stats Get & reset call*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock);
-
-}
-
-
-
-IxEthAccStatus
-ixEthAccMibIIStatsGetClear (IxEthAccPortId portId,
- IxEthEthObjStats *retStats)
-{
- IxNpeMhMessage message;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (retStats == NULL)
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n");
- return (IX_ETH_ACC_FAIL);
- }
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId);
-
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0);
-
- /* Return all zero stats */
- IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));
-
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if (!IX_ETH_IS_PORT_INITIALIZED(portId))
- {
- printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId);
- return (IX_ETH_ACC_PORT_UNINITIALIZED);
- }
-
- IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));
-
- message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;
- message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);
-
- /* Permit only one task to request MIB statistics Get-Reset operation at a time */
- ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER);
-
- if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),
- message,
- IX_ETHNPE_RESETSTATS,
- ixEthAccMacNpeStatsResetMessageCallback,
- IX_NPEMH_SEND_RETRIES_DEFAULT)
- != IX_SUCCESS)
- {
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n");
-
- return IX_ETH_ACC_FAIL;
- }
-
- /* Wait for callback invocation indicating response to this request */
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);
-
- /* permit other tasks to get and reset MIB stats*/
- ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- ixEthAccMibIIStatsEndianConvert(retStats);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-IxEthAccStatus
-ixEthAccMibIIStatsClear (IxEthAccPortId portId)
-{
- static IxEthEthObjStats retStats;
- IxEthAccStatus status;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- /* there is no reset operation without a corresponding Get */
- status = ixEthAccMibIIStatsGetClear(portId, &retStats);
-
- return status;
-}
-
-/* Initialize the ethernet MAC settings */
-IxEthAccStatus
-ixEthAccMacInit(IxEthAccPortId portId)
-{
- IX_OSAL_MBUF_POOL* portDisablePool;
- UINT8 *data;
-
- IX_ETH_ACC_VALIDATE_PORT_ID(portId);
-
- if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))
- {
- IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0);
- return IX_ETH_ACC_SUCCESS ;
- }
-
- if(ixEthAccMacState[portId].macInitialised == false)
- {
- ixEthAccMacState[portId].fullDuplex = true;
- ixEthAccMacState[portId].rxFCSAppend = true;
- ixEthAccMacState[portId].txFCSAppend = true;
- ixEthAccMacState[portId].txPADAppend = true;
- ixEthAccMacState[portId].enabled = false;
- ixEthAccMacState[portId].promiscuous = true;
- ixEthAccMacState[portId].joinAll = false;
- ixEthAccMacState[portId].initDone = false;
- ixEthAccMacState[portId].macInitialised = true;
-
- /* initialize MIB stats mutexes */
- ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock);
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock);
- ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);
-
- ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock);
-
- ixEthAccMacState[portId].portDisableRxMbufPtr = NULL;
- ixEthAccMacState[portId].portDisableTxMbufPtr = NULL;
-
- portDisablePool = IX_OSAL_MBUF_POOL_INIT(2,
- IX_ETHACC_RX_MBUF_MIN_SIZE,
- "portDisable Pool");
-
- IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool");
-
- ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
- ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool);
-
- IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL,
- "Pool allocation failed");
- IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL,
- "Pool allocation failed");
- /* fill the payload of the Rx mbuf used in portDisable */
- IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE;
-
- memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr),
- 0xAA,
- IX_ETHACC_RX_MBUF_MIN_SIZE);
-
- /* fill the payload of the Tx mbuf used in portDisable (64 bytes) */
- IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
- IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64;
-
- data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr);
- memset(data, 0xBB, 64);
- data[0] = 0x00; /* unicast destination MAC address */
- data[6] = 0x00; /* unicast source MAC address */
- data[12] = 0x08; /* typelength : IP frame */
- data[13] = 0x00; /* typelength : IP frame */
-
- IX_OSAL_CACHE_FLUSH(data, 64);
- }
-
- IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_RESET);
-
- ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_CORE_CNTRL,
- IX_ETH_ACC_CORE_MDC_EN);
-
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_INT_CLK_THRESH,
- IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT);
-
- ixEthAccMacStateUpdate(portId);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/* PRIVATE Functions*/
-
-PRIVATE void
-ixEthAccMacStateUpdate(IxEthAccPortId portId)
-{
- UINT32 regval;
-
- if ( ixEthAccMacState[portId].enabled == false )
- {
- /* Just disable both the transmitter and reciver in the MAC. */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN);
- }
-
- if(ixEthAccMacState[portId].fullDuplex)
- {
- ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX);
- }
- else
- {
- ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX);
- }
-
- if(ixEthAccMacState[portId].rxFCSAppend)
- {
- ixEthAccPortRxFrameAppendFCSEnablePriv (portId);
- }
- else
- {
- ixEthAccPortRxFrameAppendFCSDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].txFCSAppend)
- {
- ixEthAccPortTxFrameAppendFCSEnablePriv (portId);
- }
- else
- {
- ixEthAccPortTxFrameAppendFCSDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].txPADAppend)
- {
- ixEthAccPortTxFrameAppendPaddingEnablePriv (portId);
- }
- else
- {
- ixEthAccPortTxFrameAppendPaddingDisablePriv (portId);
- }
-
- if(ixEthAccMacState[portId].promiscuous)
- {
- ixEthAccPortPromiscuousModeSetPriv(portId);
- }
- else
- {
- ixEthAccPortPromiscuousModeClearPriv(portId);
- }
-
- if ( ixEthAccMacState[portId].enabled == true )
- {
- /* Enable both the transmitter and reciver in the MAC. */
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_RX_CNTRL1,
- regval | IX_ETH_ACC_RX_CNTRL1_RX_EN);
-
- REG_READ(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_TX_CNTRL1,
- regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
- }
-}
-
-
-PRIVATE BOOL
-ixEthAccMacEqual(IxEthAccMacAddr *macAddr1,
- IxEthAccMacAddr *macAddr2)
-{
- UINT32 i;
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE; i++)
- {
- if(macAddr1->macAddress[i] != macAddr2->macAddress[i])
- {
- return false;
- }
- }
- return true;
-}
-
-PRIVATE void
-ixEthAccMacPrint(IxEthAccMacAddr *m)
-{
- printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x",
- m->macAddress[0], m->macAddress[1],
- m->macAddress[2], m->macAddress[3],
- m->macAddress[4], m->macAddress[5]);
-}
-
-/* Set the multicast address and address mask registers
- *
- * A bit in the address mask register must be set if
- * all multicast addresses always have that bit set, or if
- * all multicast addresses always have that bit cleared.
- *
- * A bit in the address register must be set if all multicast
- * addresses have that bit set, otherwise, it should be cleared
- */
-
-PRIVATE void
-ixEthAccMulticastAddressSet(IxEthAccPortId portId)
-{
- UINT32 i;
- UINT32 j;
- IxEthAccMacAddr addressMask;
- IxEthAccMacAddr address;
- IxEthAccMacAddr alwaysClearBits;
- IxEthAccMacAddr alwaysSetBits;
-
- /* calculate alwaysClearBits and alwaysSetBits:
- * alwaysClearBits is calculated by ORing all
- * multicast addresses, those bits that are always
- * clear are clear in the result
- *
- * alwaysSetBits is calculated by ANDing all
- * multicast addresses, those bits that are always set
- * are set in the result
- */
-
- if (ixEthAccMacState[portId].promiscuous == true)
- {
- /* Promiscuous Mode is set, and filtering
- * allow all packets, and enable the mcast and
- * bcast detection.
- */
- memset(&addressMask.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(&address.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else
- {
- if(ixEthAccMacState[portId].joinAll == true)
- {
- /* Join all is set. The mask and address are
- * the multicast settings.
- */
- IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}};
-
- memcpy(addressMask.macAddress,
- macAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memcpy(address.macAddress,
- macAddr.macAddress,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else if(ixEthAccMacState[portId].mcastAddrIndex == 0)
- {
- /* No entry in the filtering database,
- * Promiscuous Mode is cleared, Broadcast filtering
- * is configured.
- */
- memset(addressMask.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(address.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- }
- else
- {
- /* build a mask and an address which mix all entreis
- * from the list of multicast addresses
- */
- memset(alwaysClearBits.macAddress,
- 0,
- IX_IEEE803_MAC_ADDRESS_SIZE);
- memset(alwaysSetBits.macAddress,
- IX_ETH_ACC_MAC_ALL_BITS_SET,
- IX_IEEE803_MAC_ADDRESS_SIZE);
-
- for(i=0;i<ixEthAccMacState[portId].mcastAddrIndex;i++)
- {
- for(j=0;j<IX_IEEE803_MAC_ADDRESS_SIZE;j++)
- {
- alwaysClearBits.macAddress[j] |=
- ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
- alwaysSetBits.macAddress[j] &=
- ixEthAccMacState[portId].mcastAddrsTable[i].macAddress[j];
- }
- }
-
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- addressMask.macAddress[i] = alwaysSetBits.macAddress[i]
- | ~alwaysClearBits.macAddress[i];
- address.macAddress[i] = alwaysSetBits.macAddress[i];
- }
- }
- }
-
- /*write the new addr filtering to h/w*/
- for(i=0;i<IX_IEEE803_MAC_ADDRESS_SIZE;i++)
- {
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_MASK_1+i*sizeof(UINT32),
- addressMask.macAddress[i]);
- REG_WRITE(ixEthAccMacBase[portId],
- IX_ETH_ACC_MAC_ADDR_1+i*sizeof(UINT32),
- address.macAddress[i]);
- }
-}
diff --git a/drivers/net/npe/IxEthAccMii.c b/drivers/net/npe/IxEthAccMii.c
deleted file mode 100644
index bfe606f507..0000000000
--- a/drivers/net/npe/IxEthAccMii.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/**
- * @file IxEthAccMii.c
- *
- * @author Intel Corporation
- * @date
- *
- * @brief MII control functions
- *
- * Design Notes:
- *
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxOsal.h"
-#include "IxEthAcc.h"
-#include "IxEthAcc_p.h"
-#include "IxEthAccMac_p.h"
-#include "IxEthAccMii_p.h"
-
-
-PRIVATE UINT32 miiBaseAddressVirt;
-PRIVATE IxOsalMutex miiAccessLock;
-
-PUBLIC UINT32 ixEthAccMiiRetryCount = IX_ETH_ACC_MII_TIMEOUT_10TH_SECS;
-PUBLIC UINT32 ixEthAccMiiAccessTimeout = IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS;
-
-/* -----------------------------------
- * private function prototypes
- */
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand);
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data);
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data);
-
-
-PRIVATE void
-ixEthAccMdioCmdWrite(UINT32 mdioCommand)
-{
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_1,
- mdioCommand & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_2,
- (mdioCommand >> 8) & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_3,
- (mdioCommand >> 16) & 0xff);
-
- REG_WRITE(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_4,
- (mdioCommand >> 24) & 0xff);
-}
-
-PRIVATE void
-ixEthAccMdioCmdRead(UINT32 *data)
-{
- UINT32 regval;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_1,
- regval);
-
- *data = regval & 0xff;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_2,
- regval);
-
- *data |= (regval & 0xff) << 8;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_3,
- regval);
-
- *data |= (regval & 0xff) << 16;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_CMD_4,
- regval);
-
- *data |= (regval & 0xff) << 24;
-
-}
-
-PRIVATE void
-ixEthAccMdioStatusRead(UINT32 *data)
-{
- UINT32 regval;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_1,
- regval);
-
- *data = regval & 0xff;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_2,
- regval);
-
- *data |= (regval & 0xff) << 8;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_3,
- regval);
-
- *data |= (regval & 0xff) << 16;
-
- REG_READ(miiBaseAddressVirt,
- IX_ETH_ACC_MAC_MDIO_STS_4,
- regval);
-
- *data |= (regval & 0xff) << 24;
-
-}
-
-
-/********************************************************************
- * ixEthAccMiiInit
- */
-IxEthAccStatus
-ixEthAccMiiInit()
-{
- if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS)
- {
- return IX_ETH_ACC_FAIL;
- }
-
- miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE);
-
- if (miiBaseAddressVirt == 0)
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthAcc: Could not map MII I/O mapped memory\n",
- 0, 0, 0, 0, 0, 0);
-
- return IX_ETH_ACC_FAIL;
- }
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-void
-ixEthAccMiiUnload(void)
-{
- IX_OSAL_MEM_UNMAP(miiBaseAddressVirt);
-
- miiBaseAddressVirt = 0;
-}
-
-PUBLIC IxEthAccStatus
-ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount)
-{
- if (retryCount < 1) return IX_ETH_ACC_FAIL;
-
- ixEthAccMiiRetryCount = retryCount;
- ixEthAccMiiAccessTimeout = timeout;
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-/*********************************************************************
- * ixEthAccMiiReadRtn - read a 16 bit value from a PHY
- */
-IxEthAccStatus
-ixEthAccMiiReadRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 *value)
-{
- UINT32 mdioCommand;
- UINT32 regval;
- UINT32 miiTimeout;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
- || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if (value == NULL)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
- | phyAddr << IX_ETH_ACC_MII_ADDR_SHL;
- mdioCommand |= IX_ETH_ACC_MII_GO;
-
- ixEthAccMdioCmdWrite(mdioCommand);
-
- miiTimeout = ixEthAccMiiRetryCount;
-
- while(miiTimeout)
- {
-
- ixEthAccMdioCmdRead(&regval);
-
- if((regval & IX_ETH_ACC_MII_GO) == 0x0)
- {
- break;
- }
- /* Sleep for a while */
- ixOsalSleep(ixEthAccMiiAccessTimeout);
- miiTimeout--;
- }
-
-
-
- if(miiTimeout == 0)
- {
- ixOsalMutexUnlock(&miiAccessLock);
- *value = 0xffff;
- return IX_ETH_ACC_FAIL;
- }
-
-
- ixEthAccMdioStatusRead(&regval);
- if(regval & IX_ETH_ACC_MII_READ_FAIL)
- {
- ixOsalMutexUnlock(&miiAccessLock);
- *value = 0xffff;
- return IX_ETH_ACC_FAIL;
- }
-
- *value = regval & 0xffff;
- ixOsalMutexUnlock(&miiAccessLock);
- return IX_ETH_ACC_SUCCESS;
-
-}
-
-
-/*********************************************************************
- * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY
- */
-IxEthAccStatus
-ixEthAccMiiWriteRtn (UINT8 phyAddr,
- UINT8 phyReg,
- UINT16 value)
-{
- UINT32 mdioCommand;
- UINT32 regval;
- UINT16 readVal;
- UINT32 miiTimeout;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
- || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- /* ensure that a PHY is present at this address */
- if(ixEthAccMiiReadRtn(phyAddr,
- IX_ETH_ACC_MII_CTRL_REG,
- &readVal) != IX_ETH_ACC_SUCCESS)
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
- | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ;
- mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value;
-
- ixEthAccMdioCmdWrite(mdioCommand);
-
- miiTimeout = ixEthAccMiiRetryCount;
-
- while(miiTimeout)
- {
-
- ixEthAccMdioCmdRead(&regval);
-
- /*The "GO" bit is reset to 0 when the write completes*/
- if((regval & IX_ETH_ACC_MII_GO) == 0x0)
- {
- break;
- }
- /* Sleep for a while */
- ixOsalSleep(ixEthAccMiiAccessTimeout);
- miiTimeout--;
- }
-
- ixOsalMutexUnlock(&miiAccessLock);
- if(miiTimeout == 0)
- {
- return IX_ETH_ACC_FAIL;
- }
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- * Phy query functions
- *
- */
-IxEthAccStatus
-ixEthAccMiiStatsShow (UINT32 phyAddr)
-{
- UINT16 regval;
- printf("Regisers on PHY at address 0x%x\n", phyAddr);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, &regval);
- printf(" Control Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, &regval);
- printf(" Status Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, &regval);
- printf(" PHY ID1 Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, &regval);
- printf(" PHY ID2 Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, &regval);
- printf(" Auto Neg ADS Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, &regval);
- printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, &regval);
- printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval);
- ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, &regval);
- printf(" Auto Neg Next Register : 0x%4.4x\n", regval);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
-
-/*****************************************************************
- *
- * Interface query functions
- *
- */
-IxEthAccStatus
-ixEthAccMdioShow (void)
-{
- UINT32 regval;
-
- if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
- {
- return (IX_ETH_ACC_FAIL);
- }
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- ixEthAccMdioCmdRead(&regval);
- ixOsalMutexUnlock(&miiAccessLock);
-
- printf("MDIO command register\n");
- printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31);
- printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26);
- printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f);
- printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f);
-
- ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
- ixEthAccMdioStatusRead(&regval);
- ixOsalMutexUnlock(&miiAccessLock);
-
- printf("MDIO status register\n");
- printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31);
- printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff);
-
- return IX_ETH_ACC_SUCCESS;
-}
-
diff --git a/drivers/net/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c
deleted file mode 100644
index 023cf50248..0000000000
--- a/drivers/net/npe/IxEthDBAPI.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxFeatureCtrl.h"
-
-extern HashTable dbHashtable;
-extern IxEthDBPortMap overflowUpdatePortList;
-extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, true);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- return ixEthDBTriggerAddPortUpdate(macAddr, portID, false);
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- /* build a remove event and place it on the event queue */
- return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID);
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBDatabaseMaintenance()
-{
- HashIterator iterator;
- UINT32 portIndex;
- BOOL agingRequired = false;
-
- /* ports who will have deleted records and therefore will need updating */
- IxEthDBPortMap triggerPorts;
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED !=
- ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
- return;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- /* check if there's at least a port that needs aging */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled)
- {
- agingRequired = true;
- }
- }
-
- if (agingRequired)
- {
- /* ask each NPE port to write back the database for aging inspection */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE
- && ixEthDBPortInfo[portIndex].agingEnabled
- && ixEthDBPortInfo[portIndex].enabled)
- {
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* send EDB_GetMACAddressDatabase message */
- FILL_GETMACADDRESSDATABASE(message,
- 0 /* unused */,
- IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* analyze NPE copy */
- ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE);
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex);
- }
- else
- {
- ixEthDBPortInfo[portIndex].agingEnabled = false;
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
- ixEthDBPortInfo[portIndex].updateMethod.userControlled = true;
-
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
- IX_OSAL_LOG_DEV_STDOUT,
- "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n",
- portIndex, 0, 0, 0, 0, 0);
-
- ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES);
- }
- }
- }
-
- /* browse database and age entries */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
- UINT32 *age = NULL;
- BOOL staticEntry = true;
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- age = &descriptor->recordData.filteringData.age;
- staticEntry = descriptor->recordData.filteringData.staticEntry;
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- age = &descriptor->recordData.filteringVlanData.age;
- staticEntry = descriptor->recordData.filteringVlanData.staticEntry;
- }
- else
- {
- staticEntry = true;
- }
-
- if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false))
- {
- /* manually increment the age if the port has no such capability */
- if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0)
- {
- *age += (IX_ETH_DB_MAINTENANCE_TIME / 60);
- }
-
- /* age entry if it exceeded the maximum time to live */
- if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60))
- {
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
-
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- /* update ports which lost records */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType)
-{
- IxEthDBPortMap triggerPorts;
- HashIterator iterator;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS)
- {
- return IX_ETH_DB_INVALID_PORT;
- }
-
- /* check if the user passes some extra bits */
- if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- /* browse database and age entries */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS))
- && ((descriptor->type & recordType) != 0))
- {
- /* add to trigger if automatic updates are required */
- if (ixEthDBPortUpdateRequired[descriptor->type])
- {
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID);
- }
-
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- /* update ports which lost records */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
- IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- if (((MacDescriptor *) (searchResult->data))->portID == portID)
- {
- result = IX_ETH_DB_SUCCESS; /* address and port match */
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- return result;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
-
- IX_ETH_DB_CHECK_REFERENCE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- /* return the port ID */
- *portID = ((MacDescriptor *) searchResult->data)->portID;
-
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- ixEthDBPortInfo[portID].agingEnabled = false;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING);
-
- ixEthDBPortInfo[portID].agingEnabled = true;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* return the port ID */
- *portID = descriptor->portID;
-
- /* reset entry age */
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- descriptor->recordData.filteringData.age = 0;
- }
- else
- {
- descriptor->recordData.filteringVlanData.age = 0;
- }
-
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- /* force bit at offset 255 to 0 (reserved) */
- dependencyPortMap[31] &= 0xFE;
-
- COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING);
-
- ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate;
- ixEthDBPortInfo[portID].updateMethod.userControlled = true;
-
- return IX_ETH_DB_SUCCESS;
-}
diff --git a/drivers/net/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c
deleted file mode 100644
index c265d942e0..0000000000
--- a/drivers/net/npe/IxEthDBAPISupport.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/**
- * @file IxEthDBAPISupport.c
- *
- * @brief Public API support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxEthDB.h>
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-#include "IxEthDBMessages_p.h"
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-#ifdef IX_UNIT_TEST
-
-int dbAccessCounter = 0;
-int overflowEvent = 0;
-
-#endif
-
-/*
- * External declaration
- */
-extern HashTable dbHashtable;
-
-/*
- * Internal declaration
- */
-IX_ETH_DB_PUBLIC
-PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS];
-
-IX_ETH_DB_PRIVATE
-struct
-{
- BOOL saved;
- IxEthDBPriorityTable priorityTable;
- IxEthDBVlanSet vlanMembership;
- IxEthDBVlanSet transmitTaggingInfo;
- IxEthDBFrameFilter frameFilter;
- IxEthDBTaggingAction taggingAction;
- IxEthDBFirewallMode firewallMode;
- BOOL stpBlocked;
- BOOL srcAddressFilterEnabled;
- UINT32 maxRxFrameSize;
- UINT32 maxTxFrameSize;
-} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS];
-
-#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518)
-
-/**
- * @brief initializes a port
- *
- * @param portID ID of the port to be initialized
- *
- * Note that redundant initializations are silently
- * dealt with and do not constitute an error
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBPortInit(IxEthDBPortId portID)
-{
- PortInfo *portInfo;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
- {
- return;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS)
- {
- WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID);
-
- return;
- }
-
- if (portInfo->initialized)
- {
- /* redundant */
- return;
- }
-
- /* initialize core fields */
- portInfo->portID = portID;
- SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID);
-
- /* default values */
- portInfo->agingEnabled = false;
- portInfo->enabled = false;
- portInfo->macAddressUploaded = false;
- portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
- portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE;
-
- /* default update control values */
- portInfo->updateMethod.searchTree = NULL;
- portInfo->updateMethod.searchTreePendingWrite = false;
- portInfo->updateMethod.treeInitialized = false;
- portInfo->updateMethod.updateEnabled = false;
- portInfo->updateMethod.userControlled = false;
-
- /* default WiFi parameters */
- memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid));
- portInfo->frameControlDurationID = 0;
-
- /* Ethernet NPE-specific initializations */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- /* update handler */
- portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler;
- }
-
- /* initialize state save */
- ixEthDBPortState[portID].saved = false;
-
- portInfo->initialized = true;
-}
-
-/**
- * @brief enables a port
- *
- * @param portID ID of the port to enable
- *
- * This function is fully documented in the main
- * header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if enabling was
- * accomplished, or a meaningful error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID)
-{
- IxEthDBPortMap triggerPorts;
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (portInfo->enabled)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- SET_DEPENDENCY_MAP(triggerPorts, portID);
-
- /* mark as enabled */
- portInfo->enabled = true;
-
- /* Operation stops here when Ethernet Learning is not enabled */
- if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
- ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- {
- return IX_ETH_DB_SUCCESS;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID);
-
- /* must use UnicastAddressSet() before enabling an NPE port */
- return IX_ETH_DB_MAC_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID);
-
- if (!portInfo->updateMethod.userControlled
- && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0))
- {
- portInfo->updateMethod.updateEnabled = true;
- }
-
- /* if this is first time initialization then we already have
- write access to the tree and can AccessRelease directly */
- if (!portInfo->updateMethod.treeInitialized)
- {
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID);
-
- /* create an initial tree and release access into it */
- ixEthDBUpdatePortLearningTrees(triggerPorts);
-
- /* mark tree as being initialized */
- portInfo->updateMethod.treeInitialized = true;
- }
- }
-
- if (ixEthDBPortState[portID].saved)
- {
- /* previous configuration data stored, restore state */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode);
- ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled);
- }
-
-#if 0 /* test-only */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter);
- ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction);
-
- ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo);
- ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership);
-
- ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable);
- }
-#endif
-
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked);
- }
-
- ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize);
- ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize);
-
- /* discard previous save */
- ixEthDBPortState[portID].saved = false;
- }
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief disables a port
- *
- * @param portID ID of the port to disable
- *
- * This function is fully documented in the
- * main header file, IxEthDB.h
- *
- * @return IX_ETH_DB_SUCCESS if disabling was
- * successful or an appropriate error message
- * otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID)
-{
- HashIterator iterator;
- IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */
- BOOL result;
- PortInfo *portInfo;
- IxEthDBFeature learningEnabled;
-#if 0 /* test-only */
- IxEthDBPriorityTable classZeroTable;
-#endif
-
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (!portInfo->enabled)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- /* save filtering state */
- ixEthDBPortState[portID].firewallMode = portInfo->firewallMode;
- ixEthDBPortState[portID].frameFilter = portInfo->frameFilter;
- ixEthDBPortState[portID].taggingAction = portInfo->taggingAction;
- ixEthDBPortState[portID].stpBlocked = portInfo->stpBlocked;
- ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled;
- ixEthDBPortState[portID].maxRxFrameSize = portInfo->maxRxFrameSize;
- ixEthDBPortState[portID].maxTxFrameSize = portInfo->maxTxFrameSize;
-
- memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet));
- memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet));
- memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable));
-
- ixEthDBPortState[portID].saved = true;
-
- /* now turn off all EthDB filtering features on the port */
-
-#if 0 /* test-only */
- /* VLAN & QoS */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
- ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false);
- ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH);
-
- memset(classZeroTable, 0, sizeof (classZeroTable));
- ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable);
- }
-#endif
-
- /* STP */
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false);
- }
-
- /* Firewall */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
- ixEthDBFirewallTableDownload((IxEthDBPortId) portID);
- ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false);
- }
-
- /* Frame size filter */
- ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE);
-
- /* WiFi */
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID);
- }
-
- /* save and disable the learning feature bit */
- learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING;
- portInfo->featureStatus &= ~IX_ETH_DB_LEARNING;
- }
- else
- {
- /* save the learning feature bit */
- learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING;
- }
-
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- ixEthDBUpdateLock();
-
- /* wipe out current entries for this port */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- /* check if the port match. If so, remove the entry */
- if (descriptor->portID == portID
- && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- && !descriptor->recordData.filteringData.staticEntry)
- {
- /* delete entry */
- BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator));
-
- /* add port to the set of update trigger ports */
- JOIN_PORT_TO_MAP(triggerPorts, portID);
- }
- else
- {
- /* move to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if (portInfo->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree);
- portInfo->updateMethod.searchTree = NULL;
- }
-
- ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD);
- }
-
- /* mark as disabled */
- portInfo->enabled = false;
-
- /* disable updates unless the user has specifically altered the default behavior */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if (!portInfo->updateMethod.userControlled)
- {
- portInfo->updateMethod.updateEnabled = false;
- }
-
- /* make sure we re-initialize the NPE learning tree when the port is re-enabled */
- portInfo->updateMethod.treeInitialized = false;
- }
-
- ixEthDBUpdateUnlock();
-
- /* restore learning feature bit */
- portInfo->featureStatus |= learningEnabled;
-
- /* if we've removed any records or lost any events make sure to force an update */
- IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts);
-
- if (!result)
- {
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends the updated maximum Tx/Rx frame lengths to the NPE
- *
- * @param portID ID of the port to update
- *
- * @return IX_ETH_DB_SUCCESS if the update completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IX_STATUS result;
-
- FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the port maximum Rx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumRxFrameSize maximum Rx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx frame size
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumTxFrameSize maximum Tx frame size
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the port maximum Tx and Rx frame sizes
- *
- * @param portID ID of the port to set the frame size on
- * @param maximumFrameSize maximum Tx and Rx frame sizes
- *
- * This function updates the internal data structures and
- * calls ixEthDBPortFrameLengthsUpdate() for NPE update.
- *
- * Note that both the maximum Tx and Rx frame size are set
- * to the same value. This function is kept for compatibility
- * reasons.
- *
- * This function is fully documented in the main header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation was
- * successfull or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) ||
- (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE))
- {
- return IX_ETH_DB_INVALID_ARG;
- }
- }
- else
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* update internal structure */
- ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize;
- ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize;
-
- /* update the maximum frame size in the NPE */
- return ixEthDBPortFrameLengthsUpdate(portID);
-}
-
-/**
- * @brief sets the MAC address of an NPE port
- *
- * @param portID port ID to set the MAC address on
- * @param macAddr pointer to the 6-byte MAC address
- *
- * This function is called by the EthAcc
- * ixEthAccUnicastMacAddressSet() and should not be
- * manually invoked unless required by special circumstances.
- *
- * @return IX_ETH_DB_SUCCESS if the operation succeeded
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* use this macro instead CHECK_PORT
- as the port doesn't need to be enabled */
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- if (!ixEthDBPortInfo[portID].initialized)
- {
- return IX_ETH_DB_PORT_UNINITIALIZED;
- }
-
- /* Operation stops here when Ethernet Learning is not enabled */
- if(IX_FEATURE_CTRL_SWCONFIG_DISABLED ==
- ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- {
- return IX_ETH_DB_SUCCESS;
- }
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- /* exit if the port is not an Ethernet NPE */
- if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
- {
- return IX_ETH_DB_INVALID_PORT;
- }
-
- /* populate message */
- FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress);
-
- IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID);
-
- /* send a SetPortAddress message */
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- ixEthDBPortInfo[portID].macAddressUploaded = true;
- }
-
- return result;
-}
diff --git a/drivers/net/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c
deleted file mode 100644
index 3d3050d5ce..0000000000
--- a/drivers/net/npe/IxEthDBCore.c
+++ /dev/null
@@ -1,439 +0,0 @@
-/**
- * @file IxEthDBDBCore.c
- *
- * @brief Database support functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* list of database hashtables */
-IX_ETH_DB_PUBLIC HashTable dbHashtable;
-IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1];
-IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-/* private initialization flag */
-IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false;
-
-/**
- * @brief initializes EthDB
- *
- * This function must be called to initialize the component.
- *
- * It does the following things:
- * - checks the port definition structure
- * - scans the capabilities of the NPE images and sets the
- * capabilities of the ports accordingly
- * - initializes the memory pools internally used in EthDB
- * for storing database records and handling data
- * - registers automatic update handlers for add and remove
- * operations
- * - registers hashing match functions, depending on key sets
- * - initializes the main database hashtable
- * - allocates contiguous memory zones to be used for NPE
- * updates
- * - registers the serialize methods used to convert data
- * into NPE-readable format
- * - starts the event processor
- *
- * Note that this function is documented in the public
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS or an appropriate error if the
- * component failed to initialize correctly
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBInit(void)
-{
- IxEthDBStatus result;
-
- if (ethDBInitializationComplete)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* trap an invalid port definition structure */
- IX_ETH_DB_PORTS_ASSERTION;
-
- /* memory management */
- ixEthDBInitMemoryPools();
-
- /* register hashing search methods */
- ixEthDBMatchMethodsRegister(matchFunctions);
-
- /* register type-based automatic port updates */
- ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired);
-
- /* register record to key type mappings */
- ixEthDBKeyTypeRegister(ixEthDBKeyType);
-
- /* hash table */
- ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor);
-
- /* NPE update zones */
- ixEthDBNPEUpdateAreasInit();
-
- /* register record serialization methods */
- ixEthDBRecordSerializeMethodsRegister();
-
- /* start the event processor */
- result = ixEthDBEventProcessorInit();
-
- /* scan NPE features */
- if (result == IX_ETH_DB_SUCCESS)
- {
- ixEthDBFeatureCapabilityScan();
- }
-
- ethDBInitializationComplete = true;
-
- return result;
-}
-
-/**
- * @brief prepares EthDB for unloading
- *
- * This function must be called before removing the
- * EthDB component from memory (e.g. doing rmmod in
- * Linux) if the component is to be re-initialized again
- * without rebooting the platform.
- *
- * All the EthDB ports must be disabled before this
- * function is to be called. Failure to disable all
- * the ports will return the IX_ETH_DB_BUSY error.
- *
- * This function will destroy mutexes, deallocate
- * memory and stop the event processor.
- *
- * Note that this function is fully documented in the
- * main component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if de-initialization
- * completed successfully or an appropriate error
- * message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUnload(void)
-{
- IxEthDBPortId portIndex;
-
- if (!ethDBInitializationComplete)
- {
- /* redundant */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* check if any ports are enabled */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortInfo[portIndex].enabled)
- {
- return IX_ETH_DB_BUSY;
- }
- }
-
- /* free port resources */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock);
- }
-
- ixEthDBPortInfo[portIndex].initialized = false;
- }
-
- /* shutdown event processor */
- ixEthDBStopLearningFunction();
-
- /* deallocate NPE update zones */
- ixEthDBNPEUpdateAreasUnload();
-
- ethDBInitializationComplete = false;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a new entry to the Ethernet database
- *
- * @param newRecordTemplate address of the record template to use
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * Creates a new database entry, populates it with the data
- * copied from the given template and adds the record to the
- * database hash table.
- * It also checks whether the new record type is registered to trigger
- * automatic updates; if it is, the update trigger will contain the
- * port on which the record insertion was performed, as well as the
- * old port in case the addition was a record migration (from one port
- * to the other). The caller can use the updateTrigger to trigger
- * automatic updates on the ports changed as a result of this addition.
- *
- * @retval IX_ETH_DB_SUCCESS addition successful
- * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool
- * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger)
-{
- IxEthDBStatus result;
- MacDescriptor *newDescriptor;
- IxEthDBPortId originalPortID;
- HashNode *node = NULL;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node));
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (node == NULL)
- {
- /* not found, create a new one */
- newDescriptor = ixEthDBAllocMacDescriptor();
-
- if (newDescriptor == NULL)
- {
- return IX_ETH_DB_NOMEM; /* no memory */
- }
-
- /* old port does not exist, avoid unnecessary updates */
- originalPortID = newRecordTemplate->portID;
- }
- else
- {
- /* a node with the same key exists, will update node */
- newDescriptor = (MacDescriptor *) node->data;
-
- /* save original port id */
- originalPortID = newDescriptor->portID;
- }
-
- /* copy/update fields into new record */
- memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr));
- memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData));
-
- newDescriptor->type = newRecordTemplate->type;
- newDescriptor->portID = newRecordTemplate->portID;
- newDescriptor->user = newRecordTemplate->user;
-
- if (node == NULL)
- {
- /* new record, insert into hashtable */
- BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result);
-
- if (result != IX_ETH_DB_SUCCESS)
- {
- ixEthDBFreeMacDescriptor(newDescriptor);
-
- return result; /* insertion failed */
- }
- }
-
- if (node != NULL)
- {
- /* release access */
- ixEthDBReleaseHashNode(node);
- }
-
- /* trigger add/remove update if required by type */
- if (updateTrigger != NULL &&
- ixEthDBPortUpdateRequired[newRecordTemplate->type])
- {
- /* add new port to update list */
- JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID);
-
- /* check if record has moved, we'll need to update the old port as well */
- if (originalPortID != newDescriptor->portID)
- {
- JOIN_PORT_TO_MAP(updateTrigger, originalPortID);
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief remove a record from the Ethernet database
- *
- * @param templateRecord template record used to determine
- * what record is to be removed
- * @param updateTrigger port map containing the update triggers
- * resulting from this update operation
- *
- * This function will examine the template record it receives
- * and attempts to delete a record of the same type and containing
- * the same keys as the template record. If deletion is successful
- * and the record type is registered for automatic port updates the
- * port will also be set in the updateTrigger port map, so that the
- * client can perform an update of the port.
- *
- * @retval IX_ETH_DB_SUCCESS removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found
- * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger)
-{
- IxEthDBStatus result;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result);
-
- if (result != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_NO_SUCH_ADDR; /* not found */
- }
-
- /* trigger add/remove update if required by type */
- if (updateTrigger != NULL
- &&ixEthDBPortUpdateRequired[templateRecord->type])
- {
- /* add new port to update list */
- JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID);
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief register record key types
- *
- * This function registers the appropriate key types,
- * depending on record types.
- *
- * All filtering records use the MAC address as the key.
- * WiFi and Firewall records use a compound key consisting
- * in both the MAC address and the port ID.
- *
- * @return the number of registered record types
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType)
-{
- /* safety */
- memset(keyType, 0, sizeof (keyType));
-
- /* register all known record types */
- keyType[IX_ETH_DB_FILTERING_RECORD] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY;
- keyType[IX_ETH_DB_WIFI_RECORD] = IX_ETH_DB_MAC_PORT_KEY;
- keyType[IX_ETH_DB_FIREWALL_RECORD] = IX_ETH_DB_MAC_PORT_KEY;
-
- return 5;
-}
-
-/**
- * @brief Sets a user-defined field into a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field)
-{
- HashNode *result = NULL;
-
- if (macAddr == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (recordType == IX_ETH_DB_FILTERING_RECORD)
- {
- result = ixEthDBSearch(macAddr, recordType);
- }
- else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
- }
- else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
- {
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- result = ixEthDBPortSearch(macAddr, portID, recordType);
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (result == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- ((MacDescriptor *) result->data)->user = field;
-
- ixEthDBReleaseHashNode(result);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief Retrieves a user-defined field from a database record
- *
- * Note that this function is fully documented in the main component
- * header file.
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field)
-{
- HashNode *result = NULL;
-
- if (macAddr == NULL || field == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (recordType == IX_ETH_DB_FILTERING_RECORD)
- {
- result = ixEthDBSearch(macAddr, recordType);
- }
- else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- result = ixEthDBVlanSearch(macAddr, vlanID, recordType);
- }
- else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD)
- {
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- result = ixEthDBPortSearch(macAddr, portID, recordType);
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- if (result == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- *field = ((MacDescriptor *) result->data)->user;
-
- ixEthDBReleaseHashNode(result);
-
- return IX_ETH_DB_SUCCESS;
-}
diff --git a/drivers/net/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c
deleted file mode 100644
index 5b3be0b6c1..0000000000
--- a/drivers/net/npe/IxEthDBEvents.c
+++ /dev/null
@@ -1,496 +0,0 @@
-/**
- * @file IxEthDBEvents.c
- *
- * @brief Implementation of the event processor component
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include <IxNpeMh.h>
-#include <IxFeatureCtrl.h>
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *);
-IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg);
-IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void);
-
-/* data */
-IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore;
-IX_ETH_DB_PRIVATE PortEventQueue eventQueue;
-IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock;
-IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock;
-
-IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false;
-IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false;
-
-/* imported data */
-extern HashTable dbHashtable;
-
-/**
- * @brief initializes the event processor
- *
- * Initializes the event processor queue and processing thread.
- * Called from ixEthDBInit() DB-subcomponent master init function.
- *
- * @warning do not call directly
- *
- * @retval IX_ETH_DB_SUCCESS initialization was successful
- * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure)
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEventProcessorInit(void)
-{
- if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- if (IX_FEATURE_CTRL_SWCONFIG_ENABLED ==
- ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING))
- {
-
- /* start processor loop thread */
- if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief initializes the event queue and the event processor
- *
- * This function is called by the component initialization
- * function, ixEthDBInit().
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStartLearningFunction(void)
-{
- IxOsalThread eventProcessorThread;
- IxOsalThreadAttr threadAttr;
-
- threadAttr.name = "EthDB event thread";
- threadAttr.stackSize = 32 * 1024; /* 32kbytes */
- threadAttr.priority = 128;
-
- /* reset event queue */
- ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
- RESET_QUEUE(&eventQueue);
-
- ixOsalMutexUnlock(&eventQueueLock);
-
- /* init event queue semaphore */
- if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- ixEthDBLearningShutdown = false;
-
- /* create processor loop thread */
- if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- /* start event processor */
- ixOsalThreadStart(&eventProcessorThread);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief stops the event processor
- *
- * Stops the event processor and frees the event queue semaphore
- * Called by the component de-initialization function, ixEthDBUnload()
- *
- * @warning do not call directly
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise;
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBStopLearningFunction(void)
-{
- ixEthDBLearningShutdown = true;
-
- /* wake up event processing loop to actually process the shutdown event */
- ixOsalSemaphorePost(&eventQueueSemaphore);
-
- if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief default NPE event processing callback
- *
- * @param npeID ID of the NPE that generated the event
- * @param msg NPE message (encapsulated event)
- *
- * Creates an event object on the Ethernet event processor queue
- * and signals the new event by incrementing the event queue semaphore.
- * Events are processed by @ref ixEthDBEventProcessorLoop() which runs
- * at user level.
- *
- * @see ixEthDBEventProcessorLoop()
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
- PortEvent *local_event;
-
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0);
-
- if (CAN_ENQUEUE(&eventQueue))
- {
- TEST_FIXTURE_LOCK_EVENT_QUEUE;
-
- local_event = QUEUE_HEAD(&eventQueue);
-
- /* create event structure on queue */
- local_event->eventType = NPE_MSG_ID(msg);
- local_event->portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
-
- /* update queue */
- PUSH_UPDATE_QUEUE(&eventQueue);
-
- TEST_FIXTURE_UNLOCK_EVENT_QUEUE;
-
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0);
-
- /* increment event queue semaphore */
- ixOsalSemaphorePost(&eventQueueSemaphore);
- }
- else
- {
- IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0);
- }
-}
-
-/**
- * @brief Ethernet event processor loop
- *
- * Extracts at most EVENT_PROCESSING_LIMIT batches of events and
- * sends them for processing to @ref ixEthDBProcessEvent().
- * Triggers port updates which normally follow learning events.
- *
- * @warning do not call directly, executes in separate thread
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBEventProcessorLoop(void *unused1)
-{
- IxEthDBPortMap triggerPorts;
- IxEthDBPortId portIndex;
-
- ixEthDBEventProcessorRunning = true;
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n");
-
- while (!ixEthDBLearningShutdown)
- {
- BOOL keepProcessing = true;
- UINT32 processedEvents = 0;
-
- IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n");
-
- ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER);
-
- IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n");
-
- if (!ixEthDBLearningShutdown)
- {
- /* port update handling */
- SET_EMPTY_DEPENDENCY_MAP(triggerPorts);
-
- while (keepProcessing)
- {
- PortEvent local_event;
- UINT32 intLockKey;
-
- /* lock queue */
- ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER);
-
- /* lock NPE interrupts */
- intLockKey = ixOsalIrqLock();
-
- /* extract event */
- local_event = *(QUEUE_TAIL(&eventQueue));
-
- SHIFT_UPDATE_QUEUE(&eventQueue);
-
- ixOsalIrqUnlock(intLockKey);
-
- ixOsalMutexUnlock(&eventQueueLock);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType);
-
- ixEthDBProcessEvent(&local_event, triggerPorts);
-
- processedEvents++;
-
- if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */
- || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */
- {
- keepProcessing = false;
- }
- }
-
- ixEthDBUpdatePortLearningTrees(triggerPorts);
- }
- }
-
- /* turn off automatic updates */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false;
- }
-
- ixEthDBEventProcessorRunning = false;
-}
-
-/**
- * @brief event processor routine
- *
- * @param event event to be processed
- * @param triggerPorts port map accumulating ports to be updated
- *
- * Processes learning events by synchronizing the database with
- * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop().
- *
- * @warning do not call directly
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts)
-{
- MacDescriptor recordTemplate;
-
- switch (local_event->eventType)
- {
- case IX_ETH_DB_ADD_FILTERING_RECORD:
- /* add record */
- memset(&recordTemplate, 0, sizeof (recordTemplate));
- memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FILTERING_RECORD;
- recordTemplate.portID = local_event->portID;
- recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry;
-
- ixEthDBAdd(&recordTemplate, triggerPorts);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID);
-
- break;
-
- case IX_ETH_DB_REMOVE_FILTERING_RECORD:
- /* remove record */
- memset(&recordTemplate, 0, sizeof (recordTemplate));
- memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD;
-
- ixEthDBRemove(&recordTemplate, triggerPorts);
-
- IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID);
-
- break;
-
- default:
- /* can't handle/not interested in this event type */
- ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType);
-
- return;
- }
-}
-
-/**
- * @brief asynchronously adds a filtering record
- * by posting an ADD_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the new record
- * @param portID port ID of the new record
- * @param staticEntry true if record is static, false if dynamic
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
- MacDescriptor reference;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr));
- reference.portID = portID;
-
- /* set acceptable record types */
- reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS;
-
- if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS)
- {
- /* already have an identical record */
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry);
- }
-}
-
-/**
- * @brief asynchronously removes a filtering record
- * by posting a REMOVE_FILTERING_RECORD event to the event queue
- *
- * @param macAddr MAC address of the record to remove
- * @param portID port ID of the record to remove
- *
- * @return IX_ETH_DB_SUCCESS if the event creation was
- * successfull or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID)
-{
- if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR)
- {
- return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false);
- }
- else
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-}
-
-/**
- * @brief adds an ADD or REMOVE event to the main event queue
- *
- * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD
- * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a
- * record.
- *
- * @return IX_ETH_DB_SUCCESS if the event was successfully
- * sent or IX_ETH_DB_BUSY if the event queue is full
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry)
-{
- UINT32 intLockKey;
-
- /* lock interrupts to protect queue */
- intLockKey = ixOsalIrqLock();
-
- if (CAN_ENQUEUE(&eventQueue))
- {
- PortEvent *queueEvent = QUEUE_HEAD(&eventQueue);
-
- /* update fields on the queue */
- memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr));
-
- queueEvent->eventType = eventType;
- queueEvent->portID = portID;
- queueEvent->staticEntry = staticEntry;
-
- PUSH_UPDATE_QUEUE(&eventQueue);
-
- /* imcrement event queue semaphore */
- ixOsalSemaphorePost(&eventQueueSemaphore);
-
- /* unlock interrupts */
- ixOsalIrqUnlock(intLockKey);
-
- return IX_ETH_DB_SUCCESS;
- }
- else /* event queue full */
- {
- /* unlock interrupts */
- ixOsalIrqUnlock(intLockKey);
-
- return IX_ETH_DB_BUSY;
- }
-}
-
-/**
- * @brief Locks learning tree updates and port disable
- *
- *
- * This function locks portUpdateLock single mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateLock(void)
-{
- ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER);
-}
-
-/**
- * @brief Unlocks learning tree updates and port disable
- *
- *
- * This function unlocks a portUpdateLock mutex. It is primarily used
- * to avoid executing 'port disable' during ELT maintenance.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdateUnlock(void)
-{
- ixOsalMutexUnlock(&portUpdateLock);
-}
-
diff --git a/drivers/net/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c
deleted file mode 100644
index 1f7624016a..0000000000
--- a/drivers/net/npe/IxEthDBFeatures.c
+++ /dev/null
@@ -1,638 +0,0 @@
-/**
- * @file IxEthDBFeatures.c
- *
- * @brief Implementation of the EthDB feature control API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxNpeDl.h"
-#include "IxEthDBQoS.h"
-#include "IxEthDB_p.h"
-
-/**
- * @brief scans the capabilities of the loaded NPE images
- *
- * This function MUST be called by the ixEthDBInit() function.
- * No EthDB features (including learning and filtering) are enabled
- * before this function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFeatureCapabilityScan(void)
-{
- IxNpeDlImageId imageId, npeAImageId;
- IxEthDBPortId portIndex;
- PortInfo *portInfo;
- IxEthDBPriorityTable defaultPriorityTable;
- IX_STATUS result;
- UINT32 queueIndex;
- UINT32 queueStructureIndex;
- UINT32 trafficClassDefinitionIndex;
-
- /* read version of NPE A - required to set the AQM queues for B and C */
- npeAImageId.functionalityId = 0;
- ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- IxNpeMhMessage msg;
-
- portInfo = &ixEthDBPortInfo[portIndex];
-
- /* check and bypass if NPE B or C is fused out */
- if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue;
-
- /* all ports are capable of LEARNING by default */
- portInfo->featureCapability |= IX_ETH_DB_LEARNING;
- portInfo->featureStatus |= IX_ETH_DB_LEARNING;
-
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
-
- if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS)
- {
- WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex);
- }
- else
- {
- /* initialize and empty NPE response mutex */
- ixOsalMutexInit(&portInfo->npeAckLock);
- ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER);
-
- /* check NPE response to GetStatus */
- msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24;
- msg.data[1] = 0;
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result);
- if (result != IX_SUCCESS)
- {
- WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n");
- continue;
- }
-
-
- if (imageId.functionalityId == 0x00
- || imageId.functionalityId == 0x03
- || imageId.functionalityId == 0x04
- || imageId.functionalityId == 0x80)
- {
- portInfo->featureCapability |= IX_ETH_DB_FILTERING;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- }
- else if (imageId.functionalityId == 0x01
- || imageId.functionalityId == 0x81)
- {
- portInfo->featureCapability |= IX_ETH_DB_FILTERING;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
- }
- else if (imageId.functionalityId == 0x02
- || imageId.functionalityId == 0x82)
- {
- portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION;
- portInfo->featureCapability |= IX_ETH_DB_FIREWALL;
- portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL;
- portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS;
- }
-
- /* reset AQM queues */
- memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments));
-
- /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */
- IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h");
-
- /* find the traffic class definition index compatible with the current NPE A functionality ID */
- for (trafficClassDefinitionIndex = 0 ;
- trafficClassDefinitionIndex < ARRAY_SIZE(ixEthDBTrafficClassDefinitions);
- trafficClassDefinitionIndex++)
- {
- if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId)
- {
- /* found it */
- break;
- }
- }
-
- /* select the default case if we went over the array boundary */
- if (trafficClassDefinitionIndex == ARRAY_SIZE(ixEthDBTrafficClassDefinitions))
- {
- trafficClassDefinitionIndex = 0; /* the first record is the default case */
- }
-
- /* select queue assignment structure based on the traffic class configuration index */
- queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX];
-
- /* only traffic class 0 is active at initialization time */
- portInfo->ixEthDBTrafficClassCount = 1;
-
- /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */
- portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS;
- portInfo->featureStatus |= IX_ETH_DB_FIREWALL;
- portInfo->enabled = true;
-
-#define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* set VLAN initial configuration (permissive) */
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */
- {
- /* QoS capable */
- portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX];
-
- /* set AQM queues */
- for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
- {
- portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex];
- }
-
- /* set default PVID (0) and default traffic class 0 */
- ixEthDBPortVlanTagSet(portIndex, 0);
-
- /* enable reception of all frames */
- ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES);
-
- /* clear full VLAN membership */
- ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID);
-
- /* clear TTI table - no VLAN tagged frames will be transmitted */
- ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false);
-
- /* set membership on 0, otherwise no Tx or Rx is working */
- ixEthDBPortVlanMembershipAdd(portIndex, 0);
- }
- else /* QoS not available in this image */
-#endif /* test-only */
- {
- /* initialize traffic class availability (only class 0 is available) */
- portInfo->ixEthDBTrafficClassAvailable = 1;
-
- /* point all AQM queues to traffic class 0 */
- for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++)
- {
- portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] =
- ixEthDBQueueAssignments[queueStructureIndex][0];
- }
- }
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* download priority mapping table and Rx queue configuration */
- memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
- ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable);
-#endif
-
- /* by default we turn off invalid source MAC address filtering */
- ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false);
-
- /* disable port, VLAN, Firewall feature bits */
- portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS;
- portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL;
- portInfo->enabled = false;
-
- /* enable filtering by default if present */
- if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)
- {
- portInfo->featureStatus |= IX_ETH_DB_FILTERING;
- }
- }
- }
- }
-}
-
-/**
- * @brief returns the capability of a port
- *
- * @param portID ID of the port
- * @param featureSet location to store the port capability in
- *
- * This function will save the capability set of the given port
- * into the given location. Capabilities are bit-ORed, each representing
- * a bit of the feature set.
- *
- * Note that this function is documented in the main component
- * public header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or IX_ETH_DB_INVALID_PORT if the given port is invalid
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet)
-{
- IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(featureSet);
-
- *featureSet = ixEthDBPortInfo[portID].featureCapability;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables a port capability
- *
- * @param portID ID of the port
- * @param feature feature to enable or disable
- * @param enabled true to enable the selected feature or false to disable it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable)
-{
- PortInfo *portInfo;
- IxEthDBPriorityTable defaultPriorityTable;
- IxEthDBVlanSet vlanSet;
- IxEthDBStatus status = IX_ETH_DB_SUCCESS;
- BOOL portEnabled;
-
- IX_ETH_DB_CHECK_PORT_INITIALIZED(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
- portEnabled = portInfo->enabled;
-
- /* check that only one feature is selected */
- if (!ixEthDBCheckSingleBitValue(feature))
- {
- return IX_ETH_DB_FEATURE_UNAVAILABLE;
- }
-
- /* port capable of this feature? */
- if ((portInfo->featureCapability & feature) == 0)
- {
- return IX_ETH_DB_FEATURE_UNAVAILABLE;
- }
-
- /* mutual exclusion between learning and WiFi header conversion */
- if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
- == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* learning must be enabled before filtering */
- if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* filtering must be disabled before learning */
- if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* redundant enabling or disabling */
- if ((!enable && ((portInfo->featureStatus & feature) == 0))
- || (enable && ((portInfo->featureStatus & feature) != 0)))
- {
- /* do nothing */
- return IX_ETH_DB_SUCCESS;
- }
-
- /* force port enabled */
- portInfo->enabled = true;
-
- if (enable)
- {
- /* turn on enable bit */
- portInfo->featureStatus |= feature;
-
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- /* if this is VLAN/QoS set the default priority table */
- if (feature == IX_ETH_DB_VLAN_QOS)
- {
- /* turn on VLAN/QoS (most permissive mode):
- - set default 802.1Q priority mapping table, in accordance to the
- availability of traffic classes
- - set the acceptable frame filter to accept all
- - set the Ingress tagging mode to pass-through
- - set full VLAN membership list
- - set full TTI table
- - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
- - enable TPID port extraction
- */
-
- portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable;
-
- /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */
- memcpy (defaultPriorityTable,
- (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1],
- sizeof (defaultPriorityTable));
-
- /* update priority mapping and AQM queue assignments */
- status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
- }
-
- /* set membership and TTI tables */
- memset (vlanSet, 0xFF, sizeof (vlanSet));
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
- }
-
- /* reset the PVID */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBPortVlanTagSet(portID, 0);
- }
-
- /* enable TPID port extraction */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBVlanPortExtractionEnable(portID, true);
- }
- }
- else if (feature == IX_ETH_DB_FIREWALL)
-#endif
- {
- /* firewall starts in black-list mode unless otherwise configured before *
- * note that invalid source MAC address filtering is disabled by default */
- if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST
- && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST)
- {
- status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
- }
- }
- }
-
- if (status != IX_ETH_DB_SUCCESS)
- {
- /* checks failed, disable */
- portInfo->featureStatus &= ~feature;
- }
- }
- else
- {
- /* turn off features */
- if (feature == IX_ETH_DB_FIREWALL)
- {
- /* turning off the firewall is equivalent to:
- - set to black-list mode
- - clear all the entries and download the new table
- - turn off the invalid source address checking
- */
-
- status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBFirewallTableDownload(portID);
- }
- }
- else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION)
- {
- /* turn off header conversion */
- status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBWiFiConversionTableDownload(portID);
- }
- }
-#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */
- else if (feature == IX_ETH_DB_VLAN_QOS)
- {
- /* turn off VLAN/QoS:
- - set a priority mapping table with one traffic class
- - set the acceptable frame filter to accept all
- - set the Ingress tagging mode to pass-through
- - clear the VLAN membership list
- - clear the TTI table
- - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0)
- - disable TPID port extraction
- */
-
- /* initialize all => traffic class 0 priority mapping table */
- memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable));
- portInfo->ixEthDBTrafficClassCount = 1;
- status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable);
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH);
- }
-
- /* clear membership and TTI tables */
- memset (vlanSet, 0, sizeof (vlanSet));
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet);
- }
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* use the internal function to bypass PVID check */
- status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet);
- }
-
- /* reset the PVID */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBPortVlanTagSet(portID, 0);
- }
-
- /* disable TPID port extraction */
- if (status == IX_ETH_DB_SUCCESS)
- {
- status = ixEthDBVlanPortExtractionEnable(portID, false);
- }
- }
-#endif
-
- if (status == IX_ETH_DB_SUCCESS)
- {
- /* checks passed, disable */
- portInfo->featureStatus &= ~feature;
- }
- }
-
- /* restore port enabled state */
- portInfo->enabled = portEnabled;
-
- return status;
-}
-
-/**
- * @brief returns the status of a feature
- *
- * @param portID port ID
- * @param present location to store a boolean value indicating
- * if the feature is present (true) or not (false)
- * @param enabled location to store a booleam value indicating
- * if the feature is present (true) or not (false)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled)
-{
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(present);
-
- IX_ETH_DB_CHECK_REFERENCE(enabled);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- *present = (portInfo->featureCapability & feature) != 0;
- *enabled = (portInfo->featureStatus & feature) != 0;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief returns the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param type location to store the property type into
- * @param value location to store the property value into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(type);
-
- IX_ETH_DB_CHECK_REFERENCE(value);
-
- if (feature == IX_ETH_DB_VLAN_QOS)
- {
- if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY)
- {
- * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
- *type = IX_ETH_DB_INTEGER_PROPERTY;
-
- return IX_ETH_DB_SUCCESS;
- }
- else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY
- && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY)
- {
- UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;
-
- if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_FAIL;
- }
-
- * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta];
- *type = IX_ETH_DB_INTEGER_PROPERTY;
-
- return IX_ETH_DB_SUCCESS;
- }
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief sets the value of an EthDB property
- *
- * @param portID ID of the port
- * @param feature feature owning the property
- * @param property ID of the property
- * @param value location containing the property value
- *
- * This function implements a private property intended
- * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE
- * property (the value is ignored), the availability of traffic classes is
- * frozen to whatever traffic class structure is currently in use.
- * This means that if VLAN_QOS has been enabled before EthAcc
- * initialization then all the defined traffic classes will be available;
- * otherwise only one traffic class (0) will be available.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h as not accepting any parameters. The
- * current implementation is only intended for the private use of EthAcc.
- *
- * Also note that once this function is called the effect is irreversible,
- * unless EthDB is complete unloaded and re-initialized.
- *
- * @return IX_ETH_DB_INVALID_ARG (no read-write properties are
- * supported in this release)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value)
-{
- IX_ETH_DB_CHECK_PORT_EXISTS(portID);
-
- if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE))
- {
- ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount;
-
- return IX_ETH_DB_SUCCESS;
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
diff --git a/drivers/net/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c
deleted file mode 100644
index c0ae5624ff..0000000000
--- a/drivers/net/npe/IxEthDBFirewall.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/**
- * @file IxEthDBFirewall.c
- *
- * @brief Implementation of the firewall API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief updates the NPE firewall operating mode and
- * firewall address table
- *
- * @param portID ID of the port
- * @param epDelta initial entry point for binary searches (NPE optimization)
- * @param address address of the firewall MAC address table
- *
- * This function will send a message to the NPE configuring the
- * firewall mode (white list or black list), invalid source
- * address filtering and downloading a new MAC address database
- * to be used for firewall matching.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- UINT32 mode = 0;
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
-
- mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST);
-
- FILL_SETFIREWALLMODE_MSG(message,
- IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- epDelta,
- mode,
- IX_OSAL_MMU_VIRT_TO_PHYS(address));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief configures the firewall white list/black list
- * access mode
- *
- * @param portID ID of the port
- * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST
- * or IX_ETH_DB_FIREWALL_BLACK_LIST)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST
- && mode != IX_ETH_DB_FIREWALL_BLACK_LIST)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- ixEthDBPortInfo[portID].firewallMode = mode;
-
- return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief enables or disables the invalid source MAC address filter
- *
- * @param portID ID of the port
- * @param enable true to enable invalid source MAC address filtering
- * or false to disable it
- *
- * The invalid source MAC address filter will discard, when enabled,
- * frames whose source MAC address is a multicast or the broadcast MAC
- * address.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable;
-
- return ixEthDBFirewallTableDownload(portID);
-}
-
-/**
- * @brief adds a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the new record
- *
- * This function will add a new firewall record
- * on the specified port, using the specified
- * MAC address. If the record already exists this
- * function will silently return IX_ETH_DB_SUCCESS,
- * although no duplicate records are added.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBAdd(&recordTemplate, NULL);
-}
-
-/**
- * @brief removes a firewall record
- *
- * @param portID ID of the port
- * @param macAddr MAC address of the record to remove
- *
- * This function will attempt to remove a firewall
- * record from the given port, using the specified
- * MAC address.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully of an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr)
-{
- MacDescriptor recordTemplate;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr));
-
- recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD;
- recordTemplate.portID = portID;
-
- return ixEthDBRemove(&recordTemplate, NULL);
-}
-
-/**
- * @brief downloads the firewall address table to an NPE
- *
- * @param portID ID of the port
- *
- * This function will download the firewall address table to
- * an NPE port.
- *
- * Note that this function is documented in the main
- * component header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_FAIL otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID)
-{
- IxEthDBPortMap query;
- IxEthDBStatus result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL);
-
- SET_DEPENDENCY_MAP(query, portID);
-
- ixEthDBUpdateLock();
-
- ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE);
-
- result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD);
-
- ixEthDBUpdateUnlock();
-
- return result;
-}
diff --git a/drivers/net/npe/IxEthDBHashtable.c b/drivers/net/npe/IxEthDBHashtable.c
deleted file mode 100644
index 9493a5b48b..0000000000
--- a/drivers/net/npe/IxEthDBHashtable.c
+++ /dev/null
@@ -1,618 +0,0 @@
-/**
- * @file ethHash.c
- *
- * @brief Hashtable implementation
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLocks_p.h"
-
-/**
- * @addtogroup EthDB
- *
- * @{
- */
-
-/**
- * @brief initializes a hash table object
- *
- * @param hashTable uninitialized hash table structure
- * @param numBuckets number of buckets to use
- * @param entryHashFunction hash function used
- * to hash entire hash node data block (for adding)
- * @param matchFunctions array of match functions, indexed on type,
- * used to differentiate records with the same hash value
- * @param freeFunction function used to free node data blocks
- *
- * Initializes the given hash table object.
- *
- * @internal
- */
-void ixEthDBInitHash(HashTable *hashTable,
- UINT32 numBuckets,
- HashFunction entryHashFunction,
- MatchFunction *matchFunctions,
- FreeFunction freeFunction)
-{
- UINT32 bucketIndex;
- UINT32 hashSize = numBuckets * sizeof(HashNode *);
-
- /* entry hashing, matching and freeing methods */
- hashTable->entryHashFunction = entryHashFunction;
- hashTable->matchFunctions = matchFunctions;
- hashTable->freeFunction = freeFunction;
-
- /* buckets */
- hashTable->numBuckets = numBuckets;
-
- /* set to 0 all buckets */
- memset(hashTable->hashBuckets, 0, hashSize);
-
- /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/
- for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++)
- {
- ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]);
- }
-}
-
-/**
- * @brief adds an entry to the hash table
- *
- * @param hashTable hash table to add the entry to
- * @param entry entry to add
- *
- * The entry will be hashed using the entry hashing function and added to the
- * hash table, unless a locking blockage occurs, in which case the caller
- * should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if adding <i>entry</i> has succeeded
- * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool
- * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry)
-{
- UINT32 hashValue = hashTable->entryHashFunction(entry);
- UINT32 bucketIndex = hashValue % hashTable->numBuckets;
- HashNode *bucket = hashTable->hashBuckets[bucketIndex];
- HashNode *newNode;
-
- LockStack locks;
-
- INIT_STACK(&locks);
-
- /* lock bucket */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
- /* lock insertion element (first in chain), if any */
- if (bucket != NULL)
- {
- PUSH_LOCK(&locks, &bucket->lock);
- }
-
- /* get new node */
- newNode = ixEthDBAllocHashNode();
-
- if (newNode == NULL)
- {
- /* unlock everything */
- UNROLL_STACK(&locks);
-
- return IX_ETH_DB_NOMEM;
- }
-
- /* init lock - note that mutexes are unlocked after MutexInit */
- ixOsalFastMutexInit(&newNode->lock);
-
- /* populate new link */
- newNode->data = entry;
-
- /* add to bucket */
- newNode->next = bucket;
- hashTable->hashBuckets[bucketIndex] = newNode;
-
- /* unlock bucket and insertion point */
- UNROLL_STACK(&locks);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief removes an entry from the hashtable
- *
- * @param hashTable hash table to remove entry from
- * @param keyType type of record key used for matching
- * @param reference reference key used to identify the entry
- *
- * The reference key will be hashed using the key hashing function,
- * the entry is searched using the hashed value and then examined
- * against the reference entry using the match function. A positive
- * match will trigger the deletion of the entry.
- * Locking failures are reported and the caller should retry.
- *
- * @retval IX_ETH_DB_SUCCESS if the removal was successful
- * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found
- * @retval IX_ETH_DB_BUSY if a locking failure occured during the process
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
- UINT32 hashValue = hashTable->entryHashFunction(reference);
- UINT32 bucketIndex = hashValue % hashTable->numBuckets;
- HashNode *node = hashTable->hashBuckets[bucketIndex];
- HashNode *previousNode = NULL;
-
- LockStack locks;
-
- INIT_STACK(&locks);
-
- while (node != NULL)
- {
- /* try to lock node */
- PUSH_LOCK(&locks, &node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- /* found entry */
- if (node->next != NULL)
- {
- PUSH_LOCK(&locks, &node->next->lock);
- }
-
- if (previousNode == NULL)
- {
- /* node is head of chain */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]);
-
- hashTable->hashBuckets[bucketIndex] = node->next;
-
- POP_LOCK(&locks);
- }
- else
- {
- /* relink */
- previousNode->next = node->next;
- }
-
- UNROLL_STACK(&locks);
-
- /* free node */
- hashTable->freeFunction(node->data);
- ixEthDBFreeHashNode(node);
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- if (previousNode != NULL)
- {
- /* unlock previous node */
- SHIFT_STACK(&locks);
- }
-
- /* advance to next element in chain */
- previousNode = node;
- node = node->next;
- }
- }
-
- UNROLL_STACK(&locks);
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief retrieves an entry from the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- * @param searchResult pointer where a reference to the located hash node
- * is placed
- *
- * Searches the entry with the same key as <i>reference</i> and places the
- * pointer to the resulting node in <i>searchResult</i>.
- * An implicit write access lock is granted after a search, which gives the
- * caller the opportunity to modify the entry.
- * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode().
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @warning unless the return value is <b>IX_ETH_DB_SUCCESS</b> the searchResult
- * location is NOT modified and therefore using a NULL comparison test when the
- * value was not properly initialized would be an error
- *
- * @internal
- */
-IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult)
-{
- UINT32 hashValue;
- HashNode *node;
-
- hashValue = hashTable->entryHashFunction(reference);
- node = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
- while (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- *searchResult = node;
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- UNLOCK(&node->lock);
-
- node = node->next;
- }
- }
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief reports the existence of an entry in the hash table
- *
- * @param hashTable hash table to perform the search into
- * @param reference search key (a MAC address)
- * @param keyType type of record key used for matching
- *
- * Searches the entry with the same key as <i>reference</i>.
- * No implicit write access lock is granted after a search, hence the
- * caller cannot access or modify the entry. The result is only temporary.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @retval IX_ETH_DB_SUCCESS if the search was completed successfully
- * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case
- * the caller should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference)
-{
- UINT32 hashValue;
- HashNode *node;
-
- hashValue = hashTable->entryHashFunction(reference);
- node = hashTable->hashBuckets[hashValue % hashTable->numBuckets];
-
- while (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- if (hashTable->matchFunctions[keyType](reference, node->data))
- {
- UNLOCK(&node->lock);
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- UNLOCK(&node->lock);
-
- node = node->next;
- }
- }
-
- /* not found */
- return IX_ETH_DB_NO_SUCH_ADDR;
-}
-
-/**
- * @brief releases the write access lock
- *
- * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry()
- *
- * @see ixEthDBSearchHashEntry()
- *
- * @internal
- */
-void ixEthDBReleaseHashNode(HashNode *node)
-{
- UNLOCK(&node->lock);
-}
-
-/**
- * @brief initializes a hash iterator
- *
- * @param hashTable hash table to be iterated
- * @param iterator iterator object
- *
- * If the initialization is successful the iterator will point to the
- * first hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points
- * to the first valid table node
- * @retval IX_ETH_DB_FAIL if the table is empty
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- iterator->bucketIndex = 0;
- iterator->node = NULL;
- iterator->previousNode = NULL;
-
- return ixEthDBIncrementHashIterator(hashTable, iterator);
-}
-
-/**
- * @brief releases the write access locks of the iterator nodes
- *
- * @warning use of this function is required only when the caller terminates an iteration
- * before reaching the end of the table
- *
- * @see ixEthDBInitHashIterator()
- * @see ixEthDBIncrementHashIterator()
- *
- * @param iterator iterator whose node(s) should be unlocked
- *
- * @internal
- */
-void ixEthDBReleaseHashIterator(HashIterator *iterator)
-{
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
- }
-}
-
-/**
- * @brief incremenents an iterator so that it points to the next valid entry of the table
- * (if any)
- *
- * @param hashTable hash table to iterate
- * @param iterator iterator object
- *
- * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator()
- *
- * If the increment operation is successful the iterator will point to the
- * next hash table record (if any).
- * Testing if the iterator has not passed the end of the table should be
- * done using the IS_ITERATOR_VALID(iteratorPtr) macro.
- * An implicit write access lock is granted on the entry pointed by the iterator.
- * The access is automatically revoked when the iterator is re-incremented.
- * If the caller decides to terminate the iteration before the end of the table is
- * passed then the manual access release method, @ref ixEthDBReleaseHashIterator,
- * must be called.
- * Is is guaranteed that no other thread can remove or change the iterated entry until
- * the iterator is incremented successfully.
- *
- * @see ixEthDBReleaseHashIterator()
- *
- * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points
- * to the next valid table node
- * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this
- * might place the database in a permanent invalid lock state
- *
- * @internal
- */
-IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- /* unless iterator is just initialized... */
- if (iterator->node != NULL)
- {
- /* try next in chain */
- if (iterator->node->next != NULL)
- {
- TRY_LOCK(&iterator->node->next->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- iterator->previousNode = iterator->node;
- iterator->node = iterator->node->next;
-
- return IX_ETH_DB_SUCCESS;
- }
- else
- {
- /* last in chain, prepare for next bucket */
- iterator->bucketIndex++;
- }
- }
-
- /* try next used bucket */
- for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++)
- {
- HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]);
- HashNode *node = *nodePtr;
-#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince)
- if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) &&
- (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD)))
- {
- /* preload next cache line (2 cache line ahead) */
- nodePtr += IX_ETHDB_BUCKETPTR_AHEAD;
- __asm__ ("pld [%0];\n": : "r" (nodePtr));
- }
-#endif
- if (node != NULL)
- {
- TRY_LOCK(&node->lock);
-
- /* unlock last one or two nodes in the previous chain */
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
- }
-
- /* redirect iterator */
- iterator->previousNode = NULL;
- iterator->node = node;
-
- return IX_ETH_DB_SUCCESS;
- }
- }
-
- /* could not advance iterator */
- if (iterator->node != NULL)
- {
- UNLOCK(&iterator->node->lock);
-
- if (iterator->previousNode != NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
-
- iterator->node = NULL;
- }
-
- return IX_ETH_DB_END;
-}
-
-/**
- * @brief removes an entry pointed by an iterator
- *
- * @param hashTable iterated hash table
- * @param iterator iterator object
- *
- * Removes the entry currently pointed by the iterator and repositions the iterator
- * on the next valid entry (if any). Handles locking issues automatically and
- * implicitely grants write access lock to the new pointed entry.
- * Failures due to concurrent threads having write access locks in the same region
- * preserve the state of the database and the iterator object, leaving the caller
- * free to retry without loss of access. It is guaranteed that only the thread owning
- * the iterator can remove the object pointed by the iterator.
- *
- * @retval IX_ETH_DB_SUCCESS if removal has succeeded
- * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller
- * should retry
- *
- * @internal
- */
-IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator)
-{
- HashIterator nextIteratorPos;
- LockStack locks;
-
- INIT_STACK(&locks);
-
- /* set initial bucket index for next position */
- nextIteratorPos.bucketIndex = iterator->bucketIndex;
-
- /* compute iterator position before removing anything and lock ahead */
- if (iterator->node->next != NULL)
- {
- PUSH_LOCK(&locks, &iterator->node->next->lock);
-
- /* reposition on the next node in the chain */
- nextIteratorPos.node = iterator->node->next;
- nextIteratorPos.previousNode = iterator->previousNode;
- }
- else
- {
- /* try next chain - don't know yet if we'll find anything */
- nextIteratorPos.node = NULL;
-
- /* if we find something it's a chain head */
- nextIteratorPos.previousNode = NULL;
-
- /* browse up in the buckets to find a non-null chain */
- while (++nextIteratorPos.bucketIndex < hashTable->numBuckets)
- {
- nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex];
-
- if (nextIteratorPos.node != NULL)
- {
- /* found a non-empty chain, try to lock head */
- PUSH_LOCK(&locks, &nextIteratorPos.node->lock);
-
- break;
- }
- }
- }
-
- /* restore links over the to-be-deleted item */
- if (iterator->previousNode == NULL)
- {
- /* first in chain, lock bucket */
- PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]);
-
- hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next;
-
- POP_LOCK(&locks);
- }
- else
- {
- /* relink */
- iterator->previousNode->next = iterator->node->next;
-
- /* unlock last remaining node in current chain when moving between chains */
- if (iterator->node->next == NULL)
- {
- UNLOCK(&iterator->previousNode->lock);
- }
- }
-
- /* delete entry */
- hashTable->freeFunction(iterator->node->data);
- ixEthDBFreeHashNode(iterator->node);
-
- /* reposition iterator */
- *iterator = nextIteratorPos;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @}
- */
diff --git a/drivers/net/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c
deleted file mode 100644
index 1080d112de..0000000000
--- a/drivers/net/npe/IxEthDBLearning.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * @file IxEthDBLearning.c
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief hashes the mac address in a mac descriptor with a XOR function
- *
- * @param entry pointer to a mac descriptor to be hashed
- *
- * This function only extracts the mac address and employs ixEthDBKeyXORHash()
- * to do the actual hashing.
- * Used only to add a whole entry to a hash table, as opposed to searching which
- * takes only a key and uses the key hashing directly.
- *
- * @see ixEthDBKeyXORHash()
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBEntryXORHash(void *entry)
-{
- MacDescriptor *descriptor = (MacDescriptor *) entry;
-
- return ixEthDBKeyXORHash(descriptor->macAddress);
-}
-
-/**
- * @brief hashes a mac address
- *
- * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer)
- * to be hashed
- *
- * Given a 6 bytes MAC address, the hash used is:
- *
- * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5]
- *
- * Used by the hash table to search and remove entries based
- * solely on their keys (mac addresses).
- *
- * @return the hash value
- *
- * @internal
- */
-UINT32 ixEthDBKeyXORHash(void *key)
-{
- UINT32 hashValue;
- UINT8 *value = (UINT8 *) key;
-
- hashValue = (value[5] << 8) | value[4];
- hashValue ^= (value[3] << 8) | value[2];
- hashValue ^= (value[1] << 8) | value[0];
-
- return hashValue;
-}
-
-/**
- * @brief mac descriptor match function
- *
- * @param reference mac address (typically an IxEthDBMacAddr pointer) structure
- * @param entry pointer to a mac descriptor whose key (mac address) is to be
- * matched against the reference key
- *
- * Used by the hash table to retrieve entries. Hashing entries can produce
- * collisions, i.e. descriptors with different mac addresses and the same
- * hash value, where this function is used to differentiate entries.
- *
- * @retval true if the entry matches the reference key (equal addresses)
- * @retval false if the entry does not match the reference key
- *
- * @internal
- */
-BOOL ixEthDBAddressMatch(void *reference, void *entry)
-{
- return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0);
-}
-
-/**
- * @brief compares two mac addresses
- *
- * @param mac1 first mac address to compare
- * @param mac2 second mac address to compare
- *
- * This comparison works in a similar way to strcmp, producing similar results.
- * Used to insert values keyed on mac addresses into binary search trees.
- *
- * @retval -1 if mac1 < mac2
- * @retval 0 if ma1 == mac2
- * @retval 1 if mac1 > mac2
- */
-UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2)
-{
- UINT32 local_index;
-
- for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++)
- {
- if (mac1[local_index] > mac2[local_index])
- {
- return 1;
- }
- else if (mac1[local_index] < mac2[local_index])
- {
- return -1;
- }
- }
-
- return 0;
-}
-
diff --git a/drivers/net/npe/IxEthDBMem.c b/drivers/net/npe/IxEthDBMem.c
deleted file mode 100644
index 78fce4bd92..0000000000
--- a/drivers/net/npe/IxEthDBMem.c
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * @file IxEthDBDBMem.c
- *
- * @brief Memory handling routines for the MAC address database
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PRIVATE HashNode *nodePool = NULL;
-IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL;
-IX_ETH_DB_PRIVATE MacTreeNode *treePool = NULL;
-
-IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE];
-IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE];
-
-IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock;
-IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock;
-
-#define LOCK_NODE_POOL { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); }
-
-#define LOCK_MAC_POOL { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_MAC_POOL { ixOsalMutexUnlock(&macPoolLock); }
-
-#define LOCK_TREE_POOL { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); }
-#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); }
-
-/* private function prototypes */
-IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void);
-IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor);
-
-/**
- * @addtogroup EthMemoryManagement
- *
- * @{
- */
-
-/**
- * @brief initializes the memory pools used by the ethernet database component
- *
- * Initializes the hash table node, mac descriptor and mac tree node pools.
- * Called at initialization time by @ref ixEthDBInit().
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBInitMemoryPools(void)
-{
- int local_index;
-
- /* HashNode pool */
- ixOsalMutexInit(&nodePoolLock);
-
- for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++)
- {
- HashNode *freeNode = &nodePoolArea[local_index];
-
- freeNode->nextFree = nodePool;
- nodePool = freeNode;
- }
-
- /* MacDescriptor pool */
- ixOsalMutexInit(&macPoolLock);
-
- for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++)
- {
- MacDescriptor *freeDescriptor = &macPoolArea[local_index];
-
- freeDescriptor->nextFree = macPool;
- macPool = freeDescriptor;
- }
-
- /* MacTreeNode pool */
- ixOsalMutexInit(&treePoolLock);
-
- for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++)
- {
- MacTreeNode *freeNode = &treePoolArea[local_index];
-
- freeNode->nextFree = treePool;
- treePool = freeNode;
- }
-}
-
-/**
- * @brief allocates a hash node from the pool
- *
- * Allocates a hash node and resets its value.
- *
- * @return the allocated hash node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBAllocHashNode(void)
-{
- HashNode *allocatedNode = NULL;
-
- if (nodePool != NULL)
- {
- LOCK_NODE_POOL;
-
- allocatedNode = nodePool;
- nodePool = nodePool->nextFree;
-
- UNLOCK_NODE_POOL;
-
- memset(allocatedNode, 0, sizeof(HashNode));
- }
-
- return allocatedNode;
-}
-
-/**
- * @brief frees a hash node into the pool
- *
- * @param hashNode node to be freed
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeHashNode(HashNode *hashNode)
-{
- if (hashNode != NULL)
- {
- LOCK_NODE_POOL;
-
- hashNode->nextFree = nodePool;
- nodePool = hashNode;
-
- UNLOCK_NODE_POOL;
- }
-}
-
-/**
- * @brief allocates a mac descriptor from the pool
- *
- * Allocates a mac descriptor and resets its value.
- * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor()
- * is used, which keeps track of the pointer reference count.
- *
- * @see ixEthDBAllocMacDescriptor()
- *
- * @warning this function is not used directly by any other function
- * apart from ixEthDBAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacDescriptor* ixEthDBPoolAllocMacDescriptor(void)
-{
- MacDescriptor *allocatedDescriptor = NULL;
-
- if (macPool != NULL)
- {
- LOCK_MAC_POOL;
-
- allocatedDescriptor = macPool;
- macPool = macPool->nextFree;
-
- UNLOCK_MAC_POOL;
-
- memset(allocatedDescriptor, 0, sizeof(MacDescriptor));
- }
-
- return allocatedDescriptor;
-}
-
-/**
- * @brief allocates and initializes a mac descriptor smart pointer
- *
- * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor
- * from the pool and initializes its reference count.
- *
- * @see ixEthDBPoolAllocMacDescriptor()
- *
- * @return the allocated mac descriptor or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBAllocMacDescriptor(void)
-{
- MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor();
-
- if (allocatedDescriptor != NULL)
- {
- LOCK_MAC_POOL;
-
- allocatedDescriptor->refCount++;
-
- UNLOCK_MAC_POOL;
- }
-
- return allocatedDescriptor;
-}
-
-/**
- * @brief frees a mac descriptor back into the pool
- *
- * @param macDescriptor mac descriptor to be freed
- *
- * @warning this function is not to be called by anyone but
- * ixEthDBFreeMacDescriptor()
- *
- * @see ixEthDBFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
- LOCK_MAC_POOL;
-
- macDescriptor->nextFree = macPool;
- macPool = macDescriptor;
-
- UNLOCK_MAC_POOL;
-}
-
-/**
- * @brief frees or reduces the usage count of a mac descriptor smart pointer
- *
- * If the reference count reaches 0 (structure is no longer used anywhere)
- * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor().
- *
- * @see ixEthDBPoolFreeMacDescriptor()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor)
-{
- if (macDescriptor != NULL)
- {
- LOCK_MAC_POOL;
-
- if (macDescriptor->refCount > 0)
- {
- macDescriptor->refCount--;
-
- if (macDescriptor->refCount == 0)
- {
- UNLOCK_MAC_POOL;
-
- ixEthDBPoolFreeMacDescriptor(macDescriptor);
- }
- else
- {
- UNLOCK_MAC_POOL;
- }
- }
- else
- {
- UNLOCK_MAC_POOL;
- }
- }
-}
-
-/**
- * @brief clones a mac descriptor smart pointer
- *
- * @param macDescriptor mac descriptor to clone
- *
- * Increments the usage count of the smart pointer
- *
- * @returns the cloned smart pointer
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor)
-{
- LOCK_MAC_POOL;
-
- if (macDescriptor->refCount == 0)
- {
- UNLOCK_MAC_POOL;
-
- return NULL;
- }
-
- macDescriptor->refCount++;
-
- UNLOCK_MAC_POOL;
-
- return macDescriptor;
-}
-
-/**
- * @brief allocates a mac tree node from the pool
- *
- * Allocates and initializes a mac tree node from the pool.
- *
- * @return the allocated mac tree node or NULL if the pool is empty
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBAllocMacTreeNode(void)
-{
- MacTreeNode *allocatedNode = NULL;
-
- if (treePool != NULL)
- {
- LOCK_TREE_POOL;
-
- allocatedNode = treePool;
- treePool = treePool->nextFree;
-
- UNLOCK_TREE_POOL;
-
- memset(allocatedNode, 0, sizeof(MacTreeNode));
- }
-
- return allocatedNode;
-}
-
-/**
- * @brief frees a mac tree node back into the pool
- *
- * @param macNode mac tree node to be freed
- *
- * @warning not to be used except from ixEthDBFreeMacTreeNode().
- *
- * @see ixEthDBFreeMacTreeNode()
- *
- * @internal
- */
-void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode != NULL)
- {
- LOCK_TREE_POOL;
-
- macNode->nextFree = treePool;
- treePool = macNode;
-
- UNLOCK_TREE_POOL;
- }
-}
-
-/**
- * @brief frees or reduces the usage count of a mac tree node smart pointer
- *
- * @param macNode mac tree node to free
- *
- * Reduces the usage count of the given mac node. If the usage count
- * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFreeMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode->descriptor != NULL)
- {
- ixEthDBFreeMacDescriptor(macNode->descriptor);
- }
-
- if (macNode->left != NULL)
- {
- ixEthDBFreeMacTreeNode(macNode->left);
- }
-
- if (macNode->right != NULL)
- {
- ixEthDBFreeMacTreeNode(macNode->right);
- }
-
- ixEthDBPoolFreeMacTreeNode(macNode);
-}
-
-/**
- * @brief clones a mac tree node
- *
- * @param macNode mac tree node to be cloned
- *
- * Increments the usage count of the node, <i>its associated descriptor
- * and <b>recursively</b> of all its child nodes</i>.
- *
- * @warning this function is recursive and clones whole trees/subtrees, use only for
- * root nodes
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode)
-{
- if (macNode != NULL)
- {
- MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode();
-
- if (clonedMacNode != NULL)
- {
- if (macNode->right != NULL)
- {
- clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right);
- }
-
- if (macNode->left != NULL)
- {
- clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left);
- }
-
- if (macNode->descriptor != NULL)
- {
- clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor);
- }
- }
-
- return clonedMacNode;
- }
- else
- {
- return NULL;
- }
-}
-
-#ifndef NDEBUG
-/* Debug statistical functions for memory usage */
-
-extern HashTable dbHashtable;
-int ixEthDBNumHashElements(void);
-
-int ixEthDBNumHashElements(void)
-{
- UINT32 bucketIndex;
- int numElements = 0;
- HashTable *hashTable = &dbHashtable;
-
- for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++)
- {
- if (hashTable->hashBuckets[bucketIndex] != NULL)
- {
- HashNode *node = hashTable->hashBuckets[bucketIndex];
-
- while (node != NULL)
- {
- numElements++;
-
- node = node->next;
- }
- }
- }
-
- return numElements;
-}
-
-UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree)
-{
- if (tree == NULL)
- {
- return 0;
- }
- else
- {
- return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right);
- }
-}
-
-int ixEthDBShowMemoryStatus(void)
-{
- MacDescriptor *mac;
- MacTreeNode *tree;
- HashNode *node;
-
- int macCounter = 0;
- int treeCounter = 0;
- int nodeCounter = 0;
-
- int totalTreeUsage = 0;
- int totalDescriptorUsage = 0;
- int totalCloneDescriptorUsage = 0;
- int totalNodeUsage = 0;
-
- UINT32 portIndex;
-
- LOCK_NODE_POOL;
- LOCK_MAC_POOL;
- LOCK_TREE_POOL;
-
- mac = macPool;
- tree = treePool;
- node = nodePool;
-
- while (mac != NULL)
- {
- macCounter++;
-
- mac = mac->nextFree;
-
- if (macCounter > MAC_POOL_SIZE)
- {
- break;
- }
- }
-
- while (tree != NULL)
- {
- treeCounter++;
-
- tree = tree->nextFree;
-
- if (treeCounter > TREE_POOL_SIZE)
- {
- break;
- }
- }
-
- while (node != NULL)
- {
- nodeCounter++;
-
- node = node->nextFree;
-
- if (nodeCounter > NODE_POOL_SIZE)
- {
- break;
- }
- }
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree);
-
- totalTreeUsage += treeUsage;
- totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */
- }
-
- totalNodeUsage = ixEthDBNumHashElements();
- totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */
-
- UNLOCK_NODE_POOL;
- UNLOCK_MAC_POOL;
- UNLOCK_TREE_POOL;
-
- printf("Ethernet database memory usage stats:\n\n");
-
- if (macCounter <= MAC_POOL_SIZE)
- {
- printf("\tMAC descriptor pool : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE);
- }
- else
- {
- printf("\tMAC descriptor pool : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE);
- }
-
- if (treeCounter <= TREE_POOL_SIZE)
- {
- printf("\tTree node pool : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE);
- }
- else
- {
- printf("\tTREE descriptor pool : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE);
- }
-
- if (nodeCounter <= NODE_POOL_SIZE)
- {
- printf("\tHash node pool : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE);
- }
- else
- {
- printf("\tNODE descriptor pool : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE);
- }
-
- printf("\n");
- printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage);
- printf("\tTree node usage : %d entries\n", totalTreeUsage);
- printf("\tHash node usage : %d entries\n", totalNodeUsage);
- printf("\n");
-
- /* search for duplicate nodes in the mac pool */
- {
- MacDescriptor *reference = macPool;
-
- while (reference != NULL)
- {
- MacDescriptor *comparison = reference->nextFree;
-
- while (comparison != NULL)
- {
- if (reference == comparison)
- {
- printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference);
-
- return 1;
- }
-
- comparison = comparison->nextFree;
- }
-
- reference = reference->nextFree;
- }
- }
-
- printf("No duplicates found in the MAC pool (sanity check ok)\n");
-
- return 0;
-}
-
-#endif /* NDEBUG */
-
-/**
- * @} EthMemoryManagement
- */
diff --git a/drivers/net/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c
deleted file mode 100644
index 30e1f61ab9..0000000000
--- a/drivers/net/npe/IxEthDBNPEAdaptor.c
+++ /dev/null
@@ -1,695 +0,0 @@
-/**
- * @file IxEthDBDBNPEAdaptor.c
- *
- * @brief Routines that read and write learning/search trees in NPE-specific format
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-#include "IxEthDBLog_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID);
-IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void);
-
-/* data */
-UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS];
-UINT32 dumpEltSize;
-
-/* private data */
-IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1];
-
-#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES];
-
-/**
- * @brief allocates non-cached or contiguous NPE tree update areas for all the ports
- *
- * This function is called only once at initialization time from
- * @ref ixEthDBInit().
- *
- * @warning do not call manually
- *
- * @see ixEthDBInit()
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasInit(void)
-{
- UINT32 portIndex;
- PortUpdateMethod *update;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- update = &ixEthDBPortInfo[portIndex].updateMethod;
-
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- update->npeUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE);
- update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE);
- update->vlanUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE);
-
- if (update->npeUpdateZone == NULL
- || update->npeGwUpdateZone == NULL
- || update->vlanUpdateZone == NULL)
- {
- ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n");
- }
- else
- {
- memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE);
- memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE);
- memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE);
- }
- }
- else
- {
- /* unused */
- update->npeUpdateZone = NULL;
- update->npeGwUpdateZone = NULL;
- update->vlanUpdateZone = NULL;
- }
- }
-}
-
-/**
- * @brief deallocates the NPE update areas for all the ports
- *
- * This function is called at component de-initialization time
- * by @ref ixEthDBUnload().
- *
- * @warning do not call manually
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEUpdateAreasUnload(void)
-{
- UINT32 portIndex;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE)
- {
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone);
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone);
- IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone);
- }
- }
-}
-
-/**
- * @brief general-purpose NPE callback function
- *
- * @param npeID NPE ID
- * @param msg NPE message
- *
- * This function will unblock the caller by unlocking
- * the npeAckLock mutex defined for each NPE port
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg)
-{
- IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID);
- PortInfo *portInfo;
-
- if (portID >= IX_ETH_DB_NUMBER_OF_PORTS)
- {
- /* invalid port */
- return;
- }
-
- if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE)
- {
- /* not an NPE */
- return;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- ixOsalMutexUnlock(&portInfo->npeAckLock);
-}
-
-/**
- * @brief synchronizes the database with tree
- *
- * @param portID port ID of the NPE whose tree is to be scanned
- * @param eltBaseAddress memory base address of the NPE serialized tree
- * @param eltSize size in bytes of the NPE serialized tree
- *
- * Scans the NPE learning tree and resets the age of active database records.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize)
-{
- UINT32 eltEntryOffset;
- UINT32 entryPortID;
-
- /* invalidate cache */
- IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize);
-
- for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
- {
- /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
- *
- * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
- * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
- */
- void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
- /* debug */
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE);
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true)
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n");
- }
- else if (eltEntryOffset == ELT_ROOT_OFFSET)
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n");
- }
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
- {
- entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
- /* check only active entries belonging to this port */
- if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID)
- && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0))
- {
- /* search record */
- HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- /* safety check, maybe user deleted record right before sync? */
- if (node != NULL)
- {
- /* found record */
- MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress));
-
- /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */
- if (!descriptor->recordData.filteringData.staticEntry)
- {
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- descriptor->recordData.filteringData.age = AGE_RESET;
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- descriptor->recordData.filteringVlanData.age = AGE_RESET;
- }
- }
-
- /* end transaction */
- ixEthDBReleaseHashNode(node);
- }
- }
- else
- {
- IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID);
- }
- }
- }
-}
-
-/**
- * @brief writes a search tree in NPE format
- *
- * @param type type of records to be written into the NPE update zone
- * @param totalSize maximum size of the linearized tree
- * @param baseAddress memory base address where to write the NPE tree into
- * @param tree search tree to write in NPE format
- * @param blocks number of written 64-byte blocks
- * @param startIndex optimal binary search start index
- *
- * Serializes the given tree in NPE linear format
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks)
-{
- MacTreeNodeStack *stack;
- UINT32 maxOffset = 0;
- UINT32 emptyOffset;
-
- stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack));
-
- if (stack == NULL)
- {
- ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n");
- return;
- }
-
- /* zero out empty root */
- memset(baseAddress, 0, ELT_ENTRY_SIZE);
-
- NODE_STACK_INIT(stack);
-
- if (tree != NULL)
- {
- /* push tree root at offset 1 */
- NODE_STACK_PUSH(stack, tree, 1);
-
- maxOffset = 1;
- }
-
- while (NODE_STACK_NONEMPTY(stack))
- {
- MacTreeNode *node;
- UINT32 offset;
-
- NODE_STACK_POP(stack, node, offset);
-
- /* update maximum offset */
- if (offset > maxOffset)
- {
- maxOffset = offset;
- }
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset);
-
- /* add node to NPE ELT at position indicated by offset */
- if (offset < MAX_ELT_SIZE)
- {
- ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node);
- }
-
- if (node->left != NULL)
- {
- NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset));
- }
- else
- {
- /* ensure this entry is zeroed */
- memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
- }
-
- if (node->right != NULL)
- {
- NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset));
- }
- else
- {
- /* ensure this entry is zeroed */
- memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE);
- }
- }
-
- emptyOffset = maxOffset + 1;
-
- /* zero out rest of the tree */
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n",
- emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
-
- if (emptyOffset < MAX_ELT_SIZE - 1)
- {
- memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE));
- }
-
- /* flush cache */
- IX_OSAL_CACHE_FLUSH(baseAddress, totalSize);
-
- /* debug */
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n",
- (UINT32) baseAddress, FULL_ELT_BYTE_SIZE);
-
- IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE);
-
- /* compute number of 64-byte blocks */
- if (blocks != NULL)
- {
- *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0;
-
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks);
- }
-
- /* compute epDelta - start index for binary search */
- if (epDelta != NULL)
- {
- UINT32 deltaIndex = 0;
-
- *epDelta = 0;
-
- for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++)
- {
- if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset)
- {
- *epDelta = ixEthDBEPDelta[type][deltaIndex];
- break;
- }
- }
-
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset);
- }
-
- ixOsalCacheDmaFree(stack);
-}
-
-/**
- * @brief implements a dummy node serialization function
- *
- * @param address address of where the node is to be serialized (unused)
- * @param node tree node to be serialized (unused)
- *
- * This function is registered for safety reasons and should
- * never be called. It will display an error message if this
- * function is called.
- *
- * @return none
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNullSerialize(void *address, MacTreeNode *node)
-{
- IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n");
-}
-
-/**
- * @brief writes a filtering entry in NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* copy port ID */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID);
-
- /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID;
-
- IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1));
-}
-
-/**
- * @brief writes a WiFi header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* copy index */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex;
-
- /* copy flags (type and valid) */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID;
-}
-
-/**
- * @brief writes a WiFi gateway header conversion record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node)
-{
- /* copy mac address */
- memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-
- /* set reserved field, two bytes */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0;
-}
-
-/**
- * @brief writes a firewall record in
- * NPE linear format
- *
- * @param address memory address to write node to
- * @param node node to be written
- *
- * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree
- * in NPE-readable format.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node)
-{
- /* set reserved field */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0;
-
- /* set flags */
- NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID;
-
- /* copy mac address */
- memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE);
-}
-
-/**
- * @brief registers the NPE serialization methods
- *
- * This functions registers NPE serialization methods
- * for writing the following types of records in NPE
- * readable linear format:
- * - filtering records
- * - WiFi header conversion records
- * - WiFi gateway header conversion records
- * - firewall records
- *
- * Note that this function should be called by the
- * component initialization function.
- *
- * @return number of registered record types
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBRecordSerializeMethodsRegister()
-{
- int i;
-
- /* safety - register a blank method for everybody first */
- for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++)
- {
- ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize;
- }
-
- /* register real methods */
- ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD] = ixEthDBNPELearningNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD] = ixEthDBNPEWiFiNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD] = ixEthDBNPEFirewallNodeWrite;
- ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD] = ixEthDBNPEGatewayNodeWrite;
-
- /* EP Delta arrays */
- memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset));
- memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta));
-
- /* filtering records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1] = 7;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511;
- ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2] = 14;
-
- /* wifi records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1] = 7;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511;
- ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2] = 14;
-
- /* firewall records */
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0] = 0;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1] = 5;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2] = 13;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3] = 21;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4] = 29;
-
- ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31;
- ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5] = 37;
-
- return 5; /* 5 methods registered */
-}
-
-#ifndef IX_NDEBUG
-
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2];
-IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0;
-
-/**
- * When compiled in DEBUG mode, this function can be used to display
- * the history of messages sent to the NPEs (up to 100).
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBShowNpeMsgHistory()
-{
- UINT32 i = 0;
- UINT32 base, len;
-
- if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH)
- {
- base = 0;
- len = npeMsgHistoryLen;
- }
- else
- {
- base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- len = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- }
-
- printf("NPE message history [last %d messages, from least to most recent]:\n", len);
-
- for (; i < len ; i++)
- {
- UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH;
- printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]);
- }
-}
-
-IX_ETH_DB_PUBLIC
-void ixEthDBELTShow(IxEthDBPortId portID)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- /* send EDB_GetMACAddressDatabase message */
- FILL_GETMACADDRESSDATABASE(message,
- 0 /* reserved */,
- IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- /* analyze NPE copy */
- UINT32 eltEntryOffset;
- UINT32 entryPortID;
-
- UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone;
- UINT32 eltSize = FULL_ELT_BYTE_SIZE;
-
- /* invalidate cache */
- IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize);
-
- printf("Listing records in main learning tree for port %d\n", portID);
-
- for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE)
- {
- /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node
- *
- * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit]
- * therefore we can just use the pointer for database searches as only the first 6 bytes are checked
- */
- void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset);
-
- if (IX_EDB_NPE_NODE_VALID(eltNodeAddress))
- {
- HashNode *node;
-
- entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress));
-
- /* search record */
- node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES);
-
- printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID,
- IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive");
-
- /* safety check, maybe user deleted record right before sync? */
- if (node != NULL)
- {
- /* found record */
- MacDescriptor *descriptor = (MacDescriptor *) node->data;
-
- printf("- %s ",
- descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" :
- descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" :
- descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)");
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ",
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ",
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
- descriptor->recordData.filteringVlanData.ieee802_1qTag);
-
- /* end transaction */
- ixEthDBReleaseHashNode(node);
- }
- else
- {
- printf("- not synced");
- }
-
- printf("\n");
- }
- }
- }
- else
- {
- ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT,
- "EthDB: (ShowELT) Could not complete action (communication failure)\n",
- portID, 0, 0, 0, 0, 0);
- }
-}
-
-#endif
diff --git a/drivers/net/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c
deleted file mode 100644
index 92af331a54..0000000000
--- a/drivers/net/npe/IxEthDBPortUpdate.c
+++ /dev/null
@@ -1,716 +0,0 @@
-/**
- * @file IxEthDBDBPortUpdate.c
- *
- * @brief Implementation of dependency and port update handling
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-/* forward prototype declarations */
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor);
-IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts);
-IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size);
-IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count);
-IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x);
-
-extern HashTable dbHashtable;
-
-/**
- * @brief register types requiring automatic updates
- *
- * @param typeArray array indexed on record types, each
- * element indicating whether the record type requires an
- * automatic update (true) or not (false)
- *
- * Automatic updates are done for registered record types
- * upon adding, updating (that is, updating the record portID)
- * and removing records. Whenever an automatic update is triggered
- * the appropriate ports will be provided with new database
- * information.
- *
- * It is assumed that the typeArray parameter is allocated large
- * enough to hold all the user defined types. Also, the type
- * array should be initialized to false as this function only
- * caters for types which do require automatic updates.
- *
- * Note that this function should be called by the component
- * initialization function.
- *
- * @return number of record types registered for automatic
- * updates
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray)
-{
- typeArray[IX_ETH_DB_FILTERING_RECORD] = true;
- typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true;
-
- return 2;
-}
-
-/**
- * @brief computes dependencies and triggers port learning tree updates
- *
- * @param triggerPorts port map consisting in the ports which triggered the update
- *
- * This function browses through all the ports and determines how to waterfall the update
- * event from the trigger ports to all other ports depending on them.
- *
- * Once the list of ports to be updated is determined this function
- * calls @ref ixEthDBCreateTrees.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts)
-{
- IxEthDBPortMap updatePorts;
- UINT32 portIndex;
-
- ixEthDBUpdateLock();
-
- SET_EMPTY_DEPENDENCY_MAP(updatePorts);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *port = &ixEthDBPortInfo[portIndex];
- BOOL mapsCollide;
-
- MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap);
-
- if (mapsCollide /* do triggers influence this port? */
- && !IS_PORT_INCLUDED(portIndex, updatePorts) /* and it's not already in the update list */
- && port->updateMethod.updateEnabled) /* and we're allowed to update it */
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex);
-
- JOIN_PORT_TO_MAP(updatePorts, portIndex);
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex);
-
- if (!mapsCollide)
- {
- IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex);
- }
-
- if (IS_PORT_INCLUDED(portIndex, updatePorts))
- {
- IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex);
- }
-
- if (!port->updateMethod.updateEnabled)
- {
- IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex);
- }
- }
- }
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n");
-
- ixEthDBCreateTrees(updatePorts);
-
- ixEthDBUpdateUnlock();
-}
-
-/**
- * @brief creates learning trees and calls the port update handlers
- *
- * @param updatePorts set of ports in need of learning trees
- *
- * This function determines the optimal method of creating learning
- * trees using a minimal number of database queries, keeping in mind
- * that different ports can either use the same learning trees or they
- * can partially share them. The actual tree building routine is
- * @ref ixEthDBQuery.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBCreateTrees(IxEthDBPortMap updatePorts)
-{
- UINT32 portIndex;
- BOOL result;
- BOOL portsLeft = true;
-
- while (portsLeft)
- {
- /* get port with minimal dependency map and NULL search tree */
- UINT32 minPortIndex = MAX_PORT_SIZE;
- UINT32 minimalSize = MAX_PORT_SIZE;
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- UINT32 size;
- PortInfo *port = &ixEthDBPortInfo[portIndex];
-
- /* generate trees only for ports that need them */
- if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts))
- {
- GET_MAP_SIZE(port->dependencyPortMap, size);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n",
- portIndex, size);
-
- if (size < minimalSize)
- {
- minPortIndex = portIndex;
- minimalSize = size;
- }
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex,
- port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query");
- }
- }
-
- /* if a port was found than minimalSize is not MAX_PORT_SIZE */
- if (minimalSize != MAX_PORT_SIZE)
- {
- /* minPortIndex is the port we seek */
- PortInfo *port = &ixEthDBPortInfo[minPortIndex];
-
- IxEthDBPortMap query;
- MacTreeNode *baseTree;
-
- /* now try to find a port with minimal map difference */
- PortInfo *minimalDiffPort = NULL;
- UINT32 minimalDiff = MAX_PORT_SIZE;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *diffPort = &ixEthDBPortInfo[portIndex];
- BOOL mapIsSubset;
-
- IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap);
-
-
- if (portIndex != minPortIndex
- && diffPort->updateMethod.searchTree != NULL
- && mapIsSubset)
- {
- /* compute size and pick only minimal size difference */
- UINT32 diffPortSize;
- UINT32 sizeDifference;
-
- GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex);
-
- sizeDifference = minimalSize - diffPortSize;
-
- if (sizeDifference < minimalDiff)
- {
- minimalDiffPort = diffPort;
- minimalDiff = sizeDifference;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n",
- minimalDiff, portIndex);
- }
- }
- }
-
- /* check if filtering is enabled on this port */
- if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0)
- {
- /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */
- if (minimalDiff != MAX_PORT_SIZE)
- {
- baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree);
- DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n",
- minimalDiffPort->portID);
- }
- else /* .. otherwise no similar port was found, build tree from scratch */
- {
- baseTree = NULL;
-
- COPY_DEPENDENCY_MAP(query, port->dependencyPortMap);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n");
- }
-
- IS_EMPTY_DEPENDENCY_MAP(result, query);
-
- if (!result) /* otherwise we don't need anything more on top of the cloned tree */
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex);
-
- /* build learning tree */
- port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE);
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n");
-
- port->updateMethod.searchTree = baseTree;
- }
- }
- else
- {
- /* filtering is not enabled, will download an empty tree */
- if (port->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
- }
-
- port->updateMethod.searchTree = NULL;
- }
-
- /* mark tree as valid */
- port->updateMethod.searchTreePendingWrite = true;
- }
- else
- {
- portsLeft = false;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n");
- }
- }
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- PortInfo *updatePort = &ixEthDBPortInfo[portIndex];
-
- if (updatePort->updateMethod.searchTreePendingWrite)
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n",
- updatePort->updateMethod.searchTree != NULL ? "not " : "",
- portIndex);
-
- updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD);
- }
- }
-}
-
-/**
- * @brief standard NPE update handler
- *
- * @param portID id of the port to be updated
- * @param type record type to be pushed during this update
- *
- * The NPE update handler manages updating the NPE databases
- * given a certain record type.
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type)
-{
- UINT32 epDelta, blockCount;
- IxNpeMhMessage message;
- UINT32 treeSize = 0;
- PortInfo *port = &ixEthDBPortInfo[portID];
-
- /* size selection and type check */
- if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
- {
- treeSize = FULL_ELT_BYTE_SIZE;
- }
- else if (type == IX_ETH_DB_FIREWALL_RECORD)
- {
- treeSize = FULL_FW_BYTE_SIZE;
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- /* serialize tree into memory */
- ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount);
-
- /* free internal copy */
- if (port->updateMethod.searchTree != NULL)
- {
- ixEthDBFreeMacTreeNode(port->updateMethod.searchTree);
- }
-
- /* forget last used search tree */
- port->updateMethod.searchTree = NULL;
- port->updateMethod.searchTreePendingWrite = false;
-
- /* dependending on the update type we do different things */
- if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD)
- {
- IX_STATUS result;
-
- FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- epDelta, blockCount,
- IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone));
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- if (result == IX_SUCCESS)
- {
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID);
- }
- else
- {
- ixEthDBPortInfo[portID].agingEnabled = false;
- ixEthDBPortInfo[portID].updateMethod.updateEnabled = false;
- ixEthDBPortInfo[portID].updateMethod.userControlled = true;
-
- ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID);
-
- ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES);
-
- return IX_ETH_DB_FAIL;
- }
-
- return IX_ETH_DB_SUCCESS;
- }
- else if (type == IX_ETH_DB_FIREWALL_RECORD)
- {
- return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta);
- }
-
- return IX_ETH_DB_INVALID_ARG;
-}
-
-/**
- * @brief queries the database for a set of records to be inserted into a given tree
- *
- * @param searchTree pointer to a tree where insertions will be performed; can be NULL
- * @param query set of ports that a database record must match to be inserted into the tree
- *
- * The query method browses through the database, extracts all the descriptors matching
- * the given query parameter and inserts them into the given learning tree.
- * Note that this is an append procedure, the given tree needs not to be empty.
- * A "descriptor matching the query" is a descriptor whose port id is in the query map.
- * If the given tree is empty (NULL) a new tree is created and returned.
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries)
-{
- HashIterator iterator;
- UINT32 entryCount = 0;
-
- /* browse database */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ",
- mac2string(descriptor->macAddress),
- descriptor->portID);
-
- if ((descriptor->type & recordFilter) != 0
- && IS_PORT_INCLUDED(descriptor->portID, query))
- {
- MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor);
-
- IX_ETH_DB_UPDATE_TRACE("match\n");
-
- if (descriptorClone != NULL)
- {
- /* add descriptor to tree */
- searchTree = ixEthDBTreeInsert(searchTree, descriptorClone);
-
- entryCount++;
- }
- }
- else
- {
- IX_ETH_DB_UPDATE_TRACE("no match\n");
- }
-
- if (entryCount < maxEntries)
- {
- /* advance to the next record */
- BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator));
- }
- else
- {
- /* the NPE won't accept more entries so we can stop now */
- ixEthDBReleaseHashIterator(&iterator);
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n");
-
- break;
- }
- }
-
- IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount);
-
- return ixEthDBTreeRebalance(searchTree);
-}
-
-/**
- * @brief inserts a mac descriptor into an tree
- *
- * @param searchTree tree where the insertion is to be performed (may be NULL)
- * @param descriptor descriptor to insert into tree
- *
- * @return the tree root
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor)
-{
- MacTreeNode *currentNode = searchTree;
- MacTreeNode *insertLocation = NULL;
- MacTreeNode *newNode;
- INT32 insertPosition = RIGHT;
-
- if (descriptor == NULL)
- {
- return searchTree;
- }
-
- /* create a new node */
- newNode = ixEthDBAllocMacTreeNode();
-
- if (newNode == NULL)
- {
- /* out of memory */
- ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__);
-
- ixEthDBFreeMacDescriptor(descriptor);
-
- return NULL;
- }
-
- /* populate node */
- newNode->descriptor = descriptor;
-
- /* an empty initial tree is a special case */
- if (searchTree == NULL)
- {
- return newNode;
- }
-
- /* get insertion location */
- while (insertLocation == NULL)
- {
- MacTreeNode *nextNode;
-
- /* compare given key with current node key */
- insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress);
-
- /* navigate down */
- if (insertPosition == RIGHT)
- {
- nextNode = currentNode->right;
- }
- else if (insertPosition == LEFT)
- {
- nextNode = currentNode->left;
- }
- else
- {
- /* error, duplicate key */
- ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n");
-
- /* this will free the MAC descriptor as well */
- ixEthDBFreeMacTreeNode(newNode);
-
- return searchTree;
- }
-
- /* when we can no longer dive through the tree we found the insertion place */
- if (nextNode != NULL)
- {
- currentNode = nextNode;
- }
- else
- {
- insertLocation = currentNode;
- }
- }
-
- /* insert node */
- if (insertPosition == RIGHT)
- {
- insertLocation->right = newNode;
- }
- else
- {
- insertLocation->left = newNode;
- }
-
- return searchTree;
-}
-
-/**
- * @brief balance a tree
- *
- * @param searchTree tree to balance
- *
- * Converts a tree into a balanced tree and returns the root of
- * the balanced tree. The resulting tree is <i>route balanced</i>
- * not <i>perfectly balanced</i>. This makes no difference to the
- * average tree search time which is the same in both cases, O(log2(n)).
- *
- * @return root of the balanced tree or NULL if there's no memory left
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree)
-{
- MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode();
- UINT32 size;
-
- if (pseudoRoot == NULL)
- {
- /* out of memory */
- return NULL;
- }
-
- pseudoRoot->right = searchTree;
-
- ixEthDBRebalanceTreeToVine(pseudoRoot, &size);
- ixEthDBRebalanceVineToTree(pseudoRoot, size);
-
- searchTree = pseudoRoot->right;
-
- /* remove pseudoRoot right branch, otherwise it will free the entire tree */
- pseudoRoot->right = NULL;
-
- ixEthDBFreeMacTreeNode(pseudoRoot);
-
- return searchTree;
-}
-
-/**
- * @brief converts a tree into a vine
- *
- * @param root root of tree to convert
- * @param size depth of vine (equal to the number of nodes in the tree)
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size)
-{
- MacTreeNode *vineTail = root;
- MacTreeNode *remainder = vineTail->right;
- MacTreeNode *tempPtr;
-
- *size = 0;
-
- while (remainder != NULL)
- {
- if (remainder->left == NULL)
- {
- /* move tail down one */
- vineTail = remainder;
- remainder = remainder->right;
- (*size)++;
- }
- else
- {
- /* rotate around remainder */
- tempPtr = remainder->left;
- remainder->left = tempPtr->right;
- tempPtr->right = remainder;
- remainder = tempPtr;
- vineTail->right = tempPtr;
- }
- }
-}
-
-/**
- * @brief converts a vine into a balanced tree
- *
- * @param root vine to convert
- * @param size depth of vine
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size)
-{
- UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1));
-
- ixEthDBRebalanceCompression(root, leafCount);
-
- size = size - leafCount;
-
- while (size > 1)
- {
- ixEthDBRebalanceCompression(root, size / 2);
-
- size /= 2;
- }
-}
-
-/**
- * @brief compresses a vine/tree stage into a more balanced vine/tree
- *
- * @param root root of the tree to compress
- * @param count number of "spine" nodes
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count)
-{
- MacTreeNode *scanner = root;
- MacTreeNode *child;
- UINT32 local_index;
-
- for (local_index = 0 ; local_index < count ; local_index++)
- {
- child = scanner->right;
- scanner->right = child->right;
- scanner = scanner->right;
- child->right = scanner->left;
- scanner->left = child;
- }
-}
-
-/**
- * @brief computes |_log2(x)_| (a.k.a. floor(log2(x)))
- *
- * @param x number to compute |_log2(x)_| for
- *
- * @return |_log2(x)_|
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-UINT32 ixEthDBRebalanceLog2Floor(UINT32 x)
-{
- UINT32 log = 0;
- UINT32 val = 1;
-
- while (val < x)
- {
- log++;
- val <<= 1;
- }
-
- return val == x ? log : log - 1;
-}
-
diff --git a/drivers/net/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c
deleted file mode 100644
index d74f1215fd..0000000000
--- a/drivers/net/npe/IxEthDBReports.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/**
- * @file IxEthDBAPI.c
- *
- * @brief Implementation of the public API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter);
-IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter);
-IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map);
-
-/**
- * @brief displays a port dependency map
- *
- * @param portID ID of the port
- * @param map port map to display
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map)
-{
- UINT32 portIndex;
- BOOL mapSelf = true, mapNone = true, firstPort = true;
-
- /* dependency port maps */
- printf("Dependency port map: ");
-
- /* browse the port map */
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- if (IS_PORT_INCLUDED(portIndex, map))
- {
- mapNone = false;
-
- if (portIndex != portID)
- {
- mapSelf = false;
- }
-
- printf("%s%d", firstPort ? "{" : ", ", portIndex);
-
- firstPort = false;
- }
- }
-
- if (mapNone)
- {
- mapSelf = false;
- }
-
- printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group");
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to a port
- *
- * @param portID ID of the port to display
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords()
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID)
-{
- IxEthDBStatus local_result;
- HashIterator iterator;
- PortInfo *portInfo;
- UINT32 recordCount = 0;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- /* display table header */
- printf("Ethernet database records for port ID [%d]\n", portID);
-
- ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf("updates disabled (not an NPE)\n\n");
- }
-
- printf(" MAC address | Age | Type \n");
- printf("___________________________________\n");
-
- /* browse database */
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- recordCount++;
-
- /* display entry */
- printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d | %s\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
-
- /* move to the next record */
- BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
- /* debug */
- if (local_result == IX_ETH_DB_BUSY)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- /* display number of records */
- printf("\nFound %d records\n", recordCount);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays all the filtering records belonging to all the ports
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords()
- * instead. Calling this function is equivalent to calling
- * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD)
- */
-IX_ETH_DB_PUBLIC
-void ixEthDBFilteringDatabaseShowAll()
-{
- IxEthDBPortId portIndex;
-
- printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS);
-
- for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++)
- {
- ixEthDBFilteringDatabaseShow(portIndex);
-
- if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1)
- {
- printf("\n");
- }
- }
-}
-
-/**
- * @brief displays one record in a format depending on the record filter
- *
- * @param descriptor pointer to the record
- * @param recordFilter format filter
- *
- * This function will display the fields in a record depending on the
- * selected record filter.
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter)
-{
- if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
- || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
- {
- /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n");
- printf("___________________________________________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic",
- IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
- (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
- IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
- }
- else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
- {
- /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Age | Type \n");
- printf("_______________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic");
- }
- }
- else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
- {
- /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | GW MAC address \n");
- printf("_______________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
- {
- if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* gateway address present */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.wifiData.gwMacAddress[0],
- descriptor->recordData.wifiData.gwMacAddress[1],
- descriptor->recordData.wifiData.gwMacAddress[2],
- descriptor->recordData.wifiData.gwMacAddress[3],
- descriptor->recordData.wifiData.gwMacAddress[4],
- descriptor->recordData.wifiData.gwMacAddress[5]);
- }
- else
- {
- /* no gateway */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- }
- else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
- {
- /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address \n");
- printf("__________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
- {
- /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header
- printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n");
- printf("_______________________________________________________________________________\n"); */
-
- if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | VLAN | %2d | %s | %4d | %1d | %1d | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringVlanData.age,
- descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic",
- IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag),
- (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12,
- IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag));
- }
- else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.filteringData.age,
- descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic");
- }
- else if (descriptor->type == IX_ETH_DB_WIFI_RECORD)
- {
- if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP)
- {
- /* gateway address present */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>AP | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5],
- descriptor->recordData.wifiData.gwMacAddress[0],
- descriptor->recordData.wifiData.gwMacAddress[1],
- descriptor->recordData.wifiData.gwMacAddress[2],
- descriptor->recordData.wifiData.gwMacAddress[3],
- descriptor->recordData.wifiData.gwMacAddress[4],
- descriptor->recordData.wifiData.gwMacAddress[5]);
- }
- else
- {
- /* no gateway */
- printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>ST | ---- | - | --- | -- no gateway -- \n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD)
- {
- printf("%02X:%02X:%02X:%02X:%02X:%02X | FW | -- | ------- | ---- | - | --- | -----------------\n",
- descriptor->macAddress[0],
- descriptor->macAddress[1],
- descriptor->macAddress[2],
- descriptor->macAddress[3],
- descriptor->macAddress[4],
- descriptor->macAddress[5]);
- }
- }
- else
- {
- printf("invalid record filter\n");
- }
-}
-
-/**
- * @brief displays the status, records and configuration information of a port
- *
- * @param portID ID of the port
- * @param recordFilter record filter to display
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- UINT32 recordCount = 0;
- HashIterator iterator;
- IxEthDBStatus local_result;
-
- /* display port status */
- printf("== Port ID %d ==\n", portID);
-
- /* display capabilities */
- printf("- Capabilities: ");
-
- if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0)
- {
- printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0)
- {
- printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0)
- {
- printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off");
- }
-
- printf("\n");
-
- /* dependency map */
- ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap);
-
- /* NPE dynamic updates */
- if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE)
- {
- printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf(" - dynamic update disabled (not an NPE)\n");
- }
-
- if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0)
- {
- /* WiFi header conversion */
- if ((portInfo->frameControlDurationID
- + portInfo->bbsid[0]
- + portInfo->bbsid[1]
- + portInfo->bbsid[2]
- + portInfo->bbsid[3]
- + portInfo->bbsid[4]
- + portInfo->bbsid[5]) == 0)
- {
- printf(" - WiFi header conversion not configured\n");
- }
- else
- {
- printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n",
- portInfo->bbsid[0],
- portInfo->bbsid[1],
- portInfo->bbsid[2],
- portInfo->bbsid[3],
- portInfo->bbsid[4],
- portInfo->bbsid[5],
- portInfo->frameControlDurationID >> 16,
- portInfo->frameControlDurationID & 0xFFFF);
- }
- }
- else
- {
- printf(" - WiFi header conversion not enabled\n");
- }
- }
-
- /* Firewall */
- if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0)
- {
- if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0)
- {
- printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white");
- printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled");
- }
- else
- {
- printf(" - Firewall not enabled\n");
- }
- }
-
- /* browse database if asked to display records */
- if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE)
- {
- printf("\n");
- ixEthDBHeaderShow(recordFilter);
-
- BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator));
-
- while (IS_ITERATOR_VALID(&iterator))
- {
- MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data;
-
- if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0)
- {
- recordCount++;
-
- /* display entry */
- ixEthDBRecordShow(descriptor, recordFilter);
- }
-
- /* move to the next record */
- BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result);
-
- /* debug */
- if (local_result == IX_ETH_DB_BUSY)
- {
- printf("EthDB (API): Error, database browser failed (no access), giving up\n");
- }
- }
-
- printf("\nFound %d records\n\n", recordCount);
- }
-}
-
-/**
- * @brief displays a record header
- *
- * @param recordFilter record type filter
- *
- * This function displays a record header, depending on
- * the given record type filter. It is useful when used
- * in conjunction with ixEthDBRecordShow which will display
- * record fields formatted for the header, provided the same
- * record filter is used.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter
- * parameter is invalid or not supported
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter)
-{
- if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD
- || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD))
- {
- /* display VLAN record header */
- printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n");
- printf("___________________________________________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_FILTERING_RECORD)
- {
- /* display filtering record header */
- printf(" MAC address | Age | Type \n");
- printf("_______________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_WIFI_RECORD)
- {
- /* display WiFi record header */
- printf(" MAC address | GW MAC address \n");
- printf("_______________________________________\n");
- }
- else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD)
- {
- /* display Firewall record header */
- printf(" MAC address \n");
- printf("__________________\n");
- }
- else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES)
- {
- /* display composite record header */
- printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n");
- printf("_______________________________________________________________________________\n");
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief displays database information (records and port information)
- *
- * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports)
- * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only
- * port information)
- *
- * Note that this function is documented in the main component header
- * file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully or
- * an appropriate error code otherwise
- *
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter)
-{
- IxEthDBPortId currentPort;
- BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS);
-
- IX_ETH_DB_CHECK_PORT_ALL(portID);
-
- printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1);
-
- currentPort = showAllPorts ? 0 : portID;
-
- while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS)
- {
- /* display port info */
- ixEthDBPortInfoShow(currentPort, recordFilter);
-
- /* next port */
- currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS;
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
diff --git a/drivers/net/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c
deleted file mode 100644
index 4fd28da080..0000000000
--- a/drivers/net/npe/IxEthDBSearch.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/**
- * @file IxEthDBSearch.c
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB_p.h"
-
-extern HashTable dbHashtable;
-
-/**
- * @brief matches two database records based on their MAC addresses
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return false;
-
- return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and VLAN IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return false;
-
- return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) ==
- IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) &&
- (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief matches two database records based on their MAC addresses
- * and port IDs
- *
- * @param untypedReference record to match against
- * @param untypedEntry record to match
- *
- * @return true if the match is successful or false otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry)
-{
- MacDescriptor *entry = (MacDescriptor *) untypedEntry;
- MacDescriptor *reference = (MacDescriptor *) untypedReference;
-
- /* check accepted record types */
- if ((entry->type & reference->type) == 0) return false;
-
- return (entry->portID == reference->portID) &&
- (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0);
-}
-
-/**
- * @brief dummy matching function, registered for safety
- *
- * @param reference record to match against (unused)
- * @param entry record to match (unused)
- *
- * This function is registered in the matching functions
- * array on invalid types. Calling it will display an
- * error message, indicating an error in the component logic.
- *
- * @return false
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBNullMatch(void *reference, void *entry)
-{
- /* display an error message */
-
- ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0);
-
-
- return false;
-}
-
-/**
- * @brief registers hash matching methods
- *
- * @param matchFunctions table of match functions to be populated
- *
- * This function registers the available record matching functions
- * by indexing them on record types into the given function array.
- *
- * Note that it is compulsory to call this in ixEthDBInit(),
- * otherwise hashtable searching and removal will not work
- *
- * @return number of registered functions
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions)
-{
- UINT32 i;
-
- /* safety first */
- for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++)
- {
- matchFunctions[i] = ixEthDBNullMatch;
- }
-
- /* register MAC search method */
- matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch;
-
- /* register MAC/PortID search method */
- matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch;
-
- /* register MAC/VLAN ID search method */
- matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch;
-
- return 3; /* three methods */
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult));
-
- return searchResult;
-}
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter)
-{
- MacDescriptor reference;
- IxEthDBStatus result;
-
- TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER;
-
- if (macAddress == NULL)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference);
-
- return result;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param portID port ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/port ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
- reference.portID = portID;
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult));
-
- return searchResult;
-}
-
-/**
- * @brief search a record in the Ethernet datbase
- *
- * @param macAddress MAC address to perform the search on
- * @param vlanID VLAN ID to perform the search on
- * @param typeFilter type of records to consider for matching
- *
- * @warning if searching is successful an implicit write lock
- * to the search result is granted, therefore unlock the
- * entry using @ref ixEthDBReleaseHashNode() as soon as possible.
- *
- * @see ixEthDBReleaseHashNode()
- *
- * @return the search result, or NULL if a record with the given
- * MAC address/VLAN ID combination was not found
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter)
-{
- HashNode *searchResult = NULL;
- MacDescriptor reference;
-
- if (macAddress == NULL)
- {
- return NULL;
- }
-
- /* fill search fields */
- memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr));
- reference.recordData.filteringVlanData.ieee802_1qTag =
- IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID);
-
- /* set acceptable record types */
- reference.type = typeFilter;
-
- BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult));
-
- return searchResult;
-}
diff --git a/drivers/net/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c
deleted file mode 100644
index e12be0d884..0000000000
--- a/drivers/net/npe/IxEthDBSpanningTree.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
- * @file IxEthDBSpanningTree.c
- *
- * @brief Implementation of the STP API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxEthDB_p.h"
-
-/**
- * @brief sets the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked true to block the port or false to unblock it
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-
- ixEthDBPortInfo[portID].stpBlocked = blocked;
-
- FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief retrieves the STP blocking state of a port
- *
- * @param portID ID of the port
- * @param blocked address to write the blocked status into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL);
-
- IX_ETH_DB_CHECK_REFERENCE(blocked);
-
- *blocked = ixEthDBPortInfo[portID].stpBlocked;
-
- return IX_ETH_DB_SUCCESS;
-}
diff --git a/drivers/net/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c
deleted file mode 100644
index 40d4470bef..0000000000
--- a/drivers/net/npe/IxEthDBUtil.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/**
- * @file ethUtil.c
- *
- * @brief Utility functions
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-
-#include "IxFeatureCtrl.h"
-#include "IxEthDB_p.h"
-
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID)
-{
- /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */
- if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 !=
- (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK))
- || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ()))
- {
- if ((portID == 0) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
-
- if ((portID == 1) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
-
- if ((portID == 2) &&
- (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) ==
- IX_FEATURE_CTRL_COMPONENT_DISABLED))
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
-}
-
-IX_ETH_DB_PUBLIC
-BOOL ixEthDBCheckSingleBitValue(UINT32 value)
-{
-#if (CPU != SIMSPARCSOLARIS) && !defined (__wince)
- UINT32 shift;
-
- /* use the count-leading-zeros XScale instruction */
- __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value));
-
- return ((value << shift) == 0x80000000UL);
-
-#else
-
- while (value != 0)
- {
- if (value == 1) return true;
- else if ((value & 1) == 1) return false;
-
- value >>= 1;
- }
-
- return false;
-
-#endif
-}
-
-const char *mac2string(const unsigned char *mac)
-{
- static char str[19];
-
- if (mac == NULL)
- {
- return NULL;
- }
-
- sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-
- return str;
-}
diff --git a/drivers/net/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c
deleted file mode 100644
index 483e348934..0000000000
--- a/drivers/net/npe/IxEthDBVlan.c
+++ /dev/null
@@ -1,1155 +0,0 @@
-/**
- * @file IxEthDBVlan.c
- *
- * @brief Implementation of the VLAN API
- *
- * @par
- * IXP400 SW Release version 2.0
- *
- * -- Copyright Notice --
- *
- * @par
- * Copyright 2001-2005, Intel Corporation.
- * All rights reserved.
- *
- * @par
- * SPDX-License-Identifier: BSD-3-Clause
- * @par
- * -- End of Copyright Notice --
- */
-
-#include "IxEthDB.h"
-#include "IxEthDB_p.h"
-
-/* forward prototypes */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex);
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet);
-
-/* contants used by various functions as "action" parameter */
-#define ADD_VLAN (0x1)
-#define REMOVE_VLAN (0x2)
-
-/**
- * @brief adds or removes a VLAN from a VLAN set
- *
- * @param vlanID VLAN ID to add or remove
- * @param table VLAN set to add into or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action)
-{
- UINT32 setOffset;
-
- /* add/remove VID to membership table */
- setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */
-
- if (action == ADD_VLAN)
- {
- table[setOffset] |= 1 << VLAN_SET_MASK(vlanID);
- }
- else if (action == REMOVE_VLAN)
- {
- table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID));
- }
-}
-
-/**
- * @brief updates a set of 8 VLANs in an NPE
- *
- * @param portID ID of the port
- * @param setOffset offset of the 8 VLANs
- *
- * This function updates the VLAN membership table
- * and Transmit Tagging Info table for 8 consecutive
- * VLAN IDs indexed by setOffset.
- *
- * For example, a setOffset of 0 indexes VLAN IDs 0
- * through 7, 1 indexes VLAN IDs 8 through 9 etc.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- 2 * setOffset,
- portInfo->vlanMembership[setOffset],
- portInfo->transmitTaggingInfo[setOffset]);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief updates a VLAN range in an NPE
- *
- * @param portID ID of the port
- *
- * This function is similar to @ref ixEthDBVlanTableEntryUpdate
- * except that it can update more than one VLAN set (up to
- * the entire VLAN membership and TTI tables if the offset is 0
- * and length is sizeof (IxEthDBVlanSet) (512 bytes).
- *
- * Updating the NPE via this method is slower as it requires
- * a memory copy from SDRAM, hence it is recommended that the
- * ixEthDBVlanTableEntryUpdate function is used where possible.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone;
- IxNpeMhMessage message;
- UINT32 setIndex;
- IX_STATUS result;
-
- /* copy membership info and transmit tagging into into exchange area */
- for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++)
- {
- /* membership and TTI data are interleaved */
- vlanUpdateZone[setIndex * 2] = portInfo->vlanMembership[setIndex];
- vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex];
- }
-
- IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE);
-
- /* build NPE message */
- FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0,
- IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone));
-
- /* send message */
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief adds or removes a VLAN from a port's VLAN membership table
- * or Transmit Tagging Information table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add or remove
- * @param table to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed
- * successfully or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action)
-{
- /* change VLAN in local membership table */
- ixEthDBLocalVlanMembershipChange(vlanID, table, action);
-
- /* send updated entry to NPE */
- return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID));
-}
-
-/**
- * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag port VLAN tag (802.1Q tag)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* add VLAN ID to local membership table */
- ixEthDBPortVlanMembershipChange(portID,
- vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK,
- ixEthDBPortInfo[portID].vlanMembership,
- ADD_VLAN);
-
- /* set tag in portInfo */
- ixEthDBPortInfo[portID].vlanTag = vlanTag;
-
- /* build VLAN_SetDefaultRxVID message */
- FILL_SETDEFAULTRXVID_MSG(message,
- IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID),
- IX_IEEE802_1Q_VLAN_TPID,
- vlanTag);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID)
- *
- * @param portID ID of the port
- * @param vlanTag address to write the port VLAN tag (802.1Q tag) into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-
- *vlanTag = ixEthDBPortInfo[portID].vlanTag;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a
- * database filtering record
- *
- * @param portID ID of the port
- * @param vlanTag VLAN tag (802.1Q tag)
- *
- * Important: filtering records are automatically converted to
- * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag.
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_VLAN_TAG(vlanTag);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* set record type to VLAN if not already set */
- descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD;
-
- /* add vlan tag */
- descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag;
-
- /* transaction completed */
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a
- * database VLAN filtering record
- *
- * @param portID ID of the port
- * @param vlanTag address to write the VLAN tag (802.1Q tag) into
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag)
-{
- HashNode *searchResult;
- MacDescriptor *descriptor;
-
- IX_ETH_DB_CHECK_REFERENCE(macAddr);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanTag);
-
- searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD);
-
- if (searchResult == NULL)
- {
- return IX_ETH_DB_NO_SUCH_ADDR;
- }
-
- descriptor = (MacDescriptor *) searchResult->data;
-
- /* get vlan tag */
- *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag;
-
- /* transaction completed */
- ixEthDBReleaseHashNode(searchResult);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief adds a VLAN to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to add
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to remove
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */
- vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK;
-
- /* check we're not asked to remove the default port VID */
- if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag))
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief adds or removes a VLAN range from a port's
- * VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- * @param table VLAN set to add or remove from
- * @param action ADD_VLAN or REMOVE_VLAN
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action)
-{
- UINT32 setOffsetMin, setOffsetMax;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax);
-
- /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */
- vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK;
- vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK;
-
- /* is this a range? */
- if (vlanIDMax < vlanIDMin)
- {
- return IX_ETH_DB_INVALID_VLAN;
- }
-
- /* check that we're not specifically asked to remove the default port VID */
- if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin)
- {
- return IX_ETH_DB_NO_PERMISSION;
- }
-
- /* compute set offsets */
- setOffsetMin = VLAN_SET_OFFSET(vlanIDMin);
- setOffsetMax = VLAN_SET_OFFSET(vlanIDMax);
-
- /* change VLAN range */
- for (; vlanIDMin <= vlanIDMax ; vlanIDMin++)
- {
- /* change vlan in local membership table */
- ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action);
- }
-
- /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */
- if (setOffsetMin == setOffsetMax)
- {
- /* send updated entry to NPE */
- return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin);
- }
- else
- {
- /* update a zone of the membership/transmit tag info table */
- return ixEthDBVlanTableRangeUpdate(portID);
- }
-}
-
-/**
- * @brief adds a VLAN range to a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN);
-}
-
-/**
- * @brief removes a VLAN range from a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanIDMin start of the VLAN range
- * @param vlanIDMax end of the VLAN range
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN);
-}
-
-/**
- * @brief sets a port's VLAN membership table or TTI table and
- * updates the NPE VLAN configuration
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to set
- * @param vlanSet new set contents
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet));
-
- return ixEthDBVlanTableRangeUpdate(portID);
-}
-
-/**
- * @brief retireves a port's VLAN membership table or TTI table
- *
- * @param portID ID of the port
- * @param portVlanTable port VLAN table to retrieve
- * @param vlanSet address to
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet));
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet new VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IxEthDBVlanId vlanID;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- /* set the bit corresponding to the PVID just in case */
- vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
- vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-
- return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief retrieves a port's VLAN membership table
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's VLAN membership table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet);
-}
-
-/**
- * @brief enables or disables Egress tagging for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to enable or disable Egress tagging on
- * @param enabled true to enable and false to disable tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief retrieves the Egress tagging status for one VLAN ID
- *
- * @param portID ID of the port
- * @param vlanID VLAN ID to retrieve the tagging status for
- * @param enabled location to store the tagging status
- * (true - tagging enabled, false - tagging disabled)
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(enabled);
-
- IX_ETH_DB_CHECK_VLAN_ID(vlanID);
-
- *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0);
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief enables or disables Egress VLAN tagging for a VLAN range
- *
- * @param portID ID of the port
- * @param vlanIDMin start of VLAN range
- * @param vlanIDMax end of VLAN range
- * @param enabled true to enable or false to disable VLAN tagging
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN);
-}
-
-/**
- * @brief sets the Egress VLAN tagging table (the Transmit Tagging
- * Information table)
- *
- * @param portID ID of the port
- * @param vlanSet new TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IxEthDBVlanId vlanID;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_REFERENCE(vlanSet);
-
- /* set the PVID bit just in case */
- vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag);
- vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID);
-
- return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief retrieves the Egress VLAN tagging table (the Transmit
- * Tagging Information table)
- *
- * @param portID ID of the port
- * @param vlanSet location to store the port's TTI table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet);
-}
-
-/**
- * @brief sends the NPE the updated frame filter and default
- * Ingress tagging
- *
- * @param portID ID of the port
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PRIVATE
-IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID)
-{
- PortInfo *portInfo = &ixEthDBPortInfo[portID];
- IxNpeMhMessage message;
- IX_STATUS result;
-
- FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction);
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the default Ingress tagging behavior
- *
- * @param portID ID of the port
- * @param taggingAction default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction)
-{
- PortInfo *portInfo;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- portInfo = &ixEthDBPortInfo[portID];
-
- if (taggingAction == IX_ETH_DB_PASS_THROUGH)
- {
- portInfo->npeTaggingAction = 0x00;
- }
- else if (taggingAction == IX_ETH_DB_ADD_TAG)
- {
- portInfo->npeTaggingAction = 0x02;
- }
- else if (taggingAction == IX_ETH_DB_REMOVE_TAG)
- {
- portInfo->npeTaggingAction = 0x01;
- }
- else
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- portInfo->taggingAction = taggingAction;
-
- return ixEthDBIngressVlanModeUpdate(portID);
-}
-
-/**
- * @brief retrieves the default Ingress tagging behavior of a port
- *
- * @param portID ID of the port
- * @param taggingAction location to save the default tagging behavior
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(taggingAction);
-
- *taggingAction = ixEthDBPortInfo[portID].taggingAction;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sets the Ingress acceptable frame type filter
- *
- * @param portID ID of the port
- * @param frameFilter acceptable frame type filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter)
-{
- PortInfo *portInfo;
- IxEthDBStatus result = IX_ETH_DB_SUCCESS;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- /* check parameter range
- the ORed value of the valid values is 0x7
- a value having extra bits is invalid */
- if ((frameFilter | 0x7) != 0x7 || frameFilter == 0)
- {
- return IX_ETH_DB_INVALID_ARG;
- }
-
- portInfo = &ixEthDBPortInfo[portID];
-
- portInfo->frameFilter = frameFilter;
- portInfo->npeFrameFilter = 0; /* allow all by default */
-
- /* if accepting priority tagged but not all VLAN tagged
- set the membership table to contain only VLAN ID 0
- hence remove vlans 1-4094 and add VLAN ID 0 */
- if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0)
- && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0))
- {
- result = ixEthDBPortVlanMembershipRangeChange(portID,
- 1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN);
-
- if (result == IX_ETH_DB_SUCCESS)
- {
- ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN);
- result = ixEthDBVlanTableRangeUpdate(portID);
- }
- }
-
- /* untagged only? */
- if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES)
- {
- portInfo->npeFrameFilter = 0x01;
- }
-
- /* tagged only? */
- if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0)
- {
- portInfo->npeFrameFilter = 0x02;
- }
-
- if (result == IX_ETH_DB_SUCCESS)
- {
- result = ixEthDBIngressVlanModeUpdate(portID);
- }
-
- return result;
-}
-
-/**
- * @brief retrieves the acceptable frame type filter for a port
- *
- * @param portID ID of the port
- * @param frameFilter location to store the frame filter
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter)
-{
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(frameFilter);
-
- *frameFilter = ixEthDBPortInfo[portID].frameFilter;
-
- return IX_ETH_DB_SUCCESS;
-}
-
-/**
- * @brief sends an NPE the updated configuration related
- * to one QoS priority (associated traffic class and AQM mapping)
- *
- * @param portID ID of the port
- * @param classIndex QoS priority (traffic class index)
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- *
- * @internal
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex)
-{
- IxNpeMhMessage message;
- IX_STATUS result;
-
- UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex];
- UINT32 aqmQueue = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass];
-
- FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue);
-
- IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result);
-
- return result;
-}
-
-/**
- * @brief sets the priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable new priority mapping table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
- UINT32 classIndex;
-
- IX_ETH_DB_CHECK_PORT(portID);
-
- IX_ETH_DB_CHECK_SINGLE_NPE(portID);
-
- IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS);
-
- IX_ETH_DB_CHECK_REFERENCE(priorityTable);
-
- for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
- {
- /* check range */
- if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount)
- {
- return IX_ETH_DB_INVALID_PRIORITY;
- }
- }
-
- /* set new traffic classes */
- for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++)
- {
- ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex];
-
- if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS)
- {
- return IX_ETH_DB_FAIL;
- }
- }
-
- return IX_ETH_DB_SUCCESS;
- }
-
-/**
- * @brief retrieves a port's priority mapping table
- *
- * @param portID ID of the port
- * @param priorityTable location to store the priority table
- *
- * Note that this function is documented in the main component
- * header file, IxEthDB.h.
- *
- * @return IX_ETH_DB_SUCCESS if the operation completed successfully
- * or an appropriate error message otherwise
- */
-IX_ETH_DB_PUBLIC
-IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable)
-{
- IX_ETH_DB_CHECK_PORT(portID);
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