diff options
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/mem.h | 12 | ||||
| -rw-r--r-- | board/ti/dra7xx/mux_data.h | 36 | ||||
| -rw-r--r-- | include/configs/dra7xx_evm.h | 38 |
3 files changed, 78 insertions, 8 deletions
diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h index d2e708bba5..3e5d655de9 100644 --- a/arch/arm/include/asm/arch-omap5/mem.h +++ b/arch/arm/include/asm/arch-omap5/mem.h @@ -46,13 +46,13 @@ #define M_NAND_GPMC_CONFIG6 0x16000f80 #define M_NAND_GPMC_CONFIG7 0x00000008 -#define STNOR_GPMC_CONFIG1 0x00001200 -#define STNOR_GPMC_CONFIG2 0x00101000 -#define STNOR_GPMC_CONFIG3 0x00030301 -#define STNOR_GPMC_CONFIG4 0x10041004 -#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG1 0x00001000 +#define STNOR_GPMC_CONFIG2 0x001f1f00 +#define STNOR_GPMC_CONFIG3 0x001f1f01 +#define STNOR_GPMC_CONFIG4 0x1f011f01 +#define STNOR_GPMC_CONFIG5 0x001d1f1f #define STNOR_GPMC_CONFIG6 0x08070280 -#define STNOR_GPMC_CONFIG7 0x00000F48 +#define STNOR_GPMC_CONFIG7 0x00000048 /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 1ea236b4b8..5bc4fc9bf1 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -21,6 +21,37 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ +#if defined(CONFIG_NOR) + /* NOR only pin-mux */ + {GPMC_A0 , M0 | IDIS | PDIS}, /* nor.GPMC_A[0 ] */ + {GPMC_A1 , M0 | IDIS | PDIS}, /* nor.GPMC_A[1 ] */ + {GPMC_A2 , M0 | IDIS | PDIS}, /* nor.GPMC_A[2 ] */ + {GPMC_A3 , M0 | IDIS | PDIS}, /* nor.GPMC_A[3 ] */ + {GPMC_A4 , M0 | IDIS | PDIS}, /* nor.GPMC_A[4 ] */ + {GPMC_A5 , M0 | IDIS | PDIS}, /* nor.GPMC_A[5 ] */ + {GPMC_A6 , M0 | IDIS | PDIS}, /* nor.GPMC_A[6 ] */ + {GPMC_A7 , M0 | IDIS | PDIS}, /* nor.GPMC_A[7 ] */ + {GPMC_A8 , M0 | IDIS | PDIS}, /* nor.GPMC_A[8 ] */ + {GPMC_A9 , M0 | IDIS | PDIS}, /* nor.GPMC_A[9 ] */ + {GPMC_A10 , M0 | IDIS | PDIS}, /* nor.GPMC_A[10] */ + {GPMC_A11 , M0 | IDIS | PDIS}, /* nor.GPMC_A[11] */ + {GPMC_A12 , M0 | IDIS | PDIS}, /* nor.GPMC_A[12] */ + {GPMC_A13 , M0 | IDIS | PDIS}, /* nor.GPMC_A[13] */ + {GPMC_A14 , M0 | IDIS | PDIS}, /* nor.GPMC_A[14] */ + {GPMC_A15 , M0 | IDIS | PDIS}, /* nor.GPMC_A[15] */ + {GPMC_A16 , M0 | IDIS | PDIS}, /* nor.GPMC_A[16] */ + {GPMC_A17 , M0 | IDIS | PDIS}, /* nor.GPMC_A[17] */ + {GPMC_A18 , M0 | IDIS | PDIS}, /* nor.GPMC_A[18] */ + {GPMC_A19 , M0 | IDIS | PDIS}, /* nor.GPMC_A[19] */ + {GPMC_A20 , M0 | IDIS | PDIS}, /* nor.GPMC_A[20] */ + {GPMC_A21 , M0 | IDIS | PDIS}, /* nor.GPMC_A[21] */ + {GPMC_A22 , M0 | IDIS | PDIS}, /* nor.GPMC_A[22] */ + {GPMC_A23 , M0 | IDIS | PDIS}, /* nor.GPMC_A[23] */ + {GPMC_A24 , M0 | IDIS | PDIS}, /* nor.GPMC_A[24] */ + {GPMC_A25 , M0 | IDIS | PDIS}, /* nor.GPMC_A[25] */ + {GPMC_A26 , M0 | IDIS | PDIS}, /* nor.GPMC_A[26] */ +#else + /* eMMC pinmux */ {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ @@ -31,6 +62,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ +#endif #if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ @@ -68,7 +100,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {VIN2A_D21, (IEN | M3)}, {VIN2A_D22, (IEN | M3)}, {VIN2A_D23, (IEN | M3)}, -#ifdef CONFIG_NAND +#if defined(CONFIG_NAND) || defined(CONFIG_NOR) /* NAND / NOR pin-mux */ {GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */ {GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */ @@ -105,7 +137,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */ {GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */ {GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/ -#endif /* CONFIG_NAND */ +#endif /* CONFIG_NAND || CONFIG_NOR */ {USB2_DRVVBUS, (M0 | IEN | FSC) }, }; #endif /* _MUX_DATA_DRA7XX_H_ */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 10c88dcf96..d7d6d304c6 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -193,4 +193,42 @@ #endif #endif /* !CONFIG_NAND */ +/* Parallel NOR Support */ +#if defined(CONFIG_NOR) +/* NOR: device related configs */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ +/* #define CONFIG_INIT_IGNORE_ERROR */ +#undef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +/* Reduce SPL size by removing unlikey targets */ +#ifdef CONFIG_NOR_BOOT +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */ +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ + "128k(NOR.SPL)," \ + "128k(NOR.SPL.backup1)," \ + "128k(NOR.SPL.backup2)," \ + "128k(NOR.SPL.backup3)," \ + "256k(NOR.u-boot-spl-os)," \ + "1m(NOR.u-boot)," \ + "128k(NOR.u-boot-env)," \ + "128k(NOR.u-boot-env.backup1)," \ + "8m(NOR.kernel)," \ + "-(NOR.rootfs)" +#define CONFIG_ENV_OFFSET 0x001c0000 +#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 +#endif +#endif /* NOR support */ + #endif /* __CONFIG_DRA7XX_EVM_H */ |
