diff options
| -rw-r--r-- | board/timll/devkit3250/devkit3250.c | 31 | ||||
| -rw-r--r-- | configs/devkit3250_defconfig | 3 | ||||
| -rw-r--r-- | include/configs/devkit3250.h | 92 |
3 files changed, 120 insertions, 6 deletions
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 6acc416899..4b3c94eaf7 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -1,23 +1,52 @@ /* * Embest/Timll DevKit3250 board support * - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/clk.h> #include <asm/arch/cpu.h> #include <asm/arch/emc.h> +#include <asm/arch/wdt.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; + +void reset_periph(void) +{ + /* This function resets peripherals by triggering RESOUT_N */ + setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); + writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); + udelay(300); + + writel(0, &wdt->mctrl); + clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); + + /* Such a long delay is needed to initialize SMSC phy */ + udelay(10000); +} int board_early_init_f(void) { lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + lpc32xx_i2c_init(1); + lpc32xx_i2c_init(2); + lpc32xx_ssp_init(); + lpc32xx_mac_init(); + + /* + * nWP may be controlled by GPO19, but unpopulated by default R23 + * makes no sense to configure this GPIO level, nWP is always high + */ + lpc32xx_slc_nand_init(); return 0; } diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index f0c4ee12d6..56d719f61e 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_DEVKIT3250=y +# CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_DM=y +CONFIG_DM_GPIO=y diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 4f35234ced..b8218b51f0 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -1,7 +1,7 @@ /* * Embest/Timll DevKit3250 board configuration file * - * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -43,10 +43,44 @@ /* * Serial Driver */ -#define CONFIG_SYS_LPC32XX_UART 2 /* UART2 */ +#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ #define CONFIG_BAUDRATE 115200 /* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_LPC32XX +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + +/* + * GPIO + */ +#define CONFIG_LPC32XX_GPIO +#define CONFIG_CMD_GPIO + +/* + * SSP/SPI + */ +#define CONFIG_LPC32XX_SSP +#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 +#define CONFIG_CMD_SPI + +/* + * Ethernet + */ +#define CONFIG_RMII +#define CONFIG_PHY_SMSC +#define CONFIG_LPC32XX_ETH +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0x1F +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +/* * NOR Flash */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -56,6 +90,29 @@ #define CONFIG_SYS_FLASH_CFI /* + * NAND controller + */ +#define CONFIG_NAND_LPC32XX_SLC +#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + +/* + * NAND chip timings + */ +#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 +#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 +#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 +#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 +#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 +#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 +#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 +#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 + +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_CMD_NAND + +/* * U-Boot General Configurations */ #define CONFIG_SYS_LONGHELP @@ -71,8 +128,33 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION -#define CONFIG_ENV_IS_NOWHERE +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_OFFSET 0x000A0000 + +#define CONFIG_BOOTCOMMAND \ + "dhcp; " \ + "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ + "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ + "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ + "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ + "bootm ${loadaddr} - ${dtbaddr}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "ethaddr=00:01:90:00:C0:81\0" \ + "dtbaddr=0x81000000\0" \ + "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ + "tftpdir=vladimir/oe/devkit3250\0" \ + "userargs=oops=panic\0" /* * U-Boot Commands @@ -85,10 +167,10 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_ZERO_BOOTDELAY_CHECK -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 1 #define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTARGS "console=ttyS2,115200n8" +#define CONFIG_BOOTARGS "console=ttyS0,115200n8" #define CONFIG_LOADADDR 0x80008000 /* |
