diff options
198 files changed, 3865 insertions, 2352 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 4e2f8a9abb..c8386ab619 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -192,7 +192,8 @@ CFI FLASH M: Stefan Roese <sr@denx.de> S: Maintained T: git git://git.denx.de/u-boot-cfi-flash.git -F: drivers/mtd/* +F: drivers/mtd/cfi_flash.c +F: drivers/mtd/jedec_flash.c COLDFIRE M: Jason Jin <jason.jin@freescale.com> @@ -1,14 +1,7 @@ -# -# (C) Copyright 2000-2013 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -VERSION = 2014 -PATCHLEVEL = 10 +VERSION = 2015 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = # *DOCUMENTATION* @@ -17,11 +10,9 @@ NAME = # Comments in this file are targeted only to the developer, do not # expect to learn how to build the kernel reading this file. -# Do not: -# o use make's built-in rules and variables -# (this increases performance and avoids hard-to-debug behaviour); -# o print "Entering directory ..."; -MAKEFLAGS += -rR --no-print-directory +# Do not use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour); +MAKEFLAGS += -rR # Avoid funny character set dependencies unexport LC_ALL @@ -29,6 +20,9 @@ LC_COLLATE=C LC_NUMERIC=C export LC_COLLATE LC_NUMERIC +# Avoid interference with shell env settings +unexport GREP_OPTIONS + # We are using a recursive build, so we need to do a little thinking # to get the ordering right. # @@ -45,6 +39,29 @@ export LC_COLLATE LC_NUMERIC # descending is started. They are now explicitly listed as the # prepare rule. +# Beautify output +# --------------------------------------------------------------------------- +# +# Normally, we echo the whole command before executing it. By making +# that echo $($(quiet)$(cmd)), we now have the possibility to set +# $(quiet) to choose other forms of output instead, e.g. +# +# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@ +# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< +# +# If $(quiet) is empty, the whole command will be printed. +# If it is set to "quiet_", only the short version will be printed. +# If it is set to "silent_", nothing will be printed at all, since +# the variable $(silent_cmd_cc_o_c) doesn't exist. +# +# A simple variant is to prefix commands with $(Q) - that's useful +# for commands that shall be hidden in non-verbose mode. +# +# $(Q)ln $@ :< +# +# If KBUILD_VERBOSE equals 0 then the above command will be hidden. +# If KBUILD_VERBOSE equals 1 then the above command is displayed. +# # To put more focus on warnings, be less verbose as default # Use 'make V=1' to see the full commands @@ -55,33 +72,28 @@ ifndef KBUILD_VERBOSE KBUILD_VERBOSE = 0 endif -# Call a source code checker (by default, "sparse") as part of the -# C compilation. -# -# Use 'make C=1' to enable checking of only re-compiled files. -# Use 'make C=2' to enable checking of *all* source files, regardless -# of whether they are re-compiled or not. -# -# See the file "Documentation/sparse.txt" for more details, including -# where to get the "sparse" utility. +ifeq ($(KBUILD_VERBOSE),1) + quiet = + Q = +else + quiet=quiet_ + Q = @ +endif -ifeq ("$(origin C)", "command line") - KBUILD_CHECKSRC = $(C) +# If the user is running make -s (silent mode), suppress echoing of +# commands + +ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4 +ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),) + quiet=silent_ endif -ifndef KBUILD_CHECKSRC - KBUILD_CHECKSRC = 0 +else # make-3.8x +ifneq ($(filter s% -s%,$(MAKEFLAGS)),) + quiet=silent_ endif - -# Use make M=dir to specify directory of external module to build -# Old syntax make ... SUBDIRS=$PWD is still supported -# Setting the environment variable KBUILD_EXTMOD take precedence -ifdef SUBDIRS - KBUILD_EXTMOD ?= $(SUBDIRS) endif -ifeq ("$(origin M)", "command line") - KBUILD_EXTMOD := $(M) -endif +export quiet Q KBUILD_VERBOSE # kbuild supports saving output files in a separate directory. # To locate output files in a separate directory two syntaxes are supported. @@ -98,7 +110,6 @@ endif # The O= assignment takes precedence over the KBUILD_OUTPUT environment # variable. - # KBUILD_SRC is set on invocation of make in OBJ directory # KBUILD_SRC is not intended to be used by the regular user (for now) ifeq ($(KBUILD_SRC),) @@ -131,10 +142,8 @@ $(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make @: sub-make: FORCE - $(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \ - KBUILD_SRC=$(CURDIR) \ - KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \ - $(filter-out _all sub-make,$(MAKECMDGOALS)) + $(Q)$(MAKE) -C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR) \ + -f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS)) # Leave processing to above invocation of make skip-makefile := 1 @@ -144,6 +153,39 @@ endif # ifeq ($(KBUILD_SRC),) # We process the rest of the Makefile if this is the final invocation of make ifeq ($(skip-makefile),) +# Do not print "Entering directory ...", +# but we want to display it when entering to the output directory +# so that IDEs/editors are able to understand relative filenames. +MAKEFLAGS += --no-print-directory + +# Call a source code checker (by default, "sparse") as part of the +# C compilation. +# +# Use 'make C=1' to enable checking of only re-compiled files. +# Use 'make C=2' to enable checking of *all* source files, regardless +# of whether they are re-compiled or not. +# +# See the file "Documentation/sparse.txt" for more details, including +# where to get the "sparse" utility. + +ifeq ("$(origin C)", "command line") + KBUILD_CHECKSRC = $(C) +endif +ifndef KBUILD_CHECKSRC + KBUILD_CHECKSRC = 0 +endif + +# Use make M=dir to specify directory of external module to build +# Old syntax make ... SUBDIRS=$PWD is still supported +# Setting the environment variable KBUILD_EXTMOD take precedence +ifdef SUBDIRS + KBUILD_EXTMOD ?= $(SUBDIRS) +endif + +ifeq ("$(origin M)", "command line") + KBUILD_EXTMOD := $(M) +endif + # If building an external module we do not care about the all: rule # but instead _all depend on modules PHONY += all @@ -153,8 +195,18 @@ else _all: modules endif -srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR)) -objtree := $(CURDIR) +ifeq ($(KBUILD_SRC),) + # building in the source tree + srctree := . +else + ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR))) + # building in a subdirectory of the source tree + srctree := .. + else + srctree := $(KBUILD_SRC) + endif +endif +objtree := . src := $(srctree) obj := $(objtree) @@ -262,52 +314,6 @@ endif export KBUILD_MODULES KBUILD_BUILTIN export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD -# Beautify output -# --------------------------------------------------------------------------- -# -# Normally, we echo the whole command before executing it. By making -# that echo $($(quiet)$(cmd)), we now have the possibility to set -# $(quiet) to choose other forms of output instead, e.g. -# -# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@ -# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< -# -# If $(quiet) is empty, the whole command will be printed. -# If it is set to "quiet_", only the short version will be printed. -# If it is set to "silent_", nothing will be printed at all, since -# the variable $(silent_cmd_cc_o_c) doesn't exist. -# -# A simple variant is to prefix commands with $(Q) - that's useful -# for commands that shall be hidden in non-verbose mode. -# -# $(Q)ln $@ :< -# -# If KBUILD_VERBOSE equals 0 then the above command will be hidden. -# If KBUILD_VERBOSE equals 1 then the above command is displayed. - -ifeq ($(KBUILD_VERBOSE),1) - quiet = - Q = -else - quiet=quiet_ - Q = @ -endif - -# If the user is running make -s (silent mode), suppress echoing of -# commands - -ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4 -ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),) - quiet=silent_ -endif -else # make-3.8x -ifneq ($(filter s% -s%,$(MAKEFLAGS)),) - quiet=silent_ -endif -endif - -export quiet Q KBUILD_VERBOSE - # Look for make include files relative to root of kernel src MAKEFLAGS += --include-dir=$(srctree) @@ -780,6 +786,13 @@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@ all: $(ALL-y) +ifneq ($(CONFIG_SYS_GENERIC_BOARD),y) + @echo "===================== WARNING ======================" + @echo "Please convert this board to generic board." + @echo "Otherwise it will be removed by the end of 2014." + @echo "See doc/README.generic-board for further information" + @echo "====================================================" +endif PHONY += dtbs dtbs dts/dt.dtb: checkdtc u-boot @@ -827,7 +840,7 @@ u-boot.bin: u-boot FORCE u-boot.ldr: u-boot $(CREATE_LDR_ENV) - $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) + $(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex @@ -1220,13 +1233,12 @@ include/license.h: tools/bin2header COPYING # make distclean Remove editor backup files, patch leftover files and the like # Directories & files removed with 'make clean' -CLEAN_DIRS += $(MODVERDIR) -CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h - -# Directories & files removed with 'make clobber' -CLOBBER_DIRS += $(foreach d, spl tpl, $(patsubst %,$d/%, \ +CLEAN_DIRS += $(MODVERDIR) \ + $(foreach d, spl tpl, $(patsubst %,$d/%, \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) -CLOBBER_FILES += u-boot* MLO* SPL System.map + +CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ + u-boot* MLO* SPL System.map # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl \ @@ -1259,17 +1271,6 @@ clean: $(clean-dirs) -o -name modules.builtin -o -name '.tmp_*.o.*' \ -o -name '*.gcno' \) -type f -print | xargs rm -f -# clobber -# -clobber: rm-dirs := $(CLOBBER_DIRS) -clobber: rm-files := $(CLOBBER_FILES) - -PHONY += clobber - -clobber: clean - $(call cmd,rmdirs) - $(call cmd,rmfiles) - # mrproper - Delete all generated files, including .config # mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS)) @@ -1280,7 +1281,7 @@ PHONY += $(mrproper-dirs) mrproper archmrproper $(mrproper-dirs): $(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@) -mrproper: clobber $(mrproper-dirs) +mrproper: clean $(mrproper-dirs) $(call cmd,rmdirs) $(call cmd,rmfiles) @rm -f arch/*/include/asm/arch @@ -1304,9 +1305,7 @@ backup: help: @echo 'Cleaning targets:' - @echo ' clean - Remove most generated files but keep the config and' - @echo ' necessities for testing u-boot' - @echo ' clobber - Remove most generated files but keep the config' + @echo ' clean - Remove most generated files but keep the config' @echo ' mrproper - Remove all generated files + config + various backup files' @echo ' distclean - mrproper + remove editor backup and patch files' @echo '' @@ -1315,7 +1314,7 @@ help: @echo '' @echo 'Other generic targets:' @echo ' all - Build all necessary images depending on configuration' - @echo ' u-boot - Build the bare u-boot' + @echo '* u-boot - Build the bare u-boot' @echo ' dir/ - Build all files in dir and below' @echo ' dir/file.[oisS] - Build specified target only' @echo ' dir/file.lst - Build specified mixed source/assembly target only' @@ -1323,8 +1322,8 @@ help: @echo ' tags/ctags - Generate ctags file for editors' @echo ' etags - Generate etags file for editors' @echo ' cscope - Generate cscope index' - @echo ' ubootrelease - Output the release version string' - @echo ' ubootversion - Output the version stored in Makefile' + @echo ' ubootrelease - Output the release version string (use with make -s)' + @echo ' ubootversion - Output the version stored in Makefile (use with make -s)' @echo '' @echo 'Static analysers' @echo ' checkstack - Generate a list of stack hogs' @@ -1445,7 +1444,7 @@ endif # Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir # Usage: # $(Q)$(MAKE) $(clean)=dir -clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj +clean := -f $(srctree)/scripts/Makefile.clean obj endif # skip-makefile @@ -5012,14 +5012,14 @@ this behavior and build U-Boot to some external directory: make O=/tmp/build NAME_defconfig make O=/tmp/build all -2. Set environment variable BUILD_DIR to point to the desired location: +2. Set environment variable KBUILD_OUTPUT to point to the desired location: - export BUILD_DIR=/tmp/build + export KBUILD_OUTPUT=/tmp/build make distclean make NAME_defconfig make all -Note that the command line "O=" setting overrides the BUILD_DIR environment +Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment variable. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22eb2d5854..7e26744582 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -49,6 +49,7 @@ config SYS_CPU default "armv7" if CPU_V7 default "pxa" if CPU_PXA default "sa1100" if CPU_SA1100 + default "armv8" if ARM64 choice prompt "Target select" @@ -225,9 +226,11 @@ config KIRKWOOD config TARGET_DB_MV784MP_GP bool "Support db-mv784mp-gp" + select CPU_V7 config TARGET_MAXBCM bool "Support maxbcm" + select CPU_V7 config TARGET_DEVKIT3250 bool "Support devkit3250" @@ -629,6 +632,7 @@ config TARGET_HUMMINGBOARD config TARGET_KOSAGI_NOVENA bool "Support Kosagi Novena" + select CPU_V7 config TARGET_TQMA6 bool "TQ Systems TQMa6 board" @@ -775,8 +779,6 @@ config ARCH_UNIPHIER endchoice -source "arch/arm/cpu/armv8/Kconfig" - source "arch/arm/cpu/arm926ejs/davinci/Kconfig" source "arch/arm/cpu/armv7/exynos/Kconfig" @@ -950,4 +952,6 @@ source "board/woodburn/Kconfig" source "board/xaeniax/Kconfig" source "board/zipitz2/Kconfig" +source "arch/arm/Kconfig.debug" + endmenu diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug new file mode 100644 index 0000000000..624bcf4682 --- /dev/null +++ b/arch/arm/Kconfig.debug @@ -0,0 +1,64 @@ +menu "ARM debug" + +config DEBUG_LL + bool "Low-level debugging functions" + depends on !ARM64 + help + Say Y here to include definitions of printascii, printch, printhex + in U-Boot. This is helpful if you are debugging code that + executes before the console is initialized. + +choice + prompt "Low-level debugging port" + depends on DEBUG_LL + + config DEBUG_LL_UART_8250 + bool "Low-level debugging via 8250 UART" + help + Say Y here if you wish the debug print routes to direct + their output to an 8250 UART. You can use this option + to provide the parameters for the 8250 UART rather than + selecting one of the platform specific options above if + you know the parameters for the port. + + This option is preferred over the platform specific + options; the platform specific options are deprecated + and will be soon removed. + +endchoice + +config DEBUG_LL_INCLUDE + string + depends on DEBUG_LL + default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default "mach/debug-macro.S" + +# Compatibility options for 8250 +config DEBUG_UART_8250 + bool + +config DEBUG_UART_PHYS + hex "Physical base address of debug UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + +# This is not used in U-Boot +config DEBUG_UART_VIRT + hex + default DEBUG_UART_PHYS + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + +config DEBUG_UART_8250_SHIFT + int "Register offset shift for the 8250 debug UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + default 2 + +config DEBUG_UART_8250_WORD + bool "Use 32-bit accesses for 8250 UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + depends on DEBUG_UART_8250_SHIFT >= 2 + +config DEBUG_UART_8250_FLOW_CONTROL + bool "Enable flow control for 8250 UART" + depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 + +endmenu diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 365542fe0b..ef130aea42 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -83,7 +83,9 @@ void mx28_fixup_vt(uint32_t start_addr) int i; for (i = 0; i < 8; i++) { + /* cppcheck-suppress nullPointer */ vt[i] = ldr_pc; + /* cppcheck-suppress nullPointer */ vt[i + 8] = start_addr + (4 * i); } } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index d3e136991a..d29b9aaf3d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -118,6 +118,8 @@ static void mxs_spl_fixup_vectors(void) * fine. */ extern uint32_t _start; + + /* cppcheck-suppress nullPointer */ memcpy(0x0, &_start, 0x60); } diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 99d3fb8731..f2e72257d1 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -91,6 +91,8 @@ unsigned long long get_ticks(void) TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET; #elif defined(CONFIG_MX28) now = readl(&timrot_regs->hw_timrot_running_count0); +#else +#error "Don't know how to read timrot_regs" #endif if (lastdec >= now) { diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 2ce682f6b1..781d83fc72 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -18,6 +18,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <power/tps65910.h> +#include <linux/compiler.h> struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE; @@ -51,11 +52,11 @@ u32 get_cpu_type(void) /** * get_board_rev() - setup to pass kernel board revision information - * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) + * returns: 0 for the ATAG REVISION tag value. */ -u32 get_board_rev(void) +u32 __weak get_board_rev(void) { - return BOARD_REV_ID; + return 0; } /** diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index c215404469..a029379a4f 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -22,6 +22,9 @@ config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" select SUPPORT_SPL +config TARGET_CM_T3517 + bool "CompuLab CM-T3517 boards" + config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" select SUPPORT_SPL @@ -98,6 +101,7 @@ source "board/teejet/mt_ventoux/Kconfig" source "board/ti/sdp3430/Kconfig" source "board/ti/beagle/Kconfig" source "board/compulab/cm_t35/Kconfig" +source "board/compulab/cm_t3517/Kconfig" source "board/timll/devkit8000/Kconfig" source "board/ti/evm/Kconfig" source "board/isee/igep00x0/Kconfig" diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c index d869f47c88..fa3b93a257 100644 --- a/arch/arm/cpu/armv7/socfpga/clock_manager.c +++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c @@ -507,6 +507,19 @@ unsigned int cm_get_qspi_controller_clk_hz(void) return clock; } +unsigned int cm_get_spi_controller_clk_hz(void) +{ + uint32_t reg, clock = 0; + + clock = cm_get_per_vco_clk_hz(); + + /* get the clock prior L4 SP divider (periph_base_clk) */ + reg = readl(&clock_manager_base->per_pll.perbaseclk); + clock /= (reg + 1); + + return clock; +} + static void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000); @@ -518,6 +531,7 @@ static void cm_print_clock_quick_summary(void) printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000); printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000); printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000); + printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000); } int set_cpu_clk_info(void) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 8c3e5f7cd4..73cffd3a8d 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -202,6 +202,12 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_spim_enable(); +#endif + return 0; } diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 1d3a95d0c8..af9db850fe 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable) #endif } } + +/* SPI Master enable (its held in reset by the preloader) */ +void socfpga_spim_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); +} diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 3ea6d7651c..1446452c23 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,10 +20,6 @@ endchoice config USE_PRIVATE_LIBGCC default y if SPL_BUILD -config SYS_CPU - default "arm720t" if SPL_BUILD - default "armv7" if !SPL_BUILD - source "arch/arm/cpu/armv7/tegra20/Kconfig" source "arch/arm/cpu/armv7/tegra30/Kconfig" source "arch/arm/cpu/armv7/tegra114/Kconfig" diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index f013dc3cad..36b7f11fbe 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -32,4 +32,31 @@ config CMD_PINMON The boot mode pins are latched when the system reset is deasserted and determine which device the system should load a boot image from. +config SOC_INIT + bool + default SPL_BUILD + +config DRAM_INIT + bool + default SPL_BUILD + +choice + prompt "DDR3 Frequency select" + depends on DRAM_INIT + +config DDR_FREQ_1600 + bool "DDR3 1600" + depends on MACH_PH1_PRO4 || MACH_PH1_LD4 + +config DDR_FREQ_1333 + bool "DDR3 1333" + depends on MACH_PH1_LD4 || MACH_PH1_SLD8 + +endchoice + +config DDR_FREQ + int + default 1333 if DDR_FREQ_1333 + default 1600 if DDR_FREQ_1600 + endmenu diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile index dd57469d9c..0f64d2591c 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o obj-y += timer.o obj-y += reset.o obj-y += cache_uniphier.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o obj-y += dram_init.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c index 4302277dfc..89e44bb95b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/board_postclk_init.c +++ b/arch/arm/cpu/armv7/uniphier/board_postclk_init.c @@ -5,11 +5,13 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/compiler.h> #include <asm/arch/led.h> #include <asm/arch/board.h> -void bcu_init(void); +void __weak bcu_init(void) +{ +}; void sbc_init(void); void sg_init(void); void pll_init(void); @@ -18,12 +20,15 @@ void clkrst_init(void); int board_postclk_init(void) { +#ifdef CONFIG_SOC_INIT bcu_init(); sbc_init(); sg_init(); + uniphier_board_reset(); + pll_init(); uniphier_board_init(); @@ -33,7 +38,7 @@ int board_postclk_init(void) clkrst_init(); led_write(B, 2, , ); - +#endif pin_init(); led_write(B, 3, , ); diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c index 5465a0e6bf..7de657b7af 100644 --- a/arch/arm/cpu/armv7/uniphier/dram_init.c +++ b/arch/arm/cpu/armv7/uniphier/dram_init.c @@ -16,7 +16,7 @@ int dram_init(void) DECLARE_GLOBAL_DATA_PTR; gd->ram_size = CONFIG_SYS_SDRAM_SIZE; -#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_DRAM_INIT led_write(B, 4, , ); { diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile index 781b511a97..fba1cc7498 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c index 0047223181..62f5b0148d 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c index 1344ac1caa..ebcbaabf65 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c @@ -149,10 +149,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR Frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile index e11f4f6d8b..74129bc86a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \ - sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c deleted file mode 100644 index 7198829988..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/board_postclk_init.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/led.h> -#include <asm/arch/board.h> - -void sbc_init(void); -void sg_init(void); -void pll_init(void); -void pin_init(void); -void clkrst_init(void); - -int board_postclk_init(void) -{ - sbc_init(); - - sg_init(); - - pll_init(); - - uniphier_board_init(); - - led_write(B, 1, , ); - - clkrst_init(); - - led_write(B, 2, , ); - - pin_init(); - - led_write(B, 3, , ); - - return 0; -} diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c index 503c247d6b..4e3d47615b 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c @@ -41,5 +41,12 @@ void pin_init(void) sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */ #endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */ +#endif + writel(1, SG_LOADPINCTRL); } diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c index 6da921e920..1843d0469f 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c @@ -13,3 +13,13 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c index dd462875bb..328b2f4d9a 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c @@ -122,10 +122,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1600 -#error Unsupported DDR frequency. -#endif - #if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile index 781b511a97..fba1cc7498 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-y += platdevice.o obj-y += boot-mode.o -obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \ - sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o -obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \ - umc_init.o +obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \ + clkrst_init.o +obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o +obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c deleted file mode 100644 index 287b33c21d..0000000000 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/board_postclk_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/board_postclk_init.c" diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c index 59d054a310..72ec599f69 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c @@ -13,3 +13,16 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK) SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK) SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK) SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK) + +/* USB : TODO for Masahiro Yamada: move base address to Device Tree */ +struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = { + { + .base = 0x5a800100, + }, + { + .base = 0x5a810100, + }, + { + .base = 0x5a820100, + }, +}; diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c index ff2dcb1640..a44f999fbf 100644 --- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c +++ b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c @@ -129,10 +129,6 @@ int umc_init(void) CONFIG_SDRAM1_SIZE / 0x08000000); } -#if CONFIG_DDR_FREQ != 1333 -#error Unsupported DDR frequency. -#endif - #if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c index b0dc9673b4..50d1fed647 100644 --- a/arch/arm/cpu/armv7/uniphier/reset.c +++ b/arch/arm/cpu/armv7/uniphier/reset.c @@ -8,14 +8,11 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/sc-regs.h> -#include <asm/arch/board.h> void reset_cpu(unsigned long ignored) { u32 tmp; - uniphier_board_reset(); - writel(5, SC_IRQTIMSET); /* default value */ tmp = readl(SC_SLFRSTSEL); diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index 1ea086d520..d74f8dbbc4 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -40,6 +40,7 @@ void zynq_ddrc_init(void) * first stage bootloader. To get ECC to work all memory has * been initialized by writing any value. */ + /* cppcheck-suppress nullPointer */ memset((void *)0, 0, 1 * 1024 * 1024); } else { puts("ECC disabled "); diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig deleted file mode 100644 index 3d1655bd5c..0000000000 --- a/arch/arm/cpu/armv8/Kconfig +++ /dev/null @@ -1,6 +0,0 @@ -if ARM64 - -config SYS_CPU - default "armv8" - -endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8977d4b5ae..ba6dec930b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -41,6 +41,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb +dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi new file mode 100644 index 0000000000..4472fd9268 --- /dev/null +++ b/arch/arm/dts/socfpga.dtsi @@ -0,0 +1,755 @@ +/* + * Copyright (C) 2012 Altera <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/reset/altr,rst-mgr.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@fffed000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xfffed000 0x1000>, + <0xfffec100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffe01000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffe01000 0x1000>; + interrupts = <0 104 4>, + <0 105 4>, + <0 106 4>, + <0 107 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; + }; + }; + + can0: can@ffc00000 { + compatible = "bosch,d_can"; + reg = <0xffc00000 0x1000>; + interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>; + clocks = <&can0_clk>; + status = "disabled"; + }; + + can1: can@ffc01000 { + compatible = "bosch,d_can"; + reg = <0xffc01000 0x1000>; + interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>; + clocks = <&can1_clk>; + status = "disabled"; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_periph_ref_clk: f2s_periph_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + reg = <0x40>; + + mpuclk: mpuclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe0 0 9>; + reg = <0x48>; + }; + + mainclk: mainclk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe4 0 9>; + reg = <0x4C>; + }; + + dbg_base_clk: dbg_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + div-reg = <0xe8 0 9>; + reg = <0x50>; + }; + + main_qspi_clk: main_qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x54>; + }; + + main_nand_sdmmc_clk: main_nand_sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x58>; + }; + + cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&main_pll>; + reg = <0x5C>; + }; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; + reg = <0x80>; + + emac0_clk: emac0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x88>; + }; + + emac1_clk: emac1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x8C>; + }; + + per_qspi_clk: per_qsi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x90>; + }; + + per_nand_mmc_clk: per_nand_mmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x94>; + }; + + per_base_clk: per_base_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x98>; + }; + + h2f_usr1_clk: h2f_usr1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&periph_pll>; + reg = <0x9C>; + }; + }; + + sdram_pll: sdram_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; + reg = <0xC0>; + + ddr_dqs_clk: ddr_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xC8>; + }; + + ddr_2x_dqs_clk: ddr_2x_dqs_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xCC>; + }; + + ddr_dq_clk: ddr_dq_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD0>; + }; + + h2f_usr2_clk: h2f_usr2_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&sdram_pll>; + reg = <0xD4>; + }; + }; + + mpu_periph_clk: mpu_periph_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <4>; + }; + + mpu_l2_ram_clk: mpu_l2_ram_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mpuclk>; + fixed-divider = <2>; + }; + + l4_main_clk: l4_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + clk-gate = <0x60 0>; + }; + + l3_main_clk: l3_main_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-perip-clk"; + clocks = <&mainclk>; + fixed-divider = <1>; + }; + + l3_mp_clk: l3_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 0 2>; + clk-gate = <0x60 1>; + }; + + l3_sp_clk: l3_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>; + div-reg = <0x64 2 2>; + }; + + l4_mp_clk: l4_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 4 3>; + clk-gate = <0x60 2>; + }; + + l4_sp_clk: l4_sp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&mainclk>, <&per_base_clk>; + div-reg = <0x64 7 3>; + clk-gate = <0x60 3>; + }; + + dbg_at_clk: dbg_at_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 0 2>; + clk-gate = <0x60 4>; + }; + + dbg_clk: dbg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x68 2 2>; + clk-gate = <0x60 5>; + }; + + dbg_trace_clk: dbg_trace_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + div-reg = <0x6C 0 3>; + clk-gate = <0x60 6>; + }; + + dbg_timer_clk: dbg_timer_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&dbg_base_clk>; + clk-gate = <0x60 7>; + }; + + cfg_clk: cfg_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 8>; + }; + + h2f_user0_clk: h2f_user0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&cfg_h2f_usr0_clk>; + clk-gate = <0x60 9>; + }; + + emac_0_clk: emac_0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac0_clk>; + clk-gate = <0xa0 0>; + }; + + emac_1_clk: emac_1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&emac1_clk>; + clk-gate = <0xa0 1>; + }; + + usb_mp_clk: usb_mp_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 2>; + div-reg = <0xa4 0 3>; + }; + + spi_m_clk: spi_m_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 3>; + div-reg = <0xa4 3 3>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 4>; + div-reg = <0xa4 6 3>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 5>; + div-reg = <0xa4 9 3>; + }; + + gpio_db_clk: gpio_db_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&per_base_clk>; + clk-gate = <0xa0 6>; + div-reg = <0xa8 0 24>; + }; + + h2f_user1_clk: h2f_user1_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&h2f_usr1_clk>; + clk-gate = <0xa0 7>; + }; + + sdmmc_clk: sdmmc_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 8>; + clk-phase = <0 135>; + }; + + nand_x_clk: nand_x_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 9>; + }; + + nand_clk: nand_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; + clk-gate = <0xa0 10>; + fixed-divider = <4>; + }; + + qspi_clk: qspi_clk { + #clock-cells = <0>; + compatible = "altr,socfpga-gate-clk"; + clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; + clk-gate = <0xa0 11>; + }; + }; + }; + + gmac0: ethernet@ff700000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 0>; + reg = <0xff700000 0x2000>; + interrupts = <0 115 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac0_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + gmac1: ethernet@ff702000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x60 2>; + reg = <0xff702000 0x2000>; + interrupts = <0 120 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ + clocks = <&emac1_clk>; + clock-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + status = "disabled"; + }; + + i2c0: i2c@ffc04000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc04000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 158 0x4>; + status = "disabled"; + }; + + i2c1: i2c@ffc05000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc05000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 159 0x4>; + status = "disabled"; + }; + + i2c2: i2c@ffc06000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc06000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 160 0x4>; + status = "disabled"; + }; + + i2c3: i2c@ffc07000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc07000 0x1000>; + clocks = <&l4_sp_clk>; + interrupts = <0 161 0x4>; + status = "disabled"; + }; + + gpio0: gpio@ff708000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff708000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 164 4>; + }; + }; + + gpio1: gpio@ff709000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff709000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 165 4>; + }; + }; + + gpio2: gpio@ff70a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xff70a000 0x1000>; + clocks = <&per_base_clk>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 166 4>; + }; + }; + + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + + L2: l2-cache@fffef000 { + compatible = "arm,pl310-cache"; + reg = <0xfffef000 0x1000>; + interrupts = <0 38 0x04>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <1 1 1>; + arm,data-latency = <2 1 1>; + }; + + mmc: dwmmc0@ff704000 { + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff704000 0x1000>; + interrupts = <0 139 4>; + fifo-depth = <0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; + clock-names = "biu", "ciu"; + }; + + /* Local timer */ + timer@fffec600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xfffec600 0x100>; + interrupts = <1 13 0xf04>; + clocks = <&mpu_periph_clk>; + }; + + timer0: timer0@ffc08000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 167 4>; + reg = <0xffc08000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer1: timer1@ffc09000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 168 4>; + reg = <0xffc09000 0x1000>; + clocks = <&l4_sp_clk>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 169 4>; + reg = <0xffd00000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + timer3: timer3@ffd01000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffd01000 0x1000>; + clocks = <&osc1>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x1000>; + interrupts = <0 162 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + uart1: serial1@ffc03000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc03000 0x1000>; + interrupts = <0 163 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&l4_sp_clk>; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x1000>; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 125 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 128 4>; + clocks = <&usb_mp_clk>; + clock-names = "otg"; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd02000 { + compatible = "snps,dw-wdt"; + reg = <0xffd02000 0x1000>; + interrupts = <0 171 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd03000 { + compatible = "snps,dw-wdt"; + reg = <0xffd03000 0x1000>; + interrupts = <0 172 4>; + clocks = <&osc1>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd08000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd08000 0x4000>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi new file mode 100644 index 0000000000..28c05e7a31 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; +#include "socfpga.dtsi" + +/ { + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + mmc0: dwmmc0@ff704000 { + num-slots = <1>; + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + }; + + ethernet@ff702000 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + status = "okay"; + }; + + sysmgr@ffd08000 { + cpu1-start-addr = <0xffd080c4>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts new file mode 100644 index 0000000000..a1814b4574 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "EBV SOCrates"; + compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rtc: rtc@68 { + compatible = "stm,m41t82"; + reg = <0x68>; + }; +}; + +&mmc { + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 33a82fca98..7eacf27a93 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -14,8 +14,6 @@ #include <asm/ti-common/sys_proto.h> #include <asm/arch/cpu.h> -#define BOARD_REV_ID 0x0 - u32 get_cpu_rev(void); u32 get_sysboot_value(void); diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index 9512756619..df499957e5 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -57,8 +57,6 @@ #define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 -#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 -#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 /* NETCP */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 5a9ea4fbca..195c0d3003 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -98,8 +98,6 @@ #define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 #define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 #define KS2_NETCP_PDMA_RX_FLOW_NUM 32 -#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 -#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 #define KS2_NETCP_PDMA_TX_SND_QUEUE 648 /* NETCP */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h index 05532ada70..4f1197ea92 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -84,6 +84,10 @@ /* OSR memory size */ #define KS2_OSR_SIZE 0x100000 +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02320000 +#define KS2_LANES_PER_SGMII_SERDES 2 + /* Number of DSP cores */ #define KS2_NUM_DSPS 4 @@ -98,4 +102,7 @@ #define KS2_NETCP_PDMA_RX_FLOW_NUM 96 #define KS2_NETCP_PDMA_TX_SND_QUEUE 896 +/* NETCP */ +#define KS2_NETCP_BASE 0x26000000 + #endif /* __ASM_ARCH_HARDWARE_K2L_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index c6a54d8b91..be22bdb1ca 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -122,6 +122,10 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_EDMA_QEESR 0x108c #define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x)) +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 + /* Chip Interrupt Controller */ #define KS2_CIC2_BASE 0x02608000 diff --git a/arch/arm/include/asm/arch-socfpga/gpio.h b/arch/arm/include/asm/arch-socfpga/gpio.h new file mode 100644 index 0000000000..6c61f188bc --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_GPIO_H +#define _SOCFPGA_GPIO_H + +#endif /* _SOCFPGA_GPIO_H */ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 1857b80b3e..034135bff4 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable); void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); +void socfpga_spim_enable(void); struct socfpga_reset_manager { u32 status; @@ -35,5 +36,7 @@ struct socfpga_reset_manager { #define RSTMGR_PERMODRST_EMAC0_LSB 0 #define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_SPIM0_LSB 18 +#define RSTMGR_PERMODRST_SPIM1_LSB 19 #endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h new file mode 100644 index 0000000000..e9c5fb4af8 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/ehci-uniphier.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PLAT_UNIPHIER_EHCI_H +#define __PLAT_UNIPHIER_EHCI_H + +#include <linux/types.h> +#include <asm/io.h> +#include "mio-regs.h" + +struct uniphier_ehci_platform_data { + unsigned long base; +}; + +extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[]; + +static inline void uniphier_ehci_reset(int index, int on) +{ + u32 tmp; + + tmp = readl(MIO_USB_RSTCTRL(index)); + if (on) + tmp &= ~MIO_USB_RSTCTRL_XRST; + else + tmp |= MIO_USB_RSTCTRL_XRST; + writel(tmp, MIO_USB_RSTCTRL(index)); +} + +#endif /* __PLAT_UNIPHIER_EHCI_H */ diff --git a/arch/arm/include/asm/arch-uniphier/mio-regs.h b/arch/arm/include/asm/arch-uniphier/mio-regs.h new file mode 100644 index 0000000000..3306934ff7 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/mio-regs.h @@ -0,0 +1,20 @@ +/* + * UniPhier MIO (Media I/O) registers + * + * Copyright (C) 2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_MIO_REGS_H +#define ARCH_MIO_REGS_H + +#define MIO_BASE 0x59810000 + +#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020) +#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110) +#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114) + +#define MIO_USB_RSTCTRL_XRST (0x1 << 0) + +#endif /* ARCH_MIO_REGS_H */ diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h index cdf7d132d4..62a512659c 100644 --- a/arch/arm/include/asm/arch-uniphier/platdevice.h +++ b/arch/arm/include/asm/arch-uniphier/platdevice.h @@ -21,4 +21,6 @@ U_BOOT_DEVICE(serial##n) = { \ .platdata = &serial_device##n \ }; +#include <asm/arch/ehci-uniphier.h> + #endif /* ARCH_PLATDEVICE_H */ diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h index 79d7ec7148..fa5e6ae0f2 100644 --- a/arch/arm/include/asm/arch-uniphier/sg-regs.h +++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h @@ -88,7 +88,18 @@ #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16) #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16) -#ifndef __ASSEMBLY__ +#ifdef __ASSEMBLY__ + + .macro set_pinsel, n, value, ra, rd + ldr \ra, =SG_PINSEL_ADDR(\n) + ldr \rd, [\ra] + and \rd, \rd, #SG_PINSEL_MASK(\n) + orr \rd, \rd, #SG_PINSEL_MODE(\n, \value) + str \rd, [\ra] + .endm + +#else + #include <linux/types.h> #include <asm/io.h> diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 541b443254..1c8c4251ee 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -193,7 +193,7 @@ lr .req x30 0 : wfi ldr \wreg2, [\xreg1, GICC_AIAR] str \wreg2, [\xreg1, GICC_AEOIR] - and \wreg2, \wreg2, #3ff + and \wreg2, \wreg2, #0x3ff cbnz \wreg2, 0b .endm #endif diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S new file mode 100644 index 0000000000..d47a892652 --- /dev/null +++ b/arch/arm/include/debug/8250.S @@ -0,0 +1,52 @@ +/* + * arch/arm/include/debug/8250.S + * + * Copyright (C) 1994-2013 Russell King + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <linux/serial_reg.h> + + .macro addruart, rp, rv, tmp + ldr \rp, =CONFIG_DEBUG_UART_PHYS + ldr \rv, =CONFIG_DEBUG_UART_VIRT + .endm + +#ifdef CONFIG_DEBUG_UART_8250_WORD + .macro store, rd, rx:vararg + str \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldr \rd, \rx + .endm +#else + .macro store, rd, rx:vararg + strb \rd, \rx + .endm + + .macro load, rd, rx:vararg + ldrb \rd, \rx + .endm +#endif + +#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT + + .macro senduart,rd,rx + store \rd, [\rx, #UART_TX << UART_SHIFT] + .endm + + .macro busyuart,rd,rx +1002: load \rd, [\rx, #UART_LSR << UART_SHIFT] + and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE + teq \rd, #UART_LSR_TEMT | UART_LSR_THRE + bne 1002b + .endm + + .macro waituart,rd,rx +#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL +1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] + tst \rd, #UART_MSR_CTS + beq 1001b +#endif + .endm diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 1ef240047f..d74e4b8415 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -48,6 +48,8 @@ ifndef CONFIG_ARM64 obj-y += cache-cp15.o endif +obj-$(CONFIG_DEBUG_LL) += debug.o + # For EABI conformant tool chains, provide eabi_compat() ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) extra-y += eabi_compat.o diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index cdb1975105..4949d573af 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -15,7 +15,6 @@ #include <common.h> #include <command.h> #include <image.h> -#include <vxworks.h> #include <u-boot/zlib.h> #include <asm/byteorder.h> #include <libfdt.h> diff --git a/arch/arm/lib/debug.S b/arch/arm/lib/debug.S new file mode 100644 index 0000000000..760ba74a3c --- /dev/null +++ b/arch/arm/lib/debug.S @@ -0,0 +1,136 @@ +/* + * linux/arch/arm/kernel/debug.S + * + * Copyright (C) 1994-1999 Russell King + * + * SPDX-License-Identifier: GPL-2.0+ + * + * 32-bit debugging code + */ +#include <linux/linkage.h> +#include <asm/assembler.h> + + .text + +/* + * Some debugging routines (useful if you've got MM problems and + * printk isn't working). For DEBUGGING ONLY!!! Do not leave + * references to these in a production kernel! + */ + +#if !defined(CONFIG_DEBUG_SEMIHOSTING) +#include CONFIG_DEBUG_LL_INCLUDE +#endif + +#ifdef CONFIG_MMU + .macro addruart_current, rx, tmp1, tmp2 + addruart \tmp1, \tmp2, \rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + moveq \rx, \tmp1 + movne \rx, \tmp2 + .endm + +#else /* !CONFIG_MMU */ + .macro addruart_current, rx, tmp1, tmp2 + addruart \rx, \tmp1, \tmp2 + .endm + +#endif /* CONFIG_MMU */ + +/* + * Useful debugging routines + */ +ENTRY(printhex8) + mov r1, #8 + b printhex +ENDPROC(printhex8) + +ENTRY(printhex4) + mov r1, #4 + b printhex +ENDPROC(printhex4) + +ENTRY(printhex2) + mov r1, #2 +printhex: adr r2, hexbuf + add r3, r2, r1 + mov r1, #0 + strb r1, [r3] +1: and r1, r0, #15 + mov r0, r0, lsr #4 + cmp r1, #10 + addlt r1, r1, #'0' + addge r1, r1, #'a' - 10 + strb r1, [r3, #-1]! + teq r3, r2 + bne 1b + mov r0, r2 + b printascii +ENDPROC(printhex2) + +hexbuf: .space 16 + + .ltorg + +#ifndef CONFIG_DEBUG_SEMIHOSTING + +ENTRY(printascii) + addruart_current r3, r1, r2 + b 2f +1: waituart r2, r3 + senduart r1, r3 + busyuart r2, r3 + teq r1, #'\n' + moveq r1, #'\r' + beq 1b +2: teq r0, #0 + ldrneb r1, [r0], #1 + teqne r1, #0 + bne 1b + mov pc, lr +ENDPROC(printascii) + +ENTRY(printch) + addruart_current r3, r1, r2 + mov r1, r0 + mov r0, #0 + b 1b +ENDPROC(printch) + +#ifdef CONFIG_MMU +ENTRY(debug_ll_addr) + addruart r2, r3, ip + str r2, [r0] + str r3, [r1] + mov pc, lr +ENDPROC(debug_ll_addr) +#endif + +#else + +ENTRY(printascii) + mov r1, r0 + mov r0, #0x04 @ SYS_WRITE0 + ARM( svc #0x123456 ) + THUMB( svc #0xab ) + mov pc, lr +ENDPROC(printascii) + +ENTRY(printch) + adr r1, hexbuf + strb r0, [r1] + mov r0, #0x03 @ SYS_WRITEC + ARM( svc #0x123456 ) + THUMB( svc #0xab ) + mov pc, lr +ENDPROC(printch) + +ENTRY(debug_ll_addr) + mov r2, #0 + str r2, [r0] + str r2, [r1] + mov pc, lr +ENDPROC(debug_ll_addr) + +#endif diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 2e640afc45..fde54eaa3e 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -955,6 +955,7 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) uint32_t *hibernate_magic = 0; SSYNC(); + /* cppcheck-suppress nullPointer */ if (hibernate_magic[0] == 0xDEADBEEF) { serial_putc('c'); bfin_write_EVT15(hibernate_magic[1]); diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 836658a1c4..73cbfa2cc8 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -178,4 +178,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_ARCH_MISC_INIT +#define CONFIG_CPU CONFIG_BFIN_CPU + #endif diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index c1fb92af4b..bd64ea694f 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -38,9 +38,6 @@ config TARGET_IPEK01 config TARGET_JUPITER bool "Support jupiter" -config TARGET_MCC200 - bool "Support mcc200" - config TARGET_MOTIONPRO bool "Support motionpro" @@ -130,7 +127,6 @@ source "board/jupiter/Kconfig" source "board/manroland/hmi1001/Kconfig" source "board/manroland/mucmc52/Kconfig" source "board/manroland/uc101/Kconfig" -source "board/mcc200/Kconfig" source "board/motionpro/Kconfig" source "board/munices/Kconfig" source "board/phytec/pcm030/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 47b712d56b..072387a87e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -161,9 +161,12 @@ void cpu_init_early_f(void *fdt) setup_ifc_sram = (void *)SRAM_BASE_ADDR; dst = (u32 *) SRAM_BASE_ADDR; src = (u32 *) setup_ifc; - for (i = 0; i < 1024; i++) + for (i = 0; i < 1024; i++) { + /* cppcheck-suppress nullPointer */ *dst++ = *src++; + } + /* cppcheck-suppress nullPointer */ setup_ifc_sram(); /* CLEANUP */ diff --git a/arch/powerpc/include/asm/ppc4xx-i2c.h b/arch/powerpc/include/asm/ppc4xx-i2c.h index 09189cf19b..df97f175b3 100644 --- a/arch/powerpc/include/asm/ppc4xx-i2c.h +++ b/arch/powerpc/include/asm/ppc4xx-i2c.h @@ -72,6 +72,8 @@ struct ppc4xx_i2c { #define IIC_EXTSTS_XFRA 0x01 #define IIC_EXTSTS_ICT 0x02 #define IIC_EXTSTS_LA 0x04 +#define IIC_EXTSTS_BCS_MASK 0x70 +#define IIC_EXTSTS_BCS_FREE 0x40 /* XTCNTLSS Register Bit definition */ #define IIC_XTCNTLSS_SRST 0x01 diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index b3d70515dc..53a99ae71b 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -5,6 +5,7 @@ #include <common.h> #include <os.h> +#include <cli.h> #include <asm/getopt.h> #include <asm/io.h> #include <asm/sections.h> @@ -76,6 +77,8 @@ int sandbox_main_loop_init(void) /* Execute command if required */ if (state->cmd) { + cli_init(); + run_command_list(state->cmd, -1, 0); if (!state->interactive) os_exit(state->exit_type); diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c index 86d39983c8..3fea5f5b53 100644 --- a/arch/sh/lib/zimageboot.c +++ b/arch/sh/lib/zimageboot.c @@ -45,6 +45,7 @@ int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bootargs = getenv("bootargs"); /* Clear zero page */ + /* cppcheck-suppress nullPointer */ memset(param, 0, 0x1000); /* Set commandline */ diff --git a/board/Marvell/db-mv784mp-gp/Kconfig b/board/Marvell/db-mv784mp-gp/Kconfig index f94a444cf2..98aa10ade0 100644 --- a/board/Marvell/db-mv784mp-gp/Kconfig +++ b/board/Marvell/db-mv784mp-gp/Kconfig @@ -1,23 +1,15 @@ if TARGET_DB_MV784MP_GP -config SYS_CPU - string - default "armv7" - config SYS_BOARD - string default "db-mv784mp-gp" config SYS_VENDOR - string default "Marvell" config SYS_SOC - string default "armada-xp" config SYS_CONFIG_NAME - string default "db-mv784mp-gp" endif diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 0f81d899a6..ce625e54d0 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -8,6 +8,10 @@ #include <asm/arch/reset_manager.h> #include <asm/io.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include <usb_mass_storage.h> + #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,3 +43,20 @@ int board_init(void) return 0; } + +#ifdef CONFIG_USB_GADGET +struct s3c_plat_otg_data socfpga_otg_data = { + .regs_otg = CONFIG_USB_DWC2_REG_ADDR, + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + return s3c_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c index 8e90f9853a..05ffc4d1ac 100644 --- a/board/cogent/lcd.c +++ b/board/cogent/lcd.c @@ -234,7 +234,7 @@ lcd_heartbeat(void) void board_show_activity (ulong timestamp) { #ifdef CONFIG_STATUS_LED - if ((timestamp % (CONFIG_SYS_HZ / 2) == 0) + if ((timestamp % (CONFIG_SYS_HZ / 2)) == 0) lcd_heartbeat (); #endif } diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index d0b0930f42..886c723900 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -19,12 +19,11 @@ #include <i2c.h> #include <usb.h> #include <mmc.h> -#include <nand.h> #include <twl4030.h> -#include <bmp_layout.h> #include <linux/compiler.h> #include <asm/io.h> +#include <asm/errno.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/mmc_host_def.h> @@ -33,6 +32,7 @@ #include <asm/ehci-omap.h> #include <asm/gpio.h> +#include "../common/common.h" #include "../common/eeprom.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,58 +43,6 @@ const omap3_sysinfo sysinfo = { "NAND", }; -static u32 gpmc_net_config[GPMC_MAX_REG] = { - NET_GPMC_CONFIG1, - NET_GPMC_CONFIG2, - NET_GPMC_CONFIG3, - NET_GPMC_CONFIG4, - NET_GPMC_CONFIG5, - NET_GPMC_CONFIG6, - 0 -}; - -#ifdef CONFIG_LCD -#ifdef CONFIG_CMD_NAND -static int splash_load_from_nand(u32 bmp_load_addr) -{ - struct bmp_header *bmp_hdr; - int res, splash_screen_nand_offset = 0x100000; - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); - - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) - goto splash_address_too_high; - - res = nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_header_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - if (res < 0) - return res; - - bmp_hdr = (struct bmp_header *)bmp_load_addr; - bmp_size = le32_to_cpu(bmp_hdr->file_size); - - if (bmp_load_addr + bmp_size >= gd->start_addr_sp) - goto splash_address_too_high; - - return nand_read_skip_bad(&nand_info[nand_curr_device], - splash_screen_nand_offset, &bmp_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - -splash_address_too_high: - printf("Error: splashimage address too high. Data overwrites U-Boot " - "and/or placed beyond DRAM boundaries.\n"); - - return -1; -} -#else -static inline int splash_load_from_nand(void) -{ - return -1; -} -#endif /* CONFIG_CMD_NAND */ - #ifdef CONFIG_SPL_BUILD /* * Routine: get_board_mem_timings @@ -111,24 +59,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) } #endif +#define CM_T35_SPLASH_NAND_OFFSET 0x100000 + int splash_screen_prepare(void) { - char *env_splashimage_value; - u32 bmp_load_addr; - - env_splashimage_value = getenv("splashimage"); - if (env_splashimage_value == NULL) - return -1; - - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); - if (bmp_load_addr == 0) { - printf("Error: bad splashimage address specified\n"); - return -1; - } - - return splash_load_from_nand(bmp_load_addr); + return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET); } -#endif /* CONFIG_LCD */ /* * Routine: board_init @@ -154,34 +90,18 @@ int board_init(void) return 0; } -static u32 cm_t3x_rev; - /* * Routine: get_board_rev * Description: read system revision */ u32 get_board_rev(void) { - if (!cm_t3x_rev) - cm_t3x_rev = cl_eeprom_get_board_rev(); - - return cm_t3x_rev; + return cl_eeprom_get_board_rev(); }; -/* - * Routine: misc_init_r - * Description: display die ID - */ int misc_init_r(void) { - u32 board_rev = get_board_rev(); - u32 rev_major = board_rev / 100; - u32 rev_minor = board_rev - (rev_major * 100); - - if ((rev_minor / 10) * 10 == rev_minor) - rev_minor = rev_minor / 10; - - printf("PCB: %u.%u\n", rev_major, rev_minor); + cl_print_pcb_info(); dieid_num_r(); return 0; @@ -462,37 +382,12 @@ int board_mmc_init(bd_t *bis) } #endif -/* - * Routine: setup_net_chip_gmpc - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void setup_net_chip_gmpc(void) -{ - struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5], - CM_T3X_SMC911X_BASE, GPMC_SIZE_16M); - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4], - SB_T35_SMC911X_BASE, GPMC_SIZE_16M); - - /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); - - /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); - - /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, - &ctrl_base->gpmc_nadv_ale); -} - #ifdef CONFIG_SYS_I2C_OMAP34XX /* * Routine: reset_net_chip * Description: reset the Ethernet controller via TPS65930 GPIO */ -static void reset_net_chip(void) +static int cm_t3x_reset_net_chip(int gpio) { /* Set GPIO1 of TPS65930 as output */ twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03, @@ -507,9 +402,10 @@ static void reset_net_chip(void) twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C, 0x02); mdelay(1); + return 0; } #else -static inline void reset_net_chip(void) {} +static inline int cm_t3x_reset_net_chip(int gpio) { return 0; } #endif #ifdef CONFIG_SMC911X @@ -536,7 +432,6 @@ static int handle_mac_address(void) return eth_setenv_enetaddr("ethaddr", enetaddr); } - /* * Routine: board_eth_init * Description: initialize module and base-board Ethernet chips @@ -545,18 +440,16 @@ int board_eth_init(bd_t *bis) { int rc = 0, rc1 = 0; - setup_net_chip_gmpc(); - reset_net_chip(); - rc1 = handle_mac_address(); if (rc1) printf("No MAC address found! "); - rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE); + rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE, + cm_t3x_reset_net_chip, -EINVAL); if (rc1 > 0) rc++; - rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE); + rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL); if (rc1 > 0) rc++; @@ -564,16 +457,6 @@ int board_eth_init(bd_t *bis) } #endif -void __weak get_board_serial(struct tag_serialnr *serialnr) -{ - /* - * This corresponds to what happens when we can communicate with the - * eeprom but don't get a valid board serial value. - */ - serialnr->low = 0; - serialnr->high = 0; -}; - #ifdef CONFIG_USB_EHCI_OMAP struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, @@ -583,21 +466,12 @@ struct omap_usbhs_board_data usbhs_bdata = { #define SB_T35_USB_HUB_RESET_GPIO 167 int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) + struct ehci_hccr **hccr, struct ehci_hcor **hcor) { u8 val; int offset; - if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { - printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", - SB_T35_USB_HUB_RESET_GPIO); - return -1; - } - - gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); - udelay(10); - gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); - udelay(1000); + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val); @@ -614,6 +488,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, int ehci_hcd_stop(void) { + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); return omap_ehci_hcd_stop(); } #endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig new file mode 100644 index 0000000000..2f5473d76a --- /dev/null +++ b/board/compulab/cm_t3517/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM_T3517 + +config SYS_BOARD + default "cm_t3517" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "cm_t3517" + +endif diff --git a/board/compulab/cm_t3517/MAINTAINERS b/board/compulab/cm_t3517/MAINTAINERS new file mode 100644 index 0000000000..fbb6882138 --- /dev/null +++ b/board/compulab/cm_t3517/MAINTAINERS @@ -0,0 +1,6 @@ +CM_T3517 BOARD +M: Igor Grinberg <grinberg@compulab.co.il> +S: Maintained +F: board/compulab/cm_t3517/ +F: include/configs/cm_t3517.h +F: configs/cm_t3517_defconfig diff --git a/board/compulab/cm_t3517/Makefile b/board/compulab/cm_t3517/Makefile new file mode 100644 index 0000000000..4f0db01e37 --- /dev/null +++ b/board/compulab/cm_t3517/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> +# +# Authors: Igor Grinberg <grinberg@compulab.co.il> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cm_t3517.o mux.o diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c new file mode 100644 index 0000000000..cac1ad9ef1 --- /dev/null +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -0,0 +1,231 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <status_led.h> +#include <net.h> +#include <netdev.h> +#include <usb.h> +#include <mmc.h> +#include <linux/compiler.h> +#include <linux/usb/musb.h> + +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/am35x_def.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/musb.h> +#include <asm/omap_musb.h> +#include <asm/ehci-omap.h> + +#include "../common/common.h" +#include "../common/eeprom.h" + +DECLARE_GLOBAL_DATA_PTR; + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "CM-T3517 board", + "NAND 128/512M", +}; + +#ifdef CONFIG_USB_MUSB_AM35X +static struct musb_hdrc_config cm_t3517_musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +static struct omap_musb_board_data cm_t3517_musb_board_data = { + .set_phy_power = am35x_musb_phy_power, + .clear_irq = am35x_musb_clear_irq, + .reset = am35x_musb_reset, +}; + +static struct musb_hdrc_platform_data cm_t3517_musb_pdata = { +#if defined(CONFIG_MUSB_HOST) + .mode = MUSB_HOST, +#elif defined(CONFIG_MUSB_GADGET) + .mode = MUSB_PERIPHERAL, +#else +#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET" +#endif + .config = &cm_t3517_musb_config, + .power = 250, + .platform_ops = &am35x_ops, + .board_data = &cm_t3517_musb_board_data, +}; + +static void cm_t3517_musb_init(void) +{ + /* + * Set up USB clock/mode in the DEVCONF2 register. + * USB2.0 PHY reference clock is 13 MHz + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE, + CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | + CONF2_VBDTCTEN | CONF2_DATPOL); + + if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data, + (void *)AM35XX_IPSS_USBOTGSS_BASE)) + printf("Failed initializing AM35x MUSB!\n"); +} +#else +static inline void am3517_evm_musb_init(void) {} +#endif + +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + + cm_t3517_musb_init(); + + return 0; +} + +int misc_init_r(void) +{ + cl_print_pcb_info(); + dieid_num_r(); + + return 0; +} + +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) +#define SB_T35_CD_GPIO 144 +#define SB_T35_WP_GPIO 59 + +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO); +} +#endif + +#ifdef CONFIG_DRIVER_TI_EMAC +#define CONTROL_EFUSE_EMAC_LSB 0x48002380 +#define CONTROL_EFUSE_EMAC_MSB 0x48002384 + +static int am3517_get_efuse_enetaddr(u8 *enetaddr) +{ + u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB); + u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB); + + enetaddr[0] = (u8)((msb >> 16) & 0xff); + enetaddr[1] = (u8)((msb >> 8) & 0xff); + enetaddr[2] = (u8)(msb & 0xff); + enetaddr[3] = (u8)((lsb >> 16) & 0xff); + enetaddr[4] = (u8)((lsb >> 8) & 0xff); + enetaddr[5] = (u8)(lsb & 0xff); + + return is_valid_ether_addr(enetaddr); +} + +static inline int cm_t3517_init_emac(bd_t *bis) +{ + int ret = cpu_eth_init(bis); + + if (ret > 0) + return ret; + + printf("Failed initializing EMAC! "); + return 0; +} +#else /* !CONFIG_DRIVER_TI_EMAC */ +static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; } +static inline int cm_t3517_init_emac(bd_t *bis) { return 0; } +#endif /* CONFIG_DRIVER_TI_EMAC */ + +/* + * Routine: handle_mac_address + * Description: prepare MAC address for on-board Ethernet. + */ +static int cm_t3517_handle_mac_address(void) +{ + unsigned char enetaddr[6]; + int ret; + + ret = eth_getenv_enetaddr("ethaddr", enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr); + if (ret) { + ret = am3517_get_efuse_enetaddr(enetaddr); + if (ret) + return ret; + } + + if (!is_valid_ether_addr(enetaddr)) + return -1; + + return eth_setenv_enetaddr("ethaddr", enetaddr); +} + +#define SB_T35_ETH_RST_GPIO 164 + +/* + * Routine: board_eth_init + * Description: initialize module and base-board Ethernet chips + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0, rc1 = 0; + + rc1 = cm_t3517_handle_mac_address(); + if (rc1) + printf("No MAC address found! "); + + rc1 = cm_t3517_init_emac(bis); + if (rc1 > 0) + rc++; + + rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE, + NULL, SB_T35_ETH_RST_GPIO); + if (rc1 > 0) + rc++; + + return rc; +} + +#ifdef CONFIG_USB_EHCI_OMAP +static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +#define CM_T3517_USB_HUB_RESET_GPIO 152 +#define SB_T35_USB_HUB_RESET_GPIO 98 + +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst"); + cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst"); + + return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO); + cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO); + + return omap_ehci_hcd_stop(); +} +#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/cm_t3517/mux.c b/board/compulab/cm_t3517/mux.c new file mode 100644 index 0000000000..88ce2cc2e6 --- /dev/null +++ b/board/compulab/cm_t3517/mux.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include <asm/io.h> + +void set_muxconf_regs(void) +{ + /* SDRC */ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + + /* SB-T35 Ethernet */ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); + /* DVI enable */ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ + /* DataImage backlight */ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ + + /* SB-T35 SD/MMC WP GPIO59 */ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); + /* SB-T35 Audio Enable GPIO61 */ + MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); + /* SB-T35 Ethernet IRQ GPIO65 */ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ + + /* UART3 Console */ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); + /* RTC V3020 nCS GPIO163 */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ + /* SB-T35 Ethernet nRESET GPIO164 */ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ + + /* SB-T35 SD/MMC CD GPIO144 */ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ + /* WIFI nRESET GPIO145 */ + MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ + /* USB1 PHY Reset GPIO 146 */ + MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ + /* USB2 PHY Reset GPIO 147 */ + MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ + + /* MMC1 */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); + + /* DSS */ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); + + /* I2C */ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); + + /* SB-T35 USB HUB Reset GPIO98 */ + MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ + /* CM-T3517 USB HUB Reset GPIO152 */ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ + + /* RMII */ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); + MUX_VAL(CP(RMII_MDIO_CLK), (M0)); + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); + MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); + MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); + + /* Green LED GPIO186 */ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ + + /* SPI */ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ + /* LCD reset GPIO157 */ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ + + /* RTC V3020 CS Enable GPIO160 */ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ + /* SB-T35 LVDS Transmitter SHDN GPIO162 */ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ + + /* USB0 - mUSB */ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); + /* USB1 EHCI */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ + /* USB2 EHCI */ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + + /* SYS_BOOT */ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ +} diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index 944b7234d6..b1a067d881 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -100,16 +100,11 @@ uint mmc_get_env_part(struct mmc *mmc) #define SB_T54_CD_GPIO 228 #define SB_T54_WP_GPIO 229 -int board_mmc_getcd(struct mmc *mmc) -{ - return !gpio_get_value(SB_T54_CD_GPIO); -} - int board_mmc_init(bd_t *bis) { int ret0, ret1; - ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO); + ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO); if (ret0) printf("cm_t54: failed to initialize mmc0\n"); diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index 4044ac9d62..dbf0009652 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -6,5 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SYS_I2C) += eeprom.o -obj-$(CONFIG_LCD) += omap3_display.o +obj-y += common.o +obj-$(CONFIG_SYS_I2C) += eeprom.o +obj-$(CONFIG_LCD) += omap3_display.o +obj-$(CONFIG_SPLASH_SCREEN) += splash.o +obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c new file mode 100644 index 0000000000..b25d9a20b4 --- /dev/null +++ b/board/compulab/common/common.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/bootm.h> +#include <asm/gpio.h> + +#include "common.h" +#include "eeprom.h" + +void cl_print_pcb_info(void) +{ + u32 board_rev = get_board_rev(); + u32 rev_major = board_rev / 100; + u32 rev_minor = board_rev - (rev_major * 100); + + if ((rev_minor / 10) * 10 == rev_minor) + rev_minor = rev_minor / 10; + + printf("PCB: %u.%u\n", rev_major, rev_minor); +} + +#ifdef CONFIG_SERIAL_TAG +void __weak get_board_serial(struct tag_serialnr *serialnr) +{ + /* + * This corresponds to what happens when we can communicate with the + * eeprom but don't get a valid board serial value. + */ + serialnr->low = 0; + serialnr->high = 0; +}; +#endif + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label) +{ + if (gpio_request(gpio, label)) { + printf("Error: can't obtain GPIO%d for %s", gpio, label); + return -1; + } + + gpio_direction_output(gpio, 0); + udelay(10); + gpio_set_value(gpio, 1); + udelay(1000); + return 0; +} + +void cl_usb_hub_deinit(int gpio) +{ + gpio_free(gpio); +} +#endif diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h new file mode 100644 index 0000000000..68ffb111dc --- /dev/null +++ b/board/compulab/common/common.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CL_COMMON_ +#define _CL_COMMON_ + +#include <asm/errno.h> + +void cl_print_pcb_info(void); + +#ifdef CONFIG_CMD_USB +int cl_usb_hub_init(int gpio, const char *label); +void cl_usb_hub_deinit(int gpio); +#else /* !CONFIG_CMD_USB */ +static inline int cl_usb_hub_init(int gpio, const char *label) +{ + return -ENOSYS; +} +static inline void cl_usb_hub_deinit(int gpio) {} +#endif /* CONFIG_CMD_USB */ + +#ifdef CONFIG_SPLASH_SCREEN +int cl_splash_screen_prepare(int nand_offset); +#else /* !CONFIG_SPLASH_SCREEN */ +static inline int cl_splash_screen_prepare(int nand_offset) +{ + return -ENOSYS; +} +#endif /* CONFIG_SPLASH_SCREEN */ + +#ifdef CONFIG_SMC911X +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio); +#else /* !CONFIG_SMC911X */ +static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + return -ENOSYS; +} +#endif /* CONFIG_SMC911X */ + +#endif /* _CL_COMMON_ */ diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 2df3adabf8..a45e7be11f 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -109,23 +109,27 @@ int cl_eeprom_read_mac_addr(uchar *buf) return cl_eeprom_read(offset, buf, 6); } +static u32 board_rev; + /* * Routine: cl_eeprom_get_board_rev * Description: read system revision from eeprom */ u32 cl_eeprom_get_board_rev(void) { - u32 rev = 0; char str[5]; /* Legacy representation can contain at most 4 digits */ uint offset = BOARD_REV_OFFSET_LEGACY; + if (board_rev) + return board_rev; + if (cl_eeprom_setup_layout()) return 0; if (cl_eeprom_layout != LAYOUT_LEGACY) offset = BOARD_REV_OFFSET; - if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) + if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE)) return 0; /* @@ -133,9 +137,9 @@ u32 cl_eeprom_get_board_rev(void) * representation. i.e. for rev 1.00: 0x100 --> 0x64 */ if (cl_eeprom_layout == LAYOUT_LEGACY) { - sprintf(str, "%x", rev); - rev = simple_strtoul(str, NULL, 10); + sprintf(str, "%x", board_rev); + board_rev = simple_strtoul(str, NULL, 10); } - return rev; + return board_rev; }; diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c new file mode 100644 index 0000000000..4561661987 --- /dev/null +++ b/board/compulab/common/omap3_smc911x.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <netdev.h> + +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/cpu.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> + +#include "common.h" + +static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = { + NET_GPMC_CONFIG1, + NET_GPMC_CONFIG2, + NET_GPMC_CONFIG3, + NET_GPMC_CONFIG4, + NET_GPMC_CONFIG5, + NET_GPMC_CONFIG6, + 0 +}; + +static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + + enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config, + &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); + + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ + writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); + + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); + + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale); +} + +#ifdef CONFIG_OMAP_GPIO +static int cl_omap3_smc911x_reset_net_chip(int gpio) +{ + int err; + + if (!gpio_is_valid(gpio)) + return -EINVAL; + + err = gpio_request(gpio, "eth rst"); + if (err) + return err; + + /* Set gpio as output and send a pulse */ + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + mdelay(40); + gpio_set_value(gpio, 1); + mdelay(1); + + return 0; +} +#else /* !CONFIG_OMAP_GPIO */ +static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; } +#endif /* CONFIG_OMAP_GPIO */ + +int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, + int (*reset)(int), int rst_gpio) +{ + int ret; + + cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr); + + if (reset) + reset(rst_gpio); + else + cl_omap3_smc911x_reset_net_chip(rst_gpio); + + ret = smc911x_initialize(id, base_addr); + if (ret > 0) + return ret; + + printf("Failed initializing SMC911x! "); + return 0; +} diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c new file mode 100644 index 0000000000..49ed49b81e --- /dev/null +++ b/board/compulab/common/splash.c @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> + * + * Authors: Igor Grinberg <grinberg@compulab.co.il> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nand.h> +#include <bmp_layout.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NAND +static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) +{ + struct bmp_header *bmp_hdr; + int res; + size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); + + if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) + goto splash_address_too_high; + + res = nand_read_skip_bad(&nand_info[nand_curr_device], + nand_offset, &bmp_header_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + if (res < 0) + return res; + + bmp_hdr = (struct bmp_header *)bmp_load_addr; + bmp_size = le32_to_cpu(bmp_hdr->file_size); + + if (bmp_load_addr + bmp_size >= gd->start_addr_sp) + goto splash_address_too_high; + + return nand_read_skip_bad(&nand_info[nand_curr_device], + nand_offset, &bmp_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + +splash_address_too_high: + printf("Error: splashimage address too high. Data overwrites U-Boot " + "and/or placed beyond DRAM boundaries.\n"); + + return -1; +} +#else +static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) +{ + return -1; +} +#endif /* CONFIG_CMD_NAND */ + +int cl_splash_screen_prepare(int nand_offset) +{ + char *env_splashimage_value; + u32 bmp_load_addr; + + env_splashimage_value = getenv("splashimage"); + if (env_splashimage_value == NULL) + return -1; + + bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); + if (bmp_load_addr == 0) { + printf("Error: bad splashimage address specified\n"); + return -1; + } + + return splash_load_from_nand(bmp_load_addr, nand_offset); +} diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 85c3567b0b..b1680741e1 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -377,7 +377,7 @@ int do_auto_update(void) { block_dev_desc_t *stor_dev = NULL; long sz; - int i, res, cnt, old_ctrlc; + int i, res, old_ctrlc; char buffer[32]; char str[80]; int n; @@ -455,7 +455,6 @@ int do_auto_update(void) clear_ctrlc (); break; } - cnt++; } while (res < 0); } diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 55c20d02d3..29c688a787 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -23,7 +23,7 @@ */ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int *ptr = 0; + unsigned int *ptr; int count = 0; int count2 = 0; int i; @@ -35,12 +35,14 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * Mark sync address */ ptr = 0; + /* cppcheck-suppress nullPointer */ *ptr = 0xffffffff; puts("\nWaiting for image from pci host -"); /* * Wait for host to write the start address */ + /* cppcheck-suppress nullPointer */ while (*ptr == 0xffffffff) { count++; if (!(count % 100)) { diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index 2ddb3da38f..b9aff1a84d 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -360,6 +360,7 @@ static int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc, testboot = (testpin != 0) && (s); if (verbose) { printf("testpin = %d\n", testpin); + /* cppcheck-suppress nullPointer */ printf("test_bank = %s\n", s ? s : "not set"); printf("boot test app : %s\n", (testboot) ? "yes" : "no"); } diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig index 4ba63999ae..94f1754a47 100644 --- a/board/kosagi/novena/Kconfig +++ b/board/kosagi/novena/Kconfig @@ -1,8 +1,5 @@ if TARGET_KOSAGI_NOVENA -config SYS_CPU - default "armv7" - config SYS_BOARD default "novena" diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c index 1a2ac8d6c8..db42987010 100644 --- a/board/matrix_vision/mvblx/sys_eeprom.c +++ b/board/matrix_vision/mvblx/sys_eeprom.c @@ -348,7 +348,7 @@ int mac_read_from_eeprom(void) if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) && memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) { - char ethaddr[9]; + char ethaddr[18]; sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X", e.mac[0], diff --git a/board/maxbcm/Kconfig b/board/maxbcm/Kconfig index d34e2abf36..d833ca0e25 100644 --- a/board/maxbcm/Kconfig +++ b/board/maxbcm/Kconfig @@ -1,19 +1,12 @@ if TARGET_MAXBCM -config SYS_CPU - string - default "armv7" - config SYS_BOARD - string default "maxbcm" config SYS_SOC - string default "armada-xp" config SYS_CONFIG_NAME - string default "maxbcm" endif diff --git a/board/mcc200/Kconfig b/board/mcc200/Kconfig deleted file mode 100644 index 3b27eeb1de..0000000000 --- a/board/mcc200/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_MCC200 - -config SYS_BOARD - default "mcc200" - -config SYS_CONFIG_NAME - default "mcc200" - -endif diff --git a/board/mcc200/MAINTAINERS b/board/mcc200/MAINTAINERS deleted file mode 100644 index a59a498795..0000000000 --- a/board/mcc200/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -MCC200 BOARD -#M: - -S: Maintained -F: board/mcc200/ -F: include/configs/mcc200.h -F: configs/mcc200_defconfig -F: configs/mcc200_COM12_defconfig -F: configs/mcc200_COM12_highboot_defconfig -F: configs/mcc200_COM12_highboot_SDRAM_defconfig -F: configs/mcc200_COM12_SDRAM_defconfig -F: configs/mcc200_highboot_defconfig -F: configs/mcc200_highboot_SDRAM_defconfig -F: configs/mcc200_SDRAM_defconfig -F: configs/prs200_defconfig -F: configs/prs200_DDR_defconfig -F: configs/prs200_highboot_defconfig -F: configs/prs200_highboot_DDR_defconfig diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile deleted file mode 100644 index db3b39646a..0000000000 --- a/board/mcc200/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := mcc200.o lcd.o auto_update.o diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c deleted file mode 100644 index 43173ce060..0000000000 --- a/board/mcc200/auto_update.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <image.h> -#include <asm/byteorder.h> -#include <usb.h> -#include <part.h> - -#ifdef CONFIG_AUTO_UPDATE - -#ifndef CONFIG_USB_OHCI -#error "must define CONFIG_USB_OHCI" -#endif - -#ifndef CONFIG_USB_STORAGE -#error "must define CONFIG_USB_STORAGE" -#endif - -#ifndef CONFIG_SYS_HUSH_PARSER -#error "must define CONFIG_SYS_HUSH_PARSER" -#endif - -#if !defined(CONFIG_CMD_FAT) -#error "must define CONFIG_CMD_FAT" -#endif - -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - -/* possible names of files on the USB stick. */ -#define AU_FIRMWARE "u-boot.img" -#define AU_KERNEL "kernel.img" -#define AU_ROOTFS "rootfs.img" - -struct flash_layout { - long start; - long end; -}; - -/* layout of the FLASH. ST = start address, ND = end address. */ -#define AU_FL_FIRMWARE_ST 0xfC000000 -#define AU_FL_FIRMWARE_ND 0xfC03FFFF -#define AU_FL_KERNEL_ST 0xfC0C0000 -#define AU_FL_KERNEL_ND 0xfC1BFFFF -#define AU_FL_ROOTFS_ST 0xFC1C0000 -#define AU_FL_ROOTFS_ND 0xFCFBFFFF - -static int au_usb_stor_curr_dev; /* current device */ - -/* index of each file in the following arrays */ -#define IDX_FIRMWARE 0 -#define IDX_KERNEL 1 -#define IDX_ROOTFS 2 - -/* max. number of files which could interest us */ -#define AU_MAXFILES 3 - -/* pointers to file names */ -char *aufile[AU_MAXFILES] = { - AU_FIRMWARE, - AU_KERNEL, - AU_ROOTFS -}; - -/* sizes of flash areas for each file */ -long ausize[AU_MAXFILES] = { - (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST, - (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST, - (AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST, -}; - -/* array of flash areas start and end addresses */ -struct flash_layout aufl_layout[AU_MAXFILES] = { - { AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, }, - { AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, }, - { AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, }, -}; - -ulong totsize; - -/* where to load files into memory */ -#define LOAD_ADDR ((unsigned char *)0x00200000) - -/* the root file system is the largest image */ -#define MAX_LOADSZ ausize[IDX_ROOTFS] - -/*i2c address of the keypad status*/ -#define I2C_PSOC_KEYPAD_ADDR 0x53 - -/* keypad mask */ -#define KEYPAD_ROW 2 -#define KEYPAD_COL 2 -#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF) -#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8) - -/* externals */ -extern int fat_register_device(block_dev_desc_t *, int); -extern int file_fat_detectfs(void); -extern long file_fat_read(const char *, void *, unsigned long); -extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int); -extern int flash_sect_erase(ulong, ulong); -extern int flash_sect_protect (int, ulong, ulong); -extern int flash_write (char *, ulong, ulong); -extern int u_boot_hush_start(void); -#ifdef CONFIG_PROGRESSBAR -extern void show_progress(int, int); -extern void lcd_puts (char *); -extern void lcd_enable(void); -#endif - -int au_check_cksum_valid(int idx, long nbytes) -{ - image_header_t *hdr; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - if (nbytes != image_get_image_size (hdr)) { - printf ("Image %s bad total SIZE\n", aufile[idx]); - return -1; - } - /* check the data CRC */ - if (!image_check_dcrc (hdr)) { - printf ("Image %s bad data checksum\n", aufile[idx]); - return -1; - } - return 0; -} - -int au_check_header_valid(int idx, long nbytes) -{ - image_header_t *hdr; - unsigned long checksum, fsize; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); -#endif - if (nbytes < image_get_header_size ()) { - printf ("Image %s bad header SIZE\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { - printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the hdr CRC */ - if (!image_check_hcrc (hdr)) { - printf ("Image %s bad header checksum\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* check the type - could do this all in one gigantic if() */ - if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - if ((idx == IDX_ROOTFS) && - (!image_check_type (hdr, IH_TYPE_RAMDISK) && - !image_check_type (hdr, IH_TYPE_FILESYSTEM))) { - printf ("Image %s wrong type\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* recycle checksum */ - checksum = image_get_data_size (hdr); - - fsize = checksum + image_get_header_size (); - /* for kernel and ramdisk the image header must also fit into flash */ - if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK)) - checksum += image_get_header_size (); - - /* check the size does not exceed space in flash. HUSH scripts */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", aufile[idx]); - ausize[idx] = 0; - return -1; - } - /* Update with the real filesize */ - ausize[idx] = fsize; - - return checksum; /* return size to be written to flash */ -} - -int au_do_update(int idx, long sz) -{ - image_header_t *hdr; - char *addr; - long start, end; - int off, rc; - uint nbytes; - - hdr = (image_header_t *)LOAD_ADDR; -#if defined(CONFIG_FIT) - if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { - puts ("Non legacy image format not supported\n"); - return -1; - } -#endif - - /* execute a script */ - if (image_check_type (hdr, IH_TYPE_SCRIPT)) { - addr = (char *)((char *)hdr + image_get_header_size ()); - /* stick a NULL at the end of the script, otherwise */ - /* parse_string_outer() runs off the end. */ - addr[image_get_data_size (hdr)] = 0; - addr += 8; - run_command_list(addr, -1, 0); - return 0; - } - - start = aufl_layout[idx].start; - end = aufl_layout[idx].end; - - /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) { -#undef AU_UPDATE_TEST -#ifdef AU_UPDATE_TEST - /* erase it where Linux goes */ - start = aufl_layout[1].start; - end = aufl_layout[1].end; -#endif - flash_sect_protect(0, start, end); - } - - /* - * erase the address range. - */ - debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); - mdelay(100); -#ifdef CONFIG_PROGRESSBAR - show_progress(end - start, totsize); -#endif - - /* strip the header - except for the kernel and ramdisk */ - if (image_check_type (hdr, IH_TYPE_KERNEL) || - image_check_type (hdr, IH_TYPE_RAMDISK)) { - addr = (char *)hdr; - off = image_get_header_size (); - nbytes = image_get_image_size (hdr); - } else { - addr = (char *)((char *)hdr + image_get_header_size ()); -#ifdef AU_UPDATE_TEST - /* copy it to where Linux goes */ - if (idx == IDX_FIRMWARE) - start = aufl_layout[1].start; -#endif - off = 0; - nbytes = image_get_data_size (hdr); - } - - /* copy the data from RAM to FLASH */ - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write(addr, start, nbytes); - if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); - return -1; - } - -#ifdef CONFIG_PROGRESSBAR - show_progress(nbytes, totsize); -#endif - - /* check the data CRC of the copy */ - if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) != - image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]); - return -1; - } - - /* protect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (idx == IDX_FIRMWARE) - flash_sect_protect(1, start, end); - return 0; -} - -/* - * this is called from board_init() after the hardware has been set up - * and is usable. That seems like a good time to do this. - * Right now the return value is ignored. - */ -int do_auto_update(void) -{ - block_dev_desc_t *stor_dev; - long sz; - int i, res = 0, cnt, old_ctrlc; - char *env; - long start, end; - -#if 0 /* disable key-press detection to speed up boot-up time */ - uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0}; - - /* - * Read keypad status - */ - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2); - mdelay(500); - i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2); - - /* - * Check keypad - */ - if ( !(keypad_status1[1] & KEYPAD_MASK_LO) || - (keypad_status1[1] != keypad_status2[1])) { - return 0; - } - -#endif - au_usb_stor_curr_dev = -1; - /* start USB */ - if (usb_stop() < 0) { - debug ("usb_stop failed\n"); - return -1; - } - if (usb_init() < 0) { - debug ("usb_init failed\n"); - return -1; - } - /* - * check whether a storage device is attached (assume that it's - * a USB memory stick, since nothing else should be attached). - */ - au_usb_stor_curr_dev = usb_stor_scan(0); - if (au_usb_stor_curr_dev == -1) { - debug ("No device found. Not initialized?\n"); - res = -1; - goto xit; - } - /* check whether it has a partition table */ - stor_dev = get_dev("usb", 0); - if (stor_dev == NULL) { - debug ("uknown device type\n"); - res = -1; - goto xit; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to use USB %d:%d for fatls\n", - au_usb_stor_curr_dev, 1); - res = -1; - goto xit; - } - if (file_fat_detectfs() != 0) { - debug ("file_fat_detectfs failed\n"); - } - - /* - * now check whether start and end are defined using environment - * variables. - */ - start = -1; - end = 0; - env = getenv("firmware_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("firmware_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_FIRMWARE] = (end + 1) - start; - aufl_layout[IDX_FIRMWARE].start = start; - aufl_layout[IDX_FIRMWARE].end = end; - } - start = -1; - end = 0; - env = getenv("kernel_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("kernel_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_KERNEL] = (end + 1) - start; - aufl_layout[IDX_KERNEL].start = start; - aufl_layout[IDX_KERNEL].end = end; - } - start = -1; - end = 0; - env = getenv("rootfs_st"); - if (env != NULL) - start = simple_strtoul(env, NULL, 16); - env = getenv("rootfs_nd"); - if (env != NULL) - end = simple_strtoul(env, NULL, 16); - if (start >= 0 && end && end > start) { - ausize[IDX_ROOTFS] = (end + 1) - start; - aufl_layout[IDX_ROOTFS].start = start; - aufl_layout[IDX_ROOTFS].end = end; - } - - /* make certain that HUSH is runnable */ - u_boot_hush_start(); - /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); - - /* validate the images first */ - for (i = 0; i < AU_MAXFILES; i++) { - ulong imsize; - /* just read the header */ - sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ()); - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - if (sz <= 0 || sz < image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - ausize[i] = 0; - continue; - } - /* au_check_header_valid() updates ausize[] */ - if ((imsize = au_check_header_valid(i, sz)) < 0) { - debug ("%s header not valid\n", aufile[i]); - continue; - } - /* totsize accounts for image size and flash erase size */ - totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start)); - } - -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - lcd_puts(" Update in progress\n"); - lcd_enable(); - } -#endif - - /* just loop thru all the possible files */ - for (i = 0; i < AU_MAXFILES && totsize; i++) { - if (!ausize[i]) { - continue; - } - sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]); - - debug ("read %s sz %ld hdr %d\n", - aufile[i], sz, image_get_header_size ()); - - if (sz != ausize[i]) { - printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz); - continue; - } - - if (sz <= 0 || sz <= image_get_header_size ()) { - debug ("%s not found\n", aufile[i]); - continue; - } - if (au_check_cksum_valid(i, sz) < 0) { - debug ("%s checksum not valid\n", aufile[i]); - continue; - } - /* this is really not a good idea, but it's what the */ - /* customer wants. */ - cnt = 0; - do { - res = au_do_update(i, sz); - /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); - break; - } - cnt++; -#ifdef AU_TEST_ONLY - } while (res < 0 && cnt < (AU_MAXFILES + 1)); - if (cnt < (AU_MAXFILES + 1)) -#else - } while (res < 0); -#endif - } - - /* restore the old state */ - disable_ctrlc(old_ctrlc); -#ifdef CONFIG_PROGRESSBAR - if (totsize) { - if (!res) { - lcd_puts("\n Update completed\n"); - } else { - lcd_puts("\n Update error\n"); - } - lcd_enable(); - } -#endif - xit: - usb_stop(); - return res; -} -#endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c deleted file mode 100644 index c911445d97..0000000000 --- a/board/mcc200/lcd.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <lcd.h> -#include <mpc5xxx.h> -#include <malloc.h> - -#ifdef CONFIG_LCD - -#undef SWAPPED_LCD /* For the previous h/w version */ -/* - * The name of the device used for communication - * with the PSoC. - */ -#define PSOC_PSC MPC5XXX_PSC2 -#define PSOC_BAUD 230400UL - -#define RTS_ASSERT 1 -#define RTS_NEGATE 0 -#define CTS_ASSERT 1 -#define CTS_NEGATE 0 - -/* - * Dimensions in pixels - */ -#define LCD_WIDTH 160 -#define LCD_HEIGHT 100 - -/* - * Dimensions in bytes - */ -#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3) - -#if LCD_BPP != LCD_MONOCHROME -#error "MCC200 support only monochrome displays (1 bpp)!" -#endif - -#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ -#define PSOC_WAIT_TIME 10 /* usec */ - -#include <video_font.h> -#define FONT_WIDTH VIDEO_FONT_WIDTH - -DECLARE_GLOBAL_DATA_PTR; - -/* - * LCD information - */ -vidinfo_t panel_info = { - LCD_WIDTH, LCD_HEIGHT, LCD_BPP -}; - - -/* - * The device we use to communicate with PSoC - */ -int serial_inited = 0; - -/* - * Imported functions to support the PSoC protocol - */ -extern int serial_init_dev (unsigned long dev_base); -extern void serial_setrts_dev (unsigned long dev_base, int s); -extern int serial_getcts_dev (unsigned long dev_base); -extern void serial_putc_raw_dev(unsigned long dev_base, const char c); - -/* - * Just stubs for our driver, needed for compiling compabilty with - * the common LCD driver code. - */ -void lcd_initcolregs (void) -{ -} - -void lcd_ctrl_init (void *lcdbase) -{ -} - -/* - * Function sends the contents of the frame-buffer to the LCD - */ -void lcd_enable (void) -{ - int i, retries, fb_size; - - if (!serial_inited) { - unsigned long baud; - - baud = gd->baudrate; - gd->baudrate = PSOC_BAUD; - serial_init_dev(PSOC_PSC); - gd->baudrate = baud; - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - serial_inited = 1; - } - - /* - * Implement PSoC communication protocol: - * 1. Assert RTS, wait CTS assertion - * 2. Transmit data - * 3. Negate RTS, wait CTS negation - */ - - /* 1 */ - serial_setrts_dev (PSOC_PSC, RTS_ASSERT); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT) - break; - udelay (PSOC_WAIT_TIME); - } - if (!retries) { - printf ("%s Error: PSoC doesn't respond on " - "RTS ASSERT\n", __FUNCTION__); - } - - /* 2 */ - fb_size = panel_info.vl_row * (panel_info.vl_col >> 3); - -#if !defined(SWAPPED_LCD) - for (i=0; i<fb_size; i++) { - serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]); - } -#else - { - int x, y, pwidth; - char *p = (char *)gd->fb_base; - - pwidth = ((panel_info.vl_col+7) >> 3); - for (y=0; y<panel_info.vl_row; y++) { - i = y * pwidth; - for (x=0; x<pwidth; x+=5) { - serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F)); - serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F)); - } - } - } -#endif - - /* 3 */ - serial_setrts_dev (PSOC_PSC, RTS_NEGATE); - for (retries = PSOC_RETRIES; retries; retries--) { - if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE) - break; - udelay (PSOC_WAIT_TIME); - } - - return; -} -#ifdef CONFIG_PROGRESSBAR - -void show_progress (int size, int tot) -{ - int cnt; - int i; - static int rc = 0; - - rc += size; - - cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot; - - rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH); - - for (i = 0; i < cnt; i++) { - lcd_putc(0xdc); - } - - if (cnt) { - lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */ - } -} - -#endif - -int bmp_display(ulong addr, int x, int y) -{ - int ret; - bmp_image_t *bmp = (bmp_image_t *)addr; - - if (!bmp) { - printf("There is no valid bmp file at the given address\n"); - return 1; - } - - ret = lcd_display_bitmap((ulong)bmp, x, y); - - if ((unsigned long)bmp != addr) - free(bmp); - - return ret; -} - -#endif /* CONFIG_LCD */ diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c deleted file mode 100644 index 706886b84a..0000000000 --- a/board/mcc200/mcc200.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc5xxx.h> -#include <pci.h> -#include <asm/processor.h> - -/* Two MT48LC8M32B2 for 32 MB */ -/* #include "mt48lc8m32b2-6-7.h" */ - -/* One MT48LC16M32S2 for 64 MB */ -/* #include "mt48lc16m32s2-75.h" */ -#if defined (CONFIG_MCC200_SDRAM) -#include "mt48lc16m16a2-75.h" -#else -#include "mt46v16m16-75.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -extern flash_info_t flash_info[]; /* FLASH chips info */ - -extern int do_auto_update(void); -ulong flash_get_size (ulong base, int banknum); - -#ifndef CONFIG_SYS_RAMBOOT -static void sdram_start (int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set mode register: extended mode */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; - __asm__ volatile ("sync"); - - /* set mode register: reset DLL */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; - __asm__ volatile ("sync"); -#endif - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; - __asm__ volatile ("sync"); - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - __asm__ volatile ("sync"); - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; - __asm__ volatile ("sync"); - - udelay(10); -} -#endif - -/* - * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE - * is something else than 0x00000000. - */ - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; - ulong dramsize2 = 0; - uint svr, pvr; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - __asm__ volatile ("sync"); - -#if SDRAM_DDR - /* set tap delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; - __asm__ volatile ("sync"); -#endif - - /* find RAM size using SDRAM CS0 only */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) { - dramsize = 0; - } - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; - } else { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ - } - - /* let SDRAM CS1 start right after CS0 */ - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ - - /* find RAM size using SDRAM CS1 only */ - if (!dramsize) - sdram_start(0); - test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - if (!dramsize) { - sdram_start(1); - test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); - } - if (test1 > test2) { - sdram_start(0); - dramsize2 = test1; - } else { - dramsize2 = test2; - } - - /* memory smaller than 1MB is impossible */ - if (dramsize2 < (1 << 20)) { - dramsize2 = 0; - } - - /* set SDRAM CS1 size according to the amount of RAM found */ - if (dramsize2 > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize - | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); - } else { - *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ - } - -#else /* CONFIG_SYS_RAMBOOT */ - - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) { - dramsize = (1 << (dramsize - 0x13)) << 20; - } else { - dramsize = 0; - } - - /* retrieve size of memory connected to SDRAM CS1 */ - dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; - if (dramsize2 >= 0x13) { - dramsize2 = (1 << (dramsize2 - 0x13)) << 20; - } else { - dramsize2 = 0; - } - -#endif /* CONFIG_SYS_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - } - - return dramsize + dramsize2; -} - -int checkboard (void) -{ -#if defined(CONFIG_PRS200) - puts ("Board: PRS200\n"); -#else - puts ("Board: MCC200\n"); -#endif - return 0; -} - -int misc_init_r (void) -{ - ulong flash_sup_end, snum; - - /* - * Adjust flash start and offset to detected values - */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; - - /* - * Check if boot FLASH isn't max size - */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) { - /* adjust mapping */ - *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(gd->bd->bi_flashstart); - *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); - - /* - * Re-check to get correct base address - */ - flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); - - /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - } - - if (gd->bd->bi_flashsize > (32 << 20)) { - /* Unprotect the upper bank of the Flash */ - *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6); - flash_protect (FLAG_PROTECT_CLEAR, - flash_info[0].start[0] + flash_info[0].size / 2, - (flash_info[0].start[0] - 1) + flash_info[0].size, - &flash_info[0]); - *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); - printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); - flash_info[0].size = 32 << 20; - for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); - flash_info[0].start[snum] < flash_sup_end; - snum++); - flash_info[0].sector_count = snum; - } - -#ifdef CONFIG_AUTO_UPDATE - do_auto_update(); -#endif - return (0); -} - -#ifdef CONFIG_PCI -static struct pci_controller hose; - -extern void pci_mpc5xxx_init(struct pci_controller *); - -void pci_init_board(void) -{ - pci_mpc5xxx_init(&hose); -} -#endif - -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) - -void init_ide_reset (void) -{ - debug ("init_ide_reset\n"); - -} - -void ide_set_reset (int idereset) -{ - debug ("ide_reset(%d)\n", idereset); - -} -#endif - -#if defined(CONFIG_CMD_DOC) -void doc_init (void) -{ - doc_probe (CONFIG_SYS_DOC_BASE); -} -#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h deleted file mode 100644 index 9068fbf36f..0000000000 --- a/board/mcc200/mt46v16m16-75.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 1 /* is DDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m16a2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h deleted file mode 100644 index 0133eaa2ca..0000000000 --- a/board/mcc200/mt48lc16m32s2-75.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ -#define SDRAM_MODE 0x00CD0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xD2322800 -#define SDRAM_CONFIG2 0x8AD70000 diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h deleted file mode 100644 index 13aebbd8af..0000000000 --- a/board/mcc200/mt48lc8m32b2-6-7.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform - */ - -#define SDRAM_DDR 0 /* is SDR */ - -/* Settings for XLB = 132 MHz */ - -#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ -#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ -#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ -#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c index e3a582f3dc..73bfa00eed 100644 --- a/board/scb9328/flash.c +++ b/board/scb9328/flash.c @@ -72,8 +72,10 @@ static FLASH_BUS_RET flash_status_reg (void) FLASH_BUS *addr = (FLASH_BUS *) 0; + /* cppcheck-suppress nullPointer */ *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + /* cppcheck-suppress nullPointer */ return *addr; } diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 64e69dc93d..559af0e0e5 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -229,7 +229,7 @@ int board_eth_init(bd_t *bis) #endif /* #ifdef CONFIG_FACTORYSET */ /* Set rgmii mode and enable rmii clock to be sourced from chip */ - writel(RGMII_MODE_ENABLE , &cdev->miisel); + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index b9f6bd7122..1ddbb2c67c 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -22,4 +22,19 @@ config CONS_INDEX board you may want something other than UART0 as for example the IDK uses UART3 so enter 4 here. +config NOR + bool "Support for NOR flash" + help + The AM335x SoC supports having a NOR flash connected to the GPMC. + In practice this is seen as a NOR flash module connected to the + "memory cape" for the BeagleBone family. + +config NOR_BOOT + bool "Support for booting from NOR flash" + depends on NOR + help + Enabling this will make a U-Boot binary that is capable of being + booted via NOR. In this case we will enable certain pinmux early + as the ROM only partially sets up pinmux. We also default to using + NOR for environment. endif diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 96c5f22ead..384b175e9c 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -27,15 +27,12 @@ endif if TARGET_K2L_EVM config SYS_BOARD - string default "ks2_evm" config SYS_VENDOR - string default "ti" config SYS_CONFIG_NAME - string default "k2l_evm" endif diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index a551e2869a..9ee90a4f9d 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -3,10 +3,11 @@ U-Boot port for Texas Instruments Keystone II EVM boards Author: Murali Karicheri <m-karicheri2@ti.com> -This README has information on the u-boot port for K2HK, K2E boards. +This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards. Documentation for this board can be found at http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html +https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K. More details on these SoCs are available at company websites @@ -14,7 +15,10 @@ More details on these SoCs are available at company websites K2H: http://www.ti.com/product/tci6638k2h The K2E SoC details are available at - K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + http://www.ti.com/lit/ds/symlink/66ak2e05.pdf + +The K2L SoC details are available at + http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf Board configuration: ==================== @@ -25,6 +29,7 @@ Some of the peripherals that are configured by u-boot +------+-------+-------+-----------+-----------+-------+-------+----+ |K2HK |2 |512MB |6MB |4(2) |2 |3 |3 | |K2E |4 |512MB |2MB |8(2) |2 |3 |3 | +|K2L |2 |512MB |2MB |4(2) |4 |3 |3 | +------+-------+-------+-----------+-----------+-------+-------+----+ There are only 2 eth port installed on the boards. @@ -41,10 +46,13 @@ The port related files can be found at following folders Board configuration files: include/configs/k2hk_evm.h include/configs/k2e_evm.h +include/configs/k2l_evm.h +include/configs/k2l_evm.h As u-boot is migrating to Kconfig there is also board defconfig files configs/k2e_evm_defconfig configs/k2hk_evm_defconfig +configs/k2l_evm_defconfig Supported boot modes: - SPI NOR boot @@ -58,7 +66,7 @@ Supported image formats: Build instructions: =================== -Examples for k2hk, for k2e just replace k2hk prefix accordingly. +Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly. Don't forget to add ARCH=arm and CROSS_COMPILE. To build u-boot.bin @@ -84,6 +92,8 @@ Use u-boot.bin from the build folder for loading and running u-boot binary on EVM. Follow instructions at K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup +K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup + to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" and Power ON the EVM. Follow instructions to connect serial port of EVM to PC and start TeraTerm or Hyper Terminal. @@ -128,8 +138,8 @@ instructions: 2. Suspend Target. Select Run -> Suspend from top level menu CortexA15_1 (Free Running)" 3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM - using CCS", but using address 0x87000000. + through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L + EVM using CCS", but using address 0x87000000. 4. Free Run the target as described earlier (step 4) to get u-boot prompt 5. At the U-Boot console type following to setup u-boot environment variables. setenv addr_uboot 0x87000000 diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 4029493452..ff7bc4bb18 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -122,7 +122,6 @@ void ft_board_setup(void *blob, bd_t *bd) int nbanks; u64 size[2]; u64 start[2]; - char name[32]; int nodeoffset; u32 ddr3a_size; int unitrd_fixup = 0; @@ -158,15 +157,13 @@ void ft_board_setup(void *blob, bd_t *bd) } /* reserve memory at start of bank */ - sprintf(name, "mem_reserve_head"); - env = getenv(name); + env = getenv("mem_reserve_head"); if (env) { start[0] += ustrtoul(env, &endp, 0); size[0] -= ustrtoul(env, &endp, 0); } - sprintf(name, "mem_reserve"); - env = getenv(name); + env = getenv("mem_reserve"); if (env) size[0] -= ustrtoul(env, &endp, 0); diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index 559d20ca88..729a193239 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -10,7 +10,7 @@ #include <common.h> #include <asm/arch/ddr3.h> #include <asm/arch/hardware.h> -#include <asm/ti-common/ti-aemif.h> +#include <asm/ti-common/keystone_net.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,6 +42,44 @@ static struct pll_init_data tetris_pll_config[] = { static struct pll_init_data pa_pll_config = PASS_PLL_983; +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2L_EMAC", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2L_EMAC1", + .rx_flow = 8, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2L_EMAC2", + .rx_flow = 16, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2L_EMAC3", + .rx_flow = 32, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { diff --git a/common/cli_hush.c b/common/cli_hush.c index 2b654b754f..d643912922 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -3162,7 +3162,7 @@ static int parse_stream_outer(struct in_str *inp, int flag) o_string temp=NULL_O_STRING; int rcode; #ifdef __U_BOOT__ - int code = 0; + int code = 1; #endif do { ctx.type = flag; @@ -3217,7 +3217,7 @@ static int parse_stream_outer(struct in_str *inp, int flag) } b_free(&temp); /* loop on syntax errors, return on EOF */ - } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) && + } while (rcode != 1 && !(flag & FLAG_EXIT_FROM_LOOP) && (inp->peek != static_peek || b_peek(inp))); #ifndef __U_BOOT__ return 0; @@ -3236,8 +3236,10 @@ int parse_string_outer(const char *s, int flag) #ifdef __U_BOOT__ char *p = NULL; int rcode; - if ( !s || !*s) + if (!s) return 1; + if (!*s) + return 0; if (!(p = strchr(s, '\n')) || *++p) { p = xmalloc(strlen(s) + 2); strcpy(p, s); diff --git a/common/cmd_fitupd.c b/common/cmd_fitupd.c index e811473b47..b0459744d9 100644 --- a/common/cmd_fitupd.c +++ b/common/cmd_fitupd.c @@ -1,12 +1,8 @@ -de <net.h> - -#if !defined(CONFIG_UPDATE_TFTP) -#error "CONFIG_UPDATE_TFTP required" -#endif - -static int do_fitupd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr = 0Un the root directory of the source tree for details. +/* + * (C) Copyright 2011 + * Andreas Pretzsch, carpe noctem engineering, apr@cn-eng.de + * + * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> diff --git a/common/dlmalloc.c b/common/dlmalloc.c index f9873393c1..d87834df67 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -2181,7 +2181,7 @@ Void_t* mALLOc(bytes) size_t bytes; INTERNAL_SIZE_T nb; #ifdef CONFIG_SYS_MALLOC_F_LEN - if (!(gd->flags & GD_FLG_RELOC)) { + if (gd && !(gd->flags & GD_FLG_RELOC)) { ulong new_ptr; void *ptr; diff --git a/common/image-fdt.c b/common/image-fdt.c index a2342fa3df..a39ae1b4cc 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -413,11 +413,11 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto error; } } else { debug("## No Flattened Device Tree\n"); - return 0; + goto error; } *of_flat_tree = fdt_blob; diff --git a/common/lcd.c b/common/lcd.c index 787d80e3cb..37147af805 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -881,7 +881,7 @@ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb, } #endif -#if defined(CONFIG_MPC823) || defined(CONFIG_MCC200) +#if defined(CONFIG_MPC823) #define FB_PUT_BYTE(fb, from) *(fb)++ = (255 - *(from)++) #else #define FB_PUT_BYTE(fb, from) *(fb)++ = *(from)++ @@ -906,9 +906,7 @@ static inline void fb_put_word(uchar **fb, uchar **from) int lcd_display_bitmap(ulong bmp_image, int x, int y) { -#if !defined(CONFIG_MCC200) ushort *cmap = NULL; -#endif ushort *cmap_base = NULL; ushort i, j; uchar *fb; @@ -956,8 +954,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) debug("Display-bmp: %d x %d with %d colors\n", (int)width, (int)height, (int)colors); -#if !defined(CONFIG_MCC200) - /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ if (bmp_bpix == 8) { cmap = configuration_get_cmap(); cmap_base = cmap; @@ -985,24 +981,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) #endif } } -#endif - /* - * BMP format for Monochrome assumes that the state of a - * pixel is described on a per Bit basis, not per Byte. - * So, in case of Monochrome BMP we should align widths - * on a byte boundary and convert them from Bit to Byte - * units. - * Probably, PXA250 and MPC823 process 1bpp BMP images in - * their own ways, so make the converting to be MCC200 - * specific. - */ -#if defined(CONFIG_MCC200) - if (bpix == 1) { - width = ((width + 7) & ~7) >> 3; - x = ((x + 7) & ~7) >> 3; - pwidth= ((pwidth + 7) & ~7) >> 3; - } -#endif padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width); diff --git a/common/usb_storage.c b/common/usb_storage.c index eb7706c100..1411737bed 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1351,8 +1351,11 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, perq = usb_stor_buf[0]; modi = usb_stor_buf[1]; - if ((perq & 0x1f) == 0x1f) { - /* skip unknown devices */ + /* + * Skip unknown devices (0x1f) and enclosure service devices (0x0d), + * they would not respond to test_unit_ready . + */ + if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) { return 0; } if ((modi&0x80) == 0x80) { diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index 41f31cc02e..be901633ac 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -1,5 +1,6 @@ CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="NAND,NOR" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_CONS_INDEX=1 +S:CONFIG_ARM=y +S:CONFIG_TARGET_AM335X_EVM=y +CONFIG_NOR=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index 7dbfa277e0..47ff6cdb16 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -1,4 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="NOR,NOR_BOOT" CONFIG_CONS_INDEX=1 CONFIG_ARM=y CONFIG_TARGET_AM335X_EVM=y +CONFIG_NOR=y +CONFIG_NOR_BOOT=y diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig new file mode 100644 index 0000000000..4000d2c75d --- /dev/null +++ b/configs/cm_t3517_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=n ++S:CONFIG_ARM=y ++S:CONFIG_OMAP34XX=y ++S:CONFIG_TARGET_CM_T3517=y diff --git a/configs/mcc200_COM12_SDRAM_defconfig b/configs/mcc200_COM12_SDRAM_defconfig deleted file mode 100644 index be6dbd7240..0000000000 --- a/configs/mcc200_COM12_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_COM12_defconfig b/configs/mcc200_COM12_defconfig deleted file mode 100644 index 6ed86358a1..0000000000 --- a/configs/mcc200_COM12_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_COM12_highboot_SDRAM_defconfig b/configs/mcc200_COM12_highboot_SDRAM_defconfig deleted file mode 100644 index 5f93702f0e..0000000000 --- a/configs/mcc200_COM12_highboot_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_COM12_highboot_defconfig b/configs/mcc200_COM12_highboot_defconfig deleted file mode 100644 index 7abb0a40be..0000000000 --- a/configs/mcc200_COM12_highboot_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_SDRAM_defconfig b/configs/mcc200_SDRAM_defconfig deleted file mode 100644 index 37761b5625..0000000000 --- a/configs/mcc200_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_defconfig b/configs/mcc200_defconfig deleted file mode 100644 index b6aafec3ee..0000000000 --- a/configs/mcc200_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_highboot_SDRAM_defconfig b/configs/mcc200_highboot_SDRAM_defconfig deleted file mode 100644 index 94d33e5896..0000000000 --- a/configs/mcc200_highboot_SDRAM_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/mcc200_highboot_defconfig b/configs/mcc200_highboot_defconfig deleted file mode 100644 index f863dd9fcb..0000000000 --- a/configs/mcc200_highboot_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index e6aba422f8..f54b15fa30 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -8,4 +8,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y CONFIG_UNIPHIER_SERIAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 334ec4bbdf..e7957520fb 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -8,4 +8,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y CONFIG_UNIPHIER_SERIAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 4e8f354c9b..65109374b7 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -8,4 +8,7 @@ CONFIG_SYS_NAND_DENALI_64BIT=y CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8 CONFIG_DM_SERIAL=y CONFIG_UNIPHIER_SERIAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y S:CONFIG_SPL_NAND_DENALI=y diff --git a/configs/prs200_DDR_defconfig b/configs/prs200_DDR_defconfig deleted file mode 100644 index 541fb995af..0000000000 --- a/configs/prs200_DDR_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/prs200_defconfig b/configs/prs200_defconfig deleted file mode 100644 index a094a088cb..0000000000 --- a/configs/prs200_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/prs200_highboot_DDR_defconfig b/configs/prs200_highboot_DDR_defconfig deleted file mode 100644 index b8eb8d4d81..0000000000 --- a/configs/prs200_highboot_DDR_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/prs200_highboot_defconfig b/configs/prs200_highboot_defconfig deleted file mode 100644 index 8d68cc06b8..0000000000 --- a/configs/prs200_highboot_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM" -CONFIG_PPC=y -CONFIG_MPC5xxx=y -CONFIG_TARGET_MCC200=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig new file mode 100644 index 0000000000..0f3896d5f0 --- /dev/null +++ b/configs/socfpga_socrates_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" diff --git a/doc/README.kwbimage b/doc/README.kwbimage index 13f6f92f68..762b2e3acb 100644 --- a/doc/README.kwbimage +++ b/doc/README.kwbimage @@ -30,10 +30,10 @@ kwbimage support available with mkimage utility will generate kirkwood boot image that can be flashed on the board NAND/SPI flash. The make target which uses mkimage to produce such an image is "u-boot.kwb". For example: - export BUILD_DIR=/tmp/build + export KBUILD_OUTPUT=/tmp/build make distclean make yourboard_config - make $BUILD_DIR/u-boot.kwb + make u-boot.kwb Board specific configuration file specifications: diff --git a/doc/README.scrapyard b/doc/README.scrapyard index bd4dd3c829..8ba6e0ae65 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,9 +12,11 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -TOP5200 powerpc mpc5200 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> -TOP860 powerpc mpc860 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> -TOP9000 arm at91sam9xeXXX - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> +PRS200 powerpc mpc5200 - - +MCC200 powerpc mpc5200 - - +TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> +TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> +TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk <wd@denx.de> TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk <wd@denx.de> IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher <hs@denx.de> diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c index 77707c2109..dfca75abdc 100644 --- a/drivers/dma/keystone_nav.c +++ b/drivers/dma/keystone_nav.c @@ -81,9 +81,6 @@ void qm_close(void) { u32 j; - if (qm_cfg == NULL) - return; - queue_close(qm_cfg->qpool_num); qm_cfg->mngr_cfg->link_ram_base0 = 0; @@ -105,9 +102,6 @@ void qm_push(struct qm_host_desc *hd, u32 qnum) { u32 regd; - if (!qm_cfg) - return; - cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4); regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1); writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh); @@ -127,9 +121,6 @@ struct qm_host_desc *qm_pop(u32 qnum) { u32 uhd; - if (!qm_cfg) - return NULL; - uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf; if (uhd) cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4); @@ -139,9 +130,6 @@ struct qm_host_desc *qm_pop(u32 qnum) struct qm_host_desc *qm_pop_from_free_pool(void) { - if (!qm_cfg) - return NULL; - return qm_pop(qm_cfg->qpool_num); } diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 811033b0b8..7bb1702bba 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -38,7 +38,7 @@ * generic value. */ #ifndef CONFIG_I2C_TIMEOUT -#define CONFIG_I2C_TIMEOUT 10000 +#define CONFIG_I2C_TIMEOUT 100000 #endif #define I2C_READ_BIT 1 diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c index e7a15ba644..df8888550b 100644 --- a/drivers/i2c/ppc4xx_i2c.c +++ b/drivers/i2c/ppc4xx_i2c.c @@ -158,8 +158,7 @@ static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) * * Typical case is a Write of an addr followd by a Read. The * IBM FAQ does not cover this. On the last byte of the write - * we don't set the creg CHT bit, and on the first bytes of the - * read we set the RPST bit. + * we don't set the creg CHT bit but the RPST bit. * * It does not support address only transfers, there must be * a data part. If you want to write the address yourself, put @@ -247,6 +246,10 @@ static int _i2c_transfer(struct i2c_adapter *adap, if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt)) creg |= IIC_CNTL_CHT; + /* last part of address, prepare for repeated start on read */ + if (cmd_type && (ptr == addr) && ((tran + bc) == cnt)) + creg |= IIC_CNTL_RPST; + if (reading) { creg |= IIC_CNTL_READ; } else { @@ -286,6 +289,27 @@ static int _i2c_transfer(struct i2c_adapter *adap, /* Transfer aborted? */ if (status & IIC_EXTSTS_XFRA) result = IIC_NOK_XFRA; + /* Is bus free? + * If error happened during combined xfer + * IIC interface is usually stuck in some strange + * state without a valid stop condition. + * Brute, but working: generate stop, then soft reset. + */ + if ((status & IIC_EXTSTS_BCS_MASK) + != IIC_EXTSTS_BCS_FREE){ + u8 mdcntl = in_8(&i2c->mdcntl); + + /* Generate valid stop condition */ + out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST); + out_8(&i2c->directcntl, IIC_DIRCNTL_SCC); + udelay(10); + out_8(&i2c->directcntl, + IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC); + out_8(&i2c->xtcntlss, 0); + + ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM) + ? 400000 : 100000, 0); + } } else if ( status & IIC_STS_PT) { result = IIC_NOK_TOUT; } @@ -314,8 +338,6 @@ static int _i2c_transfer(struct i2c_adapter *adap, cnt = data_len; tran = 0; reading = cmd_type; - if (reading) - creg = IIC_CNTL_RPST; } } return result; diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index 50cebd622b..90ad116a98 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -119,10 +119,10 @@ rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) /* set slave address, receive */ writel((chip << 1) | 1, &dev->icmar); - /* clear status */ - writel(0, &dev->icmsr); /* start master receive */ writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); + /* clear status */ + writel(0, &dev->icmsr); while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) != (MSR_MAT | MSR_MDR)) diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 464cee16d1..461d7d8ec1 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -5,37 +5,39 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o +obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o +obj-$(CONFIG_DWMMC) += dw_mmc.o +obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o obj-$(CONFIG_GENERIC_MMC) += mmc.o obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o +obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o -obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o +obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o obj-$(CONFIG_MXC_MMC) += mxcmmc.o obj-$(CONFIG_MXS_MMC) += mxsmmc.o obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o -obj-$(CONFIG_SDHCI) += sdhci.o -obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o -obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o +obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o +obj-$(CONFIG_SDHCI) += sdhci.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o +obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o -obj-$(CONFIG_DWMMC) += dw_mmc.o -obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o -obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o -obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o -obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o + ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else obj-$(CONFIG_GENERIC_MMC) += mmc_write.o endif -obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o + diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index ef2cbf9e2f..ffb5284a00 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -611,7 +611,8 @@ static int omap_hsmmc_getcd(struct mmc *mmc) if (cd_gpio < 0) return 1; - return gpio_get_value(cd_gpio); + /* NOTE: assumes card detect signal is active-low */ + return !gpio_get_value(cd_gpio); } static int omap_hsmmc_getwp(struct mmc *mmc) @@ -624,6 +625,7 @@ static int omap_hsmmc_getwp(struct mmc *mmc) if (wp_gpio < 0) return 0; + /* NOTE: assumes write protect signal is active-high */ return gpio_get_value(wp_gpio); } #endif diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index c8681d0223..bedab1d606 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -315,7 +315,7 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); -#ifdef CONFIG_K2E_EVM +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) /* Map RX packet flow priority to 0 */ writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); #endif @@ -400,6 +400,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) keystone2_net_serdes_setup(); + if (sys_has_mdio) + keystone2_mdio_reset(mdio_bus); + keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1, eth_priv->sgmii_link_type); @@ -582,7 +585,7 @@ static void keystone2_net_serdes_setup(void) &ks2_serdes_sgmii_156p25mhz, CONFIG_KSNET_SERDES_LANES_PER_SGMII); -#ifdef CONFIG_SOC_K2E +#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, &ks2_serdes_sgmii_156p25mhz, CONFIG_KSNET_SERDES_LANES_PER_SGMII); diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index d2ecadc890..9437c3bbcc 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -276,6 +276,57 @@ static int m88e1111s_config(struct phy_device *phydev) return 0; } +/** + * m88e1518_phy_writebits - write bits to a register + */ +void m88e1518_phy_writebits(struct phy_device *phydev, + u8 reg_num, u16 offset, u16 len, u16 data) +{ + u16 reg, mask; + + if ((len + offset) >= 16) + mask = 0 - (1 << offset); + else + mask = (1 << (len + offset)) - (1 << offset); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); + + reg &= ~mask; + reg |= data << offset; + + phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); +} + +static int m88e1518_config(struct phy_device *phydev) +{ + /* + * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 + * /88E1514 Rev A0, Errata Section 3.1 + */ + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* page 0xff */ + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); /* reg page 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); /* reg page 18 */ + /* Write HWCFG_MODE = SGMII to Copper */ + m88e1518_phy_writebits(phydev, 20, 0, 3, 1); + + /* Phy reset */ + m88e1518_phy_writebits(phydev, 20, 15, 1, 1); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */ + udelay(100); + } + + return m88e1111s_config(phydev); +} + /* Marvell 88E1118 */ static int m88e1118_config(struct phy_device *phydev) { @@ -493,7 +544,7 @@ static struct phy_driver M88E1518_driver = { .uid = 0x1410dd1, .mask = 0xffffff0, .features = PHY_GBIT_FEATURES, - .config = &m88e1111s_config, + .config = &m88e1518_config, .startup = &m88e1011s_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index b097c1a56f..5959672370 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -187,6 +187,7 @@ static int smc911x_send(struct eth_device *dev, void *packet, int length) static void smc911x_halt(struct eth_device *dev) { smc911x_reset(dev); + smc911x_handle_mac_address(dev); } static int smc911x_rx(struct eth_device *dev) diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 538f11e3eb..9526faa4af 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -548,7 +548,7 @@ static int uli526x_rx_packet(struct eth_device *dev) rdes0 = le32_to_cpu(rxptr->rdes0); #ifdef RX_DEBUG - printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0); + printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0); #endif if (!(rdes0 & 0x80000000)) { /* packet owner check */ if ((rdes0 & 0x300) != 0x300) { diff --git a/drivers/power/power_spi.c b/drivers/power/power_spi.c index fb455a0061..1e554461f3 100644 --- a/drivers/power/power_spi.c +++ b/drivers/power/power_spi.c @@ -17,27 +17,14 @@ static struct spi_slave *slave; -void pmic_spi_free(struct spi_slave *slave) -{ - if (slave) - spi_free_slave(slave); -} - -struct spi_slave *pmic_spi_probe(struct pmic *p) -{ - return spi_setup_slave(p->bus, - p->hw.spi.cs, - p->hw.spi.clk, - p->hw.spi.mode); -} - static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write) { u32 pmic_tx, pmic_rx; u32 tmp; if (!slave) { - slave = pmic_spi_probe(p); + slave = spi_setup_slave(p->bus, p->hw.spi.cs, p->hw.spi.clk, + p->hw.spi.mode); if (!slave) return -1; @@ -54,25 +41,25 @@ static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write) tmp = cpu_to_be32(pmic_tx); if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx, - pmic_spi_flags)) { - spi_release_bus(slave); - return -1; - } + pmic_spi_flags)) + goto err; if (write) { pmic_tx = p->hw.spi.prepare_tx(reg, val, 0); tmp = cpu_to_be32(pmic_tx); if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx, - pmic_spi_flags)) { - spi_release_bus(slave); - return -1; - } + pmic_spi_flags)) + goto err; } spi_release_bus(slave); *val = cpu_to_be32(pmic_rx); return 0; + +err: + spi_release_bus(slave); + return -1; } int pmic_reg_write(struct pmic *p, u32 reg, u32 val) diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 3f3d415213..6046efb51f 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> +#include <linux/serial_reg.h> #include <asm/io.h> #include <asm/errno.h> #include <dm/device.h> @@ -37,17 +37,6 @@ struct uniphier_serial { #define thr rbr -/* - * These are the definitions for the Line Control Register - */ -#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ - -/* - * These are the definitions for the Line Status Register - */ -#define UART_LSR_DR 0x01 /* Data ready */ -#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ - struct uniphier_serial_private_data { struct uniphier_serial __iomem *membase; }; @@ -62,7 +51,7 @@ static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) const unsigned int mode_x_div = 16; unsigned int divisor; - writeb(UART_LCR_WLS_8, &port->lcr); + writeb(UART_LCR_WLEN8, &port->lcr); divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate); diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index e69de29bb2..b4a9442703 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -0,0 +1,46 @@ +config USB_ARCH_HAS_HCD + def_bool y + +config USB + bool "Support for Host-side USB" + depends on USB_ARCH_HAS_HCD + ---help--- + Universal Serial Bus (USB) is a specification for a serial bus + subsystem which offers higher speeds and more features than the + traditional PC serial port. The bus supplies power to peripherals + and allows for hot swapping. Up to 127 USB peripherals can be + connected to a single USB host in a tree structure. + + The USB host is the root of the tree, the peripherals are the + leaves and the inner nodes are special USB devices called hubs. + Most PCs now have USB host ports, used to connect peripherals + such as scanners, keyboards, mice, modems, cameras, disks, + flash memory, network links, and printers to the PC. + + Say Y here if your computer has a host-side USB port and you want + to use USB devices. You then need to say Y to at least one of the + Host Controller Driver (HCD) options below. Choose a USB 1.1 + controller, such as "UHCI HCD support" or "OHCI HCD support", + and "EHCI HCD (USB 2.0) support" except for older systems that + do not have USB 2.0 support. It doesn't normally hurt to select + them all if you are not certain. + + If your system has a device-side USB port, used in the peripheral + side of the USB protocol, see the "USB Gadget" framework instead. + + After choosing your HCD, then select drivers for the USB peripherals + you'll be using. You may want to check out the information provided + in <file:Documentation/usb/> and especially the links given in + <file:Documentation/usb/usb-help.txt>. + +if USB + +source "drivers/usb/host/Kconfig" + +config USB_STORAGE + bool "USB Mass Storage support" + ---help--- + Say Y here if you want to connect USB mass storage devices to your + board's USB port. + +endif diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile index 94551c4c0c..e6ae9f1e52 100644 --- a/drivers/usb/eth/Makefile +++ b/drivers/usb/eth/Makefile @@ -5,8 +5,6 @@ # new USB host ethernet layer dependencies obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o -ifdef CONFIG_USB_ETHER_ASIX -obj-y += asix.o -endif +obj-$(CONFIG_USB_ETHER_ASIX) += asix.o obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 2efd5a4d5b..70bb550fa4 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o ifdef CONFIG_USB_GADGET obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o +obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_THOR_FUNCTION) += f_thor.o diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index b9816dfe30..7653f03949 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -31,7 +31,6 @@ #include <asm/io.h> #include <asm/mach-types.h> -#include <asm/arch/gpio.h> #include "regs-otg.h" #include <usb/lin_gadget_compat.h> @@ -105,7 +104,7 @@ static void stop_activity(struct s3c_udc *dev, struct usb_gadget_driver *driver); static int udc_enable(struct s3c_udc *dev); static void udc_set_address(struct s3c_udc *dev, unsigned char address); -static void reconfig_usbd(void); +static void reconfig_usbd(struct s3c_udc *dev); static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed); static void nuke(struct s3c_ep *ep, int status); static int s3c_udc_set_halt(struct usb_ep *_ep, int value); @@ -146,68 +145,14 @@ static struct usb_ep_ops s3c_ep_ops = { void __iomem *regs_otg; struct s3c_usbotg_reg *reg; -struct s3c_usbotg_phy *phy; -static unsigned int usb_phy_ctrl; bool dfu_usb_get_reset(void) { return !!(readl(®->gintsts) & INT_RESET); } -void otg_phy_init(struct s3c_udc *dev) -{ - dev->pdata->phy_control(1); - - /*USB PHY0 Enable */ - printf("USB PHY0 Enable\n"); - - /* Enable PHY */ - writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); - - if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */ - writel((readl(&phy->phypwr) - &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN) - &~FORCE_SUSPEND_0), &phy->phypwr); - else /* C110 GONI */ - writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) - &~FORCE_SUSPEND_0), &phy->phypwr); - - if (s5p_cpu_id == 0x4412) - writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | - EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, - &phy->phyclk); /* PLL 24Mhz */ - else - writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | - CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ - - writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) - | PHY_SW_RST0, &phy->rstcon); - udelay(10); - writel(readl(&phy->rstcon) - &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon); - udelay(10); -} - -void otg_phy_off(struct s3c_udc *dev) -{ - /* reset controller just in case */ - writel(PHY_SW_RST0, &phy->rstcon); - udelay(20); - writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); - udelay(20); - - writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN - | FORCE_SUSPEND_0, &phy->phypwr); - - writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); - - writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)), - &phy->phyclk); - - udelay(10000); - - dev->pdata->phy_control(0); -} +__weak void otg_phy_init(struct s3c_udc *dev) {} +__weak void otg_phy_off(struct s3c_udc *dev) {} /***********************************************************/ @@ -270,7 +215,7 @@ static int udc_enable(struct s3c_udc *dev) debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev); otg_phy_init(dev); - reconfig_usbd(); + reconfig_usbd(dev); debug_cond(DEBUG_SETUP != 0, "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n", @@ -451,15 +396,17 @@ static void stop_activity(struct s3c_udc *dev, udc_reinit(dev); } -static void reconfig_usbd(void) +static void reconfig_usbd(struct s3c_udc *dev) { /* 2. Soft-reset OTG Core and then unreset again. */ int i; unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); + uint32_t dflt_gusbcfg; debug("Reseting OTG controller\n"); - writel(0<<15 /* PHY Low Power Clock sel*/ + dflt_gusbcfg = + 0<<15 /* PHY Low Power Clock sel*/ |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/ |0x5<<10 /* Turnaround time*/ |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/ @@ -468,8 +415,12 @@ static void reconfig_usbd(void) |0<<6 /* 0: high speed utmi+, 1: full speed serial*/ |0<<4 /* 0: utmi+, 1:ulpi*/ |1<<3 /* phy i/f 0:8bit, 1:16bit*/ - |0x7<<0, /* HS/FS Timeout**/ - ®->gusbcfg); + |0x7<<0; /* HS/FS Timeout**/ + + if (dev->pdata->usb_gusbcfg) + dflt_gusbcfg = dev->pdata->usb_gusbcfg; + + writel(dflt_gusbcfg, ®->gusbcfg); /* 3. Put the OTG device core in the disconnected state.*/ uTemp = readl(®->dctl); @@ -854,9 +805,7 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata) dev->pdata = pdata; - phy = (struct s3c_usbotg_phy *)pdata->regs_phy; reg = (struct s3c_usbotg_reg *)pdata->regs_otg; - usb_phy_ctrl = pdata->usb_phy_ctrl; /* regs_otg = (void *)pdata->regs_otg; */ diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c b/drivers/usb/gadget/s3c_udc_otg_phy.c new file mode 100644 index 0000000000..f13cb8910a --- /dev/null +++ b/drivers/usb/gadget/s3c_udc_otg_phy.c @@ -0,0 +1,101 @@ +/* + * drivers/usb/gadget/s3c_udc_otg.c + * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers + * + * Copyright (C) 2008 for Samsung Electronics + * + * BSP Support for Samsung's UDC driver + * available at: + * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git + * + * State machine bugfixes: + * Marek Szyprowski <m.szyprowski@samsung.com> + * + * Ported to u-boot: + * Marek Szyprowski <m.szyprowski@samsung.com> + * Lukasz Majewski <l.majewski@samsumg.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/errno.h> +#include <linux/list.h> +#include <malloc.h> + +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> + +#include <asm/byteorder.h> +#include <asm/unaligned.h> +#include <asm/io.h> + +#include <asm/mach-types.h> + +#include "regs-otg.h" +#include <usb/lin_gadget_compat.h> + +#include <usb/s3c_udc.h> + +void otg_phy_init(struct s3c_udc *dev) +{ + unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; + struct s3c_usbotg_phy *phy = + (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + + dev->pdata->phy_control(1); + + /* USB PHY0 Enable */ + printf("USB PHY0 Enable\n"); + + /* Enable PHY */ + writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); + + if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */ + writel((readl(&phy->phypwr) + &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN) + &~FORCE_SUSPEND_0), &phy->phypwr); + else /* C110 GONI */ + writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) + &~FORCE_SUSPEND_0), &phy->phypwr); + + if (s5p_cpu_id == 0x4412) + writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | + EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, + &phy->phyclk); /* PLL 24Mhz */ + else + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | + CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ + + writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) + | PHY_SW_RST0, &phy->rstcon); + udelay(10); + writel(readl(&phy->rstcon) + &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon); + udelay(10); +} + +void otg_phy_off(struct s3c_udc *dev) +{ + unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl; + struct s3c_usbotg_phy *phy = + (struct s3c_usbotg_phy *)dev->pdata->regs_phy; + + /* reset controller just in case */ + writel(PHY_SW_RST0, &phy->rstcon); + udelay(20); + writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); + udelay(20); + + writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN + | FORCE_SUSPEND_0, &phy->phypwr); + + writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); + + writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)), + &phy->phyclk); + + udelay(10000); + + dev->pdata->phy_control(0); +} diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 4f69b22a25..9c54b462c4 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -551,7 +551,7 @@ static int s3c_udc_irq(int irq, void *_dev) debug_cond(DEBUG_ISR, "\t\tOTG core got reset (%d)!!\n", reset_available); - reconfig_usbd(); + reconfig_usbd(dev); dev->ep0state = WAIT_FOR_SETUP; reset_available = 0; s3c_udc_pre_setup(); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig new file mode 100644 index 0000000000..30d1457638 --- /dev/null +++ b/drivers/usb/host/Kconfig @@ -0,0 +1,56 @@ +# +# USB Host Controller Drivers +# +comment "USB Host Controller Drivers" + +config USB_XHCI_HCD + bool "xHCI HCD (USB 3.0) support" + ---help--- + The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 + "SuperSpeed" host controller hardware. + +config USB_XHCI + bool + default USB_XHCI_HCD + ---help--- + TODO: rename after most boards switch to Kconfig + +if USB_XHCI_HCD + +endif + +config USB_EHCI_HCD + bool "EHCI HCD (USB 2.0) support" + ---help--- + The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 + "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. + If your USB host controller supports USB 2.0, you will likely want to + configure this Host Controller Driver. + + EHCI controllers are packaged with "companion" host controllers (OHCI + or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports + will connect to EHCI if the device is high speed, otherwise they + connect to a companion controller. If you configure EHCI, you should + probably configure the OHCI (for NEC and some other vendors) USB Host + Controller Driver or UHCI (for Via motherboards) Host Controller + Driver too. + + You may want to read <file:Documentation/usb/ehci.txt>. + +config USB_EHCI + bool + default USB_EHCI_HCD + ---help--- + TODO: rename after most boards switch to Kconfig + +if USB_EHCI_HCD + +config USB_EHCI_UNIPHIER + bool "Support for Panasonic UniPhier on-chip EHCI USB controller" + depends on ARCH_UNIPHIER + default y + ---help--- + Enables support for the on-chip EHCI controller on Panasonic + UniPhier SoCs. + +endif diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 1c3592914d..c11b551620 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o +obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c index b4330876f8..7fe79efc17 100644 --- a/drivers/usb/host/ehci-rmobile.c +++ b/drivers/usb/host/ehci-rmobile.c @@ -13,18 +13,18 @@ #include "ehci.h" #if defined(CONFIG_R8A7740) -static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { +static u32 usb_base_address[] = { 0xC6700000 }; #elif defined(CONFIG_R8A7790) -static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { +static u32 usb_base_address[] = { 0xEE080000, /* USB0 (EHCI) */ 0xEE0A0000, /* USB1 */ 0xEE0C0000, /* USB2 */ }; #elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ defined(CONFIG_R8A7794) -static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { +static u32 usb_base_address[] = { 0xEE080000, /* USB0 (EHCI) */ 0xEE0C0000, /* USB1 */ }; @@ -53,7 +53,7 @@ int ehci_hcd_stop(int index) if (!i) printf("error : ehci(%d) reset failed.\n", index); - if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1)) + if (index == (ARRAY_SIZE(usb_base_address) - 1)) setbits_le32(SMSTPCR7, SMSTPCR703); return 0; diff --git a/drivers/usb/host/ehci-uniphier.c b/drivers/usb/host/ehci-uniphier.c new file mode 100644 index 0000000000..77f6c9d9d1 --- /dev/null +++ b/drivers/usb/host/ehci-uniphier.c @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <usb.h> +#include <asm/arch/ehci-uniphier.h> +#include "ehci.h" + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, + struct ehci_hcor **hcor) +{ + struct ehci_hccr *cr; + struct ehci_hcor *or; + + uniphier_ehci_reset(index, 0); + + cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base); + or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase)); + + *hccr = cr; + *hcor = or; + + return 0; +} + +int ehci_hcd_stop(int index) +{ + uniphier_ehci_reset(index, 1); + + return 0; +} diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 433e703da8..79aecd414e 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -47,9 +47,9 @@ struct ehci_hcor { uint32_t or_usbcmd; #define CMD_PARK (1 << 11) /* enable "park" */ #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ -#define CMD_ASE (1 << 5) /* async schedule enable */ #define CMD_LRESET (1 << 7) /* partial reset */ -#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */ +#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */ +#define CMD_ASE (1 << 5) /* async schedule enable */ #define CMD_PSE (1 << 4) /* periodic schedule enable */ #define CMD_RESET (1 << 1) /* reset HC not bus */ #define CMD_RUN (1 << 0) /* start/stop HC */ diff --git a/fs/zfs/zfs.c b/fs/zfs/zfs.c index 818d3d926d..fb2b3ee089 100644 --- a/fs/zfs/zfs.c +++ b/fs/zfs/zfs.c @@ -736,7 +736,7 @@ zap_hash(uint64_t salt, const char *name) uint64_t crc = salt; if (table[128] == 0) { - uint64_t *ct; + uint64_t *ct = NULL; int i, j; for (i = 0; i < 256; i++) { for (ct = table + i, *ct = i, j = 8; j > 0; j--) @@ -1060,6 +1060,7 @@ zap_lookup(dnode_end_t *zap_dnode, char *name, uint64_t *val, } printf("unknown ZAP type\n"); + free(zapbuf); return ZFS_ERR_BAD_FS; } @@ -1094,6 +1095,7 @@ zap_iterate(dnode_end_t *zap_dnode, return ret; } printf("unknown ZAP type\n"); + free(zapbuf); return 0; } @@ -1865,6 +1867,7 @@ zfs_mount(device_t dev) ubbest = malloc(sizeof(*ubbest)); if (!ubbest) { + free(ub_array); zfs_unmount(data); return 0; } @@ -1953,6 +1956,7 @@ zfs_mount(device_t dev) if (err) { printf("couldn't zio_read object directory\n"); zfs_unmount(data); + free(osp); free(ubbest); return 0; } @@ -2052,6 +2056,9 @@ zfs_open(struct zfs_file *file, const char *fsfilename) hdrsize = SA_HDR_SIZE(((sa_hdr_phys_t *) sahdrp)); file->size = *(uint64_t *) ((char *) sahdrp + hdrsize + SA_SIZE_OFFSET); + if ((data->dnode.dn.dn_bonuslen == 0) && + (data->dnode.dn.dn_flags & DNODE_FLAG_SPILL_BLKPTR)) + free(sahdrp); } else { file->size = zfs_to_cpu64(((znode_phys_t *) DN_BONUS(&data->dnode.dn))->zp_size, data->dnode.endian); } diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 1ec783daf4..560e3bf775 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -314,6 +314,18 @@ #define CONFIG_AM335X_USB1 #define CONFIG_AM335X_USB1_MODE MUSB_HOST +#ifndef CONFIG_SPL_USBETH_SUPPORT +/* Fastboot */ +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 + +/* To support eMMC booting */ +#define CONFIG_STORAGE_EMMC +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#endif + #ifdef CONFIG_MUSB_HOST #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE @@ -325,8 +337,8 @@ #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" /* USB TI's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x0403 -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_VENDOR_NUM 0x0451 +#define CONFIG_G_DNL_PRODUCT_NUM 0xD022 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" #endif /* CONFIG_MUSB_GADGET */ diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index ea9acf69d1..07ec5f2bd8 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -39,6 +39,7 @@ # define CONFIG_CMD_FAT # define CONFIG_CMD_MMC # define CONFIG_DOS_PARTITION +# define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 # endif # ifdef CONFIG_MMC_SPI # define CONFIG_CMD_MMC_SPI diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h new file mode 100644 index 0000000000..918032bd75 --- /dev/null +++ b/include/configs/cm_t3517.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2013 CompuLab, Ltd. + * Author: Igor Grinberg <grinberg@compulab.co.il> + * + * Configuration settings for the CompuLab CM-T3517 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_CM_T3517 /* working with CM-T3517 */ +#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * This is needed for the DMA stuff. + * Although the default iss 64, we still define it + * to be on the safe side once the default is changed. + */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_OF_LIBFDT +/* + * The early kernel mapping on ARM currently only maps from the base of DRAM + * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. + * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, + * so that leaves DRAM base to DRAM base + 0x4000 available. + */ +#define CONFIG_SYS_BOOTMAPSZ 0x4000 + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_SERIAL_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +#define CONFIG_OMAP_GPIO + +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION + +/* USB */ +#define CONFIG_USB_MUSB_AM35X + +#ifndef CONFIG_USB_MUSB_AM35X +#define CONFIG_USB_OMAP3 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 +#else /* !CONFIG_USB_MUSB_AM35X */ +#define CONFIG_MUSB_HOST +#define CONFIG_MUSB_PIO_ONLY +#endif /* CONFIG_USB_MUSB_AM35X */ + +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),256k(u-boot-env),"\ + "4m(kernel),-(fs)" + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_GPIO + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_BUS 0 +#define CONFIG_I2C_MULTI_BUS + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "baudrate=115200\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=auto\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ + "mmcrootfstype=ext4\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=setenv bootargs console=${console} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 2a0000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_CMD_BOOTZ +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_TIMESTAMP +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "CM-T3517 # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define CONFIG_SYS_CS0_SIZE (256 << 20) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) +#endif /* CONFIG_CMD_NET */ + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Status LED */ +#define CONFIG_STATUS_LED /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_GPIO_LED +#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ +#define GREEN_LED_DEV 0 +#define STATUS_LED_BIT GREEN_LED_GPIO +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BOOT GREEN_LED_DEV + +/* GPIO banks */ +#ifdef CONFIG_STATUS_LED +#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ +#endif + +/* Display Configuration */ +#define CONFIG_OMAP3_GPIO_2 +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_VIDEO_OMAP3 +#define LCD_BPP LCD_COLOR16 + +#define CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASHIMAGE_GUARD +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_SCF0403_LCD + +#define CONFIG_OMAP3_SPI + +#endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 89ba14e05d..41631c72e9 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -59,6 +59,7 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 7c8065ad18..d83e07e242 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -17,14 +17,15 @@ /* U-Boot general configuration */ #define CONFIG_SYS_PROMPT "K2E EVM # " -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" - -#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0" -#define KS2_ADDR_MON "addr_mon=0x0c140000\0" -#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0" -#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0" -#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0" +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c140000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "name_fdt=uImage-k2e-evm.dtb\0" \ + "name_mon=skern-k2e-evm.bin\0" \ + "name_ubi=k2e-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2e-evm.gph\0" \ + "name_fs=arago-console-image-k2e-evm.cpio.gz\0" #include <configs/ks2_evm.h> @@ -35,14 +36,8 @@ #define CONFIG_SYS_NAND_PAGE_2K /* Network */ -#define CONFIG_DRIVER_TI_KEYSTONE_NET -#define CONFIG_TI_KSNAV -#define CONFIG_KSNAV_PKTDMA_NETCP #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 #define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -/* SerDes */ -#define CONFIG_TI_KEYSTONE_SERDES - #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 034cbfd4d7..ffddf1391c 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -17,14 +17,15 @@ /* U-Boot general configuration */ #define CONFIG_SYS_PROMPT "K2HK EVM # " -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" - -#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0" -#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0" -#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0" -#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0" -#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0" +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c5f0000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "name_fdt=uImage-k2hk-evm.dtb\0" \ + "name_mon=skern-k2hk-evm.bin\0" \ + "name_ubi=k2hk-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ + "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" #include <configs/ks2_evm.h> @@ -35,13 +36,7 @@ #define CONFIG_SYS_NAND_PAGE_2K /* Network */ -#define CONFIG_DRIVER_TI_KEYSTONE_NET -#define CONFIG_TI_KSNAV -#define CONFIG_KSNAV_PKTDMA_NETCP #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 -/* SerDes */ -#define CONFIG_TI_KEYSTONE_SERDES - #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 0e1f7251b3..805164a679 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -17,14 +17,15 @@ /* U-Boot general configuration */ #define CONFIG_SYS_PROMPT "K2L EVM # " -#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" - -#define KS2_FDT_NAME "name_fdt=k2l-evm.dtb\0" -#define KS2_ADDR_MON "addr_mon=0x0c140000\0" -#define KS2_NAME_MON "name_mon=skern-k2l-evm.bin\0" -#define NAME_UBOOT "name_uboot=u-boot-spi-k2l-evm.gph\0" -#define NAME_UBI "name_ubi=k2l-evm-ubifs.ubi\0" +#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "addr_mon=0x0c140000\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" \ + "name_fdt=uImage-k2l-evm.dtb\0" \ + "name_mon=skern-k2l-evm.bin\0" \ + "name_ubi=k2l-evm-ubifs.ubi\0" \ + "name_uboot=u-boot-spi-k2l-evm.gph\0" \ + "name_fs=arago-console-image-k2l-evm.cpio.gz\0" #include <configs/ks2_evm.h> @@ -34,4 +35,9 @@ /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_4K +/* Network */ +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + #endif /* __CONFIG_K2L_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index b0c91d8dcb..dd5050fbe9 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -105,6 +105,7 @@ #define CONFIG_SYS_SGMII_RATESCALE 2 /* Keyston Navigator Configuration */ +#define CONFIG_TI_KSNAV #define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS #define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE #define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE @@ -121,6 +122,7 @@ #define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM /* NETCP pktdma */ +#define CONFIG_KSNAV_PKTDMA_NETCP #define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE #define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE #define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM @@ -134,12 +136,16 @@ #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE /* Keystone net */ +#define CONFIG_DRIVER_TI_KEYSTONE_NET #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES +/* SerDes */ +#define CONFIG_TI_KEYSTONE_SERDES + /* AEMIF */ #define CONFIG_TI_AEMIF #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE @@ -218,6 +224,8 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC /* U-Boot general configuration */ #define CONFIG_SYS_GENERIC_BOARD @@ -239,30 +247,25 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "uImage" #define CONFIG_EXTRA_ENV_SETTINGS \ - "boot=ramfs\0" \ + CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ + "boot=ubi\0" \ "tftp_root=/\0" \ "nfs_root=/export\0" \ "mem_lpae=1\0" \ "mem_reserve=512M\0" \ "addr_fdt=0x87000000\0" \ "addr_kern=0x88000000\0" \ - KS2_ADDR_MON \ "addr_uboot=0x87000000\0" \ "addr_fs=0x82000000\0" \ "addr_ubi=0x82000000\0" \ "addr_secdb_key=0xc000000\0" \ "fdt_high=0xffffffff\0" \ - KS2_FDT_NAME \ - "name_fs=arago-console-image.cpio.gz\0" \ - "name_kern=uImage\0" \ - KS2_NAME_MON \ - NAME_UBOOT \ - NAME_UBI \ + "name_kern=uImage-keystone-evm.bin\0" \ "run_mon=mon_install ${addr_mon}\0" \ "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ "init_net=run args_all args_net\0" \ "init_ubi=run args_all args_ubi; " \ - "ubi part ubifs; ubifsmount boot;" \ + "ubi part ubifs; ubifsmount ubi:boot;" \ "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ @@ -276,7 +279,6 @@ "burn_uboot_nand=nand erase 0 0x100000; " \ "nand write ${addr_uboot} 0 ${filesize}\0" \ "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ - KS2_ARGS_UBI \ "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ "${nfs_options} ip=dhcp\0" \ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h deleted file mode 100644 index a317782dbe..0000000000 --- a/include/configs/mcc200.h +++ /dev/null @@ -1,397 +0,0 @@ -/* - * (C) Copyright 2006-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5200 -#define CONFIG_MCC200 1 /* MCC200 board */ - -/* - * Valid values for CONFIG_SYS_TEXT_BASE are: - * 0xFC000000 boot low (standard configuration) - * 0xFFF00000 boot high - * 0x00100000 boot from RAM (for testing only) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xFC000000 -#endif - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - * - * To select console on the one of 8 external UARTs, - * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, - * or as 5, 6, 7, or 8 for the second Quad UART. - * COM11, COM12, COM13, COM14 are located on the second Quad UART. - * - * CONFIG_PSC_CONSOLE must be undefined in this case. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#ifdef CONFIG_CONSOLE_COM12 -#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ -#else -#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ -#endif -#else -/* PRS200 configuration: */ -#undef CONFIG_QUART_CONSOLE -#endif /* CONFIG_PRS200 */ -/* - * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 - * and undefine CONFIG_QUART_CONSOLE. - */ -#if !defined(CONFIG_PRS200) -/* MCC200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ -#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ -#else -/* PRS200 configuration: */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#endif -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_MII 1 - -#define CONFIG_DOS_PARTITION - -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -/* automatic software updates (see board/mcc200/auto_update.c) */ -#define CONFIG_AUTO_UPDATE 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_USB - -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#ifdef CONFIG_PRS200 -# define CONFIG_SYS__BOARDNAME "prs200" -# define CONFIG_SYS__LINUX_CONSOLE "ttyS0" -#else -# define CONFIG_SYS__BOARDNAME "mcc200" -# define CONFIG_SYS__LINUX_CONSOLE "ttyEU5" -#endif - -/* Network */ -#define CONFIG_ETHADDR 00:17:17:ff:00:00 -#define CONFIG_IPADDR 10.76.9.29 -#define CONFIG_SERVERIP 10.76.9.1 - -#include <version.h> /* For U-Boot version */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubootver=" U_BOOT_VERSION "\0" \ - "netdev=eth0\0" \ - "hostname=" CONFIG_SYS__BOARDNAME "\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/mtdblock2 " \ - "rootfstype=cramfs\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate} " \ - "ubootver=${ubootver} board=${board}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "console=" CONFIG_SYS__LINUX_CONSOLE "\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \ - "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \ - "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "kernel_addr=0xFC0C0000\0" \ - "update=protect off ${text_base} +${filesize};" \ - "era ${text_base} +${filesize};" \ - "cp.b 200000 ${text_base} ${filesize}\0" \ - "unlock=yes\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * Flash configuration (8,16 or 32 MB) - * TEXT base always at 0xFFF00000 - * ENV_ADDR always at 0xFFF40000 - * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) - * 0xFE000000 for 32 MB - * 0xFF000000 for 16 MB - * 0xFF800000 for 8 MB - */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 - -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ - -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ - -#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xf0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -/* #define CONFIG_MPC5xxx_FEC 1 */ -/* #define CONFIG_MPC5xxx_FEC_MII100 */ -/* - * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb - */ -/* #define CONFIG_MPC5xxx_FEC_MII10 */ -#define CONFIG_PHY_ADDR 1 - -/* - * LCD Splash Screen - */ -#if !defined(CONFIG_PRS200) -#define CONFIG_LCD 1 -#define CONFIG_PROGRESSBAR 1 -#endif - -#if defined(CONFIG_LCD) -#define CONFIG_SPLASH_SCREEN 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -#define LCD_BPP LCD_MONOCHROME -#endif - -/* - * GPIO configuration - */ -/* 0x10000004 = 32MB SDRAM */ -/* 0x90000004 = 64MB SDRAM */ -#if defined(CONFIG_LCD) -/* set PSC2 in UART mode */ -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044 -#else -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#define CONFIG_SYS_BOOTCS_CFG 0x0004fb00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ -#define CONFIG_SYS_CS2_START 0x80000000 -#define CONFIG_SYS_CS2_SIZE 0x00001000 -#define CONFIG_SYS_CS2_CFG 0x1d300 - -/* Second Quad UART @0x80010000 */ -#define CONFIG_SYS_CS1_START 0x80010000 -#define CONFIG_SYS_CS1_SIZE 0x00001000 -#define CONFIG_SYS_CS1_CFG 0x1d300 - -/* Leica - build revision resistors */ -/* -#define CONFIG_SYS_CS3_START 0x80020000 -#define CONFIG_SYS_CS3_SIZE 0x00000004 -#define CONFIG_SYS_CS3_CFG 0x1d300 -*/ - -/* - * Select one of quarts as a default - * console. If undefined - PSC console - * wil be default - */ -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/* - * QUART Expanders support - */ -#if defined(CONFIG_QUART_CONSOLE) -/* - * We'll use NS16550 chip routines, - */ -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL 1 -#define CONFIG_CONS_INDEX 1 -/* - * To achieve necessary offset on SC16C554 - * A0-A2 (register select) pins with NS16550 - * functions (in struct NS16550), REG_SIZE - * should be 4, because A0-A2 pins are connected - * to DA2-DA4 address bus lines. - */ -#define CONFIG_SYS_NS16550_REG_SIZE 4 -/* - * LocalPlus Bus already inited in cpu_init_f(), - * so can work with QUART's chip selects. - * One of four SC16C554 UARTs is selected with - * A3-A4 (DA5-DA6) lines. - */ -#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) -#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) -#else -#error "Wrong QUART expander number." -#endif - -/* - * SC16C554 chip's external crystal oscillator frequency - * is 7.3728 MHz - */ -#define CONFIG_SYS_NS16550_CLK 7372800 -#endif /* CONFIG_QUART_CONSOLE */ -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00005000 - -#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#define CONFIG_AUTOBOOT_STOP_STR "432" -#define CONFIG_SILENT_CONSOLE 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 183c449284..18388d150b 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -17,6 +17,8 @@ * High Level Configuration Options */ #define CONFIG_MPC5200 +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 006c9a9c0d..b2b3750c1e 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -29,8 +29,6 @@ #define CONFIG_REVISION_TAG 1 -#define CONFIG_SUPPORT_RAW_INITRD - /* define to enable boot progress via leds */ #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) diff --git a/include/configs/ph1_ld4.h b/include/configs/ph1_ld4.h index 005a853f56..73a95e615e 100644 --- a/include/configs/ph1_ld4.h +++ b/include/configs/ph1_ld4.h @@ -37,8 +37,6 @@ #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 -#define CONFIG_DDR_FREQ 1600 - /* * Memory Size & Mapping */ diff --git a/include/configs/ph1_pro4.h b/include/configs/ph1_pro4.h index 7dd6fd2a92..fc5132d1cc 100644 --- a/include/configs/ph1_pro4.h +++ b/include/configs/ph1_pro4.h @@ -37,8 +37,6 @@ #define CONFIG_DDR_NUM_CH0 2 #define CONFIG_DDR_NUM_CH1 2 -#define CONFIG_DDR_FREQ 1600 - #define CONFIG_UNIPHIER_SMP /* diff --git a/include/configs/ph1_sld8.h b/include/configs/ph1_sld8.h index 1062aace38..e2f1102003 100644 --- a/include/configs/ph1_sld8.h +++ b/include/configs/ph1_sld8.h @@ -37,8 +37,6 @@ #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 -#define CONFIG_DDR_FREQ 1333 - /* #define CONFIG_DDR_STANDARD */ /* diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 3633a355bd..dfa2e07948 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -281,6 +281,7 @@ #define CONFIG_SYS_MAX_I2C_BUS 7 #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_CMD_USB_MASS_STORAGE diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 4b30d148c3..e7bace4345 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -181,6 +181,7 @@ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED /* diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index a2469eb60c..655025c912 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -14,6 +14,7 @@ #undef CONFIG_BOARD_COMMON #undef CONFIG_USB_GADGET #undef CONFIG_USB_GADGET_S3C_UDC_OTG +#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY #undef CONFIG_CMD_USB_MASS_STORAGE #undef CONFIG_REVISION_TAG #undef CONFIG_CMD_THOR_DOWNLOAD diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 83a1bcdfbe..c436fdaf52 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -37,7 +37,7 @@ */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE @@ -79,6 +79,25 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 + */ +#endif + +/* * Ethernet on SoC (EMAC) */ #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) @@ -141,6 +160,33 @@ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ #endif + /* + * I2C support + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DW +#define CONFIG_SYS_I2C_BUS_MAX 4 +#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS +#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS +#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS +#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS +/* Using standard mode which the speed up to 100Kb/s */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SPEED1 100000 +#define CONFIG_SYS_I2C_SPEED2 100000 +#define CONFIG_SYS_I2C_SPEED3 100000 +/* Address of device when used as slave */ +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_SYS_I2C_SLAVE1 0x02 +#define CONFIG_SYS_I2C_SLAVE2 0x02 +#define CONFIG_SYS_I2C_SLAVE3 0x02 +#ifndef __ASSEMBLY__ +/* Clock supplied to I2C controller in unit of MHz */ +unsigned int cm_get_l4_sp_clk_hz(void); +#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) +#endif +#define CONFIG_CMD_I2C + /* * Serial Driver */ @@ -172,6 +218,34 @@ #endif /* + * USB Gadget (DFU, UMS) + */ +#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_MASS_STORAGE + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ +#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ +#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM +#ifndef CONFIG_G_DNL_MANUFACTURER +#define CONFIG_G_DNL_MANUFACTURER "Altera" +#endif +#endif + +/* * U-Boot environment */ #define CONFIG_SYS_CONSOLE_IS_IN_ENV diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 942738c138..c3d958cb30 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -42,7 +42,7 @@ /* Booting Linux */ #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTFILE "zImage" -#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_BOOTCOMMAND "run ramboot" #else diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 4b9b629692..a8790c2f8f 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -174,6 +174,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD /* * Common filesystems support. When we have removable storage we diff --git a/include/configs/uniphier-common.h b/include/configs/uniphier-common.h index b18ae6dfae..7c4dba0387 100644 --- a/include/configs/uniphier-common.h +++ b/include/configs/uniphier-common.h @@ -43,7 +43,7 @@ are defined. Select only one of them." #define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE #define CONFIG_SMC911X_32_BIT -#define CONFIG_SYS_MALLOC_F_LEN 0x7000 +#define CONFIG_SYS_MALLOC_F_LEN 0x2000 /*----------------------------------------------------------------------- * MMU and Cache Setting @@ -166,6 +166,13 @@ are defined. Select only one of them." #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_DOS_PARTITION + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) @@ -241,9 +248,9 @@ are defined. Select only one of them." #define CONFIG_SYS_TEXT_BASE 0x84000000 -#if defined(CONFIG_SPL_BUILD) #define CONFIG_BOARD_POSTCLK_INIT -#else + +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h new file mode 100644 index 0000000000..3f04908fb8 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 +#define L2_RESET 4 + +/* PERMODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define USB0_RESET 34 +#define USB1_RESET 35 +#define NAND_RESET 36 +#define QSPI_RESET 37 +#define L4WD0_RESET 38 +#define L4WD1_RESET 39 +#define OSC1TIMER0_RESET 40 +#define OSC1TIMER1_RESET 41 +#define SPTIMER0_RESET 42 +#define SPTIMER1_RESET 43 +#define I2C0_RESET 44 +#define I2C1_RESET 45 +#define I2C2_RESET 46 +#define I2C3_RESET 47 +#define UART0_RESET 48 +#define UART1_RESET 49 +#define SPIM0_RESET 50 +#define SPIM1_RESET 51 +#define SPIS0_RESET 52 +#define SPIS1_RESET 53 +#define SDMMC_RESET 54 +#define CAN0_RESET 55 +#define CAN1_RESET 56 +#define GPIO0_RESET 57 +#define GPIO1_RESET 58 +#define GPIO2_RESET 59 +#define DMA_RESET 60 +#define SDR_RESET 61 + +/* PER2MODRST */ +#define DMAIF0_RESET 64 +#define DMAIF1_RESET 65 +#define DMAIF2_RESET 66 +#define DMAIF3_RESET 67 +#define DMAIF4_RESET 68 +#define DMAIF5_RESET 69 +#define DMAIF6_RESET 70 +#define DMAIF7_RESET 71 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 + +/* MISCMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +#define SYSMGR_RESET 130 +#define SYSMGRCOLD_RESET 131 +#define FPGAMGR_RESET 132 +#define ACPIDMAP_RESET 133 +#define S2F_RESET 134 +#define S2FCOLD_RESET 135 +#define NRSTPIN_RESET 136 +#define TIMESTAMPCOLD_RESET 137 +#define CLKMGRCOLD_RESET 138 +#define SCANMGR_RESET 139 +#define FRZCTRLCOLD_RESET 140 +#define SYSDBG_RESET 141 +#define DBG_RESET 142 +#define TAPCOLD_RESET 143 +#define SDRCOLD_RESET 144 + +#endif diff --git a/include/lcd.h b/include/lcd.h index ea5860c861..020d8800e9 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -250,7 +250,7 @@ typedef struct vidinfo { void *priv; /* Pointer to driver-specific data */ } vidinfo_t; -#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */ +#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */ extern vidinfo_t panel_info; diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h new file mode 100644 index 0000000000..9214b67b11 --- /dev/null +++ b/include/linux/serial_reg.h @@ -0,0 +1,388 @@ +/* + * include/linux/serial_reg.h + * + * Copyright (C) 1992, 1994 by Theodore Ts'o. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * These are the UART port assignments, expressed as offsets from the base + * register. These assignments should hold for any serial port based on + * a 8250, 16450, or 16550(A). + */ + +#ifndef _LINUX_SERIAL_REG_H +#define _LINUX_SERIAL_REG_H + +/* + * DLAB=0 + */ +#define UART_RX 0 /* In: Receive buffer */ +#define UART_TX 0 /* Out: Transmit buffer */ + +#define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ +/* + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 + */ +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ + +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x0e /* Mask for the interrupt ID */ +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +#define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ + +#define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ +#define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ +#define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ + +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +/* + * Note: The FIFO trigger levels are chip specific: + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 + * PC16550D: 1 4 8 14 xx xx xx xx + * TI16C550A: 1 4 8 14 xx xx xx xx + * TI16C550C: 1 4 8 14 xx xx xx xx + * ST16C550: 1 4 8 14 xx xx xx xx + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 + * NS16C552: 1 4 8 14 xx xx xx xx + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 + * TI16C752: 8 16 56 60 8 16 32 56 + * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA + */ +#define UART_FCR_R_TRIG_00 0x00 +#define UART_FCR_R_TRIG_01 0x40 +#define UART_FCR_R_TRIG_10 0x80 +#define UART_FCR_R_TRIG_11 0xc0 +#define UART_FCR_T_TRIG_00 0x00 +#define UART_FCR_T_TRIG_01 0x10 +#define UART_FCR_T_TRIG_10 0x20 +#define UART_FCR_T_TRIG_11 0x30 + +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +/* 16650 definitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ + +#define UART_LCR 3 /* Out: Line Control Register */ +/* + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * Access to some registers depends on register access / configuration + * mode. + */ +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ +#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ + +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_LSR_FIFOE 0x80 /* Fifo error */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ +#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ + +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +#define UART_SCR 7 /* I/O: Scratch Register */ + +/* + * DLAB=1 + */ +#define UART_DLL 0 /* Out: Divisor Latch Low */ +#define UART_DLM 1 /* Out: Divisor Latch High */ + +/* + * LCR=0xBF (or DLAB=1 for 16C660) + */ +#define UART_EFR 2 /* I/O: Extended Features Register */ +#define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ECB 0x10 /* Enhanced control bit */ +/* + * the low four bits control software flow control + */ + +/* + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 + */ +#define UART_XON1 4 /* I/O: Xon character 1 */ +#define UART_XON2 5 /* I/O: Xon character 2 */ +#define UART_XOFF1 6 /* I/O: Xoff character 1 */ +#define UART_XOFF2 7 /* I/O: Xoff character 2 */ + +/* + * EFR[4]=1 MCR[6]=1, TI16C752 + */ +#define UART_TI752_TCR 6 /* I/O: transmission control register */ +#define UART_TI752_TLR 7 /* I/O: trigger level register */ + +/* + * LCR=0xBF, XR16C85x + */ +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx + * In: Fifo count + * Out: Fifo custom trigger levels */ +/* + * These are the definitions for the Programmable Trigger Register + */ +#define UART_TRG_1 0x01 +#define UART_TRG_4 0x04 +#define UART_TRG_8 0x08 +#define UART_TRG_16 0x10 +#define UART_TRG_32 0x20 +#define UART_TRG_64 0x40 +#define UART_TRG_96 0x60 +#define UART_TRG_120 0x78 +#define UART_TRG_128 0x80 + +#define UART_FCTR 1 /* Feature Control Register */ +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ +#define UART_FCTR_RTS_4DELAY 0x01 +#define UART_FCTR_RTS_6DELAY 0x02 +#define UART_FCTR_RTS_8DELAY 0x03 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ + +/* + * LCR=0xBF, FCTR[6]=1 + */ +#define UART_EMSR 7 /* Extended Mode Select Register */ +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ + +/* + * The Intel XScale on-chip UARTs define these bits + */ +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */ +#define UART_IER_UUE 0x40 /* UART Unit Enable */ +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */ +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ + +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ + +#define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ +#define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ +#define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ +#define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ + +/* + * Intel MID on-chip HSU (High Speed UART) defined bits + */ +#define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ +#define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ +#define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ +#define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ + +#define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ +#define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ +#define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ +#define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ + +#define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ +#define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ + +#define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ +#define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ + +/* + * These register definitions are for the 16C950 + */ +#define UART_ASR 0x01 /* Additional Status Register */ +#define UART_RFL 0x03 /* Receiver FIFO level */ +#define UART_TFL 0x04 /* Transmitter FIFO level */ +#define UART_ICR 0x05 /* Index Control Register */ + +/* The 16950 ICR registers */ +#define UART_ACR 0x00 /* Additional Control Register */ +#define UART_CPR 0x01 /* Clock Prescalar Register */ +#define UART_TCR 0x02 /* Times Clock Register */ +#define UART_CKS 0x03 /* Clock Select Register */ +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ +#define UART_FCL 0x06 /* Flow Control Level Lower */ +#define UART_FCH 0x07 /* Flow Control Level Higher */ +#define UART_ID1 0x08 /* ID #1 */ +#define UART_ID2 0x09 /* ID #2 */ +#define UART_ID3 0x0A /* ID #3 */ +#define UART_REV 0x0B /* Revision */ +#define UART_CSR 0x0C /* Channel Software Reset */ +#define UART_NMR 0x0D /* Nine-bit Mode Register */ +#define UART_CTR 0xFF + +/* + * The 16C950 Additional Control Register + */ +#define UART_ACR_RXDIS 0x01 /* Receiver disable */ +#define UART_ACR_TXDIS 0x02 /* Transmitter disable */ +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */ +#define UART_ACR_ASREN 0x80 /* Additional status enable */ + + + +/* + * These definitions are for the RSA-DV II/S card, from + * + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp> + */ + +#define UART_RSA_BASE (-8) + +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ + +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ + +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ + +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ + +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ + +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ + +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ + +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ + +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ + +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ + +/* + * The RSA DSV/II board has two fixed clock frequencies. One is the + * standard rate, and the other is 8 times faster. + */ +#define SERIAL_RSA_BAUD_BASE (921600) +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) + +/* + * Extra serial register definitions for the internal UARTs + * in TI OMAP processors. + */ +#define UART_OMAP_MDR1 0x08 /* Mode definition register */ +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ +#define UART_OMAP_SCR 0x10 /* Supplementary control register */ +#define UART_OMAP_SSR 0x11 /* Supplementary status register */ +#define UART_OMAP_EBLR 0x12 /* BOF length register */ +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ +#define UART_OMAP_MVER 0x14 /* Module version register */ +#define UART_OMAP_SYSC 0x15 /* System configuration register */ +#define UART_OMAP_SYSS 0x16 /* System status register */ +#define UART_OMAP_WER 0x17 /* Wake-up enable register */ + +/* + * These are the definitions for the MDR1 register + */ +#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ +#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ +#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ +#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ +#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ +#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ +#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ +#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ + +/* + * These are definitions for the Exar XR17V35X and XR17(C|D)15X + */ +#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ +#define UART_EXAR_SLEEP 0x8b /* Sleep mode */ +#define UART_EXAR_DVID 0x8d /* Device identification */ + +#define UART_EXAR_FCTR 0x08 /* Feature Control Register */ +#define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */ +#define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */ +#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ +#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ +#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ +#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ + +#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ +#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ + +#endif /* _LINUX_SERIAL_REG_H */ + diff --git a/include/twl4030.h b/include/twl4030.h index 18795a601b..f33cd1eaed 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -390,6 +390,8 @@ /* Voltage Selection in PM Receiver Module */ #define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05 +#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09 +#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01 #define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03 #define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05 #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 diff --git a/include/usb.h b/include/usb.h index 9d0d04dd8e..d3c741597c 100644 --- a/include/usb.h +++ b/include/usb.h @@ -11,6 +11,8 @@ #include <usb_defs.h> #include <linux/usb/ch9.h> +#include <asm/cache.h> +#include <part.h> /* * The EHCI spec says that we must align to at least 32 bytes. However, diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 70e48f88ee..7f49a4e2d5 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -108,5 +108,6 @@ struct s3c_plat_otg_data { unsigned int regs_otg; unsigned int usb_phy_ctrl; unsigned int usb_flags; + unsigned int usb_gusbcfg; }; #endif diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 4c333599c1..d20f20ae32 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -177,13 +177,13 @@ ld-ifversion = $(shell [ $(call ld-version) $(1) $(2) ] && echo $(3)) # Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj= # Usage: # $(Q)$(MAKE) $(build)=dir -build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj +build := -f $(srctree)/scripts/Makefile.build obj ### # Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj= # Usage: # $(Q)$(MAKE) $(modbuiltin)=dir -modbuiltin := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.modbuiltin obj +modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj # Prefix -I with $(srctree) if it is not an absolute path. # skip if -I has no parameter @@ -221,11 +221,13 @@ else arg-check = $(if $(strip $(cmd_$@)),,1) endif -# >'< substitution is for echo to work, -# >$< substitution to preserve $ when reloading .cmd file -# note: when using inline perl scripts [perl -e '...$$t=1;...'] -# in $(cmd_xxx) double $$ your perl vars -make-cmd = $(subst \\,\\\\,$(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1)))))) +# Replace >$< with >$$< to preserve $ when reloading the .cmd file +# (needed for make) +# Replace >#< with >\#< to avoid starting a comment in the .cmd file +# (needed for make) +# Replace >'< with >'\''< to be able to enclose the whole string in '...' +# (needed for the shell) +make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1))))) # Find any prerequisites that is newer than target or that does not exist. # PHONY targets skipped in both cases. @@ -236,7 +238,7 @@ any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^) if_changed = $(if $(strip $(any-prereq) $(arg-check)), \ @set -e; \ $(echo-cmd) $(cmd_$(1)); \ - echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd) + printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd) # Execute the command and also postprocess generated .d dependencies file. if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \ diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index ced2b9a6b0..8e9d71f89e 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -89,9 +89,12 @@ PHONY += create_symlink create_symlink: ifneq ($(KBUILD_SRC),) $(Q)mkdir -p include/asm + $(Q)ln -fsn $(KBUILD_SRC)/arch/$(ARCH)/include/asm/arch-$(if $(SOC),$(SOC),$(CPU)) \ + include/asm/arch +else + $(Q)ln -fsn arch-$(if $(SOC),$(SOC),$(CPU)) \ + arch/$(ARCH)/include/asm/arch endif - $(Q)ln -fsn $(srctree)/arch/$(ARCH)/include/asm/arch-$(if $(SOC),$(SOC),$(CPU)) \ - $(if $(KBUILD_SRC),,arch/$(ARCH)/)include/asm/arch PHONY += FORCE FORCE: diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 6742ddd0b8..14cf0925d2 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -97,11 +97,11 @@ endif # =========================================================================== -ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),) +ifneq ($(strip $(lib-y) $(lib-m) $(lib-)),) lib-target := $(obj)/lib.a endif -ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(subdir-m) $(lib-target)),) +ifneq ($(strip $(obj-y) $(obj-m) $(obj-) $(subdir-m) $(lib-target)),) builtin-target := $(obj)/built-in.o endif @@ -400,16 +400,14 @@ cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalys quiet_cmd_link_multi-m = LD [M] $@ cmd_link_multi-m = $(cmd_link_multi-y) -# We would rather have a list of rules like -# foo.o: $(foo-objs) -# but that's not so easy, so we rather make all composite objects depend -# on the set of all their parts -$(multi-used-y) : %.o: $(multi-objs-y) FORCE +$(multi-used-y): FORCE $(call if_changed,link_multi-y) +$(call multi_depend, $(multi-used-y), .o, -objs -y) -$(multi-used-m) : %.o: $(multi-objs-m) FORCE +$(multi-used-m): FORCE $(call if_changed,link_multi-m) @{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod) +$(call multi_depend, $(multi-used-m), .o, -objs -y) targets += $(multi-used-y) $(multi-used-m) diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean index 88f14e2d8f..21e1f21531 100644 --- a/scripts/Makefile.clean +++ b/scripts/Makefile.clean @@ -10,7 +10,7 @@ __clean: # Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir # Usage: # $(Q)$(MAKE) $(clean)=dir -clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj +clean := -f $(srctree)/scripts/Makefile.clean obj # The filename Kbuild has precedence over Makefile kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) @@ -23,15 +23,13 @@ __subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y))) subdir-y += $(__subdir-y) __subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m))) subdir-m += $(__subdir-m) -__subdir-n := $(patsubst %/,%,$(filter %/, $(obj-n))) -subdir-n += $(__subdir-n) __subdir- := $(patsubst %/,%,$(filter %/, $(obj-))) subdir- += $(__subdir-) # Subdirectories we need to descend into subdir-ym := $(sort $(subdir-y) $(subdir-m)) -subdir-ymn := $(sort $(subdir-ym) $(subdir-n) $(subdir-)) +subdir-ymn := $(sort $(subdir-ym) $(subdir-)) # Add subdir path diff --git a/scripts/Makefile.host b/scripts/Makefile.host index 66893643fd..133edfae5b 100644 --- a/scripts/Makefile.host +++ b/scripts/Makefile.host @@ -20,21 +20,12 @@ # Will compile qconf as a C++ program, and menu as a C program. # They are linked as C++ code to the executable qconf -# hostprogs-y := conf -# conf-objs := conf.o libkconfig.so -# libkconfig-objs := expr.o type.o -# Will create a shared library named libkconfig.so that consists of -# expr.o and type.o (they are both compiled as C code and the object files -# are made as position independent code). -# conf.c is compiled as a C program, and conf.o is linked together with -# libkconfig.so as the executable conf. -# Note: Shared libraries consisting of C++ files are not supported - __hostprogs := $(sort $(hostprogs-y) $(hostprogs-m)) # C code # Executables compiled from a single .c file -host-csingle := $(foreach m,$(__hostprogs),$(if $($(m)-objs),,$(m))) +host-csingle := $(foreach m,$(__hostprogs), \ + $(if $($(m)-objs)$($(m)-cxxobjs),,$(m))) # C executables linked based on several .o files host-cmulti := $(foreach m,$(__hostprogs),\ @@ -44,33 +35,17 @@ host-cmulti := $(foreach m,$(__hostprogs),\ host-cobjs := $(sort $(foreach m,$(__hostprogs),$($(m)-objs))) # C++ code -# C++ executables compiled from at least on .cc file +# C++ executables compiled from at least one .cc file # and zero or more .c files host-cxxmulti := $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m))) # C++ Object (.o) files compiled from .cc files host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs))) -# Shared libaries (only .c supported) -# Shared libraries (.so) - all .so files referenced in "xxx-objs" -host-cshlib := $(sort $(filter %.so, $(host-cobjs))) -# Remove .so files from "xxx-objs" -host-cobjs := $(filter-out %.so,$(host-cobjs)) - -#Object (.o) files used by the shared libaries -host-cshobjs := $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs)))) - # output directory for programs/.o files -# hostprogs-y := tools/build may have been specified. Retrieve directory -host-objdirs := $(foreach f,$(__hostprogs), $(if $(dir $(f)),$(dir $(f)))) -# directory of .o files from prog-objs notation -host-objdirs += $(foreach f,$(host-cmulti), \ - $(foreach m,$($(f)-objs), \ - $(if $(dir $(m)),$(dir $(m))))) -# directory of .o files from prog-cxxobjs notation -host-objdirs += $(foreach f,$(host-cxxmulti), \ - $(foreach m,$($(f)-cxxobjs), \ - $(if $(dir $(m)),$(dir $(m))))) +# hostprogs-y := tools/build may have been specified. +# Retrieve also directory of .o files from prog-objs or prog-cxxobjs notation +host-objdirs := $(dir $(__hostprogs) $(host-cobjs) $(host-cxxobjs)) host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs)))) @@ -81,8 +56,6 @@ host-cmulti := $(addprefix $(obj)/,$(host-cmulti)) host-cobjs := $(addprefix $(obj)/,$(host-cobjs)) host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti)) host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs)) -host-cshlib := $(addprefix $(obj)/,$(host-cshlib)) -host-cshobjs := $(addprefix $(obj)/,$(host-cshobjs)) host-objdirs := $(addprefix $(obj)/,$(host-objdirs)) obj-dirs += $(host-objdirs) @@ -123,8 +96,9 @@ quiet_cmd_host-cmulti = HOSTLD $@ cmd_host-cmulti = $(HOSTCC) $(HOSTLDFLAGS) -o $@ \ $(addprefix $(obj)/,$($(@F)-objs)) \ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) -$(host-cmulti): $(obj)/%: $(host-cobjs) $(host-cshlib) FORCE +$(host-cmulti): FORCE $(call if_changed,host-cmulti) +$(call multi_depend, $(host-cmulti), , -objs) # Create .o file from a single .c file # host-cobjs -> .o @@ -140,8 +114,9 @@ quiet_cmd_host-cxxmulti = HOSTLD $@ $(foreach o,objs cxxobjs,\ $(addprefix $(obj)/,$($(@F)-$(o)))) \ $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) -$(host-cxxmulti): $(obj)/%: $(host-cobjs) $(host-cxxobjs) $(host-cshlib) FORCE +$(host-cxxmulti): FORCE $(call if_changed,host-cxxmulti) +$(call multi_depend, $(host-cxxmulti), , -objs -cxxobjs) # Create .o file from a single .cc (C++) file quiet_cmd_host-cxxobjs = HOSTCXX $@ @@ -149,21 +124,5 @@ quiet_cmd_host-cxxobjs = HOSTCXX $@ $(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE $(call if_changed_dep,host-cxxobjs) -# Compile .c file, create position independent .o file -# host-cshobjs -> .o -quiet_cmd_host-cshobjs = HOSTCC -fPIC $@ - cmd_host-cshobjs = $(HOSTCC) $(hostc_flags) -fPIC -c -o $@ $< -$(host-cshobjs): $(obj)/%.o: $(src)/%.c FORCE - $(call if_changed_dep,host-cshobjs) - -# Link a shared library, based on position independent .o files -# *.o -> .so shared library (host-cshlib) -quiet_cmd_host-cshlib = HOSTLLD -shared $@ - cmd_host-cshlib = $(HOSTCC) $(HOSTLDFLAGS) -shared -o $@ \ - $(addprefix $(obj)/,$($(@F:.so=-objs))) \ - $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) -$(host-cshlib): $(obj)/%: $(host-cshobjs) FORCE - $(call if_changed,host-cshlib) - targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\ - $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs) + $(host-cxxmulti) $(host-cxxobjs) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 072abaafb1..9d1383a38f 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -160,6 +160,15 @@ dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ modname-multi = $(sort $(foreach m,$(multi-used),\ $(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs)) $($(m:.o=-y))),$(m:.o=)))) +# Useful for describing the dependency of composite objects +# Usage: +# $(call multi_depend, multi_used_targets, suffix_to_remove, suffix_to_add) +define multi_depend +$(foreach m, $(notdir $1), \ + $(eval $(obj)/$m: \ + $(addprefix $(obj)/, $(foreach s, $3, $($(m:%$(strip $2)=%$(s))))))) +endef + ifdef REGENERATE_PARSERS # GPERF diff --git a/scripts/binutils-version.sh b/scripts/binutils-version.sh index d4d9eb4361..d4d9eb4361 100644..100755 --- a/scripts/binutils-version.sh +++ b/scripts/binutils-version.sh diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh index e8c94d390b..e8c94d390b 100644..100755 --- a/scripts/dtc-version.sh +++ b/scripts/dtc-version.sh diff --git a/scripts/gcc-stack-usage.sh b/scripts/gcc-stack-usage.sh index 27ac928969..27ac928969 100644..100755 --- a/scripts/gcc-stack-usage.sh +++ b/scripts/gcc-stack-usage.sh diff --git a/scripts/gcc-version.sh b/scripts/gcc-version.sh index debecb5561..debecb5561 100644..100755 --- a/scripts/gcc-version.sh +++ b/scripts/gcc-version.sh diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile index 9c4d2412fb..349f77038e 100644 --- a/scripts/kconfig/Makefile +++ b/scripts/kconfig/Makefile @@ -104,6 +104,23 @@ endif %_defconfig: $(obj)/conf $(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig) +configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config) + +define mergeconfig +$(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target)) +$(if $(call configfiles,$(1)),, $(error No configuration exists for this target on this architecture)) +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(call configfiles,$(1)) +$(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig +endef + +PHONY += kvmconfig +kvmconfig: + $(call mergeconfig,kvm_guest) + +PHONY += tinyconfig +tinyconfig: allnoconfig + $(call mergeconfig,tiny) + # Help text used by make help help: @echo ' config - Update current config utilising a line-oriented program' @@ -124,6 +141,8 @@ help: @echo ' randconfig - New config with random answer to all options' @echo ' listnewconfig - List new options' @echo ' olddefconfig - Same as silentoldconfig but sets new symbols to their default value' +# @echo ' kvmconfig - Enable additional options for guest kernel support' +# @echo ' tinyconfig - Configure the tiniest possible kernel' # lxdialog stuff check-lxdialog := $(srctree)/$(src)/lxdialog/check-lxdialog.sh @@ -157,39 +176,10 @@ qconf-cxxobjs := qconf.o qconf-objs := zconf.tab.o gconf-objs := gconf.o zconf.tab.o -hostprogs-y := conf - -ifeq ($(MAKECMDGOALS),nconfig) - hostprogs-y += nconf -endif - -ifeq ($(MAKECMDGOALS),menuconfig) - hostprogs-y += mconf -endif - -ifeq ($(MAKECMDGOALS),update-po-config) - hostprogs-y += kxgettext -endif - -ifeq ($(MAKECMDGOALS),xconfig) - qconf-target := 1 -endif -ifeq ($(MAKECMDGOALS),gconfig) - gconf-target := 1 -endif - - -ifeq ($(qconf-target),1) - hostprogs-y += qconf -endif - -ifeq ($(gconf-target),1) - hostprogs-y += gconf -endif +hostprogs-y := conf nconf mconf kxgettext qconf gconf clean-files := qconf.moc .tmp_qtcheck .tmp_gtkcheck clean-files += zconf.tab.c zconf.lex.c zconf.hash.c gconf.glade.h -clean-files += mconf qconf gconf nconf clean-files += config.pot linux.pot # Check that we have the required ncurses stuff installed for lxdialog (menuconfig) @@ -220,11 +210,12 @@ HOSTCFLAGS_gconf.o = `pkg-config --cflags gtk+-2.0 gmodule-2.0 libglade-2.0` \ HOSTLOADLIBES_mconf = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC)) HOSTLOADLIBES_nconf = $(shell \ - pkg-config --libs menu panel ncurses 2>/dev/null \ + pkg-config --libs menuw panelw ncursesw 2>/dev/null \ + || pkg-config --libs menu panel ncurses 2>/dev/null \ || echo "-lmenu -lpanel -lncurses" ) $(obj)/qconf.o: $(obj)/.tmp_qtcheck -ifeq ($(qconf-target),1) +ifeq ($(MAKECMDGOALS),xconfig) $(obj)/.tmp_qtcheck: $(src)/Makefile -include $(obj)/.tmp_qtcheck @@ -281,7 +272,7 @@ endif $(obj)/gconf.o: $(obj)/.tmp_gtkcheck -ifeq ($(gconf-target),1) +ifeq ($(MAKECMDGOALS),gconfig) -include $(obj)/.tmp_gtkcheck # GTK needs some extra effort, too... diff --git a/scripts/kconfig/lxdialog/check-lxdialog.sh b/scripts/kconfig/lxdialog/check-lxdialog.sh index 9d2a4c585e..9d2a4c585e 100644..100755 --- a/scripts/kconfig/lxdialog/check-lxdialog.sh +++ b/scripts/kconfig/lxdialog/check-lxdialog.sh diff --git a/scripts/kconfig/lxdialog/dialog.h b/scripts/kconfig/lxdialog/dialog.h index b4343d3849..fcffd5b41f 100644 --- a/scripts/kconfig/lxdialog/dialog.h +++ b/scripts/kconfig/lxdialog/dialog.h @@ -170,7 +170,7 @@ char item_tag(void); /* item list manipulation for lxdialog use */ #define MAXITEMSTR 200 struct dialog_item { - char str[MAXITEMSTR]; /* promtp displayed */ + char str[MAXITEMSTR]; /* prompt displayed */ char tag; void *data; /* pointer to menu item - used by menubox+checklist */ int selected; /* Set to 1 by dialog_*() function if selected. */ diff --git a/scripts/kconfig/streamline_config.pl b/scripts/kconfig/streamline_config.pl index 9cb8522d8d..9cb8522d8d 100644..100755 --- a/scripts/kconfig/streamline_config.pl +++ b/scripts/kconfig/streamline_config.pl diff --git a/scripts/kernel-doc b/scripts/kernel-doc index c881b8cb3e..08a6c76845 100755 --- a/scripts/kernel-doc +++ b/scripts/kernel-doc @@ -2073,6 +2073,7 @@ sub check_return_section { sub dump_function($$) { my $prototype = shift; my $file = shift; + my $noret = 0; $prototype =~ s/^static +//; $prototype =~ s/^extern +//; @@ -2084,9 +2085,10 @@ sub dump_function($$) { $prototype =~ s/^noinline +//; $prototype =~ s/__init +//; $prototype =~ s/__init_or_module +//; + $prototype =~ s/__meminit +//; $prototype =~ s/__must_check +//; $prototype =~ s/__weak +//; - $prototype =~ s/^#\s*define\s+//; #ak added + my $define = $prototype =~ s/^#\s*define\s+//; #ak added $prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//; # Yes, this truly is vile. We are looking for: @@ -2105,7 +2107,15 @@ sub dump_function($$) { # - atomic_set (macro) # - pci_match_device, __copy_to_user (long return type) - if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || + if ($define && $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s+/) { + # This is an object-like macro, it has no return type and no parameter + # list. + # Function-like macros are not allowed to have spaces between + # declaration_name and opening parenthesis (notice the \s+). + $return_type = $1; + $declaration_name = $2; + $noret = 1; + } elsif ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || $prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ || @@ -2140,7 +2150,7 @@ sub dump_function($$) { # of warnings goes sufficiently down, the check is only performed in # verbose mode. # TODO: always perform the check. - if ($verbose) { + if ($verbose && !$noret) { check_return_section($file, $declaration_name, $return_type); } diff --git a/scripts/mkmakefile b/scripts/mkmakefile index 84af27bf0f..84af27bf0f 100644..100755 --- a/scripts/mkmakefile +++ b/scripts/mkmakefile diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index 70f3a5df6f..70f3a5df6f 100644..100755 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh diff --git a/test/command_ut.c b/test/command_ut.c index e136075541..926573a395 100644 --- a/test/command_ut.c +++ b/test/command_ut.c @@ -188,6 +188,11 @@ static int do_ut_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif #endif + assert(run_command("", 0) == 0); + assert(run_command(" ", 0) == 0); + + assert(run_command("'", 0) == 1); + printf("%s: Everything went swimmingly\n", __func__); return 0; } diff --git a/tools/Makefile b/tools/Makefile index 3b95964fd1..c422b76054 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -157,7 +157,7 @@ HOSTCFLAGS_sha256.o := -pedantic #HOSTCFLAGS_mpc86x_clk.o := -pedantic quiet_cmd_wrap = WRAP $@ -cmd_wrap = echo "\#include <$(srctree)/$(patsubst $(obj)/%,%,$@)>" >$@ +cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@ $(obj)/lib/%.c $(obj)/common/%.c: $(call cmd,wrap) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 30d5b037f0..1173eea782 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -125,7 +125,7 @@ static int get_config (char *); #endif static inline ulong getenvsize (void) { - ulong rc = CUR_ENVSIZE - sizeof(long); + ulong rc = CUR_ENVSIZE - sizeof(uint32_t); if (HaveRedundEnv) rc -= sizeof (char); diff --git a/tools/mkenvimage.c b/tools/mkenvimage.c index bbd3041e36..6971b91314 100644 --- a/tools/mkenvimage.c +++ b/tools/mkenvimage.c @@ -37,6 +37,8 @@ static void usage(const char *exec_name) "\t\tkey1=value1\n" "\t\tkey2=value2\n" "\t\t...\n" + "\tEmpty lines are skipped, and lines with a # in the first\n" + "\tcolumn are treated as comments (also skipped).\n" "\t-r : the environment has multiple copies in flash\n" "\t-b : the target is big endian (default is little endian)\n" "\t-p <byte> : fill the image with <byte> bytes instead of 0xff bytes\n" @@ -221,10 +223,9 @@ int main(int argc, char **argv) /* Replace newlines separating variables with \0 */ for (fp = 0, ep = 0 ; fp < filesize ; fp++) { if (filebuf[fp] == '\n') { - if (ep == 0) { + if (fp == 0 || filebuf[fp-1] == '\n') { /* - * Newlines at the beginning of the file ? - * Ignore them. + * Skip empty lines. */ continue; } else if (filebuf[fp-1] == '\\') { @@ -240,6 +241,10 @@ int main(int argc, char **argv) /* End of a variable */ envptr[ep++] = '\0'; } + } else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') { + /* Comment, skip the line. */ + while (++fp < filesize && filebuf[fp] != '\n') + continue; } else { envptr[ep++] = filebuf[fp]; } |
