diff options
| -rw-r--r-- | arch/arm/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 212 | ||||
| -rw-r--r-- | configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 41 | ||||
| -rw-r--r-- | include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h | 24 |
4 files changed, 278 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e76f56b22e..ed897cf52a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-zcu102-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ + zynqmp-zc1751-xm018-dc4.dtb \ zynqmp-zc1751-xm019-dc5.dtb dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \ am335x-evmsk.dtb \ diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts new file mode 100644 index 0000000000..03f1ad7934 --- /dev/null +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -0,0 +1,212 @@ +/* + * dts file for Xilinx ZynqMP zc1751-xm018-dc4 + * + * (C) Copyright 2015 - 2016, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" + +/ { + model = "ZynqMP zc1751-xm018-dc4"; + compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; + + aliases { + can0 = &can0; + can1 = &can1; + ethernet0 = &gem0; + ethernet1 = &gem1; + ethernet2 = &gem2; + ethernet3 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &qspi; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; + +&gem0 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ + reg = <0>; + }; + ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ + reg = <7>; + }; + ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ + reg = <3>; + }; + ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ + reg = <8>; + }; +}; + +&gem1 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 91]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy7>; +}; + +&gem2 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 92]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy3>; +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 93]; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy8>; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig new file mode 100644 index 0000000000..f7f3822d69 --- /dev/null +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4" +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_DM_MMC=y +CONFIG_ZYNQ_SDHCI=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h new file mode 100644 index 0000000000..fd2ec6a775 --- /dev/null +++ b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h @@ -0,0 +1,24 @@ +/* + * Configuration for Xilinx ZynqMP zc1751 XM018 DC4 + * + * (C) Copyright 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H +#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H + +#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm018 dc4" + +#define CONFIG_KERNEL_FDT_OFST_SIZE \ + "kernel_offset=0x400000\0" \ + "fdt_offset=0x2400000\0" \ + "kernel_size=0x2000000\0" \ + "fdt_size=0x80000\0" \ + "board=zc1751-dc4\0" + +#include <configs/xilinx_zynqmp.h> + +#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */ |
