diff options
| -rw-r--r-- | board/amcc/luan/init.S | 170 | ||||
| -rw-r--r-- | board/amcc/luan/luan.c | 99 | ||||
| -rw-r--r-- | board/amcc/luan/u-boot.lds | 13 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 2 | ||||
| -rw-r--r-- | include/configs/luan.h | 18 |
5 files changed, 62 insertions, 240 deletions
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S index 7830ebdfa6..d5ee117dfa 100644 --- a/board/amcc/luan/init.S +++ b/board/amcc/luan/init.S @@ -1,73 +1,31 @@ /* -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ #include <ppc_asm.tmpl> #include <config.h> - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - +#include <asm-ppc/mmu.h> /************************************************************************** * TLB TABLE @@ -80,53 +38,37 @@ * *************************************************************************/ - .section .bootpg,"ax" - .globl tlbtab + .section .bootpg,"ax" + .globl tlbtab tlbtab: - tlbtab_start - -#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */ - /* large flash */ - tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) - - tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) -#else /* else booting from small flash */ - tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - - tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) - tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) -#endif - - tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I ) - -#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */ - tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) -#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */ - tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) -#elif (CFG_SMALL_FLASH == 0xfff00000) - tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) -#else - #error DONT KNOW SRAM LOCATION -#endif - - /* internal ram (l2 cache) */ - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I ) - - /* peripherals at f0000000 */ - tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I ) - - /* PCI */ -#if (CONFIG_COMMANDS & CFG_CMD_PCI) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I ) -#endif - tlbtab_end + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G) + + tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + + /* internal ram (l2 cache) */ + tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I) + + /* peripherals at f0000000 */ + tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I) + + /* PCI */ + tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I) + tlbtab_end diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 06a57f6c4a..778aafc766 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -106,105 +106,6 @@ int checkboard(void) /************************************************************************* - * long int fixed_sdram() - * - ************************************************************************/ -static long int fixed_sdram(void) -{ /* DDR2 init from BDI2000 script */ - mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */ - mtdcr( 0x11, 0x84000000 ); - mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */ - mtdcr( 0x11, 0x2D122000 ); - mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */ - mtdcr( 0x11, 0x00800026 ); - mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */ - mtdcr( 0x11, 0x82000800 ); - mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */ - mtdcr( 0x11, 0x80000000 ); - mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */ - mtdcr( 0x11, 0x00000201 ); - mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */ - mtdcr( 0x11, 0x00000201 ); - mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */ - mtdcr( 0x11, 0x08200000 ); - mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */ - mtdcr( 0x11, 0x80201000 ); - mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */ - mtdcr( 0x11, 0x42103242 ); - mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */ - mtdcr( 0x11, 0x0C100D14 ); - mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */ - mtdcr( 0x11, 0x00000642 ); - mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */ - mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */ - - mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */ - mtdcr( 0x11, 0x81b80000 ); - mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */ - mtdcr( 0x11, 0x82100400 ); - mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */ - mtdcr( 0x11, 0x80820000 ); - mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */ - mtdcr( 0x11, 0x80830000 ); - mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */ - mtdcr( 0x11, 0x80810000 ); - mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */ - mtdcr( 0x11, 0x80800542 ); - mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */ - mtdcr( 0x11, 0x82100400 ); - mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */ - mtdcr( 0x11, 0x99080000 ); - mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */ - mtdcr( 0x11, 0x80800442 ); - mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */ - mtdcr( 0x11, 0x80810380 ); - mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */ - mtdcr( 0x11, 0x80810000 ); - udelay( 10*1000 ); - - mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */ - mtdcr( 0x11, 0x28000000 ); /* set DC_EN */ - udelay( 100*1000 ); - - mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */ - mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */ - - mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */ - mtdcr( 0x11, 0x00000000 ); - mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */ - mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */ - mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */ - mtdcr( 0x11, 0x00000200 ); - - return 512 << 20; -} - - -/************************************************************************* - * long int initdram - * - ************************************************************************/ -long int initdram( int board_type ) -{ - long dram_size = 0; - -#if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); -#else - dram_size = fixed_sdram (); -#endif - - return dram_size; -} - - -/************************************************************************* * int testdram() * ************************************************************************/ diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds index d122f499f1..72ce6855d7 100644 --- a/board/amcc/luan/u-boot.lds +++ b/board/amcc/luan/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/luan/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 24b30dfe71..1301cd26d8 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1361,7 +1361,7 @@ ppcSync: relocate_code: #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) * to speed up the boot process. Now this cache needs to be disabled. diff --git a/include/configs/luan.h b/include/configs/luan.h index 5c9d208feb..9c8769b200 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -37,8 +37,9 @@ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -132,10 +133,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */ -#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */ -#define IIC0_DIMM0_ADDR 0x52 -#define IIC0_DIMM1_ADDR 0x53 +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ +#undef CONFIG_DDR_ECC /* no ECC support for now */ /*----------------------------------------------------------------------- * I2C @@ -206,11 +206,6 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* needed for NetConsole */ -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - #ifdef DEBUG #define CONFIG_PANIC_HANG #else @@ -219,9 +214,7 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ CFG_CMD_ELF | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ @@ -232,7 +225,6 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ - CFG_CMD_SETGETDCR | \ CFG_CMD_SDRAM | \ 0) |
