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authorDinh Nguyen <>2012-06-08 05:26:52 +0000
committerJoe Hershberger <>2012-07-11 13:15:31 -0500
commit66f119e50cc854695a3709c67bf6a6c8ef60f6bc (patch)
tree791c774f4a8c2152f6df5d95e5f81f69341fa76c /net
parentc59ab0921fcc99db87efa02022f4ca39dad975b2 (diff)
net/designware: Consecutive writes to the same register to be avoided
This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay. According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required: DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1. GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3. Signed-off-by: Dinh Nguyen <> Reviewed-by: Matthew Gerlach <> Acked-by: Amit Virdi <>
Diffstat (limited to 'net')
0 files changed, 0 insertions, 0 deletions
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