path: root/nand_spl/nand_boot_fsl_elbc.c
diff options
authorBecky Bruce <>2010-06-17 11:37:20 -0500
committerKumar Gala <>2010-07-16 10:55:09 -0500
commitf51cdaf19141151ce2b40d562a468605340f2315 (patch)
tree60b51af79796f061d119f2839d101f9584964dfc /nand_spl/nand_boot_fsl_elbc.c
parent0914f4832887341ee073d2d2bfbada69a6872548 (diff)
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <> Acked-by: Kim Phillips <> Signed-off-by: Kumar Gala <>
Diffstat (limited to 'nand_spl/nand_boot_fsl_elbc.c')
1 files changed, 2 insertions, 2 deletions
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index ff47d55311..9547d44238 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -32,7 +32,7 @@
static void nand_wait(void)
- fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
for (;;) {
uint32_t status = in_be32(&regs->ltesr);
@@ -49,7 +49,7 @@ static void nand_wait(void)
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
- fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
int block_shift = large ? 17 : 14;
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