Merge branch 'master' of git://git.denx.de/u-boot-arm

5 files changed, 0 insertions, 901 deletions

diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h
deleted file mode 100644
index 3f49c6f0b1..0000000000
--- a/include/configs/ns9750dev.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- * Markus Pietrek <mpietrek@fsforth.de>
- *
- * Configuation settings for the NetSilicon NS9750 DevBoard
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
-#define	CONFIG_NS9750		1	/* in an NetSilicon NS9750 SoC     */
-#define CONFIG_NS9750DEV	1	/* on an NetSilicon NS9750 DevBoard  */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	324403200 /* Don't use PLL. SW11-4 off */
-
-#define CPU_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/2)
-#define AHB_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/4)
-#define BBUS_CLK_FREQ		(CONFIG_SYS_CLK_FREQ/8)
-
-/*@TODO #define CONFIG_STATUS_LED*/
-#define CONFIG_USE_IRQ
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_NS9750_UART		1	/* use on-chip UART */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX          1		/* Port B */
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY	3
-/*#define CONFIG_BOOTARGS	"root=ramfs devfs=mount console=ttySA0,9600" */
-
-#define CONFIG_ETHADDR		00:04:f3:ff:ff:fb /*@TODO unset */
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		192.168.42.30
-#define CONFIG_SERVERIP		192.168.42.1
-
-/*#define CONFIG_BOOTFILE	"elinos-lart" */
-/*#define CONFIG_BOOTCOMMAND	"tftp; bootm" */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"NS9750DEV # "	/* Monitor Command Prompt	*/
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x00780000	/* 7,5 MB in DRAM	*/ /* @TODO */
-
-#define	CONFIG_SYS_LOAD_ADDR		0x00600000	/* default load address	*/ /* @TODO */
-
-#define	CONFIG_SYS_HZ			(CPU_CLK_FREQ/64)
-
-#define NS9750_ETH_PHY_ADDRESS	(0x0000)
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-/* TODO */
-#define CONFIG_NR_DRAM_BANKS	2	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x00800000 /* 8 MB */
-#define PHYS_SDRAM_2		0x10000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_2_SIZE	0x00800000 /* 8 MB */
-
-#define PHYS_FLASH_1		0x50000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-/* @TODO*/
-#define CONFIG_AMD_LV400	1	/* uncomment this if you have a LV400 flash */
-#if 0
-#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
-#endif
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* @TODO */
-/*#define	CONFIG_ENV_IS_IN_FLASH	1*/
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
-
-#ifdef CONFIG_STATUS_LED
-
-extern void __led_init(led_id_t mask, int state);
-extern void __led_toggle(led_id_t mask);
-extern void __led_set(led_id_t mask, int state);
-
-#endif /* CONFIG_STATUS_LED */
-
-#endif	/* __CONFIG_H */
diff --git a/include/ns9750_bbus.h b/include/ns9750_bbus.h
deleted file mode 100644
index 9485338f73..0000000000
--- a/include/ns9750_bbus.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for BBus usage
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_BBUS_H
-#define FS_NS9750_BBUS_H
-
-#define NS9750_BBUS_MODULE_BASE		(0x90600000)
-
-#define get_bbus_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
-
-/* We have support for 50 GPIO pins */
-
-#define get_gpio_cfg_reg_addr(pin) \
-	get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
-
-/* To Read/Modify/Write a pin configuration register, use it like
-   set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
-   They should be wrapped by cli()/sti() */
-#define set_gpio_cfg_reg_val(pin,cfg) \
-	*get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
-					~NS9750_GPIO_CFG_MASK((pin))) |\
-				NS9750_GPIO_CFG_VAL((pin),(cfg));
-
-#define NS9750_GPIO_CFG_MASK(pin)	(NS9750_GPIO_CFG_VAL(pin, \
-					 NS9750_GPIO_CFG_MA))
-#define NS9750_GPIO_CFG_VAL(pin,cfg)	((cfg) << (((pin) % 8) * 4))
-
-#define NS9750_GPIO_CFG_MA		(0x0F)
-#define NS9750_GPIO_CFG_INPUT		(0x00)
-#define NS9750_GPIO_CFG_OUTPUT		(0x08)
-#define NS9750_GPIO_CFG_FUNC_GPIO	(0x03)
-#define NS9750_GPIO_CFG_FUNC_2		(0x02)
-#define NS9750_GPIO_CFG_FUNC_1		(0x01)
-#define NS9750_GPIO_CFG_FUNC_0		(0x00)
-
-/* the register addresses */
-
-#define NS9750_BBUS_MASTER_RESET	(0x00)
-#define NS9750_BBUS_GPIO_CFG_BASE	(0x10)
-#define NS9750_BBUS_GPIO_CTRL_BASE	(0x30)
-#define NS9750_BBUS_GPIO_STAT_BASE	(0x40)
-#define NS9750_BBUS_MONITOR		(0x50)
-#define NS9750_BBUS_DMA_INT_STAT	(0x60)
-#define NS9750_BBUS_DMA_INT_ENABLE	(0x64)
-#define NS9750_BBUS_USB_CFG		(0x70)
-#define NS9750_BBUS_ENDIAN_CFG		(0x80)
-#define NS9750_BBUS_ARM_WAKE_UP		(0x90)
-
-/* register bit fields */
-
-#define NS9750_BBUS_MASTER_RESET_UTIL	(0x00000100)
-#define NS9750_BBUS_MASTER_RESET_I2C	(0x00000080)
-#define NS9750_BBUS_MASTER_RESET_1284	(0x00000040)
-#define NS9750_BBUS_MASTER_RESET_SER4	(0x00000020)
-#define NS9750_BBUS_MASTER_RESET_SER3	(0x00000010)
-#define NS9750_BBUS_MASTER_RESET_SER2	(0x00000008)
-#define NS9750_BBUS_MASTER_RESET_SER1	(0x00000004)
-#define NS9750_BBUS_MASTER_RESET_USB	(0x00000002)
-#define NS9750_BBUS_MASTER_RESET_DMA	(0x00000001)
-
-/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
-
-#define NS9750_BBUS_DMA_INT_BINT16	(0x00010000)
-#define NS9750_BBUS_DMA_INT_BINT15	(0x00008000)
-#define NS9750_BBUS_DMA_INT_BINT14	(0x00004000)
-#define NS9750_BBUS_DMA_INT_BINT13	(0x00002000)
-#define NS9750_BBUS_DMA_INT_BINT12	(0x00001000)
-#define NS9750_BBUS_DMA_INT_BINT11	(0x00000800)
-#define NS9750_BBUS_DMA_INT_BINT10	(0x00000400)
-#define NS9750_BBUS_DMA_INT_BINT9	(0x00000200)
-#define NS9750_BBUS_DMA_INT_BINT8	(0x00000100)
-#define NS9750_BBUS_DMA_INT_BINT7	(0x00000080)
-#define NS9750_BBUS_DMA_INT_BINT6	(0x00000040)
-#define NS9750_BBUS_DMA_INT_BINT5	(0x00000020)
-#define NS9750_BBUS_DMA_INT_BINT4	(0x00000010)
-#define NS9750_BBUS_DMA_INT_BINT3	(0x00000008)
-#define NS9750_BBUS_DMA_INT_BINT2	(0x00000004)
-#define NS9750_BBUS_DMA_INT_BINT1	(0x00000002)
-#define NS9750_BBUS_DMA_INT_BINT0	(0x00000001)
-
-#define NS9750_BBUS_USB_CFG_OUTEN	(0x00000008)
-#define NS9750_BBUS_USB_CFG_SPEED	(0x00000004)
-#define NS9750_BBUS_USB_CFG_CFG_MA	(0x00000003)
-#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
-#define NS9750_BBUS_USB_CFG_CFG_DEVICE	(0x00000002)
-#define NS9750_BBUS_USB_CFG_CFG_HOST	(0x00000001)
-#define NS9750_BBUS_USB_CFG_CFG_DIS	(0x00000000)
-
-#define NS9750_BBUS_ENDIAN_CFG_AHBM	(0x00001000)
-#define NS9750_BBUS_ENDIAN_CFG_I2C	(0x00000080)
-#define NS9750_BBUS_ENDIAN_CFG_IEEE1284	(0x00000040)
-#define NS9750_BBUS_ENDIAN_CFG_SER4	(0x00000020)
-#define NS9750_BBUS_ENDIAN_CFG_SER3	(0x00000010)
-#define NS9750_BBUS_ENDIAN_CFG_SER2	(0x00000008)
-#define NS9750_BBUS_ENDIAN_CFG_SER1	(0x00000004)
-#define NS9750_BBUS_ENDIAN_CFG_USB	(0x00000002)
-#define NS9750_BBUS_ENDIAN_CFG_DMA	(0x00000001)
-
-#endif /* FS_NS9750_BBUS_H */
diff --git a/include/ns9750_mem.h b/include/ns9750_mem.h
deleted file mode 100644
index 666e4127c8..0000000000
--- a/include/ns9750_mem.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_mem.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for Memory Control Module
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 5
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_MEM_H
-#define FS_NS9750_SYS_H
-
-#define NS9750_MEM_MODULE_BASE		(0xA0700000)
-
-#define get_mem_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_MEM_MODULE_BASE+(unsigned int) (c)))
-
-/* the register addresses */
-
-#define NS9750_MEM_CTRL			(0x0000)
-#define NS9750_MEM_STATUS		(0x0004)
-#define NS9750_MEM_CFG			(0x0008)
-#define NS9750_MEM_DYN_CTRL		(0x0020)
-#define NS9750_MEM_DYN_REFRESH		(0x0024)
-#define NS9750_MEM_DYN_READ_CFG		(0x0028)
-#define NS9750_MEM_DYN_TRP		(0x0030)
-#define NS9750_MEM_DYN_TRAS		(0x0034)
-#define NS9750_MEM_DYN_TSREX		(0x0038)
-#define NS9750_MEM_DYN_TAPR		(0x003C)
-#define NS9750_MEM_DYN_TDAL		(0x0040)
-#define NS9750_MEM_DYN_TWR		(0x0044)
-#define NS9750_MEM_DYN_TRC		(0x0048)
-#define NS9750_MEM_DYN_TRFC		(0x004C)
-#define NS9750_MEM_DYN_TXSR		(0x0050)
-#define NS9750_MEM_DYN_TRRD		(0x0054)
-#define NS9750_MEM_DYN_TMRD		(0x0058)
-#define NS9750_MEM_STAT_EXT_WAIT	(0x0080)
-#define NS9750_MEM_DYN_CFG_BASE		(0x0100)
-#define NS9750_MEM_DYN_RAS_CAS_BASE	(0x0104)
-#define NS9750_MEM_STAT_CFG_BASE	(0x0200)
-#define NS9750_MEM_STAT_WAIT_WEN_BASE	(0x0204)
-#define NS9750_MEM_STAT_WAIT_OEN_BASE	(0x0208)
-#define NS9750_MEM_STAT_WAIT_RD_BASE	(0x020C)
-#define NS9750_MEM_STAT_WAIT_PAGE_BASE	(0x0210)
-#define NS9750_MEM_STAT_WAIR_WR_BASE	(0x0214)
-#define NS9750_MEM_STAT_WAIT_TURN_BASE	(0x0218)
-
-/* the vectored register addresses */
-
-#define NS9750_MEM_DYN_CFG(c)		(NS9750_MEM_DYN_CFG_BASE + (c)*0x20)
-#define NS9750_MEM_DYN_RAS_CAS(c)	(NS9750_MEM_DYN_RAS_CAS_BASE + (c)*0x20)
-#define NS9750_MEM_STAT_CFG(c)		(NS9750_MEM_STAT_CFG_BASE + (c)*0x20)
-#define NS9750_MEM_STAT_WAIT_WEN(c)	(NS9750_MEM_STAT_WAIT_WEN_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_WAIT_OEN(c)	(NS9750_MEM_STAT_WAIT_OEN_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_RD(c)		(NS9750_MEM_STAT_WAIT_RD_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_PAGE(c)		(NS9750_MEM_STAT_WAIT_PAGE_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_WR(c)		(NS9750_MEM_STAT_WAIT_WR_BASE+(c)*0x20)
-#define NS9750_MEM_STAT_TURN(c)		(NS9750_MEM_STAT_WAIT_TURN_BASE+(c)*0x20)
-
-/* register bit fields */
-
-#define NS9750_MEM_CTRL_L		(0x00000004)
-#define NS9750_MEM_CTRL_M		(0x00000002)
-#define NS9750_MEM_CTRL_E		(0x00000001)
-
-#define NS9750_MEM_STAT_SA		(0x00000004)
-#define NS9750_MEM_STAT_S		(0x00000002)
-#define NS9750_MEM_STAT_B		(0x00000001)
-
-#define NS9750_MEM_CFG_CLK		(0x00000010)
-#define NS9750_MEM_CFG_N		(0x00000001)
-
-#define NS9750_MEM_DYN_CTRL_NRP		(0x00004000)
-#define NS9750_MEM_DYN_CTRL_DP		(0x00002000)
-#define NS9750_MEM_DYN_CTRL_I_MA	(0x00000180)
-#define NS9750_MEM_DYN_CTRL_I_NORMAL	(0x00000000)
-#define NS9750_MEM_DYN_CTRL_I_MODE	(0x00000080)
-#define NS9750_MEM_DYN_CTRL_I_PALL	(0x00000100)
-#define NS9750_MEM_DYN_CTRL_I_NOP	(0x00000180)
-#define NS9750_MEM_DYN_CTRL_SR		(0x00000002)
-#define NS9750_MEM_DYN_CTRL_CE		(0x00000001)
-
-
-#define NS9750_MEM_DYN_REFRESH_MA	(0x000007FF)
-
-#define NS9750_MEM_DYN_READ_CFG_MA	(0x00000003)
-#define NS9750_MEM_DYN_READ_CFG_DELAY0	(0x00000001)
-#define NS9750_MEM_DYN_READ_CFG_DELAY1  (0x00000002)
-#define NS9750_MEM_DYN_READ_CFG_DELAY2	(0x00000003)
-
-#define NS9750_MEM_DYN_TRP_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TRAS_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TSREX_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TAPR_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TDAL_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TWR_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TRC_MA		(0x0000001F)
-
-#define NS9750_MEM_DYN_TRFC_MA		(0x0000001F)
-
-#define NS9750_MEM_DYN_TXSR_MA		(0x0000001F)
-
-#define NS9750_MEM_DYN_TRRD_MA		(0x0000000F)
-
-#define NS9750_MEM_DYN_TMRD_MA		(0x0000000F)
-
-#define NS9750_MEM_STAT_EXTW_WAIT_MA	(0x0000003F)
-
-#define NS9750_MEM_DYN_CFG_P		(0x00100000)
-#define NS9750_MEM_DYN_CFG_BDMC		(0x00080000)
-#define NS9750_MEM_DYN_CFG_AM		(0x00004000)
-#define NS9750_MEM_DYN_CFG_AM_MA	(0x00001F80)
-#define NS9750_MEM_DYN_CFG_MD		(0x00000018)
-
-#define NS9750_MEM_DYN_RAS_CAS_CAS_MA	(0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_1	(0x00000100)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_2	(0x00000200)
-#define NS9750_MEM_DYN_RAS_CAS_CAS_3	(0x00000300)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_MA	(0x00000003)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_1	(0x00000001)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_2	(0x00000002)
-#define NS9750_MEM_DYN_RAS_CAS_RAS_3	(0x00000003)
-
-#define NS9750_MEM_STAT_CFG_PSMC	(0x00100000)
-#define NS9750_MEM_STAT_CFG_BSMC	(0x00080000)
-#define NS9750_MEM_STAT_CFG_EW		(0x00000100)
-#define NS9750_MEM_STAT_CFG_PB		(0x00000080)
-#define NS9750_MEM_STAT_CFG_PC		(0x00000040)
-#define NS9750_MEM_STAT_CFG_PM		(0x00000008)
-#define NS9750_MEM_STAT_CFG_MW_MA	(0x00000003)
-#define NS9750_MEM_STAT_CFG_MW_8	(0x00000000)
-#define NS9750_MEM_STAT_CFG_MW_16	(0x00000001)
-#define NS9750_MEM_STAT_CFG_MW_32	(0x00000002)
-
-#define NS9750_MEM_STAT_WAIT_WEN_MA	(0x0000000F)
-
-#define NS9750_MEM_STAT_WAIT_OEN_MA	(0x0000000F)
-
-#define NS9750_MEM_STAT_WAIT_RD_MA	(0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_PAGE_MA	(0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_WR_MA	(0x0000001F)
-
-#define NS9750_MEM_STAT_WAIT_TURN_MA	(0x0000000F)
-
-
-#endif /* FS_NS9750_MEM_H */
diff --git a/include/ns9750_ser.h b/include/ns9750_ser.h
deleted file mode 100644
index b5c297e436..0000000000
--- a/include/ns9750_ser.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_ser.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @References: [1] NS9750 Hardware Reference, December 2003
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_SER_H
-#define FS_NS9750_SER_H
-
-#define NS9750_SER_MODULE_BASE		(0x90200000)
-
-#define get_ser_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_SER_MODULE_BASE+(unsigned int) (c)))
-
-#define get_ser_reg_addr_channel(reg,chan) \
-	get_ser_reg_addr((reg)+(((chan)<2)?0:0x00100000)+(((chan)&1)?0x40:0))
-
-/* the register addresses */
-
-#define NS9750_SER_CTRL_A		(0x00)
-#define NS9750_SER_CTRL_B		(0x04)
-#define NS9750_SER_STAT_A		(0x08)
-#define NS9750_SER_BITRATE		(0x0C)
-#define NS9750_SER_FIFO			(0x10)
-#define NS9750_SER_RX_BUF_TIMER		(0x14)
-#define NS9750_SER_RX_CHAR_TIMER	(0x18)
-#define NS9750_SER_RX_MATCH		(0x1C)
-#define NS9750_SER_RX_MATCH_MASK	(0x20)
-#define NS9750_SER_FLOW_CTRL		(0x34)
-#define NS9750_SER_FLOW_CTRL_FORCE	(0x38)
-
-/* register bit fields */
-
-/* control A register */
-
-#define NS9750_SER_CTRL_A_CE		(0x80000000)
-#define NS9750_SER_CTRL_A_BRK		(0x40000000)
-#define NS9750_SER_CTRL_A_STICKP	(0x20000000)
-#define NS9750_SER_CTRL_A_EPS		(0x10000000)
-#define NS9750_SER_CTRL_A_PE		(0x08000000)
-#define NS9750_SER_CTRL_A_STOP		(0x04000000)
-#define NS9750_SER_CTRL_A_WLS_MA	(0x03000000)
-#define NS9750_SER_CTRL_A_WLS_5		(0x00000000)
-#define NS9750_SER_CTRL_A_WLS_6		(0x01000000)
-#define NS9750_SER_CTRL_A_WLS_7		(0x02000000)
-#define NS9750_SER_CTRL_A_WLS_8		(0x03000000)
-#define NS9750_SER_CTRL_A_CTSTX		(0x00800000)
-#define NS9750_SER_CTRL_A_RTSRX		(0x00400000)
-#define NS9750_SER_CTRL_A_RL		(0x00200000)
-#define NS9750_SER_CTRL_A_LL		(0x00100000)
-#define NS9750_SER_CTRL_A_RES		(0x000CF000)
-#define NS9750_SER_CTRL_A_DTR		(0x00020000)
-#define NS9750_SER_CTRL_A_RTS		(0x00010000)
-#define NS9750_SER_CTRL_A_RIE_MA	(0x00000E00)
-#define NS9750_SER_CTRL_A_ERXDMA	(0x00000100)
-#define NS9750_SER_CTRL_A_RIC_MA	(0x000000E0)
-#define NS9750_SER_CTRL_A_TIC_MA	(0x0000001E)
-#define NS9750_SER_CTRL_A_ETXDMA	(0x00000001)
-
-/* control B register */
-
-#define NS9750_SER_CTRL_B_RDM1		(0x80000000)
-#define NS9750_SER_CTRL_B_RDM2		(0x40000000)
-#define NS9750_SER_CTRL_B_RDM3		(0x20000000)
-#define NS9750_SER_CTRL_B_RDM4		(0x10000000)
-#define NS9750_SER_CTRL_B_RBGT		(0x08000000)
-#define NS9750_SER_CTRL_B_RCGT		(0x04000000)
-#define NS9750_SER_CTRL_B_MODE_MA	(0x00300000)
-#define NS9750_SER_CTRL_B_MODE_UART	(0x00000000)
-#define NS9750_SER_CTRL_B_MODE_HDLC	(0x00100000)
-#define NS9750_SER_CTRL_B_MODE_SPI_M	(0x00200000)
-#define NS9750_SER_CTRL_B_MODE_SPI_S	(0x00300000)
-#define NS9750_SER_CTRL_B_BITORDR	(0x00080000)
-#define NS9750_SER_CTRL_B_RES		(0x0007703F)
-#define NS9750_SER_CTRL_B_RTSTX		(0x00008000)
-#define NS9750_SER_CTRL_B_ENDEC_MA	(0x00000FC0)
-
-/* status A register */
-
-#define NS9750_SER_STAT_A_MATCH1	(0x80000000)
-#define NS9750_SER_STAT_A_MATCH2	(0x40000000)
-#define NS9750_SER_STAT_A_MATCH3	(0x20000000)
-#define NS9750_SER_STAT_A_MATCH4	(0x10000000)
-#define NS9750_SER_STAT_A_BGAP		(0x08000000)
-#define NS9750_SER_STAT_A_CGAP		(0x04000000)
-#define NS9750_SER_STAT_A_RXFDB_MA	(0x00300000)
-#define NS9750_SER_STAT_A_RXFDB_FULL	(0x00000000)
-#define NS9750_SER_STAT_A_RXFDB_1	(0x00100000)
-#define NS9750_SER_STAT_A_RXFDB_2	(0x00200000)
-#define NS9750_SER_STAT_A_RXFDB_3	(0x00300000)
-#define NS9750_SER_STAT_A_DCD		(0x00080000)
-#define NS9750_SER_STAT_A_RI		(0x00040000)
-#define NS9750_SER_STAT_A_DSR		(0x00020000)
-#define NS9750_SER_STAT_A_CTS		(0x00010000)
-#define NS9750_SER_STAT_A_RBRK		(0x00008000)
-#define NS9750_SER_STAT_A_RFE		(0x00004000)
-#define NS9750_SER_STAT_A_RPE		(0x00002000)
-#define NS9750_SER_STAT_A_ROVER		(0x00001000)
-#define NS9750_SER_STAT_A_RRDY		(0x00000800)
-#define NS9750_SER_STAT_A_RHALF		(0x00000400)
-#define NS9750_SER_STAT_A_RBC		(0x00000200)
-#define NS9750_SER_STAT_A_RFULL		(0x00000100)
-#define NS9750_SER_STAT_A_DCDI		(0x00000080)
-#define NS9750_SER_STAT_A_RII		(0x00000040)
-#define NS9750_SER_STAT_A_DSRI		(0x00000020)
-#define NS9750_SER_STAT_A_CTSI		(0x00000010)
-#define NS9750_SER_STAT_A_TRDY		(0x00000008)
-#define NS9750_SER_STAT_A_THALF		(0x00000004)
-#define NS9750_SER_STAT_A_TBC		(0x00000002)
-#define NS9750_SER_STAT_A_TEMPTY	(0x00000001)
-
-#define NS9750_SER_STAT_A_RX_COND_ERR ( NS9750_SER_STAT_A_RFE | \
-				        NS9750_SER_STAT_A_ROVER | \
-				        NS9750_SER_STAT_A_RPE )
-#define NS9750_SER_STAT_A_RX_COND_ALL ( NS9750_SER_STAT_A_RX_COND_ERR | \
-				        NS9750_SER_STAT_A_RBRK | \
-				        NS9750_SER_STAT_A_RRDY | \
-					NS9750_SER_STAT_A_RHALF | \
-					NS9750_SER_STAT_A_RBC | \
-					NS9750_SER_STAT_A_DCDI | \
-					NS9750_SER_STAT_A_RII | \
-					NS9750_SER_STAT_A_DSRI | \
-					NS9750_SER_STAT_A_CTSI )
-#define NS9750_SER_STAT_A_TX_COND_ALL ( NS9750_SER_STAT_A_TRDY | \
-				        NS9750_SER_STAT_A_THALF | \
-				        NS9750_SER_STAT_A_TBC | \
-					NS9750_SER_STAT_A_TEMPTY )
-/* bit rate register */
-
-#define NS9750_SER_BITRATE_EBIT		 (0x80000000)
-#define NS9750_SER_BITRATE_TMODE	 (0x40000000)
-#define NS9750_SER_BITRATE_RXSRC	 (0x20000000)
-#define NS9750_SER_BITRATE_TXSRC	 (0x10000000)
-#define NS9750_SER_BITRATE_RXEXT	 (0x08000000)
-#define NS9750_SER_BITRATE_TXEXT	 (0x04000000)
-#define NS9750_SER_BITRATE_CLKMUX_MA	 (0x03000000)
-#define NS9750_SER_BITRATE_CLKMUX_XTAL	 (0x00000000)
-#define NS9750_SER_BITRATE_CLKMUX_BCLK	 (0x01000000)
-#define NS9750_SER_BITRATE_CLKMUX_OUT1	 (0x02000000)
-#define NS9750_SER_BITRATE_CLKMUX_OUT2	 (0x03000000)
-#define NS9750_SER_BITRATE_TXCINV	 (0x00800000)
-#define NS9750_SER_BITRATE_RXCINV	 (0x00400000)
-#define NS9750_SER_BITRATE_TCDR_MA	 (0x00180000)
-#define NS9750_SER_BITRATE_TCDR_1	 (0x00000000)
-#define NS9750_SER_BITRATE_TCDR_8	 (0x00080000)
-#define NS9750_SER_BITRATE_TCDR_16	 (0x00100000)
-#define NS9750_SER_BITRATE_TCDR_32	 (0x00180000)
-#define NS9750_SER_BITRATE_RCDR_MA	 (0x00070000)
-#define NS9750_SER_BITRATE_RCDR_1	 (0x00000000)
-#define NS9750_SER_BITRATE_RCDR_8	 (0x00020000)
-#define NS9750_SER_BITRATE_RCDR_16	 (0x00040000)
-#define NS9750_SER_BITRATE_RCDR_32	 (0x00060000)
-#define NS9750_SER_BITRATE_TICS		 (0x00010000)
-#define NS9750_SER_BITRATE_RICS		 (0x00008000)
-#define NS9750_SER_BITRATE_N_MA		 (0x00007FFF)
-
-/* receive buffer gap timer */
-
-#define NS9750_SER_RX_BUF_TIMER_TRUN	 (0x80000000) /* UART and SPI */
-#define NS9750_SER_RX_BUF_TIMER_BT_MA	 (0x0000FFFF) /* UART and SPI */
-#define NS9750_SER_RX_BUF_TIMER_MAXLEN_MA (0x0000FFFF) /* HDLC only */
-
-/* receive character gap timer */
-
-#define NS9750_SER_RX_CHAR_TIMER_TRUN	 (0x80000000)
-#define NS9750_SER_RX_CHAR_TIMER_CT_MA	 (0x000FFFFF)
-
-/* receive match */
-
-#define NS9750_SER_RX_MATCH_RDMB1_MA	 (0xFF000000)
-#define NS9750_SER_RX_MATCH_RDMB2_MA	 (0x00FF0000)
-#define NS9750_SER_RX_MATCH_RDMB3_MA	 (0x0000FF00)
-#define NS9750_SER_RX_MATCH_RDMB4_MA	 (0x000000FF)
-
-/* receive match mask */
-
-#define NS9750_SER_RX_MATCH_MASK_RDMB1_MA (0xFF000000)
-#define NS9750_SER_RX_MATCH_MASK_RDMB2_MA (0x00FF0000)
-#define NS9750_SER_RX_MATCH_MASK_RDMB3_MA (0x0000FF00)
-#define NS9750_SER_RX_MATCH_MASK_RDMB4_MA (0x000000FF)
-
-#endif /* FS_NS9750_SER_H */
diff --git a/include/ns9750_sys.h b/include/ns9750_sys.h
deleted file mode 100644
index f1dc2b2382..0000000000
--- a/include/ns9750_sys.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2004 by FS Forth-Systeme GmbH.
- * All rights reserved.
- *
- * $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
- * @Author: Markus Pietrek
- * @Descr: Definitions for SYS Control Module
- * @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- ***********************************************************************/
-
-#ifndef FS_NS9750_SYS_H
-#define FS_NS9750_SYS_H
-
-#define NS9750_SYS_MODULE_BASE		(0xA0900000)
-
-#define get_sys_reg_addr(c) \
-	((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
-
-/* the register addresses */
-
-#define NS9750_SYS_AHB_GEN		(0x0000)
-#define NS9750_SYS_BRC_BASE		(0x0004)
-#define NS9750_SYS_AHB_TIMEOUT		(0x0014)
-#define NS9750_SYS_AHB_ERROR1		(0x0018)
-#define NS9750_SYS_AHB_ERROR2		(0x001C)
-#define NS9750_SYS_AHB_MON		(0x0020)
-#define NS9750_SYS_TIMER_COUNT_BASE	(0x0044)
-#define NS9750_SYS_TIMER_READ_BASE	(0x0084)
-#define NS9750_SYS_INT_VEC_ADR_BASE	(0x00C4)
-#define NS9750_SYS_INT_CFG_BASE		(0x0144)
-#define NS9750_SYS_ISRADDR		(0x0164)
-#define NS9750_SYS_INT_STAT_ACTIVE	(0x0168)
-#define NS9750_SYS_INT_STAT_RAW		(0x016C)
-#define NS9750_SYS_TIMER_INT_STAT	(0x0170)
-#define NS9750_SYS_SW_WDOG_CFG		(0x0174)
-#define NS9750_SYS_SW_WDOG_TIMER	(0x0178)
-#define NS9750_SYS_CLOCK		(0x017C)
-#define NS9750_SYS_RESET		(0x0180)
-#define NS9750_SYS_MISC			(0x0184)
-#define NS9750_SYS_PLL			(0x0188)
-#define NS9750_SYS_ACT_INT_STAT		(0x018C)
-#define NS9750_SYS_TIMER_CTRL_BASE	(0x0190)
-#define NS9750_SYS_CS_DYN_BASE_BASE	(0x01D0)
-#define NS9750_SYS_CS_DYN_MASK_BASE	(0x01D4)
-#define NS9750_SYS_CS_STATIC_BASE_BASE	(0x01F0)
-#define NS9750_SYS_CS_STATIC_MASK_BASE	(0x01F4)
-#define NS9750_SYS_GEN_ID		(0x0210)
-#define NS9750_SYS_EXT_INT_CTRL_BASE	(0x0214)
-
-/* the vectored register addresses */
-
-#define NS9750_SYS_TIMER_COUNT(c)	(NS9750_SYS_TIMER_COUNT_BASE + (c))
-#define NS9750_SYS_TIMER_READ(c)	(NS9750_SYS_TIMER_READ_BASE + (c))
-#define NS9750_SYS_INT_VEC_ADR(c)	(NS9750_SYS_INT_VEC_ADR_BASE + (c))
-#define NS9750_SYS_TIMER_CTRL(c)	(NS9750_SYS_TIMER_CTRL_BASE + (c))
-/* CS_DYN start with 4 */
-#define NS9750_SYS_CS_DYN_BASE(c)	(NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2)
-#define NS9750_SYS_CS_DYN_MASK(c)	(NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2)
-/* CS_STATIC start with 0 */
-#define NS9750_SYS_CS_STATIC_BASE(c)	(NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2)
-#define NS9750_SYS_CS_STATIC_MASK(c)	(NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2)
-#define NS9750_SYS_EXT_INT_CTRL(c)	(NS9750_SYS_EXT_INT_CTRL + (c))
-
-/* register bit fields */
-
-#define NS9750_SYS_AHB_GEN_EXMAM	(0x00000001)
-
-/* need to be n*8bit to BRC channel */
-#define NS9750_SYS_BRC_CEB		(0x00000080)
-#define NS9750_SYS_BRC_BRF_MA		(0x00000030)
-#define NS9750_SYS_BRC_BRF_100		(0x00000000)
-#define NS9750_SYS_BRC_BRF_75		(0x00000010)
-#define NS9750_SYS_BRC_BRF_50		(0x00000020)
-#define NS9750_SYS_BRC_BRF_25		(0x00000030)
-
-#define NS9750_SYS_AHB_TIMEOUT_BAT_MA	(0xFFFF0000)
-#define NS9750_SYS_AHB_TIMEOUT_BMT_MA	(0x0000FFFF)
-
-#define NS9750_SYS_AHB_ERROR2_ABL	(0x00040000)
-#define NS9750_SYS_AHB_ERROR2_AER	(0x00020000)
-#define NS9750_SYS_AHB_ERROR2_ABM	(0x00010000)
-#define NS9750_SYS_AHB_ERROR2_ABA	(0x00008000)
-#define NS9750_SYS_AHB_ERROR2_HWRT	(0x00004000)
-#define NS9750_SYS_AHB_ERROR2_HMID_MA	(0x00003C00)
-#define NS9750_SYS_AHB_ERROR2_HTPC_MA	(0x000003C0)
-#define NS9750_SYS_AHB_ERROR2_HSZ_MA	(0x00000038)
-#define NS9750_SYS_AHB_ERROR2_RR_MA	(0x00000007)
-
-#define NS9750_SYS_AHB_MON_EIC		(0x00800000)
-#define NS9750_SYS_AHB_MON_MBII		(0x00400000)
-#define NS9750_SYS_AHB_MON_MBL_MA	(0x003FFFC0)
-#define NS9750_SYS_AHB_MON_MBLDC	(0x00000020)
-#define NS9750_SYS_AHB_MON_SERDC	(0x00000010)
-#define NS9750_SYS_AHB_MON_BMTC_MA	(0x0000000C)
-#define NS9750_SYS_AHB_MON_BMTC_RECORD	(0x00000000)
-#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ	(0x00000004)
-#define NS9750_SYS_AHB_MON_BMTC_GEN_RES	(0x00000008)
-#define NS9750_SYS_AHB_MON_BATC_MA	(0x00000003)
-#define NS9750_SYS_AHB_MON_BATC_RECORD	(0x00000000)
-#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ	(0x00000001)
-#define NS9750_SYS_AHB_MON_BATC_GEN_RES	(0x00000002)
-
-/* need to be n*8bit to Int Level */
-
-#define NS9750_SYS_INT_CFG_IE		(0x00000080)
-#define NS9750_SYS_INT_CFG_IT		(0x00000020)
-#define NS9750_SYS_INT_CFG_IAD_MA	(0x0000001F)
-
-#define NS9750_SYS_TIMER_INT_STAT_MA	(0x0000FFFF)
-
-#define NS9750_SYS_SW_WDOG_CFG_SWWE	(0x00000080)
-#define NS9750_SYS_SW_WDOG_CFG_SWWI	(0x00000020)
-#define NS9750_SYS_SW_WDOG_CFG_SWWIC	(0x00000010)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA	(0x00000007)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2	(0x00000000)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4	(0x00000001)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8	(0x00000002)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16	(0x00000003)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32	(0x00000004)
-#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64	(0x00000005)
-
-#define NS9750_SYS_CLOCK_LPCS_MA	(0x00000380)
-#define NS9750_SYS_CLOCK_LPCS_1		(0x00000000)
-#define NS9750_SYS_CLOCK_LPCS_2		(0x00000080)
-#define NS9750_SYS_CLOCK_LPCS_4		(0x00000100)
-#define NS9750_SYS_CLOCK_LPCS_8		(0x00000180)
-#define NS9750_SYS_CLOCK_LPCS_EXT	(0x00000200)
-#define NS9750_SYS_CLOCK_BBC		(0x00000040)
-#define NS9750_SYS_CLOCK_LCC		(0x00000020)
-#define NS9750_SYS_CLOCK_MCC		(0x00000010)
-#define NS9750_SYS_CLOCK_PARBC		(0x00000008)
-#define NS9750_SYS_CLOCK_PC		(0x00000004)
-#define NS9750_SYS_CLOCK_MACC		(0x00000001)
-
-#define NS9750_SYS_RESET_SR		(0x80000000)
-#define NS9750_SYS_RESET_I2CW		(0x00100000)
-#define NS9750_SYS_RESET_CSE		(0x00080000)
-#define NS9750_SYS_RESET_SMWE		(0x00040000)
-#define NS9750_SYS_RESET_EWE		(0x00020000)
-#define NS9750_SYS_RESET_PI3WE		(0x00010000)
-#define NS9750_SYS_RESET_BBT		(0x00000040)
-#define NS9750_SYS_RESET_LCDC		(0x00000020)
-#define NS9750_SYS_RESET_MEMC		(0x00000010)
-#define NS9750_SYS_RESET_PCIAR		(0x00000008)
-#define NS9750_SYS_RESET_PCIM		(0x00000004)
-#define NS9750_SYS_RESET_MACM		(0x00000001)
-
-#define NS9750_SYS_MISC_REV_MA		(0xFF000000)
-#define NS9750_SYS_MISC_PCIA		(0x00002000)
-#define NS9750_SYS_MISC_VDIS		(0x00001000)
-#define NS9750_SYS_MISC_BMM		(0x00000800)
-#define NS9750_SYS_MISC_CS1DB		(0x00000400)
-#define NS9750_SYS_MISC_CS1DW_MA	(0x00000300)
-#define NS9750_SYS_MISC_MCCM		(0x00000080)
-#define NS9750_SYS_MISC_PMSS		(0x00000040)
-#define NS9750_SYS_MISC_CS1P		(0x00000020)
-#define NS9750_SYS_MISC_ENDM		(0x00000008)
-#define NS9750_SYS_MISC_MBAR		(0x00000004)
-#define NS9750_SYS_MISC_IRAM0		(0x00000001)
-
-#define NS9750_SYS_PLL_PLLBS		(0x02000000)
-#define NS9750_SYS_PLL_PLLFS_MA		(0x01800000)
-#define NS9750_SYS_PLL_PLLIS_MA		(0x00600000)
-#define NS9750_SYS_PLL_PLLND_MA		(0x001F0000)
-#define NS9750_SYS_PLL_PLLSW		(0x00008000)
-#define NS9750_SYS_PLL_PLLBSSW		(0x00000200)
-#define NS9750_SYS_PLL_FSEL_MA		(0x00000180)
-#define NS9750_SYS_PLL_CPCC_MA		(0x00000060)
-#define NS9750_SYS_PLL_NDSW_MA		(0x0000001F)
-
-#define NS9750_SYS_ACT_INT_STAT_MA	(0x0000FFFF)
-
-#define NS9750_SYS_TIMER_CTRL_TEN	(0x00008000)
-#define NS9750_SYS_TIMER_CTRL_INTC	(0x00000200)
-#define NS9750_SYS_TIMER_CTRL_TLCS_MA	(0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_1	(0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TLCS_2	(0x00000040)
-#define NS9750_SYS_TIMER_CTRL_TLCS_4	(0x00000080)
-#define NS9750_SYS_TIMER_CTRL_TLCS_8	(0x000000C0)
-#define NS9750_SYS_TIMER_CTRL_TLCS_16	(0x00000100)
-#define NS9750_SYS_TIMER_CTRL_TLCS_32	(0x00000140)
-#define NS9750_SYS_TIMER_CTRL_TLCS_64	(0x00000180)
-#define NS9750_SYS_TIMER_CTRL_TLCS_EXT	(0x000001C0)
-#define NS9750_SYS_TIMER_CTRL_TM_MA	(0x00000030)
-#define NS9750_SYS_TIMER_CTRL_TM_INT	(0x00000000)
-#define NS9750_SYS_TIMER_CTRL_TM_LOW	(0x00000010)
-#define NS9750_SYS_TIMER_CTRL_TM_HIGH	(0x00000020)
-#define NS9750_SYS_TIMER_CTRL_INTS	(0x00000008)
-#define NS9750_SYS_TIMER_CTRL_UDS	(0x00000004)
-#define NS9750_SYS_TIMER_CTRL_TSZ	(0x00000002)
-#define NS9750_SYS_TIMER_CTRL_REN	(0x00000001)
-
-#define NS9750_SYS_EXT_INT_CTRL_STS	(0x00000008)
-#define NS9750_SYS_EXT_INT_CTRL_CLR	(0x00000004)
-#define NS9750_SYS_EXT_INT_CTRL_PLTY	(0x00000002)
-#define NS9750_SYS_EXT_INT_CTRL_LVEDG	(0x00000001)
-
-#endif /* FS_NS9750_SYS_H */