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| author | Wolfgang Denk <wd@denx.de> | 2008-05-20 16:00:29 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-05-21 00:14:08 +0200 |
| commit | 53677ef18e25c97ac613349087c5cb33ae5a2741 (patch) | |
| tree | f947d34d6efaee2401ea0e4c6104ef2f6a0f7ad0 /include | |
| parent | 727f63334676e760877d43bfb8f0e9331ac8b101 (diff) | |
| download | blackbird-obmc-uboot-53677ef18e25c97ac613349087c5cb33ae5a2741.tar.gz blackbird-obmc-uboot-53677ef18e25c97ac613349087c5cb33ae5a2741.zip | |
Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include')
280 files changed, 6212 insertions, 6218 deletions
diff --git a/include/ACEX1K.h b/include/ACEX1K.h index f249d6402d..6ea0eed952 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -73,9 +73,9 @@ typedef struct { * Filesize of an *.rbf file is 166965 Bytes */ #if 0 -#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ +#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ #endif -#define Altera_EP1K100_SIZE (166965*8) +#define Altera_EP1K100_SIZE (166965*8) #define Altera_EP2C35_SIZE 883905 diff --git a/include/SA-1100.h b/include/SA-1100.h index 9985783e58..7589df238a 100644 --- a/include/SA-1100.h +++ b/include/SA-1100.h @@ -1,20 +1,20 @@ /* - * FILE SA-1100.h + * FILE SA-1100.h * - * Version 1.2 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date January 1998 (April 1997) - * System StrongARM SA-1100 + * Version 1.2 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date January 1998 (April 1997) + * System StrongARM SA-1100 * Language C or ARM Assembly - * Purpose Definition of constants related to the StrongARM - * SA-1100 microprocessor (Advanced RISC Machine (ARM) - * architecture version 4). This file is based on the - * StrongARM SA-1100 data sheet version 2.2. + * Purpose Definition of constants related to the StrongARM + * SA-1100 microprocessor (Advanced RISC Machine (ARM) + * architecture version 4). This file is based on the + * StrongARM SA-1100 data sheet version 2.2. * - * Language-specific definitions are selected by the - * macro "LANGUAGE", which should be defined as either - * "C" (default) or "Assembly". + * Language-specific definitions are selected by the + * macro "LANGUAGE", which should be defined as either + * "C" (default) or "Assembly". */ @@ -32,17 +32,17 @@ #include <asm/arch-sa1100/bitfield.h> -#define C 0 +#define C 0 #define Assembly 1 #if LANGUAGE == C -typedef unsigned short Word16 ; -typedef unsigned int Word32 ; -typedef Word32 Word ; -typedef Word Quad [4] ; -typedef void *Address ; -typedef void (*ExcpHndlr) (void) ; +typedef unsigned short Word16 ; +typedef unsigned int Word32 ; +typedef Word32 Word ; +typedef Word Quad [4] ; +typedef void *Address ; +typedef void (*ExcpHndlr) (void) ; #endif /* LANGUAGE == C */ @@ -50,65 +50,65 @@ typedef void (*ExcpHndlr) (void) ; * Memory */ -#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ +#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */ #define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */ -#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ - /* [byte] */ -#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ - /* [byte] */ -#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ - /* [byte] */ -#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ - /* [byte] */ - -#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ -#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ -#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ -#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ -#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ +#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */ + /* [byte] */ +#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */ + /* [byte] */ +#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */ + /* [byte] */ +#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */ + /* [byte] */ + +#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */ +#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */ +#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */ +#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */ +#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */ #define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */ -#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ +#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \ (0x00000000 + (Nb)*StMemBnkSp) -#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ -#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ -#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ -#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ +#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */ +#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */ +#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */ +#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */ #if LANGUAGE == C -typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; -#define StMemBnk /* Static Memory Bank [0..3] */ \ +typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ; +#define StMemBnk /* Static Memory Bank [0..3] */ \ ((StMemBnkType *) io_p2v (_StMemBnk (0))) -#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ -#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ -#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ -#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ +#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */ +#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */ +#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */ +#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */ #endif /* LANGUAGE == C */ -#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ +#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \ (0xC0000000 + (Nb)*DRAMBnkSp) -#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ -#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ -#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ -#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ +#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */ +#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */ +#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */ +#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */ #if LANGUAGE == C -typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; -#define DRAMBnk /* DRAM Bank [0..3] */ \ +typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ; +#define DRAMBnk /* DRAM Bank [0..3] */ \ ((DRAMBnkType *) io_p2v (_DRAMBnk (0))) -#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ -#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ -#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ -#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ +#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */ +#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */ +#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */ +#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */ #endif /* LANGUAGE == C */ -#define _ZeroMem 0xE0000000 /* Zero Memory bank */ +#define _ZeroMem 0xE0000000 /* Zero Memory bank */ #if LANGUAGE == C -typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; -#define ZeroMem /* Zero Memory bank */ \ +typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; +#define ZeroMem /* Zero Memory bank */ \ (*((ZeroMemType *) io_p2v (_ZeroMem))) #endif /* LANGUAGE == C */ @@ -118,60 +118,60 @@ typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ; */ #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ -#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ -#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ -#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ -#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ -#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ -#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ -#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ -#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ (0x20000000 + (Nb)*PCMCIASp) -#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ -#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ (_PCMCIA (Nb) + 2*PCMCIAPrtSp) -#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ (_PCMCIA (Nb) + 3*PCMCIAPrtSp) -#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ -#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ -#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ -#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ -#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ -#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ -#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ -#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ #if LANGUAGE == C -typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; +typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ; typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; -#define PCMCIA0 /* PCMCIA 0 */ \ +#define PCMCIA0 /* PCMCIA 0 */ \ (*((PCMCIAType *) io_p2v (_PCMCIA0))) -#define PCMCIA0IO /* PCMCIA 0 I/O */ \ +#define PCMCIA0IO /* PCMCIA 0 I/O */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO))) -#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ +#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr))) -#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ +#define PCMCIA0Mem /* PCMCIA 0 Memory */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem))) -#define PCMCIA1 /* PCMCIA 1 */ \ +#define PCMCIA1 /* PCMCIA 1 */ \ (*((PCMCIAType *) io_p2v (_PCMCIA1))) -#define PCMCIA1IO /* PCMCIA 1 I/O */ \ +#define PCMCIA1IO /* PCMCIA 1 I/O */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO))) -#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ +#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr))) -#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ +#define PCMCIA1Mem /* PCMCIA 1 Memory */ \ (*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem))) #endif /* LANGUAGE == C */ @@ -181,254 +181,254 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Universal Serial Bus (USB) Device Controller (UDC) control registers * * Registers - * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control Register (read/write). - * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Address Register (read/write). + * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control Register (read/write). + * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Address Register (read/write). * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Output Maximum Packet size register - * (read/write). + * Controller (UDC) Output Maximum Packet size register + * (read/write). * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Input Maximum Packet size register - * (read/write). + * Controller (UDC) Input Maximum Packet size register + * (read/write). * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 0 - * (read/write). + * Controller (UDC) Control/Status register end-point 0 + * (read/write). * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 1 - * (output, read/write). + * Controller (UDC) Control/Status register end-point 1 + * (output, read/write). * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Control/Status register end-point 2 - * (input, read/write). - * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data register end-point 0 - * (read/write). - * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Write Count register end-point 0 - * (read). - * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Data Register (read/write). - * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device - * Controller (UDC) Status Register (read/write). + * Controller (UDC) Control/Status register end-point 2 + * (input, read/write). + * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data register end-point 0 + * (read/write). + * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Write Count register end-point 0 + * (read). + * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data Register (read/write). + * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Status Register (read/write). */ #define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */ #define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */ #define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */ - /* Packet size reg. */ + /* Packet size reg. */ #define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */ - /* Packet size reg. */ + /* Packet size reg. */ #define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 0 */ + /* reg. end-point 0 */ #define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 1 (output) */ + /* reg. end-point 1 (output) */ #define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */ - /* reg. end-point 2 (input) */ -#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ - /* end-point 0 */ -#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ - /* reg. end-point 0 */ -#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ -#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ + /* reg. end-point 2 (input) */ +#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */ + /* end-point 0 */ +#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */ + /* reg. end-point 0 */ +#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */ +#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */ #if LANGUAGE == C -#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ +#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCCR))) -#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ +#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCAR))) -#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ - /* Packet size reg. */ \ +#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \ + /* Packet size reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCOMP))) -#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ - /* Packet size reg. */ \ +#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \ + /* Packet size reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCIMP))) -#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 0 */ \ +#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 0 */ \ (*((volatile Word *) io_p2v (_Ser0UDCCS0))) -#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 1 (output) */ \ +#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 1 (output) */ \ (*((volatile Word *) io_p2v (_Ser0UDCCS1))) -#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ - /* reg. end-point 2 (input) */ \ +#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \ + /* reg. end-point 2 (input) */ \ (*((volatile Word *) io_p2v (_Ser0UDCCS2))) -#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ - /* end-point 0 */ \ +#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \ + /* end-point 0 */ \ (*((volatile Word *) io_p2v (_Ser0UDCD0))) -#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ - /* reg. end-point 0 */ \ +#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \ + /* reg. end-point 0 */ \ (*((volatile Word *) io_p2v (_Ser0UDCWC))) -#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ +#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCDR))) -#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ +#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \ (*((volatile Word *) io_p2v (_Ser0UDCSR))) #endif /* LANGUAGE == C */ -#define UDCCR_UDD 0x00000001 /* UDC Disable */ -#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ +#define UDCCR_UDD 0x00000001 /* UDC Disable */ +#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ -#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ - /* (disable) */ -#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ - /* (disable) */ -#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ - /* (disable) */ +#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ + /* (disable) */ +#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ + /* (disable) */ +#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ + /* (disable) */ #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ - /* (disable) */ + /* (disable) */ #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ -#define UDCAR_ADD Fld (7, 0) /* function ADDress */ +#define UDCAR_ADD Fld (7, 0) /* function ADDress */ #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ - /* [1..256 byte] */ \ + /* [byte] */ +#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ + /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ - /* [byte] */ -#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ - /* [1..256 byte] */ \ + /* [byte] */ +#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ + /* [1..256 byte] */ \ (((Size) - 1) << FShft (UDCIMP_INMAXP)) -#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ -#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ -#define UDCCS0_SST 0x00000004 /* Sent STall */ -#define UDCCS0_FST 0x00000008 /* Force STall */ -#define UDCCS0_DE 0x00000010 /* Data End */ -#define UDCCS0_SE 0x00000020 /* Setup End (read) */ +#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ +#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ +#define UDCCS0_SST 0x00000004 /* Sent STall */ +#define UDCCS0_FST 0x00000008 /* Force STall */ +#define UDCCS0_DE 0x00000010 /* Data End */ +#define UDCCS0_SE 0x00000020 /* Setup End (read) */ #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ - /* (write) */ -#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ + /* (write) */ +#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ - /* Service request (read) */ -#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ -#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ -#define UDCCS1_SST 0x00000008 /* Sent STall */ -#define UDCCS1_FST 0x00000010 /* Force STall */ + /* Service request (read) */ +#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ +#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ +#define UDCCS1_SST 0x00000008 /* Sent STall */ +#define UDCCS1_FST 0x00000010 /* Force STall */ #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ - /* Service request (read) */ -#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ + /* Service request (read) */ +#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ -#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ -#define UDCCS2_SST 0x00000010 /* Sent STall */ -#define UDCCS2_FST 0x00000020 /* Force STall */ +#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ +#define UDCCS2_SST 0x00000010 /* Sent STall */ +#define UDCCS2_FST 0x00000020 /* Force STall */ -#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#define UDCWC_WC Fld (4, 0) /* Write Count */ +#define UDCWC_WC Fld (4, 0) /* Write Count */ -#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ -#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ -#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ -#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ -#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ -#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ +#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ +#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ +#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ +#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ +#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ /* * Universal Asynchronous Receiver/Transmitter (UART) control registers * * Registers - * Ser1UTCR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser1UTCR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser1UTCR2 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser1UTCR3 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser1UTDR Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser1UTSR0 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser1UTSR1 Serial port 1 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). + * Ser1UTCR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser1UTCR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser1UTCR2 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser1UTCR3 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser1UTDR Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser1UTSR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser1UTSR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). * - * Ser2UTCR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser2UTCR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser2UTCR2 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser2UTCR3 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser2UTCR4 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 4 - * (read/write). - * Ser2UTDR Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser2UTSR0 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser2UTSR1 Serial port 2 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). + * Ser2UTCR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser2UTCR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser2UTCR2 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser2UTCR3 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser2UTCR4 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 4 + * (read/write). + * Ser2UTDR Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser2UTSR0 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser2UTSR1 Serial port 2 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). * - * Ser3UTCR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 0 - * (read/write). - * Ser3UTCR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 1 - * (read/write). - * Ser3UTCR2 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 2 - * (read/write). - * Ser3UTCR3 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Control Register 3 - * (read/write). - * Ser3UTDR Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Data Register - * (read/write). - * Ser3UTSR0 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 0 - * (read/write). - * Ser3UTSR1 Serial port 3 Universal Asynchronous - * Receiver/Transmitter (UART) Status Register 1 (read). + * Ser3UTCR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser3UTCR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser3UTCR2 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser3UTCR3 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser3UTDR Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). + * Ser3UTSR0 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 0 + * (read/write). + * Ser3UTSR1 Serial port 3 Universal Asynchronous + * Receiver/Transmitter (UART) Status Register 1 (read). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fua, Tua Frequency, period of the UART communication. + * or 3.5795 MHz). + * fua, Tua Frequency, period of the UART communication. */ -#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ +#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \ (0x80010000 + ((Nb) - 1)*0x00020000) -#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ +#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \ (0x80010004 + ((Nb) - 1)*0x00020000) -#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ +#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \ (0x80010008 + ((Nb) - 1)*0x00020000) -#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ +#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \ (0x8001000C + ((Nb) - 1)*0x00020000) -#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ +#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \ (0x80010010 + ((Nb) - 1)*0x00020000) -#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ +#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \ (0x80010014 + ((Nb) - 1)*0x00020000) -#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ +#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \ (0x8001001C + ((Nb) - 1)*0x00020000) -#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ +#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \ (0x80010020 + ((Nb) - 1)*0x00020000) #define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */ #define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */ #define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */ #define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */ -#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ +#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */ #define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */ #define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */ @@ -437,7 +437,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */ #define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */ #define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */ -#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ +#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */ #define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */ #define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */ @@ -445,57 +445,57 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */ #define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */ #define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */ -#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ +#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */ #define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */ #define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */ #if LANGUAGE == C -#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ +#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR0))) -#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ +#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR1))) -#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ +#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR2))) -#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ +#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser1UTCR3))) -#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ +#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser1UTDR))) -#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ +#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1UTSR0))) -#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ +#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1UTSR1))) -#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ +#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR0))) -#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ +#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR1))) -#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ +#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR2))) -#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ +#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR3))) -#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ +#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \ (*((volatile Word *) io_p2v (_Ser2UTCR4))) -#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ +#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser2UTDR))) -#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ +#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2UTSR0))) -#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ +#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2UTSR1))) -#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ +#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR0))) -#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ +#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR1))) -#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ +#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR2))) -#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ +#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser3UTCR3))) -#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ +#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser3UTDR))) -#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ +#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser3UTSR0))) -#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ +#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser3UTSR1))) #elif LANGUAGE == Assembly @@ -526,89 +526,89 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* LANGUAGE == C */ -#define UTCR0_PE 0x00000001 /* Parity Enable */ -#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ -#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ -#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ -#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ -#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ -#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ -#define UTCR0_DSS 0x00000008 /* Data Size Select */ -#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ -#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ -#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ - /* (ser. port 1: GPIO [18], */ - /* ser. port 3: GPIO [20]) */ -#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ -#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ -#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ -#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ -#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ +#define UTCR0_PE 0x00000001 /* Parity Enable */ +#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */ +#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */ +#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */ +#define UTCR0_SBS 0x00000004 /* Stop Bit Select */ +#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */ +#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */ +#define UTCR0_DSS 0x00000008 /* Data Size Select */ +#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */ +#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */ +#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */ + /* (ser. port 1: GPIO [18], */ + /* ser. port 3: GPIO [20]) */ +#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */ +#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */ +#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */ +#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */ +#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */ #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */ -#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ +#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \ (UTCR0_1StpBit + UTCR0_8BitData) #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ /* fua = fxtl/(16*(BRD[11:0] + 1)) */ /* Tua = 16*(BRD [11:0] + 1)*Txtl */ -#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) -#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Floor (Div/16)) */ /* Tua = 16*Floor (Div/16)*Txtl */ -#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \ FShft (UTCR1_BRD)) -#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \ FShft (UTCR2_BRD)) /* fua = fxtl/(16*Ceil (Div/16)) */ /* Tua = 16*Ceil (Div/16)*Txtl */ -#define UTCR3_RXE 0x00000001 /* Receive Enable */ -#define UTCR3_TXE 0x00000002 /* Transmit Enable */ -#define UTCR3_BRK 0x00000004 /* BReaK mode */ +#define UTCR3_RXE 0x00000001 /* Receive Enable */ +#define UTCR3_TXE 0x00000002 /* Transmit Enable */ +#define UTCR3_BRK 0x00000004 /* BReaK mode */ #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ -#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ + /* Interrupt Enable */ +#define UTCR3_LBM 0x00000020 /* Look-Back Mode */ +#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \ /* TIE, LBM can be set or cleared) */ \ (UTCR3_RXE + UTCR3_TXE) #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */ - /* (HP-SIR) modulation Enable */ + /* (HP-SIR) modulation Enable */ #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */ -#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ -#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ -#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ -#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ +#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */ +#define UTCR4_LPM 0x00000002 /* Low-Power Mode */ +#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */ +#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */ -#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ +#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */ #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */ #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ -#define UTSR0_RID 0x00000004 /* Receiver IDle */ -#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ -#define UTSR0_REB 0x00000010 /* Receive End of Break */ -#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ + /* more Service request (read) */ +#define UTSR0_RID 0x00000004 /* Receiver IDle */ +#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */ +#define UTSR0_REB 0x00000010 /* Receive End of Break */ +#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */ -#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ +#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */ #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */ #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */ -#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ +#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */ #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */ #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */ @@ -617,27 +617,27 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Synchronous Data Link Controller (SDLC) control registers * * Registers - * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 0 (read/write). - * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 1 (read/write). - * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 2 (read/write). - * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 3 (read/write). - * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) - * Control Register 4 (read/write). - * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) - * Data Register (read/write). - * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 0 (read/write). - * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) - * Status Register 1 (read/write). + * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 0 (read/write). + * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 1 (read/write). + * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 2 (read/write). + * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 3 (read/write). + * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC) + * Control Register 4 (read/write). + * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC) + * Data Register (read/write). + * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 0 (read/write). + * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC) + * Status Register 1 (read/write). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fsd, Tsd Frequency, period of the SDLC communication. + * or 3.5795 MHz). + * fsd, Tsd Frequency, period of the SDLC communication. */ #define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */ @@ -645,110 +645,110 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */ #define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */ #define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */ -#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ +#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */ #define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */ #define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */ #if LANGUAGE == C -#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ +#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR0))) -#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ +#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR1))) -#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ +#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR2))) -#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ +#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR3))) -#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ +#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \ (*((volatile Word *) io_p2v (_Ser1SDCR4))) -#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ +#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser1SDDR))) -#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ +#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser1SDSR0))) -#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ +#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser1SDSR1))) #endif /* LANGUAGE == C */ -#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ -#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ -#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ +#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */ +#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */ +#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */ #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */ -#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ -#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ -#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ -#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ -#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ +#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */ +#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */ +#define SDCR0_LBM 0x00000004 /* Look-Back Mode */ +#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */ +#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */ #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */ #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */ #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */ - /* (GPIO [16]) */ -#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ -#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ -#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ -#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ -#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ -#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ -#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ + /* (GPIO [16]) */ +#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */ +#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */ +#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */ +#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */ +#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */ +#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */ +#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */ #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */ -#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ - /* (GPIO [17]) */ -#define SDCR1_TXE 0x00000002 /* Transmit Enable */ -#define SDCR1_RXE 0x00000004 /* Receive Enable */ +#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */ + /* (GPIO [17]) */ +#define SDCR1_TXE 0x00000002 /* Transmit Enable */ +#define SDCR1_RXE 0x00000004 /* Receive Enable */ #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SDCR1_AME 0x00000020 /* Address Match Enable */ + /* Interrupt Enable */ +#define SDCR1_AME 0x00000020 /* Address Match Enable */ #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */ -#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ -#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ +#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */ +#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */ #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */ -#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ +#define SDCR2_AMV Fld (8, 0) /* Address Match Value */ #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */ #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */ /* fsd = fxtl/(16*(BRD[11:0] + 1)) */ /* Tsd = 16*(BRD[11:0] + 1)*Txtl */ -#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \ FShft (SDCR3_BRD)) -#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ +#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \ (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \ FShft (SDCR4_BRD)) /* fsd = fxtl/(16*Floor (Div/16)) */ /* Tsd = 16*Floor (Div/16)*Txtl */ -#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \ FShft (SDCR3_BRD)) -#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ +#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \ (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \ FShft (SDCR4_BRD)) /* fsd = fxtl/(16*Ceil (Div/16)) */ /* Tsd = 16*Ceil (Div/16)*Txtl */ -#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ +#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */ #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ -#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define SDSR0_RAB 0x00000004 /* Receive ABort */ +#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define SDSR0_RAB 0x00000004 /* Receive ABort */ #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */ #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ -#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ -#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ +#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */ +#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */ +#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */ #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */ @@ -756,159 +756,159 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * High-Speed Serial to Parallel controller (HSSP) control registers * * Registers - * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 0 (read/write). - * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 1 (read/write). - * Ser2HSDR Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Data Register (read/write). - * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 0 (read/write). - * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Status Register 1 (read). - * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel - * controller (HSSP) Control Register 2 (read/write). - * [The HSCR2 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] + * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 0 (read/write). + * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 1 (read/write). + * Ser2HSDR Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Data Register (read/write). + * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 0 (read/write). + * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Status Register 1 (read). + * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel + * controller (HSSP) Control Register 2 (read/write). + * [The HSCR2 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] */ #define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */ #define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */ -#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ +#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */ #define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */ #define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */ #define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */ #if LANGUAGE == C -#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ +#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2HSCR0))) -#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ +#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2HSCR1))) -#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ +#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser2HSDR))) -#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ +#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser2HSSR0))) -#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ +#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser2HSSR1))) -#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ +#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_Ser2HSCR2))) #endif /* LANGUAGE == C */ -#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ +#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */ #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */ -#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ -#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ +#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */ +#define HSCR0_LBM 0x00000002 /* Look-Back Mode */ #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */ -#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ -#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ -#define HSCR0_TXE 0x00000008 /* Transmit Enable */ -#define HSCR0_RXE 0x00000010 /* Receive Enable */ +#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */ +#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */ +#define HSCR0_TXE 0x00000008 /* Transmit Enable */ +#define HSCR0_RXE 0x00000010 /* Receive Enable */ #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Interrupt Enable */ + /* more Interrupt Enable */ #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define HSCR0_AME 0x00000080 /* Address Match Enable */ + /* Interrupt Enable */ +#define HSCR0_AME 0x00000080 /* Address Match Enable */ -#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ +#define HSCR1_AMV Fld (8, 0) /* Address Match Value */ -#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ -#if 0 /* Hidden receive FIFO bits */ +#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ +#if 0 /* Hidden receive FIFO bits */ #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */ -#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ +#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */ #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */ #endif /* 0 */ -#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ -#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ -#define HSSR0_RAB 0x00000004 /* Receive ABort */ +#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */ +#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */ +#define HSSR0_RAB 0x00000004 /* Receive ABort */ #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */ - /* more Service request (read) */ -#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ + /* more Service request (read) */ +#define HSSR0_FRE 0x00000020 /* receive FRaming Error */ #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */ -#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ +#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */ #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */ -#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ -#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ +#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */ +#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */ #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */ #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */ -#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ - /* (inverted) */ -#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ - /* (non-inverted) */ +#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */ + /* (inverted) */ +#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */ + /* (non-inverted) */ #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */ -#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ - /* (inverted) */ -#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ - /* (non-inverted) */ +#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */ + /* (inverted) */ +#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */ + /* (non-inverted) */ /* * Multi-media Communications Port (MCP) control registers * * Registers - * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 0 (read/write). - * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 0 (audio, read/write). - * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 1 (telecom, read/write). - * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) - * Data Register 2 (CODEC registers, read/write). - * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) - * Status Register (read/write). - * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) - * Control Register 1 (read/write). - * [The MCCR1 register is only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] + * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 0 (read/write). + * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 0 (audio, read/write). + * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 1 (telecom, read/write). + * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP) + * Data Register 2 (CODEC registers, read/write). + * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP) + * Status Register (read/write). + * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP) + * Control Register 1 (read/write). + * [The MCCR1 register is only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] * * Clocks - * fmc, Tmc Frequency, period of the MCP communication (10 MHz, - * 12 MHz, or GPIO [21]). + * fmc, Tmc Frequency, period of the MCP communication (10 MHz, + * 12 MHz, or GPIO [21]). * faud, Taud Frequency, period of the audio sampling. * ftcm, Ttcm Frequency, period of the telecom sampling. */ #define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */ -#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ - /* (audio) */ -#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ - /* (telecom) */ -#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ - /* (CODEC reg.) */ -#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ +#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */ + /* (audio) */ +#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */ + /* (telecom) */ +#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */ + /* (CODEC reg.) */ +#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */ #define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */ #if LANGUAGE == C -#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ +#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser4MCCR0))) -#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ - /* (audio) */ \ +#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \ + /* (audio) */ \ (*((volatile Word *) io_p2v (_Ser4MCDR0))) -#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ - /* (telecom) */ \ +#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \ + /* (telecom) */ \ (*((volatile Word *) io_p2v (_Ser4MCDR1))) -#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ - /* (CODEC reg.) */ \ +#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \ + /* (CODEC reg.) */ \ (*((volatile Word *) io_p2v (_Ser4MCDR2))) -#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ +#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \ (*((volatile Word *) io_p2v (_Ser4MCSR))) -#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ +#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser4MCCR1))) #endif /* LANGUAGE == C */ #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */ - /* [6..127] */ - /* faud = fmc/(32*ASD) */ - /* Taud = 32*ASD*Tmc */ -#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ - /* [192..4064] */ \ + /* [6..127] */ + /* faud = fmc/(32*ASD) */ + /* Taud = 32*ASD*Tmc */ +#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \ + /* [192..4064] */ \ ((Div)/32 << FShft (MCCR0_ASD)) /* faud = fmc/(32*Floor (Div/32)) */ /* Taud = 32*Floor (Div/32)*Tmc */ @@ -916,12 +916,12 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; (((Div) + 31)/32 << FShft (MCCR0_ASD)) /* faud = fmc/(32*Ceil (Div/32)) */ /* Taud = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ - /* Divisor/32 [16..127] */ - /* ftcm = fmc/(32*TSD) */ - /* Ttcm = 32*TSD*Tmc */ -#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ - /* [512..4064] */ \ +#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */ + /* Divisor/32 [16..127] */ + /* ftcm = fmc/(32*TSD) */ + /* Ttcm = 32*TSD*Tmc */ +#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \ + /* [512..4064] */ \ ((Div)/32 << FShft (MCCR0_TSD)) /* ftcm = fmc/(32*Floor (Div/32)) */ /* Ttcm = 32*Floor (Div/32)*Tmc */ @@ -929,460 +929,460 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; (((Div) + 31)/32 << FShft (MCCR0_TSD)) /* ftcm = fmc/(32*Ceil (Div/32)) */ /* Ttcm = 32*Ceil (Div/32)*Tmc */ -#define MCCR0_MCE 0x00010000 /* MCP Enable */ -#define MCCR0_ECS 0x00020000 /* External Clock Select */ +#define MCCR0_MCE 0x00010000 /* MCP Enable */ +#define MCCR0_ECS 0x00020000 /* External Clock Select */ #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */ -#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ -#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ - /* sampling/storing Mode */ -#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ +#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */ +#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */ + /* sampling/storing Mode */ +#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */ #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */ #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ + /* or less interrupt Enable */ #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */ - /* or more interrupt Enable */ + /* or more interrupt Enable */ #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */ - /* or less interrupt Enable */ + /* or less interrupt Enable */ #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */ - /* more interrupt Enable */ -#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ + /* more interrupt Enable */ +#define MCCR0_LBM 0x00800000 /* Look-Back Mode */ #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */ -#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ +#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \ (((Div) - 1) << FShft (MCCR0_ECP)) -#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ - /* FIFOs */ +#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */ + /* FIFOs */ #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */ - /* FIFOs */ + /* FIFOs */ - /* receive/transmit CODEC reg. */ - /* FIFOs: */ -#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ -#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ -#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ -#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ -#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ + /* receive/transmit CODEC reg. */ + /* FIFOs: */ +#define MCDR2_DATA Fld (16, 0) /* reg. DATA */ +#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */ +#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */ +#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */ +#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */ #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */ /* or less Service request (read) */ #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */ - /* more Service request (read) */ + /* more Service request (read) */ #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */ /* or less Service request (read) */ #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */ /* or more Service request (read) */ #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */ -#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ +#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */ #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */ #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */ #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */ - /* (read) */ + /* (read) */ #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */ - /* (read) */ + /* (read) */ #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */ - /* (read) */ + /* (read) */ #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */ - /* (read) */ + /* (read) */ #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */ - /* (read) */ + /* (read) */ #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */ - /* (read) */ -#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ + /* (read) */ +#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */ #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */ -#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ -#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ - /* (11.981 MHz) */ -#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ - /* (9.585 MHz) */ +#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */ +#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */ + /* (11.981 MHz) */ +#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */ + /* (9.585 MHz) */ /* * Synchronous Serial Port (SSP) control registers * * Registers - * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 0 (read/write). - * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control - * Register 1 (read/write). - * [Bits SPO and SP are only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data - * Register (read/write). - * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status - * Register (read/write). + * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 0 (read/write). + * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control + * Register 1 (read/write). + * [Bits SPO and SP are only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data + * Register (read/write). + * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status + * Register (read/write). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). - * fss, Tss Frequency, period of the SSP communication. + * or 3.5795 MHz). + * fss, Tss Frequency, period of the SSP communication. */ #define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */ #define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */ -#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ -#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ +#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */ +#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */ #if LANGUAGE == C -#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ +#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_Ser4SSCR0))) -#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ +#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_Ser4SSCR1))) -#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ +#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \ (*((volatile Word *) io_p2v (_Ser4SSDR))) -#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ +#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \ (*((volatile Word *) io_p2v (_Ser4SSSR))) #endif /* LANGUAGE == C */ #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */ -#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ +#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \ (((Size) - 1) << FShft (SSCR0_DSS)) -#define SSCR0_FRF Fld (2, 4) /* FRame Format */ -#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ - /* Interface (SPI) format */ \ +#define SSCR0_FRF Fld (2, 4) /* FRame Format */ +#define SSCR0_Motorola /* Motorola Serial Peripheral */ \ + /* Interface (SPI) format */ \ (0 << FShft (SSCR0_FRF)) -#define SSCR0_TI /* Texas Instruments Synchronous */ \ - /* Serial format */ \ +#define SSCR0_TI /* Texas Instruments Synchronous */ \ + /* Serial format */ \ (1 << FShft (SSCR0_FRF)) -#define SSCR0_National /* National Microwire format */ \ +#define SSCR0_National /* National Microwire format */ \ (2 << FShft (SSCR0_FRF)) -#define SSCR0_SSE 0x00000080 /* SSP Enable */ +#define SSCR0_SSE 0x00000080 /* SSP Enable */ #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */ - /* fss = fxtl/(2*(SCR + 1)) */ - /* Tss = 2*(SCR + 1)*Txtl */ -#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ + /* fss = fxtl/(2*(SCR + 1)) */ + /* Tss = 2*(SCR + 1)*Txtl */ +#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \ (((Div) - 2)/2 << FShft (SSCR0_SCR)) /* fss = fxtl/(2*Floor (Div/2)) */ - /* Tss = 2*Floor (Div/2)*Txtl */ + /* Tss = 2*Floor (Div/2)*Txtl */ #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \ (((Div) - 1)/2 << FShft (SSCR0_SCR)) /* fss = fxtl/(2*Ceil (Div/2)) */ - /* Tss = 2*Ceil (Div/2)*Txtl */ + /* Tss = 2*Ceil (Div/2)*Txtl */ #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */ - /* Interrupt Enable */ + /* Interrupt Enable */ #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */ - /* Interrupt Enable */ -#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ + /* Interrupt Enable */ +#define SSCR1_LBM 0x00000004 /* Look-Back Mode */ #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */ -#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ -#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ -#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ +#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */ +#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */ +#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */ #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */ /* after frame (SFRM, 1st edge) */ #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */ /* after frame (SFRM, 1st edge) */ -#define SSCR1_ECS 0x00000020 /* External Clock Select */ -#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ -#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ +#define SSCR1_ECS 0x00000020 /* External Clock Select */ +#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */ +#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */ -#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ +#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */ #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */ #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */ -#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ +#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */ #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */ - /* Service request (read) */ + /* Service request (read) */ #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */ - /* Service request (read) */ -#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ + /* Service request (read) */ +#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */ /* * Operating System (OS) timer control registers * * Registers - * OSMR0 Operating System (OS) timer Match Register 0 - * (read/write). - * OSMR1 Operating System (OS) timer Match Register 1 - * (read/write). - * OSMR2 Operating System (OS) timer Match Register 2 - * (read/write). - * OSMR3 Operating System (OS) timer Match Register 3 - * (read/write). - * OSCR Operating System (OS) timer Counter Register - * (read/write). - * OSSR Operating System (OS) timer Status Register - * (read/write). - * OWER Operating System (OS) timer Watch-dog Enable Register - * (read/write). - * OIER Operating System (OS) timer Interrupt Enable Register - * (read/write). + * OSMR0 Operating System (OS) timer Match Register 0 + * (read/write). + * OSMR1 Operating System (OS) timer Match Register 1 + * (read/write). + * OSMR2 Operating System (OS) timer Match Register 2 + * (read/write). + * OSMR3 Operating System (OS) timer Match Register 3 + * (read/write). + * OSCR Operating System (OS) timer Counter Register + * (read/write). + * OSSR Operating System (OS) timer Status Register + * (read/write). + * OWER Operating System (OS) timer Watch-dog Enable Register + * (read/write). + * OIER Operating System (OS) timer Interrupt Enable Register + * (read/write). */ -#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ +#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \ (0x90000000 + (Nb)*4) -#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ -#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ -#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ -#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ -#define _OSCR 0x90000010 /* OS timer Counter Reg. */ -#define _OSSR 0x90000014 /* OS timer Status Reg. */ -#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ -#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ +#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */ +#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */ +#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */ +#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */ +#define _OSCR 0x90000010 /* OS timer Counter Reg. */ +#define _OSSR 0x90000014 /* OS timer Status Reg. */ +#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */ +#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */ #if LANGUAGE == C -#define OSMR /* OS timer Match Reg. [0..3] */ \ +#define OSMR /* OS timer Match Reg. [0..3] */ \ ((volatile Word *) io_p2v (_OSMR (0))) -#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ -#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ -#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ -#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ -#define OSCR /* OS timer Counter Reg. */ \ +#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */ +#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */ +#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */ +#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */ +#define OSCR /* OS timer Counter Reg. */ \ (*((volatile Word *) io_p2v (_OSCR))) -#define OSSR /* OS timer Status Reg. */ \ +#define OSSR /* OS timer Status Reg. */ \ (*((volatile Word *) io_p2v (_OSSR))) -#define OWER /* OS timer Watch-dog Enable Reg. */ \ +#define OWER /* OS timer Watch-dog Enable Reg. */ \ (*((volatile Word *) io_p2v (_OWER))) -#define OIER /* OS timer Interrupt Enable Reg. */ \ +#define OIER /* OS timer Interrupt Enable Reg. */ \ (*((volatile Word *) io_p2v (_OIER))) #endif /* LANGUAGE == C */ -#define OSSR_M(Nb) /* Match detected [0..3] */ \ +#define OSSR_M(Nb) /* Match detected [0..3] */ \ (0x00000001 << (Nb)) -#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ -#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ -#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ -#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ +#define OSSR_M0 OSSR_M (0) /* Match detected 0 */ +#define OSSR_M1 OSSR_M (1) /* Match detected 1 */ +#define OSSR_M2 OSSR_M (2) /* Match detected 2 */ +#define OSSR_M3 OSSR_M (3) /* Match detected 3 */ -#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ - /* (set only) */ +#define OWER_WME 0x00000001 /* Watch-dog Match Enable */ + /* (set only) */ -#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ +#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ (0x00000001 << (Nb)) -#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ -#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ -#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ -#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ +#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */ +#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */ +#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */ +#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */ /* * Real-Time Clock (RTC) control registers * * Registers - * RTAR Real-Time Clock (RTC) Alarm Register (read/write). - * RCNR Real-Time Clock (RTC) CouNt Register (read/write). - * RTTR Real-Time Clock (RTC) Trim Register (read/write). - * RTSR Real-Time Clock (RTC) Status Register (read/write). + * RTAR Real-Time Clock (RTC) Alarm Register (read/write). + * RCNR Real-Time Clock (RTC) CouNt Register (read/write). + * RTTR Real-Time Clock (RTC) Trim Register (read/write). + * RTSR Real-Time Clock (RTC) Status Register (read/write). * * Clocks * frtx, Trtx Frequency, period of the real-time clock crystal - * (32.768 kHz nominal). + * (32.768 kHz nominal). * frtc, Trtc Frequency, period of the real-time clock counter - * (1 Hz nominal). + * (1 Hz nominal). */ -#define _RTAR 0x90010000 /* RTC Alarm Reg. */ -#define _RCNR 0x90010004 /* RTC CouNt Reg. */ -#define _RTTR 0x90010008 /* RTC Trim Reg. */ -#define _RTSR 0x90010010 /* RTC Status Reg. */ +#define _RTAR 0x90010000 /* RTC Alarm Reg. */ +#define _RCNR 0x90010004 /* RTC CouNt Reg. */ +#define _RTTR 0x90010008 /* RTC Trim Reg. */ +#define _RTSR 0x90010010 /* RTC Status Reg. */ #if LANGUAGE == C -#define RTAR /* RTC Alarm Reg. */ \ +#define RTAR /* RTC Alarm Reg. */ \ (*((volatile Word *) io_p2v (_RTAR))) -#define RCNR /* RTC CouNt Reg. */ \ +#define RCNR /* RTC CouNt Reg. */ \ (*((volatile Word *) io_p2v (_RCNR))) -#define RTTR /* RTC Trim Reg. */ \ +#define RTTR /* RTC Trim Reg. */ \ (*((volatile Word *) io_p2v (_RTTR))) -#define RTSR /* RTC Status Reg. */ \ +#define RTSR /* RTC Status Reg. */ \ (*((volatile Word *) io_p2v (_RTSR))) #endif /* LANGUAGE == C */ -#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ -#define RTTR_D Fld (10, 16) /* trim Delete count */ +#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */ +#define RTTR_D Fld (10, 16) /* trim Delete count */ /* frtc = (1023*(C + 1) - D)*frtx/ */ - /* (1023*(C + 1)^2) */ + /* (1023*(C + 1)^2) */ /* Trtc = (1023*(C + 1)^2)*Trtx/ */ - /* (1023*(C + 1) - D) */ + /* (1023*(C + 1) - D) */ -#define RTSR_AL 0x00000001 /* ALarm detected */ -#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ -#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ -#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ +#define RTSR_AL 0x00000001 /* ALarm detected */ +#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */ +#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */ +#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */ /* * Power Manager (PM) control registers * * Registers - * PMCR Power Manager (PM) Control Register (read/write). - * PSSR Power Manager (PM) Sleep Status Register (read/write). - * PSPR Power Manager (PM) Scratch-Pad Register (read/write). - * PWER Power Manager (PM) Wake-up Enable Register - * (read/write). - * PCFR Power Manager (PM) general ConFiguration Register - * (read/write). - * PPCR Power Manager (PM) Phase-Locked Loop (PLL) - * Configuration Register (read/write). - * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) - * Sleep state Register (read/write, see GPIO pins). - * POSR Power Manager (PM) Oscillator Status Register (read). + * PMCR Power Manager (PM) Control Register (read/write). + * PSSR Power Manager (PM) Sleep Status Register (read/write). + * PSPR Power Manager (PM) Scratch-Pad Register (read/write). + * PWER Power Manager (PM) Wake-up Enable Register + * (read/write). + * PCFR Power Manager (PM) general ConFiguration Register + * (read/write). + * PPCR Power Manager (PM) Phase-Locked Loop (PLL) + * Configuration Register (read/write). + * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO) + * Sleep state Register (read/write, see GPIO pins). + * POSR Power Manager (PM) Oscillator Status Register (read). * * Clocks * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz - * or 3.5795 MHz). + * or 3.5795 MHz). * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). */ -#define _PMCR 0x90020000 /* PM Control Reg. */ -#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ -#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ -#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ -#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ -#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ -#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ -#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ +#define _PMCR 0x90020000 /* PM Control Reg. */ +#define _PSSR 0x90020004 /* PM Sleep Status Reg. */ +#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */ +#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */ +#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */ +#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */ +#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */ +#define _POSR 0x9002001C /* PM Oscillator Status Reg. */ #if LANGUAGE == C -#define PMCR /* PM Control Reg. */ \ +#define PMCR /* PM Control Reg. */ \ (*((volatile Word *) io_p2v (_PMCR))) -#define PSSR /* PM Sleep Status Reg. */ \ +#define PSSR /* PM Sleep Status Reg. */ \ (*((volatile Word *) io_p2v (_PSSR))) -#define PSPR /* PM Scratch-Pad Reg. */ \ +#define PSPR /* PM Scratch-Pad Reg. */ \ (*((volatile Word *) io_p2v (_PSPR))) -#define PWER /* PM Wake-up Enable Reg. */ \ +#define PWER /* PM Wake-up Enable Reg. */ \ (*((volatile Word *) io_p2v (_PWER))) -#define PCFR /* PM general ConFiguration Reg. */ \ +#define PCFR /* PM general ConFiguration Reg. */ \ (*((volatile Word *) io_p2v (_PCFR))) -#define PPCR /* PM PLL Configuration Reg. */ \ +#define PPCR /* PM PLL Configuration Reg. */ \ (*((volatile Word *) io_p2v (_PPCR))) -#define PGSR /* PM GPIO Sleep state Reg. */ \ +#define PGSR /* PM GPIO Sleep state Reg. */ \ (*((volatile Word *) io_p2v (_PGSR))) -#define POSR /* PM Oscillator Status Reg. */ \ +#define POSR /* PM Oscillator Status Reg. */ \ (*((volatile Word *) io_p2v (_POSR))) #elif LANGUAGE == Assembly -#define PMCR (io_p2v (_PMCR)) -#define PSSR (io_p2v (_PSSR)) -#define PSPR (io_p2v (_PSPR)) -#define PWER (io_p2v (_PWER)) -#define PCFR (io_p2v (_PCFR)) -#define PPCR (io_p2v (_PPCR)) -#define PGSR (io_p2v (_PGSR)) -#define POSR (io_p2v (_POSR)) +#define PMCR (io_p2v (_PMCR)) +#define PSSR (io_p2v (_PSSR)) +#define PSPR (io_p2v (_PSPR)) +#define PWER (io_p2v (_PWER)) +#define PCFR (io_p2v (_PCFR)) +#define PPCR (io_p2v (_PPCR)) +#define PGSR (io_p2v (_PGSR)) +#define POSR (io_p2v (_POSR)) #endif /* LANGUAGE == C */ -#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ +#define PMCR_SF 0x00000001 /* Sleep Force (set only) */ -#define PSSR_SS 0x00000001 /* Software Sleep */ -#define PSSR_BFS 0x00000002 /* Battery Fault Status */ - /* (BATT_FAULT) */ +#define PSSR_SS 0x00000001 /* Software Sleep */ +#define PSSR_BFS 0x00000002 /* Battery Fault Status */ + /* (BATT_FAULT) */ #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */ -#define PSSR_DH 0x00000008 /* DRAM control Hold */ -#define PSSR_PH 0x00000010 /* Peripheral control Hold */ - -#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ -#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ -#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ -#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ -#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ -#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ -#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ -#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ -#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ -#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ -#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ -#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ -#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ -#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ -#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ -#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ -#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ -#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ -#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ -#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ -#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ -#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ -#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ -#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ -#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ -#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ -#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ -#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ -#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ -#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ +#define PSSR_DH 0x00000008 /* DRAM control Hold */ +#define PSSR_PH 0x00000010 /* Peripheral control Hold */ + +#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ +#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */ +#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */ +#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */ +#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */ +#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */ +#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */ +#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */ +#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */ +#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */ +#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */ +#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */ +#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */ +#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */ +#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */ +#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */ +#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */ +#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */ +#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */ +#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */ +#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */ +#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */ +#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */ +#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */ +#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */ +#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */ +#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */ +#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */ +#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */ +#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */ #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */ #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */ #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */ -#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ -#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ -#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ -#define PCFR_FS 0x00000004 /* Float Static memory pins */ +#define PCFR_FP 0x00000002 /* Float PCMCIA pins */ +#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */ +#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */ +#define PCFR_FS 0x00000004 /* Float Static memory pins */ #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */ #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */ -#define PCFR_FO 0x00000008 /* Force RTC oscillator */ - /* (32.768 kHz) enable On */ +#define PCFR_FO 0x00000008 /* Force RTC oscillator */ + /* (32.768 kHz) enable On */ -#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ -#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ +#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */ +#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \ (0x00 << FShft (PPCR_CCF)) -#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ +#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \ (0x01 << FShft (PPCR_CCF)) -#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ +#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \ (0x02 << FShft (PPCR_CCF)) -#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ +#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \ (0x03 << FShft (PPCR_CCF)) -#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ +#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \ (0x04 << FShft (PPCR_CCF)) -#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ +#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \ (0x05 << FShft (PPCR_CCF)) -#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ +#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \ (0x06 << FShft (PPCR_CCF)) -#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ +#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \ (0x07 << FShft (PPCR_CCF)) -#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ +#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \ (0x08 << FShft (PPCR_CCF)) -#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ +#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \ (0x09 << FShft (PPCR_CCF)) -#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ +#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \ (0x0A << FShft (PPCR_CCF)) -#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ +#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \ (0x0B << FShft (PPCR_CCF)) -#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ +#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \ (0x0C << FShft (PPCR_CCF)) -#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ +#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \ (0x0D << FShft (PPCR_CCF)) -#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ +#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \ (0x0E << FShft (PPCR_CCF)) -#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ +#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \ (0x0F << FShft (PPCR_CCF)) - /* 3.6864 MHz crystal (fxtl): */ -#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ -#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ -#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ -#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ -#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ -#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ -#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ -#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ -#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ -#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ -#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ -#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ -#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ -#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ -#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ -#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ - /* 3.5795 MHz crystal (fxtl): */ -#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ -#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ -#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ -#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ -#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ -#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ -#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ -#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ -#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ -#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ -#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ -#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ -#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ -#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ -#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ -#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ + /* 3.6864 MHz crystal (fxtl): */ +#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */ +#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */ +#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */ +#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */ +#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */ +#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */ +#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */ +#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */ +#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */ +#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */ +#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */ +#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */ +#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */ +#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */ +#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */ +#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */ + /* 3.5795 MHz crystal (fxtl): */ +#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */ +#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */ +#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */ +#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */ +#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */ +#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */ +#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */ +#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */ +#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */ +#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */ +#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */ +#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */ +#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */ +#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */ +#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */ +#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */ #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */ @@ -1391,75 +1391,75 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Reset Controller (RC) control registers * * Registers - * RSRR Reset Controller (RC) Software Reset Register - * (read/write). - * RCSR Reset Controller (RC) Status Register (read/write). + * RSRR Reset Controller (RC) Software Reset Register + * (read/write). + * RCSR Reset Controller (RC) Status Register (read/write). */ -#define _RSRR 0x90030000 /* RC Software Reset Reg. */ -#define _RCSR 0x90030004 /* RC Status Reg. */ +#define _RSRR 0x90030000 /* RC Software Reset Reg. */ +#define _RCSR 0x90030004 /* RC Status Reg. */ #if LANGUAGE == C -#define RSRR /* RC Software Reset Reg. */ \ +#define RSRR /* RC Software Reset Reg. */ \ (*((volatile Word *) io_p2v (_RSRR))) -#define RCSR /* RC Status Reg. */ \ +#define RCSR /* RC Status Reg. */ \ (*((volatile Word *) io_p2v (_RCSR))) #endif /* LANGUAGE == C */ -#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ +#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */ -#define RCSR_HWR 0x00000001 /* HardWare Reset */ -#define RCSR_SWR 0x00000002 /* SoftWare Reset */ -#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ -#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ +#define RCSR_HWR 0x00000001 /* HardWare Reset */ +#define RCSR_SWR 0x00000002 /* SoftWare Reset */ +#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */ +#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */ /* * Test unit control registers * * Registers - * TUCR Test Unit Control Register (read/write). + * TUCR Test Unit Control Register (read/write). */ -#define _TUCR 0x90030008 /* Test Unit Control Reg. */ +#define _TUCR 0x90030008 /* Test Unit Control Reg. */ #if LANGUAGE == C -#define TUCR /* Test Unit Control Reg. */ \ +#define TUCR /* Test Unit Control Reg. */ \ (*((volatile Word *) io_p2v (_TUCR))) #endif /* LANGUAGE == C */ -#define TUCR_TIC 0x00000040 /* TIC mode */ -#define TUCR_TTST 0x00000080 /* Trim TeST mode */ -#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ - /* Check */ -#define TUCR_PMD 0x00000200 /* Power Management Disable */ -#define TUCR_MR 0x00000400 /* Memory Request mode */ +#define TUCR_TIC 0x00000040 /* TIC mode */ +#define TUCR_TTST 0x00000080 /* Trim TeST mode */ +#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */ + /* Check */ +#define TUCR_PMD 0x00000200 /* Power Management Disable */ +#define TUCR_MR 0x00000400 /* Memory Request mode */ #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */ #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */ /* grant (MBGNT) on GPIO [22:21] */ -#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ -#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ +#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */ +#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */ #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */ #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */ -#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ +#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */ #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */ -#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ +#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \ (0 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ +#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \ (1 << FShft (TUCR_TSEL)) -#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ +#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \ (2 << FShft (TUCR_TSEL)) -#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ +#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \ (3 << FShft (TUCR_TSEL)) -#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ - /* Clocks on GPIO [26:27] */ \ +#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \ + /* Clocks on GPIO [26:27] */ \ (4 << FShft (TUCR_TSEL)) -#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ - /* (Alternative) */ \ +#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \ + /* (Alternative) */ \ (5 << FShft (TUCR_TSEL)) -#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ +#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \ (6 << FShft (TUCR_TSEL)) -#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ +#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \ (7 << FShft (TUCR_TSEL)) @@ -1467,52 +1467,52 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * General-Purpose Input/Output (GPIO) control registers * * Registers - * GPLR General-Purpose Input/Output (GPIO) Pin Level - * Register (read). - * GPDR General-Purpose Input/Output (GPIO) Pin Direction - * Register (read/write). - * GPSR General-Purpose Input/Output (GPIO) Pin output Set - * Register (write). - * GPCR General-Purpose Input/Output (GPIO) Pin output Clear - * Register (write). - * GRER General-Purpose Input/Output (GPIO) Rising-Edge - * detect Register (read/write). - * GFER General-Purpose Input/Output (GPIO) Falling-Edge - * detect Register (read/write). - * GEDR General-Purpose Input/Output (GPIO) Edge Detect - * status Register (read/write). - * GAFR General-Purpose Input/Output (GPIO) Alternate - * Function Register (read/write). + * GPLR General-Purpose Input/Output (GPIO) Pin Level + * Register (read). + * GPDR General-Purpose Input/Output (GPIO) Pin Direction + * Register (read/write). + * GPSR General-Purpose Input/Output (GPIO) Pin output Set + * Register (write). + * GPCR General-Purpose Input/Output (GPIO) Pin output Clear + * Register (write). + * GRER General-Purpose Input/Output (GPIO) Rising-Edge + * detect Register (read/write). + * GFER General-Purpose Input/Output (GPIO) Falling-Edge + * detect Register (read/write). + * GEDR General-Purpose Input/Output (GPIO) Edge Detect + * status Register (read/write). + * GAFR General-Purpose Input/Output (GPIO) Alternate + * Function Register (read/write). * * Clock * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). */ -#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ -#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ -#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ -#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ -#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ -#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ -#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ -#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ +#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */ +#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */ +#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */ +#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */ +#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */ +#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */ +#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */ +#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */ #if LANGUAGE == C -#define GPLR /* GPIO Pin Level Reg. */ \ +#define GPLR /* GPIO Pin Level Reg. */ \ (*((volatile Word *) io_p2v (_GPLR))) -#define GPDR /* GPIO Pin Direction Reg. */ \ +#define GPDR /* GPIO Pin Direction Reg. */ \ (*((volatile Word *) io_p2v (_GPDR))) -#define GPSR /* GPIO Pin output Set Reg. */ \ +#define GPSR /* GPIO Pin output Set Reg. */ \ (*((volatile Word *) io_p2v (_GPSR))) -#define GPCR /* GPIO Pin output Clear Reg. */ \ +#define GPCR /* GPIO Pin output Clear Reg. */ \ (*((volatile Word *) io_p2v (_GPCR))) -#define GRER /* GPIO Rising-Edge detect Reg. */ \ +#define GRER /* GPIO Rising-Edge detect Reg. */ \ (*((volatile Word *) io_p2v (_GRER))) -#define GFER /* GPIO Falling-Edge detect Reg. */ \ +#define GFER /* GPIO Falling-Edge detect Reg. */ \ (*((volatile Word *) io_p2v (_GFER))) -#define GEDR /* GPIO Edge Detect status Reg. */ \ +#define GEDR /* GPIO Edge Detect status Reg. */ \ (*((volatile Word *) io_p2v (_GEDR))) -#define GAFR /* GPIO Alternate Function Reg. */ \ +#define GAFR /* GPIO Alternate Function Reg. */ \ (*((volatile Word *) io_p2v (_GAFR))) #elif LANGUAGE == Assembly @@ -1530,280 +1530,280 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define GPIO_MIN (0) #define GPIO_MAX (27) -#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ +#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ (0x00000001 << (Nb)) -#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ -#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ -#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ -#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ -#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ -#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ -#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ -#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ -#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ -#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ -#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ -#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ -#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ -#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ -#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ -#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ -#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ -#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ -#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ -#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ -#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ -#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ -#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ -#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ -#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ -#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ -#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ -#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ - -#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ +#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */ +#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */ +#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */ +#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */ +#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */ +#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */ +#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */ +#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */ +#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */ +#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */ +#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */ +#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */ +#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */ +#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */ +#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */ +#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */ +#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */ +#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */ +#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */ +#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */ +#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */ +#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */ +#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */ +#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */ +#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */ +#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */ +#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */ +#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */ + +#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ GPIO_GPIO ((Nb) - 6) -#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ -#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ -#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ -#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ -#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ -#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ -#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ -#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ - /* ser. port 4: */ -#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ -#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ -#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ -#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ - /* ser. port 1: */ -#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ -#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ -#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ -#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ -#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ - /* ser. port 4: */ -#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ - /* ser. port 3: */ -#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ - /* ser. port 4: */ -#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ - /* test controller: */ -#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ -#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ -#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ -#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ -#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ -#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ +#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */ +#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */ +#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */ +#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */ +#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */ +#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */ +#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */ +#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */ + /* ser. port 4: */ +#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */ +#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */ +#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */ +#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */ + /* ser. port 1: */ +#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */ +#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */ +#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */ +#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */ +#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */ + /* ser. port 4: */ +#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */ + /* ser. port 3: */ +#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */ + /* ser. port 4: */ +#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */ + /* test controller: */ +#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */ +#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */ +#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */ +#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */ +#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */ +#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */ #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */ -#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ +#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */ -#define GPDR_In 0 /* Input */ -#define GPDR_Out 1 /* Output */ +#define GPDR_In 0 /* Input */ +#define GPDR_Out 1 /* Output */ /* * Interrupt Controller (IC) control registers * * Registers - * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) - * Pending register (read). - * ICMR Interrupt Controller (IC) Mask Register (read/write). - * ICLR Interrupt Controller (IC) Level Register (read/write). - * ICCR Interrupt Controller (IC) Control Register - * (read/write). - * [The ICCR register is only implemented in versions 2.0 - * (rev. = 8) and higher of the StrongARM SA-1100.] - * ICFP Interrupt Controller (IC) Fast Interrupt reQuest - * (FIQ) Pending register (read). - * ICPR Interrupt Controller (IC) Pending Register (read). - * [The ICPR register is active low (inverted) in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it is active high (non-inverted) in - * versions 2.0 (rev. = 8) and higher.] + * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ) + * Pending register (read). + * ICMR Interrupt Controller (IC) Mask Register (read/write). + * ICLR Interrupt Controller (IC) Level Register (read/write). + * ICCR Interrupt Controller (IC) Control Register + * (read/write). + * [The ICCR register is only implemented in versions 2.0 + * (rev. = 8) and higher of the StrongARM SA-1100.] + * ICFP Interrupt Controller (IC) Fast Interrupt reQuest + * (FIQ) Pending register (read). + * ICPR Interrupt Controller (IC) Pending Register (read). + * [The ICPR register is active low (inverted) in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it is active high (non-inverted) in + * versions 2.0 (rev. = 8) and higher.] */ -#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ -#define _ICMR 0x90050004 /* IC Mask Reg. */ -#define _ICLR 0x90050008 /* IC Level Reg. */ -#define _ICCR 0x9005000C /* IC Control Reg. */ -#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ -#define _ICPR 0x90050020 /* IC Pending Reg. */ +#define _ICIP 0x90050000 /* IC IRQ Pending reg. */ +#define _ICMR 0x90050004 /* IC Mask Reg. */ +#define _ICLR 0x90050008 /* IC Level Reg. */ +#define _ICCR 0x9005000C /* IC Control Reg. */ +#define _ICFP 0x90050010 /* IC FIQ Pending reg. */ +#define _ICPR 0x90050020 /* IC Pending Reg. */ #if LANGUAGE == C -#define ICIP /* IC IRQ Pending reg. */ \ +#define ICIP /* IC IRQ Pending reg. */ \ (*((volatile Word *) io_p2v (_ICIP))) -#define ICMR /* IC Mask Reg. */ \ +#define ICMR /* IC Mask Reg. */ \ (*((volatile Word *) io_p2v (_ICMR))) -#define ICLR /* IC Level Reg. */ \ +#define ICLR /* IC Level Reg. */ \ (*((volatile Word *) io_p2v (_ICLR))) -#define ICCR /* IC Control Reg. */ \ +#define ICCR /* IC Control Reg. */ \ (*((volatile Word *) io_p2v (_ICCR))) -#define ICFP /* IC FIQ Pending reg. */ \ +#define ICFP /* IC FIQ Pending reg. */ \ (*((volatile Word *) io_p2v (_ICFP))) -#define ICPR /* IC Pending Reg. */ \ +#define ICPR /* IC Pending Reg. */ \ (*((volatile Word *) io_p2v (_ICPR))) #endif /* LANGUAGE == C */ -#define IC_GPIO(Nb) /* GPIO [0..10] */ \ +#define IC_GPIO(Nb) /* GPIO [0..10] */ \ (0x00000001 << (Nb)) -#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ -#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ -#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ -#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ -#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ -#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ -#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ -#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ -#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ -#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ -#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ -#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ -#define IC_LCD 0x00001000 /* LCD controller */ -#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ -#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ -#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ -#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ -#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ -#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ -#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ -#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ +#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */ +#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */ +#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */ +#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */ +#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */ +#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */ +#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */ +#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */ +#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */ +#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */ +#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */ +#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */ +#define IC_LCD 0x00001000 /* LCD controller */ +#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */ +#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */ +#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */ +#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */ +#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */ +#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */ +#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */ +#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ (0x00100000 << (Nb)) -#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ -#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ -#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ -#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ -#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ -#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ -#define IC_OST(Nb) /* OS Timer match [0..3] */ \ +#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */ +#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */ +#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */ +#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */ +#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */ +#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */ +#define IC_OST(Nb) /* OS Timer match [0..3] */ \ (0x04000000 << (Nb)) -#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ -#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ -#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ -#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ -#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ -#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ - -#define ICLR_IRQ 0 /* Interrupt ReQuest */ -#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ - -#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ - /* Mask */ +#define IC_OST0 IC_OST (0) /* OS Timer match 0 */ +#define IC_OST1 IC_OST (1) /* OS Timer match 1 */ +#define IC_OST2 IC_OST (2) /* OS Timer match 2 */ +#define IC_OST3 IC_OST (3) /* OS Timer match 3 */ +#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */ +#define IC_RTCAlrm 0x80000000 /* RTC Alarm */ + +#define ICLR_IRQ 0 /* Interrupt ReQuest */ +#define ICLR_FIQ 1 /* Fast Interrupt reQuest */ + +#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */ + /* Mask */ #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */ - /* (ICMR ignored) */ + /* (ICMR ignored) */ #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */ - /* enable (ICMR used) */ + /* enable (ICMR used) */ /* * Peripheral Pin Controller (PPC) control registers * * Registers - * PPDR Peripheral Pin Controller (PPC) Pin Direction - * Register (read/write). - * PPSR Peripheral Pin Controller (PPC) Pin State Register - * (read/write). - * PPAR Peripheral Pin Controller (PPC) Pin Assignment - * Register (read/write). - * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin - * Direction Register (read/write). - * PPFR Peripheral Pin Controller (PPC) Pin Flag Register - * (read). + * PPDR Peripheral Pin Controller (PPC) Pin Direction + * Register (read/write). + * PPSR Peripheral Pin Controller (PPC) Pin State Register + * (read/write). + * PPAR Peripheral Pin Controller (PPC) Pin Assignment + * Register (read/write). + * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin + * Direction Register (read/write). + * PPFR Peripheral Pin Controller (PPC) Pin Flag Register + * (read). */ -#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ -#define _PPSR 0x90060004 /* PPC Pin State Reg. */ -#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ -#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ - /* Reg. */ -#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ +#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */ +#define _PPSR 0x90060004 /* PPC Pin State Reg. */ +#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */ +#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */ + /* Reg. */ +#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */ #if LANGUAGE == C -#define PPDR /* PPC Pin Direction Reg. */ \ +#define PPDR /* PPC Pin Direction Reg. */ \ (*((volatile Word *) io_p2v (_PPDR))) -#define PPSR /* PPC Pin State Reg. */ \ +#define PPSR /* PPC Pin State Reg. */ \ (*((volatile Word *) io_p2v (_PPSR))) -#define PPAR /* PPC Pin Assignment Reg. */ \ +#define PPAR /* PPC Pin Assignment Reg. */ \ (*((volatile Word *) io_p2v (_PPAR))) -#define PSDR /* PPC Sleep-mode pin Direction */ \ - /* Reg. */ \ +#define PSDR /* PPC Sleep-mode pin Direction */ \ + /* Reg. */ \ (*((volatile Word *) io_p2v (_PSDR))) -#define PPFR /* PPC Pin Flag Reg. */ \ +#define PPFR /* PPC Pin Flag Reg. */ \ (*((volatile Word *) io_p2v (_PPFR))) #endif /* LANGUAGE == C */ -#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ +#define PPC_LDD(Nb) /* LCD Data [0..7] */ \ (0x00000001 << (Nb)) -#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ -#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ -#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ -#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ -#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ -#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ -#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ -#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ -#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ -#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ -#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ -#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ - /* ser. port 1: */ -#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ -#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ - /* ser. port 2: */ -#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ -#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ - /* ser. port 3: */ -#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ -#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ - /* ser. port 4: */ -#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ -#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ -#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ -#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ - -#define PPDR_In 0 /* Input */ -#define PPDR_Out 1 /* Output */ - - /* ser. port 1: */ -#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ -#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ -#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ - /* ser. port 4: */ -#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ +#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */ +#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */ +#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */ +#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */ +#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */ +#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */ +#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */ +#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */ +#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */ +#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */ +#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */ +#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */ + /* ser. port 1: */ +#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */ +#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */ + /* ser. port 2: */ +#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */ +#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */ + /* ser. port 3: */ +#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */ +#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */ + /* ser. port 4: */ +#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */ +#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */ +#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */ +#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */ + +#define PPDR_In 0 /* Input */ +#define PPDR_Out 1 /* Output */ + + /* ser. port 1: */ +#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */ +#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */ +#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */ + /* ser. port 4: */ +#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */ #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */ - /* & SFRM_C */ -#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ + /* & SFRM_C */ +#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */ -#define PSDR_OutL 0 /* Output Low in sleep mode */ -#define PSDR_Flt 1 /* Floating (input) in sleep mode */ +#define PSDR_OutL 0 /* Output Low in sleep mode */ +#define PSDR_Flt 1 /* Floating (input) in sleep mode */ -#define PPFR_LCD 0x00000001 /* LCD controller */ +#define PPFR_LCD 0x00000001 /* LCD controller */ #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */ #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */ -#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ -#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ -#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ -#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ -#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ -#define PPFR_PerEn 0 /* Peripheral Enabled */ -#define PPFR_PPCEn 1 /* PPC Enabled */ +#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */ +#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */ +#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */ +#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */ +#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */ +#define PPFR_PerEn 0 /* Peripheral Enabled */ +#define PPFR_PPCEn 1 /* PPC Enabled */ /* * Dynamic Random-Access Memory (DRAM) control registers * * Registers - * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) - * CoNFiGuration register (read/write). - * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 0 - * (read/write). - * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 1 - * (read/write). - * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) - * Column Address Strobe (CAS) shift register 2 - * (read/write). + * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM) + * CoNFiGuration register (read/write). + * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 0 + * (read/write). + * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 1 + * (read/write). + * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM) + * Column Address Strobe (CAS) shift register 2 + * (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). @@ -1811,23 +1811,23 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * fcas, Tcas Frequency, period of the DRAM CAS shift registers. */ - /* Memory system: */ -#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ -#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ + /* Memory system: */ +#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */ +#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \ (0xA0000004 + (Nb)*4) -#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ -#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ -#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ +#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */ +#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */ +#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */ #if LANGUAGE == C - /* Memory system: */ -#define MDCNFG /* DRAM CoNFiGuration reg. */ \ + /* Memory system: */ +#define MDCNFG /* DRAM CoNFiGuration reg. */ \ (*((volatile Word *) io_p2v (_MDCNFG))) -#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ +#define MDCAS /* DRAM CAS shift reg. [0..3] */ \ ((volatile Word *) io_p2v (_MDCAS (0))) -#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ -#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ -#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ +#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */ +#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */ +#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */ #elif LANGUAGE == Assembly @@ -1836,58 +1836,58 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* LANGUAGE == C */ /* SA1100 MDCNFG values */ -#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ +#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ (0x00000001 << (Nb)) -#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ -#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ -#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ -#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ -#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ -#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ +#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */ +#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */ +#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */ +#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */ +#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */ +#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \ (((Add) - 9) << FShft (MDCNFG_DRAC)) #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */ - /* (fcas = fcpu/2) */ + /* (fcas = fcpu/2) */ #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */ -#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ +#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \ (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ +#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \ (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP)) -#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ -#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ +#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */ +#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \ (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ +#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \ (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR)) -#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ -#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ +#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */ +#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \ ((Tcpu) << FShft (MDCNFG_TDL)) #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */ - /* [Tmem] */ -#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ - /* [0..262136 Tcpu] */ \ + /* [Tmem] */ +#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \ + /* [0..262136 Tcpu] */ \ ((Tcpu)/8 << FShft (MDCNFG_DRI)) /* SA1110 MDCNFG values */ -#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */ #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */ - /* bank 0/1 */ + /* bank 0/1 */ #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/ - /* deassertion 0/1 */ + /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */ -#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ -#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ +#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */ +#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */ #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */ -#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ +#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */ #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */ - /* bank 0/1 */ + /* bank 0/1 */ #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */ -#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ +#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */ #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/ - /* deassertion 0/1 */ + /* deassertion 0/1 */ #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */ @@ -1895,32 +1895,32 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Static memory control registers * * Registers - * MSC0 Memory system: Static memory Control register 0 - * (read/write). - * MSC1 Memory system: Static memory Control register 1 - * (read/write). + * MSC0 Memory system: Static memory Control register 0 + * (read/write). + * MSC1 Memory system: Static memory Control register 1 + * (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). */ - /* Memory system: */ -#define _MSC(Nb) /* Static memory Control reg. */ \ - /* [0..1] */ \ + /* Memory system: */ +#define _MSC(Nb) /* Static memory Control reg. */ \ + /* [0..1] */ \ (0xA0000010 + (Nb)*4) -#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ -#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ +#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */ +#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */ #define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */ #if LANGUAGE == C - /* Memory system: */ -#define MSC /* Static memory Control reg. */ \ - /* [0..1] */ \ + /* Memory system: */ +#define MSC /* Static memory Control reg. */ \ + /* [0..1] */ \ ((volatile Word *) io_p2v (_MSC (0))) -#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ -#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ -#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ +#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */ +#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */ +#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */ #elif LANGUAGE == Assembly @@ -1930,54 +1930,54 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #endif /* LANGUAGE == C */ -#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ +#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ Fld (16, ((Nb) Modulo 2)*16) -#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ -#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ -#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ -#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ +#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */ +#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */ +#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */ +#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */ -#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ -#define MSC_NonBrst /* Non-Burst static memory */ \ +#define MSC_RT Fld (2, 0) /* ROM/static memory Type */ +#define MSC_NonBrst /* Non-Burst static memory */ \ (0 << FShft (MSC_RT)) -#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ +#define MSC_SRAM /* 32-bit byte-writable SRAM */ \ (1 << FShft (MSC_RT)) -#define MSC_Brst4 /* Burst-of-4 static memory */ \ +#define MSC_Brst4 /* Burst-of-4 static memory */ \ (2 << FShft (MSC_RT)) -#define MSC_Brst8 /* Burst-of-8 static memory */ \ +#define MSC_Brst8 /* Burst-of-8 static memory */ \ (3 << FShft (MSC_RT)) -#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ -#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ -#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ -#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ - /* First access - 1(.5) [Tmem] */ -#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ +#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */ +#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */ +#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */ +#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */ + /* First access - 1(.5) [Tmem] */ +#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \ /* static memory) [3..65 Tcpu] */ \ ((((Tcpu) - 3)/2) << FShft (MSC_RDF)) -#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ +#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ +#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDF)) -#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ +#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDF)) -#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ - /* Next access - 1 [Tmem] */ -#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ +#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */ + /* Next access - 1 [Tmem] */ +#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ +#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ +#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \ /* static memory) [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MSC_RDN)) -#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ +#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MSC_RDN)) -#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ - /* time/2 [Tmem] */ -#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ +#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */ + /* time/2 [Tmem] */ +#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \ (((Tcpu)/4) << FShft (MSC_RRR)) -#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ +#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \ ((((Tcpu) + 3)/4) << FShft (MSC_RRR)) @@ -1986,8 +1986,8 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * register * * Register - * MECR Memory system: Expansion memory bus (PCMCIA) - * Configuration Register (read/write). + * MECR Memory system: Expansion memory bus (PCMCIA) + * Configuration Register (read/write). * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). @@ -1995,37 +1995,37 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). */ - /* Memory system: */ -#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ - /* Configuration Reg. */ + /* Memory system: */ +#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */ + /* Configuration Reg. */ #if LANGUAGE == C - /* Memory system: */ -#define MECR /* Expansion memory bus (PCMCIA) */ \ - /* Configuration Reg. */ \ + /* Memory system: */ +#define MECR /* Expansion memory bus (PCMCIA) */ \ + /* Configuration Reg. */ \ (*((volatile Word *) io_p2v (_MECR))) #endif /* LANGUAGE == C */ -#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ +#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ Fld (15, (Nb)*16) -#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ -#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ +#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */ +#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */ -#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ -#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ +#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ +#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSIO)) -#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ +#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSIO)) -#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ - /* [Tmem] */ -#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ +#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ + /* [Tmem] */ +#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSA)) -#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ +#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSA)) #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */ -#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ +#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \ ((((Tcpu) - 2)/2) << FShft (MECR_BSM)) -#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ +#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \ ((((Tcpu) - 1)/2) << FShft (MECR_BSM)) /* @@ -2035,7 +2035,7 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; #define _MDREFR 0xA000001C #if LANGUAGE == C - /* Memory system: */ + /* Memory system: */ #define MDREFR \ (*((volatile Word *) io_p2v (_MDREFR))) @@ -2064,769 +2064,769 @@ typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ; * Direct Memory Access (DMA) control registers * * Registers - * DDAR0 Direct Memory Access (DMA) Device Address Register - * channel 0 (read/write). - * DCSR0 Direct Memory Access (DMA) Control and Status - * Register channel 0 (read/write). - * DBSA0 Direct Memory Access (DMA) Buffer Start address - * register A channel 0 (read/write). - * DBTA0 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 0 (read/write). - * DBSB0 Direct Memory Access (DMA) Buffer Start address - * register B channel 0 (read/write). - * DBTB0 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 0 (read/write). + * DDAR0 Direct Memory Access (DMA) Device Address Register + * channel 0 (read/write). + * DCSR0 Direct Memory Access (DMA) Control and Status + * Register channel 0 (read/write). + * DBSA0 Direct Memory Access (DMA) Buffer Start address + * register A channel 0 (read/write). + * DBTA0 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 0 (read/write). + * DBSB0 Direct Memory Access (DMA) Buffer Start address + * register B channel 0 (read/write). + * DBTB0 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 0 (read/write). * - * DDAR1 Direct Memory Access (DMA) Device Address Register - * channel 1 (read/write). - * DCSR1 Direct Memory Access (DMA) Control and Status - * Register channel 1 (read/write). - * DBSA1 Direct Memory Access (DMA) Buffer Start address - * register A channel 1 (read/write). - * DBTA1 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 1 (read/write). - * DBSB1 Direct Memory Access (DMA) Buffer Start address - * register B channel 1 (read/write). - * DBTB1 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 1 (read/write). + * DDAR1 Direct Memory Access (DMA) Device Address Register + * channel 1 (read/write). + * DCSR1 Direct Memory Access (DMA) Control and Status + * Register channel 1 (read/write). + * DBSA1 Direct Memory Access (DMA) Buffer Start address + * register A channel 1 (read/write). + * DBTA1 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 1 (read/write). + * DBSB1 Direct Memory Access (DMA) Buffer Start address + * register B channel 1 (read/write). + * DBTB1 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 1 (read/write). * - * DDAR2 Direct Memory Access (DMA) Device Address Register - * channel 2 (read/write). - * DCSR2 Direct Memory Access (DMA) Control and Status - * Register channel 2 (read/write). - * DBSA2 Direct Memory Access (DMA) Buffer Start address - * register A channel 2 (read/write). - * DBTA2 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 2 (read/write). - * DBSB2 Direct Memory Access (DMA) Buffer Start address - * register B channel 2 (read/write). - * DBTB2 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 2 (read/write). + * DDAR2 Direct Memory Access (DMA) Device Address Register + * channel 2 (read/write). + * DCSR2 Direct Memory Access (DMA) Control and Status + * Register channel 2 (read/write). + * DBSA2 Direct Memory Access (DMA) Buffer Start address + * register A channel 2 (read/write). + * DBTA2 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 2 (read/write). + * DBSB2 Direct Memory Access (DMA) Buffer Start address + * register B channel 2 (read/write). + * DBTB2 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 2 (read/write). * - * DDAR3 Direct Memory Access (DMA) Device Address Register - * channel 3 (read/write). - * DCSR3 Direct Memory Access (DMA) Control and Status - * Register channel 3 (read/write). - * DBSA3 Direct Memory Access (DMA) Buffer Start address - * register A channel 3 (read/write). - * DBTA3 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 3 (read/write). - * DBSB3 Direct Memory Access (DMA) Buffer Start address - * register B channel 3 (read/write). - * DBTB3 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 3 (read/write). + * DDAR3 Direct Memory Access (DMA) Device Address Register + * channel 3 (read/write). + * DCSR3 Direct Memory Access (DMA) Control and Status + * Register channel 3 (read/write). + * DBSA3 Direct Memory Access (DMA) Buffer Start address + * register A channel 3 (read/write). + * DBTA3 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 3 (read/write). + * DBSB3 Direct Memory Access (DMA) Buffer Start address + * register B channel 3 (read/write). + * DBTB3 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 3 (read/write). * - * DDAR4 Direct Memory Access (DMA) Device Address Register - * channel 4 (read/write). - * DCSR4 Direct Memory Access (DMA) Control and Status - * Register channel 4 (read/write). - * DBSA4 Direct Memory Access (DMA) Buffer Start address - * register A channel 4 (read/write). - * DBTA4 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 4 (read/write). - * DBSB4 Direct Memory Access (DMA) Buffer Start address - * register B channel 4 (read/write). - * DBTB4 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 4 (read/write). + * DDAR4 Direct Memory Access (DMA) Device Address Register + * channel 4 (read/write). + * DCSR4 Direct Memory Access (DMA) Control and Status + * Register channel 4 (read/write). + * DBSA4 Direct Memory Access (DMA) Buffer Start address + * register A channel 4 (read/write). + * DBTA4 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 4 (read/write). + * DBSB4 Direct Memory Access (DMA) Buffer Start address + * register B channel 4 (read/write). + * DBTB4 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 4 (read/write). * - * DDAR5 Direct Memory Access (DMA) Device Address Register - * channel 5 (read/write). - * DCSR5 Direct Memory Access (DMA) Control and Status - * Register channel 5 (read/write). - * DBSA5 Direct Memory Access (DMA) Buffer Start address - * register A channel 5 (read/write). - * DBTA5 Direct Memory Access (DMA) Buffer Transfer count - * register A channel 5 (read/write). - * DBSB5 Direct Memory Access (DMA) Buffer Start address - * register B channel 5 (read/write). - * DBTB5 Direct Memory Access (DMA) Buffer Transfer count - * register B channel 5 (read/write). + * DDAR5 Direct Memory Access (DMA) Device Address Register + * channel 5 (read/write). + * DCSR5 Direct Memory Access (DMA) Control and Status + * Register channel 5 (read/write). + * DBSA5 Direct Memory Access (DMA) Buffer Start address + * register A channel 5 (read/write). + * DBTA5 Direct Memory Access (DMA) Buffer Transfer count + * register A channel 5 (read/write). + * DBSB5 Direct Memory Access (DMA) Buffer Start address + * register B channel 5 (read/write). + * DBTB5 Direct Memory Access (DMA) Buffer Transfer count + * register B channel 5 (read/write). */ -#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ +#define DMASp 0x00000020 /* DMA control reg. Space [byte] */ -#define _DDAR(Nb) /* DMA Device Address Reg. */ \ - /* channel [0..5] */ \ +#define _DDAR(Nb) /* DMA Device Address Reg. */ \ + /* channel [0..5] */ \ (0xB0000000 + (Nb)*DMASp) -#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ +#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ (0xB0000004 + (Nb)*DMASp) -#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ - /* channel [0..5] (write) */ \ +#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \ + /* channel [0..5] (write) */ \ (0xB0000008 + (Nb)*DMASp) -#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ - /* channel [0..5] (read) */ \ +#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \ + /* channel [0..5] (read) */ \ (0xB000000C + (Nb)*DMASp) -#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ - /* channel [0..5] */ \ +#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \ + /* channel [0..5] */ \ (0xB0000010 + (Nb)*DMASp) -#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ - /* reg. A channel [0..5] */ \ +#define _DBTA(Nb) /* DMA Buffer Transfer count */ \ + /* reg. A channel [0..5] */ \ (0xB0000014 + (Nb)*DMASp) -#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ - /* channel [0..5] */ \ +#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \ + /* channel [0..5] */ \ (0xB0000018 + (Nb)*DMASp) -#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ - /* reg. B channel [0..5] */ \ +#define _DBTB(Nb) /* DMA Buffer Transfer count */ \ + /* reg. B channel [0..5] */ \ (0xB000001C + (Nb)*DMASp) -#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ - /* channel 0 */ +#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */ + /* channel 0 */ #define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */ - /* channel 0 (write) */ + /* channel 0 (write) */ #define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */ - /* channel 0 (write) */ + /* channel 0 (write) */ #define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */ - /* channel 0 (read) */ -#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ - /* channel 0 */ -#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ - /* reg. A channel 0 */ -#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ - /* channel 0 */ -#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ - /* reg. B channel 0 */ - -#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ - /* channel 1 */ + /* channel 0 (read) */ +#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */ + /* channel 0 */ +#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */ + /* reg. A channel 0 */ +#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */ + /* channel 0 */ +#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */ + /* reg. B channel 0 */ + +#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */ + /* channel 1 */ #define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */ - /* channel 1 (write) */ + /* channel 1 (write) */ #define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */ - /* channel 1 (write) */ + /* channel 1 (write) */ #define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */ - /* channel 1 (read) */ -#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ - /* channel 1 */ -#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ - /* reg. A channel 1 */ -#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ - /* channel 1 */ -#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ - /* reg. B channel 1 */ - -#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ - /* channel 2 */ + /* channel 1 (read) */ +#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */ + /* channel 1 */ +#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */ + /* reg. A channel 1 */ +#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */ + /* channel 1 */ +#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */ + /* reg. B channel 1 */ + +#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */ + /* channel 2 */ #define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */ - /* channel 2 (write) */ + /* channel 2 (write) */ #define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */ - /* channel 2 (write) */ + /* channel 2 (write) */ #define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */ - /* channel 2 (read) */ -#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ - /* channel 2 */ -#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ - /* reg. A channel 2 */ -#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ - /* channel 2 */ -#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ - /* reg. B channel 2 */ - -#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ - /* channel 3 */ + /* channel 2 (read) */ +#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */ + /* channel 2 */ +#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */ + /* reg. A channel 2 */ +#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */ + /* channel 2 */ +#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */ + /* reg. B channel 2 */ + +#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */ + /* channel 3 */ #define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */ - /* channel 3 (write) */ + /* channel 3 (write) */ #define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */ - /* channel 3 (write) */ + /* channel 3 (write) */ #define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */ - /* channel 3 (read) */ -#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ - /* channel 3 */ -#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ - /* reg. A channel 3 */ -#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ - /* channel 3 */ -#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ - /* reg. B channel 3 */ - -#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ - /* channel 4 */ + /* channel 3 (read) */ +#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */ + /* channel 3 */ +#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */ + /* reg. A channel 3 */ +#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */ + /* channel 3 */ +#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */ + /* reg. B channel 3 */ + +#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */ + /* channel 4 */ #define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */ - /* channel 4 (write) */ + /* channel 4 (write) */ #define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */ - /* channel 4 (write) */ + /* channel 4 (write) */ #define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */ - /* channel 4 (read) */ -#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ - /* channel 4 */ -#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ - /* reg. A channel 4 */ -#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ - /* channel 4 */ -#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ - /* reg. B channel 4 */ - -#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ - /* channel 5 */ + /* channel 4 (read) */ +#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */ + /* channel 4 */ +#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */ + /* reg. A channel 4 */ +#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */ + /* channel 4 */ +#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */ + /* reg. B channel 4 */ + +#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */ + /* channel 5 */ #define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */ - /* channel 5 (write) */ + /* channel 5 (write) */ #define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */ - /* channel 5 (write) */ + /* channel 5 (write) */ #define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */ - /* channel 5 (read) */ -#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ - /* channel 5 */ -#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ - /* reg. A channel 5 */ -#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ - /* channel 5 */ -#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ - /* reg. B channel 5 */ + /* channel 5 (read) */ +#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */ + /* channel 5 */ +#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */ + /* reg. A channel 5 */ +#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */ + /* channel 5 */ +#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */ + /* reg. B channel 5 */ #if LANGUAGE == C -#define DDAR0 /* DMA Device Address Reg. */ \ - /* channel 0 */ \ +#define DDAR0 /* DMA Device Address Reg. */ \ + /* channel 0 */ \ (*((volatile Word *) io_p2v (_DDAR0))) -#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ +#define SetDCSR0 /* Set DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR0))) -#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ - /* channel 0 (write) */ \ +#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \ + /* channel 0 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR0))) -#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ - /* channel 0 (read) */ \ +#define RdDCSR0 /* Read DMA Control & Status Reg. */ \ + /* channel 0 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR0))) -#define DBSA0 /* DMA Buffer Start address reg. A */ \ - /* channel 0 */ \ +#define DBSA0 /* DMA Buffer Start address reg. A */ \ + /* channel 0 */ \ (*((volatile Address *) io_p2v (_DBSA0))) -#define DBTA0 /* DMA Buffer Transfer count */ \ - /* reg. A channel 0 */ \ +#define DBTA0 /* DMA Buffer Transfer count */ \ + /* reg. A channel 0 */ \ (*((volatile Word *) io_p2v (_DBTA0))) -#define DBSB0 /* DMA Buffer Start address reg. B */ \ - /* channel 0 */ \ +#define DBSB0 /* DMA Buffer Start address reg. B */ \ + /* channel 0 */ \ (*((volatile Address *) io_p2v (_DBSB0))) -#define DBTB0 /* DMA Buffer Transfer count */ \ - /* reg. B channel 0 */ \ +#define DBTB0 /* DMA Buffer Transfer count */ \ + /* reg. B channel 0 */ \ (*((volatile Word *) io_p2v (_DBTB0))) -#define DDAR1 /* DMA Device Address Reg. */ \ - /* channel 1 */ \ +#define DDAR1 /* DMA Device Address Reg. */ \ + /* channel 1 */ \ (*((volatile Word *) io_p2v (_DDAR1))) -#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ +#define SetDCSR1 /* Set DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR1))) -#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ - /* channel 1 (write) */ \ +#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \ + /* channel 1 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR1))) -#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ - /* channel 1 (read) */ \ +#define RdDCSR1 /* Read DMA Control & Status Reg. */ \ + /* channel 1 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR1))) -#define DBSA1 /* DMA Buffer Start address reg. A */ \ - /* channel 1 */ \ +#define DBSA1 /* DMA Buffer Start address reg. A */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DBSA1))) -#define DBTA1 /* DMA Buffer Transfer count */ \ - /* reg. A channel 1 */ \ +#define DBTA1 /* DMA Buffer Transfer count */ \ + /* reg. A channel 1 */ \ (*((volatile Word *) io_p2v (_DBTA1))) -#define DBSB1 /* DMA Buffer Start address reg. B */ \ - /* channel 1 */ \ +#define DBSB1 /* DMA Buffer Start address reg. B */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DBSB1))) -#define DBTB1 /* DMA Buffer Transfer count */ \ - /* reg. B channel 1 */ \ +#define DBTB1 /* DMA Buffer Transfer count */ \ + /* reg. B channel 1 */ \ (*((volatile Word *) io_p2v (_DBTB1))) -#define DDAR2 /* DMA Device Address Reg. */ \ - /* channel 2 */ \ +#define DDAR2 /* DMA Device Address Reg. */ \ + /* channel 2 */ \ (*((volatile Word *) io_p2v (_DDAR2))) -#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ +#define SetDCSR2 /* Set DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR2))) -#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ - /* channel 2 (write) */ \ +#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \ + /* channel 2 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR2))) -#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ - /* channel 2 (read) */ \ +#define RdDCSR2 /* Read DMA Control & Status Reg. */ \ + /* channel 2 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR2))) -#define DBSA2 /* DMA Buffer Start address reg. A */ \ - /* channel 2 */ \ +#define DBSA2 /* DMA Buffer Start address reg. A */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DBSA2))) -#define DBTA2 /* DMA Buffer Transfer count */ \ - /* reg. A channel 2 */ \ +#define DBTA2 /* DMA Buffer Transfer count */ \ + /* reg. A channel 2 */ \ (*((volatile Word *) io_p2v (_DBTA2))) -#define DBSB2 /* DMA Buffer Start address reg. B */ \ - /* channel 2 */ \ +#define DBSB2 /* DMA Buffer Start address reg. B */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DBSB2))) -#define DBTB2 /* DMA Buffer Transfer count */ \ - /* reg. B channel 2 */ \ +#define DBTB2 /* DMA Buffer Transfer count */ \ + /* reg. B channel 2 */ \ (*((volatile Word *) io_p2v (_DBTB2))) -#define DDAR3 /* DMA Device Address Reg. */ \ - /* channel 3 */ \ +#define DDAR3 /* DMA Device Address Reg. */ \ + /* channel 3 */ \ (*((volatile Word *) io_p2v (_DDAR3))) -#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ +#define SetDCSR3 /* Set DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR3))) -#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ - /* channel 3 (write) */ \ +#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \ + /* channel 3 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR3))) -#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ - /* channel 3 (read) */ \ +#define RdDCSR3 /* Read DMA Control & Status Reg. */ \ + /* channel 3 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR3))) -#define DBSA3 /* DMA Buffer Start address reg. A */ \ - /* channel 3 */ \ +#define DBSA3 /* DMA Buffer Start address reg. A */ \ + /* channel 3 */ \ (*((volatile Address *) io_p2v (_DBSA3))) -#define DBTA3 /* DMA Buffer Transfer count */ \ - /* reg. A channel 3 */ \ +#define DBTA3 /* DMA Buffer Transfer count */ \ + /* reg. A channel 3 */ \ (*((volatile Word *) io_p2v (_DBTA3))) -#define DBSB3 /* DMA Buffer Start address reg. B */ \ - /* channel 3 */ \ +#define DBSB3 /* DMA Buffer Start address reg. B */ \ + /* channel 3 */ \ (*((volatile Address *) io_p2v (_DBSB3))) -#define DBTB3 /* DMA Buffer Transfer count */ \ - /* reg. B channel 3 */ \ +#define DBTB3 /* DMA Buffer Transfer count */ \ + /* reg. B channel 3 */ \ (*((volatile Word *) io_p2v (_DBTB3))) -#define DDAR4 /* DMA Device Address Reg. */ \ - /* channel 4 */ \ +#define DDAR4 /* DMA Device Address Reg. */ \ + /* channel 4 */ \ (*((volatile Word *) io_p2v (_DDAR4))) -#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ +#define SetDCSR4 /* Set DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR4))) -#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ - /* channel 4 (write) */ \ +#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \ + /* channel 4 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR4))) -#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ - /* channel 4 (read) */ \ +#define RdDCSR4 /* Read DMA Control & Status Reg. */ \ + /* channel 4 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR4))) -#define DBSA4 /* DMA Buffer Start address reg. A */ \ - /* channel 4 */ \ +#define DBSA4 /* DMA Buffer Start address reg. A */ \ + /* channel 4 */ \ (*((volatile Address *) io_p2v (_DBSA4))) -#define DBTA4 /* DMA Buffer Transfer count */ \ - /* reg. A channel 4 */ \ +#define DBTA4 /* DMA Buffer Transfer count */ \ + /* reg. A channel 4 */ \ (*((volatile Word *) io_p2v (_DBTA4))) -#define DBSB4 /* DMA Buffer Start address reg. B */ \ - /* channel 4 */ \ +#define DBSB4 /* DMA Buffer Start address reg. B */ \ + /* channel 4 */ \ (*((volatile Address *) io_p2v (_DBSB4))) -#define DBTB4 /* DMA Buffer Transfer count */ \ - /* reg. B channel 4 */ \ +#define DBTB4 /* DMA Buffer Transfer count */ \ + /* reg. B channel 4 */ \ (*((volatile Word *) io_p2v (_DBTB4))) -#define DDAR5 /* DMA Device Address Reg. */ \ - /* channel 5 */ \ +#define DDAR5 /* DMA Device Address Reg. */ \ + /* channel 5 */ \ (*((volatile Word *) io_p2v (_DDAR5))) -#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ +#define SetDCSR5 /* Set DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ (*((volatile Word *) io_p2v (_SetDCSR5))) -#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ - /* channel 5 (write) */ \ +#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \ + /* channel 5 (write) */ \ (*((volatile Word *) io_p2v (_ClrDCSR5))) -#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ - /* channel 5 (read) */ \ +#define RdDCSR5 /* Read DMA Control & Status Reg. */ \ + /* channel 5 (read) */ \ (*((volatile Word *) io_p2v (_RdDCSR5))) -#define DBSA5 /* DMA Buffer Start address reg. A */ \ - /* channel 5 */ \ +#define DBSA5 /* DMA Buffer Start address reg. A */ \ + /* channel 5 */ \ (*((volatile Address *) io_p2v (_DBSA5))) -#define DBTA5 /* DMA Buffer Transfer count */ \ - /* reg. A channel 5 */ \ +#define DBTA5 /* DMA Buffer Transfer count */ \ + /* reg. A channel 5 */ \ (*((volatile Word *) io_p2v (_DBTA5))) -#define DBSB5 /* DMA Buffer Start address reg. B */ \ - /* channel 5 */ \ +#define DBSB5 /* DMA Buffer Start address reg. B */ \ + /* channel 5 */ \ (*((volatile Address *) io_p2v (_DBSB5))) -#define DBTB5 /* DMA Buffer Transfer count */ \ - /* reg. B channel 5 */ \ +#define DBTB5 /* DMA Buffer Transfer count */ \ + /* reg. B channel 5 */ \ (*((volatile Word *) io_p2v (_DBTB5))) #endif /* LANGUAGE == C */ -#define DDAR_RW 0x00000001 /* device data Read/Write */ -#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ - /* (memory -> device) */ -#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ - /* (device -> memory) */ -#define DDAR_E 0x00000002 /* big/little Endian device */ -#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ -#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ -#define DDAR_BS 0x00000004 /* device Burst Size */ -#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ -#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ -#define DDAR_DW 0x00000008 /* device Data Width */ -#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ -#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ -#define DDAR_DS Fld (4, 4) /* Device Select */ -#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ +#define DDAR_RW 0x00000001 /* device data Read/Write */ +#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */ + /* (memory -> device) */ +#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */ + /* (device -> memory) */ +#define DDAR_E 0x00000002 /* big/little Endian device */ +#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */ +#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */ +#define DDAR_BS 0x00000004 /* device Burst Size */ +#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */ +#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */ +#define DDAR_DW 0x00000008 /* device Data Width */ +#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */ +#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */ +#define DDAR_DS Fld (4, 4) /* Device Select */ +#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \ (0x0 << FShft (DDAR_DS)) -#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ +#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \ (0x1 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ +#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \ (0x2 << FShft (DDAR_DS)) -#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ +#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \ (0x3 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ +#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \ (0x4 << FShft (DDAR_DS)) -#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ +#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \ (0x5 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ +#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \ (0x6 << FShft (DDAR_DS)) -#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ +#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \ (0x7 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ +#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \ (0x8 << FShft (DDAR_DS)) -#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ +#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \ (0x9 << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ - /* (audio) */ \ +#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \ + /* (audio) */ \ (0xA << FShft (DDAR_DS)) -#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ - /* (audio) */ \ +#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \ + /* (audio) */ \ (0xB << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \ + /* (telecom) */ \ (0xC << FShft (DDAR_DS)) -#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \ + /* (telecom) */ \ (0xD << FShft (DDAR_DS)) -#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ +#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \ (0xE << FShft (DDAR_DS)) -#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ +#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \ (0xF << FShft (DDAR_DS)) -#define DDAR_DA Fld (24, 8) /* Device Address */ -#define DDAR_DevAdd(Add) /* Device Address */ \ +#define DDAR_DA Fld (24, 8) /* Device Address */ +#define DDAR_DevAdd(Add) /* Device Address */ \ (((Add) & 0xF0000000) | \ (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2))) -#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ +#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \ (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ +#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \ (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR)) -#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ +#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ +#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR)) -#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ +#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ +#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR)) -#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ +#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ +#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR)) -#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ +#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \ (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ +#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \ (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \ DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR)) -#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ +#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ +#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \ DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR)) -#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ +#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ +#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0)) -#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \ + /* (telecom) */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ - /* (telecom) */ \ +#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \ + /* (telecom) */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1)) -#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ +#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \ (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR)) -#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ +#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \ (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \ DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR)) -#define DCSR_RUN 0x00000001 /* DMA RUNing */ -#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ -#define DCSR_ERROR 0x00000004 /* DMA ERROR */ -#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ +#define DCSR_RUN 0x00000001 /* DMA RUNing */ +#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */ +#define DCSR_ERROR 0x00000004 /* DMA ERROR */ +#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */ #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */ -#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ +#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */ #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */ -#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ -#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ -#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ +#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */ +#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */ +#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */ -#define DBT_TC Fld (13, 0) /* Transfer Count */ -#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ -#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ +#define DBT_TC Fld (13, 0) /* Transfer Count */ +#define DBTA_TCA DBT_TC /* Transfer Count buffer A */ +#define DBTB_TCB DBT_TC /* Transfer Count buffer B */ /* * Liquid Crystal Display (LCD) control registers * * Registers - * LCCR0 Liquid Crystal Display (LCD) Control Register 0 - * (read/write). - * [Bits LDM, BAM, and ERM are only implemented in - * versions 2.0 (rev. = 8) and higher of the StrongARM - * SA-1100.] - * LCSR Liquid Crystal Display (LCD) Status Register - * (read/write). - * [Bit LDD can be only read in versions 1.0 (rev. = 1) - * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be - * read and written (cleared) in versions 2.0 (rev. = 8) - * and higher.] - * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 1 (read/write). - * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 1 (read). - * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Base Address Register channel 2 (read/write). - * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access - * (DMA) Current Address Register channel 2 (read). - * LCCR1 Liquid Crystal Display (LCD) Control Register 1 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR2 Liquid Crystal Display (LCD) Control Register 2 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher.] - * LCCR3 Liquid Crystal Display (LCD) Control Register 3 - * (read/write). - * [The LCCR1 register can be only written in - * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the - * StrongARM SA-1100, it can be written and read in - * versions 2.0 (rev. = 8) and higher. Bit PCP is only - * implemented in versions 2.0 (rev. = 8) and higher of - * the StrongARM SA-1100.] + * LCCR0 Liquid Crystal Display (LCD) Control Register 0 + * (read/write). + * [Bits LDM, BAM, and ERM are only implemented in + * versions 2.0 (rev. = 8) and higher of the StrongARM + * SA-1100.] + * LCSR Liquid Crystal Display (LCD) Status Register + * (read/write). + * [Bit LDD can be only read in versions 1.0 (rev. = 1) + * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be + * read and written (cleared) in versions 2.0 (rev. = 8) + * and higher.] + * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 1 (read/write). + * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 1 (read). + * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Base Address Register channel 2 (read/write). + * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access + * (DMA) Current Address Register channel 2 (read). + * LCCR1 Liquid Crystal Display (LCD) Control Register 1 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR2 Liquid Crystal Display (LCD) Control Register 2 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher.] + * LCCR3 Liquid Crystal Display (LCD) Control Register 3 + * (read/write). + * [The LCCR1 register can be only written in + * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the + * StrongARM SA-1100, it can be written and read in + * versions 2.0 (rev. = 8) and higher. Bit PCP is only + * implemented in versions 2.0 (rev. = 8) and higher of + * the StrongARM SA-1100.] * * Clocks * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK). * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2). * fpix, Tpix Frequency, period of the pixel clock. - * fln, Tln Frequency, period of the line clock. - * fac, Tac Frequency, period of the AC bias clock. + * fln, Tln Frequency, period of the line clock. + * fac, Tac Frequency, period of the AC bias clock. */ -#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ -#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ - /* [byte] */ \ +#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */ +#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \ + /* [byte] */ \ (16*LCD_PEntrySp) -#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ - /* [byte] */ \ +#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \ + /* [byte] */ \ (256*LCD_PEntrySp) -#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ - /* dummy-Palette Space [byte] */ \ +#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \ + /* dummy-Palette Space [byte] */ \ (16*LCD_PEntrySp) #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */ #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */ #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */ -#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ -#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ -#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ +#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */ +#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */ +#define LCD_4Bit /* LCD 4-Bit pixel mode */ \ (0 << FShft (LCD_PBS)) -#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ +#define LCD_8Bit /* LCD 8-Bit pixel mode */ \ (1 << FShft (LCD_PBS)) -#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ +#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \ (2 << FShft (LCD_PBS)) -#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ -#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ -#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ -#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ -#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ -#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ -#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ -#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ -#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ -#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ -#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ -#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ -#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ -#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ -#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ -#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ - /* (Alternative) */ - -#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ -#define _LCSR 0xB0100004 /* LCD Status Reg. */ -#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ - /* channel 1 */ -#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ - /* channel 1 */ -#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ - /* channel 2 */ -#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ - /* channel 2 */ -#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ -#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ -#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ +#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */ +#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */ +#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */ +#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */ +#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */ +#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */ +#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */ +#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */ +#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */ +#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */ +#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */ +#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */ +#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */ +#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */ +#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */ +#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ + /* (Alternative) */ + +#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */ +#define _LCSR 0xB0100004 /* LCD Status Reg. */ +#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */ + /* channel 1 */ +#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */ + /* channel 1 */ +#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */ + /* channel 2 */ +#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */ + /* channel 2 */ +#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */ +#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */ +#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */ #if LANGUAGE == C -#define LCCR0 /* LCD Control Reg. 0 */ \ +#define LCCR0 /* LCD Control Reg. 0 */ \ (*((volatile Word *) io_p2v (_LCCR0))) -#define LCSR /* LCD Status Reg. */ \ +#define LCSR /* LCD Status Reg. */ \ (*((volatile Word *) io_p2v (_LCSR))) -#define DBAR1 /* LCD DMA Base Address Reg. */ \ - /* channel 1 */ \ +#define DBAR1 /* LCD DMA Base Address Reg. */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DBAR1))) -#define DCAR1 /* LCD DMA Current Address Reg. */ \ - /* channel 1 */ \ +#define DCAR1 /* LCD DMA Current Address Reg. */ \ + /* channel 1 */ \ (*((volatile Address *) io_p2v (_DCAR1))) -#define DBAR2 /* LCD DMA Base Address Reg. */ \ - /* channel 2 */ \ +#define DBAR2 /* LCD DMA Base Address Reg. */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DBAR2))) -#define DCAR2 /* LCD DMA Current Address Reg. */ \ - /* channel 2 */ \ +#define DCAR2 /* LCD DMA Current Address Reg. */ \ + /* channel 2 */ \ (*((volatile Address *) io_p2v (_DCAR2))) -#define LCCR1 /* LCD Control Reg. 1 */ \ +#define LCCR1 /* LCD Control Reg. 1 */ \ (*((volatile Word *) io_p2v (_LCCR1))) -#define LCCR2 /* LCD Control Reg. 2 */ \ +#define LCCR2 /* LCD Control Reg. 2 */ \ (*((volatile Word *) io_p2v (_LCCR2))) -#define LCCR3 /* LCD Control Reg. 3 */ \ +#define LCCR3 /* LCD Control Reg. 3 */ \ (*((volatile Word *) io_p2v (_LCCR3))) #endif /* LANGUAGE == C */ -#define LCCR0_LEN 0x00000001 /* LCD ENable */ +#define LCCR0_LEN 0x00000001 /* LCD ENable */ #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ -#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ -#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ -#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ - /* Select */ -#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ -#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ -#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ - /* interrupt Mask (disable) */ -#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ - /* interrupt Mask (disable) */ +#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ +#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */ +#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */ + /* Select */ +#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */ +#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */ +#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */ + /* interrupt Mask (disable) */ +#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */ + /* interrupt Mask (disable) */ #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */ /* IUU, OOL, OUL, OOU, and OUU) */ - /* interrupt Mask (disable) */ + /* interrupt Mask (disable) */ #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */ -#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ -#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ -#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ -#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ -#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ +#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */ +#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */ +#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */ +#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */ +#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */ #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */ - /* display mode) */ -#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ - /* display */ -#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ - /* [Tmem] */ -#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ - /* [0..510 Tcpu] */ \ + /* display mode) */ +#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */ + /* display */ +#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */ + /* [Tmem] */ +#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \ + /* [0..510 Tcpu] */ \ ((Tcpu)/2 << FShft (LCCR0_PDD)) -#define LCSR_LDD 0x00000001 /* LCD Disable Done */ -#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ -#define LCSR_BER 0x00000004 /* Bus ERror */ -#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ -#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ - /* panel */ -#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ - /* panel */ -#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ - /* panel */ -#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ - /* panel */ -#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ - /* panel */ -#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ - /* panel */ -#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ - /* panel */ -#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ - /* panel */ - -#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ -#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ +#define LCSR_LDD 0x00000001 /* LCD Disable Done */ +#define LCSR_BAU 0x00000002 /* Base Address Update (read) */ +#define LCSR_BER 0x00000004 /* Bus ERror */ +#define LCSR_ABC 0x00000008 /* AC Bias clock Count */ +#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */ + /* panel */ +#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */ + /* panel */ +#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */ + /* panel */ +#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */ + /* panel */ +#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */ + /* panel */ +#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */ + /* panel */ +#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */ + /* panel */ +#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */ + /* panel */ + +#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */ +#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \ (((Pixel) - 16)/16 << FShft (LCCR1_PPL)) -#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ /* pulse Width - 2 [Tpix] (L_LCLK) */ -#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ - /* pulse Width [2..65 Tpix] */ \ +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ + /* pulse Width [2..65 Tpix] */ \ (((Tpix) - 2) << FShft (LCCR1_HSW)) #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ - /* count - 1 [Tpix] */ -#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ - /* [1..256 Tpix] */ \ + /* count - 1 [Tpix] */ +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ + /* [1..256 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_ELW)) #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ - /* Wait count - 1 [Tpix] */ -#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ - /* [1..256 Tpix] */ \ + /* Wait count - 1 [Tpix] */ +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ + /* [1..256 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_BLW)) -#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ -#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ (((Line) - 1) << FShft (LCCR2_LPP)) #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ - /* Width - 1 [Tln] (L_FCLK) */ -#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ - /* Width [1..64 Tln] */ \ + /* Width - 1 [Tln] (L_FCLK) */ +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ + /* Width [1..64 Tln] */ \ (((Tln) - 1) << FShft (LCCR2_VSW)) #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ - /* count [Tln] */ -#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ - /* [0..255 Tln] */ \ + /* count [Tln] */ +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ + /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_EFW)) #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ - /* Wait count [Tln] */ -#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ - /* [0..255 Tln] */ \ + /* Wait count [Tln] */ +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ + /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_BFW)) -#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ - /* [1..255] (L_PCLK) */ - /* fpix = fcpu/(2*(PCD + 2)) */ - /* Tpix = 2*(PCD + 2)*Tcpu */ -#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */ + /* [1..255] (L_PCLK) */ + /* fpix = fcpu/(2*(PCD + 2)) */ + /* Tpix = 2*(PCD + 2)*Tcpu */ +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \ (((Div) - 4)/2 << FShft (LCCR3_PCD)) /* fpix = fcpu/(2*Floor (Div/2)) */ /* Tpix = 2*Floor (Div/2)*Tcpu */ #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \ (((Div) - 3)/2 << FShft (LCCR3_PCD)) /* fpix = fcpu/(2*Ceil (Div/2)) */ - /* Tpix = 2*Ceil (Div/2)*Tcpu */ + /* Tpix = 2*Ceil (Div/2)*Tcpu */ #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */ - /* [Tln] (L_BIAS) */ -#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ + /* [Tln] (L_BIAS) */ +#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \ (((Div) - 2)/2 << FShft (LCCR3_ACB)) /* fac = fln/(2*Floor (Div/2)) */ - /* Tac = 2*Floor (Div/2)*Tln */ -#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ + /* Tac = 2*Floor (Div/2)*Tln */ +#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \ (((Div) - 1)/2 << FShft (LCCR3_ACB)) - /* fac = fln/(2*Ceil (Div/2)) */ - /* Tac = 2*Ceil (Div/2)*Tln */ -#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ - /* Interrupt */ -#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ - /* Off */ \ + /* fac = fln/(2*Ceil (Div/2)) */ + /* Tac = 2*Ceil (Div/2)*Tln */ +#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */ + /* Interrupt */ +#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \ + /* Off */ \ (0 << FShft (LCCR3_API)) -#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ - /* [1..15] */ \ +#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \ + /* [1..15] */ \ ((Trans) << FShft (LCCR3_API)) #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */ - /* Polarity (L_FCLK) */ + /* Polarity (L_FCLK) */ #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ - /* active High */ + /* active High */ #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ - /* active Low */ -#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ - /* pulse Polarity (L_LCLK) */ -#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ - /* pulse active High */ -#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ - /* pulse active Low */ + /* active Low */ +#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */ + /* pulse Polarity (L_LCLK) */ +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ + /* pulse active High */ +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ + /* pulse active Low */ #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */ -#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ -#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ +#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */ +#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */ #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */ - /* active display mode) */ -#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ -#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ + /* active display mode) */ +#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ +#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ #undef C diff --git a/include/ahci.h b/include/ahci.h index 80701e298c..b363ee1969 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -91,12 +91,12 @@ #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ -#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ +#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \ | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR -#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ - | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ - | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ +#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \ + | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \ + | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \ | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \ | PORT_IRQ_D2H_REG_FIS @@ -172,7 +172,7 @@ struct ahci_ioports { }; struct ahci_probe_ent { - pci_dev_t dev; + pci_dev_t dev; struct ahci_ioports port[AHCI_MAX_PORTS]; u32 n_ports; u32 hard_port_no; diff --git a/include/armcoremodule.h b/include/armcoremodule.h index 7dac6f8c9e..f1ded85fcf 100644 --- a/include/armcoremodule.h +++ b/include/armcoremodule.h @@ -28,20 +28,20 @@ #ifndef __ARMCOREMODULE_H #define __ARMCOREMODULE_H -#define CM_BASE 0x10000000 +#define CM_BASE 0x10000000 /* CM registers common to all CMs */ /* Note that observed values after reboot into the ARM Boot Monitor have been used as defaults, rather than the POR values */ -#define OS_CTRL 0x0000000C +#define OS_CTRL 0x0000000C #define CMMASK_REMAP 0x00000005 /* set remap & led */ #define CMMASK_RESET 0x00000008 -#define OS_LOCK 0x00000014 -#define CMVAL_LOCK1 0x0000A000 /* locking value */ +#define OS_LOCK 0x00000014 +#define CMVAL_LOCK1 0x0000A000 /* locking value */ #define CMVAL_LOCK2 0x0000005F /* locking value */ #define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */ #define OS_SDRAM 0x00000020 -#define OS_INIT 0x00000024 +#define OS_INIT 0x00000024 #define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ #define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ #define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */ diff --git a/include/asm-arm/arch-arm720t/netarm_mem_module.h b/include/asm-arm/arch-arm720t/netarm_mem_module.h index f0529fd09b..c650c3b004 100644 --- a/include/asm-arm/arch-arm720t/netarm_mem_module.h +++ b/include/asm-arm/arch-arm720t/netarm_mem_module.h @@ -170,15 +170,15 @@ /* Option B Registers (0xFFC0_00x8) */ #define NETARM_MEM_OPTB_SYNC_1_STAGE (0x00000001) #define NETARM_MEM_OPTB_SYNC_2_STAGE (0x00000002) -#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) -#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) -#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) - -#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) -#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) -#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) -#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) +#define NETARM_MEM_OPTB_BCYC_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_BCYC_PLUS4 (0x00000004) +#define NETARM_MEM_OPTB_BCYC_PLUS8 (0x00000008) +#define NETARM_MEM_OPTB_BCYC_PLUS12 (0x0000000C) + +#define NETARM_MEM_OPTB_WAIT_PLUS0 (0x00000000) +#define NETARM_MEM_OPTB_WAIT_PLUS16 (0x00000010) +#define NETARM_MEM_OPTB_WAIT_PLUS32 (0x00000020) +#define NETARM_MEM_OPTB_WAIT_PLUS48 (0x00000030) #endif #endif diff --git a/include/asm-arm/arch-arm720t/netarm_ser_module.h b/include/asm-arm/arch-arm720t/netarm_ser_module.h index fceabd173e..6fbae11c8d 100644 --- a/include/asm-arm/arch-arm720t/netarm_ser_module.h +++ b/include/asm-arm/arch-arm720t/netarm_ser_module.h @@ -284,21 +284,21 @@ typedef struct { /* from section 7.5.4 of HW Ref Guide */ /* #ifdef CONFIG_NETARM_PLL_BYPASS */ -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_EXT_5 | \ - ( ( ( ( NETARM_XTAL_FREQ / \ - ( x * 10 ) ) - 1 ) / 16 ) & \ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_EXT_5 | \ + ( ( ( ( NETARM_XTAL_FREQ / \ + ( x * 10 ) ) - 1 ) / 16 ) & \ NETARM_SER_BR_MASK ) ) /* #else -#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ - NETARM_SER_BR_RX_CLK_INT | \ - NETARM_SER_BR_TX_CLK_INT | \ - NETARM_SER_BR_CLK_SYSTEM | \ - ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ - ( x * 2 ) ) - 1 ) / 16 ) & \ +#define NETARM_SER_BR_X16(x) ( NETARM_SER_BR_EN | \ + NETARM_SER_BR_RX_CLK_INT | \ + NETARM_SER_BR_TX_CLK_INT | \ + NETARM_SER_BR_CLK_SYSTEM | \ + ( ( ( ( NETARM_PLLED_SYSCLK_FREQ / \ + ( x * 2 ) ) - 1 ) / 16 ) & \ NETARM_SER_BR_MASK ) ) #endif */ @@ -313,13 +313,13 @@ typedef struct { /* #ifdef CONFIG_NETARM_PLL_BYPASS */ #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ + ( x * 5 * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) /* #else #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ + ( x * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #endif */ @@ -327,11 +327,11 @@ typedef struct { #if 0 #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) / \ - ( x * 5 * 512 ) ) - 1 ) & \ + ( x * 5 * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #define NETARM_SER_RXGAP(x) ( NETARM_SER_RX_GAP_TIMER_EN | \ ( ( ( ( 10 * NETARM_XTAL_FREQ ) / \ - ( x * 512 ) ) - 1 ) & \ + ( x * 512 ) ) - 1 ) & \ NETARM_SER_RX_GAP_MASK ) ) #endif diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-arm720t/s3c4510b.h index 73a3b6d856..6b8c8edd7a 100644 --- a/include/asm-arm/arch-arm720t/s3c4510b.h +++ b/include/asm-arm/arch-arm720t/s3c4510b.h @@ -35,7 +35,7 @@ /* Special Register Start Address After System Reset */ #define REG_BASE (0x03ff0000) -#define SPSTR (REG_BASE) +#define SPSTR (REG_BASE) /* *********************** */ /* System Manager Register */ @@ -100,7 +100,7 @@ #define REG_I2C_CON (REG_BASE+0xf000) #define REG_I2C_BUF (REG_BASE+0xf004) #define REG_I2C_PS (REG_BASE+0xf008) -#define REG_I2C_COUNT (REG_BASE+0xf00c) +#define REG_I2C_COUNT (REG_BASE+0xf00c) /********************/ /* GDMA 0 */ @@ -149,7 +149,7 @@ /********************/ /* Timer Register */ /********************/ -#define REG_TMOD (REG_BASE+0x6000) +#define REG_TMOD (REG_BASE+0x6000) #define REG_TDATA0 (REG_BASE+0x6004) #define REG_TDATA1 (REG_BASE+0x6008) #define REG_TCNT0 (REG_BASE+0x600c) @@ -159,8 +159,8 @@ /* I/O Port Interface */ /**********************/ #define REG_IOPMODE (REG_BASE+0x5000) -#define REG_IOPCON (REG_BASE+0x5004) -#define REG_IOPDATA (REG_BASE+0x5008) +#define REG_IOPCON (REG_BASE+0x5004) +#define REG_IOPDATA (REG_BASE+0x5008) /*********************************/ /* Interrupt Controller Register */ diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 0e01005a91..2f7f71036b 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -32,17 +32,17 @@ typedef volatile unsigned int AT91_REG; /* Hardware register definition */ /*****************************************************************************/ typedef struct _AT91S_TC { - AT91_REG TC_CCR; /* Channel Control Register */ - AT91_REG TC_CMR; /* Channel Mode Register */ - AT91_REG Reserved0[2]; /* */ - AT91_REG TC_CV; /* Counter Value */ - AT91_REG TC_RA; /* Register A */ - AT91_REG TC_RB; /* Register B */ - AT91_REG TC_RC; /* Register C */ - AT91_REG TC_SR; /* Status Register */ - AT91_REG TC_IER; /* Interrupt Enable Register */ - AT91_REG TC_IDR; /* Interrupt Disable Register */ - AT91_REG TC_IMR; /* Interrupt Mask Register */ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register */ + AT91_REG Reserved0[2]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ } AT91S_TC, *AT91PS_TC; #define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ @@ -65,33 +65,33 @@ typedef struct _AT91S_TC /*****************************************************************************/ typedef struct _AT91S_USART { - AT91_REG US_CR; /* Control Register */ - AT91_REG US_MR; /* Mode Register */ - AT91_REG US_IER; /* Interrupt Enable Register */ - AT91_REG US_IDR; /* Interrupt Disable Register */ - AT91_REG US_IMR; /* Interrupt Mask Register */ - AT91_REG US_CSR; /* Channel Status Register */ - AT91_REG US_RHR; /* Receiver Holding Register */ - AT91_REG US_THR; /* Transmitter Holding Register */ - AT91_REG US_BRGR; /* Baud Rate Generator Register */ - AT91_REG US_RTOR; /* Receiver Time-out Register */ - AT91_REG US_TTGR; /* Transmitter Time-guard Register */ - AT91_REG Reserved0[5]; /* */ - AT91_REG US_FIDI; /* FI_DI_Ratio Register */ - AT91_REG US_NER; /* Nb Errors Register */ - AT91_REG US_XXR; /* XON_XOFF Register */ - AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[5]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG US_XXR; /* XON_XOFF Register */ + AT91_REG US_IF; /* IRDA_FILTER Register */ AT91_REG Reserved1[44]; /* */ - AT91_REG US_RPR; /* Receive Pointer Register */ - AT91_REG US_RCR; /* Receive Counter Register */ - AT91_REG US_TPR; /* Transmit Pointer Register */ - AT91_REG US_TCR; /* Transmit Counter Register */ - AT91_REG US_RNPR; /* Receive Next Pointer Register */ - AT91_REG US_RNCR; /* Receive Next Counter Register */ - AT91_REG US_TNPR; /* Transmit Next Pointer Register */ - AT91_REG US_TNCR; /* Transmit Next Counter Register */ - AT91_REG US_PTCR; /* PDC Transfer Control Register */ - AT91_REG US_PTSR; /* PDC Transfer Status Register */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ } AT91S_USART, *AT91PS_USART; /*****************************************************************************/ @@ -99,10 +99,10 @@ typedef struct _AT91S_USART /*****************************************************************************/ typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; /* Main Oscillator Register */ - AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ - AT91_REG CKGR_PLLAR; /* PLL A Register */ - AT91_REG CKGR_PLLBR; /* PLL B Register */ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG CKGR_PLLAR; /* PLL A Register */ + AT91_REG CKGR_PLLBR; /* PLL B Register */ } AT91S_CKGR, *AT91PS_CKGR; /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ @@ -146,41 +146,41 @@ typedef struct _AT91S_CKGR /*****************************************************************************/ typedef struct _AT91S_PIO { - AT91_REG PIO_PER; /* PIO Enable Register */ - AT91_REG PIO_PDR; /* PIO Disable Register */ - AT91_REG PIO_PSR; /* PIO Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PIO_OER; /* Output Enable Register */ - AT91_REG PIO_ODR; /* Output Disable Registerr */ - AT91_REG PIO_OSR; /* Output Status Register */ - AT91_REG Reserved1[1]; /* */ - AT91_REG PIO_IFER; /* Input Filter Enable Register */ - AT91_REG PIO_IFDR; /* Input Filter Disable Register */ - AT91_REG PIO_IFSR; /* Input Filter Status Register */ - AT91_REG Reserved2[1]; /* */ - AT91_REG PIO_SODR; /* Set Output Data Register */ - AT91_REG PIO_CODR; /* Clear Output Data Register */ - AT91_REG PIO_ODSR; /* Output Data Status Register */ - AT91_REG PIO_PDSR; /* Pin Data Status Register */ - AT91_REG PIO_IER; /* Interrupt Enable Register */ - AT91_REG PIO_IDR; /* Interrupt Disable Register */ - AT91_REG PIO_IMR; /* Interrupt Mask Register */ - AT91_REG PIO_ISR; /* Interrupt Status Register */ - AT91_REG PIO_MDER; /* Multi-driver Enable Register */ - AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ - AT91_REG PIO_MDSR; /* Multi-driver Status Register */ - AT91_REG Reserved3[1]; /* */ - AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ - AT91_REG PIO_PPUER; /* Pull-up Enable Register */ - AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ - AT91_REG Reserved4[1]; /* */ - AT91_REG PIO_ASR; /* Select A Register */ - AT91_REG PIO_BSR; /* Select B Register */ - AT91_REG PIO_ABSR; /* AB Select Status Register */ - AT91_REG Reserved5[9]; /* */ - AT91_REG PIO_OWER; /* Output Write Enable Register */ - AT91_REG PIO_OWDR; /* Output Write Disable Register */ - AT91_REG PIO_OWSR; /* Output Write Status Register */ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[1]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[1]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[1]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved4[1]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[9]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ } AT91S_PIO, *AT91PS_PIO; @@ -189,30 +189,30 @@ typedef struct _AT91S_PIO /*****************************************************************************/ typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; /* Control Register */ - AT91_REG DBGU_MR; /* Mode Register */ - AT91_REG DBGU_IER; /* Interrupt Enable Register */ - AT91_REG DBGU_IDR; /* Interrupt Disable Register */ - AT91_REG DBGU_IMR; /* Interrupt Mask Register */ - AT91_REG DBGU_CSR; /* Channel Status Register */ - AT91_REG DBGU_RHR; /* Receiver Holding Register */ - AT91_REG DBGU_THR; /* Transmitter Holding Register */ - AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ - AT91_REG Reserved0[7]; /* */ - AT91_REG DBGU_C1R; /* Chip ID1 Register */ - AT91_REG DBGU_C2R; /* Chip ID2 Register */ - AT91_REG DBGU_FNTR; /* Force NTRST Register */ - AT91_REG Reserved1[45]; /* */ - AT91_REG DBGU_RPR; /* Receive Pointer Register */ - AT91_REG DBGU_RCR; /* Receive Counter Register */ - AT91_REG DBGU_TPR; /* Transmit Pointer Register */ - AT91_REG DBGU_TCR; /* Transmit Counter Register */ - AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ - AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ - AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ - AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ - AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ - AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[7]; /* */ + AT91_REG DBGU_C1R; /* Chip ID1 Register */ + AT91_REG DBGU_C2R; /* Chip ID2 Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[45]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ } AT91S_DBGU, *AT91PS_DBGU; /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ @@ -247,7 +247,7 @@ typedef struct _AT91S_DBGU /*****************************************************************************/ typedef struct _AT91S_SMC2 { - AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ + AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ } AT91S_SMC2, *AT91PS_SMC2; /* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ @@ -272,21 +272,21 @@ typedef struct _AT91S_SMC2 /*****************************************************************************/ typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; /* System Clock Enable Register */ - AT91_REG PMC_SCDR; /* System Clock Disable Register */ - AT91_REG PMC_SCSR; /* System Clock Status Register */ - AT91_REG Reserved0[1]; /* */ - AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ - AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ - AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ - AT91_REG Reserved1[5]; /* */ - AT91_REG PMC_MCKR; /* Master Clock Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ - AT91_REG PMC_IER; /* Interrupt Enable Register */ - AT91_REG PMC_IDR; /* Interrupt Disable Register */ - AT91_REG PMC_SR; /* Status Register */ - AT91_REG PMC_IMR; /* Interrupt Mask Register */ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[5]; /* */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ } AT91S_PMC, *AT91PS_PMC; /*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ @@ -346,49 +346,49 @@ typedef struct _AT91S_PMC /*****************************************************************************/ typedef struct _AT91S_EMAC { - AT91_REG EMAC_CTL; /* Network Control Register */ - AT91_REG EMAC_CFG; /* Network Configuration Register */ - AT91_REG EMAC_SR; /* Network Status Register */ - AT91_REG EMAC_TAR; /* Transmit Address Register */ - AT91_REG EMAC_TCR; /* Transmit Control Register */ - AT91_REG EMAC_TSR; /* Transmit Status Register */ - AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ - AT91_REG Reserved0[1]; /* */ - AT91_REG EMAC_RSR; /* Receive Status Register */ - AT91_REG EMAC_ISR; /* Interrupt Status Register */ - AT91_REG EMAC_IER; /* Interrupt Enable Register */ - AT91_REG EMAC_IDR; /* Interrupt Disable Register */ - AT91_REG EMAC_IMR; /* Interrupt Mask Register */ - AT91_REG EMAC_MAN; /* PHY Maintenance Register */ - AT91_REG Reserved1[2]; /* */ - AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ - AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ - AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ - AT91_REG EMAC_OK; /* Frames Received OK Register */ - AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ - AT91_REG EMAC_ALE; /* Alignment Error Register */ - AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ - AT91_REG EMAC_LCOL; /* Late Collision Register */ - AT91_REG EMAC_ECOL; /* Excessive Collision Register */ - AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ - AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ - AT91_REG EMAC_CDE; /* Code Error Register */ - AT91_REG EMAC_ELR; /* Excessive Length Error Register */ - AT91_REG EMAC_RJB; /* Receive Jabber Register */ - AT91_REG EMAC_USF; /* Undersize Frame Register */ - AT91_REG EMAC_SQEE; /* SQE Test Error Register */ - AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ - AT91_REG Reserved2[3]; /* */ - AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ - AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ - AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ - AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ - AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ - AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ - AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ - AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ - AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ - AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ + AT91_REG EMAC_CTL; /* Network Control Register */ + AT91_REG EMAC_CFG; /* Network Configuration Register */ + AT91_REG EMAC_SR; /* Network Status Register */ + AT91_REG EMAC_TAR; /* Transmit Address Register */ + AT91_REG EMAC_TCR; /* Transmit Control Register */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG Reserved0[1]; /* */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG Reserved1[2]; /* */ + AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ + AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ + AT91_REG EMAC_OK; /* Frames Received OK Register */ + AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CDE; /* Code Error Register */ + AT91_REG EMAC_ELR; /* Excessive Length Error Register */ + AT91_REG EMAC_RJB; /* Receive Jabber Register */ + AT91_REG EMAC_USF; /* Undersize Frame Register */ + AT91_REG EMAC_SQEE; /* SQE Test Error Register */ + AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ + AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ } AT91S_EMAC, *AT91PS_EMAC; /* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ @@ -476,27 +476,27 @@ typedef struct _AT91S_EMAC /*****************************************************************************/ typedef struct _AT91S_SPI { - AT91_REG SPI_CR; /* Control Register */ - AT91_REG SPI_MR; /* Mode Register */ - AT91_REG SPI_RDR; /* Receive Data Register */ - AT91_REG SPI_TDR; /* Transmit Data Register */ - AT91_REG SPI_SR; /* Status Register */ - AT91_REG SPI_IER; /* Interrupt Enable Register */ - AT91_REG SPI_IDR; /* Interrupt Disable Register */ - AT91_REG SPI_IMR; /* Interrupt Mask Register */ - AT91_REG Reserved0[4]; /* */ - AT91_REG SPI_CSR[4]; /* Chip Select Register */ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[4]; /* */ + AT91_REG SPI_CSR[4]; /* Chip Select Register */ AT91_REG Reserved1[48]; /* */ - AT91_REG SPI_RPR; /* Receive Pointer Register */ - AT91_REG SPI_RCR; /* Receive Counter Register */ - AT91_REG SPI_TPR; /* Transmit Pointer Register */ - AT91_REG SPI_TCR; /* Transmit Counter Register */ - AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ - AT91_REG SPI_RNCR; /* Receive Next Counter Register */ - AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ - AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ - AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ - AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ } AT91S_SPI, *AT91PS_SPI; /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ @@ -560,16 +560,16 @@ typedef struct _AT91S_SPI /*****************************************************************************/ typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; /* Receive Pointer Register */ - AT91_REG PDC_RCR; /* Receive Counter Register */ - AT91_REG PDC_TPR; /* Transmit Pointer Register */ - AT91_REG PDC_TCR; /* Transmit Counter Register */ - AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ - AT91_REG PDC_RNCR; /* Receive Next Counter Register */ - AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ - AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ - AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ - AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ } AT91S_PDC, *AT91PS_PDC; /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ @@ -700,7 +700,7 @@ typedef struct _AT91S_PDC #define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ #define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ #define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ -#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ +#define AT91C_PIO_PB22 ((unsigned int) 1 << 22) /* Pin Controlled by PB22 */ #define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ #define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ #define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ @@ -775,7 +775,7 @@ typedef struct _AT91S_PDC #define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ #define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ #define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ -#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ diff --git a/include/asm-arm/arch-at91sam9/gpio.h b/include/asm-arm/arch-at91sam9/gpio.h index c157e107e1..c4d7b971be 100644 --- a/include/asm-arm/arch-at91sam9/gpio.h +++ b/include/asm-arm/arch-at91sam9/gpio.h @@ -218,7 +218,7 @@ static inline unsigned pin_to_mask(unsigned pin) */ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) { - void *pio = pin_to_controller(pin); + void *pio = pin_to_controller(pin); unsigned mask = pin_to_mask(pin); __raw_writel(mask, pio + PIO_IDR); @@ -232,7 +232,7 @@ static inline int at91_set_GPIO_periph(unsigned pin, int use_pullup) */ static inline int at91_set_A_periph(unsigned pin, int use_pullup) { - void *pio = pin_to_controller(pin); + void *pio = pin_to_controller(pin); unsigned mask = pin_to_mask(pin); __raw_writel(mask, pio + PIO_IDR); diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h index 11dc356a92..2114437dc7 100644 --- a/include/asm-arm/arch-ixp/ixp425.h +++ b/include/asm-arm/arch-ixp/ixp425.h @@ -53,13 +53,13 @@ * * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr * - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG + * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG * * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG * * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL * - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG + * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG */ /* @@ -171,17 +171,17 @@ #define IXP425_SDR_REFRESH_OFFSET 0x04 #define IXP425_SDR_IR_OFFSET 0x08 -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) +#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) #define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) +#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) +#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) /* * UART registers */ -#define IXP425_UART1 0 -#define IXP425_UART2 0x1000 +#define IXP425_UART1 0 +#define IXP425_UART2 0x1000 #define IXP425_UART_RBR_OFFSET 0x00 #define IXP425_UART_THR_OFFSET 0x00 @@ -476,49 +476,49 @@ */ /* CSR bit definitions */ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) +#define PCI_CSR_HOST BIT(0) +#define PCI_CSR_ARBEN BIT(1) +#define PCI_CSR_ADS BIT(2) +#define PCI_CSR_PDS BIT(3) +#define PCI_CSR_ABE BIT(4) +#define PCI_CSR_DBT BIT(5) +#define PCI_CSR_ASE BIT(8) +#define PCI_CSR_IC BIT(15) /* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) +#define PCI_ISR_PSE BIT(0) +#define PCI_ISR_PFE BIT(1) +#define PCI_ISR_PPE BIT(2) +#define PCI_ISR_AHBE BIT(3) +#define PCI_ISR_APDC BIT(4) +#define PCI_ISR_PADC BIT(5) +#define PCI_ISR_ADB BIT(6) +#define PCI_ISR_PDB BIT(7) /* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) +#define PCI_INTEN_PSE BIT(0) +#define PCI_INTEN_PFE BIT(1) +#define PCI_INTEN_PPE BIT(2) +#define PCI_INTEN_AHBE BIT(3) +#define PCI_INTEN_APDC BIT(4) +#define PCI_INTEN_PADC BIT(5) +#define PCI_INTEN_ADB BIT(6) +#define PCI_INTEN_PDB BIT(7) /* * Shift value for byte enable on NP cmd/byte enable register */ -#define IXP425_PCI_NP_CBE_BESL 4 +#define IXP425_PCI_NP_CBE_BESL 4 /* * PCI commands supported by NP access unit */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 +#define NP_CMD_IOREAD 0x2 +#define NP_CMD_IOWRITE 0x3 +#define NP_CMD_CONFIGREAD 0xa +#define NP_CMD_CONFIGWRITE 0xb +#define NP_CMD_MEMREAD 0x6 +#define NP_CMD_MEMWRITE 0x7 #if 0 #ifndef __ASSEMBLY__ diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h index 2a95af1810..2e92569a9c 100644 --- a/include/asm-arm/arch-omap24xx/clocks.h +++ b/include/asm-arm/arch-omap24xx/clocks.h @@ -35,9 +35,9 @@ ; PRCM Scheme II ; ; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] ; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] ; DSPI=100 6 CM_CLKSEL_DSP[6:5] ; DSP_S bypass CM_CLKSEL_DSP[7] @@ -64,9 +64,9 @@ ; PRCM Scheme III ; ; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] ; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] ; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] ; DSP_S ACTIVATED CM_CLKSEL_DSP[7] diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h index 2ac5ea21cf..104a21c2e4 100644 --- a/include/asm-arm/arch-pxa/bitfield.h +++ b/include/asm-arm/arch-pxa/bitfield.h @@ -1,13 +1,13 @@ /* - * FILE bitfield.h + * FILE bitfield.h * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. + * Purpose Definition of macros to operate on bit fields. */ @@ -35,11 +35,11 @@ * line-size limit). * * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. * * Output - * Fld Encoded bit field. + * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) @@ -54,14 +54,14 @@ * bit field. * * Input - * Field Encoded bit field (using the macro "Fld"). + * Field Encoded bit field (using the macro "Fld"). * * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) @@ -79,11 +79,11 @@ * former appropriately. * * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FInsrt Bit-field value positioned appropriately. + * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ @@ -98,11 +98,11 @@ * shifting it appropriately. * * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FExtr Bit-field value. + * FExtr Bit-field value. */ #define FExtr(Data, Field) \ diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index b9304b1bdc..9440d80b50 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -16,95 +16,95 @@ /* PXA-250 MMC controller registers */ /* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) +#define MMC_STRPCL_STOP_CLK (0x0001UL) #define MMC_STRPCL_START_CLK (0x0002UL) /* MMC_STAT */ #define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) +#define MMC_STAT_PRG_DONE (0x0001UL << 12) +#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) +#define MMC_STAT_CLK_EN (0x0001UL << 8) +#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) +#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) +#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) #define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) +#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) +#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) +#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) +#define MMC_STAT_READ_TIME_OUT (0x0001UL) #define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) /* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) +#define MMC_CLKRT_20MHZ (0x0000UL) +#define MMC_CLKRT_10MHZ (0x0001UL) +#define MMC_CLKRT_5MHZ (0x0002UL) #define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) +#define MMC_CLKRT_1_25MHZ (0x0004UL) +#define MMC_CLKRT_0_625MHZ (0x0005UL) +#define MMC_CLKRT_0_3125MHZ (0x0006UL) /* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) +#define MMC_SPI_DISABLE (0x00UL) +#define MMC_SPI_EN (0x01UL) +#define MMC_SPI_CS_EN (0x01UL << 2) +#define MMC_SPI_CS_ADDRESS (0x01UL << 3) +#define MMC_SPI_CRC_ON (0x01UL << 1) /* MMC_CMDAT */ #define MMC_CMDAT_SD_4DAT (0x0001UL << 8) #define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) +#define MMC_CMDAT_INIT (0x0001UL << 6) +#define MMC_CMDAT_BUSY (0x0001UL << 5) +#define MMC_CMDAT_BCR (0x0003UL << 5) #define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) +#define MMC_CMDAT_BLOCK (0x0000UL << 4) +#define MMC_CMDAT_WRITE (0x0001UL << 3) +#define MMC_CMDAT_READ (0x0000UL << 3) +#define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R0 (0) +#define MMC_CMDAT_R1 (0x0001UL) +#define MMC_CMDAT_R2 (0x0002UL) +#define MMC_CMDAT_R3 (0x0003UL) /* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ /* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ /* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ /* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) #define MMC_PRTBUF_BUF_FULL (0x00UL ) /* MMC_I_MASK */ #define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) #define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_MASK_STOP_CMD (0x01UL << 3) +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) +#define MMC_I_MASK_PRG_DONE (0x01UL << 1) #define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) +#define MMC_I_MASK_ALL (0x07fUL) /* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) #define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) +#define MMC_I_REG_STOP_CMD (0x01UL << 3) +#define MMC_I_REG_END_CMD_RES (0x01UL << 2) +#define MMC_I_REG_PRG_DONE (0x01UL << 1) +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) +#define MMC_I_REG_ALL (0x007fUL) /* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ #define CMD(x) (x) #define MMC_DEFAULT_RCA 1 @@ -112,11 +112,11 @@ #define MMC_BLOCK_SIZE 512 #define MMC_CMD_RESET 0 #define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_ALL_SEND_CID 2 #define MMC_CMD_SET_RCA 3 #define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 #define MMC_CMD_SEND_STATUS 13 #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_BLOCK 17 @@ -203,5 +203,4 @@ typedef struct mmc_csd ecc:2; } mmc_csd_t; - #endif /* __MMC_PXA_P_H__ */ diff --git a/include/asm-arm/arch-s3c24x0/memory.h b/include/asm-arm/arch-s3c24x0/memory.h index 333f218679..5e254d2356 100644 --- a/include/asm-arm/arch-s3c24x0/memory.h +++ b/include/asm-arm/arch-s3c24x0/memory.h @@ -103,10 +103,10 @@ extern unsigned long __phys_to_virt(unsigned long ppage); * The nodes are matched with the physical memory bank addresses which are * incidentally the same as virtual addresses. * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff + * node 0: 0xc0000000 - 0xc7ffffff + * node 1: 0xc8000000 - 0xcfffffff + * node 2: 0xd0000000 - 0xd7ffffff + * node 3: 0xd8000000 - 0xdfffffff */ #define NR_NODES 4 diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h index 2ac5ea21cf..104a21c2e4 100644 --- a/include/asm-arm/arch-sa1100/bitfield.h +++ b/include/asm-arm/arch-sa1100/bitfield.h @@ -1,13 +1,13 @@ /* - * FILE bitfield.h + * FILE bitfield.h * - * Version 1.1 - * Author Copyright (c) Marc A. Viredaz, 1998 - * DEC Western Research Laboratory, Palo Alto, CA - * Date April 1998 (April 1997) - * System Advanced RISC Machine (ARM) + * Version 1.1 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date April 1998 (April 1997) + * System Advanced RISC Machine (ARM) * Language C or ARM Assembly - * Purpose Definition of macros to operate on bit fields. + * Purpose Definition of macros to operate on bit fields. */ @@ -35,11 +35,11 @@ * line-size limit). * * Input - * Size Size of the bit field, in number of bits. - * Shft Shift value of the bit field with respect to bit 0. + * Size Size of the bit field, in number of bits. + * Shft Shift value of the bit field with respect to bit 0. * * Output - * Fld Encoded bit field. + * Fld Encoded bit field. */ #define Fld(Size, Shft) (((Size) << 16) + (Shft)) @@ -54,14 +54,14 @@ * bit field. * * Input - * Field Encoded bit field (using the macro "Fld"). + * Field Encoded bit field (using the macro "Fld"). * * Output - * FSize Size of the bit field, in number of bits. - * FShft Shift value of the bit field with respect to bit 0. - * FMsk Mask for the bit field. - * FAlnMsk Mask for the bit field, aligned on bit 0. - * F1stBit First bit of the bit field. + * FSize Size of the bit field, in number of bits. + * FShft Shift value of the bit field with respect to bit 0. + * FMsk Mask for the bit field. + * FAlnMsk Mask for the bit field, aligned on bit 0. + * F1stBit First bit of the bit field. */ #define FSize(Field) ((Field) >> 16) @@ -79,11 +79,11 @@ * former appropriately. * * Input - * Value Bit-field value. - * Field Encoded bit field (using the macro "Fld"). + * Value Bit-field value. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FInsrt Bit-field value positioned appropriately. + * FInsrt Bit-field value positioned appropriately. */ #define FInsrt(Value, Field) \ @@ -98,11 +98,11 @@ * shifting it appropriately. * * Input - * Data Data containing the bit-field to be extracted. - * Field Encoded bit field (using the macro "Fld"). + * Data Data containing the bit-field to be extracted. + * Field Encoded bit field (using the macro "Fld"). * * Output - * FExtr Bit-field value. + * FExtr Bit-field value. */ #define FExtr(Data, Field) \ diff --git a/include/asm-arm/u-boot.h b/include/asm-arm/u-boot.h index c120312e0a..b11d5558f0 100644 --- a/include/asm-arm/u-boot.h +++ b/include/asm-arm/u-boot.h @@ -47,7 +47,7 @@ typedef struct bd_info { { ulong start; ulong size; - } bi_dram[CONFIG_NR_DRAM_BANKS]; + } bi_dram[CONFIG_NR_DRAM_BANKS]; #ifdef CONFIG_HAS_ETH1 /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h index fcfbbb3c6c..6a33fef5a8 100644 --- a/include/asm-avr32/arch-at32ap700x/mmc.h +++ b/include/asm-avr32/arch-at32ap700x/mmc.h @@ -74,13 +74,13 @@ struct mmc_csd /* MMC Command numbers */ #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_ALL_SEND_CID 2 #define MMC_CMD_SET_RELATIVE_ADDR 3 #define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 #define MMC_CMD_SET_DSR 4 #define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 #define MMC_CMD_SEND_STATUS 13 #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_SINGLE_BLOCK 17 diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 7aa712fe0a..e36af2da3d 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -42,8 +42,8 @@ #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE -#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID -#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL +#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID +#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL /* Data Attibutes*/ diff --git a/include/asm-blackfin/shared_resources.h b/include/asm-blackfin/shared_resources.h index d280ffeeaa..2ac8990693 100644 --- a/include/asm-blackfin/shared_resources.h +++ b/include/asm-blackfin/shared_resources.h @@ -27,7 +27,7 @@ void swap_to(int device_id); -#define FLASH 0 +#define FLASH 0 #define ETHERNET 1 #endif /* _SHARED_RESOURCES_H_ */ diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h index d5abbbe52a..0f7e7a551e 100644 --- a/include/asm-i386/ic/sc520.h +++ b/include/asm-i386/ic/sc520.h @@ -25,209 +25,209 @@ #define _ASM_IC_SC520_H_ 1 /* Memory mapped configuration registers, MMCR */ -#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ -#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ -#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ -#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ -#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ -#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ -#define SC520_ECCCTL 0x0020 /* ECC Control Register */ -#define SC520_ECCSTA 0x0021 /* ECC Status Register */ -#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ -#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ -#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ -#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ -#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ -#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ -#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ -#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ -#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ -#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ -#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ -#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ -#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ -#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ -#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ -#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ -#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ -#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ -#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ -#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ -#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ -#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ -#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ -#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ -#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ -#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ -#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ -#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ -#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ -#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ -#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ -#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ -#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ -#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ -#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ -#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ -#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ -#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ -#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ -#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ -#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ -#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ -#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ -#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ -#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ -#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ -#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ -#define SC520_CLKSEL 0x0c26 /* Clock Select */ -#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ -#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ -#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ -#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ -#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ -#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ -#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ -#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ -#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ -#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ -#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ -#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ -#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ -#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ -#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ -#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ -#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ -#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ -#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ -#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ -#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ -#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ -#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ -#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ -#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ -#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ -#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ -#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ -#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ -#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ -#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ -#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ -#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ -#define SC520_SSICTL 0x0cd0 /* SSI Control */ -#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ -#define SC520_SSICMD 0x0cd2 /* SSI Command */ -#define SC520_SSISTA 0x0cd3 /* SSI Status */ -#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ -#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ -#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ -#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ -#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ -#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ -#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ -#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ -#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ -#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ -#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ -#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ -#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ -#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ -#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ -#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ -#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ -#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ -#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ -#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ -#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ -#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ -#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ -#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ -#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ -#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ -#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ -#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ -#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ -#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ -#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ -#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ -#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ -#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ -#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ -#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ -#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ -#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ -#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ -#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ -#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ -#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ -#define SC520_RESSTA 0x0d74 /* Reset Status Register */ -#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ -#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ -#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ -#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ -#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ -#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ -#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ -#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ -#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ -#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ -#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ -#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ -#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ -#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ -#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ -#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ -#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ -#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ -#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ -#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ -#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ -#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ -#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ -#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ -#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ -#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ -#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ -#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ -#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ -#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ +#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ +#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ +#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ +#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ +#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ +#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ +#define SC520_ECCCTL 0x0020 /* ECC Control Register */ +#define SC520_ECCSTA 0x0021 /* ECC Status Register */ +#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ +#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ +#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ +#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ +#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ +#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ +#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ +#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ +#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ +#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ +#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ +#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ +#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ +#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ +#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ +#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ +#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ +#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ +#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ +#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ +#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ +#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ +#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ +#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ +#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ +#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ +#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ +#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ +#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ +#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ +#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ +#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ +#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ +#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ +#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ +#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ +#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ +#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ +#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ +#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ +#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ +#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ +#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ +#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ +#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ +#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ +#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ +#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ +#define SC520_CLKSEL 0x0c26 /* Clock Select */ +#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ +#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ +#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ +#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ +#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ +#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ +#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ +#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ +#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ +#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ +#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ +#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ +#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ +#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ +#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ +#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ +#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ +#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ +#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ +#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ +#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ +#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ +#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ +#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ +#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ +#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ +#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ +#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ +#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ +#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ +#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ +#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ +#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ +#define SC520_SSICTL 0x0cd0 /* SSI Control */ +#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ +#define SC520_SSICMD 0x0cd2 /* SSI Command */ +#define SC520_SSISTA 0x0cd3 /* SSI Status */ +#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ +#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ +#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ +#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ +#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ +#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ +#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ +#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ +#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ +#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ +#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ +#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ +#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ +#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ +#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ +#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ +#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ +#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ +#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ +#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ +#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ +#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ +#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ +#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ +#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ +#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ +#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ +#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ +#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ +#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ +#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ +#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ +#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ +#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ +#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ +#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ +#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ +#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ +#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ +#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ +#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ +#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ +#define SC520_RESSTA 0x0d74 /* Reset Status Register */ +#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ +#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ +#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ +#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ +#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ +#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ +#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ +#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ +#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ +#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ +#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ +#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ +#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ +#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ +#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ +#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ +#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ +#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ +#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ +#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ +#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ +#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ +#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ +#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ +#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ +#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ +#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ +#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ +#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ +#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ +#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ /* MMCR Register bits (not all of them :) ) */ /* SSI Stuff */ -#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ -#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ -#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ -#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ -#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ -#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ -#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ -#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ +#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */ +#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */ +#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */ +#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */ +#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */ +#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */ +#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */ +#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */ -#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ -#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ -#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ -#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ +#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */ +#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */ +#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */ +#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */ -#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ -#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ -#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ -#define SSISTA_BSY 0x02 /* SSI Busy */ -#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ +#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */ +#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */ +#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */ +#define SSISTA_BSY 0x02 /* SSI Busy */ +#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ /* BITS for SC520_ADDDECCTL: */ -#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ -#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ -#define RTC_DIS 0x04 /* RTC Disable */ -#define UART2_DIS 0x02 /* UART2 Disable */ -#define UART1_DIS 0x01 /* UART1 Disable */ +#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ +#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ +#define RTC_DIS 0x04 /* RTC Disable */ +#define UART2_DIS 0x02 /* UART2 Disable */ +#define UART1_DIS 0x01 /* UART1 Disable */ /* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */ #define SC520_REG_ADDR 0x00000cf8 @@ -256,7 +256,7 @@ /* PCI bus memory from 0x10000000 to 0x26ffffff * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */ #define SC520_PCI_MEM_PHYS 0x10000000 -#define SC520_PCI_MEM_BUS 0x10000000 +#define SC520_PCI_MEM_BUS 0x10000000 #define SC520_PCI_MEM_SIZE 0x17000000 /* 0x28000000 - 0x3fffffff is used by the flash banks */ diff --git a/include/asm-m68k/m5249.h b/include/asm-m68k/m5249.h index 5ed3cbc056..facf0c9090 100644 --- a/include/asm-m68k/m5249.h +++ b/include/asm-m68k/m5249.h @@ -58,7 +58,7 @@ #define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ #define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ #define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ +#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ #define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ #define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h index 7473bb9be6..f6a6b0408f 100644 --- a/include/asm-m68k/m5282.h +++ b/include/asm-m68k/m5282.h @@ -382,15 +382,15 @@ #define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A)) /* Bit level definitions and macros */ -#define MCFCCM_CCR_LOAD (0x8000) -#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8) -#define MCFCCM_CCR_SZEN (0x0040) -#define MCFCCM_CCR_PSTEN (0x0020) -#define MCFCCM_CCR_BME (0x0008) -#define MCFCCM_CCR_BMT(x) (((x)&0x0007)) +#define MCFCCM_CCR_LOAD (0x8000) +#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8) +#define MCFCCM_CCR_SZEN (0x0040) +#define MCFCCM_CCR_PSTEN (0x0020) +#define MCFCCM_CCR_BME (0x0008) +#define MCFCCM_CCR_BMT(x) (((x)&0x0007)) -#define MCFCCM_CIR_PIN_MASK (0xFF00) -#define MCFCCM_CIR_PRN_MASK (0x00FF) +#define MCFCCM_CIR_PIN_MASK (0xFF00) +#define MCFCCM_CIR_PRN_MASK (0x00FF) /* Clock Module */ @@ -554,7 +554,7 @@ #define MCFGPT_GPTIE_C1I (0x02) #define MCFGPT_GPTIE_C0I (0x01) -#define MCFGPT_GPTSCR2_TOI (0x80) +#define MCFGPT_GPTSCR2_TOI (0x80) #define MCFGPT_GPTSCR2_PUPT (0x20) #define MCFGPT_GPTSCR2_RDPT (0x10) #define MCFGPT_GPTSCR2_TCRE (0x08) diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h index f10f89c941..deb23e094a 100644 --- a/include/asm-microblaze/asm.h +++ b/include/asm-microblaze/asm.h @@ -74,7 +74,7 @@ { \ register unsigned tmp; \ __asm__ __volatile__ (" \ - mfs %0, rmsr; \ + mfs %0, rmsr; \ ori %0, %0, "#val"; \ mts rmsr, %0; \ nop;" \ @@ -87,7 +87,7 @@ { \ register unsigned tmp; \ __asm__ __volatile__ (" \ - mfs %0, rmsr; \ + mfs %0, rmsr; \ andi %0, %0, ~"#val"; \ mts rmsr, %0; \ nop;" \ diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h index a4e9947d93..6a33197f6c 100644 --- a/include/asm-mips/au1x00.h +++ b/include/asm-mips/au1x00.h @@ -5,7 +5,7 @@ * * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * ppopov@mvista.com or source@mvista.com * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h index 256ad2cc6e..70bcad7694 100644 --- a/include/asm-mips/cacheops.h +++ b/include/asm-mips/cacheops.h @@ -21,7 +21,7 @@ #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 #if defined(CONFIG_CPU_LOONGSON2) -#define Hit_Invalidate_I 0x00 +#define Hit_Invalidate_I 0x00 #else #define Hit_Invalidate_I 0x10 #endif diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 0586c53d3b..61a0dac1ce 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -283,7 +283,7 @@ set_cp0_##name(unsigned int set) \ \ res = read_32bit_cp0_register(register); \ res |= set; \ - write_32bit_cp0_register(register, res); \ + write_32bit_cp0_register(register, res); \ \ return res; \ } \ @@ -332,7 +332,7 @@ __BUILD_SET_CP0(config,CP0_CONFIG) # define KSU_KERNEL 0x00000000 #define ST0_UX 0x00000020 #define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 +#define ST0_KX 0x00000080 #define ST0_DE 0x00010000 #define ST0_CE 0x00020000 @@ -362,22 +362,22 @@ __BUILD_SET_CP0(config,CP0_CONFIG) */ #define TX39_CONF_ICS_SHIFT 19 #define TX39_CONF_ICS_MASK 0x00380000 -#define TX39_CONF_ICS_1KB 0x00000000 -#define TX39_CONF_ICS_2KB 0x00080000 -#define TX39_CONF_ICS_4KB 0x00100000 -#define TX39_CONF_ICS_8KB 0x00180000 -#define TX39_CONF_ICS_16KB 0x00200000 +#define TX39_CONF_ICS_1KB 0x00000000 +#define TX39_CONF_ICS_2KB 0x00080000 +#define TX39_CONF_ICS_4KB 0x00100000 +#define TX39_CONF_ICS_8KB 0x00180000 +#define TX39_CONF_ICS_16KB 0x00200000 #define TX39_CONF_DCS_SHIFT 16 #define TX39_CONF_DCS_MASK 0x00070000 -#define TX39_CONF_DCS_1KB 0x00000000 -#define TX39_CONF_DCS_2KB 0x00010000 -#define TX39_CONF_DCS_4KB 0x00020000 -#define TX39_CONF_DCS_8KB 0x00030000 -#define TX39_CONF_DCS_16KB 0x00040000 - -#define TX39_CONF_CWFON 0x00004000 -#define TX39_CONF_WBON 0x00002000 +#define TX39_CONF_DCS_1KB 0x00000000 +#define TX39_CONF_DCS_2KB 0x00010000 +#define TX39_CONF_DCS_4KB 0x00020000 +#define TX39_CONF_DCS_8KB 0x00030000 +#define TX39_CONF_DCS_16KB 0x00040000 + +#define TX39_CONF_CWFON 0x00004000 +#define TX39_CONF_WBON 0x00002000 #define TX39_CONF_RF_SHIFT 10 #define TX39_CONF_RF_MASK 0x00000c00 #define TX39_CONF_DOZE 0x00000200 diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index 12a0bd9152..8b788068b3 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -34,21 +34,21 @@ #define readb(addr)\ ({unsigned char val;\ asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ + " ld %0, [%1] \n"\ " ext8d %0, %1 \n"\ :"=r"(val) : "r" (addr)); val;}) #define readw(addr)\ ({unsigned short val;\ asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ + " ld %0, [%1] \n"\ " ext16d %0, %1 \n"\ :"=r"(val) : "r" (addr)); val;}) #define readl(addr)\ ({unsigned long val;\ asm volatile( " pfxio 0 \n"\ - " ld %0, [%1] \n"\ + " ld %0, [%1] \n"\ :"=r"(val) : "r" (addr)); val;}) #define writeb(addr,val)\ diff --git a/include/asm-ppc/4xx_pci.h b/include/asm-ppc/4xx_pci.h index 3c1adec19c..30125a19ef 100644 --- a/include/asm-ppc/4xx_pci.h +++ b/include/asm-ppc/4xx_pci.h @@ -47,6 +47,6 @@ #define PTM2MS 0xEF400038 #define PTM2LA 0xEF40003C -#define PCIDEVID_405GP 0x0 +#define PCIDEVID_405GP 0x0 #endif diff --git a/include/asm-ppc/5xx_immap.h b/include/asm-ppc/5xx_immap.h index 8e570573b6..72cbab43e4 100644 --- a/include/asm-ppc/5xx_immap.h +++ b/include/asm-ppc/5xx_immap.h @@ -408,31 +408,31 @@ typedef struct uimb { /* Internal Memory Map MPC555 */ typedef struct immap { - char res1[262144]; /* CMF Flash A 256 Kbytes */ - char res2[196608]; /* CMF Flash B 192 Kbytes */ - char res3[2670592]; /* Reserved for Flash */ - sysconf5xx_t im_siu_conf; /* SIU Configuration */ + char res1[262144]; /* CMF Flash A 256 Kbytes */ + char res2[196608]; /* CMF Flash B 192 Kbytes */ + char res3[2670592]; /* Reserved for Flash */ + sysconf5xx_t im_siu_conf; /* SIU Configuration */ memctl5xx_t im_memctl; /* Memory Controller */ sit5xx_t im_sit; /* System Integration Timers */ car5xx_t im_clkrst; /* Clocks and Reset */ - sitk5xx_t im_sitk; /* System Integration Timer Keys*/ - cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ + sitk5xx_t im_sitk; /* System Integration Timer Keys*/ + cark8xx_t im_clkrstk; /* Clocks and Resert Keys */ fl5xx_t im_fla; /* Flash Module A */ fl5xx_t im_flb; /* Flash Module B */ - char res4[14208]; /* Reserved for SIU */ - dprc5xx_t im_dprc; /* Dpram Control Register */ - char res5[8180]; /* Reserved */ - char dptram[6144]; /* Dptram */ - char res6[2048]; /* Reserved */ + char res4[14208]; /* Reserved for SIU */ + dprc5xx_t im_dprc; /* Dpram Control Register */ + char res5[8180]; /* Reserved */ + char dptram[6144]; /* Dptram */ + char res6[2048]; /* Reserved */ tpu5xx_t im_tpua; /* Time Proessing Unit A */ - tpu5xx_t im_tpub; /* Time Processing Unit B */ - qadc5xx_t im_qadca; /* QADC A */ - qadc5xx_t im_qadcb; /* QADC B */ + tpu5xx_t im_tpub; /* Time Processing Unit B */ + qadc5xx_t im_qadca; /* QADC A */ + qadc5xx_t im_qadcb; /* QADC B */ qsmcm5xx_t im_qsmcm; /* SCI and SPI */ - mios5xx_t im_mios; /* MIOS */ - tcan5xx_t im_tcana; /* Toucan A */ - tcan5xx_t im_tcanb; /* Toucan B */ - char res7[1792]; /* Reserved */ + mios5xx_t im_mios; /* MIOS */ + tcan5xx_t im_tcana; /* Toucan A */ + tcan5xx_t im_tcanb; /* Toucan B */ + char res7[1792]; /* Reserved */ uimb5xx_t im_uimb; /* UIMB */ } immap_t; diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index de8239965a..05db0de8f8 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -16,59 +16,59 @@ */ /* #define HID0 1008 already defined in processor.h */ -#define HID0_MASK_MACHINE_CHECK 0x00000000 -#define HID0_ENABLE_MACHINE_CHECK 0x80000000 +#define HID0_MASK_MACHINE_CHECK 0x00000000 +#define HID0_ENABLE_MACHINE_CHECK 0x80000000 -#define HID0_DISABLE_CACHE_PARITY 0x00000000 -#define HID0_ENABLE_CACHE_PARITY 0x40000000 +#define HID0_DISABLE_CACHE_PARITY 0x00000000 +#define HID0_ENABLE_CACHE_PARITY 0x40000000 -#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 +#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ +#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 -#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ -#define HID0_ENABLE_DATE_PARITY 0x10000000 +#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ +#define HID0_ENABLE_DATE_PARITY 0x10000000 -#define HID0_CORE_CLK_OUT 0x00000000 -#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 +#define HID0_CORE_CLK_OUT 0x00000000 +#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 #define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ #define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 -#define HID0_DISABLE_DOSE_MODE 0x00000000 -#define HID0_ENABLE_DOSE_MODE 0x00800000 +#define HID0_DISABLE_DOSE_MODE 0x00000000 +#define HID0_ENABLE_DOSE_MODE 0x00800000 -#define HID0_DISABLE_NAP_MODE 0x00000000 -#define HID0_ENABLE_NAP_MODE 0x00400000 +#define HID0_DISABLE_NAP_MODE 0x00000000 +#define HID0_ENABLE_NAP_MODE 0x00400000 -#define HID0_DISABLE_SLEEP_MODE 0x00000000 -#define HID0_ENABLE_SLEEP_MODE 0x00200000 +#define HID0_DISABLE_SLEEP_MODE 0x00000000 +#define HID0_ENABLE_SLEEP_MODE 0x00200000 #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 -#define HID0_SOFT_RESET 0x00010000 +#define HID0_SOFT_RESET 0x00010000 -#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 -#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 +#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 +#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 -#define HID0_DISABLE_DATA_CACHE 0x00000000 -#define HID0_ENABLE_DATA_CACHE 0x00004000 +#define HID0_DISABLE_DATA_CACHE 0x00000000 +#define HID0_ENABLE_DATA_CACHE 0x00004000 -#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 +#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 -#define HID0_LOCK_DATA_CACHE 0x00001000 +#define HID0_LOCK_DATA_CACHE 0x00001000 #define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 -#define HID0_INVALIDATE_DATA_CACHE 0x00000400 +#define HID0_INVALIDATE_DATA_CACHE 0x00000400 -#define HID0_DISABLE_M_BIT 0x00000000 -#define HID0_ENABLE_M_BIT 0x00000080 +#define HID0_DISABLE_M_BIT 0x00000000 +#define HID0_ENABLE_M_BIT 0x00000080 -#define HID0_FBIOB 0x00000010 +#define HID0_FBIOB 0x00000010 -#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 -#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 +#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 +#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 @@ -90,37 +90,37 @@ /* BAT (block address translation */ -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 +#define BATU_BEPI_MSK 0xfffe0000 +#define BATU_BL_MSK 0x00001ffc + +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 + +#define BATL_BRPN_MSK 0xfffe0000 +#define BATL_WIMG_MSK 0x00000078 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 #endif /* __E300_H__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 2d07625464..113ba482da 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1054,7 +1054,7 @@ typedef struct ccsr_cpm { * 0x9000-0x90bff: General SIU */ typedef struct ccsr_cpm_siu { - char res1[80]; + char res1[80]; uint smaer; uint smser; uint smevr; @@ -1143,9 +1143,9 @@ typedef struct ccsr_cpm_timer { /* 0x91018-0x912ff: SDMA */ typedef struct ccsr_cpm_sdma { uchar sdsr; - char res1[3]; - uchar sdmr; - char res2[739]; + char res1[3]; + uchar sdmr; + char res2[739]; } ccsr_cpm_sdma_t; /* 0x91300-0x9131f: FCC1 */ @@ -1228,7 +1228,7 @@ typedef struct ccsr_cpm_fcc3_ext { /* 0x91400-0x915ef: TC layers */ typedef struct ccsr_cpm_tmp1 { - char res[496]; + char res[496]; } ccsr_cpm_tmp1_t; /* 0x915f0-0x9185f: BRGs:5,6,7,8 */ @@ -1296,7 +1296,7 @@ typedef struct ccsr_cpm_scc { /* 0x91a80-0x91a9f */ typedef struct ccsr_cpm_tmp2 { - char res[32]; + char res[32]; } ccsr_cpm_tmp2_t; /* 0x91aa0-0x91aff: SPI */ @@ -1338,16 +1338,16 @@ typedef struct ccsr_cpm { /* Some references are into the unique and known dpram spaces, * others are from the generic base. */ -#define im_dprambase im_dpram1 - u_char im_dpram1[16*1024]; - char res1[16*1024]; - u_char im_dpram2[16*1024]; - char res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ - ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ - ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ - ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ - ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ +#define im_dprambase im_dpram1 + u_char im_dpram1[16*1024]; + char res1[16*1024]; + u_char im_dpram2[16*1024]; + char res2[16*1024]; + ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ + ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ + ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ + ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ + ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ ccsr_cpm_fcc1_t im_cpm_fcc1; ccsr_cpm_fcc2_t im_cpm_fcc2; ccsr_cpm_fcc3_t im_cpm_fcc3; @@ -1553,7 +1553,7 @@ typedef struct par_io { typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */ -#define MPC85xx_PORBMSR_HA 0x00070000 +#define MPC85xx_PORBMSR_HA 0x00070000 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 @@ -1561,13 +1561,13 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 #define MPC85xx_PORDEVSR_IO_SEL 0x00380000 -#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 -#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 -#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 -#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 -#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 +#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 +#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 +#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 +#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 +#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 -#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 +#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ @@ -1593,13 +1593,13 @@ typedef struct ccsr_gur { #define MPC85xx_DEVDISR_SEC 0x01000000 #define MPC85xx_DEVDISR_SRIO 0x00080000 #define MPC85xx_DEVDISR_RMSG 0x00040000 -#define MPC85xx_DEVDISR_DDR 0x00010000 -#define MPC85xx_DEVDISR_CPU 0x00008000 -#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU -#define MPC85xx_DEVDISR_TB 0x00004000 -#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB -#define MPC85xx_DEVDISR_CPU1 0x00002000 -#define MPC85xx_DEVDISR_TB1 0x00001000 +#define MPC85xx_DEVDISR_DDR 0x00010000 +#define MPC85xx_DEVDISR_CPU 0x00008000 +#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU +#define MPC85xx_DEVDISR_TB 0x00004000 +#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB +#define MPC85xx_DEVDISR_CPU1 0x00002000 +#define MPC85xx_DEVDISR_TB1 0x00001000 #define MPC85xx_DEVDISR_DMA 0x00000400 #define MPC85xx_DEVDISR_TSEC1 0x00000080 #define MPC85xx_DEVDISR_TSEC2 0x00000040 diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 0b78c94f7c..c03b4b8157 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -119,7 +119,7 @@ typedef struct ccsr_ddr { uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ + uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ char res8[4]; uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ char res9[12]; @@ -464,7 +464,7 @@ typedef struct ccsr_dma { /* tsec1-4: 24000-28000 */ typedef struct ccsr_tsec { - uint id; /* 0x24000 - Controller ID Register */ + uint id; /* 0x24000 - Controller ID Register */ char res1[12]; uint ievent; /* 0x24010 - Interrupt Event Register */ uint imask; /* 0x24014 - Interrupt Mask Register */ @@ -538,7 +538,7 @@ typedef struct ccsr_tsec { uint rbifx; /* 0x24330 - Receive bit field extract control Register */ uint rqfar; /* 0x24334 - Receive queue filing table address Register */ uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ - uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ + uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ char res28[56]; uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 49d6860fc7..4f78ca7a94 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -343,7 +343,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) #define MAS0_NV(x) ((x) & 0x00000FFF) -#define MAS1_VALID 0x80000000 +#define MAS1_VALID 0x80000000 #define MAS1_IPROT 0x40000000 #define MAS1_TID(x) ((x << 16) & 0x3FFF0000) #define MAS1_TS 0x00001000 @@ -685,7 +685,7 @@ extern int num_tlb_entries; #define MSYNC .long 0x7c000000|\ (598<<1) -#define MBAR_INST .long 0x7c000000|\ +#define MBAR_INST .long 0x7c000000|\ (854<<1) #ifndef __ASSEMBLY__ diff --git a/include/asm-ppc/ppc4xx-intvec.h b/include/asm-ppc/ppc4xx-intvec.h index e2181190e3..5b45de4335 100644 --- a/include/asm-ppc/ppc4xx-intvec.h +++ b/include/asm-ppc/ppc4xx-intvec.h @@ -323,9 +323,9 @@ #define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ #define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ -#define VECNUM_MS 18 /* MAL_SERR_INT */ -#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ -#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ +#define VECNUM_MS 18 /* MAL_SERR_INT */ +#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ +#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ #define VECNUM_MTE 19 /* MAL TXEOB */ #define VECNUM_MTE1 20 /* MAL TXEOB1 */ diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h index 3c2f4e605a..196613b9f1 100644 --- a/include/asm-ppc/ptrace.h +++ b/include/asm-ppc/ptrace.h @@ -39,7 +39,7 @@ struct pt_regs { PPC_REG trap; /* Reason for being here */ PPC_REG dar; /* Fault registers */ PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ + PPC_REG result; /* Result of a system call */ }; #endif diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h index 4bd66a707d..715c868ab6 100644 --- a/include/asm-ppc/sigcontext.h +++ b/include/asm-ppc/sigcontext.h @@ -9,7 +9,7 @@ struct sigcontext_struct { int signal; unsigned long handler; unsigned long oldmask; - struct pt_regs *regs; + struct pt_regs *regs; }; #endif diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 786ba030ea..83af2f584e 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -126,14 +126,14 @@ typedef struct bd_info { #if defined(CONFIG_4xx) #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) - int bi_phynum[4]; /* Determines phy mapping */ - int bi_phymode[4]; /* Determines phy mode */ + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ #elif defined(CONFIG_405EP) || defined(CONFIG_440) - int bi_phynum[2]; /* Determines phy mapping */ - int bi_phymode[2]; /* Determines phy mode */ + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ #else - int bi_phynum[1]; /* Determines phy mapping */ - int bi_phymode[1]; /* Determines phy mode */ + int bi_phynum[1]; /* Determines phy mapping */ + int bi_phymode[1]; /* Determines phy mode */ #endif #endif /* defined(CONFIG_4xx) */ } bd_t; diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h index 3c3c30980a..4e43a465e6 100644 --- a/include/asm-sh/cpu_sh7750.h +++ b/include/asm-sh/cpu_sh7750.h @@ -32,108 +32,108 @@ #endif /* OCN */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define BASRA 0xFF000014 +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define BASRA 0xFF000014 #define BASRB 0xFF000018 #define CCR 0xFF00001C -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 -#define PTEA 0xFF000034 -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 +#define PTEA 0xFF000034 +#define QACR0 0xFF000038 +#define QACR1 0xFF00003C /* UBC */ -#define BARA 0xFF200000 -#define BAMRA 0xFF200004 -#define BBRA 0xFF200008 -#define BARB 0xFF20000C -#define BAMRB 0xFF200010 -#define BBRB 0xFF200014 -#define BDRB 0xFF200018 -#define BDMRB 0xFF20001C -#define BRCR 0xFF200020 +#define BARA 0xFF200000 +#define BAMRA 0xFF200004 +#define BBRA 0xFF200008 +#define BARB 0xFF20000C +#define BAMRB 0xFF200010 +#define BBRB 0xFF200014 +#define BDRB 0xFF200018 +#define BDMRB 0xFF20001C +#define BRCR 0xFF200020 /* BSC */ #define BCR1 0xFF800000 #define BCR2 0xFF800004 -#define BCR3 0xFF800050 +#define BCR3 0xFF800050 #define BCR4 0xFE0A00F0 -#define WCR1 0xFF800008 -#define WCR2 0xFF80000C -#define WCR3 0xFF800010 -#define MCR 0xFF800014 -#define PCR 0xFF800018 -#define RTCSR 0xFF80001C -#define RTCNT 0xFF800020 -#define RTCOR 0xFF800024 -#define RFCR 0xFF800028 -#define PCTRA 0xFF80002C -#define PDTRA 0xFF800030 -#define PCTRB 0xFF800040 -#define PDTRB 0xFF800044 -#define GPIOIC 0xFF800048 +#define WCR1 0xFF800008 +#define WCR2 0xFF80000C +#define WCR3 0xFF800010 +#define MCR 0xFF800014 +#define PCR 0xFF800018 +#define RTCSR 0xFF80001C +#define RTCNT 0xFF800020 +#define RTCOR 0xFF800024 +#define RFCR 0xFF800028 +#define PCTRA 0xFF80002C +#define PDTRA 0xFF800030 +#define PCTRB 0xFF800040 +#define PDTRB 0xFF800044 +#define GPIOIC 0xFF800048 /* DMAC */ -#define SAR0 0xFFA00000 -#define DAR0 0xFFA00004 +#define SAR0 0xFFA00000 +#define DAR0 0xFFA00004 #define DMATCR0 0xFFA00008 #define CHCR0 0xFFA0000C -#define SAR1 0xFFA00010 -#define DAR1 0xFFA00014 +#define SAR1 0xFFA00010 +#define DAR1 0xFFA00014 #define DMATCR1 0xFFA00018 -#define CHCR1 0xFFA0001C -#define SAR2 0xFFA00020 -#define DAR2 0xFFA00024 +#define CHCR1 0xFFA0001C +#define SAR2 0xFFA00020 +#define DAR2 0xFFA00024 #define DMATCR2 0xFFA00028 -#define CHCR2 0xFFA0002C -#define SAR3 0xFFA00030 -#define DAR3 0xFFA00034 +#define CHCR2 0xFFA0002C +#define SAR3 0xFFA00030 +#define DAR3 0xFFA00034 #define DMATCR3 0xFFA00038 -#define CHCR3 0xFFA0003C -#define DMAOR 0xFFA00040 +#define CHCR3 0xFFA0003C +#define DMAOR 0xFFA00040 #define SAR4 0xFFA00050 -#define DAR4 0xFFA00054 +#define DAR4 0xFFA00054 #define DMATCR4 0xFFA00058 /* CPG */ -#define FRQCR 0xFFC00000 -#define STBCR 0xFFC00004 -#define WTCNT 0xFFC00008 -#define WTCSR 0xFFC0000C -#define STBCR2 0xFFC00010 +#define FRQCR 0xFFC00000 +#define STBCR 0xFFC00004 +#define WTCNT 0xFFC00008 +#define WTCSR 0xFFC0000C +#define STBCR2 0xFFC00010 /* RTC */ #define R64CNT 0xFFC80000 #define RSECCNT 0xFFC80004 #define RMINCNT 0xFFC80008 -#define RHRCNT 0xFFC8000C -#define RWKCNT 0xFFC80010 +#define RHRCNT 0xFFC8000C +#define RWKCNT 0xFFC80010 #define RDAYCNT 0xFFC80014 #define RMONCNT 0xFFC80018 -#define RYRCNT 0xFFC8001C -#define RSECAR 0xFFC80020 -#define RMINAR 0xFFC80024 -#define RHRAR 0xFFC80028 -#define RWKAR 0xFFC8002C -#define RDAYAR 0xFFC80030 -#define RMONAR 0xFFC80034 -#define RCR1 0xFFC80038 -#define RCR2 0xFFC8003C -#define RCR3 0xFFC80050 -#define RYRAR 0xFFC80054 +#define RYRCNT 0xFFC8001C +#define RSECAR 0xFFC80020 +#define RMINAR 0xFFC80024 +#define RHRAR 0xFFC80028 +#define RWKAR 0xFFC8002C +#define RDAYAR 0xFFC80030 +#define RMONAR 0xFFC80034 +#define RCR1 0xFFC80038 +#define RCR2 0xFFC8003C +#define RCR3 0xFFC80050 +#define RYRAR 0xFFC80054 /* ICR */ -#define ICR 0xFFD00000 -#define IPRA 0xFFD00004 -#define IPRB 0xFFD00008 +#define ICR 0xFFD00000 +#define IPRA 0xFFD00004 +#define IPRB 0xFFD00008 #define IPRC 0xFFD0000C -#define IPRD 0xFFD00010 -#define INTPRI 0xFE080000 +#define IPRD 0xFFD00010 +#define INTPRI 0xFE080000 #define INTREQ 0xFE080020 #define INTMSK 0xFE080040 #define INTMSKCL 0xFE080060 @@ -143,54 +143,54 @@ #define CLKSTPCLR 0xFE0A0008 /* TMU */ -#define TSTR2 0xFE100004 -#define TCOR3 0xFE100008 -#define TCNT3 0xFE10000C -#define TCR3 0xFE100010 -#define TCOR4 0xFE100014 -#define TCNT4 0xFE100018 -#define TCR4 0xFE10001C -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 +#define TSTR2 0xFE100004 +#define TCOR3 0xFE100008 +#define TCNT3 0xFE10000C +#define TCR3 0xFE100010 +#define TCOR4 0xFE100014 +#define TCNT4 0xFE100018 +#define TCR4 0xFE10001C +#define TOCR 0xFFD80000 +#define TSTR0 0xFFD80004 #define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 +#define TCPR2 0xFFD8002C #define TSTR TSTR0 /* SCI */ -#define SCSMR1 0xFFE00000 -#define SCBRR1 0xFFE00004 -#define SCSCR1 0xFFE00008 -#define SCTDR1 0xFFE0000C -#define SCSSR1 0xFFE00010 -#define SCRDR1 0xFFE00014 +#define SCSMR1 0xFFE00000 +#define SCBRR1 0xFFE00004 +#define SCSCR1 0xFFE00008 +#define SCTDR1 0xFFE0000C +#define SCSSR1 0xFFE00010 +#define SCRDR1 0xFFE00014 #define SCSCMR1 0xFFE00018 #define SCSPTR1 0xFFE0001C #define SCF0_BASE SCSMR1 /* SCIF */ -#define SCSMR2 0xFFE80000 -#define SCBRR2 0xFFE80004 -#define SCSCR2 0xFFE80008 +#define SCSMR2 0xFFE80000 +#define SCBRR2 0xFFE80004 +#define SCSCR2 0xFFE80008 #define SCFTDR2 0xFFE8000C -#define SCFSR2 0xFFE80010 +#define SCFSR2 0xFFE80010 #define SCFRDR2 0xFFE80014 -#define SCFCR2 0xFFE80018 -#define SCFDR2 0xFFE8001C +#define SCFCR2 0xFFE80018 +#define SCFDR2 0xFFE8001C #define SCSPTR2 0xFFE80020 -#define SCLSR2 0xFFE80024 +#define SCLSR2 0xFFE80024 #define SCIF1_BASE SCSMR2 /* H-UDI */ -#define SDIR 0xFFF00000 -#define SDDR 0xFFF00008 -#define SDINT 0xFFF00014 +#define SDIR 0xFFF00000 +#define SDDR 0xFFF00008 +#define SDINT 0xFFF00014 #endif /* _ASM_CPU_SH7750_H_ */ diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h index 14cc1aca63..16252cc25b 100644 --- a/include/asm-sh/ptrace.h +++ b/include/asm-sh/ptrace.h @@ -28,7 +28,7 @@ #define REG_PR 17 #define REG_SR 18 -#define REG_GBR 19 +#define REG_GBR 19 #define REG_MACH 20 #define REG_MACL 21 diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h index b353bc5c3b..a62c42261d 100644 --- a/include/asm-sh/system.h +++ b/include/asm-sh/system.h @@ -23,21 +23,21 @@ register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \ register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \ register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \ - __asm__ __volatile__ (".balign 4\n\t" \ - "stc.l gbr, @-r15\n\t" \ - "sts.l pr, @-r15\n\t" \ - "mov.l r8, @-r15\n\t" \ - "mov.l r9, @-r15\n\t" \ - "mov.l r10, @-r15\n\t" \ - "mov.l r11, @-r15\n\t" \ - "mov.l r12, @-r15\n\t" \ - "mov.l r13, @-r15\n\t" \ - "mov.l r14, @-r15\n\t" \ + __asm__ __volatile__ (".balign 4\n\t" \ + "stc.l gbr, @-r15\n\t" \ + "sts.l pr, @-r15\n\t" \ + "mov.l r8, @-r15\n\t" \ + "mov.l r9, @-r15\n\t" \ + "mov.l r10, @-r15\n\t" \ + "mov.l r11, @-r15\n\t" \ + "mov.l r12, @-r15\n\t" \ + "mov.l r13, @-r15\n\t" \ + "mov.l r14, @-r15\n\t" \ "mov.l r15, @r1 ! save SP\n\t" \ "mov.l @r6, r15 ! change to new stack\n\t" \ - "mova 1f, %0\n\t" \ - "mov.l %0, @r2 ! save PC\n\t" \ - "mov.l 2f, %0\n\t" \ + "mova 1f, %0\n\t" \ + "mov.l %0, @r2 ! save PC\n\t" \ + "mov.l 2f, %0\n\t" \ "jmp @%0 ! call __switch_to\n\t" \ " lds r7, pr ! with return to new PC\n\t" \ ".balign 4\n" \ @@ -54,8 +54,8 @@ "lds.l @r15+, pr\n\t" \ "ldc.l @r15+, gbr\n\t" \ : "=z" (__last) \ - : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ - "r" (__ts5), "r" (__ts6), "r" (__ts7) \ + : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ + "r" (__ts5), "r" (__ts6), "r" (__ts7) \ : "r3", "t"); \ last = __last; \ } while (0) @@ -145,7 +145,7 @@ do { \ "mov.l 1f, %0\n\t" \ "or %1, %0\n\t" \ "jmp @%0\n\t" \ - " nop\n\t" \ + " nop\n\t" \ ".balign 4\n" \ "1: .long 2f\n" \ "2:" \ diff --git a/include/bcm5221.h b/include/bcm5221.h index 6fb94aaef5..61424b1276 100644 --- a/include/bcm5221.h +++ b/include/bcm5221.h @@ -23,7 +23,7 @@ * MA 02111-1307 USA */ -#define BCM5221_BMCR 0 /* Basic Mode Control Register */ +#define BCM5221_BMCR 0 /* Basic Mode Control Register */ #define BCM5221_BMSR 1 /* Basic Mode Status Register */ #define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */ #define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */ diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h index 9cc8f9fa38..46bf8db1a7 100644 --- a/include/bedbug/ppc.h +++ b/include/bedbug/ppc.h @@ -321,7 +321,7 @@ struct opcode { array are the operand identifiers */ int (*hfunc)(struct ppc_ctx *); - /* Address of a function to handle the given + /* Address of a function to handle the given mnemonic */ char * name; /* The symbolic name of this opcode */ diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h index 66cf8eaea3..e675de3209 100644 --- a/include/bedbug/tables.h +++ b/include/bedbug/tables.h @@ -12,43 +12,43 @@ */ struct operand operands[] = { - /*Field Name Bits Shift Hint Position */ - /*----- ------ ----- ----- ---- ------------ */ - { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ + /*Field Name Bits Shift Hint Position */ + /*----- ------ ----- ----- ---- ------------ */ + { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */ - { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ - { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ - { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ - { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ - { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ - { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ + { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ + { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ + { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ + { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ + { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ + { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */ - { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ - { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ - { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ - { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ + { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ + { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ + { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ + { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */ - { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ - { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ - { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ - { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ - { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ - { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ - { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ - { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ - { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ - { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ - { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ + { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ + { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ + { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ + { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ + { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ + { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ + { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ + { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ + { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ + { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ + { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */ - { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ - { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ + { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ + { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */ - { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ - { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ - { O_L, "O_L", 1, 21, 0 }, /* 10 */ + { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ + { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ + { O_L, "O_L", 1, 21, 0 }, /* 10 */ { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */ { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */ - { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ + { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ }; const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); @@ -64,418 +64,418 @@ const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); bit locations */ struct opcode opcodes[] = { - { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, - 0, "twi", 0 }, - { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "mulli", 0 }, - { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "subfic", 0 }, - { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, - 0, "cmpli", 0 }, - { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, - 0, "cmpi", 0 }, - { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addic", 0 }, - { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addic.", 0 }, - { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addi", H_RA0_IS_0 }, - { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, - { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - handle_bc, "bc", H_RELATIVE }, - { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bcl", H_RELATIVE }, - { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bca", 0 }, - { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bcla", 0 }, - { SC_OPCODE(17), SC_MASK, {0}, - 0, "sc", 0 }, - { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "b", H_RELATIVE }, - { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "bl", H_RELATIVE }, - { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "ba", 0 }, - { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "bla", 0 }, - { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, - 0, "mcrf", 0 }, + { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, + 0, "twi", 0 }, + { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "mulli", 0 }, + { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "subfic", 0 }, + { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, + 0, "cmpli", 0 }, + { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, + 0, "cmpi", 0 }, + { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic", 0 }, + { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addic.", 0 }, + { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addi", H_RA0_IS_0 }, + { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, + 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, + { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + handle_bc, "bc", H_RELATIVE }, + { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcl", H_RELATIVE }, + { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bca", 0 }, + { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, + 0, "bcla", 0 }, + { SC_OPCODE(17), SC_MASK, {0}, + 0, "sc", 0 }, + { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "b", H_RELATIVE }, + { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bl", H_RELATIVE }, + { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "ba", 0 }, + { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, + 0, "bla", 0 }, + { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, + 0, "mcrf", 0 }, { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bclr", 0 }, + 0, "bclr", 0 }, { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bclrl", 0 }, + 0, "bclrl", 0 }, { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crnor", 0 }, + 0, "crnor", 0 }, { XL_OPCODE(19,50,0), XL_MASK, {0}, - 0, "rfi", 0 }, + 0, "rfi", 0 }, { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crandc", 0 }, + 0, "crandc", 0 }, { XL_OPCODE(19,150,0), XL_MASK, {0}, - 0, "isync", 0 }, + 0, "isync", 0 }, { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crxor", 0 }, + 0, "crxor", 0 }, { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crnand", 0 }, + 0, "crnand", 0 }, { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crand", 0 }, + 0, "crand", 0 }, { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "creqv", 0 }, + 0, "creqv", 0 }, { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crorc", 0 }, + 0, "crorc", 0 }, { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "cror", 0 }, + 0, "cror", 0 }, { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bcctr", 0 }, + 0, "bcctr", 0 }, { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bcctrl", 0 }, - { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwimi", 0 }, - { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwimi.", 0 }, - { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwinm", 0 }, - { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwinm.", 0 }, - { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, - 0, "rlwnm", 0 }, - { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, - 0, "rlwnm.", 0 }, - { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "ori", 0 }, - { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "oris", H_IMM_HIGH }, - { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "xori", 0 }, - { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "xoris", H_IMM_HIGH }, - { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "andi.", 0 }, - { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "andis.", H_IMM_HIGH }, - { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, - 0, "cmp", 0 }, - { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, - 0, "tw", 0 }, + 0, "bcctrl", 0 }, + { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi", 0 }, + { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwimi.", 0 }, + { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm", 0 }, + { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, + 0, "rlwinm.", 0 }, + { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm", 0 }, + { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, + 0, "rlwnm.", 0 }, + { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "ori", 0 }, + { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "oris", H_IMM_HIGH }, + { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xori", 0 }, + { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "xoris", H_IMM_HIGH }, + { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andi.", 0 }, + { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, + 0, "andis.", H_IMM_HIGH }, + { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmp", 0 }, + { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, + 0, "tw", 0 }, { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfc", 0 }, + 0, "subfc", 0 }, { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfc.", 0 }, + 0, "subfc.", 0 }, { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addc", 0 }, + 0, "addc", 0 }, { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addc.", 0 }, + 0, "addc.", 0 }, { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhwu", 0 }, + 0, "mulhwu", 0 }, { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhwu.", 0 }, - { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, - 0, "mfcr", 0 }, - { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwarx", H_RA0_IS_0 }, - { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwzx", H_RA0_IS_0 }, - { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "slw", 0 }, - { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "slw.", 0 }, - { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, - 0, "cntlzw", 0 }, - { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "cntlzw.", 0 }, - { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "and", 0 }, - { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "and.", 0 }, - { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, - 0, "cmpl", 0 }, + 0, "mulhwu.", 0 }, + { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, + 0, "mfcr", 0 }, + { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwarx", H_RA0_IS_0 }, + { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzx", H_RA0_IS_0 }, + { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw", 0 }, + { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "slw.", 0 }, + { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, + 0, "cntlzw", 0 }, + { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, + 0, "cntlzw.", 0 }, + { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and", 0 }, + { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "and.", 0 }, + { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, + 0, "cmpl", 0 }, { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subf", 0 }, + 0, "subf", 0 }, { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subf.", 0 }, - { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbst", H_RA0_IS_0 }, - { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwzux", 0 }, - { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "andc", 0 }, - { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "andc.", 0 }, + 0, "subf.", 0 }, + { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbst", H_RA0_IS_0 }, + { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lwzux", 0 }, + { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc", 0 }, + { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, + 0, "andc.", 0 }, { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhw", 0 }, + 0, "mulhw", 0 }, { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhw.", 0 }, - { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, - 0, "mfmsr", 0 }, - { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbf", H_RA0_IS_0 }, - { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lbzx", H_RA0_IS_0 }, + 0, "mulhw.", 0 }, + { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, + 0, "mfmsr", 0 }, + { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, + 0, "dcbf", H_RA0_IS_0 }, + { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, + 0, "lbzx", H_RA0_IS_0 }, { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "neg", 0 }, + 0, "neg", 0 }, { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "neg.", 0 }, + 0, "neg.", 0 }, { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lbzux", 0 }, + 0, "lbzux", 0 }, { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nor", 0 }, + 0, "nor", 0 }, { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nor.", 0 }, + 0, "nor.", 0 }, { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfe", 0 }, + 0, "subfe", 0 }, { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfe.", 0 }, + 0, "subfe.", 0 }, { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "adde", 0 }, + 0, "adde", 0 }, { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "adde.", 0 }, + 0, "adde.", 0 }, { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0}, - 0, "mtcrf", 0 }, + 0, "mtcrf", 0 }, { X_OPCODE(31,146,0), X_MASK, {O_rS, 0}, - 0, "mtmsr", 0 }, + 0, "mtmsr", 0 }, { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwcx.", 0 }, + 0, "stwcx.", 0 }, { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwx", 0 }, + 0, "stwx", 0 }, { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwux", 0 }, + 0, "stwux", 0 }, { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfze", 0 }, + 0, "subfze", 0 }, { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfze.", 0 }, + 0, "subfze.", 0 }, { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addze", 0 }, + 0, "addze", 0 }, { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addze.", 0 }, + 0, "addze.", 0 }, { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0}, - 0, "mtsr", 0 }, + 0, "mtsr", 0 }, { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stbx", H_RA0_IS_0 }, + 0, "stbx", H_RA0_IS_0 }, { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfme", 0 }, + 0, "subfme", 0 }, { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfme.", 0 }, + 0, "subfme.", 0 }, { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addme", 0 }, + 0, "addme", 0 }, { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addme.", 0 }, + 0, "addme.", 0 }, { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullw", 0 }, + 0, "mullw", 0 }, { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullw.", 0 }, + 0, "mullw.", 0 }, { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0}, - 0, "mtsrin", 0 }, + 0, "mtsrin", 0 }, { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbtst", H_RA0_IS_0 }, + 0, "dcbtst", H_RA0_IS_0 }, { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stbux", 0 }, + 0, "stbux", 0 }, { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "add", 0 }, + 0, "add", 0 }, { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "add.", 0 }, + 0, "add.", 0 }, { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbt", H_RA0_IS_0 }, + 0, "dcbt", H_RA0_IS_0 }, { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhzx", H_RA0_IS_0 }, + 0, "lhzx", H_RA0_IS_0 }, { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "eqv", 0 }, + 0, "eqv", 0 }, { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "eqv.", 0 }, + 0, "eqv.", 0 }, { X_OPCODE(31,306,0), X_MASK, {O_rB, 0}, - 0, "tlbie", 0 }, + 0, "tlbie", 0 }, { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "eciwx", H_RA0_IS_0 }, + 0, "eciwx", H_RA0_IS_0 }, { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhzux", 0 }, + 0, "lhzux", 0 }, { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "xor", 0 }, + 0, "xor", 0 }, { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "xor.", 0 }, + 0, "xor.", 0 }, { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0}, - 0, "mfspr", 0 }, + 0, "mfspr", 0 }, { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhax", H_RA0_IS_0 }, + 0, "lhax", H_RA0_IS_0 }, { X_OPCODE(31,370,0), X_MASK, {0}, - 0, "tlbia", 0 }, + 0, "tlbia", 0 }, { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0}, - 0, "mftb", 0 }, + 0, "mftb", 0 }, { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhaux", 0 }, + 0, "lhaux", 0 }, { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthx", H_RA0_IS_0 }, + 0, "sthx", H_RA0_IS_0 }, { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "orc", 0 }, + 0, "orc", 0 }, { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "orc.", 0 }, + 0, "orc.", 0 }, { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "ecowx", H_RA0_IS_0 }, + 0, "ecowx", H_RA0_IS_0 }, { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthux", 0 }, + 0, "sthux", 0 }, { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "or", 0 }, + 0, "or", 0 }, { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "or.", 0 }, + 0, "or.", 0 }, { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwu", 0 }, + 0, "divwu", 0 }, { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwu.", 0 }, + 0, "divwu.", 0 }, { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0}, - 0, "mtspr", 0 }, + 0, "mtspr", 0 }, { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbi", H_RA0_IS_0 }, + 0, "dcbi", H_RA0_IS_0 }, { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nand", 0 }, + 0, "nand", 0 }, { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0}, - 0, "nand.", 0 }, + 0, "nand.", 0 }, { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divw", 0 }, + 0, "divw", 0 }, { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divw.", 0 }, + 0, "divw.", 0 }, { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0}, - 0, "mcrxr", 0 }, + 0, "mcrxr", 0 }, { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfco", 0 }, + 0, "subfco", 0 }, { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfco.", 0 }, + 0, "subfco.", 0 }, { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addco", 0 }, + 0, "addco", 0 }, { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addco.", 0 }, + 0, "addco.", 0 }, { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lswx", H_RA0_IS_0 }, + 0, "lswx", H_RA0_IS_0 }, { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwbrx", H_RA0_IS_0 }, + 0, "lwbrx", H_RA0_IS_0 }, { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "srw", 0 }, + 0, "srw", 0 }, { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "srw.", 0 }, + 0, "srw.", 0 }, { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfo", 0 }, + 0, "subfo", 0 }, { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfo.", 0 }, + 0, "subfo.", 0 }, { X_OPCODE(31,566,0), X_MASK, {0}, - 0, "tlbsync", 0 }, + 0, "tlbsync", 0 }, { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0}, - 0, "mfsr", 0 }, + 0, "mfsr", 0 }, { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0}, - 0, "lswi", H_RA0_IS_0 }, + 0, "lswi", H_RA0_IS_0 }, { X_OPCODE(31,598,0), X_MASK, {0}, - 0, "sync", 0 }, + 0, "sync", 0 }, { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "nego", 0 }, + 0, "nego", 0 }, { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "nego.", 0 }, + 0, "nego.", 0 }, { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfeo", 0 }, + 0, "subfeo", 0 }, { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfeo.", 0 }, + 0, "subfeo.", 0 }, { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addeo", 0 }, + 0, "addeo", 0 }, { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addeo.", 0 }, + 0, "addeo.", 0 }, { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0}, - 0, "mfsrin", 0 }, + 0, "mfsrin", 0 }, { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stswx", H_RA0_IS_0 }, + 0, "stswx", H_RA0_IS_0 }, { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwbrx", H_RA0_IS_0 }, + 0, "stwbrx", H_RA0_IS_0 }, { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfzeo", 0 }, + 0, "subfzeo", 0 }, { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfzeo.", 0 }, + 0, "subfzeo.", 0 }, { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addzeo", 0 }, + 0, "addzeo", 0 }, { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addzeo.", 0 }, + 0, "addzeo.", 0 }, { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0}, - 0, "stswi", H_RA0_IS_0 }, + 0, "stswi", H_RA0_IS_0 }, { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfmeo", 0 }, + 0, "subfmeo", 0 }, { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfmeo.", 0 }, + 0, "subfmeo.", 0 }, { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addmeo", 0 }, + 0, "addmeo", 0 }, { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addmeo.", 0 }, + 0, "addmeo.", 0 }, { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullwo", 0 }, + 0, "mullwo", 0 }, { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullwo.", 0 }, + 0, "mullwo.", 0 }, { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addo", 0 }, + 0, "addo", 0 }, { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addo.", 0 }, + 0, "addo.", 0 }, { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhbrx", H_RA0_IS_0 }, + 0, "lhbrx", H_RA0_IS_0 }, { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "sraw", 0 }, + 0, "sraw", 0 }, { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "sraw.", 0 }, + 0, "sraw.", 0 }, { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, - 0, "srawi", 0 }, + 0, "srawi", 0 }, { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, - 0, "srawi.", 0 }, + 0, "srawi.", 0 }, { X_OPCODE(31,854,0), X_MASK, {0}, - 0, "eieio", 0 }, + 0, "eieio", 0 }, { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthbrx", H_RA0_IS_0 }, + 0, "sthbrx", H_RA0_IS_0 }, { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsh", 0 }, + 0, "extsh", 0 }, { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsh.", 0 }, + 0, "extsh.", 0 }, { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsb", 0 }, + 0, "extsb", 0 }, { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsb.", 0 }, + 0, "extsb.", 0 }, { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwuo", 0 }, + 0, "divwuo", 0 }, { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwuo.", 0 }, + 0, "divwuo.", 0 }, { X_OPCODE(31,978,0), X_MASK, {O_rB, 0}, - 0, "tlbld", 0 }, + 0, "tlbld", 0 }, { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0}, - 0, "icbi", H_RA0_IS_0 }, + 0, "icbi", H_RA0_IS_0 }, { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwo", 0 }, + 0, "divwo", 0 }, { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwo.", 0 }, + 0, "divwo.", 0 }, { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0}, - 0, "tlbli", 0 }, + 0, "tlbli", 0 }, { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbz", H_RA0_IS_0 }, - { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lwz", H_RA0_IS_0 }, - { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lwzu", 0 }, - { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lbz", H_RA0_IS_0 }, - { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lbzu", 0 }, - { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stw", H_RA0_IS_0 }, - { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stwu", 0 }, - { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stb", H_RA0_IS_0 }, - { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stbu", 0 }, - { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhz", H_RA0_IS_0 }, - { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhzu", 0 }, - { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lha", H_RA0_IS_0 }, - { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhau", 0 }, - { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "sth", H_RA0_IS_0 }, - { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "sthu", 0 }, - { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lmw", H_RA0_IS_0 }, - { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stmw", H_RA0_IS_0 }, + 0, "dcbz", H_RA0_IS_0 }, + { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwz", H_RA0_IS_0 }, + { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lwzu", 0 }, + { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbz", H_RA0_IS_0 }, + { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lbzu", 0 }, + { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stw", H_RA0_IS_0 }, + { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stwu", 0 }, + { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stb", H_RA0_IS_0 }, + { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stbu", 0 }, + { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhz", H_RA0_IS_0 }, + { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhzu", 0 }, + { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lha", H_RA0_IS_0 }, + { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lhau", 0 }, + { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sth", H_RA0_IS_0 }, + { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "sthu", 0 }, + { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, + 0, "lmw", H_RA0_IS_0 }, + { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, + 0, "stmw", H_RA0_IS_0 }, }; const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]); diff --git a/include/clps7111.h b/include/clps7111.h index d122d847ad..baf600773b 100644 --- a/include/clps7111.h +++ b/include/clps7111.h @@ -231,7 +231,7 @@ #define IO_RTCDR IO_WORD(RTCDR) #define IO_RTCMR IO_WORD(RTCMR) #define IO_PMPCON IO_WORD(PMPCON) -#define IO_CODR IO_BYTE(CODR) +#define IO_CODR IO_BYTE(CODR) #define IO_UARTDR IO_WORD(UARTDR) #define IO_UBRLCR IO_WORD(UBRLCR) #define IO_SYNCIO IO_WORD(SYNCIO) diff --git a/include/command.h b/include/command.h index 0597c10daf..c3ef51d8c4 100644 --- a/include/command.h +++ b/include/command.h @@ -74,7 +74,7 @@ extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int * * void function (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); */ -typedef void command_t (cmd_tbl_t *, int, int, char *[]); +typedef void command_t (cmd_tbl_t *, int, int, char *[]); #endif /* __ASSEMBLY__ */ diff --git a/include/commproc.h b/include/commproc.h index 32a3e1c82a..0a4e817fa6 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -786,19 +786,19 @@ typedef struct scc_enet { #undef SCC_ENET #define FEC_ENET -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ +#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ +#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ +#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ +#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ +#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ +#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ +#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ +#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ +#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ +#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ +#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ +#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ +#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ #define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ #endif /* CONFIG_GEN860T */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d1b5ffb897..c2bb094e2a 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -16,13 +16,13 @@ #define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */ #define CONFIG_CMD_ASKENV /* ask for env variable */ #define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ -#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */ #define CONFIG_CMD_BMP /* BMP support */ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_BSP /* Board Specific functions */ #define CONFIG_CMD_CACHE /* icache, dcache */ -#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_DATE /* support for RTC, date/time...*/ #define CONFIG_CMD_DHCP /* DHCP Support */ @@ -71,7 +71,7 @@ #define CONFIG_CMD_SAVES /* save S record dump */ #define CONFIG_CMD_SCSI /* SCSI Support */ #define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ -#define CONFIG_CMD_SETEXPR /* setexpr support */ +#define CONFIG_CMD_SETEXPR /* setexpr support */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ #define CONFIG_CMD_SNTP /* SNTP support */ #define CONFIG_CMD_SPI /* SPI utility */ diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index f61cfc9368..b556706c73 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -17,7 +17,7 @@ */ #define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ -#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BDI /* bdinfo */ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_ECHO /* echo arguments */ diff --git a/include/configs/A3000.h b/include/configs/A3000.h index 0a9a1ff90c..dba1bf727d 100644 --- a/include/configs/A3000.h +++ b/include/configs/A3000.h @@ -87,7 +87,7 @@ *----------------------------------------------------------------------- */ #define CONFIG_HARD_I2C 1 /* To enable I2C support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -95,9 +95,9 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ #define CONFIG_NET_MULTI /* Multi ethernet cards support */ @@ -120,11 +120,11 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ +#define CFG_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the @@ -170,7 +170,7 @@ * Definitions for initial stack pointer and data area */ -/* #define CFG_MONITOR_BASE TEXT_BASE */ +/* #define CFG_MONITOR_BASE TEXT_BASE */ /*#define CFG_GBL_DATA_SIZE 256*/ #define CFG_GBL_DATA_SIZE 128 #define CFG_INIT_RAM_ADDR 0x40000000 @@ -192,7 +192,7 @@ */ #define CFG_ROMNAL 7 #define CFG_ROMFAL 11 -#define CFG_DBUS_SIZE 0x3 +#define CFG_DBUS_SIZE 0x3 /* Bit-field values for MCCR2. */ @@ -218,7 +218,7 @@ #define CFG_EXTROM 1 #define CFG_REGDIMM 0 -#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ +#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index c45c39554e..01ee72b8bc 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -81,9 +81,9 @@ * appropriately -- this is very important if you plan to move your * memory to another place as configured at this time !!!). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ diff --git a/include/configs/ADNPESC1_base_32.h b/include/configs/ADNPESC1_base_32.h index 55210ebd3a..c8428b4e79 100644 --- a/include/configs/ADNPESC1_base_32.h +++ b/include/configs/ADNPESC1_base_32.h @@ -370,10 +370,10 @@ #define CFG_NIOS_CPU_IDE_NUMS 2 /* number of IDE contr. */ #define CFG_NIOS_CPU_IDE0 0x00001000 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ +#define CFG_NIOS_CPU_IDE0_IRQ 36 /* IRQ */ #define CFG_NIOS_CPU_IDE1 0x00001020 /* IDE1 addr */ -#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ +#define CFG_NIOS_CPU_IDE1_IRQ 37 /* IRQ */ /* memory accessibility */ #undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h index 6f64038073..035ebc6935 100644 --- a/include/configs/AMX860.h +++ b/include/configs/AMX860.h @@ -115,7 +115,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 8ad33f11d5..02f0c76e07 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -36,7 +36,7 @@ */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_APCG405 1 /* ...on a APC405 board */ +#define CONFIG_APCG405 1 /* ...on a APC405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_BOARD_EARLY_INIT_R 1 diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 50f09b03f3..06023819f9 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -208,7 +208,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/ #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ -#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ +#define CFG_ENV_SIZE 0x04000 /* Size of Environment */ #define CFG_ENV_ADDR_REDUND 0xFFFA0000 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 0d644da7ae..f05c1d592b 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -55,7 +55,7 @@ #define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ #undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -84,7 +84,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ +#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */ #define CONFIG_ENABLE_36BIT_PHYS 1 #undef CFG_DRAM_TEST #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ @@ -276,7 +276,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #if defined(CONFIG_PCI) diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 8a76c264ca..7389c38b9e 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -149,7 +149,7 @@ /* Environment is in flash */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CONFIG_ENV_OVERWRITE @@ -191,16 +191,16 @@ #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) /* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CFG_PISCR (PISCR_PS | PISCR_PITF) /* PLPRCR - PLL, Low-Power, and Reset Control Register */ -/* #define CFG_PLPRCR PLPRCR_TEXPS */ +/* #define CFG_PLPRCR PLPRCR_TEXPS */ /* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 +#define SCCR_MASK SCCR_EBDF11 #define CFG_SCCR SCCR_RTSEL -#define CFG_DER 0 +#define CFG_DER 0 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/B2.h b/include/configs/B2.h index f1411db66c..d6ab1adeb9 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -37,7 +37,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_B2 1 /* on an B2 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 9f06957d2f..6194c5c6e2 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -137,7 +137,7 @@ #define CFG_LOAD_ADDR 0x00100000 /* default load address */ /* Ethernet hardware configuration done using port pins */ -#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ +#define CFG_PA_ETH_RESET 0x0200 /* PA 6 */ #define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */ #define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */ #define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 9763e64295..10cebc99c2 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -115,9 +115,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /*----------------------------------------------------------------------- diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 2356858d8c..604779a691 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -130,16 +130,16 @@ /* * Miscellaneous configurable options */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_LOAD_ADDR 0x100000/* where to load what we get from TFTP */ +#define CFG_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */ #define CFG_TFTP_LOADADDR CFG_LOAD_ADDR -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CFG_DRAM_TEST 1 /*----------------------------------------------------------------------- @@ -218,7 +218,7 @@ #else #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) diff --git a/include/configs/CU824.h b/include/configs/CU824.h index 8b50087f40..f36d8dacc0 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -305,7 +305,7 @@ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_TULIP #define CONFIG_TULIP_USE_IO diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index eb78080208..fb06689074 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -76,9 +76,9 @@ * a memory resource (so you must make sure TEXT_BASE is chosen * appropriately). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index bd360717a7..7a9ef79adc 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -84,9 +84,9 @@ * a memory resource (so you must make sure TEXT_BASE is chosen * appropriately). * - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ diff --git a/include/configs/DK1S10_mtx_ldk_20.h b/include/configs/DK1S10_mtx_ldk_20.h index 4eb96290bb..0115699416 100644 --- a/include/configs/DK1S10_mtx_ldk_20.h +++ b/include/configs/DK1S10_mtx_ldk_20.h @@ -147,7 +147,7 @@ /* IDE i/f */ #define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ #define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ -#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ +#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ /* memory accessibility */ #undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ diff --git a/include/configs/DU440.h b/include/configs/DU440.h index d54da9717b..0f5f85c22a 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -375,11 +375,11 @@ int du440_phy_addr(int devnum); #define CFG_FLASH CFG_FLASH_BASE #define CFG_CPLD_BASE 0xC0000000 -#define CFG_CPLD_RANGE 0x00000010 +#define CFG_CPLD_RANGE 0x00000010 #define CFG_DUMEM_BASE 0xC0100000 -#define CFG_DUMEM_RANGE 0x00100000 +#define CFG_DUMEM_RANGE 0x00100000 #define CFG_DUIO_BASE 0xC0200000 -#define CFG_DUIO_RANGE 0x00010000 +#define CFG_DUIO_RANGE 0x00010000 #define CFG_NAND0_CS 2 /* NAND chip connected to CSx */ #define CFG_NAND1_CS 3 /* NAND chip connected to CSx */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index 5ba7585bce..417099e037 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -95,7 +95,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL @@ -157,7 +157,7 @@ */ #define CFG_INIT_RAM_ADDR 0x20000000 #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -219,13 +219,13 @@ #define CFG_CS0_BASE CFG_FLASH_BASE #define CFG_CS0_SIZE 2*1024*1024 #define CFG_CS0_WIDTH 16 -#define CFG_CS0_RO 0 +#define CFG_CS0_RO 0 #define CFG_CS0_WS 6 #define CFG_CS3_BASE 0xE0000000 #define CFG_CS3_SIZE 1*1024*1024 #define CFG_CS3_WIDTH 16 -#define CFG_CS3_RO 0 +#define CFG_CS3_RO 0 #define CFG_CS3_WS 6 /*----------------------------------------------------------------------- @@ -250,7 +250,7 @@ #define CFG_PEHLPAR 0xC0 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ #define CFG_DDRUA 0x05 -#define CFG_PJPAR 0xFF; +#define CFG_PJPAR 0xFF; /*----------------------------------------------------------------------- * CCM configuration diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h index c2ab18a79e..7824b900ad 100644 --- a/include/configs/EP88x.h +++ b/include/configs/EP88x.h @@ -144,7 +144,7 @@ /* Environment is in flash */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_OR0_PRELIM 0xFC000160 @@ -192,13 +192,13 @@ #define CFG_TBSCR (TBSCR_TBF | TBSCR_TBE) /* PISCR - Periodic Interrupt Status and Control */ -#define CFG_PISCR PISCR_PS +#define CFG_PISCR PISCR_PS /* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 +#define SCCR_MASK SCCR_EBDF11 #define CFG_SCCR SCCR_RTSEL -#define CFG_DER 0 +#define CFG_DER 0 /*----------------------------------------------------------------------- * Cache Configuration diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index dc15b0c349..bfdcf6a554 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -330,7 +330,7 @@ * BR0/1 and OR0/1 (FLASH) */ -#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ +#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 8MB */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h index ed439b1922..525051fb57 100644 --- a/include/configs/ETX094.h +++ b/include/configs/ETX094.h @@ -51,7 +51,7 @@ #define CONFIG_BOARD_TYPES 1 /* support board types */ #define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */ -#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ +#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */ #define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */ #define CONFIG_ETHADDR 08:00:06:00:00:00 diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index 1c44a0c6d7..c9d8c271ba 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -42,7 +42,7 @@ #define CONFIG_EVB64260 1 /* this is an EVB64260 board */ #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ +#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ #undef CONFIG_ECC /* enable ECC support */ /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ @@ -91,7 +91,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp && " \ + "bootp && " \ "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:" \ "$netmask:$hostname:eth0:none; && " \ @@ -412,10 +412,10 @@ #define CFG_L2 #ifdef CONFIG_750CX -#define L2_INIT 0 +#define L2_INIT 0 #else -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #endif #define L2_ENABLE (L2_INIT | L2CR_L2E) diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index 251227c7ff..99d1cf255c 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 86cbe5872a..6f3e6a75b8 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -93,10 +93,10 @@ #define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */ #define CONFIG_BOOTARGS "" #define CONFIG_BOOTCOMMAND \ -"bootp ;" \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ +"bootp ;" \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \ "bootm" #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index c8b5a6d8a5..037b115c13 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -39,9 +39,9 @@ * Identify the board */ #if !defined(CONFIG_SC) -#define CONFIG_IDENT_STRING " B2" +#define CONFIG_IDENT_STRING " B2" #else -#define CONFIG_IDENT_STRING " SC" +#define CONFIG_IDENT_STRING " SC" #endif /* @@ -50,26 +50,26 @@ * generated by the DS1337 - and the DS1337 clock can be turned off. */ #if !defined(CONFIG_SC) -#define CONFIG_8xx_GCLK_FREQ 66600000 +#define CONFIG_8xx_GCLK_FREQ 66600000 #else -#define CONFIG_8xx_GCLK_FREQ 48000000 +#define CONFIG_8xx_GCLK_FREQ 48000000 #endif /* * The RS-232 console port is on SMC1 */ #define CONFIG_8xx_CONS_SMC1 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 /* * Set allowable console baud rates */ -#define CFG_BAUDRATE_TABLE { 9600, \ - 19200, \ - 38400, \ - 57600, \ - 115200, \ - } +#define CFG_BAUDRATE_TABLE { 9600, \ + 19200, \ + 38400, \ + 57600, \ + 115200, \ + } /* * Print console information @@ -148,7 +148,7 @@ #define CFG_DISCOVER_PHY #define CONFIG_MII #define CONFIG_MII_INIT 1 -#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_ADDR 0 /* * Set default IP stuff just to get bootstrap entries into the @@ -172,7 +172,7 @@ * Enable I2C and select the hardware/software driver */ #define CONFIG_HARD_I2C 1 /* CPM based I2C */ -#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ +#undef CONFIG_SOFT_I2C /* Bit-banged I2C */ #ifdef CONFIG_HARD_I2C #define CFG_I2C_SPEED 100000 /* clock speed in Hz */ @@ -181,7 +181,7 @@ #ifdef CONFIG_SOFT_I2C #define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ +#define PB_SDA 0x00000010 /* PB 27 */ #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) @@ -388,7 +388,7 @@ */ #define CFG_INIT_RAM_ADDR CFG_IMMR #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ +#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -480,18 +480,18 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ - SYPCR_SWE | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ + SYPCR_SWE | \ SYPCR_SWRI | \ SYPCR_SWP \ ) #else #define CFG_SYPCR ( SYPCR_SWTC | \ - SYPCR_BMT | \ - SYPCR_BME | \ - SYPCR_SWF | \ + SYPCR_BMT | \ + SYPCR_BME | \ + SYPCR_SWF | \ SYPCR_SWP \ ) #endif @@ -557,18 +557,18 @@ #define SCCR_MASK SCCR_EBDF11 #if !defined(CONFIG_SC) -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ SCCR_DFNL000 | \ SCCR_DFNH000 \ ) #else -#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ - SCCR_COM00 | /* full strength CLKOUT */ \ - SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ - SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ +#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ + SCCR_COM00 | /* full strength CLKOUT */ \ + SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ + SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ SCCR_DFNL000 | \ SCCR_DFNH000 | \ SCCR_RTDIV | \ @@ -614,7 +614,7 @@ #define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ BR_MS_GPCM | \ BR_PS_8 | \ - BR_V \ + BR_V \ ) /* @@ -626,9 +626,9 @@ ) #define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ - BR_MS_UPMA | \ - BR_PS_32 | \ - BR_V \ + BR_MS_UPMA | \ + BR_PS_32 | \ + BR_V \ ) /* @@ -646,9 +646,9 @@ * MAMR settings for SDRAM */ #define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ - MAMR_PTAE | \ + MAMR_PTAE | \ MAMR_AMA_TYPE_1 | \ - MAMR_DSA_1_CYCL | \ + MAMR_DSA_1_CYCL | \ MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | \ MAMR_WLFA_1X | \ @@ -660,7 +660,7 @@ * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, * no burst. */ -#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_CSNT_SAM | \ OR_ACS_DIV2 | \ OR_BI | \ @@ -685,20 +685,20 @@ */ #define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ OR_SCY_15_CLK | \ - OR_BI \ + OR_BI \ ) #define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ BR_PS_32 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* * CS4* configuration for FPGA SelectMap configuration interface. * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge * of GCLK1_50 */ -#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ +#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ OR_G5LS | \ OR_BI \ ) @@ -706,7 +706,7 @@ #define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ BR_PS_8 | \ BR_MS_UPMB | \ - BR_V \ + BR_V \ ) /* @@ -728,7 +728,7 @@ #define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ BR_PS_16 | \ BR_MS_GPCM | \ - BR_V \ + BR_V \ ) /* @@ -760,5 +760,3 @@ #endif #endif /* __CONFIG_GEN860T_H */ - -/* vim: set ts=4 tw=78 ai shiftwidth=4: */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h index 3a660edae2..f6d6ae0ce5 100644 --- a/include/configs/GENIETV.h +++ b/include/configs/GENIETV.h @@ -80,10 +80,10 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 9600 -#define MPC8XX_FACT 12 /* Multiply by 12 */ -#define MPC8XX_XIN 5000000 /* 4 MHz clock */ +#define MPC8XX_FACT 12 /* Multiply by 12 */ +#define MPC8XX_XIN 5000000 /* 4 MHz clock */ -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) +#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) #define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20) #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */ @@ -95,9 +95,9 @@ #define CONFIG_BOOTARGS "" #define CONFIG_BOOTCOMMAND \ "bootp; tftp; " \ -"setenv bootargs console=tty0 console=ttyS0 " \ -"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ -"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ +"setenv bootargs console=tty0 console=ttyS0 " \ +"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \ +"ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;" \ "bootm " #else #define CONFIG_BOOTDELAY 0 /* autoboot disabled */ @@ -197,7 +197,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ +#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/ /* values according to the manual */ @@ -291,15 +291,15 @@ #define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */ -#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask (512Kb) */ /* FLASH timing */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ OR_SCY_15_CLK | OR_TRLX ) /*#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) */ -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 0xfff80ff4 */ #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) /* 0x02800401 */ /* diff --git a/include/configs/GTH.h b/include/configs/GTH.h index 79f5714e6f..00e09f703c 100644 --- a/include/configs/GTH.h +++ b/include/configs/GTH.h @@ -135,7 +135,7 @@ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ /* Default location to load data from net */ -#define CFG_LOAD_ADDR 0x100000 +#define CFG_LOAD_ADDR 0x100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -196,7 +196,7 @@ #define CFG_ENV_IS_IN_FLASH 1 #undef CFG_ENV_IS_IN_EEPROM #define CFG_ENV_OFFSET 0x000E0000 -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 18e5b3c288..8ea1ac37d1 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -41,7 +41,7 @@ #define CONFIG_405EP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_HH405 1 /* ...on a HH405 board */ +#define CONFIG_HH405 1 /* ...on a HH405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h index 7f3f16dbb1..87827ead1c 100644 --- a/include/configs/IAD210.h +++ b/include/configs/IAD210.h @@ -70,15 +70,15 @@ #undef CONFIG_BOOTARGS /* #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm" + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootm" */ #define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/nfs" \ - "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ + "setenv bootargs root=/dev/nfs" \ + "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -159,7 +159,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index 9c88d7c417..f693956d42 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -72,9 +72,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -164,7 +164,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h index bb2c96ac94..7d564a0957 100644 --- a/include/configs/IPHASE4539.h +++ b/include/configs/IPHASE4539.h @@ -274,7 +274,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ - HID0_IFEM|HID0_ABE) + HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 965b515f0e..760f7cca6e 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -186,7 +186,7 @@ /* Environment is in flash, there is little space left in Serial EEPROM */ #define CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ #define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index 1142f2afac..0ffdfac07c 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -205,7 +205,7 @@ # if defined (CONFIG_IVML24_16M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) # elif defined (CONFIG_IVML24_32M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWP) @@ -265,7 +265,7 @@ /* 0x01800014 */ #define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD101 | \ @@ -458,8 +458,8 @@ #if defined (CONFIG_IVML24_16M) /* 8 column SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) #elif defined (CONFIG_IVML24_32M) /* 128 MBit SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index bd19dad1ff..ea3ffe0a10 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -200,7 +200,7 @@ #if defined(CONFIG_WATCHDOG) # if defined (CONFIG_IVMS8_16M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) # elif defined (CONFIG_IVMS8_32M) # define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWP) @@ -259,7 +259,7 @@ /* 0x01800014 */ #define CFG_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000 | SCCR_DFLCD101 | \ @@ -440,8 +440,8 @@ #if defined (CONFIG_IVMS8_16M) /* 8 column SDRAM */ # define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ - MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ - MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) + MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ + MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) #elif defined (CONFIG_IVMS8_32M) /* 128 MBit SDRAM */ #define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 38a022611a..f85cff7abf 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -172,9 +172,9 @@ * IPB Bus clocking configuration. */ #if defined(CONFIG_LITE5200B) -#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #else -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif #endif /* CONFIG_MPC5200 */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 3ee2b395a4..8af1c52abf 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -84,7 +84,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index e1cc720e77..a6fac4cbf6 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -95,7 +95,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 2b8734b4c6..7edd322bdd 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -97,7 +97,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 826778c35a..df46ee4438 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -82,7 +82,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL @@ -215,13 +215,13 @@ #define CFG_CS0_BASE CFG_FLASH_BASE #define CFG_CS0_SIZE 2*1024*1024 #define CFG_CS0_WIDTH 16 -#define CFG_CS0_RO 0 +#define CFG_CS0_RO 0 #define CFG_CS0_WS 6 /* #define CFG_CS3_BASE 0xE0000000 #define CFG_CS3_SIZE 1*1024*1024 #define CFG_CS3_WIDTH 16 -#define CFG_CS3_RO 0 +#define CFG_CS3_RO 0 #define CFG_CS3_WS 6 */ /*----------------------------------------------------------------------- @@ -246,6 +246,6 @@ #define CFG_PEHLPAR 0xC0 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ #define CFG_DDRUA 0x05 -#define CFG_PJPAR 0xFF; +#define CFG_PJPAR 0xFF; #endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 42692d69fa..b30d99c92e 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -77,7 +77,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 3b9da17e40..a710c6d9f8 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -77,7 +77,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index fea7551cf1..a19c342270 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -83,7 +83,7 @@ # define CFG_FEC1_PINMUX 0 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 454d0a28dc..b73e2e006d 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -83,7 +83,7 @@ # define CFG_FEC1_PINMUX 0 # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 9ddf82b3e0..d683b87ae0 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -123,7 +123,7 @@ * (to get SDRAM settings) ***************************************************************/ /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 -#define SDRAM_EEPROM_READ_ADDRESS 0xA1 +#define SDRAM_EEPROM_READ_ADDRESS 0xA1 */ /************************************************************** * Environment definitions @@ -132,7 +132,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ @@ -260,7 +260,7 @@ /*----------------------------------------------------------------------- * Logbuffer Configuration */ -#undef CONFIG_LOGBUFFER /* supported but not enabled */ +#undef CONFIG_LOGBUFFER /* supported but not enabled */ /*----------------------------------------------------------------------- * Bootcountlimit Configuration */ @@ -271,8 +271,8 @@ */ #if 0 /* enable this if POST is desired (is supported but not enabled) */ #define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_RTC | \ + CFG_POST_CPU | \ + CFG_POST_RTC | \ CFG_POST_I2C) #endif @@ -292,7 +292,7 @@ #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 -#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 +#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 /*----------------------------------------------------------------------- @@ -301,7 +301,7 @@ #define CFG_TEMP_STACK_OCM 1 #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) @@ -362,7 +362,7 @@ #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h index 9370c24c50..021729b582 100644 --- a/include/configs/MOUSSE.h +++ b/include/configs/MOUSSE.h @@ -265,18 +265,18 @@ #else #define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT) #endif -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT1L CFG_IBAT1L /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */ -#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) +#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT) #define CFG_DBAT2U CFG_IBAT2U #define CFG_DBAT2L CFG_IBAT2L /* PCI Memory region 2: PCI Devices in 0xFD space */ -#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) +#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) #define CFG_DBAT3U CFG_IBAT3U #define CFG_DBAT3L CFG_IBAT3L @@ -299,7 +299,7 @@ #if 0 #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ +#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */ #define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */ #else #define CFG_ENV_IS_IN_NVRAM 1 @@ -339,7 +339,7 @@ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_TULIP diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index f9fa535ff7..610151f586 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -217,7 +217,7 @@ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ -#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ +#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ /* drivers/mtd/nand/nand.c */ #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ @@ -549,28 +549,28 @@ #define MK_STR(x) XMK_STR(x) #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ "ethprime=TSEC1\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "console=ttyS0\0" \ "setbootargs=setenv bootargs " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ - "run setbootargs;" \ - "run setipargs;" \ + "run setbootargs;" \ + "run setipargs;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index ddefa5e919..1276a124c9 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -574,7 +574,7 @@ #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ -#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index cf552c2487..119e7ac7c6 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -39,7 +39,7 @@ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ #undef CONFIG_PCI -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ #define PCI_66M #ifdef PCI_66M @@ -414,7 +414,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xFIXME #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index be8850a7e7..c72de03c01 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -149,8 +149,8 @@ * DDR Setup */ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_83XX_DDR_USES_CS0 #define CFG_MEMTEST_START 0x1000 /* memtest region */ #define CFG_MEMTEST_END 0x2000 @@ -187,7 +187,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_FLASH_QUIET_TEST #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ @@ -671,21 +671,21 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=" MK_STR(CONFIG_CONSOLE) "\0" \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "console=" MK_STR(CONFIG_CONSOLE) "\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f6af6733..7b7d6f50c0 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -535,11 +535,11 @@ "ubootfile=u-boot.bin\0"\ "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),-(rootfs)\0"\ "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ - "$mtdparts panic=1\0"\ + "$mtdparts panic=1\0"\ "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ - "$gatewayip:$netmask:$hostname:$netdev:off "\ - "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ + "$gatewayip:$netmask:$hostname:$netdev:off "\ + "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "\ "rootfstype=jffs2 rw\0"\ "tftp_get_uboot=tftp 100000 $ubootfile\0"\ @@ -555,7 +555,7 @@ "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"\ "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"\ "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ - "cp.b 100000 ff800000 $filesize\0"\ + "cp.b 100000 ff800000 $filesize\0"\ "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "\ "nand_write_kernel\0"\ "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 85934d718d..5719759808 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -46,7 +46,7 @@ #endif #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -98,7 +98,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -147,7 +147,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -268,16 +268,16 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -337,7 +337,7 @@ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -345,7 +345,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -357,7 +357,7 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 77eea73787..b13c81c2e2 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -30,14 +30,14 @@ #ifndef __CONFIG_H #define __CONFIG_H /* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ #define CONFIG_MPC8540 1 /* MPC8540 specific */ #define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */ -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#undef CONFIG_PCI /* pci ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -63,7 +63,7 @@ #endif /* below can be toggled for performance analysis. otherwise use default */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #undef CONFIG_BTB /* toggle branch predition */ #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -81,8 +81,8 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -113,7 +113,7 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/ #define CFG_FLASH_CFI 1 -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -150,16 +150,16 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -168,7 +168,7 @@ #define CFG_NS16550_SERIAL #define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -203,17 +203,17 @@ #define CONFIG_NET_MULTI #undef CONFIG_EEPRO100 #define CONFIG_TULIP -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 -#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ +#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ #endif #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #define CFG_PCI_SUBSYS_DEVICEID 0x0008 #elif defined(CONFIG_TSEC_ENET) -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_HAS_ETH0 @@ -262,7 +262,7 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ +#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -318,7 +318,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* * Internal Definitions diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 3f3f741ade..5b3ea05e63 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -38,7 +38,7 @@ #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void); #define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -362,7 +362,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* * Internal Definitions diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 500b57cece..e8383455c4 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -38,7 +38,7 @@ #define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -69,7 +69,7 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -83,7 +83,7 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -155,7 +155,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -284,16 +284,16 @@ extern unsigned long get_clock_freq(void); #define CFG_OR3_PRELIM 0xfff00ff7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 @@ -361,7 +361,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_MPC85XX_PCI2 #undef CONFIG_EEPRO100 @@ -376,7 +376,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* * Internal Definitions diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index e30302c5d4..9c95cc6567 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -42,7 +42,7 @@ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -93,7 +93,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -142,7 +142,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -263,23 +263,23 @@ #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} @@ -325,7 +325,7 @@ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -333,7 +333,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -345,7 +345,7 @@ #ifdef CONFIG_TSEC_ENET #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #ifndef CONFIG_MII @@ -367,9 +367,9 @@ #endif /* CONFIG_TSEC_ENET */ -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ +#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ #if (CONFIG_ETHER_INDEX == 2) @@ -387,7 +387,7 @@ #elif (CONFIG_ETHER_INDEX == 3) /* need more definitions here for FE3 */ #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ +#endif /* CONFIG_ETHER_INDEX */ #ifndef CONFIG_MII #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 7bb20e58ca..a7c69d293c 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -38,7 +38,7 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -68,7 +68,7 @@ extern unsigned long get_clock_freq(void); /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ @@ -88,7 +88,7 @@ extern unsigned long get_clock_freq(void); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -166,7 +166,7 @@ extern unsigned long get_clock_freq(void); #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -184,10 +184,10 @@ extern unsigned long get_clock_freq(void); #define CFG_BR2_PRELIM 0xf0001861 #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * LSDMR masks @@ -267,16 +267,16 @@ extern unsigned long get_clock_freq(void); #define CFG_OR5_PRELIM 0xffff69f7 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -350,7 +350,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_eTSEC_MDIO_BUS #ifdef CONFIG_eTSEC_MDIO_BUS -#define CONFIG_MIIM_ADDRESS 0xE0024520 +#define CONFIG_MIIM_ADDRESS 0xE0024520 #endif #define CONFIG_UEC_ETH1 /* GETH1 */ @@ -379,7 +379,7 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -395,7 +395,7 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #if defined(CONFIG_TSEC_ENET) @@ -480,7 +480,7 @@ extern unsigned long get_clock_freq(void); * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ /* * Internal Definitions diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 585411c4e2..15ff0eacf2 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -330,7 +330,7 @@ #define CONFIG_USB_KEYBOARD 1 #define CFG_DEVICE_DEREGISTER #define CFG_USB_EVENT_POLL 1 -#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #define CFG_OHCI_SWAP_REG_ACCESS 1 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a8d0077ca3..9acc3da54a 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -36,11 +36,11 @@ #define CONFIG_MPC86xx 1 /* MPC86xx */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #ifdef RUN_DIAG -#define CFG_DIAG_ADDR 0xff800000 +#define CFG_DIAG_ADDR 0xff800000 #endif #define CFG_RESET_ADDRESS 0xfff00100 @@ -51,7 +51,7 @@ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ @@ -61,14 +61,14 @@ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_NUM_DDR_CONTROLLERS 2 -/* #define CONFIG_DDR_INTERLEAVE 1 */ +/* #define CONFIG_DDR_INTERLEAVE 1 */ #define CACHE_LINE_INTERLEAVING 0x20000000 #define PAGE_INTERLEAVING 0x21000000 #define BANK_INTERLEAVING 0x22000000 #define SUPER_BANK_INTERLEAVING 0x23000000 -#define CONFIG_ALTIVEC 1 +#define CONFIG_ALTIVEC 1 /* * L2CR setup -- make sure this is right for your board! @@ -81,7 +81,7 @@ #ifndef __ASSEMBLY__ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ @@ -94,7 +94,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -127,18 +127,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ #define CFG_DDR_CS0_BNDS 0x0000000F - #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ + #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ #define CFG_DDR_EXT_REFRESH 0x00000000 - #define CFG_DDR_TIMING_0 0x00260802 + #define CFG_DDR_TIMING_0 0x00260802 #define CFG_DDR_TIMING_1 0x39357322 #define CFG_DDR_TIMING_2 0x14904cc8 #define CFG_DDR_MODE_1 0x00480432 #define CFG_DDR_MODE_2 0x00000000 #define CFG_DDR_INTERVAL 0x06090100 - #define CFG_DDR_DATA_INIT 0xdeadbeef - #define CFG_DDR_CLK_CTRL 0x03800000 - #define CFG_DDR_OCD_CTRL 0x00000000 - #define CFG_DDR_OCD_STATUS 0x00000000 + #define CFG_DDR_DATA_INIT 0xdeadbeef + #define CFG_DDR_CLK_CTRL 0x03800000 + #define CFG_DDR_OCD_CTRL 0x00000000 + #define CFG_DDR_OCD_STATUS 0x00000000 #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ #define CFG_DDR_CONTROL2 0x04400000 @@ -170,7 +170,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * * Note that, on switching the boot location, fef00000 becomes fff00000. */ -#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ +#define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ #define CFG_FLASH_BASE2 0xff800000 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} @@ -189,7 +189,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ +#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ @@ -204,7 +204,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ +#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ @@ -212,7 +212,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI @@ -221,7 +221,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CFG_RAMBOOT #endif #if defined(CFG_RAMBOOT) @@ -238,32 +238,32 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #else #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ #endif -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) /* Use the HUSH parser */ #define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif @@ -286,7 +286,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3100 /* @@ -308,13 +308,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ /* PCI view of System Memory */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x80000000 +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 /* For RTL8139 */ #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 +#define _IO_BASE 0x00000000 #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE @@ -325,12 +325,12 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI) -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #undef CFG_SCSI_SCAN_BUS_REVERSE #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_RTL8139 @@ -340,19 +340,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /************************************************************ * USB support ************************************************************/ -#define CONFIG_PCI_OHCI 1 +#define CONFIG_PCI_OHCI 1 #define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_KEYBOARD 1 #define CFG_DEVICE_DEREGISTER -#define CFG_USB_EVENT_POLL 1 -#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" -#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#define CFG_USB_EVENT_POLL 1 +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 #define CFG_OHCI_SWAP_REG_ACCESS 1 #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif /*PCIE video card used*/ @@ -384,7 +384,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SATA_ULI5288 #define CFG_SCSI_MAX_SCSI_ID 4 #define CFG_SCSI_MAX_LUN 1 -#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) +#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE #endif @@ -395,19 +395,19 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "eTSEC4" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 @@ -427,76 +427,76 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_TSEC_ENET */ /* - * BAT0 2G Cacheable, non-guarded - * 0x0000_0000 2G DDR + * BAT0 2G Cacheable, non-guarded + * 0x0000_0000 2G DDR */ -#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CFG_IBAT0U CFG_DBAT0U +#define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) +#define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) +#define CFG_IBAT0U CFG_DBAT0U /* - * BAT1 1G Cache-inhibited, guarded - * 0x8000_0000 512M PCI-Express 1 Memory - * 0xa000_0000 512M PCI-Express 2 Memory + * BAT1 1G Cache-inhibited, guarded + * 0x8000_0000 512M PCI-Express 1 Memory + * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ +#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT1U CFG_DBAT1U +#define CFG_IBAT1U CFG_DBAT1U /* - * BAT2 512M Cache-inhibited, guarded - * 0xc000_0000 512M RapidIO Memory + * BAT2 512M Cache-inhibited, guarded + * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ +#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) #define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT2U CFG_DBAT2U +#define CFG_IBAT2U CFG_DBAT2U /* - * BAT3 4M Cache-inhibited, guarded - * 0xf800_0000 4M CCSR + * BAT3 4M Cache-inhibited, guarded + * 0xf800_0000 4M CCSR */ -#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ +#define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) -#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT3U CFG_DBAT3U +#define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT3U CFG_DBAT3U /* - * BAT4 32M Cache-inhibited, guarded - * 0xe200_0000 16M PCI-Express 1 I/O - * 0xe300_0000 16M PCI-Express 2 I/0 + * BAT4 32M Cache-inhibited, guarded + * 0xe200_0000 16M PCI-Express 1 I/O + * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ +#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) #define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CFG_IBAT4U CFG_DBAT4U +#define CFG_IBAT4U CFG_DBAT4U /* - * BAT5 128K Cacheable, non-guarded - * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) + * BAT5 128K Cacheable, non-guarded + * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) */ -#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CFG_IBAT5L CFG_DBAT5L -#define CFG_IBAT5U CFG_DBAT5U +#define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_IBAT5L CFG_DBAT5L +#define CFG_IBAT5U CFG_DBAT5U /* - * BAT6 32M Cache-inhibited, guarded - * 0xfe00_0000 32M FLASH + * BAT6 32M Cache-inhibited, guarded + * 0xfe00_0000 32M FLASH */ -#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ +#define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CFG_IBAT6U CFG_DBAT6U +#define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT6U CFG_DBAT6U #define CFG_DBAT7L 0x00000000 #define CFG_DBAT7U 0x00000000 @@ -557,7 +557,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ @@ -598,7 +598,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:E0:0C:00:00:01 +#define CONFIG_ETHADDR 00:E0:0C:00:00:01 #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD @@ -624,45 +624,45 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADADDR 1000000 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=c00000\0" \ - "fdtfile=mpc8641_hpcn.dtb\0" \ - "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ - "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ - "maxcpus=2" - - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=mpc8641_hpcn.dtb\0" \ + "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ + "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ + "maxcpus=2" + + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index 831cc5ecd3..e0e8554811 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -22,7 +22,7 @@ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ /* CPU type - pick one of these */ -#define CONFIG_MPC866T 1 +#define CONFIG_MPC866T 1 #undef CONFIG_MPC866P #undef CONFIG_MPC859T #undef CONFIG_MPC859DSL diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h index f8cf01e5d3..4319e6c04c 100644 --- a/include/configs/MUSENKI.h +++ b/include/configs/MUSENKI.h @@ -86,7 +86,7 @@ * PCI stuff *----------------------------------------------------------------------- */ -#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP #define CONFIG_NET_MULTI /* Multi ethernet cards support */ diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index d799f54f6a..d08d79520c 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -28,16 +28,16 @@ #define MV_VERSION "v0.2.0" /* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */ -#define ERR_NONE 0 -#define ERR_ENV 1 -#define ERR_BOOTM_BADMAGIC 2 -#define ERR_BOOTM_BADCRC 3 -#define ERR_BOOTM_GUNZIP 4 +#define ERR_NONE 0 +#define ERR_ENV 1 +#define ERR_BOOTM_BADMAGIC 2 +#define ERR_BOOTM_BADCRC 3 +#define ERR_BOOTM_GUNZIP 4 #define ERR_BOOTP_TIMEOUT 5 -#define ERR_DHCP 6 -#define ERR_TFTP 7 -#define ERR_NOLAN 8 -#define ERR_LANDRV 9 +#define ERR_DHCP 6 +#define ERR_TFTP 7 +#define ERR_NOLAN 8 +#define ERR_LANDRV 9 #define CONFIG_BOARD_TYPES 1 #define MVBLUE_BOARD_BOX 1 @@ -45,10 +45,10 @@ #if 0 #define ERR_LED(code) do { if (code) \ - *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ - else \ - *(volatile char *)(0xff000003) = ( 1 ); \ - } while(0) + *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \ + else \ + *(volatile char *)(0xff000003) = ( 1 ); \ +} while(0) #else #define ERR_LED(code) #endif @@ -116,19 +116,19 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) -#define CFG_MAXARGS 16 /* Max number of command args */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* Max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00100000 /* Default load address */ -#define CONFIG_BOOTCOMMAND "run nfsboot" +#define CONFIG_BOOTCOMMAND "run nfsboot" #define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2" -#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" +#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm" #define CONFIG_EXTRA_ENV_SETTINGS \ "console_nr=0\0" \ @@ -156,11 +156,11 @@ #define CONFIG_PCI_SCAN_SHOW #define CONFIG_NET_MULTI -#define CONFIG_NET_RETRY_COUNT 5 +#define CONFIG_NET_RETRY_COUNT 5 #define CONFIG_TULIP #define CONFIG_TULIP_FIX_DAVICOM 1 -#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 +#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0 #define CONFIG_HW_WATCHDOG @@ -224,7 +224,7 @@ */ #define CONFIG_SYS_CLK_FREQ 33000000 -#define CFG_HZ 10000 +#define CFG_HZ 10000 /* Bit-field values for MCCR1. */ #define CFG_ROMNAL 7 diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index 75efd1e0e4..87458e3624 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -43,16 +43,19 @@ #undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#define CONFIG_BAUDRATE 115200 /* console baudrate */ #define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */ -#define CONFIG_PREBOOT "echo;echo To mount root over NFS use \"run bootnet\";echo To mount root from FLASH use \"run bootflash\";echo" +#define CONFIG_PREBOOT "echo;" \ + "echo To mount root over NFS use \"run bootnet\";" \ + "echo To mount root from FLASH use \"run bootflash\";" \ + "echo" #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw" -#define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ - "bootm" +#define CONFIG_BOOTCOMMAND \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ @@ -61,7 +64,7 @@ #undef CONFIG_STATUS_LED /* Status LED disabled/enabled */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ /* @@ -100,9 +103,9 @@ #undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#undef CFG_HUSH_PARSER /* Hush parse for U-Boot ?? */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " #endif #if defined(CONFIG_CMD_KGDB) @@ -193,7 +196,7 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif @@ -267,8 +270,8 @@ #define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */ -#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ #define CFG_IDE_MAXBUS 0 /* max. no. of IDE buses */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 5346545d32..0b094827d7 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -76,12 +76,12 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" -#define CONFIG_WATCHDOG /* watchdog enabled */ +#define CONFIG_WATCHDOG /* watchdog enabled */ #undef CONFIG_STATUS_LED /* Status LED disabled */ @@ -175,7 +175,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index e3c6fd333b..27e7ab9bce 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -66,7 +66,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ + "tftpboot; " \ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" @@ -97,7 +97,7 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 @@ -105,7 +105,7 @@ #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 @@ -292,27 +292,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -322,15 +322,15 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 66666666 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -514,7 +514,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 20404a394f..56c76d3258 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -64,7 +64,7 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ + "tftpboot; " \ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" @@ -93,7 +93,7 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY /* do not discover phys */ #define CONFIG_MII 1 @@ -102,15 +102,15 @@ #if defined(CONFIG_NETTA_ISDN) #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ #define CONFIG_FEC1_PHY_NORXERR 1 #undef CONFIG_ETHER_ON_FEC2 #else #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 -#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ +#define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ #define CONFIG_FEC2_PHY_NORXERR 1 #endif @@ -296,27 +296,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -326,19 +326,19 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 80000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -633,7 +633,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index cf66e04702..b8c48482ac 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -66,9 +66,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_AUTOSCRIPT @@ -98,7 +98,7 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ +#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 @@ -106,7 +106,7 @@ #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 -#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ +#define CONFIG_FEC1_PHY 8 /* phy address of FEC */ #define CONFIG_FEC1_PHY_NORXERR 1 #define CONFIG_ETHER_ON_FEC2 1 @@ -293,27 +293,27 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 50000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 25000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 40000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 75000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 10MHz #endif @@ -323,15 +323,15 @@ #if MPC8XX_HZ == 120000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 100000000 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #elif MPC8XX_HZ == 66666666 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ - PLPRCR_TEXPS) + PLPRCR_TEXPS) #else #error unsupported CPU freq for XIN = 50MHz #endif @@ -515,7 +515,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index af5339ee00..1293fb0e2b 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -63,9 +63,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ @@ -411,7 +411,7 @@ #define ADDR_COLUMN 1 #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 3929a846bc..11e5c63ed3 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -295,8 +295,8 @@ #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) #define CFG_PCMCIA_IO_ADDR (0xEC000000) #define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ -#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ +#define PCMCIA_MEM_WIN_NO 8 /* override default 4 in pcmcia.h */ +#define PCMCIA_SOCKETS_NO 2 /* we have two sockets */ #undef NSCU_OE_INV /* PCMCIA_GCRX_CXOE was inverted on early boards */ /*----------------------------------------------------------------------- diff --git a/include/configs/NX823.h b/include/configs/NX823.h index da1c173a43..2a4bd4724c 100644 --- a/include/configs/NX823.h +++ b/include/configs/NX823.h @@ -127,7 +127,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ +#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index e85e1b91fc..5a2d157705 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -42,7 +42,7 @@ #define CONFIG_P3G4 1 /* this is a P3G4 board */ #define CFG_GT_6426x GT_64260 /* with a 64260 system controller */ -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ #undef CONFIG_ECC /* enable ECC support */ /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ @@ -417,8 +417,8 @@ #define CFG_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) #define L2_ENABLE (L2_INIT | L2CR_L2E) diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 0de7591da6..4b37eca7ce 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -32,7 +32,7 @@ */ #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_PATI 1 /* ...On a PATI board */ +#define CONFIG_PATI 1 /* ...On a PATI board */ /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 #undef CONFIG_5xx_CONS_SCI2 @@ -74,11 +74,11 @@ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_BOOTCOMMAND "" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "" /* autoboot command */ #define CONFIG_BOOTARGS "" /* */ -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ /*#define CONFIG_STATUS_LED 1 */ /* Enable status led */ @@ -123,30 +123,30 @@ /* * Internal Memory Mapped (This is not the IMMR content) */ -#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ +#define CFG_IMMR 0x01C00000 /* Physical start adress of internal memory map */ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial global data */ #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ +#define CFG_INIT_SP_ADDR (CFG_IMMR + 0x03fa000) /* Physical start adress of inital stack */ /* * Start addresses for the final memory configuration * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ #define CFG_FLASH_BASE 0xffC00000 /* External flash */ #define PCI_BASE 0x03000000 /* PCI Base (CS2) */ #define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */ #define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */ #define CFG_MONITOR_BASE 0xFFF00000 -/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ +/* CFG_FLASH_BASE */ /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ @@ -167,9 +167,9 @@ */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_MAX_FLASH_SECT 128 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_EEPROM @@ -180,8 +180,8 @@ #undef CFG_ENV_IS_IN_FLASH #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ -#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00002000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET ((0 - CFG_FLASH_BASE) - CFG_ENV_SIZE) /* Environment starts at this adress */ #endif @@ -233,7 +233,7 @@ *----------------------------------------------------------------------- * Data show cycle */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -241,7 +241,7 @@ * Set all bits to 40 Mhz * */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) @@ -251,12 +251,12 @@ *----------------------------------------------------------------------- * */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 24b25d9850..abb9bfc25c 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -54,10 +54,10 @@ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION - * -Monitor at top. - * -The heap is placed below the monitor. - * -Global data is placed below the heap. - * -The stack is placed below global data (&grows down). + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ #define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */ #define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ @@ -87,7 +87,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ #define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) /*------------------------------------------------------------------------ * CONSOLE @@ -155,8 +155,8 @@ #define CFG_LONGHELP /* Provide extended help*/ #define CFG_PROMPT "==> " /* Command prompt */ #define CFG_CBSIZE 256 /* Console I/O buf size */ -#define CFG_MAXARGS 16 /* Max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ #define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index b83520d7c1..5890012b4e 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -123,7 +123,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ @@ -252,7 +252,7 @@ #define CFG_TEMP_STACK_OCM 1 #define CFG_OCM_DATA_ADDR 0xF0000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) diff --git a/include/configs/PM520.h b/include/configs/PM520.h index ad480a6c9e..6eb6444925 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -159,7 +159,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* * I2C configuration diff --git a/include/configs/PM826.h b/include/configs/PM826.h index cf7314ddb4..36e9aa56ea 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -47,9 +47,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 38a26dc8aa..9355aafa61 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -43,7 +43,7 @@ #define CONFIG_PM856 1 /* PM856 board specific */ #define CONFIG_PCI -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_ECC /* only for ECC DDR module */ @@ -92,7 +92,7 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -141,7 +141,7 @@ #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT @@ -167,16 +167,16 @@ #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ @@ -236,7 +236,7 @@ #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -244,7 +244,7 @@ #if !defined(CONFIG_PCI_PNP) #define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -256,7 +256,7 @@ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 72acf5ae8d..da7d8b82b1 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -73,7 +73,7 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 +#define CONFIG_IPADDR 10.0.0.200 #define CONFIG_ROOTPATH /opt/eldk/ppc_82xx #define CONFIG_NETMASK 255.255.255.0 #undef CONFIG_BOOTARGS @@ -81,7 +81,7 @@ /* Boot Linux with NFS root filesystem */ #define CONFIG_BOOTCOMMAND \ "setenv verify y;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 100000; bootm" @@ -90,7 +90,7 @@ /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ #define CONFIG_BOOTCOMMAND \ "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ + "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ "root=/dev/ram rw " \ "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ "loadp 200000; bootm" @@ -128,7 +128,7 @@ /* * Networking stuff */ -#define CONFIG_NET_MULTI /* Multi ethernet cards support */ +#define CONFIG_NET_MULTI /* Multi ethernet cards support */ #define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ #define CONFIG_PCNET_79C973 @@ -153,9 +153,9 @@ /*#define CFG_GBL_DATA_SIZE 256*/ #define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_NO_FLASH 1 /* There is no FLASH memory */ diff --git a/include/configs/QS823.h b/include/configs/QS823.h index 3dd84e8c57..cef9f42dfd 100644 --- a/include/configs/QS823.h +++ b/include/configs/QS823.h @@ -492,12 +492,12 @@ /* For boards with 16M of SDRAM */ #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* For boards with 32M of SDRAM */ #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) diff --git a/include/configs/QS850.h b/include/configs/QS850.h index 7dd6eca9ca..ba5827a22d 100644 --- a/include/configs/QS850.h +++ b/include/configs/QS850.h @@ -492,12 +492,12 @@ /* For boards with 16M of SDRAM */ #define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ -#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ +#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* For boards with 32M of SDRAM */ #define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */ -#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ +#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index f4aecfc0bd..a653cca96f 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -62,9 +62,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #undef CONFIG_SCC1_ENET diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index e3c75617ec..9222d21554 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -65,9 +65,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index 793b1db889..706e2aadc7 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -78,9 +78,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "tftpboot; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "tftpboot; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -467,7 +467,7 @@ #define BCSR3 0xFA400003 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 3c5e6b8913..671094b69d 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -51,9 +51,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -156,7 +156,7 @@ #define CFG_DIRECT_FLASH_TFTP #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CONFIG_ENV_OVERWRITE @@ -361,7 +361,7 @@ #define BCSR3 0xFA400003 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ -#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ +#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 32e2285454..6a71801935 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -119,7 +119,7 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ # define CFG_I2C_SPEED 50000 /* 50 kHz is supposed to work */ # define CFG_I2C_SLAVE 0xFE diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 428c0c2b59..01ebc8f6e0 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -250,13 +250,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 946b3c2d8a..ff64378f20 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -48,7 +48,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ -#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ +#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */ #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h index bc5389fe8a..febfc39263 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -67,9 +67,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /* enable I2C and select the hardware/software driver */ @@ -165,7 +165,7 @@ * - Enable Full Duplex in FSMR */ # define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) -# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) +# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) # define CFG_CPMFCR_RAMTYPE 0 # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h index 4d9d41b927..31853c8de3 100644 --- a/include/configs/SL8245.h +++ b/include/configs/SL8245.h @@ -90,10 +90,10 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ -#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM +#define CFG_FLASH_BASE CFG_FLASH_BASE0_PRELIM #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM } #define CFG_RESET_ADDRESS 0xFFF00100 diff --git a/include/configs/SM850.h b/include/configs/SM850.h index 41a54f0f5a..465db4735f 100644 --- a/include/configs/SM850.h +++ b/include/configs/SM850.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index 8f2a5ece2c..3aee45c3c7 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -204,7 +204,7 @@ #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 @@ -250,7 +250,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 1affcfdebb..71fa36baae 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -176,7 +176,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * I2C configuration diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index 8237ba1af3..151c407c84 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -201,10 +201,10 @@ * defines we need to get FEC running */ #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ -#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ -#define FEC_ENET 1 /* eth.c needs it that way... */ +#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */ +#define FEC_ENET 1 /* eth.c needs it that way... */ #define CFG_DISCOVER_PHY 1 -#define CONFIG_MII 1 +#define CONFIG_MII 1 #define CONFIG_MII_INIT 1 #define CONFIG_PHY_ADDR 31 @@ -287,7 +287,7 @@ *----------------------------------------------------------------------- * set up SYPCR: * 16 SWTC 0xffff Software watchdog timer count - * 8 BMT 0xff Bus monitor timing + * 8 BMT 0xff Bus monitor timing * 1 BME 1 Bus monitor enable * 3 0 000 * 1 SWF 1 Software watchdog freeze @@ -297,7 +297,7 @@ */ #if defined (CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF) #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 02a16ac0a6..a86939e097 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -176,7 +176,7 @@ extern int tqm834x_num_flash_banks; #define CFG_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -231,7 +231,7 @@ extern int tqm834x_num_flash_banks; /* * TSEC */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MII #define CFG_TSEC1_OFFSET 0x24000 diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 2507d77776..31f10dd87c 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -178,7 +178,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ #endif /* diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index df6894f324..ad8db613ec 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -44,7 +44,7 @@ #define USE_920T_MMU 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 @@ -84,8 +84,8 @@ * address 0x50 with 16bit addressing ***********************************************************/ #define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CFG_I2C_SPEED 100000 /* I2C speed */ -#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ +#define CFG_I2C_SPEED 100000 /* I2C speed */ +#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */ #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_I2C_EEPROM_ADDR_LEN 2 @@ -111,7 +111,7 @@ */ #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ #define CS8900_BASE 0x20000300 -#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ #define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ @@ -145,7 +145,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 10.0.0.110 @@ -262,7 +262,7 @@ #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 -#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 #define NAND_MAX_CHIPS 1 diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index 14057847b8..db05d82bfc 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -369,7 +369,7 @@ /* * MEMORY MAP * ---------- - * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) + * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored) * CS1 - SDRAM 32MB/64Bit base=0x00000000 * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000 * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000 diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 7017fff5de..bb6b6b9d26 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -154,10 +154,10 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Set up values for external bus controller diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index bfb3156f6f..3050cafa1d 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -161,10 +161,10 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Set up values for external bus controller diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index 7c1a5b9e88..b04be766f5 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -200,13 +200,13 @@ HRCW_MODCK_H0111 \ ) /* 0x16848207 */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 81e7c1e4db..f55d91f28c 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -161,7 +161,7 @@ #define CFG_FLASH_USE_BUFFER_WRITE #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h index 703d3124e6..427b5482f5 100644 --- a/include/configs/adsvix.h +++ b/include/configs/adsvix.h @@ -359,7 +359,7 @@ /* Flash environment locations */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */ -#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ +#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */ #define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ #endif /* __CONFIG_H */ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 294cd26978..89732968ad 100755..100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -174,7 +174,7 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ #define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index 73a88854b3..98a83db296 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -41,9 +41,9 @@ * (easy to change) */ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ -#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ +#define CONFIG_ARMADILLO 1 /* on an Armadillo Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -88,7 +88,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" +#define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" #define CONFIG_BOOTCOMMAND "bootm 40000 180000" diff --git a/include/configs/atc.h b/include/configs/atc.h index 4ef50c23f0..285b4e4da0 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -111,7 +111,7 @@ #define CONFIG_BOOTCOMMAND \ "bootp;" \ "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ + "nfsroot=${serverip}:${rootpath} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\ "bootm" @@ -182,9 +182,9 @@ #define CONFIG_RTC_DS12887 -#define RTC_BASE_ADDR 0xF5000000 -#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 -#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 +#define RTC_BASE_ADDR 0xF5000000 +#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800 +#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808 #define CONFIG_MISC_INIT_R diff --git a/include/configs/barco.h b/include/configs/barco.h index 0bb446f784..4f57067db1 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -96,8 +96,8 @@ #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTCOMMAND "boot_default" +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTCOMMAND "boot_default" /* * Miscellaneous configurable options @@ -135,9 +135,9 @@ #define CONFIG_LOGBUFFER #ifdef CONFIG_LOGBUFFER -#define CFG_STDOUT_ADDR 0x1FFC000 +#define CFG_STDOUT_ADDR 0x1FFC000 #else -#define CFG_STDOUT_ADDR 0x2B9000 +#define CFG_STDOUT_ADDR 0x2B9000 #endif #define CFG_RESET_ADDRESS 0xFFF00100 @@ -158,9 +158,9 @@ #define CFG_GBL_DATA_SIZE 128 -#define CFG_INIT_RAM_ADDR 0x40000000 -#define CFG_INIT_RAM_END 0x1000 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR 0x40000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 66a0af683d..d70aa1087c 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -25,7 +25,7 @@ #define CONFIG_SMC91111_BASE 0x20300300 /* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 +#define SHARED_RESOURCES 1 /* Is I2C bit-banged? */ #define CONFIG_SOFT_I2C 1 @@ -112,7 +112,7 @@ #endif #define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ #define ENV_IS_EMBEDDED #define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ @@ -123,7 +123,7 @@ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS 1 /* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 +#define CFG_JFFS2_FIRST_SECTOR 11 /* * following timeouts shall be used once the @@ -148,7 +148,7 @@ #define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1) #define CONFIG_LOADADDR 0x01000000 -#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_LOAD_ADDR CONFIG_LOADADDR #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 39c7359d3e..a881d53289 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -103,11 +103,11 @@ #define CFG_LONGHELP 1 #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ -#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTCOMMAND "run ramboot" #if defined(CONFIG_POST_TEST) /* POST support */ -#define CONFIG_POST ( CFG_POST_MEMORY | \ +#define CONFIG_POST ( CFG_POST_MEMORY | \ CFG_POST_UART | \ CFG_POST_FLASH | \ CFG_POST_ETHER | \ @@ -208,7 +208,7 @@ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024) +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024) #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -281,10 +281,10 @@ #define NAND_MAX_CHIPS 1 #define BFIN_NAND_READY PF3 -#define NAND_WAIT_READY(nand) \ - do { \ - int timeout = 0; \ - while(!(*pPORTFIO & PF3)) \ +#define NAND_WAIT_READY(nand) \ + do { \ + int timeout = 0; \ + while(!(*pPORTFIO & PF3)) \ if (timeout++ > 100000) \ break; \ } while (0) diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 641548dafd..e99e97924c 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -148,28 +148,27 @@ #if (CONFIG_DRIVER_SMC91111) #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ - "$(rootpath) console=ttyBF0,57600\0" \ + "$(rootpath) console=ttyBF0,57600\0" \ "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ - "ramboot=tftpboot $(loadaddr) linux; " \ + "ramboot=tftpboot $(loadaddr) linux; " \ "run ramargs; run addip; bootelf\0" \ - "nfsboot=tftpboot $(loadaddr) linux; " \ + "nfsboot=tftpboot $(loadaddr) linux; " \ "run nfsargs; run addip; bootelf\0" \ - "update=tftpboot $(loadaddr) u-boot.bin; " \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ "protect off 0x20000000 0x2003FFFF; " \ "erase 0x20000000 0x2003FFFF; " \ - "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ "" #else #define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "flashboot=bootm 0x20100000\0" \ "" #endif - /* * BOOTP options */ @@ -178,7 +177,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -193,7 +191,6 @@ #define CONFIG_CMD_DHCP #endif - /* * Console settings */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index cbd74a0d8d..75dd4e7e67 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -302,7 +302,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index a5621b8056..6f0d4b0f80 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 440972c4dc..0f7bb619ce 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -31,7 +31,7 @@ #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ -#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ +#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ @@ -115,7 +115,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ +#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* * Flash configuration, expect one 16 Megabyte Bank at most diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index e06735da63..c801f037e1 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -39,7 +39,7 @@ #define BOARD_LATE_INIT 1 #define CONFIG_BAUDRATE 38400 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* * Size of malloc() pool @@ -104,7 +104,7 @@ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #endif #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -137,21 +137,21 @@ /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ -#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ -#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ -#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ - -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ +#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ +#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ +#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ #define CFG_DRAM_BASE 0xa0000000 #define CFG_DRAM_SIZE 0x04000000 @@ -210,7 +210,7 @@ * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index a869364c60..ac2b7a1e71 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -24,7 +24,7 @@ * File: cmi_mpc5xx.h * * Discription: Config header file for cmi - * board using an MPC5xx CPU + * board using an MPC5xx CPU * */ @@ -36,7 +36,7 @@ */ #define CONFIG_MPC555 1 /* This is an MPC555 CPU */ -#define CONFIG_CMI 1 /* Using the customized cmi board */ +#define CONFIG_CMI 1 /* Using the customized cmi board */ /* Serial Console Configuration */ #define CONFIG_5xx_CONS_SCI1 @@ -79,11 +79,11 @@ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif -#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */ #define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */ -#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ +#define CONFIG_WATCHDOG /* turn on platform specific watchdog */ #define CONFIG_STATUS_LED 1 /* Enable status led */ @@ -121,30 +121,30 @@ /* * Internal Memory Mapped (This is not the IMMR content) */ -#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ +#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */ /* * Definitions for initial stack pointer and data area */ -#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ -#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ -#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ +#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */ +#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */ +#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */ #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */ -#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ +#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */ /* * Start addresses for the final memory configuration * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ +#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */ #define CFG_FLASH_BASE 0x02000000 /* External flash */ #define PLD_BASE 0x03000000 /* PLD */ #define ANYBUS_BASE 0x03010000 /* Anybus Module */ #define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */ -#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ - /* This adress is given to the linker with -Ttext to */ - /* locate the text section at this adress. */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */ + /* This adress is given to the linker with -Ttext to */ + /* locate the text section at this adress. */ #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */ @@ -163,16 +163,16 @@ */ #define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */ -#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ +#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */ #define CFG_FLASH_PROTECTION 1 /* Physically section protection on */ #define CFG_ENV_IS_IN_FLASH 1 #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ -#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ +#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */ +#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */ #define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ #endif @@ -219,7 +219,7 @@ *----------------------------------------------------------------------- * Data show cycle */ -#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ +#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */ /*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register @@ -227,7 +227,7 @@ * Set all bits to 40 Mhz * */ -#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ +#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */ #define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0) @@ -236,12 +236,12 @@ *----------------------------------------------------------------------- * */ -#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ +#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register */ -#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ +#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */ /*----------------------------------------------------------------------- * USIU - Memory Controller Register @@ -256,7 +256,7 @@ #define CFG_OR2_PRELIM (OR_ADDR_MK_FF) #define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8) #define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \ - OR_ACS_10 | OR_ETHR | OR_CSNT) + OR_ACS_10 | OR_ETHR | OR_CSNT) #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index c7e3899e63..649b053c2b 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -101,7 +101,7 @@ * bootloader residing in flash ('chainloading'); if you want to use * chainloading or want to compile a u-boot binary that can be loaded into * RAM via BDM set - * "#if 0" to "#if 1" + * "#if 0" to "#if 1" * You will need a first stage bootloader then, e. g. colilo or a working BDM * cable (Background Debug Mode) * @@ -165,7 +165,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 0be0f21924..a807d0084d 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -37,7 +37,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_CSB226 1 /* on a CSB226 board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index a24478d0b3..15bf1772b9 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB272 1 /* on a Cogent CSB272 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ @@ -182,7 +182,7 @@ */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 064650cfca..b06c0a269d 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -33,7 +33,7 @@ * (easy to change) */ -#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CSB472 1 /* on a Cogent CSB472 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ @@ -181,7 +181,7 @@ */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 8ecd0595a2..632c4c2bf9 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -145,16 +145,16 @@ #define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CFG_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */ #define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*3) -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ #define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ #define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ #endif /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #undef CONFIG_BOOTDELAY #define CONFIG_BOOTFILE "uImage" /* Boot file name */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 96c9a30147..10166a1477 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -102,7 +102,7 @@ /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #undef CONFIG_BOOTDELAY #define CONFIG_BOOTFILE "uImage" /* Boot file name */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index de8c4fac2b..ba68605a05 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -140,16 +140,16 @@ #define CFG_MAX_FLASH_BANKS 1 /* max number of flash banks */ #define CFG_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */ #define CFG_ENV_OFFSET (CFG_FLASH_SECT_SZ*2) -#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ +#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */ #define CFG_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */ -#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ +#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */ #define CFG_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CFG_FLASH_SECT_SZ) #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SZ /* Env sector Size */ #endif /*==============================*/ /* U-Boot general configuration */ /*==============================*/ -#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ #define CONFIG_MISC_INIT_R #undef CONFIG_BOOTDELAY #define CONFIG_BOOTFILE "uImage" /* Boot file name */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index d32e046023..e7873e95fd 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -83,7 +83,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" #define CONFIG_ETHADDR 02:80:ad:20:31:b8 #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 172.22.2.23 diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h index f5cf477a31..54330821b1 100644 --- a/include/configs/ep7312.h +++ b/include/configs/ep7312.h @@ -34,7 +34,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_EP7312 1 /* on an EP7312 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -81,8 +81,8 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" -#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 /*#define CONFIG_NETMASK 255.255.0.0 */ /*#define CONFIG_IPADDR 172.22.2.128 */ /*#define CONFIG_SERVERIP 172.22.2.126 */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index cebe849f66..8a220b6816 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -234,13 +234,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 490db5fefd..0ce6b80b90 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -28,17 +28,17 @@ * board/config.h - configuration options, board specific * * "EP8260 H, V.1.1" - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 16M Flash (4 x AM29DL323DB90WDI) - * - 128k NVRAM with RTC + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 16M Flash (4 x AM29DL323DB90WDI) + * - 128k NVRAM with RTC * * "EP8260 H2, V.1.3" (CFG_EP8260_H2) - * - 300MHz/133MHz/66MHz - * - 64M 60x Bus SDRAM - * - 32M Local Bus SDRAM - * - 32M Flash - * - 128k NVRAM with RTC + * - 300MHz/133MHz/66MHz + * - 64M 60x Bus SDRAM + * - 32M Local Bus SDRAM + * - 32M Flash + * - 128k NVRAM with RTC */ #ifndef __CONFIG_H @@ -408,7 +408,7 @@ CFG_SBC_HRCW_IMMR |\ HRCW_APPC10 |\ HRCW_CS10PC01 |\ - CFG_SBC_MODCK_H |\ + CFG_SBC_MODCK_H |\ CFG_SBC_HRCW_BOOT_FLAGS) #else #define CFG_HRCW_MASTER 0x10400245 diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 8e5d6e57c7..ac5847ce12 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -229,7 +229,7 @@ #endif /* CFG_ENV_IS_IN_EEPROM */ /* RTC Configuration */ -#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ +#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ #define CFG_I2C_RTC_ADDR 0x68 #define CONFIG_M41T11_BASE_YEAR 1900 @@ -353,13 +353,13 @@ /* Hard reset configuration word */ #define CFG_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ /* No slaves */ -#define CFG_HRCW_SLAVE1 0 -#define CFG_HRCW_SLAVE2 0 -#define CFG_HRCW_SLAVE3 0 -#define CFG_HRCW_SLAVE4 0 -#define CFG_HRCW_SLAVE5 0 -#define CFG_HRCW_SLAVE6 0 -#define CFG_HRCW_SLAVE7 0 +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index 66500c21e0..1571477d02 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -98,7 +98,7 @@ #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTCOMMAND "tftp 100000 uImage" -/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ +/* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index 1276f4d83a..ffe7671ec0 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -58,7 +58,7 @@ #define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */ +#define CONFIG_SYS_CLK_FREQ 20000000 /* 20MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 710a082e97..7b1d582202 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -39,10 +39,10 @@ #define CONFIG_LEON3 /* This is an LEON3 CPU */ #define CONFIG_LEON 1 /* This is an LEON CPU */ /* Altera NIOS Development board, Stratix II board */ -#define CONFIG_GR_EP2S60 1 +#define CONFIG_GR_EP2S60 1 /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */ +#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index 1fdef3d4ab..6fe2b7cc3b 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -39,7 +39,7 @@ #define CONFIG_GRXC3S1500 1 /* ... on GR-XC3S-1500 board */ /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ +#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 60ad396f5f..3fb8eb3a61 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -46,7 +46,7 @@ #define CONFIG_TSIM 1 /* ... running on TSIM */ /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ +#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 2ad5b95a17..406ce3df37 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -45,7 +45,7 @@ #define CONFIG_TSIM 1 /* ... running on TSIM */ /* CPU / AMBA BUS configuration */ -#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ +#define CONFIG_SYS_CLK_FREQ 40000000 /* 40MHz */ /* Number of SPARC register windows */ #define CFG_SPARC_NWINDOWS 8 diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 4ecaf90abc..13b0358cb6 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -127,14 +127,14 @@ #ifdef CFG_ENV_IS_IN_EEPROM /* Put the environment after the SDRAM configuration */ -#define PROM_SIZE 2048 +#define PROM_SIZE 2048 #define CFG_ENV_OFFSET 512 #define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) #endif #ifdef CFG_ENV_IS_IN_FLASH /* Put the environment in Flash */ -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index f5f11978da..20808681f3 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -113,7 +113,7 @@ #ifdef CFG_ENV_IS_IN_EEPROM /* Put the environment after the SDRAM and bootstrap configuration */ -#define PROM_SIZE 2048 +#define PROM_SIZE 2048 #define CFG_BOOSTRAP_OPTION_OFFSET 512 #define CFG_ENV_OFFSET (CFG_BOOSTRAP_OPTION_OFFSET + 0x10) #define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET) @@ -134,7 +134,7 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ +#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */ #define CFG_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */ #undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */ #define CONFIG_DDR_ECC 1 /* enable ECC */ @@ -176,13 +176,13 @@ /* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME hcu5 #define CONFIG_IPADDR 172.25.1.99 -#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ +#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ #define CONFIG_OVERWRITE_ETHADDR_ONCE #define CONFIG_SERVERIP 172.25.1.3 #define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=0x01000000\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ @@ -192,11 +192,11 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "bootfile=hcu5/uImage\0" \ - "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ - "load=tftp 100000 hcu5/u-boot.bin\0" \ + "bootfile=hcu5/uImage\0" \ + "rootpath=/home/hcu/eldk/ppc_4xxFP\0" \ + "load=tftp 100000 hcu5/u-boot.bin\0" \ "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \ "cp.b 100000 FFFB0000 50000\0" \ "upd=run load update\0" \ @@ -204,9 +204,9 @@ "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \ "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \ " h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \ - "usbargs=setenv bootargs root=/dev/sda1 ro\0" \ + "usbargs=setenv bootargs root=/dev/sda1 ro\0" \ "linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \ - "run usbargs addip addtty; bootm\0" \ + "run usbargs addip addtty; bootm\0" \ "net_nfs_fdt=tftp 200000 ${bootfile};" \ "tftp ${fdt_addr} ${fdt_file};" \ "run nfsargs addip addtty;" \ diff --git a/include/configs/hermes.h b/include/configs/hermes.h index e3a2ed2803..48b23bdcd6 100644 --- a/include/configs/hermes.h +++ b/include/configs/hermes.h @@ -54,9 +54,9 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ + "bootp; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -105,7 +105,7 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ +#define CFG_ALLOC_DPRAM 1 /* use allocation routines */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) @@ -227,7 +227,7 @@ /* +0x0282 => 0x03800000 */ #define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ SCCR_RTDIV | SCCR_RTSEL | \ - /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ + /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ SCCR_EBDF00 | SCCR_DFSYNC00 | \ SCCR_DFBRG00 | SCCR_DFNL000 | \ SCCR_DFNH000) diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 2ed51f7784..7c3ebad4b7 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -164,7 +164,7 @@ # define CFG_FEC0_PINMUX 0 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 +# define MCFFEC_TOUT_LOOP 50000 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ # ifndef CFG_DISCOVER_PHY # define FECDUPLEX FULL diff --git a/include/configs/impa7.h b/include/configs/impa7.h index 0e52ffe0a2..e9704fc9af 100644 --- a/include/configs/impa7.h +++ b/include/configs/impa7.h @@ -34,7 +34,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_IMPA7 1 /* on an impA7 Board */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ -#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ +#define CONFIG_ARM7_REVD 1 /* enable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -80,7 +80,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" +#define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5a */ /*#define CONFIG_NETMASK 255.255.0.0 */ /*#define CONFIG_IPADDR 172.22.2.128 */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 5310e0d428..2b65052671 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -34,7 +34,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ @@ -136,11 +136,11 @@ /* * I2C bus */ -#define CONFIG_HARD_I2C 1 -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xfe +#define CONFIG_HARD_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xfe -#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_IS_IN_EEPROM 1 #define CFG_ENV_OFFSET 0x00 /* environment starts here */ #define CFG_ENV_SIZE 1024 /* 1 KiB */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index e1d1483b71..347fa0201d 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -140,7 +140,7 @@ SIB at Block62 End Block62 address 0x24f80000 */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ /*----------------------------------------------------------------------- * FLASH and environment organization @@ -156,9 +156,9 @@ SIB at Block62 End Block62 address 0x24f80000 */ #define CFG_FLASH_BASE 0x24000000 -#define CFG_MAX_FLASH_SECT 64 +#define CFG_MAX_FLASH_SECT 64 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index bc5f9e19bd..b7c43fedf3 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -165,7 +165,7 @@ */ #define CFG_SDR_CONFIG 0xd #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * GPIO settings @@ -178,7 +178,7 @@ * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -193,7 +193,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index a3be0b51e6..05dc841e35 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -201,13 +201,13 @@ */ #define CFG_SDR_CONFIG 0x18 #define CFG_SDR_MODE_CONFIG 0x1 -#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDRAM_REFRESH_CNT 0x81a /* * FLASH and environment organization */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -225,7 +225,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 0ac3e7e7b9..980e9fe9ce 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -142,7 +142,7 @@ /* * IPB Bus clocking configuration. */ -#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #if 0 /* pass open firmware flat tree */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index c7c42a4cdf..a59676870f 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -108,7 +108,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/korat.h b/include/configs/korat.h index 48d73ac376..765566697f 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -225,7 +225,7 @@ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #define CONFIG_HAS_ETH0 -#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ /* buffers & descriptors */ #define CONFIG_NET_MULTI 1 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ @@ -308,7 +308,7 @@ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) - /* Print Buffer Size */ + /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ @@ -339,7 +339,7 @@ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ /* CFG_PCI_MEMBASE */ /* Board-specific PCI */ #define CFG_PCI_TARGET_INIT diff --git a/include/configs/lart.h b/include/configs/lart.h index 8f18c9f1b1..4570398cd4 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -76,7 +76,7 @@ #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" +#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_IPADDR 172.22.2.131 diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 518186b08c..d3908b9eaf 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -114,9 +114,9 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_LOAD_ADDR 0x00800000 /* Default load address: 8 MB */ -#define CONFIG_BOOTCOMMAND "run bootcmd1" +#define CONFIG_BOOTCOMMAND "run bootcmd1" #define CONFIG_BOOTARGS "root=/dev/sda1 console=ttyS1,57600 netconsole=@192.168.1.7/eth0,@192.168.1.1/00:50:BF:A4:59:71 rtc-rs5c372.probe=0,0x32 debug" -#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" +#define CONFIG_NFSBOOTCOMMAND "bootp;run nfsargs;bootm" #define CFG_CONSOLE_IS_IN_ENV @@ -214,28 +214,28 @@ * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_FLASH_BASE 0xFFC00000 #define CFG_FLASH_SIZE 0x00400000 -#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_RESET_ADDRESS 0xFFF00100 -#define CFG_EUMB_ADDR 0x80000000 +#define CFG_RESET_ADDRESS 0xFFF00100 +#define CFG_EUMB_ADDR 0x80000000 #define CFG_PCI_MEM_ADDR 0xB0000000 #define CFG_MISC_REGION_ADDR 0xFE000000 -#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ +#define CFG_MONITOR_LEN 0x00040000 /* 256 kB */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */ +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0080000 |