Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	board/samsung/trats2/trats2.c
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>

46 files changed, 1233 insertions, 677 deletions

diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 5e718980ff..14bac155a3 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -106,7 +106,7 @@
 /* Ethernet */
 #define CONFIG_MACB
 #define CONFIG_RESET_PHY_R
-
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_NET_RETRY_COUNT		20
 
 /* USB */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index d75df92797..8af4d6afba 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -42,12 +42,11 @@
 	"dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \
 	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
 	"nandrootfstype=ubifs rootwait=1\0" \
-	"nandsrcaddr=0x280000\0" \
-		"nandboot=echo Booting from nand ...; " \
+	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
-		"bootz ${loadaddr}\0" \
-	"nandimgsize=0x500000\0"
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
 #else
 #define NANDARGS ""
 #endif
@@ -198,6 +197,10 @@
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+
 /* CPSW support */
 #define CONFIG_SPL_ETH_SUPPORT
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index a3473b51bd..1fa477aac8 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -141,8 +141,18 @@
 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
 #define CONFIG_SYS_I2C_OMAP34XX
 
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
+/*
+ * Ethernet
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+
 /*
  * Board NAND Info.
  */
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index ea8753b544..a3cb56b8bf 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -198,10 +198,6 @@
 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
 
-#define CONFIG_SPI_BOOTING
-#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
-#define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
 #define CONFIG_CMD_PART
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 1c4bb812f0..73917b0ec1 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -181,6 +181,7 @@
 #define CONFIG_RMII			1
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 0a1969df98..b9aa036039 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -275,6 +275,7 @@
 #define CONFIG_RMII			1
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 2095fe6879..ccfda71c95 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -15,7 +15,6 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x73f00000
 
-#define CONFIG_AT91_LEGACY
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 
 /* ARM asynchronous clock */
@@ -77,6 +76,10 @@
 /*
  * Command line configuration.
  */
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_FPGA
@@ -97,9 +100,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
 
-/* No NOR flash */
-#define CONFIG_SYS_NO_FLASH
-
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
@@ -120,6 +120,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_EHCI
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 4ec1799ebc..e23549d444 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -113,8 +113,8 @@
 #define CONFIG_SYS_NAND_BASE		0x40000000
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 5
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
 
 /* PMECC & PMERRLOC */
 #define CONFIG_ATMEL_NAND_HWECC
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
new file mode 100644
index 0000000000..56e9a8e0e8
--- /dev/null
+++ b/include/configs/cm_t335.h
@@ -0,0 +1,182 @@
+/*
+ * Config file for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_T335_H
+#define __CONFIG_CM_T335_H
+
+#define CONFIG_CM_T335
+#define CONFIG_NAND
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_SPI
+#undef CONFIG_OMAP3_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_BOOTCOUNT_LIMIT
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#undef CONFIG_MAX_RAM_BANK_SIZE
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 512MB */
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"CM-T335 # "
+
+#define CONFIG_OMAP_COMMON
+
+#define MACH_TYPE_CM_T335		4586	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_CM_T335
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
+
+#ifndef CONFIG_SPL_BUILD
+#define MMCARGS \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0"
+
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandroot=ubi0:rootfs rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"ubi.mtd=${rootfs_name}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nboot ${loadaddr} nand0 900000; " \
+		"bootm ${loadaddr}\0"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=82000000\0" \
+	"console=ttyO0,115200n8\0" \
+	"rootfs_name=rootfs\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	MMCARGS \
+	NANDARGS
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+/* Serial console configuration */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SERIAL1			1	/* UART0 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_BAUDRATE			115200
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/* SPL */
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			0
+#define CONFIG_PHY_ATHEROS
+
+/* NAND support */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+#define CONFIG_CMD_NAND
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:2m(spl)," \
+					"1m(u-boot),1m(u-boot-env)," \
+					"1m(dtb),4m(splash)," \
+					"6m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* GPIO pin + bank to pin ID mapping */
+#define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
+
+/* Status LED */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT			GPIO_PIN(2, 0)
+/* Status LED polarity is inversed, so init it in the "off" state */
+#define STATUS_LED_STATE		STATUS_LED_OFF
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT			0
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Enable PCA9555 at I2C0-0x26.
+ * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
+ */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
+#endif /* CONFIG_SPL_BUILD */
+
+#endif	/* __CONFIG_CM_T335_H */
+
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index f4ecd0ddbe..e72187e30b 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -302,12 +302,13 @@
 /* Status LED */
 #define CONFIG_STATUS_LED		/* Status LED enabled */
 #define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_GREEN		0
-#define STATUS_LED_BIT			STATUS_LED_GREEN
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+#define GREEN_LED_DEV			0
+#define STATUS_LED_BIT			GREEN_LED_GPIO
 #define STATUS_LED_STATE		STATUS_LED_ON
 #define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
-#define STATUS_LED_BOOT			STATUS_LED_BIT
-#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+#define STATUS_LED_BOOT			GREEN_LED_DEV
 
 #define CONFIG_SPLASHIMAGE_GUARD
 
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
new file mode 100644
index 0000000000..11ba4cffc4
--- /dev/null
+++ b/include/configs/corvus.h
@@ -0,0 +1,165 @@
+/*
+ * Common board functions for siemens AT91SAM9G45 based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define MACH_TYPE_CORVUS               2066
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+#define CONFIG_SYS_TEXT_BASE  0x73f00000
+
+#define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ		        1000
+
+#define CONFIG_AT91FAMILY
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
+#define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x72000000	/* load address */
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE +	\
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + \
+				128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index ccf36a5f93..39f7062388 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -280,8 +280,8 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_SYS_NAND_BASE			0x40000000
 #define CONFIG_SYS_NAND_DBW_8			1
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTC, 13
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PC(13)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 
@@ -310,6 +310,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT			20
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* LEDS */
 /* Status LED */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8a69c7d0a6..48b47cbd0b 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -83,4 +83,15 @@
 #define CONFIG_OMAP_USB_PHY
 #define CONFIG_OMAP_USB2PHY2_HOST
 
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h
index cd553ec55b..1e42f5c23c 100644
--- a/include/configs/dxr2.h
+++ b/include/configs/dxr2.h
@@ -21,8 +21,8 @@
 
 #define CONFIG_SYS_MPUCLK	275
 #define DXR2_IOCTRL_VAL	0x18b
-#define DDR_PLL_FREQ	266
-#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K
+#define DDR_PLL_FREQ	303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #define BOARD_DFU_BUTTON_GPIO	27
 #define BOARD_DFU_BUTTON_LED	64
@@ -62,7 +62,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=dxr2\0" \
-	"nand_img_size=0x300000\0" \
+	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	CONFIG_COMMON_ENV_SETTINGS
 
@@ -75,10 +75,9 @@
 	"run dfu_start; " \
 	"reset; " \
 "fi;" \
-"if ping ${serverip}; then " \
-	"run net_nfs; " \
-"fi;" \
-"run nand_boot;"
+"run nand_boot;" \
+"reset;"
+
 
 #else
 #define CONFIG_BOOTDELAY		0
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 2d8c42cf57..f7e70aa573 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -41,10 +41,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 #define CONFIG_STANDALONE_LOAD_ADDR	0x21000000
 
-#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
-#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
-
 #define CONFIG_BOOT_RETRY_TIME		30
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 252df54e98..480d8678c6 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -149,7 +149,7 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
 #endif
 
 /* JFFS2 */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 1e9c1e3118..8fb904cddf 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -157,6 +157,7 @@
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
 
 /* specific .lds file */
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
@@ -266,6 +267,7 @@
 /* SPI */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
 
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_EXYNOS_SPI
@@ -291,27 +293,6 @@
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX77686
 
-/* SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED		50000000
-#define EXYNOS5_SPI_NUM_CONTROLLERS	5
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
-#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS	1
-#define CONFIG_ENV_SPI_MAX_HZ	50000000
-#endif
-
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_SMC911X
diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h
deleted file mode 100644
index 4ba2c55e98..0000000000
--- a/include/configs/h2_p2_dbg_board.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   TI H2 and P2 Debug Board hardware map
- *
- * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
- * Author: MPC-Data Limited
- *	   Dave Peverley
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
-#define __INCLUDED_H2_P2_DBH_BOARD_H
-
-#include <asm/sizes.h>
-
-/*
- * The Debug board is designed to function with the P2 Sample, H2
- * Sample and 1610 Innovator boards. The main difference AFAICT is
- * the chip selects used with each system ;
- *
- *   P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
- *   H2 Sample : CS1a is used to select the CPLD registers.
- *
- */
-
-/***************************************************************************
- * CPLD Registers
- **************************************************************************/
-
-#define H2DBG_CPLD_REVISION        0x04000010
-#define H2DBG_BOARD_REVISION       0x04000012
-#define H2DBG_GPIO_REGISTER        0x04000014
-#define H2DBG_LED_CONTROL          0x04000016
-#define H2DBG_MISC_INPUT           0x04000018
-#define H2DBG_LAN_STATUS           0x0400001A
-#define H2DBG_LAN_RESET            0x0400001C
-#define H2DBG_ETH_REG_BASE         0x04000300
-
-/***************************************************************************
- * Ethernet Control Registers
- * These are for the LAN91C96 on the debug board
- **************************************************************************/
-
-/* Bank 0 in IO space */
-
-#define ETH_TCR            (H2DBG_ETH_REG_BASE + 0x00)   /* Transmit Control Register */
-#define ETH_EPH_STATUS     (H2DBG_ETH_REG_BASE + 0x02)   /* EPH Status Register */
-#define ETH_RCR            (H2DBG_ETH_REG_BASE + 0x04)   /* Receive Control Register */
-#define ETH_COUNTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Counter Register */
-#define ETH_MIR            (H2DBG_ETH_REG_BASE + 0x08)   /* Memory Information Register */
-#define ETH_MCR            (H2DBG_ETH_REG_BASE + 0x0A)   /* Memory Configuration Register */
-
-/* Bank 1 in IO space */
-
-#define ETH_CONFIG         (H2DBG_ETH_REG_BASE + 0x00)   /* Configuration Register */
-#define ETH_BASE           (H2DBG_ETH_REG_BASE + 0x02)   /* Base Address Register */
-#define ETH_IA0            (H2DBG_ETH_REG_BASE + 0x04)   /* Individual Address Register - 0 */
-#define ETH_IA1            (H2DBG_ETH_REG_BASE + 0x05)   /* Individual Address Register - 1 */
-#define ETH_IA2            (H2DBG_ETH_REG_BASE + 0x06)   /* Individual Address Register - 2 */
-#define ETH_IA3            (H2DBG_ETH_REG_BASE + 0x07)   /* Individual Address Register - 3 */
-#define ETH_IA4            (H2DBG_ETH_REG_BASE + 0x08)   /* Individual Address Register - 4 */
-#define ETH_IA5            (H2DBG_ETH_REG_BASE + 0x09)   /* Individual Address Register - 5 */
-#define ETH_GEN_PURPOSE    (H2DBG_ETH_REG_BASE + 0x0A)   /* General Address Registers */
-#define ETH_CONTROL        (H2DBG_ETH_REG_BASE + 0x0B)   /* Control Register */
-
-/* Bank 2 in IO space */
-
-#define ETH_MMU            (H2DBG_ETH_REG_BASE + 0x00)   /* MMU Command Register */
-#define ETH_AUTO_TX_START  (H2DBG_ETH_REG_BASE + 0x01)   /* Auto Tx Start Register */
-#define ETH_PNR            (H2DBG_ETH_REG_BASE + 0x02)   /* Packet Number Register */
-#define ETH_ARR            (H2DBG_ETH_REG_BASE + 0x03)   /* Allocation Result Register */
-#define ETH_FIFO           (H2DBG_ETH_REG_BASE + 0x04)   /* FIFO Ports Register */
-#define ETH_POINTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Pointer Register */
-#define ETH_DATA_HIGH      (H2DBG_ETH_REG_BASE + 0x08)   /* Data High Register */
-#define ETH_DATA_LOW       (H2DBG_ETH_REG_BASE + 0x0A)   /* Data Low Register */
-#define ETH_INT_STATS      (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Status Register - RO */
-#define ETH_INT_ACK        (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Acknowledge Register -WO */
-#define ETH_INT_MASK       (H2DBG_ETH_REG_BASE + 0x0D)   /* Interrupt Mask Register */
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * A couple of utility inlines to aid debugging using the LED's on the
- * debug board.
- */
-
-static inline void set_led_state(int state)
-{
-	static unsigned long hw_led_state = 0;
-	volatile unsigned short *led_address = (volatile unsigned short *)0x04000016;
-
-	hw_led_state = ((unsigned long)state);
-	*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
-}
-
-
-static inline void spin_up_leds(void)
-{
-	volatile int i, j, k;
-
-	for (k = 0; k < 2; k++) {
-		for (i = 0; i < 16; i++) {
-			for (j = 0; j < 5000; j++) {
-				set_led_state(1 << i);
-			}
-		}
-		for (i = 15; i >= 0; i--) {
-			for (j = 0; j < 5000; j++) {
-				set_led_state(1 << i);
-			}
-		}
-	}
-}
-
-#endif    /* !  __ASSEMBLY__ */
-
-#endif    /* !  __INCLUDED_H2_P2_DBH_BOARD_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
new file mode 100644
index 0000000000..59c494854b
--- /dev/null
+++ b/include/configs/koelsch.h
@@ -0,0 +1,133 @@
+/*
+ * include/configs/koelsch.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __KOELSCH_H
+#define __KOELSCH_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7791
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define	CONFIG_CMD_EDITENV
+#define	CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_BOOTZ
+#define	CONFIG_CMD_FLASH
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE633fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define KOELSCH_SDRAM_BASE	0x40000000
+#define KOELSCH_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define KOELSCH_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(KOELSCH_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* Board Clock */
+#define	CONFIG_SYS_CLK_FREQ	10000000
+#define CONFIG_SH_TMU_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ	14745600
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#define CONFIG_SYS_HZ		1000
+
+#endif	/* __KOELSCH_H */
diff --git a/include/configs/lager.h b/include/configs/lager.h
new file mode 100644
index 0000000000..7819edddc6
--- /dev/null
+++ b/include/configs/lager.h
@@ -0,0 +1,141 @@
+/*
+ * include/configs/lager.h
+ *     This file is lager board configuration.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __LAGER_H
+#define __LAGER_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7790
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Lager"
+#define CONFIG_SH_GPIO_PFC
+#define MACH_TYPE_LAGER		4538
+#define CONFIG_MACH_TYPE	MACH_TYPE_LAGER
+
+#include <asm/arch/rmobile.h>
+
+#define	CONFIG_CMD_EDITENV
+#define	CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_BOOTZ
+#define	CONFIG_CMD_FLASH
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+#define	CONFIG_OF_LIBFDT
+
+/* #define CONFIG_OF_LIBFDT */
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE827fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define LAGER_SDRAM_BASE	0x40000000
+#define LAGER_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define LAGER_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(LAGER_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* USE NOR FLASH */
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* Board Clock */
+#define CONFIG_BASE_CLK_FREQ	20000000u
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_BASE_CLK_FREQ * 156 / 2)
+#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
+#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_MP_CLK_FREQ
+
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#define CONFIG_SYS_HZ		1000
+
+#endif	/* __LAGER_H */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 91f6e2f8d3..86ce5f2397 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -143,8 +143,8 @@
 # define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
-# define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* Ethernet */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 9eab1903ff..3acb8543f8 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -118,9 +118,6 @@
 #define CONFIG_USB_EHCI_OMAP
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	147
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 6820e424d6..73dc088595 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -36,9 +36,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
 #include <configs/omap4_common.h>
 #define CONFIG_CMD_NET
 
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 4d3a800298..2f128b8a69 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -69,4 +69,14 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/omap730.h b/include/configs/omap730.h
deleted file mode 100644
index b54e0fb2da..0000000000
--- a/include/configs/omap730.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   OMAP730 hardware map
- *
- * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
- * Author: MPC-Data Limited
- *	   Dave Peverley
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __INCLUDED_OMAP730_H
-#define __INCLUDED_OMAP730_H
-
-#include <asm/sizes.h>
-
-/***************************************************************************
- * OMAP730 Configuration Registers
- **************************************************************************/
-
-#define PERSEUS2_MPU_DEV_ID               ((unsigned int)(0xFFFE1000))
-#define PERSEUS2_GSM_DEV_ID0              ((unsigned int)(0xFFFE1000))
-#define PERSEUS2_GDM_DEV_ID1              ((unsigned int)(0xFFFE1002))
-#define DSP_CONF                          ((unsigned int)(0xFFFE1004))
-#define PERSEUS2_MPU_DIE_ID0              ((unsigned int)(0xFFFE1008))
-#define GSM_ASIC_CONF                     ((unsigned int)(0xFFFE1008))
-#define PERSEUS2_MPU_DIE_ID1              ((unsigned int)(0xFFFE100C))
-#define PERSEUS2_MODE1                    ((unsigned int)(0xFFFE1010))
-#define PERSEUS2_GSM_DIE_ID0              ((unsigned int)(0xFFFE1010))
-#define PERSEUS2_GSM_DIE_ID1              ((unsigned int)(0xFFFE1012))
-#define PERSEUS2_MODE2                    ((unsigned int)(0xFFFE1014))
-#define PERSEUS2_GSM_DIE_ID2              ((unsigned int)(0xFFFE1014))
-#define PERSEUS2_GSM_DIE_ID3              ((unsigned int)(0xFFFE1016))
-#define PERSEUS2_ANALOG_CELLS_CONF        ((unsigned int)(0xFFFE1018))
-#define SPECCTL                           ((unsigned int)(0xFFFE101C))
-#define SPARE1                            ((unsigned int)(0xFFFE1020))
-#define SPARE2                            ((unsigned int)(0xFFFE1024))
-#define GSM_PBG_IRQ                       ((unsigned int)(0xFFFE1028))
-#define DMA_REQ_CONF                      ((unsigned int)(0xFFFE1030))
-#define PE_CONF_NO_DUAL                   ((unsigned int)(0xFFFE1060))
-#define PERSEUS2_IO_CONF0                 ((unsigned int)(0xFFFE1070))
-#define PERSEUS2_IO_CONF1                 ((unsigned int)(0xFFFE1074))
-#define PERSEUS2_IO_CONF2                 ((unsigned int)(0xFFFE1078))
-#define PERSEUS2_IO_CONF3                 ((unsigned int)(0xFFFE107C))
-#define PERSEUS2_IO_CONF4                 ((unsigned int)(0xFFFE1080))
-#define PERSEUS2_IO_CONF5                 ((unsigned int)(0xFFFE1084))
-#define PERSEUS2_IO_CONF6                 ((unsigned int)(0xFFFE1088))
-#define PERSEUS2_IO_CONF7                 ((unsigned int)(0xFFFE108C))
-#define PERSEUS2_IO_CONF8                 ((unsigned int)(0xFFFE1090))
-#define PERSEUS2_IO_CONF9                 ((unsigned int)(0xFFFE1094))
-#define PERSEUS2_IO_CONF10                ((unsigned int)(0xFFFE1098))
-#define PERSEUS2_IO_CONF11                ((unsigned int)(0xFFFE109C))
-#define PERSEUS2_IO_CONF12                ((unsigned int)(0xFFFE10A0))
-#define PERSEUS2_IO_CONF13                ((unsigned int)(0xFFFE10A4))
-#define PERSEUS_PCC_CONF_REG              ((unsigned int)(0xFFFE10B4))
-#define BIST_STATUS_INTERNAL              ((unsigned int)(0xFFFE10B8))
-#define BIST_CONTROL                      ((unsigned int)(0xFFFE10C0))
-#define BOOT_ROM_REG                      ((unsigned int)(0xFFFE10C4))
-#define PRODUCTION_ID_REG                 ((unsigned int)(0xFFFE10C8))
-#define BIST_SECROM_SIGNATURE1_INTERNAL   ((unsigned int)(0xFFFE10D0))
-#define BIST_SECROM_SIGNATURE2_INTERNAL   ((unsigned int)(0xFFFE10D4))
-#define BIST_CONTROL_2                    ((unsigned int)(0xFFFE10D8))
-#define DEBUG1                            ((unsigned int)(0xFFFE10E0))
-#define DEBUG2                            ((unsigned int)(0xFFFE10E4))
-#define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
-
-/***************************************************************************
- * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
- **************************************************************************/
-
-#define TCMIF_BASE                 0xFFFECC00
-
-#define EMIFS_LRUREG               (TCMIF_BASE + 0x04)
-#define EMIFS_CONFIG               (TCMIF_BASE + 0x0C)
-#define FLASH_CFG_0                (TCMIF_BASE + 0x10)
-#define FLASH_CFG_1                (TCMIF_BASE + 0x14)
-#define FLASH_CFG_2                (TCMIF_BASE + 0x18)
-#define FLASH_CFG_3                (TCMIF_BASE + 0x1C)
-#define FL_CFG_DYN_WAIT            (TCMIF_BASE + 0x40)
-#define EMIFS_TIMEOUT1_REG         (TCMIF_BASE + 0x28)
-#define EMIFS_TIMEOUT2_REG         (TCMIF_BASE + 0x2C)
-#define EMIFS_TIMEOUT3_REG         (TCMIF_BASE + 0x30)
-#define EMIFS_ABORT_ADDR           (TCMIF_BASE + 0x44)
-#define EMIFS_ABORT_TYPE           (TCMIF_BASE + 0x48)
-#define EMIFS_ABORT_TOUT           (TCMIF_BASE + 0x4C)
-#define FLASH_ACFG_0_1             (TCMIF_BASE + 0x50)
-#define FLASH_ACFG_1_1             (TCMIF_BASE + 0x54)
-#define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
-#define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
-
-/***************************************************************************
- * OMAP730 Interrupt handlers
- **************************************************************************/
-
-#define OMAP_IH1_BASE		0xFFFECB00     /* MPU Level 1 IRQ handler */
-#define OMAP_IH2_BASE           0xfffe0000
-
-/***************************************************************************
- * OMAP730 Timers
- *
- * There are three general purpose OS timers in the 730 that can be
- * configured in autoreload or one-shot modes.
- **************************************************************************/
-
-#define OMAP730_32kHz_TIMER_BASE  0xFFFB9000
-
-/* 32k Timer Registers */
-#define TIMER32k_CR               0x08
-#define TIMER32k_TVR              0x00
-#define TIMER32k_TCR              0x04
-
-/* 32k Timer Control Register definition */
-#define TIMER32k_TSS              (1<<0)
-#define TIMER32k_TRB              (1<<1)
-#define TIMER32k_INT              (1<<2)
-#define TIMER32k_ARL              (1<<3)
-
-/* MPU Timer base addresses  */
-#define OMAP730_MPUTIMER_BASE	0xfffec500
-#define OMAP730_MPUTIMER_OFF	0x00000100
-
-#define OMAP730_TIMER1_BASE	0xFFFEC500
-#define OMAP730_TIMER2_BASE	0xFFFEC600
-#define OMAP730_TIMER3_BASE	0xFFFEC700
-
-/* MPU Timer Register offsets */
-#define CNTL_TIMER	           0x00   /* MPU_CNTL_TIMER */
-#define LOAD_TIM	           0x04   /* MPU_LOAD_TIMER */
-#define READ_TIM	           0x08   /* MPU_READ_TIMER */
-
-/* MPU_CNTL_TIMER register bits */
-#define MPUTIM_FREE               (1<<6)
-#define MPUTIM_CLOCK_ENABLE       (1<<5)
-#define MPUTIM_PTV_MASK           (0x7<<MPUTIM_PTV_BIT)
-#define MPUTIM_PTV_BIT            2
-#define MPUTIM_AR                 (1<<1)
-#define MPUTIM_ST                 (1<<0)
-
-/***************************************************************************
- * OMAP730 GPIO
- *
- * The GPIO control is split over 6 register bases in the OMAP730 to allow
- * access to all the (6 x 32) GPIO pins!
- **************************************************************************/
-
-#define OMAP730_GPIO_BASE_1        0xFFFBC000
-#define OMAP730_GPIO_BASE_2        0xFFFBC800
-#define OMAP730_GPIO_BASE_3        0xFFFBD000
-#define OMAP730_GPIO_BASE_4        0xFFFBD800
-#define OMAP730_GPIO_BASE_5        0xFFFBE000
-#define OMAP730_GPIO_BASE_6        0xFFFBE800
-
-#define GPIO_DATA_INPUT            0x00
-#define GPIO_DATA_OUTPUT           0x04
-#define GPIO_DIRECTION_CONTROL     0x08
-#define GPIO_INTERRUPT_CONTROL     0x0C
-#define GPIO_INTERRUPT_MASK        0x10
-#define GPIO_INTERRUPT_STATUS      0x14
-
-#define GPIO_DATA_INPUT_1            ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_1           ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_1        ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_1      ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_2            ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_2           ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_2        ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_2      ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_3            ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_3           ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_3        ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_3      ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_4            ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_4           ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_4        ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_4      ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_5            ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_5           ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_5        ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_5      ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_6            ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_6           ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
-
-/***************************************************************************
- * OMAP730 Watchdog timers
- **************************************************************************/
-
-#define WDTIM_BASE                 0xFFFEC800
-#define WDTIM_CONTROL              (WDTIM_BASE + 0x00)    /* MPU_CNTL_TIMER */
-#define WDTIM_LOAD                 (WDTIM_BASE + 0x04)    /* MPU_LOAD_TIMER */
-#define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
-#define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
-
-/***************************************************************************
- * OMAP730 Interrupt Registers
- **************************************************************************/
-
-/* Interrupt Register offsets */
-
-#define IRQ_ITR                               0x00
-#define IRQ_MIR                               0x04
-#define IRQ_SIR_IRQ                           0x10
-#define IRQ_SIR_FIQ                           0x14
-#define IRQ_CONTROL_REG                       0x18
-#define IRQ_ILR0                              0x1C  /* ILRx == ILR0 + (0x4 * x) */
-#define IRQ_SIR                               0x9C  /* a.k.a.IRQ_ISR */
-#define IRQ_GMIR                              0xA0
-
-#define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
-#define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
-
-/***************************************************************************
- * OMAP730 Intersystem Communication Register                      (TRM 4.5)
- **************************************************************************/
-
-#define ICR_BASE                   0xFFFBB800
-
-#define M_ICR                      (ICR_BASE + 0x00)
-#define G_ICR                      (ICR_BASE + 0x02)
-#define M_CTL                      (ICR_BASE + 0x04)
-#define G_CTL                      (ICR_BASE + 0x06)
-#define PM_BA                      (ICR_BASE + 0x0A)
-#define DM_BA                      (ICR_BASE + 0x0C)
-#define RM_BA                      (ICR_BASE + 0x0E)
-#define SSPI_TAS                   (ICR_BASE + 0x12)
-
-#endif /* ! __INCLUDED_OMAP730_H */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
deleted file mode 100644
index 947f27bae5..0000000000
--- a/include/configs/omap730p2.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * MPC Data Limited (http://www.mpc-data.co.uk)
- * Dave Peverley <dpeverley at mpc-data.co.uk>
- *
- * Configuation settings for the TI OMAP Perseus 2 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_ARM926EJS	   1	     /* This is an arm926ejs CPU core  */
-#define CONFIG_OMAP		   1	     /* in a TI OMAP core    */
-#define CONFIG_OMAP730		   1	     /* which is in a 730  */
-#define CONFIG_P2_OMAP730	   1	     /*	 a Perseus 2 Board  */
-
-/*
- * Input clock of PLL
- * The OMAP730 Perseus 2 has 13MHz input clock
- */
-
-#define CONFIG_SYS_CLK_FREQ	   13000000
-
-#define CONFIG_CMDLINE_TAG	   1	     /* enable passing of ATAGs	 */
-#define CONFIG_SETUP_MEMORY_TAGS   1
-
-/*
- * Size of malloc() pool
- */
-
-#define CONFIG_SYS_MALLOC_LEN		   (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE	   0x04000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	   (1)
-#define CONFIG_SYS_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
-#define CONFIG_SYS_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
-						   * on perseus */
-
-/*
- * select serial console configuration
- */
-
-#define CONFIG_SERIAL1		   1	     /* we use SERIAL 1 on OMAP730 Perseus 2 */
-
-#define CONFIG_CONS_INDEX	   1
-#define CONFIG_BAUDRATE		   115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-#include <configs/omap730.h>
-#include <configs/h2_p2_dbg_board.h>
-
-#define CONFIG_BOOTDELAY	   3
-#define CONFIG_BOOTARGS		   "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
-
-#define CONFIG_LOADADDR		   0x10000000
-
-#define CONFIG_ETHADDR
-#define CONFIG_NETMASK		   255.255.255.0
-#define CONFIG_IPADDR		   192.168.0.23
-#define CONFIG_SERVERIP		   192.150.0.100
-#define CONFIG_BOOTFILE		   "uImage"  /* File to load */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	   115200    /* Speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	   1	     /* Which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP				       /* undef to save memory	   */
-#define CONFIG_SYS_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
-#define CONFIG_SYS_CBSIZE		   256		       /* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		   (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		   16		       /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		   CONFIG_SYS_CBSIZE	       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	   0x10000000	       /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
-
-#define CONFIG_SYS_LOAD_ADDR		   0x10000000	       /* default load address */
-
-/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
- * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
- * local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		0xFFFEC500	/* use timer 1 */
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
-#define CONFIG_NR_DRAM_BANKS	   1		  /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		   0x10000000	  /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	   0x02000000	  /* 32 MB */
-
-#if defined(CONFIG_CS0_BOOT)
-#define PHYS_FLASH_1		   0x0C000000
-#elif defined(CONFIG_CS3_BOOT)
-#define PHYS_FLASH_1		   0x00000000
-#else
-#error Unknown Boot Chip-Select number
-#endif
-
-#define PHYS_SRAM		0x20000000
-
-#define CONFIG_SYS_FLASH_BASE		   PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
-#define PHYS_FLASH_SIZE		   0x02000000	  /* 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
-/* addr of environment */
-#define CONFIG_ENV_ADDR		   (CONFIG_SYS_FLASH_BASE + 0x020000)
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH	   1
-#define CONFIG_ENV_SIZE		   0x20000	  /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET		   0x20000	  /* environment starts here  */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 	PHYS_SRAM
-
-#endif	  /* ! __CONFIG_H */
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index 3f4e0734ab..629967d054 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -193,8 +193,8 @@
 # define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
-# define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* Ethernet */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index fc95cf0bfa..4a71927217 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -50,15 +50,13 @@
 #define	CONFIG_SYS_MCKR1_VAL		\
 		(AT91_PMC_MCKR_CSS_SLOW |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
 		(AT91_PMC_MCKR_CSS_PLLA |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
@@ -166,9 +164,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTC, 12
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTC, 13
-#define	CONFIG_YELLOW_LED	AT91_PIO_PORTC, 15
+#define CONFIG_RED_LED		GPIO_PIN_PC(12)
+#define CONFIG_GREEN_LED	GPIO_PIN_PC(13)
+#define CONFIG_YELLOW_LED	GPIO_PIN_PC(15)
 
 #define CONFIG_BOOTDELAY	3
 
@@ -221,8 +219,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 16
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
 
 /* NOR flash */
 #define CONFIG_SYS_FLASH_CFI			1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 533e249a7c..d9c04d14b9 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -179,8 +179,8 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTB, 7	/* this is the power led */
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTB, 8	/* this is the user1 led */
+#define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -241,8 +241,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 30
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
 
 #endif
 
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index e0c388e70c..f78e0ec173 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -54,8 +54,8 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTD, 31 /* this is the user1 led */
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTD, 0 /* this is the user2 led */
+#define CONFIG_RED_LED		GPIO_PIN_PD(31) /* this is the user1 led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PD(0)  /* this is the user2 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -106,8 +106,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 3
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(3)
 
 #endif
 
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 20b0f9ab4d..7722f7be2e 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -70,6 +70,7 @@
 	"hostname=pxm2\0" \
 	"nand_img_size=0x500000\0" \
 	"optargs=\0" \
+	"splashpos=m,m\0"	\
 	CONFIG_COMMON_ENV_SETTINGS \
 	"mmc_dev=0\0" \
 	"mmc_root=/dev/mmcblk0p2 rw\0" \
@@ -118,9 +119,7 @@
 		"fi;" \
 	"fi;" \
 	"run nand_boot;" \
-	"if ping ${serverip}; then " \
-		"run net_nfs; " \
-	"fi; "
+	"reset;"
 
 #else
 #define CONFIG_BOOTDELAY		0
@@ -148,6 +147,8 @@
 #define DA8XX_LCD_CNTL_BASE	LCD_CNTL_BASE
 #define PWM_TICKS	0x1388
 #define PWM_DUTY	0x200
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
 #endif	/* ! __CONFIG_PXM2_H */
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 7c94644de8..d4519f946c 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -65,7 +65,8 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=rut\0" \
-	"splashpos=488,352\0" \
+	"nand_img_size=0x500000\0" \
+	"splashpos=m,m\0" \
 	"optargs=fixrtc --no-log consoleblank=0 \0" \
 	CONFIG_COMMON_ENV_SETTINGS \
 	"mmc_dev=0\0" \
@@ -111,9 +112,7 @@
 		"fi;" \
 	"fi;" \
 	"run nand_boot;" \
-	"if ping ${serverip}; then " \
-		"run net_nfs; " \
-	"fi; "
+	"reset;"
 
 #else
 #define CONFIG_BOOTDELAY		0
@@ -151,6 +150,9 @@
 #define BOARD_LCD_RESET		115	/* Bank 3 pin 19 */
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_FORMIKE
+#define DISPL_PLL_SPREAD_SPECTRUM
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
 #endif	/* ! __CONFIG_RUT_H */
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 5a6f0fc708..c34feb5081 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -24,7 +24,10 @@
 #define CONFIG_AT91FAMILY
 #define CONFIG_ARCH_CPU_INIT
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
@@ -93,8 +96,12 @@
 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
 #define CONFIG_SYS_SDRAM_SIZE		0x20000000
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x310000
+#else
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
 
 /* SerialFlash */
 #define CONFIG_CMD_SF
@@ -235,4 +242,31 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT		arch/arm/cpu/at91-common/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#endif
+
 #endif
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index cbcd4e16b2..7e16c451c3 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -115,6 +115,7 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index f37653fea3..4569fd4840 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -254,11 +254,11 @@
 #define CONFIG_USB_GADGET
 #define CONFIG_USBDOWNLOAD_GADGET
 
-/* USB TI's IDs */
+/* USB DRACO ID as default */
 #define CONFIG_USBD_HS
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0908
+#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
+#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
 
 /* USB Device Firmware Update support */
 #define CONFIG_DFU_FUNCTION
@@ -358,31 +358,38 @@
 #define CONFIG_COMMON_ENV_SETTINGS \
 	"verify=no \0" \
 	"project_dir=systemone\0" \
+	"upgrade_available=0\0" \
+	"altbootcmd=run bootcmd\0" \
+	"bootlimit=3\0" \
+	"partitionset_active=A\0" \
 	"loadaddr=0x82000000\0" \
 	"kloadaddr=0x81000000\0" \
 	"script_addr=0x81900000\0" \
-	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \
-	"active_set=a\0" \
+	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
 	"nand_active_ubi_vol=rootfs_a\0" \
+	"nand_active_ubi_vol_A=rootfs_a\0" \
+	"nand_active_ubi_vol_B=rootfs_b\0" \
 	"nand_root_fs_type=ubifs rootwait=1\0" \
 	"nand_src_addr=0x280000\0" \
-	"nand_src_addr_a=0x280000\0" \
-	"nand_src_addr_b=0x780000\0" \
+	"nand_src_addr_A=0x280000\0" \
+	"nand_src_addr_B=0x780000\0" \
 	"nfsopts=nolock rw mem=128M\0" \
 	"ip_method=none\0" \
 	"bootenv=uEnv.txt\0" \
 	"bootargs_defaults=setenv bootargs " \
 		"console=${console} " \
+		"${testargs} " \
 		"${optargs}\0" \
 	"nand_args=run bootargs_defaults;" \
 		"mtdparts default;" \
-		"setenv nand_active_ubi_vol rootfs_${active_set};" \
-		"setenv ${active_set} true;" \
-		"if test -n ${a}; then " \
-			"setenv nand_src_addr ${nand_src_addr_a};" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
+			"setenv nand_src_addr ${nand_src_addr_A};" \
 		"fi;" \
-		"if test -n ${b}; then " \
-			"setenv nand_src_addr ${nand_src_addr_b};" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
+			"setenv nand_src_addr ${nand_src_addr_B};" \
 		"fi;" \
 		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
 		"ubi.mtd=9,2048;" \
@@ -403,9 +410,26 @@
 		"setenv bootargs ${bootargs} " \
 		"root=/dev/nfs ${mtdparts} " \
 		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
-		"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+		"ip=${ipaddr}:${serverip}:" \
 		"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
-	"nand_boot=echo Booting from nand, active set ${active_set} ...; " \
+	"nand_boot=echo Booting from nand; " \
+		"if test ${upgrade_available} -eq 1; then " \
+			"if test ${bootcount} -gt ${bootlimit}; " \
+				"then " \
+				"setenv upgrade_available 0;" \
+				"setenv ${partitionset_active} true;" \
+				"if test -n ${A}; then " \
+					"setenv partitionset_active B; " \
+					"env delete A; " \
+				"fi;" \
+				"if test -n ${B}; then " \
+					"setenv partitionset_active A; " \
+					"env delete B; " \
+				"fi;" \
+				"saveenv; " \
+			"fi;" \
+		"fi;" \
+		"echo set ${partitionset_active}...;" \
 		"run nand_args; " \
 		"nand read.i ${kloadaddr} ${nand_src_addr} " \
 		"${nand_img_size}; bootm ${kloadaddr}\0" \
@@ -414,7 +438,7 @@
 		"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
 		"bootm ${kloadaddr}\0" \
 	"flash_self=run nand_boot\0" \
-	"flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \
+	"flash_self_test=setenv testargs test; " \
 		"run nand_boot\0" \
 	"dfu_start=echo Preparing for dfu mode ...; " \
 		"run dfu_args; \0" \
@@ -425,8 +449,9 @@
 		"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
 		"from memory and root filesystem over NFS; echo Type " \
 		"'run net_nfs' to get Kernel over TFTP and mount root " \
-		"filesystem over NFS; echo Set active_set variable to 'a' " \
-		"or 'b' to select kernel and rootfs partition; " \
+		"filesystem over NFS; " \
+		"echo Set partitionset_active variable to 'A' " \
+		"or 'B' to select kernel and rootfs partition; " \
 		"echo" \
 		"\0"
 
@@ -457,4 +482,15 @@
 #define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, "		\
 				"press \"<Esc><Esc>\" to stop\n", bootdelay
 
+/* Reboot after 60 sec if bootcmd fails */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME 60
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV
+
+/* Enable Device-Tree (FDT) support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_FDT
+
 #endif	/* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 5436bae15e..94a65c4d01 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -59,6 +59,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_TFTP_PORT
 #define CONFIG_TFTP_TSIZE
 
@@ -74,7 +75,6 @@
 #define CONFIG_USB_STORAGE
 
 /* GPIOs and IO expander */
-#define CONFIG_AT91_LEGACY
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_AT91_GPIO
 #define CONFIG_AT91_GPIO_PULLUP		1
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
index 248e657e4c..51339b1496 100644
--- a/include/configs/stamp9g20.h
+++ b/include/configs/stamp9g20.h
@@ -145,6 +145,7 @@
 #ifdef CONFIG_MACB
 # define CONFIG_RMII			/* use reduced MII inteface */
 # define CONFIG_NET_RETRY_COUNT	20      /* # of DHCP/BOOTP retries */
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* BOOTP and DHCP options */
 # define CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
new file mode 100644
index 0000000000..c98002317f
--- /dev/null
+++ b/include/configs/taurus.h
@@ -0,0 +1,160 @@
+/*
+ * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9260ek.h
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#define MACH_TYPE_TAURUS		2067
+#define MACH_TYPE_AXM			2068
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+#define CONFIG_SYS_HZ			1000
+
+/* Misc CPU related */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#endif
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#if defined(CONFIG_BOARD_TAURUS)
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+/* bootstrap in spi flash , u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE \
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 10fe47f4d6..4364eef7ba 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #include <asm/arch/omap.h>
 
@@ -42,9 +43,9 @@
 
 /*
  * RTC related defines. To use bootcount you must set bootlimit in the
- * environment to a non-zero value.
+ * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
+ * in the board config.
  */
-#define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
 
 /* Enable the HW watchdog, since we can use this with bootcount */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index f163303142..08771422ec 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -299,6 +299,7 @@
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_USB_CABLE_CHECK
 
 /* LCD */
 #define CONFIG_EXYNOS_FB
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 3bcdfb140c..5d86a3d4e3 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -20,8 +20,6 @@
 #define CONFIG_EXYNOS4		/* which is in a EXYNOS4XXX */
 #define CONFIG_TIZEN		/* TIZEN lib */
 
-#define PLATFORM_NO_UNALIGNED
-
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 
 #define CONFIG_ARCH_CPU_INIT
@@ -65,10 +63,9 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (2 << 20))
+#include <asm/sizes.h>
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
 #define CONFIG_SERIAL2
@@ -100,6 +97,7 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
 #define CONFIG_CMD_GPT
 #define CONFIG_CMD_PMIC
 
@@ -113,6 +111,23 @@
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
 /* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
 #undef CONFIG_CMD_NET
 
@@ -136,25 +151,29 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /* Tizen - partitions definitions */
-#define PARTS_CSA		"csa-mmc"
-#define PARTS_BOOTLOADER	"u-boot"
+#define PARTS_CSA		"csa"
 #define PARTS_BOOT		"boot"
+#define PARTS_MODEM		"modem"
+#define PARTS_CSC		"csc"
 #define PARTS_ROOT		"platform"
 #define PARTS_DATA		"data"
-#define PARTS_CSC		"csc"
 #define PARTS_UMS		"ums"
 
 #define PARTS_DEFAULT \
-	"uuid_disk=${uuid_gpt_disk};" \
-	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
-	"name="PARTS_BOOTLOADER",size=60MiB," \
-		"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
-	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
-	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
-	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \
 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 
+#define CONFIG_DFU_ALT \
+	"u-boot mmc 80 800;" \
+	"uImage ext4 0 2;" \
+	"exynos4412-trats2.dtb ext4 0 2;" \
+	""PARTS_ROOT" part 0 5\0"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
 		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
@@ -178,15 +197,16 @@
 	"rootfstype=ext4\0" \
 	"console=" CONFIG_DEFAULT_CONSOLE \
 	"kernelname=uImage\0" \
-	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
-		"0x40007FC0 ${kernelname}\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
+		"${kernelname}\0" \
 	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
 		"${fdtfile}\0" \
-	"mmcdev=0\0" \
+	"mmcdev=CONFIG_MMC_DEFAULT_DEV\0" \
 	"mmcbootpart=2\0" \
 	"mmcrootpart=5\0" \
 	"opts=always_resume=1\0" \
 	"partitions=" PARTS_DEFAULT \
+	"dfu_alt_info=" CONFIG_DFU_ALT \
 	"uartpath=ap\0" \
 	"usbpath=ap\0" \
 	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
@@ -233,8 +253,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_LOAD_ADDR \
 					- GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_HZ			1000
-
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
@@ -288,6 +306,11 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_POWER_MUIC_MAX77693
 #define CONFIG_POWER_FG_MAX77693
 #define CONFIG_POWER_BATTERY_TRATS2
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_USB_CABLE_CHECK
 
 /* LCD */
 #define CONFIG_EXYNOS_FB
@@ -300,6 +323,9 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
 
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT    1
 
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
new file mode 100644
index 0000000000..c4d04dec38
--- /dev/null
+++ b/include/configs/usb_a9263.h
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Settings for Calao USB-A9263 board
+ *
+ * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap
+ * installed on board will not be able to load it properly.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_USB_A9263
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
+#define AT91_SPI_CLK				8000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+#define MTDPARTS_DEFAULT \
+	"mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000)
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+				 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_BOOTCOMMAND	"nboot 21000000 0"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+	"root=/dev/mtdblock1 " \
+	"mtdparts=" MTDPARTS_DEFAULT " " \
+	"rw rootfstype=jffs2"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 6da5e8f5db..7e78f8ac8f 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -132,7 +132,7 @@
 #define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
 
 #define CONFIG_SYS_TIMER_RATE		1000000
-#define CONFIG_SYS_TIMER_COUNTER	(0x10011000 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 
 /* SMSC9115 Ethernet from SMSC9118 family */
diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h
index 1489080041..88aaa95fb1 100644
--- a/include/configs/vl_ma2sc.h
+++ b/include/configs/vl_ma2sc.h
@@ -320,8 +320,8 @@
 #define CONFIG_SYS_NAND_DBW_8		1
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)	/* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)	/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 0
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(0)
 #define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
@@ -330,6 +330,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT		5
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 
diff --git a/include/i2c.h b/include/i2c.h
index c1be533d57..f93a18366e 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -147,7 +147,7 @@ extern struct i2c_bus_hose	i2c_bus[];
 
 # elif (defined(CONFIG_AT91RM9200) || \
 	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
+	defined(CONFIG_AT91SAM9263))
 #  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
 # else
 #  define I2C_SOFT_DECLARATIONS
diff --git a/include/twl6030.h b/include/twl6030.h
index b4035ba4fe..7898699eac 100644
--- a/include/twl6030.h
+++ b/include/twl6030.h
@@ -110,9 +110,47 @@
 #define CTRL_P2_EOCP2	(1 << 1)
 #define CTRL_P2_BUSY	(1 << 0)
 
+#define TWL6032_CTRL_P1	0x36
+#define CTRL_P1_SP1	(1 << 3)
+
 #define GPCH0_LSB	0x57
 #define GPCH0_MSB	0x58
 
+#define TWL6032_GPCH0_LSB	0x3b
+
+#define TWL6032_GPSELECT_ISB	0x35
+
+#define USB_PRODUCT_ID_LSB	0x02
+
+#define TWL6030_GPADC_VBAT_CHNL	0x07
+#define TWL6032_GPADC_VBAT_CHNL	0x12
+
+#define TWL6030_GPADC_CTRL	0x2e
+#define TWL6032_GPADC_CTRL2	0x2f
+#define GPADC_CTRL2_CH18_SCALER_EN	(1 << 2)
+#define GPADC_CTRL_SCALER_DIV4		(1 << 3)
+
+#define TWL6030_VBAT_MULT	40 * 1000
+#define TWL6032_VBAT_MULT	25 * 1000
+
+#define TWL6030_VBAT_SHIFT	(10 + 3)
+#define TWL6032_VBAT_SHIFT	(12 + 2)
+
+enum twl603x_chip_type{
+	chip_TWL6030,
+	chip_TWL6032,
+	chip_TWL603X_cnt
+};
+
+struct twl6030_data{
+	u8 chip_type;
+	u8 adc_rbase;
+	u8 adc_ctrl;
+	u8 adc_enable;
+	int vbat_mult;
+	int vbat_shift;
+};
+
 /* Functions to read and write from TWL6030 */
 static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
 {