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authorSimon Glass <sjg@chromium.org>2015-07-27 15:47:26 -0600
committerSimon Glass <sjg@chromium.org>2015-08-05 08:42:42 -0600
commit7fd078cb8c4c132aff0ba5c9029bf7055ca9ea99 (patch)
treefac8f807fd0fe1a5cc8c5398cd4b3ce978ca94fa /doc/device-tree-bindings
parent1f2be4cea4a29b3c62f7ae3ae16a4edb6e09c4b8 (diff)
downloadblackbird-obmc-uboot-7fd078cb8c4c132aff0ba5c9029bf7055ca9ea99.tar.gz
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x86: dts: Fix typo in intel,irq-router.txt
Fix a small typo in this binding file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'doc/device-tree-bindings')
-rw-r--r--doc/device-tree-bindings/misc/intel,irq-router.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
index 598b4b1c2f..e4d8ead2ee 100644
--- a/doc/device-tree-bindings/misc/intel,irq-router.txt
+++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
@@ -17,8 +17,8 @@ Required properties :
- intel,pirq-link : Specifies the PIRQ link information with two cells. The
first cell is the register offset that controls the first PIRQ link routing.
The second cell is the total number of PIRQ links the router supports.
-- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC.
- Bit N is 1 means IRQ N is available to be routed.
+- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
+ 8259 PIC. Bit N is 1 means IRQ N is available to be routed.
- intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
encoded as 3 cells a group for a device. The first cell is the device's PCI
bus number, device number and function number encoding with PCI_BDF() macro.
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