spi: Fix zynq SPI binding

Zynq is using Cadence IP where binding is documented in the Linux kernel
and there is no reason to use different binding.
Synchronize it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

1 files changed, 19 insertions, 16 deletions

diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt
index f397a36d68..cb2945789d 100644
--- a/doc/device-tree-bindings/spi/spi-zynq.txt
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -1,29 +1,32 @@
-Zynq SPI controller Device Tree Bindings
-----------------------------------------
+Cadence SPI controller Device Tree Bindings
+-------------------------------------------
 
 Required properties:
-- compatible		: Should be "xlnx,spi-zynq".
+- compatible		: Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
 - reg			: Physical base address and size of SPI registers map.
-- status		: Status will be disabled in dtsi and enabled in required dts.
-- interrupt-parent	: Must be core interrupt controller.
 - interrupts		: Property with a value describing the interrupt
 			  number.
-- clocks		: Clock phandles (see clock bindings for details).
+- interrupt-parent	: Must be core interrupt controller
 - clock-names		: List of input clock names - "ref_clk", "pclk"
 			  (See clock bindings for details).
+- clocks		: Clock phandles (see clock bindings for details).
 - spi-max-frequency	: Maximum SPI clocking speed of device in Hz
 
+Optional properties:
+- num-cs		: Number of chip selects used.
+			  If a decoder is used, this will be the number of
+			  chip selects after the decoder.
+- is-decoded-cs		: Flag to indicate whether decoder is used or not.
+
 Example:
 
-	spi@e0006000 {
-		compatible = "xlnx,zynq-spi";
-		reg = <0xe0006000 0x1000>;
-		status = "disabled";
-		interrupt-parent = <&intc>;
-		interrupts = <0 26 4>;
-		clocks = <&clkc 25>, <&clkc 34>;
+	spi@e0007000 {
+		compatible = "xlnx,zynq-spi-r1p6";
 		clock-names = "ref_clk", "pclk";
-		spi-max-frequency = <166666700>;
-		#address-cells = <1>;
-		#size-cells = <0>;
+		clocks = <&clkc 26>, <&clkc 35>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 49 4>;
+		num-cs = <4>;
+		is-decoded-cs = <0>;
+		reg = <0xe0007000 0x1000>;
 	} ;