Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx

3 files changed, 10 insertions, 95 deletions

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index b5bb145808..6260b016df 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -277,87 +277,6 @@ int board_early_init_f(void)
 	return 0;
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-/*----------------------------------------------------------------------------+
-  | nand_reset.
-  |   Reset Nand flash
-  |   This routine will abort previous cmd
-  +----------------------------------------------------------------------------*/
-int nand_reset(ulong addr)
-{
-	int wait=0, stat=0;
-
-	out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
-	out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
-
-	while ((stat != 0xc0) && (wait != 0xffff)) {
-		stat = in8(addr + NAND_DATA_REG);
-		wait++;
-	}
-
-	if (stat == 0xc0) {
-		return 0;
-	} else {
-		printf("NAND Reset timeout.\n");
-		return -1;
-	}
-}
-
-void board_nand_set_device(int cs, ulong addr)
-{
-	/* Set NandFlash Core Configuration Register */
-	out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
-
-	switch (cs) {
-	case 1:
-		/* -------
-		 *  NAND0
-		 * -------
-		 * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
-		 * Set NDF1CR - Enable External CS1 in NAND FLASH controller
-		 */
-		out32(addr + NAND_CR1_REG, 0x80002222);
-		break;
-
-	case 2:
-		/* -------
-		 *  NAND1
-		 * -------
-		 * K9K2G0B : 5 addr cyc, 2 col + 3 Row
-		 * Set NDF2CR : Enable External CS2 in NAND FLASH controller
-		 */
-		out32(addr + NAND_CR2_REG, 0xC0007777);
-		break;
-	}
-
-	/* Perform Reset Command */
-	if (nand_reset(addr) != 0)
-		return;
-}
-
-void nand_init(void)
-{
-	board_nand_set_device(1, CFG_NAND_ADDR);
-
-	nand_probe(CFG_NAND_ADDR);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-
-#if 0 /* NAND1 not supported yet */
-	board_nand_set_device(2, CFG_NAND2_ADDR);
-
-	nand_probe(CFG_NAND2_ADDR);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-#endif
-}
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
 int checkboard(void)
 {
 	char *s = getenv("serial#");
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
index 176900ec2f..f6d7183199 100644
--- a/board/amcc/bamboo/u-boot.lds
+++ b/board/amcc/bamboo/u-boot.lds
@@ -68,19 +68,7 @@ SECTIONS
 
     cpu/ppc4xx/start.o	(.text)
     board/amcc/bamboo/init.o	(.text)
-    cpu/ppc4xx/kgdb.o	(.text)
-    cpu/ppc4xx/traps.o	(.text)
-    cpu/ppc4xx/interrupts.o	(.text)
-    cpu/ppc4xx/serial.o	(.text)
-    cpu/ppc4xx/cpu_init.o	(.text)
-    cpu/ppc4xx/speed.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib_generic/crc32.o		(.text)
-    lib_ppc/extable.o	(.text)
-    lib_generic/zlib.o		(.text)
-
-/*    . = env_offset;*/
-/*    common/environment.o(.text)*/
+    board/amcc/bamboo/bamboo.o	(.text)
 
     *(.text)
     *(.fixup)
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index f8b837ed28..d045df1872 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
 }
 #endif /* CONFIG_DDR_DATA_EYE */
 
+#if defined(CONFIG_NAND_SPL)
+/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val)	133000000
+#endif
+
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -404,7 +412,7 @@ long int initdram (int board_type)
 	mtsdram(DDR0_22, 0x00267F0B);
 	mtsdram(DDR0_23, 0x00000000);
 	mtsdram(DDR0_24, 0x01010002);
-	if (speed > 133333333)
+	if (speed > 133333334)
 		mtsdram(DDR0_26, 0x5B26050C);
 	else
 		mtsdram(DDR0_26, 0x5B260408);