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authorWolfgang Denk <wd@denx.de>2008-07-11 22:56:11 +0200
committerWolfgang Denk <wd@denx.de>2008-07-11 22:56:11 +0200
commitbde63587622c4b830a27d1ddf7265843de9e994f (patch)
tree17ad533148bc822a5c97a6297b30849e657e9e9a /board
parent184f1b404a90eef8b425c0e7b3018d59ef9982c8 (diff)
downloadblackbird-obmc-uboot-bde63587622c4b830a27d1ddf7265843de9e994f.tar.gz
blackbird-obmc-uboot-bde63587622c4b830a27d1ddf7265843de9e994f.zip
Fix some more printf() format issues.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board')
-rw-r--r--board/amcc/taishan/showinfo.c110
-rw-r--r--board/freescale/mpc7448hpc2/tsi108_init.c8
-rw-r--r--board/netstal/hcu5/sdram.c2
-rw-r--r--board/sandburst/metrobox/metrobox.c2
4 files changed, 61 insertions, 61 deletions
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
index 040b8004da..5b8b88e856 100644
--- a/board/amcc/taishan/showinfo.c
+++ b/board/amcc/taishan/showinfo.c
@@ -34,59 +34,59 @@ void show_reset_reg(void)
/* read clock regsiter */
printf("===== Display reset and initialize register Start =========\n");
mfcpr(clk_pllc,reg);
- printf("cpr_pllc = %#010x\n",reg);
+ printf("cpr_pllc = %#010lx\n",reg);
mfcpr(clk_plld,reg);
- printf("cpr_plld = %#010x\n",reg);
+ printf("cpr_plld = %#010lx\n",reg);
mfcpr(clk_primad,reg);
- printf("cpr_primad = %#010x\n",reg);
+ printf("cpr_primad = %#010lx\n",reg);
mfcpr(clk_primbd,reg);
- printf("cpr_primbd = %#010x\n",reg);
+ printf("cpr_primbd = %#010lx\n",reg);
mfcpr(clk_opbd,reg);
- printf("cpr_opbd = %#010x\n",reg);
+ printf("cpr_opbd = %#010lx\n",reg);
mfcpr(clk_perd,reg);
- printf("cpr_perd = %#010x\n",reg);
+ printf("cpr_perd = %#010lx\n",reg);
mfcpr(clk_mald,reg);
- printf("cpr_mald = %#010x\n",reg);
+ printf("cpr_mald = %#010lx\n",reg);
/* read sdr register */
mfsdr(sdr_ebc,reg);
- printf("sdr_ebc = %#010x\n",reg);
+ printf("sdr_ebc = %#010lx\n",reg);
mfsdr(sdr_cp440,reg);
- printf("sdr_cp440 = %#010x\n",reg);
+ printf("sdr_cp440 = %#010lx\n",reg);
mfsdr(sdr_xcr,reg);
- printf("sdr_xcr = %#010x\n",reg);
+ printf("sdr_xcr = %#010lx\n",reg);
mfsdr(sdr_xpllc,reg);
- printf("sdr_xpllc = %#010x\n",reg);
+ printf("sdr_xpllc = %#010lx\n",reg);
mfsdr(sdr_xplld,reg);
- printf("sdr_xplld = %#010x\n",reg);
+ printf("sdr_xplld = %#010lx\n",reg);
mfsdr(sdr_pfc0,reg);
- printf("sdr_pfc0 = %#010x\n",reg);
+ printf("sdr_pfc0 = %#010lx\n",reg);
mfsdr(sdr_pfc1,reg);
- printf("sdr_pfc1 = %#010x\n",reg);
+ printf("sdr_pfc1 = %#010lx\n",reg);
mfsdr(sdr_cust0,reg);
- printf("sdr_cust0 = %#010x\n",reg);
+ printf("sdr_cust0 = %#010lx\n",reg);
mfsdr(sdr_cust1,reg);
- printf("sdr_cust1 = %#010x\n",reg);
+ printf("sdr_cust1 = %#010lx\n",reg);
mfsdr(sdr_uart0,reg);
- printf("sdr_uart0 = %#010x\n",reg);
+ printf("sdr_uart0 = %#010lx\n",reg);
mfsdr(sdr_uart1,reg);
- printf("sdr_uart1 = %#010x\n",reg);
+ printf("sdr_uart1 = %#010lx\n",reg);
printf("===== Display reset and initialize register End =========\n");
}
@@ -97,13 +97,13 @@ void show_xbridge_info(void)
printf("PCI-X chip control registers\n");
mfsdr(sdr_xcr, reg);
- printf("sdr_xcr = %#010x\n", reg);
+ printf("sdr_xcr = %#010lx\n", reg);
mfsdr(sdr_xpllc, reg);
- printf("sdr_xpllc = %#010x\n", reg);
+ printf("sdr_xpllc = %#010lx\n", reg);
mfsdr(sdr_xplld, reg);
- printf("sdr_xplld = %#010x\n", reg);
+ printf("sdr_xplld = %#010lx\n", reg);
printf("PCI-X Bridge Configure registers\n");
printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
@@ -116,49 +116,49 @@ void show_xbridge_info(void)
printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
- printf("PCIX0_BAR0 = %#010x\n", in32r(PCIX0_BAR0));
- printf("PCIX0_BAR1 = %#010x\n", in32r(PCIX0_BAR1));
- printf("PCIX0_BAR2 = %#010x\n", in32r(PCIX0_BAR2));
- printf("PCIX0_BAR3 = %#010x\n", in32r(PCIX0_BAR3));
- printf("PCIX0_BAR4 = %#010x\n", in32r(PCIX0_BAR4));
- printf("PCIX0_BAR5 = %#010x\n", in32r(PCIX0_BAR5));
+ printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0));
+ printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1));
+ printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2));
+ printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3));
+ printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4));
+ printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5));
- printf("PCIX0_CISPTR = %#010x\n", in32r(PCIX0_CISPTR));
+ printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR));
printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
- printf("PCIX0_EROMBA = %#010x\n", in32r(PCIX0_EROMBA));
+ printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA));
printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
- printf("PCIX0_BRDGOPT1 = %#010x\n", in32r(PCIX0_BRDGOPT1));
- printf("PCIX0_BRDGOPT2 = %#010x\n", in32r(PCIX0_BRDGOPT2));
-
- printf("PCIX0_POM0LAL = %#010x\n", in32r(PCIX0_POM0LAL));
- printf("PCIX0_POM0LAH = %#010x\n", in32r(PCIX0_POM0LAH));
- printf("PCIX0_POM0SA = %#010x\n", in32r(PCIX0_POM0SA));
- printf("PCIX0_POM0PCILAL = %#010x\n", in32r(PCIX0_POM0PCIAL));
- printf("PCIX0_POM0PCILAH = %#010x\n", in32r(PCIX0_POM0PCIAH));
- printf("PCIX0_POM1LAL = %#010x\n", in32r(PCIX0_POM1LAL));
- printf("PCIX0_POM1LAH = %#010x\n", in32r(PCIX0_POM1LAH));
- printf("PCIX0_POM1SA = %#010x\n", in32r(PCIX0_POM1SA));
- printf("PCIX0_POM1PCILAL = %#010x\n", in32r(PCIX0_POM1PCIAL));
- printf("PCIX0_POM1PCILAH = %#010x\n", in32r(PCIX0_POM1PCIAH));
- printf("PCIX0_POM2SA = %#010x\n", in32r(PCIX0_POM2SA));
-
- printf("PCIX0_PIM0SA = %#010x\n", in32r(PCIX0_PIM0SA));
- printf("PCIX0_PIM0LAL = %#010x\n", in32r(PCIX0_PIM0LAL));
- printf("PCIX0_PIM0LAH = %#010x\n", in32r(PCIX0_PIM0LAH));
- printf("PCIX0_PIM1SA = %#010x\n", in32r(PCIX0_PIM1SA));
- printf("PCIX0_PIM1LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
- printf("PCIX0_PIM1LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
- printf("PCIX0_PIM2SA = %#010x\n", in32r(PCIX0_PIM1SA));
- printf("PCIX0_PIM2LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
- printf("PCIX0_PIM2LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
-
- printf("PCIX0_XSTS = %#010x\n", in32r(PCIX0_STS));
+ printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1));
+ printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2));
+
+ printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL));
+ printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH));
+ printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA));
+ printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL));
+ printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH));
+ printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL));
+ printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH));
+ printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA));
+ printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL));
+ printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH));
+ printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA));
+
+ printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA));
+ printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL));
+ printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH));
+ printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA));
+ printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
+ printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
+ printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA));
+ printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL));
+ printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH));
+
+ printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS));
}
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
index efa952c2e7..ad80694077 100644
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ b/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -165,8 +165,8 @@ int board_early_init_f (void)
printf ("Invalid DDR2 clock setting\n");
return -1;
}
- printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
- printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
+ printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
+ printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
return 0;
}
@@ -622,8 +622,8 @@ int misc_init_r (void)
#ifdef CFG_L2
l2cache_enable ();
#endif
- printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
- printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
+ printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000);
+ printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
/*
* All the information needed to print the cache details is avaiblable
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 80e84aebb8..66a958c78a 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -71,7 +71,7 @@ void board_add_ram_info(int use_default)
}
get_sys_info(&board_cfg);
- printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+ printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
mfsdram(DDR0_03, val);
val = DDR0_03_CASLAT_DECODE(val);
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 97049013e1..66cdfb1562 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -270,7 +270,7 @@ int checkboard (void)
}
printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
- printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, (char *)board_id_as[brd_id]);
+ printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
/* Fix the ack in the bme 32 */
udelay(5000);
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