ARM: tegra: Tegra20 pinmux cleanup

This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

7 files changed, 33 insertions, 33 deletions

diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 177d185ea8..9c8677943a 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -37,8 +37,8 @@ void pin_mux_mmc(void)
 {
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
 	/* for write-protect GPIO PI6 */
-	pinmux_tristate_disable(PINGRP_ATA);
+	pinmux_tristate_disable(PMUX_PINGRP_ATA);
 	/* for CD GPIO PH2 */
-	pinmux_tristate_disable(PINGRP_ATD);
+	pinmux_tristate_disable(PMUX_PINGRP_ATD);
 }
 #endif
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index d6e5c3740e..462ab05556 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -28,23 +28,23 @@
 void pin_mux_mmc(void)
 {
 	/* SDMMC4: config 3, x8 on 2nd set of pins */
-	pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
-	pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
-	pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
 
-	pinmux_tristate_disable(PINGRP_ATB);
-	pinmux_tristate_disable(PINGRP_GMA);
-	pinmux_tristate_disable(PINGRP_GME);
+	pinmux_tristate_disable(PMUX_PINGRP_ATB);
+	pinmux_tristate_disable(PMUX_PINGRP_GMA);
+	pinmux_tristate_disable(PMUX_PINGRP_GME);
 
 	/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
-	pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+	pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
 
-	pinmux_tristate_disable(PINGRP_SDIO1);
+	pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
 
 	/* For power GPIO PV1 */
-	pinmux_tristate_disable(PINGRP_UAC);
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
 	/* For CD GPIO PV5 */
-	pinmux_tristate_disable(PINGRP_GPV);
+	pinmux_tristate_disable(PMUX_PINGRP_GPV);
 }
 #endif
 
@@ -55,6 +55,6 @@ void pin_mux_display(void)
 	debug("init display pinmux\n");
 
 	/* EN_VDD_PANEL GPIO A4 */
-	pinmux_tristate_disable(PINGRP_DAP2);
+	pinmux_tristate_disable(PMUX_PINGRP_DAP2);
 }
 #endif
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index ef949303a6..723293fef3 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -20,7 +20,7 @@ void pin_mux_usb(void)
 	 * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
 	 * in the current device tree.
 	 */
-	pinmux_tristate_disable(PINGRP_UAC);
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
 }
 
 void pin_mux_spi(void)
@@ -38,5 +38,5 @@ void pin_mux_mmc(void)
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
 
 	/* For CD GPIO PP1 */
-	pinmux_tristate_disable(PINGRP_DAP3);
+	pinmux_tristate_disable(PMUX_PINGRP_DAP3);
 }
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index b74c219347..c892a25751 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -25,28 +25,28 @@ void pin_mux_mmc(void)
 	funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
 
 	/* For power GPIO PI6 */
-	pinmux_tristate_disable(PINGRP_ATA);
+	pinmux_tristate_disable(PMUX_PINGRP_ATA);
 	/* For CD GPIO PH2 */
-	pinmux_tristate_disable(PINGRP_ATD);
+	pinmux_tristate_disable(PMUX_PINGRP_ATD);
 
 	/* For power GPIO PT3 */
-	pinmux_tristate_disable(PINGRP_DTB);
+	pinmux_tristate_disable(PMUX_PINGRP_DTB);
 	/* For CD GPIO PI5 */
-	pinmux_tristate_disable(PINGRP_ATC);
+	pinmux_tristate_disable(PMUX_PINGRP_ATC);
 }
 #endif
 
 void pin_mux_usb(void)
 {
 	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
-	pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
-	pinmux_tristate_disable(PINGRP_CDEV2);
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
 	/* USB2 PHY reset GPIO */
-	pinmux_tristate_disable(PINGRP_UAC);
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
 }
 
 void pin_mux_display(void)
 {
-	pinmux_set_func(PINGRP_SDC, PMUX_FUNC_PWM);
-	pinmux_tristate_disable(PINGRP_SDC);
+	pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
+	pinmux_tristate_disable(PMUX_PINGRP_SDC);
 }
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index ef4e481c75..ce2db40f9e 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -37,14 +37,14 @@ void pin_mux_mmc(void)
 	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
 
 	/* For power GPIO PI6 */
-	pinmux_tristate_disable(PINGRP_ATA);
+	pinmux_tristate_disable(PMUX_PINGRP_ATA);
 	/* For CD GPIO PI5 */
-	pinmux_tristate_disable(PINGRP_ATC);
+	pinmux_tristate_disable(PMUX_PINGRP_ATC);
 }
 #endif
 
 void pin_mux_usb(void)
 {
 	/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
-	pinmux_tristate_disable(PINGRP_SLXK);
+	pinmux_tristate_disable(PMUX_PINGRP_SLXK);
 }
diff --git a/board/toradex/colibri_t20-common/colibri_t20-common.c b/board/toradex/colibri_t20-common/colibri_t20-common.c
index 823d0de5e4..58a9916f0a 100644
--- a/board/toradex/colibri_t20-common/colibri_t20-common.c
+++ b/board/toradex/colibri_t20-common/colibri_t20-common.c
@@ -18,12 +18,12 @@ void colibri_t20_common_pin_mux_usb(void)
 	/* module internal USB bus to connect ethernet chipset */
 	funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
 	/* ULPI reference clock output */
-	pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
-	pinmux_tristate_disable(PINGRP_CDEV2);
+	pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
+	pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
 	/* PHY reset GPIO */
-	pinmux_tristate_disable(PINGRP_UAC);
+	pinmux_tristate_disable(PMUX_PINGRP_UAC);
 	/* VBus GPIO */
-	pinmux_tristate_disable(PINGRP_DTE);
+	pinmux_tristate_disable(PMUX_PINGRP_DTE);
 }
 #endif
 
diff --git a/board/toradex/colibri_t20_iris/colibri_t20_iris.c b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
index f5f0475b89..49c74f34f1 100644
--- a/board/toradex/colibri_t20_iris/colibri_t20_iris.c
+++ b/board/toradex/colibri_t20_iris/colibri_t20_iris.c
@@ -19,7 +19,7 @@ void pin_mux_usb(void)
 	colibri_t20_common_pin_mux_usb();
 
 	/* USB 1 aka Tegra USB port 3 VBus*/
-	pinmux_tristate_disable(PINGRP_SPIG);
+	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
 }
 #endif
 
@@ -31,6 +31,6 @@ void pin_mux_usb(void)
 void pin_mux_mmc(void)
 {
 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
-	pinmux_tristate_disable(PINGRP_GMB);
+	pinmux_tristate_disable(PMUX_PINGRP_GMB);
 }
 #endif