path: root/board
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authorBenoît Thébaudeau <>2012-08-08 03:55:32 +0000
committerStefano Babic <>2012-09-23 19:57:13 +0200
commit5527024fdb10798d2975197f287457b29e2d4084 (patch)
tree2255a6b8aab740717826f9b28462fdb8baa82529 /board
parent362635bd50e386770ebaa2d5d090eb8cbf96430b (diff)
KARO TX25: Fix NAND Flash R/W cycle times
The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. Signed-off-by: Benoît Thébaudeau <> Cc: John Rigby <> Cc: Scott Wood <> Cc: Stefano Babic <> Cc: Daniel Gachet <> Acked-by: Stefano Babic <>
Diffstat (limited to 'board')
1 files changed, 8 insertions, 0 deletions
diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
index 823df10701..eb3f187806 100644
--- a/board/karo/tx25/lowlevel_init.S
+++ b/board/karo/tx25/lowlevel_init.S
@@ -67,6 +67,14 @@
write32 0x53f80008, 0x20034000
+ * PCDR2: NFC = 33.25 MHz
+ * This is required for the NAND Flash of this board, which is a Samsung
+ * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+ * the NFC driver in symmetric (i.e. one-cycle) mode.
+ */
+ write32 0x53f80020, 0x01010103
+ /*
* enable all implemented clocks in all three
* clock control registers
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