Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next

18 files changed, 151 insertions, 119 deletions

diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c
index 3ea20a6109..8ae2ec69ce 100644
--- a/board/BuS/EB+MCF-EV123/mii.c
+++ b/board/BuS/EB+MCF-EV123/mii.c
@@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index d5cee64bde..8452054e68 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <mpc512x.h>
+#include "iopin.h"
 #include <asm/bitops.h>
 #include <command.h>
 #include <fdt_support.h>
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c
index 87cf0cbbe9..26628d3eb5 100644
--- a/board/ads5121/ads5121_diu.c
+++ b/board/ads5121/ads5121_diu.c
@@ -57,7 +57,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
 	/* Modify PXCLK in GUTS CLKDVDR */
 	debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
 	temp = *clkdvdr & 0xFFFFFF00;
-	*clkdvdr = temp | (pixval & 0x1F);
+	*clkdvdr = temp | (pixval & 0xFF);
 	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
 }
 
diff --git a/board/ads5121/iopin.c b/board/ads5121/iopin.c
index 6a35c8154d..a6792a0e27 100644
--- a/board/ads5121/iopin.c
+++ b/board/ads5121/iopin.c
@@ -25,71 +25,90 @@
 #include <linux/types.h>
 #include "iopin.h"
 
-/*
- * IO PAD TYPES
- *	for all types   fmux is used to select the funtion
- *			ds sets the slew rate
- *	STD pins  nothing extra (can set ds & fmux only)
- *	STD_PU	  pue=1 to enable pull & pud sets whether up or down resistors
- *	STD_ST	  st sets the Schmitt trigger
- *	STD_PU_ST pue & pud sets pull-up/down resistors as in STD_PU
- *		  st sets the Schmitt trigger
- *	PCI	  hold sets output delay
- *	PCI_ST	  hold sets output delay and st sets the Schmitt trigger
- */
+/* IO pin fields */
+#define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
+#define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
+#define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
+#define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
+#define IO_PIN_ST(v)	((v) << 2)	/* schmitt trigger */
+#define IO_PIN_DS(v)	((v))		/* slew rate */
 
 static struct iopin_t {
-	u_short p_offset; /* offset from IOCTL_MEM_OFFSET 		*/
-	u_short p_no;	  /* number of pins to set this way		*/
-	u_short bit_or:7; /* Do bitwise OR instead of setting		*/
-	u_short fmux:2;	  /* pad function select 0-3			*/
-	u_short hold:2;   /* PCI pad types only; 			*/
-	u_short pud:1; 	  /* pull resistor; PU types only;		*/
-			  /* if pue=1 then 0=pull-down, 1=pull-up	*/
-	u_short	pue:1;	  /* Pull resistor enable; _PU types only	*/
-	u_short st:1;	  /* Schmitt trigger enable; _ST types only	*/
-	u_short	ds:2;	  /* Slew rate class, 0=class1, ..., 3=class4	*/
+	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
+	int nr_pins;		/* number of pins to set this way */
+	int bit_or;		/* or in the value instead of overwrite */
+	u_long val;		/* value to write or or */
 } ioregs_init[] = {
-/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads 	*/
-	{IOCTL_SPDIF_TXCLK, 	3,  0, 1, 0, 0, 0, 0, 3},
-/* Set highest Slew on 9 PATA pins		*/
-	{IOCTL_PATA_CE1, 	9,  1, 0, 0, 0, 0, 0, 3},
-/* FUNC1=FEC_COL Sets Next 15 to FEC pads 	*/
-	{IOCTL_PSC0_0, 		15, 0, 1, 0, 0, 0, 0, 3},
-/* FUNC1=SPDIF_TXCLK				*/
-	{IOCTL_LPC_CS1, 	1,  0, 1, 0, 0, 0, 1, 3},
-/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX	*/
-	{IOCTL_I2C1_SCL, 	2,  0, 2, 0, 0, 0, 1, 3},
-/* FUNC2=DIU CLK				*/
-	{IOCTL_PSC6_0, 		1,  0, 2, 0, 0, 0, 1, 3},
-/* FUNC2=DIU_HSYNC 				*/
-	{IOCTL_PSC6_1, 		1,  0, 2, 0, 0, 0, 0, 3},
-/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads	*/
-	{IOCTL_PSC6_4, 		26, 0, 2, 0, 0, 0, 0, 3}
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		IOCTL_SPDIF_TXCLK, 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* Set highest Slew on 9 PATA pins */
+	{
+		IOCTL_PATA_CE1, 9, 1,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		IOCTL_PSC0_0, 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SPDIF_TXCLK */
+	{
+		IOCTL_LPC_CS1, 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+	{
+		IOCTL_I2C1_SCL, 2, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU CLK */
+	{
+		IOCTL_PSC6_0, 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		IOCTL_PSC6_1, 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		IOCTL_PSC6_4, 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
 };
 
 void iopin_initialize(void)
 {
 	short i, j, n, p;
 	u_long *reg;
+	immap_t *im = (immap_t *)CFG_IMMR;
+
+	reg = (u_long *)&(im->io_ctrl.regs[0]);
 
 	if (sizeof(ioregs_init) == 0)
 		return;
 
-	immap_t *im = (immap_t *)CFG_IMMR;
-	reg = (u_long *)&(im->io_ctrl.regs[0]);
 	n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
 
 	for (i = 0; i < n; i++) {
 		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
-			p < ioregs_init[i].p_no; p++, j++) {
-		/* lowest 9 bits sets the register */
+			p < ioregs_init[i].nr_pins; p++, j++) {
 			if (ioregs_init[i].bit_or)
-				reg[j] |= *((u_long *) &ioregs_init[i].p_no)
-						& 0x000001ff;
+				reg[j] |= ioregs_init[i].val;
 			else
-				reg[j] = *((u_long *) &ioregs_init[i].p_no)
-						& 0x000001ff;
+				reg[j] = ioregs_init[i].val;
 		}
 	}
 	return;
diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c
index 040b8004da..5b8b88e856 100644
--- a/board/amcc/taishan/showinfo.c
+++ b/board/amcc/taishan/showinfo.c
@@ -34,59 +34,59 @@ void show_reset_reg(void)
 	/* read clock regsiter */
 	printf("===== Display reset and initialize register Start =========\n");
 	mfcpr(clk_pllc,reg);
-	printf("cpr_pllc   = %#010x\n",reg);
+	printf("cpr_pllc   = %#010lx\n",reg);
 
 	mfcpr(clk_plld,reg);
-	printf("cpr_plld   = %#010x\n",reg);
+	printf("cpr_plld   = %#010lx\n",reg);
 
 	mfcpr(clk_primad,reg);
-	printf("cpr_primad = %#010x\n",reg);
+	printf("cpr_primad = %#010lx\n",reg);
 
 	mfcpr(clk_primbd,reg);
-	printf("cpr_primbd = %#010x\n",reg);
+	printf("cpr_primbd = %#010lx\n",reg);
 
 	mfcpr(clk_opbd,reg);
-	printf("cpr_opbd   = %#010x\n",reg);
+	printf("cpr_opbd   = %#010lx\n",reg);
 
 	mfcpr(clk_perd,reg);
-	printf("cpr_perd   = %#010x\n",reg);
+	printf("cpr_perd   = %#010lx\n",reg);
 
 	mfcpr(clk_mald,reg);
-	printf("cpr_mald   = %#010x\n",reg);
+	printf("cpr_mald   = %#010lx\n",reg);
 
 	/* read sdr register */
 	mfsdr(sdr_ebc,reg);
-	printf("sdr_ebc    = %#010x\n",reg);
+	printf("sdr_ebc    = %#010lx\n",reg);
 
 	mfsdr(sdr_cp440,reg);
-	printf("sdr_cp440  = %#010x\n",reg);
+	printf("sdr_cp440  = %#010lx\n",reg);
 
 	mfsdr(sdr_xcr,reg);
-	printf("sdr_xcr    = %#010x\n",reg);
+	printf("sdr_xcr    = %#010lx\n",reg);
 
 	mfsdr(sdr_xpllc,reg);
-	printf("sdr_xpllc  = %#010x\n",reg);
+	printf("sdr_xpllc  = %#010lx\n",reg);
 
 	mfsdr(sdr_xplld,reg);
-	printf("sdr_xplld  = %#010x\n",reg);
+	printf("sdr_xplld  = %#010lx\n",reg);
 
 	mfsdr(sdr_pfc0,reg);
-	printf("sdr_pfc0   = %#010x\n",reg);
+	printf("sdr_pfc0   = %#010lx\n",reg);
 
 	mfsdr(sdr_pfc1,reg);
-	printf("sdr_pfc1   = %#010x\n",reg);
+	printf("sdr_pfc1   = %#010lx\n",reg);
 
 	mfsdr(sdr_cust0,reg);
-	printf("sdr_cust0  = %#010x\n",reg);
+	printf("sdr_cust0  = %#010lx\n",reg);
 
 	mfsdr(sdr_cust1,reg);
-	printf("sdr_cust1  = %#010x\n",reg);
+	printf("sdr_cust1  = %#010lx\n",reg);
 
 	mfsdr(sdr_uart0,reg);
-	printf("sdr_uart0  = %#010x\n",reg);
+	printf("sdr_uart0  = %#010lx\n",reg);
 
 	mfsdr(sdr_uart1,reg);
-	printf("sdr_uart1  = %#010x\n",reg);
+	printf("sdr_uart1  = %#010lx\n",reg);
 
 	printf("===== Display reset and initialize register End   =========\n");
 }
@@ -97,13 +97,13 @@ void show_xbridge_info(void)
 
 	printf("PCI-X chip control registers\n");
 	mfsdr(sdr_xcr, reg);
-	printf("sdr_xcr    = %#010x\n", reg);
+	printf("sdr_xcr    = %#010lx\n", reg);
 
 	mfsdr(sdr_xpllc, reg);
-	printf("sdr_xpllc  = %#010x\n", reg);
+	printf("sdr_xpllc  = %#010lx\n", reg);
 
 	mfsdr(sdr_xplld, reg);
-	printf("sdr_xplld  = %#010x\n", reg);
+	printf("sdr_xplld  = %#010lx\n", reg);
 
 	printf("PCI-X Bridge Configure registers\n");
 	printf("PCIX0_VENDID            = %#06x\n", in16r(PCIX0_VENDID));
@@ -116,49 +116,49 @@ void show_xbridge_info(void)
 	printf("PCIX0_HDTYPE            = %#04x\n", in8(PCIX0_HDTYPE));
 	printf("PCIX0_BIST              = %#04x\n", in8(PCIX0_BIST));
 
-	printf("PCIX0_BAR0              = %#010x\n", in32r(PCIX0_BAR0));
-	printf("PCIX0_BAR1              = %#010x\n", in32r(PCIX0_BAR1));
-	printf("PCIX0_BAR2              = %#010x\n", in32r(PCIX0_BAR2));
-	printf("PCIX0_BAR3              = %#010x\n", in32r(PCIX0_BAR3));
-	printf("PCIX0_BAR4              = %#010x\n", in32r(PCIX0_BAR4));
-	printf("PCIX0_BAR5              = %#010x\n", in32r(PCIX0_BAR5));
+	printf("PCIX0_BAR0              = %#010lx\n", in32r(PCIX0_BAR0));
+	printf("PCIX0_BAR1              = %#010lx\n", in32r(PCIX0_BAR1));
+	printf("PCIX0_BAR2              = %#010lx\n", in32r(PCIX0_BAR2));
+	printf("PCIX0_BAR3              = %#010lx\n", in32r(PCIX0_BAR3));
+	printf("PCIX0_BAR4              = %#010lx\n", in32r(PCIX0_BAR4));
+	printf("PCIX0_BAR5              = %#010lx\n", in32r(PCIX0_BAR5));
 
-	printf("PCIX0_CISPTR            = %#010x\n", in32r(PCIX0_CISPTR));
+	printf("PCIX0_CISPTR            = %#010lx\n", in32r(PCIX0_CISPTR));
 	printf("PCIX0_SBSSYSVID         = %#010x\n", in16r(PCIX0_SBSYSVID));
 	printf("PCIX0_SBSSYSID          = %#010x\n", in16r(PCIX0_SBSYSID));
-	printf("PCIX0_EROMBA            = %#010x\n", in32r(PCIX0_EROMBA));
+	printf("PCIX0_EROMBA            = %#010lx\n", in32r(PCIX0_EROMBA));
 	printf("PCIX0_CAP               = %#04x\n", in8(PCIX0_CAP));
 	printf("PCIX0_INTLN             = %#04x\n", in8(PCIX0_INTLN));
 	printf("PCIX0_INTPN             = %#04x\n", in8(PCIX0_INTPN));
 	printf("PCIX0_MINGNT            = %#04x\n", in8(PCIX0_MINGNT));
 	printf("PCIX0_MAXLTNCY          = %#04x\n", in8(PCIX0_MAXLTNCY));
 
-	printf("PCIX0_BRDGOPT1          = %#010x\n", in32r(PCIX0_BRDGOPT1));
-	printf("PCIX0_BRDGOPT2          = %#010x\n", in32r(PCIX0_BRDGOPT2));
-
-	printf("PCIX0_POM0LAL           = %#010x\n", in32r(PCIX0_POM0LAL));
-	printf("PCIX0_POM0LAH           = %#010x\n", in32r(PCIX0_POM0LAH));
-	printf("PCIX0_POM0SA            = %#010x\n", in32r(PCIX0_POM0SA));
-	printf("PCIX0_POM0PCILAL        = %#010x\n", in32r(PCIX0_POM0PCIAL));
-	printf("PCIX0_POM0PCILAH        = %#010x\n", in32r(PCIX0_POM0PCIAH));
-	printf("PCIX0_POM1LAL           = %#010x\n", in32r(PCIX0_POM1LAL));
-	printf("PCIX0_POM1LAH           = %#010x\n", in32r(PCIX0_POM1LAH));
-	printf("PCIX0_POM1SA            = %#010x\n", in32r(PCIX0_POM1SA));
-	printf("PCIX0_POM1PCILAL        = %#010x\n", in32r(PCIX0_POM1PCIAL));
-	printf("PCIX0_POM1PCILAH        = %#010x\n", in32r(PCIX0_POM1PCIAH));
-	printf("PCIX0_POM2SA            = %#010x\n", in32r(PCIX0_POM2SA));
-
-	printf("PCIX0_PIM0SA            = %#010x\n", in32r(PCIX0_PIM0SA));
-	printf("PCIX0_PIM0LAL           = %#010x\n", in32r(PCIX0_PIM0LAL));
-	printf("PCIX0_PIM0LAH           = %#010x\n", in32r(PCIX0_PIM0LAH));
-	printf("PCIX0_PIM1SA            = %#010x\n", in32r(PCIX0_PIM1SA));
-	printf("PCIX0_PIM1LAL           = %#010x\n", in32r(PCIX0_PIM1LAL));
-	printf("PCIX0_PIM1LAH           = %#010x\n", in32r(PCIX0_PIM1LAH));
-	printf("PCIX0_PIM2SA            = %#010x\n", in32r(PCIX0_PIM1SA));
-	printf("PCIX0_PIM2LAL           = %#010x\n", in32r(PCIX0_PIM1LAL));
-	printf("PCIX0_PIM2LAH           = %#010x\n", in32r(PCIX0_PIM1LAH));
-
-	printf("PCIX0_XSTS              = %#010x\n", in32r(PCIX0_STS));
+	printf("PCIX0_BRDGOPT1          = %#010lx\n", in32r(PCIX0_BRDGOPT1));
+	printf("PCIX0_BRDGOPT2          = %#010lx\n", in32r(PCIX0_BRDGOPT2));
+
+	printf("PCIX0_POM0LAL           = %#010lx\n", in32r(PCIX0_POM0LAL));
+	printf("PCIX0_POM0LAH           = %#010lx\n", in32r(PCIX0_POM0LAH));
+	printf("PCIX0_POM0SA            = %#010lx\n", in32r(PCIX0_POM0SA));
+	printf("PCIX0_POM0PCILAL        = %#010lx\n", in32r(PCIX0_POM0PCIAL));
+	printf("PCIX0_POM0PCILAH        = %#010lx\n", in32r(PCIX0_POM0PCIAH));
+	printf("PCIX0_POM1LAL           = %#010lx\n", in32r(PCIX0_POM1LAL));
+	printf("PCIX0_POM1LAH           = %#010lx\n", in32r(PCIX0_POM1LAH));
+	printf("PCIX0_POM1SA            = %#010lx\n", in32r(PCIX0_POM1SA));
+	printf("PCIX0_POM1PCILAL        = %#010lx\n", in32r(PCIX0_POM1PCIAL));
+	printf("PCIX0_POM1PCILAH        = %#010lx\n", in32r(PCIX0_POM1PCIAH));
+	printf("PCIX0_POM2SA            = %#010lx\n", in32r(PCIX0_POM2SA));
+
+	printf("PCIX0_PIM0SA            = %#010lx\n", in32r(PCIX0_PIM0SA));
+	printf("PCIX0_PIM0LAL           = %#010lx\n", in32r(PCIX0_PIM0LAL));
+	printf("PCIX0_PIM0LAH           = %#010lx\n", in32r(PCIX0_PIM0LAH));
+	printf("PCIX0_PIM1SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
+	printf("PCIX0_PIM1LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
+	printf("PCIX0_PIM1LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
+	printf("PCIX0_PIM2SA            = %#010lx\n", in32r(PCIX0_PIM1SA));
+	printf("PCIX0_PIM2LAL           = %#010lx\n", in32r(PCIX0_PIM1LAL));
+	printf("PCIX0_PIM2LAH           = %#010lx\n", in32r(PCIX0_PIM1LAH));
+
+	printf("PCIX0_XSTS              = %#010lx\n", in32r(PCIX0_STS));
 }
 
 int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c
index 037a6430da..8518856cb1 100644
--- a/board/armadillo/flash.c
+++ b/board/armadillo/flash.c
@@ -279,7 +279,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 	int i, rc;
 
 	wp = (addr & ~1);	/* get lower word aligned address */
-	printf ("Writing %d short data to 0x%p from 0x%p.\n ", cnt, wp, src);
+	printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src);
 
 	/*
 	 * handle unaligned start bytes
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 836a0c40bf..06d8512cc9 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -188,8 +188,17 @@ static void at91sam9260ek_macb_hw_init(void)
 	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
 	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
 	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
+#if defined(CONFIG_AT91SAM9260EK)
+	/*
+	 * use PA10, PA11 for ETX2, ETX3.
+	 * PA23 and PA24 are for TWI EEPROM
+	 */
+	at91_set_B_periph(AT91_PIN_PA10, 0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA11, 0);	/* ETX3 */
+#else
 	at91_set_B_periph(AT91_PIN_PA23, 0);	/* ETX2 */
 	at91_set_B_periph(AT91_PIN_PA24, 0);	/* ETX3 */
+#endif
 	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
 #endif
 
diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c
index d0a4a39f99..b30ba803f9 100644
--- a/board/cobra5272/mii.c
+++ b/board/cobra5272/mii.c
@@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
 }
 #endif				/* CFG_DISCOVER_PHY */
 
-int mii_init(void) __attribute__((weak,alias("__mii_init")));
+void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
 void __mii_init(void)
 {
diff --git a/board/delta/nand.c b/board/delta/nand.c
index a635a6521b..5024056bc3 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -254,7 +254,7 @@ static unsigned long dfc_wait_event(unsigned long event)
 			break;
 		}
 		if(get_delta(start) > timeout) {
-			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
 			return 0xff000000;
 		}
 
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index c2c8fe8590..bd8a4e5e68 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -75,9 +75,11 @@ phys_size_t initdram(int board_type)
 		sdram->dacr0 =
 		    SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
 		    SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+		asm("nop");
 
 		/* Initialize DMR0 */
 		sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+		asm("nop");
 
 		/* Set IP (bit 3) in DACR */
 		sdram->dacr0 |= SDRAMC_DARCn_IP;
@@ -100,6 +102,7 @@ phys_size_t initdram(int board_type)
 
 		/* Finish the configuration by issuing the MRS. */
 		sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
 		*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile
index ef0b19ed2c..f337a7563c 100644
--- a/board/freescale/m5275evb/Makefile
+++ b/board/freescale/m5275evb/Makefile
@@ -31,7 +31,7 @@ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	.depend $(OBJS)
+$(LIB):	$(obj).depend $(OBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS)
 
 #########################################################################
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
index efa952c2e7..ad80694077 100644
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ b/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -165,8 +165,8 @@ int board_early_init_f (void)
 		printf ("Invalid DDR2 clock setting\n");
 		return -1;
 	}
-	printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
-	printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
+	printf ("BUS: %lu MHz\n", get_board_bus_clk() / 1000000);
+	printf ("MEM: %lu MHz\n", gd->mem_clk / 1000000);
 	return 0;
 }
 
@@ -622,8 +622,8 @@ int misc_init_r (void)
 #ifdef CFG_L2
 	l2cache_enable ();
 #endif
-	printf ("BUS:   %d MHz\n", gd->bus_clk / 1000000);
-	printf ("MEM:   %d MHz\n", gd->mem_clk / 1000000);
+	printf ("BUS:   %lu MHz\n", gd->bus_clk / 1000000);
+	printf ("MEM:   %lu MHz\n", gd->mem_clk / 1000000);
 
 	/*
 	 * All the information needed to print the cache details is avaiblable
diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c
index b653c058e1..59961cdab6 100644
--- a/board/integratorcp/flash.c
+++ b/board/integratorcp/flash.c
@@ -393,7 +393,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 						*addr = (FPW) 0x00D000D0;
 					} else {
 #ifdef DEBUG
-						printf ("Timeout,0x%08x\n", status);
+						printf ("Timeout,0x%08lx\n", status);
 #else
 						printf("Timeout\n");
 #endif
@@ -515,7 +515,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
 		return (2);
 	}
 
@@ -542,7 +542,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
 #ifdef DEBUG
 			*addr = (FPW) 0x00700070;
 			status = *addr;
-			printf("## status=0x%08x, addr=0x%08x\n", status, addr);
+			printf("## status=0x%08lx, addr=0x%p\n", status, addr);
 #endif
 			*addr = (FPW) 0x00500050; /* clear status register cmd */
 			*addr = (FPW) 0x00FF00FF; /* restore read mode */
diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c
index 89ced163bb..c19d445e20 100644
--- a/board/mp2usb/flash.c
+++ b/board/mp2usb/flash.c
@@ -426,7 +426,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data)
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
 		return (2);
 	}
 	/*
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 80e84aebb8..66a958c78a 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -71,7 +71,7 @@ void board_add_ram_info(int use_default)
 	}
 
 	get_sys_info(&board_cfg);
-	printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+	printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
 
 	mfsdram(DDR0_03, val);
 	val = DDR0_03_CASLAT_DECODE(val);
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index 63c91dc59c..c38850d6c7 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -282,7 +282,7 @@ int checkboard (void)
 	}
 
 	printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
-	printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, (char *)board_id_as[brd_id]);
+	printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id].name);
 
 	/* Fix the ack in the bme 32 */
 	udelay(5000);
diff --git a/board/versatile/flash.c b/board/versatile/flash.c
index ca77c8a29e..bbe5df724d 100644
--- a/board/versatile/flash.c
+++ b/board/versatile/flash.c
@@ -476,7 +476,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
 
 	/* Check if Flash is (sufficiently) erased */
 	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, (ulong) *addr);
 		return (2);
 	}
 
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index aa3932ad2d..ca16578432 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -254,7 +254,7 @@ static unsigned long dfc_wait_event(unsigned long event)
 			break;
 		}
 		if(get_delta(start) > timeout) {
-			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+			DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
 			return 0xff000000;
 		}