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authorRicardo Ribalda Delgado <ricardo.ribalda@uam.es>2008-07-17 12:47:09 +0200
committerStefan Roese <sr@denx.de>2008-07-18 12:31:17 +0200
commit086511fc96a8a9bb56e5e19a3d84c40f4dba80cc (patch)
tree6d92e4e0c8b37ac282a601f8b9e5467425bb0628 /board/xilinx/ml507/xparameters.h
parentd865fd09809a3a18669f35f970781820af40e4de (diff)
downloadblackbird-obmc-uboot-086511fc96a8a9bb56e5e19a3d84c40f4dba80cc.tar.gz
blackbird-obmc-uboot-086511fc96a8a9bb56e5e19a3d84c40f4dba80cc.zip
ppc4xx: ML507 Board Support
The Xilinx ML507 Board is a Virtex 5 prototyping board that includes, among others: -Virtex 5 FX FPGA (With a ppc440x5 in it) -256MB of SDRAM2 -32MB of Flash -I2C Eeprom -System ACE chip -Serial ATA connectors -RS232 Level Conversors -Ethernet Transceiver This patch gives support to a standard design produced by EDK for this board: ppc440, uartlite, xilinx_int and flash - Includes Changes propossed by Stefan Roese and Michal Simek Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
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diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h
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+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
+#define XPAR_LLTEMAC_0_BASEADDR 0x81c00000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFC000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+
+#endif
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