ppc4xx: T3CORP fixes and updates

This patch fixes some problems for the T3CORP board. Here the list
of the changes:

- Add 600-67 and 677 CPU frequency setting to chip_config
  command
- Define CONFIG_DDR_RFDC_FIXED on t3corp:
  While using the "normal" auto calibration code, sometimes values for
  RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang
  upon relocation, while running from SDRAM). With this optimized RFDC
  value we can force this register and use the auto-calibration code to
  setup the remaining calibration registers.
- Increase sizes of FPGA chips selects
- EBC timing updated OEN=3 for 66 MHz EBC speed
- Change ext. IRQ2 setup to level-low active
- Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL

By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the
chip busy status. This is now used instead of the data toggle method which
is used historically by default in the common CFI driver. With this change
a problem with not written data is solved on this board, where a 32 byte
block of data is still erased instead of filled with the correct content
after these commands:

=> erase 0xfc100000 +0x1000000

....................................................................
done
Erased 128 sectors
=> cp.b 0x100000 0xfc100000 0x1000000
Copy to Flash... done
=> cmp.b 0x100000 0xfc100000 0x1000000
byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff)
Total of 12637888 bytes were the same

Signed-off-by: Stefan Roese <sr@denx.de>

3 files changed, 21 insertions, 5 deletions

diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c
index c00bf16bd9..98ab49f49f 100644
--- a/board/t3corp/chip_config.c
+++ b/board/t3corp/chip_config.c
@@ -27,13 +27,27 @@
 
 struct ppc4xx_config ppc4xx_config_val[] = {
 	{
-		"600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+		"600-67", "CPU: 600 PLB: 200 OPB:  67 EBC:  67",
+		{
+			0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
+			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
+		"600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
 		{
 			0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
 			0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
 		}
 	},
 	{
+		"667", "CPU: 667 PLB: 166 OPB:  83 EBC:  83",
+		{
+			0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
+			0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+		}
+	},
+	{
 		"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
 		{
 			0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
index 4a4217fc8e..ecd35ff7b6 100644
--- a/board/t3corp/init.S
+++ b/board/t3corp/init.S
@@ -81,11 +81,13 @@ tlbtab:
 	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
 
 	/* TLB-entry for FPGA(s) */
-	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
 		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
+		 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
+	tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
 		 AC_RW | SA_IG)
-	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
+	tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
 		 AC_RW | SA_IG)
 
 	/* TLB-entry for OCM */
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c
index 8ffa321690..ddf58970a3 100644
--- a/board/t3corp/t3corp.c
+++ b/board/t3corp/t3corp.c
@@ -45,7 +45,7 @@ int board_early_init_f(void)
 	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
 	mtdcr(UIC1ER, 0x00000000);	/* disable all */
 	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
-	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1PR, 0x7fffffff);	/* per ref-board manual */
 	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
 	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
 	mtdcr(UIC1SR, 0xffffffff);	/* clear all */