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author | Fabio Estevam <fabio.estevam@freescale.com> | 2015-05-15 16:10:47 -0300 |
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committer | Stefano Babic <sbabic@denx.de> | 2015-05-19 15:08:22 +0200 |
commit | c8d8d83e4b9c94ed5bbd6f8290c8a5170a5ed21a (patch) | |
tree | afa8f23c9543063b95e14843d5200ca095c0621f /board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg | |
parent | e06a03625d00668a1f90408ea1e4cd29752207fe (diff) | |
download | blackbird-obmc-uboot-c8d8d83e4b9c94ed5bbd6f8290c8a5170a5ed21a.tar.gz blackbird-obmc-uboot-c8d8d83e4b9c94ed5bbd6f8290c8a5170a5ed21a.zip |
hummingboard: Remove unused directory
The 'mx6-microsom' directory was only used for the previous mx6solo
hummingboard support, which has been removed in favour of the SPL
version.
Remove the remaining piece of the old mx6solo hummingboard support.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg')
-rw-r--r-- | board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg deleted file mode 100644 index f92fc19de4..0000000000 --- a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2013 Boundary Devices - * Copyright (C) 2013 SolidRun ltd. - * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * DDR3 settings - * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), - * memory bus width: 64 bits x16/x32/x64 - * MX6DL ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 64 bits x16/x32/x64 - * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) - * memory bus width: 32 bits x16/x32 - */ -/* DDR IO TYPE */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -/* Clock */ -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028 -/* Address */ -DATA 4, MX6_IOM_DRAM_CAS, 0x00000010 -DATA 4, MX6_IOM_DRAM_RAS, 0x00000010 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010 -/* Control */ -DATA 4, MX6_IOM_DRAM_RESET, 0x00000010 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010 - -/* - * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS, - * CMOS mode saves power, but have less timing margin in case of DDR - * timing issue on your board you can try DDR_MODE: [= 0x00020000] - */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 - -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000 - -/* - * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS, - * CMOS mode saves power, but have less timing margin in case of DDR - * timing issue on your board you can try DDR_MODE: [= 0x00020000] - */ -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 - -DATA 4, MX6_IOM_GRP_B0DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000028 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000000 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000000 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000000 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000000 - -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000 |