powerpc: ppc4xx: remove board support for KAREF and METROBOX

These boards have been orphaned for more than 6 months.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

10 files changed, 0 insertions, 1370 deletions

diff --git a/board/sandburst/metrobox/Kconfig b/board/sandburst/metrobox/Kconfig
deleted file mode 100644
index 4a771efef4..0000000000
--- a/board/sandburst/metrobox/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_METROBOX
-
-config SYS_BOARD
-	default "metrobox"
-
-config SYS_VENDOR
-	default "sandburst"
-
-config SYS_CONFIG_NAME
-	default "METROBOX"
-
-endif
diff --git a/board/sandburst/metrobox/MAINTAINERS b/board/sandburst/metrobox/MAINTAINERS
deleted file mode 100644
index 71d18f9186..0000000000
--- a/board/sandburst/metrobox/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-METROBOX BOARD
-#M:	Travis Sawyer <travis.sawyer@sandburst.com>
-S:	Orphan (since 2014-03)
-F:	board/sandburst/metrobox/
-F:	include/configs/METROBOX.h
-F:	configs/METROBOX_defconfig
diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile
deleted file mode 100644
index 2c1028bd2b..0000000000
--- a/board/sandburst/metrobox/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2005
-# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# TBS: add for debugging purposes
-ccflags-y += -DBUILDUSER='"$(shell whoami)"'
-
-obj-y	= metrobox.o ../common/flash.o ../common/sb_common.o
-extra-y	+= init.o
diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk
deleted file mode 100644
index 23190c8673..0000000000
--- a/board/sandburst/metrobox/config.mk
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2005
-# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -DCONFIG_440=1
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
-
-ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
-endif
diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h
deleted file mode 100644
index c99b38ca06..0000000000
--- a/board/sandburst/metrobox/hal_xc_auto.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/* ****************************************************************
- * Common defs for reg spec for chip xc
- * Auto-generated by trex2: DO NOT HAND-EDIT!!
- * ****************************************************************
- */
-
-#ifndef HAL_XC_AUTO_H
-#define HAL_XC_AUTO_H
-
-/* ----------------------------------------------------------------
- * For block: 'xcvr_cntl'
- */
-
-/* ---- Block instance addressing (for block-select) */
-#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6
-#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9
-#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4
-
-#define  XCVR_CNTL_ADDR  0x0
-
-/* ---- Reg addressing (within block) */
-#define XCVR_CNTL_REG_ADDR_BIT_L 2
-#define XCVR_CNTL_REG_ADDR_BIT_H 5
-#define XCVR_CNTL_REG_ADDR_WIDTH 4
-
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_REVISION */
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET    0x000
-#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_RESET */
-#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET    0x004
-#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_STATUS */
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET    0x008
-#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_CNTL */
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET    0x01c
-#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_BRD_INFO */
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET    0x020
-#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET    0x024
-#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_INTERRUPT */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET    0x00c
-#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET    0x010
-#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_SCRATCH */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET    0x014
-#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB      0
-
-/* ================================================================
- * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET    0x018
-#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK    0x000
-#endif
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB     31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB      0
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_REVISION */
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK    0x0000ff00
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT    8
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB    15
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB    8
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK    0x000000ff
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB    7
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT    0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_RESET */
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK    0x00020000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT    17
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB    17
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB    17
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK    0x00010000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT    16
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB    16
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB    16
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK    0x00008000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT    15
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB    15
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB    15
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK    0x00004000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT    14
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB    14
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB    14
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK    0x00002000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT    13
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB    13
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB    13
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK    0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT    12
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB    12
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB    12
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK    0x00000800
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT    11
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB    11
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB    11
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK    0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT    10
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB    10
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB    10
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK    0x00000200
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT    9
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB    9
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB    9
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK    0x00000100
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT    8
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB    8
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB    8
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK    0x00000080
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT    7
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB    7
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB    7
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK    0x00000040
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT    6
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB    6
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB    6
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK    0x00000020
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT    5
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB    5
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB    5
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK    0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT    4
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB    4
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB    4
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK    0x00000008
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT    3
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB    3
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB    3
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK    0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT    2
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB    2
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB    2
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK    0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT    1
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB    1
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB    1
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB    0
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT    0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_STATUS */
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK    0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT    2
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB    2
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB    2
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK    0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT    1
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB    1
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB    1
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB    0
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT    0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_CNTL */
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK    0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT    10
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB    10
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB    10
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK    0x00000300
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT    8
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB    9
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB    8
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK    0x000000c0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT    6
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB    7
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB    6
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK    0x00000030
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT    4
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB    5
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB    4
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK    0x0000000c
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT    2
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB    3
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB    2
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK    0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT    1
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB    1
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB    1
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB    0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT    0x00000001
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_BRD_INFO */
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK    0x000000f0
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT    4
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB    7
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB    4
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK    0x00000003
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB    1
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT    0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK    0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT    12
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB    12
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB    12
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK    0x00000f00
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT    8
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB    11
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB    8
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK    0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT    4
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB    4
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB    4
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK    0x0000000f
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB    3
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT    0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_INTERRUPT */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK    0x00002000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT    13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB    13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB    13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK    0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT    12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB    12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB    12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK    0x00000800
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT    11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB    11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB    11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK    0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT    10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB    10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB    10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK    0x00000200
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT    9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB    9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB    9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK    0x00000100
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT    8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB    8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB    8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK    0x00000080
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT    7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB    7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB    7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK    0x00000040
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT    6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB    6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB    6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK    0x00000020
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT    5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB    5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB    5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK    0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT    4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB    4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB    4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK    0x00000008
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT    3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB    3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB    3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK    0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT    2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB    2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB    2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK    0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT    1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB    1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB    1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT    0x00000000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB    0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT    0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK    0x00002000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT    13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB    13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB    13
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK    0x00001000
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT    12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB    12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB    12
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK    0x00000800
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT    11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB    11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB    11
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK    0x00000400
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT    10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB    10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB    10
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK    0x00000200
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT    9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB    9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB    9
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK    0x00000100
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT    8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB    8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB    8
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK    0x00000080
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT    7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB    7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB    7
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK    0x00000040
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT    6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB    6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB    6
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK    0x00000020
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT    5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB    5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB    5
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK    0x00000010
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT    4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB    4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB    4
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK    0x00000008
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT    3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB    3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB    3
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK    0x00000004
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT    2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB    2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB    2
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK    0x00000002
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT    1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB    1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB    1
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK    0x00000001
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB    0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT    0x00000001
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_SCRATCH */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB    31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT    0x00000000
-
-/* ================================================================
- * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK    0xffffffff
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT    0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB    31
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB    0
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE)
-#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT    0xffffffff
-
-#endif /* matches #ifndef HAL_XC_AUTO_H */
diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S
deleted file mode 100644
index 13e340eece..0000000000
--- a/board/sandburst/metrobox/init.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-*  Copyright (C) 2005
-*  Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#include <ppc_asm.tmpl>
-#include <asm/mmu.h>
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-/**************************************************************************
- * TLB TABLE
- *
- * This table is used by the cpu boot code to setup the initial tlb
- * entries. Rather than make broad assumptions in the cpu source tree,
- * this table lets each board set things up however they like.
- *
- *  Pointer to the table is returned in r1
- *
- *************************************************************************/
-
-	.section .bootpg,"ax"
-	.globl tlbtab
-
-tlbtab:
-	tlbtab_start
-	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
-	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
-	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
-	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
-	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
-	tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
-	tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
-	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
-	tlbtab_end
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
deleted file mode 100644
index 290fa020f8..0000000000
--- a/board/sandburst/metrobox/metrobox.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/*
- *  Copyright (c) 2005
- *  Travis B. Sawyer,  Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include "metrobox.h"
-#include "metrobox_version.h"
-#include <timestamp.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <spd_sdram.h>
-#include <i2c.h>
-#include "../common/sb_common.h"
-#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
-    defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
-#include <net.h>
-#endif
-
-void fpga_init (void);
-
-METROBOX_BOARD_ID_ST board_id_as[] =
-{	{"Undefined"},			    /* Not specified */
-	{"2x10Gb"},			    /* 2 ports, 10 GbE */
-	{"20x1Gb"},			    /* 20 ports, 1 GbE */
-	{"Reserved"},			     /* Reserved for future use */
-};
-
-/*************************************************************************
- *  board_early_init_f
- *
- *  Setup chip selects, initialize the Opto-FPGA, initialize
- *  interrupt polarity and triggers.
- ************************************************************************/
-int board_early_init_f (void)
-{
-	ppc440_gpio_regs_t *gpio_regs;
-
-	/* Enable GPIO interrupts */
-	mtsdr(SDR0_PFC0, 0x00103E00);
-
-	/* Setup access for LEDs, and system topology info */
-	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
-	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
-	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
-
-	/* Turn on all the leds for now */
-	gpio_regs->out = SBCOMMON_GPIO_LEDS;
-
-	/*--------------------------------------------------------------------+
-	  | Initialize EBC CONFIG
-	  +-------------------------------------------------------------------*/
-	mtebc(EBC0_CFG,
-	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
-	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
-	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
-	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
-	      EBC_CFG_PR_32);
-
-	/*--------------------------------------------------------------------+
-	  | 1/2 MB FLASH. Initialize bank 0 with default values.
-	  +-------------------------------------------------------------------*/
-	mtebc(PB0AP,
-	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
-	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
-	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
-	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
-	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
-	      EBC_BXAP_PEN_DISABLED);
-
-	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
-	/*--------------------------------------------------------------------+
-	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
-	  +-------------------------------------------------------------------*/
-	mtebc(PB1AP,
-	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
-	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
-	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
-	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
-	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
-	      EBC_BXAP_PEN_DISABLED);
-
-	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
-
-	/*--------------------------------------------------------------------+
-	  | Compact Flash, uses 2 Chip Selects (2 & 6)
-	  +-------------------------------------------------------------------*/
-	mtebc(PB2AP,
-	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
-	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
-	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
-	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
-	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
-	      EBC_BXAP_PEN_DISABLED);
-
-	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
-	/*--------------------------------------------------------------------+
-	  | OPTO & OFEM FPGA. Initialize bank 3 with default values.
-	  +-------------------------------------------------------------------*/
-	mtebc(PB3AP,
-	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
-	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
-	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
-	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
-	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
-	mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
-	/*--------------------------------------------------------------------+
-	  | MAC A for metrobox
-	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
-	  | Initialize bank 4 with default values.
-	  +-------------------------------------------------------------------*/
-	mtebc(PB4AP,
-	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
-	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
-	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
-	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
-	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
-	mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
-	/*--------------------------------------------------------------------+
-	  | Metrobox MAC B  Initialize bank 5 with default values.
-	  | KA REF FPGA	 Initialize bank 5 with default values.
-	  +-------------------------------------------------------------------*/
-	mtebc(PB5AP,
-	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
-	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
-	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
-	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
-	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
-	mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
-	/*--------------------------------------------------------------------+
-	  | Compact Flash, uses 2 Chip Selects (2 & 6)
-	  +-------------------------------------------------------------------*/
-	mtebc(PB6AP,
-	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
-	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
-	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
-	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
-	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
-	      EBC_BXAP_PEN_DISABLED);
-
-	mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
-
-	/*--------------------------------------------------------------------+
-	  | BME-32. Initialize bank 7 with default values.
-	  +-------------------------------------------------------------------*/
-	mtebc(PB7AP,
-	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
-	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
-	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
-	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
-	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
-
-	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
-	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
-
-	/*--------------------------------------------------------------------+
-	 * Setup the interrupt controller polarities, triggers, etc.
-	 +-------------------------------------------------------------------*/
-	/*
-	 * Because of the interrupt handling rework to handle 440GX interrupts
-	 * with the common code, we needed to change names of the UIC registers.
-	 * Here the new relationship:
-	 *
-	 * U-Boot name	440GX name
-	 * -----------------------
-	 * UIC0		UICB0
-	 * UIC1		UIC0
-	 * UIC2		UIC1
-	 * UIC3		UIC2
-	 */
-	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
-	mtdcr (UIC1ER, 0x00000000);	/* disable all */
-	mtdcr (UIC1CR, 0x00000000);	/* all non- critical */
-	mtdcr (UIC1PR, 0xfffffe03);	/* polarity */
-	mtdcr (UIC1TR, 0x01c00000);	/* trigger edge vs level */
-	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
-
-	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
-	mtdcr (UIC2ER, 0x00000000);	/* disable all */
-	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
-	mtdcr (UIC2PR, 0xffffc8ff);	/* polarity */
-	mtdcr (UIC2TR, 0x00ff0000);	/* trigger edge vs level */
-	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
-
-	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
-	mtdcr (UIC3ER, 0x00000000);	/* disable all */
-	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
-	mtdcr (UIC3PR, 0xffff83ff);	/* polarity */
-	mtdcr (UIC3TR, 0x00ff8c0f);	/* trigger edge vs level */
-	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
-	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
-
-	mtdcr (UIC0SR, 0xfc000000);	/* clear all */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all */
-	mtdcr (UIC0CR, 0x00000000);	/* all non-critical */
-	mtdcr (UIC0PR, 0xfc000000);
-	mtdcr (UIC0TR, 0x00000000);
-	mtdcr (UIC0VR, 0x00000001);
-
-	fpga_init();
-
-	return 0;
-}
-
-/*************************************************************************
- *  checkboard
- *
- *  Dump pertinent info to the console
- ************************************************************************/
-int checkboard (void)
-{
-	sys_info_t sysinfo;
-	unsigned char brd_rev, brd_id;
-	unsigned short sernum;
-	unsigned char opto_rev, opto_id;
-	OPTO_FPGA_REGS_ST *opto_ps;
-
-	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
-	opto_rev = (unsigned char)((opto_ps->revision_ul &
-				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
-				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
-
-	opto_id = (unsigned char)((opto_ps->revision_ul &
-				   SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
-				  >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
-
-	brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
-				   SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
-				  >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
-
-	brd_id = (unsigned char)((opto_ps->boardinfo_ul &
-				  SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
-				 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
-
-	get_sys_info (&sysinfo);
-
-	sernum = sbcommon_get_serial_number();
-	printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
-	printf ("%s\n", METROBOX_U_BOOT_REL_STR);
-
-	printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
-	if (sbcommon_get_master()) {
-		printf("Slot 0 - Master\nSlave board");
-		if (sbcommon_secondary_present())
-			printf(" present\n");
-		else
-			printf(" not detected\n");
-	} else {
-		printf("Slot 1 - Slave\n\n");
-	}
-
-	printf ("OptoFPGA ID:\t0x%02X\tRev:  0x%02X\n", opto_id, opto_rev);
-	printf ("Board Rev:\t0x%02X\tID:  %s\n", brd_rev, board_id_as[brd_id].name);
-
-	/* Fix the ack in the bme 32 */
-	udelay(5000);
-	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
-	asm("eieio");
-
-
-	return (0);
-}
-
-/*************************************************************************
- *  misc_init_f
- *
- *  Initialize I2C bus one to gain access to the fans
- ************************************************************************/
-int misc_init_f (void)
-{
-	/* Turn on fans */
-	sbcommon_fans();
-
-	return (0);
-}
-
-/*************************************************************************
- *  misc_init_r
- *
- *  Do nothing.
- ************************************************************************/
-int misc_init_r (void)
-{
-	unsigned short sernum;
-	char envstr[255];
-	uchar enetaddr[6];
-	unsigned char opto_rev;
-	OPTO_FPGA_REGS_ST *opto_ps;
-
-	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
-	if(NULL != getenv("secondserial")) {
-	    puts("secondserial is set, switching to second serial port\n");
-	    setenv("stderr", "serial1");
-	    setenv("stdout", "serial1");
-	    setenv("stdin", "serial1");
-	}
-
-	setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
-
-	memset(envstr, 0, 255);
-	sprintf (envstr, "Built %s %s by %s",
-		 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
-	setenv("bldstr", envstr);
-	saveenv();
-
-	if( getenv("autorecover")) {
-		setenv("autorecover", NULL);
-		saveenv();
-		sernum = sbcommon_get_serial_number();
-
-		printf("\nSetting up environment for automatic filesystem recovery\n");
-		/*
-		 * Setup default bootargs
-		 */
-		memset(envstr, 0, 255);
-		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
-			"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
-			sernum, sernum);
-		setenv("bootargs", envstr);
-
-		/*
-		 * Setup Default boot command
-		 */
-		setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
-		       "fatload ide 0 8100000 pramdisk;"
-		       "bootm 8000000 8100000");
-
-		printf("Done.  Please type allow the system to continue to boot\n");
-	}
-
-	if( getenv("fakeled")) {
-		setenv("bootdelay", "-1");
-		saveenv();
-		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
-		opto_rev = (unsigned char)((opto_ps->revision_ul &
-					    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
-					   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
-
-		if(0x12 <= opto_rev) {
-			opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
-		}
-	}
-
-#ifdef CONFIG_HAS_ETH0
-	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
-		board_get_enetaddr(0, enetaddr);
-		eth_setenv_enetaddr("ethaddr", enetaddr);
-	}
-#endif
-
-#ifdef CONFIG_HAS_ETH1
-	if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
-		board_get_enetaddr(1, enetaddr);
-		eth_setenv_enetaddr("eth1addr", enetaddr);
-	}
-#endif
-
-#ifdef CONFIG_HAS_ETH2
-	if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
-		board_get_enetaddr(2, enetaddr);
-		eth_setenv_enetaddr("eth2addr", enetaddr);
-	}
-#endif
-
-#ifdef CONFIG_HAS_ETH3
-	if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
-		board_get_enetaddr(3, enetaddr);
-		eth_setenv_enetaddr("eth3addr", enetaddr);
-	}
-#endif
-
-	return (0);
-}
-
-/*************************************************************************
- *  ide_set_reset
- ************************************************************************/
-#ifdef CONFIG_IDE_RESET
-void ide_set_reset(int on)
-{
-	OPTO_FPGA_REGS_ST *opto_ps;
-	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
-	if (on) {		/* assert RESET */
-	    opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
-	} else {		/* release RESET */
-	    opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
-	}
-}
-#endif /* CONFIG_IDE_RESET */
-
-/*************************************************************************
- *  fpga_init
- ************************************************************************/
-void fpga_init(void)
-{
-	OPTO_FPGA_REGS_ST *opto_ps;
-	unsigned char opto_rev;
-	unsigned long tmp;
-
-	/* Ensure we have power all around */
-	udelay(500);
-
-	/*
-	 * Take appropriate hw bits out of reset
-	 */
-	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
-
-	tmp =
-	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
-	    SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
-	opto_ps->reset_ul = tmp;
-	/*
-	 * Turn on the 'Slow Blink' for the System Error Led.
-	 * Ensure FPGA rev is up to at least rev 0x12
-	 */
-	opto_rev = (unsigned char)((opto_ps->revision_ul &
-				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
-				   >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
-	if(0x12 <= opto_rev) {
-	    opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
-	}
-
-	asm("eieio");
-
-	return;
-}
-
-int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned short sernum;
-	char envstr[255];
-
-	sernum = sbcommon_get_serial_number();
-
-	memset(envstr, 0, 255);
-	/*
-	 * Setup our ip address
-	 */
-	sprintf(envstr, "10.100.60.%d", sernum);
-
-	setenv("ipaddr", envstr);
-	/*
-	 * Setup the host ip address
-	 */
-	setenv("serverip", "10.100.17.10");
-
-	/*
-	 * Setup default bootargs
-	 */
-	memset(envstr, 0, 255);
-
-	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
-		"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
-		"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
-		":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
-		sernum, sernum, sernum);
-
-	setenv("bootargs_nfs", envstr);
-	setenv("bootargs", envstr);
-
-	/*
-	 * Setup CF bootargs
-	 */
-	memset(envstr, 0, 255);
-	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
-		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
-		sernum, sernum);
-
-	setenv("bootargs_cf", envstr);
-
-	/*
-	 * Setup Default boot command
-	 */
-	setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
-	setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
-
-	/*
-	 * Setup compact flash boot command
-	 */
-	setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
-
-	saveenv();
-
-
-	return(1);
-}
-
-int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned short sernum;
-	char envstr[255];
-
-	sernum = sbcommon_get_serial_number();
-
-	printf("\nSetting up environment for filesystem recovery\n");
-	/*
-	 * Setup default bootargs
-	 */
-	memset(envstr, 0, 255);
-	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
-		"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
-		sernum, sernum);
-
-	setenv("bootargs", envstr);
-
-	/*
-	 * Setup Default boot command
-	 */
-	setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
-	       "fatload ide 0 8100000 pramdisk;"
-	       "bootm 8000000 8100000");
-
-	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
-	       " please type fsrecover.sh<cr>\n");
-
-	return(1);
-}
-
-U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
-	   "Set environment to factory defaults", "");
-
-U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
-	   "Set environment to allow for fs recovery", "");
diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h
deleted file mode 100644
index d64f496c9a..0000000000
--- a/board/sandburst/metrobox/metrobox.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __METROBOX_H__
-#define __METROBOX_H__
-/*
- * (C) Copyright 2005
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-typedef struct metrobox_board_id_s {
-	const char name[40];
-} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST;
-
-
-/* Metrobox Opto-FPGA registers and definitions */
-#include "hal_xc_auto.h"
-typedef struct opto_fpga_regs_s {
-	volatile unsigned long revision_ul;	/* Read Only  */
-	volatile unsigned long reset_ul;	/* Read/Write */
-	volatile unsigned long status_ul;	/* Read Only  */
-	volatile unsigned long interrupt_ul;	/* Read Only  */
-	volatile unsigned long mask_ul;	/* Read/Write */
-	volatile unsigned long scratch_ul;	/* Read/Write */
-	volatile unsigned long scrmask_ul;	/* Read/Write */
-	volatile unsigned long control_ul;	/* Read/Write */
-	volatile unsigned long boardinfo_ul;	/* Read Only  */
-} __attribute__ ((packed)) OPTO_FPGA_REGS_ST , *OPTO_FPGA_REGS_PST;
-
-#endif /* __METROBOX_H__ */
diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h
deleted file mode 100644
index 8264f56d6e..0000000000
--- a/board/sandburst/metrobox/metrobox_version.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _METROBOX_VERSION_H_
-#define _METROBOX_VERSION_H_
-/*
- * (C) Copyright 2005
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#define METROBOX_U_BOOT_REL_STR "Release 2.0.3"
-
-#endif
diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug
deleted file mode 100644
index 7ff09c0671..0000000000
--- a/board/sandburst/metrobox/u-boot.lds.debug
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * (C) Copyright 2002-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)		}
-  .dynsym        : { *(.dynsym)		}
-  .dynstr        : { *(.dynstr)		}
-  .rel.text      : { *(.rel.text)	}
-  .rela.text     : { *(.rela.text)	}
-  .rel.data      : { *(.rel.data)	}
-  .rela.data     : { *(.rela.data)	}
-  .rel.rodata    : { *(.rel.rodata)	}
-  .rela.rodata   : { *(.rela.rodata)	}
-  .rel.got       : { *(.rel.got)	}
-  .rela.got      : { *(.rela.got)	}
-  .rel.ctors     : { *(.rel.ctors)	}
-  .rela.ctors    : { *(.rela.ctors)	}
-  .rel.dtors     : { *(.rel.dtors)	}
-  .rela.dtors    : { *(.rela.dtors)	}
-  .rel.bss       : { *(.rel.bss)	}
-  .rela.bss      : { *(.rela.bss)	}
-  .rel.plt       : { *(.rel.plt)	}
-  .rela.plt      : { *(.rela.plt)	}
-  .init          : { *(.init)	}
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within	*/
-    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-
-    arch/powerpc/cpu/ppc4xx/start.o	(.text)
-    board/sandburst/metrobox/init.o (.text)
-    arch/powerpc/cpu/ppc4xx/kgdb.o	(.text)
-    arch/powerpc/cpu/ppc4xx/traps.o	(.text)
-    arch/powerpc/cpu/ppc4xx/interrupts.o	(.text)
-    arch/powerpc/cpu/ppc4xx/4xx_uart.o	(.text)
-    arch/powerpc/cpu/ppc4xx/cpu_init.o	(.text)
-    arch/powerpc/cpu/ppc4xx/speed.o	(.text)
-    drivers/net/4xx_enet.o	(.text)
-    common/dlmalloc.o	(.text)
-    lib/crc32.o		(.text)
-    arch/powerpc/lib/extable.o	(.text)
-    lib/zlib.o		(.text)
-
-/*    common/env_embedded.o(.text) */
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}