sh: Update MS7750SE01 platform

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

1 files changed, 37 insertions, 26 deletions

diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S
index 056c691f6f..360c9fa173 100644
--- a/board/ms7750se/lowlevel_init.S
+++ b/board/ms7750se/lowlevel_init.S
@@ -1,7 +1,28 @@
 /*
-	modified from SH-IPL+g
-	Renesaso SuperH Solution Enginge MS775x BSC setting 
-	Coyright (c) 2007 Nobuhiro Iwamatsu
+ modified from SH-IPL+g
+ Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
+
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 
+ 
+ Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
 */
 
 #include <config.h>
@@ -9,38 +30,34 @@
 
 #include <asm/processor.h>
 
-#ifdef CONFIG_CPU_SUBTYPE_SH7751
+#ifdef CONFIG_CPU_SH7751
 #define BCR2_D_VALUE	0x2FFC	   /* Area 1-6 width: 32/32/32/32/32/16 */
 #define WCR1_D_VALUE    0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
-#ifdef CONFIG_MRSHPC
+#ifdef CONFIG_MARUBUN_PCCARD
 #define WCR2_D_VALUE    0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
 				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
-#else /* CONFIG_MRSHPC*/
+#else /* CONFIG_MARUBUN_PCCARD */
 #define WCR2_D_VALUE    0x7FFE4FE7 /* A6:3  A6B:7 A5:15 A5B:7 A4:15
 				      A3:2  A2:15 A1:15 A0:6  A0B:7  */
-#endif /* CONFIG_MRSHPC */
+#endif /* CONFIG_MARUBUN_PCCARD */
 #define WCR3_D_VALUE	0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
 				      A2: 1-3 A1: 1-3 A0: 0-1 */
-#define LED_ADDRESS	0xBA000000 /* Address of LED register */ 	
 #define RTCOR_D_VALUE	0xA50D	   /* Write code A5, data 0D (~15us?) */
 #define SDMR3_ADDRESS	0xFF940088 /* SDMR3 address on 32-bit bus */
 #define MCR_D1_VALUE	0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
 #define MCR_D2_VALUE	0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
-#define SWITCH_ADDR	0xB9000000 /* Address of DIP switches */
-#else /* CONFIG_CPU_SUBTYPE_SH7751 */
+#else /* CONFIG_CPU_SH7751 */
 #define BCR2_D_VALUE	0x2E3C	   /* Area 1-6 width: 32/32/64/16/32/16 */
 #define WCR1_D_VALUE	0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
 #define WCR2_D_VALUE	0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
 				      A3:2  A2:15 A1:15 A0:15 A0B:7  */
 #define WCR3_D_VALUE	0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
 				      A2: 1-3 A1: 1-3 A0: 0-1 */
-#define LED_ADDRESS	0xB0C00000 /* Address of LED register */ 	
 #define RTCOR_D_VALUE	0xA510	   /* Write code A5, data 10 (~15us?) */
 #define SDMR3_ADDRESS	0xFF940110 /* SDMR3 address on 64-bit bus */
 #define MCR_D1_VALUE	0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
 #define MCR_D2_VALUE	0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
-#define SWITCH_ADDR	0xb0800000 /* Address of DIP switches */
-#endif /* CONFIG_CPU_SUBTYPE_SH7751 */
+#endif /* CONFIG_CPU_SH7751 */
 
 	.global lowlevel_init
 	.text
@@ -48,8 +65,8 @@
 
 lowlevel_init:
 
-	mov.l   L_CCR, r1               ! CCR Address
-	mov.l   L_CCR_DISABLE, r0       ! CCR Data
+	mov.l   CCR_A, r1               ! CCR Address
+	mov.l   CCR_D_DISABLE, r0       ! CCR Data
 	mov.l   r0, @r1
 
 init_bsc:
@@ -77,11 +94,6 @@ init_bsc:
 	mov.l	WCR3_D,r0	/* WCR3 Data */
 	mov.l	r0,@r1
 
-	mov.l	LED_A,r1	/* LED Address */
-	mov	#0xff,r0	/* LED ALL 'on' */
-	shll8	r0
-	mov.w	r0,@r1
-
 	mov.l	MCR_A,r1	/* MCR Address */
 	mov.l	MCR_D1,r0	/* MCR Data1 */
 	mov.l	r0,@r1
@@ -129,19 +141,19 @@ init_bsc:
 
 	.align	2
 
-L_CCR:          .long   CCR
-L_CCR_DISABLE:  .long   0x0808
+CCR_A:          .long   CCR
+CCR_D_DISABLE:  .long   0x0808
 FRQCR_A:	.long	FRQCR
 FRQCR_D:
-#ifdef CONFIG_CPU_SUBTYPE_SH_R
+#ifdef CONFIG_CPU_TYPE_R
 		.long	0x00000e1a	/* 12:3:3 */
-#else
+#else	/* CONFIG_CPU_TYPE_R */
 #ifdef CONFIG_GOOD_SESH4
 		.long	0x00000e13	/* 6:2:1 */
 #else
 		.long	0x00000e23	/* 6:1:1 */
 #endif
-#endif	/* CONFIG_CPU_SUBTYPE_SH_R */
+#endif	/* CONFIG_CPU_TYPE_R */
 
 BCR1_A:		.long	BCR1
 BCR1_D:		.long	0x00000008	/* Area 3 SDRAM */
@@ -153,7 +165,6 @@ WCR2_A:		.long	WCR2
 WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
 WCR3_A:		.long	WCR3
 WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
-LED_A:		.long	LED_ADDRESS	/* LED Address */
 RTCSR_A:	.long	RTCSR	
 RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
 RTCNT_A:	.long	RTCNT