rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

6 files changed, 71 insertions, 71 deletions

diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk
index bf2b8798c1..3c6d041720 100644
--- a/board/lwmon5/config.mk
+++ b/board/lwmon5/config.mk
@@ -35,5 +35,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 5aade72b52..718cec6af5 100644
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -47,7 +47,7 @@ tlbtab:
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-	tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.
@@ -55,28 +55,28 @@ tlbtab:
 	 * routine.
 	 */
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #endif
 
 	/* TLB-entry for PCI Memory */
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
 
 	/* TLB-entry for the FPGA Chip select 2 */
-	tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
 
 	/* TLB-entry for the FPGA Chip select 3 */
-	tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
 
 	/* TLB-entry for the LIME Controller */
-	tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-	tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-	tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-	tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
 
 	/* TLB-entry for Internal Registers & OCM */
 	tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I)
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
index 1e5349a6ec..0a8787a91c 100644
--- a/board/lwmon5/kbd.c
+++ b/board/lwmon5/kbd.c
@@ -74,7 +74,7 @@ static int compare_magic (uchar *kbd_data, uchar *str);
 
 /* maximum number of "magic" key codes that can be assigned */
 
-static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
 
 static uchar *key_match (uchar *);
 
@@ -106,7 +106,7 @@ static void kbd_init (void)
 	uchar val, errcd;
 	int i;
 
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	gd->kbd_status = 0;
 
@@ -412,7 +412,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	int i;
 
 #if 0 /* Done in kbd_init */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
 	/* Read keys */
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 8975bfd3d2..aa62f37900 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -27,7 +27,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 ulong flash_get_size(ulong base, int banknum);
 int misc_init_r_kbd(void);
@@ -94,24 +94,24 @@ int board_early_init_f(void)
 	reg = 0;
 	mtsdr(sdr_pci0, 0x00000000 | reg);
 
-	gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
 
-#if CONFIG_POST & CFG_POST_BSPEC1
-	gpio_write_bit(CFG_GPIO_HIGHSIDE, 1);
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
+	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
 
 	reg = 0; /* reuse as counter */
-	out_be32((void *)CFG_DSPIC_TEST_ADDR,
-		in_be32((void *)CFG_DSPIC_TEST_ADDR)
-			& ~CFG_DSPIC_TEST_MASK);
-	while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY) && reg++ < 1000) {
+	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
+			& ~CONFIG_SYS_DSPIC_TEST_MASK);
+	while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
 		udelay(1000);
 	}
-	gpio_write_bit(CFG_GPIO_HIGHSIDE, 0);
-	if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) {
+	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
+	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
 		/* set "boot error" flag */
-		out_be32((void *)CFG_DSPIC_TEST_ADDR,
-			in_be32((void *)CFG_DSPIC_TEST_ADDR) |
-			CFG_DSPIC_TEST_MASK);
+		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+			in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
+			CONFIG_SYS_DSPIC_TEST_MASK);
 	}
 #endif
 
@@ -123,14 +123,14 @@ int board_early_init_f(void)
 	 * MDIO address. A 2nd reset at this time will make sure, that the
 	 * correct address is latched.
 	 */
-	gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
 	udelay(1000);
-	gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
-	gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
 	udelay(1000);
-	gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
 
 	return 0;
 }
@@ -194,7 +194,7 @@ int misc_init_r(void)
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[1]);
 
@@ -338,7 +338,7 @@ int pci_pre_init(struct pci_controller *hose)
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -352,14 +352,14 @@ void pci_target_init(struct pci_controller *hose)
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
@@ -374,8 +374,8 @@ void pci_target_init(struct pci_controller *hose)
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -389,13 +389,13 @@ void pci_target_init(struct pci_controller *hose)
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -410,7 +410,7 @@ void pci_master_init(struct pci_controller *hose)
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host
@@ -460,8 +460,8 @@ void hw_watchdog_reset(void)
 	/*
 	 * Toggle watchdog output
 	 */
-	val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
-	gpio_write_bit(CFG_GPIO_WATCHDOG, val);
+	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
+	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
 }
 
 int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -472,9 +472,9 @@ int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	}
 
 	if ((strcmp(argv[1], "on") == 0)) {
-		gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1);
+		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
 	} else if ((strcmp(argv[1], "off") == 0)) {
-		gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0);
+		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
 	} else {
 		printf("Usage:\n%s\n", cmdtp->usage);
 		return 1;
@@ -528,23 +528,23 @@ unsigned int board_video_init (void)
 	/*
 	 * Reset Lime controller
 	 */
-	gpio_write_bit(CFG_GPIO_LIME_S, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
 	udelay(500);
-	gpio_write_bit(CFG_GPIO_LIME_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
 
 	/* Lime memory clock adjusted to 100MHz */
-	out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
+	out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ);
 	/* Wait untill time expired. Because of requirements in lime manual */
 	udelay(300);
 	/* Write lime controller memory parameters */
-	out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
 
 	mb862xx.winSizeX = 640;
 	mb862xx.winSizeY = 480;
 	mb862xx.gdfBytesPP = 2;
 	mb862xx.gdfIndex = GDF_15BIT_555RGB;
 
-	return CFG_LIME_BASE_0;
+	return CONFIG_SYS_LIME_BASE_0;
 }
 
 #define DEFAULT_BRIGHTNESS 0x64
@@ -553,12 +553,12 @@ static void board_backlight_brightness(int brightness)
 {
 	if (brightness > 0) {
 		/* pwm duty, lamp on */
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), brightness);
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
 	} else {
 		/* lamp off */
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x00);
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x00);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
 	}
 }
 
@@ -595,5 +595,5 @@ void video_get_info_str (int line_number, char *info)
 
 void board_reset(void)
 {
-	gpio_write_bit(CFG_GPIO_BOARD_RESET, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
 }
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 189e824073..72968d7803 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -45,10 +45,10 @@
  * memory.
  *
  * If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
  * everything correctly.
  */
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
 #define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
 #else
 #define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
@@ -116,7 +116,7 @@ static void program_ecc(u32 start_address,
 	 * Because of 440EPx errata CHIP 11, we don't touch the last 256
 	 * bytes of SDRAM.
 	 */
-	bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
+	bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
 
 	/*
 	 * We have to write the ECC bytes by zeroing and flushing in smaller
@@ -252,29 +252,29 @@ phys_size_t initdram (int board_type)
 	/* -----------------------------------------------------------+
 	 * Perform data eye search if requested.
 	 * ----------------------------------------------------------*/
-	program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
 		    TLB_WORD2_I_ENABLE);
 	denali_core_search_data_eye();
-	remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
 #endif
 
 	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
-	program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
 		    MY_TLB_WORD2_I_ENABLE);
 
 	/*
 	 * Setup 2nd TLB with same physical address but different virtual address
 	 * with cache enabled. This is done for fast ECC generation.
 	 */
-	program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 
 #ifdef CONFIG_DDR_ECC
 	/*
 	 * If ECC is enabled, initialize the parity bits.
 	 */
-	program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 #endif
 
 	/*
@@ -284,5 +284,5 @@ phys_size_t initdram (int board_type)
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CFG_MBYTES_SDRAM << 20);
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
diff --git a/board/lwmon5/u-boot.lds b/board/lwmon5/u-boot.lds
index b20fb1c0a2..3cfec834e2 100644
--- a/board/lwmon5/u-boot.lds
+++ b/board/lwmon5/u-boot.lds
@@ -137,7 +137,7 @@ SECTIONS
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);