Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Conflicts:
	boards.cfg

24 files changed, 475 insertions, 1070 deletions

diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index b2d5378143..9d6b9a7b66 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -488,6 +488,9 @@ int configure_vsc3316_3308(void)
 	}
 
 	switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+	case 0x9d:
+#endif
 	case 0x9E:
 	case 0x9A:
 	case 0x98:
@@ -852,6 +855,9 @@ int config_serdes2_refclks(void)
 	 * For this SerDes2's Refclk1 need to be set to 100MHz
 	 */
 	switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+	case 0x9d:
+#endif
 	case 0x9E:
 	case 0x9A:
 	case 0xb2:
diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile
new file mode 100644
index 0000000000..701b35cd59
--- /dev/null
+++ b/board/freescale/ls2085a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls2085a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README
new file mode 100644
index 0000000000..b7023e1d48
--- /dev/null
+++ b/board/freescale/ls2085a/README
@@ -0,0 +1,16 @@
+Freescale ls2085a_emu
+
+This is a emulator target with limited peripherals.
+
+Memory map from core's view
+
+0x00_0000_0000 .. 0x00_000F_FFFF	Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF	CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF	OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF	IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF	DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF	IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF	DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c
new file mode 100644
index 0000000000..257bc162d0
--- /dev/null
+++ b/board/freescale/ls2085a/ddr.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 3) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	/*
+	 * we use identical timing for all slots. If needed, change the code
+	 * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+	 */
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[0];
+	else
+		pbsp = udimms[0];
+
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks &&
+		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+		"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+		pbsp->wrlvl_ctl_3);
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+#else
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 1073741824u,
+	.capacity = 2147483648,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 0,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 0,
+	.burst_lengths_bitmask = 0x0c,
+
+	.tckmin_x_ps = 937,
+	.caslat_x = 0x6FC << 4,  /* 14,13,11,10,9,8,7,6 */
+	.taa_ps = 13090,
+	.twr_ps = 15000,
+	.trcd_ps = 13090,
+	.trrd_ps = 5000,
+	.trp_ps = 13090,
+	.tras_ps = 33000,
+	.trc_ps = 46090,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tfaw_ps = 25000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "Fixed DDR on board";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+	    ((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+#endif
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing DDR....");
+
+	puts("using SPD\n");
+	dram_size = fsl_ddr_sdram();
+
+	return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+		gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+		gd->bd->bi_dram[1].size = gd->ram_size -
+					  CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+	} else {
+		gd->bd->bi_dram[0].size = gd->ram_size;
+	}
+}
diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2085a/ddr.h
new file mode 100644
index 0000000000..77f6aafe3d
--- /dev/null
+++ b/board/freescale/ls2085a/ddr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{2,  2140, 0, 4,     4, 0x0, 0x0},
+	{1,  2140, 0, 4,     4, 0x0, 0x0},
+	{}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+	 */
+	{4,  2140, 0, 5,     4, 0x0, 0x0},
+	{2,  2140, 0, 5,     4, 0x0, 0x0},
+	{1,  2140, 0, 4,     4, 0x0, 0x0},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
new file mode 100644
index 0000000000..a18db1d714
--- /dev/null
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_mc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	init_final_memctl_regs();
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	init_early_memctl_regs();	/* tighten IFC timing */
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	printf("DRAM:  ");
+	gd->ram_size = initdram(0);
+
+	return 0;
+}
+
+int timer_init(void)
+{
+	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+
+	out_le32(cltbenr, 0x1);		/* enable cluster0 timebase */
+	out_le32(cntcr, 0x1);		/* enable clock for timer */
+
+	return 0;
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int error = 0;
+
+#ifdef CONFIG_SMC91111
+	error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+	error = cpu_eth_init(bis);
+#endif
+	return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+	int offset;
+
+	offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+	if (get_mc_boot_status() == 0)
+		fdt_status_okay(fdt, offset);
+	else
+		fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_FSL_MC_ENET
+	fdt_fixup_board_enet(blob);
+#endif
+}
+#endif
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 387e454cef..16bba59ba8 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -177,7 +177,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 {
 	FPWV *addr;
 	int flag, prot, sect, count;
-	ulong type, start, last;
+	ulong type, start;
 	int rcode = 0, flashtype = 0;
 
 	if ((s_first < 0) || (s_first > s_last)) {
@@ -217,7 +217,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	flag = disable_interrupts();
 
 	start = get_timer(0);
-	last = start;
 
 	if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
 		if (prot == 0) {
@@ -319,14 +318,13 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong wp, count;
 	u16 data;
-	int rc, port_width;
+	int rc;
 
 	if (info->flash_id == FLASH_UNKNOWN)
 		return 4;
 
 	/* get lower word aligned address */
 	wp = addr;
-	port_width = sizeof(FPW);
 
 	/* handle unaligned start bytes */
 	if (wp & 1) {
diff --git a/board/freescale/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile
deleted file mode 100644
index 007d9580ae..0000000000
--- a/board/freescale/mpc8260ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8260ads.o flash.o
diff --git a/board/freescale/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c
deleted file mode 100644
index 4012d45868..0000000000
--- a/board/freescale/mpc8260ads/flash.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * (C) Copyright 2003 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Re-written to support multi-bank flash SIMMs.
- * Added support for real protection and JFFS2.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT  0x89898989
-#define INTEL_ALT     0xB0B0B0B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x10101010
-#define INTEL_ERASE   0x20202020
-#define INTEL_CLEAR   0x50505050
-#define INTEL_LOCKBIT 0x60606060
-#define INTEL_PROTECT 0x01010101
-#define INTEL_STATUS  0x70707070
-#define INTEL_READID  0x90909090
-#define INTEL_CONFIRM 0xD0D0D0D0
-#define INTEL_RESET   0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x80808080
-#define INTEL_OK       0x80808080
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
- * Up to 32MB of flash supported (up to 4 banks.)
- * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
- *
- * The following code can not run from flash!
- */
-unsigned long flash_init (void)
-{
-	ulong size = 0, sect_start, sect_size = 0, bank_size;
-	ushort sect_count = 0;
-	int i, j, nbanks;
-	vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
-	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-	switch (bcsr[2] & 0xF) {
-	case 0:
-		nbanks = 4;
-		break;
-	case 1:
-		nbanks = 2;
-		break;
-	case 2:
-		nbanks = 1;
-		break;
-	default:		/* Unsupported configurations */
-		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-	}
-
-	if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
-		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-
-	for (i = 0; i < nbanks; i++) {
-		*addr = INTEL_READID;	/* Read Intelligent Identifier */
-		if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
-			switch (addr[1]) {
-			case SHARP_ID_28F016SCL:
-			case SHARP_ID_28F016SCZ:
-				flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
-				sect_count = 32;
-				sect_size = 0x40000;
-				break;
-			default:
-				flash_info[i].flash_id = FLASH_UNKNOWN;
-				sect_count = CONFIG_SYS_MAX_FLASH_SECT;
-				sect_size =
-				   CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
-			}
-		}
-		else
-			flash_info[i].flash_id = FLASH_UNKNOWN;
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
-			       addr[0], addr[1], (ulong)addr);
-			size = 0;
-			*addr = INTEL_RESET; /* Reset bank to Read Array mode */
-			break;
-		}
-		flash_info[i].sector_count = sect_count;
-		flash_info[i].size = bank_size = sect_size * sect_count;
-		size += bank_size;
-		sect_start = (ulong)addr;
-		for (j = 0; j < sect_count; j++) {
-			addr = (vu_long *)sect_start;
-			flash_info[i].start[j]   = sect_start;
-			flash_info[i].protect[j] = (addr[2] == 0x01010101);
-			sect_start += sect_size;
-		}
-		*addr = INTEL_RESET; /* Reset bank to Read Array mode */
-		addr = (vu_long *)sect_start;
-	}
-
-	if (size == 0) {	/* Unknown flash, fill with hard-coded values */
-		sect_start = CONFIG_SYS_FLASH_BASE;
-		for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-			flash_info[i].flash_id = FLASH_UNKNOWN;
-			flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
-			flash_info[i].sector_count = sect_count;
-			for (j = 0; j < sect_count; j++) {
-				flash_info[i].start[j]   = sect_start;
-				flash_info[i].protect[j] = 0;
-				sect_start += sect_size;
-			}
-		}
-		size = CONFIG_SYS_FLASH_SIZE;
-	}
-	else
-		for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-			flash_info[i].flash_id = FLASH_UNKNOWN;
-			flash_info[i].size = 0;
-			flash_info[i].sector_count = 0;
-		}
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-		      &flash_info[0]);
-#endif
-	return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
-	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
-				break;
-	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
-				break;
-	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
-				break;
-	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
-	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			vu_long *addr = (vu_long *)(info->start[sect]);
-
-			last = start = get_timer (0);
-
-			/* Disable interrupts which might cause a timeout here */
-			flag = disable_interrupts();
-
-			/* Clear Status Register */
-			*addr = INTEL_CLEAR;
-			/* Single Block Erase Command */
-			*addr = INTEL_ERASE;
-			/* Confirm */
-			*addr = INTEL_CONFIRM;
-
-			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
-			    /* Resume Command, as per errata update */
-			    *addr = INTEL_CONFIRM;
-			}
-
-			/* re-enable interrupts if necessary */
-			if (flag)
-				enable_interrupts();
-
-			while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					*addr = INTEL_RESET;	/* reset bank */
-					return 1;
-				}
-				/* show that we're waiting */
-				if ((now - last) > 1000) {	/* every second */
-					putc ('.');
-					last = now;
-				}
-			}
-
-			if (*addr != INTEL_OK) {
-				printf("Block erase failed at %08X, CSR=%08X\n",
-				       (uint)addr, (uint)*addr);
-				*addr = INTEL_RESET;	/* reset bank */
-				return 1;
-			}
-
-			/* reset to read mode */
-			*addr = INTEL_RESET;
-		}
-	}
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	ulong start;
-	int rc = 0;
-	int flag;
-	vu_long *addr = (vu_long *)dest;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		return (2);
-	}
-
-	*addr = INTEL_CLEAR; /* Clear status register */
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Write Command */
-	*addr = INTEL_PROGRAM;
-
-	/* Write Data */
-	*addr = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			printf("Write timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-	if (*addr != INTEL_OK) {
-		printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
-		rc = 1;
-	}
-
-	*addr = INTEL_RESET; /* Reset to read array mode */
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	rc = write_word(info, wp, data);
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
-	ulong start;
-	int i;
-	int rc = 0;
-	vu_long *addr = (vu_long *)(info->start[sector]);
-	int flag = disable_interrupts();
-
-	*addr = INTEL_CLEAR;	/* Clear status register */
-	if (prot) {			/* Set sector lock bit */
-		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
-		*addr = INTEL_PROTECT;	/* set */
-	}
-	else {				/* Clear sector lock bit */
-		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
-		*addr = INTEL_CONFIRM;	/* clear */
-	}
-
-	start = get_timer(0);
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-			printf("Flash lock bit operation timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-
-	if (*addr != INTEL_OK) {
-		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
-		       (uint)addr, (uint)*addr);
-		rc = 1;
-	}
-
-	if (!rc)
-		info->protect[sector] = prot;
-
-	/*
-	 * Clear lock bit command clears all sectors lock bits, so
-	 * we have to restore lock bits of protected sectors.
-	 */
-	if (!prot)
-		for (i = 0; i < info->sector_count; i++)
-			if (info->protect[i]) {
-				addr = (vu_long *)(info->start[i]);
-				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
-				*addr = INTEL_PROTECT;	/* set */
-				udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
-			}
-
-	if (flag)
-		enable_interrupts();
-
-	*addr = INTEL_RESET;		/* Reset to read array mode */
-
-	return rc;
-}
diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c
deleted file mode 100644
index b8c8ce9603..0000000000
--- a/board/freescale/mpc8260ads/mpc8260ads.c
+++ /dev/null
@@ -1,544 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
-	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
-	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
-	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
-	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
-	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
-	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
-	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
-	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
-	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
-	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
-	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
-	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
-	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
-	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
-	/* PA9  */ { 0,          0,   0,   0,   0,   0 }, /* PA9 */
-	/* PA8  */ { 0,          0,   0,   0,   0,   0 }, /* PA8 */
-	/* PA7  */ { 0,          0,   0,   1,   0,   0 }, /* PA7 */
-	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
-	/* PA5  */ { 0,          0,   0,   1,   0,   0 }, /* PA5 */
-	/* PA4  */ { 0,          0,   0,   1,   0,   0 }, /* PA4 */
-	/* PA3  */ { 0,          0,   0,   1,   0,   0 }, /* PA3 */
-	/* PA2  */ { 0,          0,   0,   1,   0,   0 }, /* PA2 */
-	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
-	/* PA0  */ { 0,          0,   0,   1,   0,   0 }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
-	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
-	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
-	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
-	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
-	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
-	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
-	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
-	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
-	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
-	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
-	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
-	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
-	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
-	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
-	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
-	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
-	/* PC18 */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
-	/* PC17 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
-	/* PC16 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
-#else
-	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
-	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
-	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
-	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
-	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
-	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
-	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
-	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
-#else
-	/* PC10 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
-	/* PC9  */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8 */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7 */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6 */
-	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5 */
-	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4 */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3 */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2 */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1 */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0 */
-    },
-
-    /* Port D */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* PD29 */
-	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-void reset_phy (void)
-{
-	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-	/* Reset the PHY */
-#if CONFIG_SYS_PHY_ADDR == 0
-	bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
-	udelay(2);
-	bcsr[1] |=  FETH1_RST;
-#else
-	bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
-	udelay(2);
-	bcsr[3] |=  FETH2_RST;
-#endif /* CONFIG_SYS_PHY_ADDR == 0 */
-	udelay(1000);
-#ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-	/*
-	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
-	 * Enable autonegotiation.
-	 */
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-#else
-	/*
-	 * Ethernet PHY is configured (by means of configuration pins)
-	 * to work at 10Mb/s only. We reconfigure it using MII
-	 * to advertise all capabilities, including 100Mb/s, and
-	 * restart autonegotiation.
-	 */
-
-	/* Advertise all capabilities */
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
-
-	/* Do not bypass Rx/Tx (de)scrambler */
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER,  0x0000);
-
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-#endif /* CONFIG_MII */
-}
-
-#ifdef CONFIG_PCI
-typedef struct pci_ic_s {
-	unsigned long pci_int_stat;
-	unsigned long pci_int_mask;
-}pci_ic_t;
-#endif
-
-int board_early_init_f (void)
-{
-	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-#ifdef CONFIG_PCI
-	volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
-
-	/* mask alll the PCI interrupts */
-	pci_ic->pci_int_mask |= 0xfff00000;
-#endif
-#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
-	bcsr[1] &= ~RS232EN_1;
-#endif
-#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
-	bcsr[1] &= ~RS232EN_2;
-#endif
-
-#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-	if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-	{
-		volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
-		immap->im_siu_conf.sc_siumcr =
-			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
-			| SIUMCR_LBPC01;
-	}
-#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
-
-	return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-#if   CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-	long int msize = 32;
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	long int msize = 64;
-#else
-	long int msize = 16;
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar *ramaddr, c = 0xff;
-	uint or;
-	uint psdmr;
-	uint psrt;
-
-	int i;
-
-	immap->im_siu_conf.sc_ppc_acr  = 0x00000002;
-	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifdef CONFIG_SYS_LSDRAM_BASE
-	/*
-	  Initialise local bus SDRAM only if the pins
-	  are configured as local bus pins and not as PCI.
-	  The configuration is determined by the HRCW.
-	*/
-	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
-		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
-		memctl->memc_or3   = 0xFF803280;
-		memctl->memc_br3   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#else				  /* CS4 */
-		memctl->memc_or4   = 0xFFC01480;
-		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
-		ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
-		for (i = 0; i < 8; i++)
-			*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
-	}
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
-	/* Init 60x bus SDRAM */
-#ifdef CONFIG_SPD_EEPROM
-	{
-		spd_eeprom_t spd;
-		uint pbi, bsel, rowst, lsb, tmp;
-
-		i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
-
-		/* Bank-based interleaving is not supported for physical bank
-		   sizes greater than 128MB which is encoded as 0x20 in SPD
-		 */
-		pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
-		msize = spd.nrows * (4 * spd.row_dens);	/* Mixed size not supported */
-		or = ~(msize - 1) << 20;	/* SDAM */
-		switch (spd.nbanks) {	/* BPD */
-		case 2:
-			bsel = 1;
-			break;
-		case 4:
-			bsel = 2;
-			or |= 0x00002000;
-			break;
-		case 8:
-			bsel = 3;
-			or |= 0x00004000;
-			break;
-		}
-		lsb = 3;	/* For 64-bit port, lsb is 3 bits */
-
-		if (pbi) {	/* Bus partition depends on interleaving */
-			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
-			or |= (rowst << 9);	/* ROWST */
-		} else {
-			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
-			or |= ((rowst * 2 - 12) << 9);	/* ROWST */
-		}
-		or |= ((spd.nrow_addr - 9) << 6);	/* NUMR */
-
-		psdmr = (pbi << 31);	/* PBI */
-		/* Bus multiplexing parameters */
-		tmp = 32 - (lsb + spd.nrow_addr);	/* Tables 10-19 and 10-20 */
-		psdmr |= ((tmp - (rowst - 5) - 13) << 24);	/* SDAM */
-		psdmr |= ((tmp - 3 - 12) << 21);	/* BSMA */
-
-		tmp = (31 - lsb - 10) - tmp;
-		/* Pin connected to SDA10 is (31 - lsb - 10).
-		   rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
-		   so (rowst + tmp) alternates with AP.
-		 */
-		if (pbi)				/* Table 10-7 */
-			psdmr |= ((10 - (rowst + tmp)) << 18);	/* SDA10 */
-		else
-			psdmr |= ((12 - (rowst + tmp)) << 18);	/* SDA10 */
-
-		/* SDRAM device-specific parameters */
-		tmp = ns2clk (70);	/* Refresh recovery is not in SPD, so assume 70ns */
-		switch (tmp) {		/* RFRC */
-		case 1:
-		case 2:
-			psdmr |= (1 << 15);
-			break;
-		case 3:
-		case 4:
-		case 5:
-		case 6:
-		case 7:
-		case 8:
-			psdmr |= ((tmp - 2) << 15);
-			break;
-		default:
-			psdmr |= (7 << 15);
-		}
-		psdmr |= (ns2clk (spd.trp) % 8 << 12);	/* PRETOACT */
-		psdmr |= (ns2clk (spd.trcd) % 8 << 9);	/* ACTTORW */
-		/* BL=0 because for 64-bit SDRAM burst length must be 4 */
-		/* LDOTOPRE ??? */
-		for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
-			tmp >>= 1;
-		switch (i) {			/* WRC */
-		case 0:
-		case 1:
-			psdmr |= (1 << 4);
-			break;
-		case 2:
-		case 3:
-			psdmr |= (i << 4);
-			break;
-		}
-		/* EAMUX=0 - no external address multiplexing */
-		/* BUFCMD=0 - no external buffers */
-		for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
-			tmp >>= 1;
-		psdmr |= i;				/* CL */
-
-		switch (spd.refresh & 0x7F) {
-		case 1:
-			tmp = 3900;
-			break;
-		case 2:
-			tmp = 7800;
-			break;
-		case 3:
-			tmp = 31300;
-			break;
-		case 4:
-			tmp = 62500;
-			break;
-		case 5:
-			tmp = 125000;
-			break;
-		default:
-			tmp = 15625;
-		}
-		psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
-				  ((memctl->memc_mptpr >> 8) + 1)) - 1;
-#ifdef SPD_DEBUG
-		printf ("\nDIMM type:       %-18.18s\n", spd.mpart);
-		printf ("SPD size:        %d\n", spd.info_size);
-		printf ("EEPROM size:     %d\n", 1 << spd.chip_size);
-		printf ("Memory type:     %d\n", spd.mem_type);
-		printf ("Row addr:        %d\n", spd.nrow_addr);
-		printf ("Column addr:     %d\n", spd.ncol_addr);
-		printf ("# of rows:       %d\n", spd.nrows);
-		printf ("Row density:     %d\n", spd.row_dens);
-		printf ("# of banks:      %d\n", spd.nbanks);
-		printf ("Data width:      %d\n",
-				256 * spd.dataw_msb + spd.dataw_lsb);
-		printf ("Chip width:      %d\n", spd.primw);
-		printf ("Refresh rate:    %02X\n", spd.refresh);
-		printf ("CAS latencies:   %02X\n", spd.cas_lat);
-		printf ("Write latencies: %02X\n", spd.write_lat);
-		printf ("tRP:             %d\n", spd.trp);
-		printf ("tRCD:            %d\n", spd.trcd);
-
-		printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
-#endif /* SPD_DEBUG */
-	}
-#else  /* !CONFIG_SPD_EEPROM */
-	or    = CONFIG_SYS_OR2;
-	psdmr = CONFIG_SYS_PSDMR;
-	psrt  = CONFIG_SYS_PSRT;
-#endif /* CONFIG_SPD_EEPROM */
-	memctl->memc_psrt = psrt;
-	memctl->memc_or2 = or;
-	memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
-	ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
-	memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | 0x18000000;	/* Mode Register write */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
-	*ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* return total 60x bus SDRAM size */
-	return (msize * 1024 * 1024);
-}
-
-int checkboard (void)
-{
-#if   CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
-	puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
-	puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-	puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	puts ("Board: Motorola MPC8272ADS\n");
-#else
-	puts ("Board: unknown\n");
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc8250_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-}
-#endif
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 61b83bfc63..8a4a8a2f07 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -70,6 +70,8 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
+	.hash : { *(.hash*) }
+
 	.end :
 	{
 		*(.__end)
@@ -100,7 +102,7 @@ SECTIONS
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
+	.gnu.hash : { *(.gnu.hash) }
 	.plt : { *(.plt*) }
 	.interp : { *(.interp*) }
 	.gnu : { *(.gnu*) }
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index d8c87458e8..2b883c719e 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -182,11 +182,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-	/* By default NOR is on, and NAND is disabled */
-#ifdef CONFIG_NAND_U_BOOT
-	do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
-	do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
-#endif
 #ifdef CONFIG_HAS_FSL_DR_USB
 	fdt_fixup_dr_usb(blob, bd);
 #endif
diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c
index 8b2bf50799..3c92c14ae3 100644
--- a/board/freescale/p1023rds/tlb.c
+++ b/board/freescale/p1023rds/tlb.c
@@ -36,7 +36,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_4M, 1),
 
-#ifndef CONFIG_NAND_SPL
 	/* *W*G* - BCSR and NOR flash on local bus*/
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
@@ -79,7 +78,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
 
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9fc879a4ef..ed52fef621 100644
--- a/board/freescale/t208xqds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
@@ -25,21 +25,21 @@ struct board_specific_parameters {
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
+	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
 	 */
-	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{2,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
-	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
-	{2,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
-	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{1,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
-	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
-	{1,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{2,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
+	{2,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
+	{2,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{2,  1700,  0,  4,  7,  0x080a0a0c,  0x0c0d0e0a},
+	{2,  1900,  0,  5,  9,  0x0a0b0c0e,  0x0f10120c},
+	{2,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
+	{1,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
+	{1,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
+	{1,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{1,  1700,  0,  4,  7,  0x080a0a0c,  0x0c0d0e0a},
+	{1,  1900,  0,  5,  9,  0x0a0b0c0e,  0x0f10120c},
+	{1,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
 	{}
 };
 
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index d7a804d22a..5879198e4d 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -416,6 +416,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
 
 	switch (srds_s1) {
+	case 0x1b:
 	case 0x1c:
 	case 0x95:
 	case 0xa2:
@@ -429,8 +430,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
+	case 0x50:
 	case 0x51:
+	case 0x5e:
 	case 0x5f:
+	case 0x64:
 	case 0x65:
 		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
@@ -439,6 +443,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
 	case 0x66:
+	case 0x67:
 		/*
 		 * XFI does not need a PHY to work, but to avoid U-boot use
 		 * default PHY address which is zero to a MAC when it found
@@ -453,6 +458,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC3, 6);
 		fm_info_set_phy_address(FM1_10GEC4, 7);
 		break;
+	case 0x6a:
 	case 0x6b:
 		fm_info_set_phy_address(FM1_10GEC1, 4);
 		fm_info_set_phy_address(FM1_10GEC2, 5);
@@ -470,6 +476,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
+	case 0x70:
 	case 0x71:
 		/* SGMII in Slot3 */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
@@ -625,6 +632,7 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 
 			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+			    (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
 			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 			    (srds_s1 == 0x71)) {
 				/* As XFI is in cage intead of a slot, so
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
index c2ad0fda55..972dedc687 100644
--- a/board/freescale/t208xqds/t2080_rcw.cfg
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
@@ -3,6 +3,6 @@ aa55aa55 010e0100
 #SerDes Protocol: 0x66_0x16
 #Core/DDR: 1533Mhz/2133MT/s
 12100017 15000000 00000000 00000000
-66160002 00008400 e8104000 c1000000
+66150002 00008400 e8104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 9cfc0bd7c3..135343949e 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -105,6 +105,7 @@ int brd_mux_lane_to_slot(void)
 		/* SerDes1 is not enabled */
 		break;
 #if defined(CONFIG_T2080QDS)
+	case 0x1b:
 	case 0x1c:
 	case 0xa2:
 		/* SD1(A:D) => SLOT3 SGMII
@@ -126,6 +127,7 @@ int brd_mux_lane_to_slot(void)
 		 */
 		QIXIS_WRITE(brdcfg[12], 0x3a);
 		break;
+	case 0x50:
 	case 0x51:
 		/* SD1(A:D) => SLOT3 XAUI
 		 * SD1(E)   => SLOT1 PCIe4
@@ -140,6 +142,7 @@ int brd_mux_lane_to_slot(void)
 		 */
 		QIXIS_WRITE(brdcfg[12], 0xfe);
 		break;
+	case 0x6a:
 	case 0x6b:
 		/* SD1(A:D) => XFI cage
 		 * SD1(E)   => SLOT1 PCIe4
@@ -184,6 +187,7 @@ int brd_mux_lane_to_slot(void)
 		 QIXIS_WRITE(brdcfg[12], 0x1a);
 		 break;
 #elif defined(CONFIG_T2081QDS)
+	case 0x50:
 	case 0x51:
 		/* SD1(A:D) => SLOT2 XAUI
 		 * SD1(E)   => SLOT1 PCIe4 x1
@@ -192,6 +196,7 @@ int brd_mux_lane_to_slot(void)
 		QIXIS_WRITE(brdcfg[12], 0x98);
 		QIXIS_WRITE(brdcfg[13], 0x70);
 		break;
+	case 0x6a:
 	case 0x6b:
 		/* SD1(A:D) => XFI SFP Module
 		 * SD1(E)   => SLOT1 PCIe4 x1
@@ -201,13 +206,6 @@ int brd_mux_lane_to_slot(void)
 		QIXIS_WRITE(brdcfg[13], 0x70);
 		break;
 	case 0x6c:
-		/* SD1(A:B) => XFI SFP Module
-		 * SD1(C:D) => SLOT2 SGMII
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xe8);
-		QIXIS_WRITE(brdcfg[13], 0x0);
-		break;
 	case 0x6d:
 		/* SD1(A:B) => XFI SFP Module
 		 * SD1(C:D) => SLOT2 SGMII
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
index cd62cc8641..15e1bf43dd 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -3,6 +3,6 @@ aa55aa55 010e0100
 #SerDes Protocol: 0x66_0x16
 #Core/DDR: 1533Mhz/1600MT/s
 120c0017 15000000 00000000 00000000
-66160002 00008400 ec104000 c1000000
+66150002 00008400 ec104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 24cf907430..6210e4618f 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -449,7 +449,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot1 and Slot2 */
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
@@ -465,6 +467,7 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
+	case 37:
 	case 38:
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
@@ -479,8 +482,11 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][3]);
 		}
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
@@ -585,12 +591,17 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 		break;
+	case 6:
 	case 7:
+	case 12:
 	case 13:
 	case 14:
+	case 15:
 	case 16:
+	case 21:
 	case 22:
 	case 23:
+	case 24:
 	case 25:
 	case 26:
 		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
@@ -600,7 +611,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -612,6 +625,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
+	case 37:
 	case 38:
 		/* QSGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -623,8 +637,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* SGMII in Slot3 */
 		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
@@ -637,8 +654,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 79b770b488..fe1bc7f08d 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -354,14 +354,18 @@ int config_frontside_crossbar_vsc3316(void)
 			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 	switch (srds_prtcl_s1) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot1 */
 		vsc3316_fsm1_tx[0][1] = 14;
 		vsc3316_fsm1_tx[6][1] = 0;
 		vsc3316_fsm1_rx[1][1] = 2;
 		vsc3316_fsm1_rx[6][1] = 13;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* swap first lane and third lane on slot2 */
 		vsc3316_fsm1_tx[2][1] = 8;
@@ -382,17 +386,24 @@ int config_frontside_crossbar_vsc3316(void)
 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 	switch (srds_prtcl_s2) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot3 */
 		vsc3316_fsm2_tx[2][1] = 11;
 		vsc3316_fsm2_tx[5][1] = 4;
 		vsc3316_fsm2_rx[2][1] = 9;
 		vsc3316_fsm2_rx[4][1] = 7;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		/* swap first lane and third lane on slot4 */
 		vsc3316_fsm2_tx[6][1] = 3;
@@ -425,6 +436,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes3 is not enabled */
 		break;
+	case 1:
 	case 2:
 	case 9:
 	case 10:
@@ -434,13 +446,20 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD3MX_SLOT5;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 17:
+	case 18:
 	case 19:
 	case 20:
 		/* SD3(4:7) => SLOT6(0:3) */
@@ -462,6 +481,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes4 is not enabled */
 		break;
+	case 1:
 	case 2:
 		/* 10b, SD4(0:7) => SLOT7(0:7) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -469,8 +489,11 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT7;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
 		/* x1b, SD4(4:7) => SLOT8(0:3) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -478,9 +501,13 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT8;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 9:
 	case 10:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 18:
 		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 3e56817204..6f09a7bba2 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  1_28_6_12
+#serdes protocol  1_27_5_11
 16070019 18101916 00000000 00000000
-04383060 30548c00 ec020000 f5000000
+04362858 30548c00 ec020000 f5000000
 00000000 ee0000ee 00000000 000307fc
 00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index d220475b5a..142c6a877b 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
 	/* Register the 10G MDIO bus */
 	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
-	if (srds_prtcl_s1 == 28) {
+	if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
 		/* SGMII */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index 13408bd01f..fdbbe5ef65 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  28_56_2_10
+#serdes protocol  27_56_1_9
 16070019 18101916 00000000 00000000
-70701050 00448c00 6c020000 f5000000
+6c700848 00448c00 6c020000 f5000000
 00000000 ee0000ee 00000000 000287fc
 00000000 50000000 00000000 00000028
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index d64d3aa872..54a9f2c7c3 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -278,6 +278,26 @@ static void setup_iomux_i2c(void)
 	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
 }
 
+static void setup_iomux_qspi(void)
+{
+	static const iomux_v3_cfg_t qspi0_pads[] = {
+		VF610_PAD_PTD0__QSPI0_A_QSCK,
+		VF610_PAD_PTD1__QSPI0_A_CS0,
+		VF610_PAD_PTD2__QSPI0_A_DATA3,
+		VF610_PAD_PTD3__QSPI0_A_DATA2,
+		VF610_PAD_PTD4__QSPI0_A_DATA1,
+		VF610_PAD_PTD5__QSPI0_A_DATA0,
+		VF610_PAD_PTD7__QSPI0_B_QSCK,
+		VF610_PAD_PTD8__QSPI0_B_CS0,
+		VF610_PAD_PTD9__QSPI0_B_DATA3,
+		VF610_PAD_PTD10__QSPI0_B_DATA2,
+		VF610_PAD_PTD11__QSPI0_B_DATA1,
+		VF610_PAD_PTD12__QSPI0_B_DATA0,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
+}
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{ESDHC1_BASE_ADDR},
@@ -321,7 +341,8 @@ static void clock_init(void)
 	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
 		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
 		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
-		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
+		CCM_CCGR2_QSPI0_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
 		CCM_CCGR3_ANADIG_CTRL_MASK);
 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
@@ -352,11 +373,14 @@ static void clock_init(void)
 		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
 		CCM_CACRR_ARM_CLK_DIV(0));
 	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
-		CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+		CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
 	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
 		CCM_CSCDR1_RMII_CLK_EN);
 	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
 		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
+		CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
+		CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
 		CCM_CSCMR2_RMII_CLK_SEL(0));
 }
@@ -386,6 +410,7 @@ int board_early_init_f(void)
 	setup_iomux_uart();
 	setup_iomux_enet();
 	setup_iomux_i2c();
+	setup_iomux_qspi();
 
 	return 0;
 }