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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2013-05-03 10:32:35 +0000
committerStefano Babic <sbabic@denx.de>2013-05-05 17:55:05 +0200
commit544544a060688bea8643e211bb8ae94add17596a (patch)
tree56ed5f831df778e51e9e0fe9b12f4adb55c3fe85 /board/freescale/mx53smd/mx53smd.c
parent721d0b0026971924605701a0e409ded91e093caa (diff)
downloadblackbird-obmc-uboot-544544a060688bea8643e211bb8ae94add17596a.tar.gz
blackbird-obmc-uboot-544544a060688bea8643e211bb8ae94add17596a.zip
imx: mx53smd: Convert to iomux-v3
There is no change of behavior. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Diffstat (limited to 'board/freescale/mx53smd/mx53smd.c')
-rw-r--r--board/freescale/mx53smd/mx53smd.c152
1 files changed, 48 insertions, 104 deletions
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 761f727d08..d04f44fb3e 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -23,11 +23,10 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx53.h>
#include <asm/errno.h>
#include <netdev.h>
#include <mmc.h>
@@ -56,76 +55,41 @@ void dram_init_banksize(void)
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
static void setup_iomux_uart(void)
{
- /* UART1 RXD */
- mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
-
- /* UART1 TXD */
- mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
- mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
- PAD_CTL_ODE_OPENDRAIN_ENABLE);
+ static const iomux_v3_cfg_t uart_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
- /*FEC_MDIO*/
- mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
- mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
-
- /*FEC_MDC*/
- mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
-
- /* FEC RXD1 */
- mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RXD0 */
- mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC TXD1 */
- mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
-
- /* FEC TXD0 */
- mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_EN */
- mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
-
- /* FEC TX_CLK */
- mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC RX_ER */
- mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
-
- /* FEC CRS */
- mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
- PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
+ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
+ NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+ PAD_CTL_HYS | PAD_CTL_PKE),
+ };
+
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC
@@ -135,13 +99,28 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = {
int board_mmc_getcd(struct mmc *mmc)
{
- mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+ imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
gpio_direction_input(IMX_GPIO_NR(3, 13));
return !gpio_get_value(IMX_GPIO_NR(3, 13));
}
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH)
+
int board_mmc_init(bd_t *bis)
{
+ static const iomux_v3_cfg_t sd1_pads[] = {
+ NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+ NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13,
+ };
+
u32 index;
s32 status = 0;
@@ -150,43 +129,8 @@ int board_mmc_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
- mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA0,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA1,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA2,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_SD1_DATA3,
- IOMUX_CONFIG_ALT0);
- mxc_request_iomux(MX53_PIN_EIM_DA13,
- IOMUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
- PAD_CTL_DRV_HIGH);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
- mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
- PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
- PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
- PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
+ imx_iomux_v3_setup_multiple_pads(sd1_pads,
+ ARRAY_SIZE(sd1_pads));
break;
default:
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