path: root/board/freescale/mpc8555cds/mpc8555cds.c
diff options
authorBecky Bruce <>2010-06-17 11:37:20 -0500
committerKumar Gala <>2010-07-16 10:55:09 -0500
commitf51cdaf19141151ce2b40d562a468605340f2315 (patch)
tree60b51af79796f061d119f2839d101f9584964dfc /board/freescale/mpc8555cds/mpc8555cds.c
parent0914f4832887341ee073d2d2bfbada69a6872548 (diff)
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <> Acked-by: Kim Phillips <> Signed-off-by: Kumar Gala <>
Diffstat (limited to 'board/freescale/mpc8555cds/mpc8555cds.c')
1 files changed, 4 insertions, 8 deletions
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index ecddd0d9c4..b7e0e0cd82 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -291,7 +291,7 @@ void
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv;
uint lbc_hz;
@@ -340,7 +340,7 @@ sdram_init(void)
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
uint idx;
- volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
uint cpu_board_rev;
uint lsdmr_common;
@@ -352,12 +352,8 @@ sdram_init(void)
* Setup SDRAM Base and Option Registers
- lbc->or2 = CONFIG_SYS_OR2_PRELIM;
- asm("msync");
- lbc->br2 = CONFIG_SYS_BR2_PRELIM;
- asm("msync");
+ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
+ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
OpenPOWER on IntegriCloud