path: root/board/freescale/mpc8555cds/mpc8555cds.c
diff options
authorPaul Gortmaker <>2011-12-16 17:31:53 -0500
committerKumar Gala <>2012-01-11 13:57:56 -0600
commit1667013ddfa95007c242d7772fb38e3e3bf72b48 (patch)
tree14ad9c7bb987e8529f3c7ce94a86c4e42b4995bd /board/freescale/mpc8555cds/mpc8555cds.c
parent0ecb55132bcb6292f642657bbbd9b58749b8e303 (diff)
MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
These boards were meaning to deploy this value: #define LCRR_DBYP 0x80000000 but were missing a zero, and hence toggling a bit that lands in an area marked as reserved in the 8548 reference manual. According to the documentation, LCRR_DBYP should be used as: PLL bypass. This bit should be set when using low bus clock frequencies if the PLL is unable to lock. When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle. It is recommended that PLL bypass mode be used at frequencies of 83 MHz or less. So the impact would most likely be undefined behaviour for LBC peripherals on boards that were running below 83MHz LBC. Looking at the actual u-boot code, the missing DBYP bit was meant to be deployed as follows: Between 66 and 133, the DLL is enabled with an override workaround. In the future, we'll convert all boards to use the symbolic DBYP constant to avoid these "count the zeros" problems, but for now, just fix the impacted boards. Signed-off-by: Paul Gortmaker <> Signed-off-by: Kumar Gala <>
Diffstat (limited to 'board/freescale/mpc8555cds/mpc8555cds.c')
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 48ede9840f..3361614de5 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -273,7 +273,7 @@ local_bus_init(void)
lbc->lcrr &= (~0x80000000); /* DLL Enabled */
} else {
- lbc->lcrr &= (~0x8000000); /* DLL Enabled */
+ lbc->lcrr &= (~0x80000000); /* DLL Enabled */
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