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authorKumar Gala <galak@kernel.crashing.org>2008-12-02 16:08:36 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:03:13 -0600
commit10795f42cb94e71bcb262b615084f69dd886399a (patch)
tree8954d541f7006c1838691799daca3bacb5667c1b /board/freescale/mpc8548cds
parentc953ddfd56b3ae3f28910fe3aed6de6968d1c9aa (diff)
downloadblackbird-obmc-uboot-10795f42cb94e71bcb262b615084f69dd886399a.tar.gz
blackbird-obmc-uboot-10795f42cb94e71bcb262b615084f69dd886399a.zip
85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards
Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8548cds')
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c4
-rw-r--r--board/freescale/mpc8548cds/tlb.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 90e89bc719..ff8d26fb9c 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -306,7 +306,7 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
@@ -390,7 +390,7 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index eab212a4c5..e96c9a7fca 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -62,14 +62,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 2: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS, CONFIG_SYS_RIO_MEM_BUS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BUS + 0x10000000, CONFIG_SYS_RIO_MEM_BUS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
#endif
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