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authorPeter Tyser <ptyser@xes-inc.com>2008-11-11 10:17:10 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-12-03 22:46:42 -0600
commita2cd50ed6ef0ac6b127b3d6db756979a8336718d (patch)
treea8064eb08a501fdecadfb50af56f646c90be0f3a /board/freescale/mpc8548cds/mpc8548cds.c
parente57f0fa1333cdf3ca36110aac2900712a5f82976 (diff)
downloadblackbird-obmc-uboot-a2cd50ed6ef0ac6b127b3d6db756979a8336718d.tar.gz
blackbird-obmc-uboot-a2cd50ed6ef0ac6b127b3d6db756979a8336718d.zip
85xx: Add CPU 2 errata workaround to all 8548 boards
All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8548cds/mpc8548cds.c')
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 86986057c2..ba6bff585c 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -52,7 +52,6 @@ int checkboard (void)
uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision ();
- uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
@@ -65,17 +64,6 @@ int checkboard (void)
*/
local_bus_init ();
- svr = get_svr();
-
- /*
- * Fix CPU2 errata: A core hang possible while executing a
- * msync instruction and a snoopable transaction from an I/O
- * master tagged to make quick forward progress is present.
- * Fixed in Silicon Rev.2.1
- */
- if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
- ecm->eebpcr |= (1 << 16);
-
/*
* Hack TSEC 3 and 4 IO voltages.
*/
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