powerpc: ppc4xx: remove csb272, csb472 support

These have not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tolunay Orkun <torkun@nextio.com>

5 files changed, 0 insertions, 354 deletions

diff --git a/board/csb472/Kconfig b/board/csb472/Kconfig
deleted file mode 100644
index 53b1e7ad9a..0000000000
--- a/board/csb472/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if TARGET_CSB472
-
-config SYS_BOARD
-	default "csb472"
-
-config SYS_CONFIG_NAME
-	default "csb472"
-
-endif
diff --git a/board/csb472/MAINTAINERS b/board/csb472/MAINTAINERS
deleted file mode 100644
index 25041ed824..0000000000
--- a/board/csb472/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CSB472 BOARD
-M:	Tolunay Orkun <torkun@nextio.com>
-S:	Maintained
-F:	board/csb472/
-F:	include/configs/csb472.h
-F:	configs/csb472_defconfig
diff --git a/board/csb472/Makefile b/board/csb472/Makefile
deleted file mode 100644
index 5f7e8b533e..0000000000
--- a/board/csb472/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= csb472.o
-obj-y	+= init.o
diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
deleted file mode 100644
index b1de18ce51..0000000000
--- a/board/csb472/csb472.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2004
- * Tolunay Orkun, Nextio Inc., torkun@nextio.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <miiphy.h>
-#include <asm/ppc4xx-emac.h>
-
-void sdram_init(void);
-
-/*
- * board_early_init_f: do early board initialization
- *
- */
-int board_early_init_f(void)
-{
-   /*-------------------------------------------------------------------------+
-   | Interrupt controller setup for the Walnut board.
-   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-   |       IRQ 16    405GP internally generated; active low; level sensitive
-   |       IRQ 17-24 RESERVED
-   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
-   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
-   |       IRQ 27 (EXT IRQ 2) Not Used
-   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
-   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
-   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
-   | Note for Walnut board:
-   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
-   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
-   |       interrupt. The FPGA must be read to determine which device
-   |       caused the interrupt. The default setting of the FPGA clears
-   |
-   +-------------------------------------------------------------------------*/
-
-	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
-	mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
-
-	mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
-
-	return 0; /* success */
-}
-
-/*
- * checkboard: identify/verify the board we are running
- *
- * Remark: we just assume it is correct board here!
- *
- */
-int checkboard(void)
-{
-	printf("BOARD: Cogent CSB472\n");
-
-	return 0; /* success */
-}
-
-/*
- * initram: Determine the size of mounted DRAM
- *
- * Size is determined by reading SDRAM configuration registers as
- * configured by initialization code
- *
- */
-phys_size_t initdram (int board_type)
-{
-	ulong tot_size;
-	ulong bank_size;
-	ulong tmp;
-
-	/*
-	 * ToDo: Move the asm init routine sdram_init() to this C file,
-	 * or even better use some common ppc4xx code available
-	 * in arch/powerpc/cpu/ppc4xx
-	 */
-	sdram_init();
-
-	tot_size = 0;
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
-	tmp = mfdcr (SDRAM0_CFGDATA);
-	if (tmp & 0x00000001) {
-		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
-		tot_size += bank_size;
-	}
-
-	return tot_size;
-}
-
-/*
- * last_stage_init: final configurations (such as PHY etc)
- *
- */
-int last_stage_init(void)
-{
-	/* initialize the PHY */
-	miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
-
-	/* AUTO neg */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
-	/* LEDs     */
-	miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
-
-	return 0; /* success */
-}
diff --git a/board/csb472/init.S b/board/csb472/init.S
deleted file mode 100644
index 7383a708b0..0000000000
--- a/board/csb472/init.S
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define LI32(reg,val) \
-	addis   reg,0,val@h;\
-	ori     reg,reg,val@l
-
-#define WDCR_EBC(reg,val) \
-	addi    r4,0,reg;\
-	mtdcr   EBC0_CFGADDR,r4;\
-	addis   r4,0,val@h;\
-	ori     r4,r4,val@l;\
-	mtdcr   EBC0_CFGDATA,r4
-
-#define WDCR_SDRAM(reg,val) \
-	addi    r4,0,reg;\
-	mtdcr   SDRAM0_CFGADDR,r4;\
-	addis   r4,0,val@h;\
-	ori     r4,r4,val@l;\
-	mtdcr   SDRAM0_CFGDATA,r4
-
-/******************************************************************************
- * Function:	ext_bus_cntlr_init
- *
- * Description:	Configures EBC Controller and a few basic chip selects.
- *
- *		CS0 is setup to get the Boot Flash out of the addresss range
- *		so that we may setup a stack.  CS7 is setup so that we can
- *		access and reset the hardware watchdog.
- *
- *		IMPORTANT: For pass1 this code must run from
- *		cache since you can not reliably change a peripheral banks
- *		timing register (pbxap) while running code from that bank.
- *		For ex., since we are running from ROM on bank 0, we can NOT
- *		execute the code that modifies bank 0 timings from ROM, so
- *		we run it from cache.
- *
- * Notes:	Does NOT use the stack.
- *****************************************************************************/
-	.section ".text"
-	.align	2
-	.globl	ext_bus_cntlr_init
-	.type	ext_bus_cntlr_init, @function
-ext_bus_cntlr_init:
-	mflr	r0
-	/********************************************************************
-	 * Prefetch entire ext_bus_cntrl_init function into the icache.
-	 * This is necessary because we are going to change the same CS we
-	 * are executing from.  Otherwise a CPU lockup may occur.
-	 *******************************************************************/
-	bl	..getAddr
-..getAddr:
-	mflr	r3			/* get address of ..getAddr */
-
-	/* Calculate number of cache lines for this function */
-	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
-	mtctr	r4
-..ebcloop:
-	icbt	r0, r3			/* prefetch cache line for addr in r3*/
-	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
-	bdnz	..ebcloop		/* continue for $CTR cache lines */
-
-	/********************************************************************
-	 * Delay to ensure all accesses to ROM are complete before changing
-	 * bank 0 timings. 200usec should be enough.
-	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
-	 *******************************************************************/
-	addis	r3, 0, 0x0
-	ori	r3, r3, 0xA000		/* wait 200us from reset */
-	mtctr	r3
-..spinlp:
-	bdnz	..spinlp		/* spin loop */
-
-	/********************************************************************
-	 * SETUP CPC0_CR0
-	 *******************************************************************/
-	LI32(r4, 0x00c01030)
-	mtdcr	CPC0_CR0, r4
-
-	/********************************************************************
-	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
-	 *******************************************************************/
-	mfdcr	r4, CPC0_CR1
-	ori	r4, r4, 0x4000
-	mtdcr	CPC0_CR1, r4
-
-	/********************************************************************
-	 * Setup External Bus Controller (EBC).
-	 *******************************************************************/
-	WDCR_EBC(EBC0_CFG, 0xd84c0000)
-	/********************************************************************
-	 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
-	 *******************************************************************/
-	/*WDCR_EBC(PB1AP, 0x03055200)*/
-	/*WDCR_EBC(PB1AP, 0x04055200)*/
-	WDCR_EBC(PB1AP, 0x08055200)
-	WDCR_EBC(PB0CR, 0xff87a000)
-	/********************************************************************
-	 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
-	 *******************************************************************/
-	/*WDCR_EBC(PB3AP, 0x07869200)*/
-	WDCR_EBC(PB3AP, 0x04055200)
-	WDCR_EBC(PB3CR, 0xf081c000)
-	/********************************************************************
-	 * Memory Bank 1,2,4-7 (Unused) initialization
-	 *******************************************************************/
-	WDCR_EBC(PB1AP, 0)
-	WDCR_EBC(PB1CR, 0)
-	WDCR_EBC(PB2AP, 0)
-	WDCR_EBC(PB2CR, 0)
-	WDCR_EBC(PB4AP, 0)
-	WDCR_EBC(PB4CR, 0)
-	WDCR_EBC(PB5AP, 0)
-	WDCR_EBC(PB5CR, 0)
-	WDCR_EBC(PB6AP, 0)
-	WDCR_EBC(PB6CR, 0)
-	WDCR_EBC(PB7AP, 0)
-	WDCR_EBC(PB7CR, 0)
-
-	/* We are all done */
-	mtlr	r0			/* Restore link register */
-	blr				/* Return to calling function */
-.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
-/* end ext_bus_cntlr_init() */
-
-/******************************************************************************
- * Function:	sdram_init
- *
- * Description:	Configures SDRAM memory banks.
- *
- * Notes:	Does NOT use the stack.
- *****************************************************************************/
-	.section ".text"
-	.align	2
-	.globl	sdram_init
-	.type	sdram_init, @function
-sdram_init:
-
-	/*
-	 * Disable memory controller to allow
-	 * values to be changed.
-	 */
-	WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
-
-	/*
-	 * Configure Memory Banks
-	 */
-	WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
-	WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
-	WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
-	WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
-
-	/*
-	 * Set up SDTR1 (SDRAM Timing Register)
-	 */
-	WDCR_SDRAM(SDRAM0_TR, 0x00854009)
-
-	/*
-	 * Set RTR (Refresh Timing Register)
-	 */
-	WDCR_SDRAM(SDRAM0_RTR,   0x10000000)
-	/* WDCR_SDRAM(SDRAM0_RTR,   0x05f00000) */
-
-	/********************************************************************
-	 * Delay to ensure 200usec have elapsed since reset. Assume worst
-	 * case that the core is running 200Mhz:
-	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
-	 *******************************************************************/
-	addis   r3, 0, 0x0000
-	ori     r3, r3, 0xA000		/* Wait >200us from reset */
-	mtctr   r3
-..spinlp2:
-	bdnz    ..spinlp2		/* spin loop */
-
-	/********************************************************************
-	 * Set memory controller options reg, MCOPT1.
-	 *******************************************************************/
-	WDCR_SDRAM(SDRAM0_CFG,0x80800000)
-
-..sdri_done:
-	blr				/* Return to calling function */
-.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
-/* end sdram_init() */