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authorStefan Roese <sr@denx.de>2009-09-09 16:25:29 +0200
committerStefan Roese <sr@denx.de>2009-09-11 10:35:58 +0200
commitd1c3b27525b664e8c4db6bb173eed51bfc8220de (patch)
treec00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/amcc/yucca
parente7963772eb78a6aa1fa65063d64eab3a8626daac (diff)
downloadblackbird-obmc-uboot-d1c3b27525b664e8c4db6bb173eed51bfc8220de.tar.gz
blackbird-obmc-uboot-d1c3b27525b664e8c4db6bb173eed51bfc8220de.zip
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/yucca')
-rw-r--r--board/amcc/yucca/flash.c2
-rw-r--r--board/amcc/yucca/yucca.c20
2 files changed, 11 insertions, 11 deletions
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index eda49eb174..33b97a5040 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -981,7 +981,7 @@ unsigned long flash_init(void)
* Boot Settings in IIC EEprom address 0xA8 or 0xA0
* Read Serial Device Strap Register1 in PPC440SPe
*/
- mfsdr(sdr_sdstp1, val);
+ mfsdr(SDR0_SDSTP1, val);
boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 06c7d625a4..245004cee8 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -167,7 +167,7 @@ int board_early_init_f (void)
| 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
|
+-------------------------------------------------------------------*/
- mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
+ mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_16PERCLK |
EBC_CFG_ATC_PREVIOUS |
@@ -188,8 +188,8 @@ int board_early_init_f (void)
| boot type
|
+-------------------------------------------------------------------*/
- mtebc(pb1ap, EBC_BXAP_FPGA);
- mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
+ mtebc(PB1AP, EBC_BXAP_FPGA);
+ mtebc(PB1CR, EBC_BXCR_FPGA_CS1);
/*-------------------------------------------------------------------+
|
@@ -334,10 +334,10 @@ int board_early_init_f (void)
break;
}
- mtebc(pb0ap, ebc0_cs0_bxap_value);
- mtebc(pb0cr, ebc0_cs0_bxcr_value);
- mtebc(pb2ap, ebc0_cs2_bxap_value);
- mtebc(pb2cr, ebc0_cs2_bxcr_value);
+ mtebc(PB0AP, ebc0_cs0_bxap_value);
+ mtebc(PB0CR, ebc0_cs0_bxcr_value);
+ mtebc(PB2AP, ebc0_cs2_bxap_value);
+ mtebc(PB2CR, ebc0_cs2_bxcr_value);
/*--------------------------------------------------------------------+
| Interrupt controller setup for the AMCC 440SPe Evaluation board.
@@ -530,9 +530,9 @@ int board_early_init_f (void)
mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
- mfsdr(sdr_mfr, mfr);
+ mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
- mtsdr(sdr_mfr, mfr);
+ mtsdr(SDR0_MFR, mfr);
fpga_init();
@@ -608,7 +608,7 @@ int pci_pre_init(struct pci_controller * hose )
* The yucca board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
- mfsdr(sdr_sdstp1, strap);
+ mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
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