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authorAbhimanyu Saini <abhimanyu.saini@nxp.com>2016-06-14 13:18:31 +0530
committerYork Sun <york.sun@nxp.com>2016-06-28 12:08:54 -0700
commitdee01e426b39eac974364c0658fca431894987c3 (patch)
tree5c756e9740a9c8477e03421daf9dc172b76c932a /arch
parent49cdce163519ad760ca7769be64dd2a6133a5c11 (diff)
downloadblackbird-obmc-uboot-dee01e426b39eac974364c0658fca431894987c3.tar.gz
blackbird-obmc-uboot-dee01e426b39eac974364c0658fca431894987c3.zip
armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs
Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/fsl-ls1012a.dtsi12
-rw-r--r--arch/arm/dts/fsl-ls1043a.dtsi32
-rw-r--r--arch/arm/dts/fsl-ls2080a.dtsi61
3 files changed, 0 insertions, 105 deletions
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 546a87a0a5..024527e815 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -9,18 +9,6 @@
/ {
compatible = "fsl,ls1012a";
interrupt-parent = <&gic>;
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- clocks = <&clockgen 1 0>;
- };
-
- };
sysclk: sysclk {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index bf1dfe6db6..a8bffbafa7 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -15,38 +15,6 @@
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <&gic>;
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x0>;
- clocks = <&clockgen 1 0>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x1>;
- clocks = <&clockgen 1 0>;
- };
-
- cpu2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x2>;
- clocks = <&clockgen 1 0>;
- };
-
- cpu3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0 0x3>;
- clocks = <&clockgen 1 0>;
- };
- };
sysclk: sysclk {
compatible = "fixed-clock";
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 68ed133853..b308c8b982 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -12,67 +12,6 @@
#address-cells = <2>;
#size-cells = <2>;
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- /*
- * We expect the enable-method for cpu's to be "psci", but this
- * is dependent on the SoC FW, which will fill this in.
- *
- * Currently supported enable-method is psci v0.2
- */
-
- /* We have 4 clusters having 2 Cortex-A57 cores each */
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x1>;
- };
-
- cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x100>;
- };
-
- cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x101>;
- };
-
- cpu@200 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x200>;
- };
-
- cpu@201 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x201>;
- };
-
- cpu@300 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x300>;
- };
-
- cpu@301 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x301>;
- };
- };
-
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x80000000>;
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