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| author | Rajeshwari S Shinde <rajeshwari.s@samsung.com> | 2014-02-05 10:48:15 +0530 |
|---|---|---|
| committer | Pantelis Antoniou <panto@antoniou-consulting.com> | 2014-02-07 17:42:26 +0200 |
| commit | d3e016cc28684cd32d826a9414a0e89ccf80861a (patch) | |
| tree | 8ed71c5f9ff24fded82a3f6730cd28744e17a2cc /arch | |
| parent | def816a2ba87c2a3507536e8cb226f0f85bdae2c (diff) | |
| download | blackbird-obmc-uboot-d3e016cc28684cd32d826a9414a0e89ccf80861a.tar.gz blackbird-obmc-uboot-d3e016cc28684cd32d826a9414a0e89ccf80861a.zip | |
MMC: DWMMC: Correct the CLKDIV register value
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)
Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.
This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144sec
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/dwmmc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 09d739dfca..a7ca12c477 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -23,6 +23,10 @@ #define MPSCTRL_ENCRYPTION (0x1<<1) #define MPSCTRL_VALID (0x1<<0) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif |
