Merge branch 'master' of git://git.denx.de/u-boot-arm

51 files changed, 442 insertions, 900 deletions

diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index ce3903ba9f..d0cf43ff41 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -16,7 +16,8 @@ endif
 endif
 
 LDFLAGS_FINAL += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
+                     -fno-common -ffixed-r9 -msoft-float
 
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
@@ -94,7 +95,11 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
 endif
 endif
 
-# check that only R_ARM_RELATIVE relocations are generated
 ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-y	+= checkarmreloc
+# Check that only R_ARM_RELATIVE relocations are generated.
+ALL-y += checkarmreloc
+# The movt / movw can hardcode 16 bit parts of the addresses in the
+# instruction. Relocation is not supported for that case, so disable
+# such usage by requiring word relocations.
+PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
 endif
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
index 1ef6061365..b4d396de84 100644
--- a/arch/arm/cpu/arm1136/config.mk
+++ b/arch/arm/cpu/arm1136/config.mk
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk
index 917da030d6..f4631cb777 100644
--- a/arch/arm/cpu/arm1176/config.mk
+++ b/arch/arm/cpu/arm1176/config.mk
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5t
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk
index 56b6280d5a..2581f0ae67 100644
--- a/arch/arm/cpu/arm720t/config.mk
+++ b/arch/arm/cpu/arm720t/config.mk
@@ -6,8 +6,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS +=  -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
 # =========================================================================
 #
diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk
index 58fd756586..67537dcedc 100644
--- a/arch/arm/cpu/arm920t/config.mk
+++ b/arch/arm/cpu/arm920t/config.mk
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4
 # =========================================================================
 #
diff --git a/arch/arm/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk
index 58fd756586..67537dcedc 100644
--- a/arch/arm/cpu/arm925t/config.mk
+++ b/arch/arm/cpu/arm925t/config.mk
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4
 # =========================================================================
 #
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
index 917ff7edec..12b0d09d37 100644
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ b/arch/arm/cpu/arm926ejs/config.mk
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv5te
 # =========================================================================
 #
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
index 8db2a67f37..629b727745 100644
--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
@@ -38,5 +38,10 @@ int main(void)
 	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
 	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
 
+	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, gpcr));
+	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+		offsetof(struct system_control_regs, fmcr));
+
 	return 0;
 }
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 0392afd9be..68c30afc48 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -102,8 +102,9 @@ static uint8_t mxs_get_bootmode_index(void)
 	return i;
 }
 
-void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
-			const unsigned int iomux_size)
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+			 const iomux_cfg_t *iomux_setup,
+			 const unsigned int iomux_size)
 {
 	struct mxs_spl_data *data = (struct mxs_spl_data *)
 		((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index f357959059..4275c5d0a6 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -14,6 +14,13 @@
 
 #include "mxs_init.h"
 
+/**
+ * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
+ *
+ * This function switches the CPU core clock from PLL to 24MHz XTAL
+ * oscilator. This is necessary if the PLL is being reconfigured to
+ * prevent crash of the CPU core.
+ */
 static void mxs_power_clock2xtal(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
@@ -24,6 +31,13 @@ static void mxs_power_clock2xtal(void)
 		&clkctrl_regs->hw_clkctrl_clkseq_set);
 }
 
+/**
+ * mxs_power_clock2pll() - Switch CPU core clock source to PLL
+ *
+ * This function switches the CPU core clock from 24MHz XTAL oscilator
+ * to PLL. This can only be called once the PLL has re-locked and once
+ * the PLL is stable after reconfiguration.
+ */
 static void mxs_power_clock2pll(void)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
@@ -36,6 +50,13 @@ static void mxs_power_clock2pll(void)
 			CLKCTRL_CLKSEQ_BYPASS_CPU);
 }
 
+/**
+ * mxs_power_set_auto_restart() - Set the auto-restart bit
+ *
+ * This function ungates the RTC block and sets the AUTO_RESTART
+ * bit to work around a design bug on MX28EVK Rev. A .
+ */
+ 
 static void mxs_power_set_auto_restart(void)
 {
 	struct mxs_rtc_regs *rtc_regs =
@@ -66,6 +87,14 @@ static void mxs_power_set_auto_restart(void)
 		;
 }
 
+/**
+ * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
+ *
+ * This function configures the VDDIO, VDDA and VDDD linear regulators output
+ * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
+ * converter. This is the recommended setting for the case where we use both
+ * linear regulators and DC-DC converter to power the VDDIO rail.
+ */
 static void mxs_power_set_linreg(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -85,6 +114,11 @@ static void mxs_power_set_linreg(void)
 			POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 }
 
+/**
+ * mxs_get_batt_volt() - Measure battery input voltage
+ *
+ * This function retrieves the battery input voltage and returns it.
+ */
 static int mxs_get_batt_volt(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -96,11 +130,24 @@ static int mxs_get_batt_volt(void)
 	return volt;
 }
 
+/**
+ * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
+ *
+ * This function checks if the battery input voltage is higher than 3.6V and
+ * therefore allows the system to successfully boot using this power source.
+ */
 static int mxs_is_batt_ready(void)
 {
 	return (mxs_get_batt_volt() >= 3600);
 }
 
+/**
+ * mxs_is_batt_good() - Test if battery is operational at all
+ *
+ * This function starts recharging the battery and tests if the input current
+ * provided by the 5V input recharging the battery is also sufficient to power
+ * the DC-DC converter.
+ */
 static int mxs_is_batt_good(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -141,6 +188,15 @@ static int mxs_is_batt_good(void)
 	return 0;
 }
 
+/**
+ * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
+ *
+ * This function enables the 5V detection comparator and sets the 5V valid
+ * threshold to 4.4V . We use 4.4V threshold here to make sure that even
+ * under high load, the voltage drop on the 5V input won't be so critical
+ * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
+ * converter and thus making the system crash.
+ */
 static void mxs_power_setup_5v_detect(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -153,6 +209,12 @@ static void mxs_power_setup_5v_detect(void)
 			POWER_5VCTRL_PWRUP_VBUS_CMPS);
 }
 
+/**
+ * mxs_src_power_init() - Preconfigure the power block
+ *
+ * This function configures reasonable values for the DC-DC control loop
+ * and battery monitor.
+ */
 static void mxs_src_power_init(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -184,6 +246,12 @@ static void mxs_src_power_init(void)
 	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 }
 
+/**
+ * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
+ *
+ * This function configures the necessary parameters for the 4P2 linear
+ * regulator to supply the DC-DC converter from 5V input.
+ */
 static void mxs_power_init_4p2_params(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -208,6 +276,12 @@ static void mxs_power_init_4p2_params(void)
 		0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
+/**
+ * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
+ * @xfer:	Select if the input shall be enabled or disabled
+ *
+ * This function enables or disables the 4P2 input into the DC-DC converter.
+ */
 static void mxs_enable_4p2_dcdc_input(int xfer)
 {
 	struct mxs_power_regs *power_regs =
@@ -304,6 +378,12 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
 				POWER_CTRL_ENIRQ_VDD5V_DROOP);
 }
 
+/**
+ * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
+ *
+ * This function enables the 4P2 regulator and switches the DC-DC converter
+ * to use the 4P2 input.
+ */
 static void mxs_power_init_4p2_regulator(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -388,6 +468,12 @@ static void mxs_power_init_4p2_regulator(void)
 	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 }
 
+/**
+ * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
+ *
+ * This function configures the DC-DC converter to be supplied from the 4P2
+ * linear regulator.
+ */
 static void mxs_power_init_dcdc_4p2_source(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -410,6 +496,12 @@ static void mxs_power_init_dcdc_4p2_source(void)
 	}
 }
 
+/**
+ * mxs_power_enable_4p2() - Power up the 4P2 regulator
+ *
+ * This function drives the process of powering up the 4P2 linear regulator
+ * and switching the DC-DC converter input over to the 4P2 linear regulator.
+ */
 static void mxs_power_enable_4p2(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -469,6 +561,14 @@ static void mxs_power_enable_4p2(void)
 			&power_regs->hw_power_charge_clr);
 }
 
+/**
+ * mxs_boot_valid_5v() - Boot from 5V supply
+ *
+ * This function configures the power block to boot from valid 5V input.
+ * This is called only if the 5V is reliable and can properly supply the
+ * CPU. This function proceeds to configure the 4P2 converter to be supplied
+ * from the 5V input.
+ */
 static void mxs_boot_valid_5v(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -492,6 +592,11 @@ static void mxs_boot_valid_5v(void)
 	mxs_power_enable_4p2();
 }
 
+/**
+ * mxs_powerdown() - Shut down the system
+ *
+ * This function powers down the CPU completely.
+ */
 static void mxs_powerdown(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -501,6 +606,12 @@ static void mxs_powerdown(void)
 		&power_regs->hw_power_reset);
 }
 
+/**
+ * mxs_batt_boot() - Configure the power block to boot from battery input
+ *
+ * This function configures the power block to boot from the battery voltage
+ * supply.
+ */
 static void mxs_batt_boot(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -545,6 +656,14 @@ static void mxs_batt_boot(void)
 		0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
+/**
+ * mxs_handle_5v_conflict() - Test if the 5V input is reliable
+ *
+ * This function tests if the 5V input can reliably supply the system. If it
+ * can, then proceed to configuring the system to boot from 5V source, otherwise
+ * try booting from battery supply. If we can not boot from battery supply
+ * either, shut down the system.
+ */
 static void mxs_handle_5v_conflict(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -581,6 +700,12 @@ static void mxs_handle_5v_conflict(void)
 	}
 }
 
+/**
+ * mxs_5v_boot() - Configure the power block to boot from 5V input
+ *
+ * This function handles configuration of the power block when supplied by
+ * a 5V input.
+ */
 static void mxs_5v_boot(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -604,6 +729,12 @@ static void mxs_5v_boot(void)
 	mxs_handle_5v_conflict();
 }
 
+/**
+ * mxs_init_batt_bo() - Configure battery brownout threshold
+ *
+ * This function configures the battery input brownout threshold. The value
+ * at which the battery brownout happens is configured to 3.0V in the code.
+ */
 static void mxs_init_batt_bo(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -618,6 +749,12 @@ static void mxs_init_batt_bo(void)
 	writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 }
 
+/**
+ * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
+ *
+ * This function turns off the VDDD linear regulator and therefore makes
+ * the VDDD rail be supplied only by the DC-DC converter.
+ */
 static void mxs_switch_vddd_to_dcdc_source(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -632,6 +769,15 @@ static void mxs_switch_vddd_to_dcdc_source(void)
 		POWER_VDDDCTRL_DISABLE_STEPPING);
 }
 
+/**
+ * mxs_power_configure_power_source() - Configure power block source
+ *
+ * This function is the core of the power configuration logic. The function
+ * selects the power block input source and configures the whole power block
+ * accordingly. After the configuration is complete and the system is stable
+ * again, the function switches the CPU clock source back to PLL. Finally,
+ * the function switches the voltage rails to DC-DC converter.
+ */
 static void mxs_power_configure_power_source(void)
 {
 	int batt_ready, batt_good;
@@ -676,6 +822,15 @@ static void mxs_power_configure_power_source(void)
 #endif
 }
 
+/**
+ * mxs_enable_output_rail_protection() - Enable power rail protection
+ *
+ * This function enables overload protection on the power rails. This is
+ * triggered if the power rails' voltage drops rapidly due to overload and
+ * in such case, the supply to the powerrail is cut-off, protecting the
+ * CPU from damage. Note that under such condition, the system will likely
+ * crash or misbehave.
+ */
 static void mxs_enable_output_rail_protection(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -694,6 +849,13 @@ static void mxs_enable_output_rail_protection(void)
 			POWER_VDDIOCTRL_PWDN_BRNOUT);
 }
 
+/**
+ * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
+ *
+ * This function tests if the VDDIO rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
 static int mxs_get_vddio_power_source_off(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -722,6 +884,13 @@ static int mxs_get_vddio_power_source_off(void)
 
 }
 
+/**
+ * mxs_get_vddd_power_source_off() - Get VDDD rail power source
+ *
+ * This function tests if the VDDD rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
 static int mxs_get_vddd_power_source_off(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -810,6 +979,18 @@ static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
 };
 #endif
 
+/**
+ * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
+ * @cfg:		Configuration data of the DC-DC converter rail
+ * @new_target:		New target voltage of the DC-DC converter rail
+ * @new_brownout:	New brownout trigger voltage
+ *
+ * This function configures the output voltage on the DC-DC converter rail.
+ * The rail is selected by the @cfg argument. The new voltage target is
+ * selected by the @new_target and the voltage is specified in mV. The
+ * new brownout value is selected by the @new_brownout argument and the
+ * value is also in mV.
+ */
 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 				uint32_t new_target, uint32_t new_brownout)
 {
@@ -883,6 +1064,14 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 	}
 }
 
+/**
+ * mxs_setup_batt_detect() - Start the battery voltage measurement logic
+ *
+ * This function starts and configures the LRADC block. This allows the
+ * power initialization code to measure battery voltage and based on this
+ * knowledge, decide whether to boot at all, boot from battery or boot
+ * from 5V input.
+ */
 static void mxs_setup_batt_detect(void)
 {
 	mxs_lradc_init();
@@ -890,6 +1079,14 @@ static void mxs_setup_batt_detect(void)
 	early_delay(10);
 }
 
+/**
+ * mxs_ungate_power() - Ungate the POWER block
+ *
+ * This function ungates clock to the power block. In case the power block
+ * was still gated at this point, it will not be possible to configure the
+ * block and therefore the power initialization would fail. This function
+ * is only needed on i.MX233, on i.MX28 the power block is always ungated.
+ */
 static void mxs_ungate_power(void)
 {
 #ifdef CONFIG_MX23
@@ -900,6 +1097,12 @@ static void mxs_ungate_power(void)
 #endif
 }
 
+/**
+ * mxs_power_init() - The power block init main function
+ *
+ * This function calls all the power block initialization functions in
+ * proper sequence to start the power block.
+ */
 void mxs_power_init(void)
 {
 	struct mxs_power_regs *power_regs =
@@ -933,6 +1136,12 @@ void mxs_power_init(void)
 }
 
 #ifdef	CONFIG_SPL_MXS_PSWITCH_WAIT
+/**
+ * mxs_power_wait_pswitch() - Wait for power switch to be pressed
+ *
+ * This function waits until the power-switch was pressed to start booting
+ * the board.
+ */
 void mxs_power_wait_pswitch(void)
 {
 	struct mxs_power_regs *power_regs =
diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S
index 94b2b3fd30..3e454ae1bc 100644
--- a/arch/arm/cpu/arm926ejs/mxs/start.S
+++ b/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -152,39 +152,49 @@ _reset:
 	/*
 	 * Store all registers on old stack pointer, this will allow us later to
 	 * return to the BootROM and let the BootROM load U-Boot into RAM.
+	 *
+	 * WARNING: Register r0 and r1 are used by the BootROM to pass data
+	 *          to the called code. Register r0 will contain arbitrary
+	 *          data that are set in the BootStream. In case this code
+	 *          was started with CALL instruction, register r1 will contain
+	 *          pointer to the return value this function can then set.
+	 *          The code below MUST NOT CHANGE register r0 and r1 !
 	 */
 	push	{r0-r12,r14}
 
-	/* save control register c1 */
-	mrc	p15, 0, r0, c1, c0, 0
-	push	{r0}
+	/* Save control register c1 */
+	mrc	p15, 0, r2, c1, c0, 0
+	push	{r2}
 
-	/*
-	 * set the cpu to SVC32 mode and store old CPSR register content
-	 */
-	mrs	r0,cpsr
-	push	{r0}
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
+	/* Set the cpu to SVC32 mode and store old CPSR register content. */
+	mrs	r2, cpsr
+	push	{r2}
+	bic	r2, r2, #0x1f
+	orr	r2, r2, #0xd3
+	msr	cpsr, r2
 
 	bl	board_init_ll
 
+	/* Restore BootROM's CPU mode (especially FIQ). */
+	pop	{r2}
+	msr	cpsr,r2
+
 	/*
-	 * restore bootrom's cpu mode (especially FIQ)
+	 * Restore c1 register. Especially set exception vector location
+	 * back to BootROM space which is required by bootrom for USB boot.
 	 */
-	pop	{r0}
-	msr	cpsr,r0
+	pop	{r2}
+	mcr	p15, 0, r2, c1, c0, 0
+
+	pop	{r0-r12,r14}
 
 	/*
-	 * restore c1 register
-	 * (especially set exception vector location back to
-	 * bootrom space which is required by bootrom for USB boot)
+	 * In case this code was started by the CALL instruction, the register
+	 * r0 is examined by the BootROM after this code returns. The value in
+	 * r0 must be set to 0 to indicate successful return.
 	 */
-	pop	{r0}
-	mcr	p15, 0, r0, c1, c0, 0
+	mov r0, #0
 
-	pop	{r0-r12,r14}
 	bx	lr
 
 _hang:
diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk
index 1e41c11686..eb81a5708d 100644
--- a/arch/arm/cpu/arm946es/config.mk
+++ b/arch/arm/cpu/arm946es/config.mk
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS +=  -march=armv4
 # =========================================================================
 #
diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk
index 1e41c11686..eb81a5708d 100644
--- a/arch/arm/cpu/arm_intcm/config.mk
+++ b/arch/arm/cpu/arm_intcm/config.mk
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS +=  -march=armv4
 # =========================================================================
 #
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 2ea3d698fb..a31bf40e5b 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -27,6 +27,7 @@
 #include <miiphy.h>
 #include <cpsw.h>
 #include <asm/errno.h>
+#include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
@@ -137,6 +138,16 @@ int arch_misc_init(void)
 }
 
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
 static void rtc32k_enable(void)
 {
 	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index e5f287b338..fabe2595a3 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
 	.cm_div_m2_dpll		= CM_WKUP + 0xA0,
 };
 
-const struct dpll_params dpll_mpu = {
+struct dpll_params dpll_mpu_opp100 = {
 		CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
+const struct dpll_params dpll_core_opp100 = {
 		1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+		MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+		50, OSC-1, -1, -1, 1, 1, 1};
 const struct dpll_params dpll_per = {
 		960, OSC-1, 5, -1, -1, -1, -1};
 
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 63afaaa328..50eb598ff2 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -17,6 +17,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
+#include <power/tps65910.h>
 
 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
 
@@ -119,3 +120,59 @@ int print_cpuinfo(void)
 	return 0;
 }
 #endif	/* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+	int sil_rev;
+
+	sil_rev = readl(&cdev->deviceid) >> 28;
+
+	if (sil_rev == 1)
+		/* PG 2.0, efuse may not be set. */
+		return MPUPLL_M_800;
+	else if (sil_rev >= 2) {
+		/* Check what the efuse says our max speed is. */
+		int efuse_arm_mpu_max_freq;
+		efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+		switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
+		case AM335X_ZCZ_1000:
+			return MPUPLL_M_1000;
+		case AM335X_ZCZ_800:
+			return MPUPLL_M_800;
+		case AM335X_ZCZ_720:
+			return MPUPLL_M_720;
+		case AM335X_ZCZ_600:
+		case AM335X_ZCE_600:
+			return MPUPLL_M_600;
+		case AM335X_ZCZ_300:
+		case AM335X_ZCE_300:
+			return MPUPLL_M_300;
+		}
+	}
+
+	/* PG 1.0 or otherwise unknown, use the PG1.0 max */
+	return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+	/* For PG2.1 and later, we have one set of values. */
+	if (sil_rev >= 2) {
+		switch (frequency) {
+		case MPUPLL_M_1000:
+			return TPS65910_OP_REG_SEL_1_3_2_5;
+		case MPUPLL_M_800:
+			return TPS65910_OP_REG_SEL_1_2_6;
+		case MPUPLL_M_720:
+			return TPS65910_OP_REG_SEL_1_2_0;
+		case MPUPLL_M_600:
+		case MPUPLL_M_300:
+			return TPS65910_OP_REG_SEL_1_1_3;
+		}
+	}
+
+	/* Default to PG1.0/PG2.0 values. */
+	return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index ca4a9e72c0..f0d9c04327 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # If armv7-a is not supported by GCC fall-back to armv5, which is
 # supported by more tool-chains
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index 82b2b86520..69e3053a42 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -22,11 +22,11 @@ ENTRY(lowlevel_init)
 	ldr	sp, =CONFIG_SYS_INIT_SP_ADDR
 	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
 #ifdef CONFIG_SPL_BUILD
-	ldr	r8, =gdata
+	ldr	r9, =gdata
 #else
 	sub	sp, #GD_SIZE
 	bic	sp, sp, #7
-	mov	r8, sp
+	mov	r9, sp
 #endif
 	/*
 	 * Save the old lr(passed in ip) and the current lr to stack
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 7efb0d209a..df11678609 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -228,13 +228,13 @@ static u32 get_axi_clk(void)
 
 static u32 get_emi_slow_clk(void)
 {
-	u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
+	u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 
 	cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
 	emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
 	emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
-	emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
-	emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
+	emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
+	emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 
 	switch (emi_clk_sel) {
 	case 0:
@@ -251,7 +251,7 @@ static u32 get_emi_slow_clk(void)
 		break;
 	}
 
-	return root_freq / (emi_slow_pof + 1);
+	return root_freq / (emi_slow_podf + 1);
 }
 
 #ifdef CONFIG_MX6SL
@@ -282,6 +282,36 @@ static u32 get_mmdc_ch0_clk(void)
 	return freq / (podf + 1);
 
 }
+
+int enable_fec_anatop_clock(void)
+{
+	u32 reg = 0;
+	s32 timeout = 100000;
+
+	struct anatop_regs __iomem *anatop =
+		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+	reg = readl(&anatop->pll_enet);
+	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
+	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
+		reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+		writel(reg, &anatop->pll_enet);
+		while (timeout--) {
+			if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+				break;
+		}
+		if (timeout < 0)
+			return -ETIMEDOUT;
+	}
+
+	/* Enable FEC clock */
+	reg |= BM_ANADIG_PLL_ENET_ENABLE;
+	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+	writel(reg, &anatop->pll_enet);
+
+	return 0;
+}
+
 #else
 static u32 get_mmdc_ch0_clk(void)
 {
@@ -457,7 +487,7 @@ void enable_ipu_clock(void)
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	int reg;
 	reg = readl(&mxc_ccm->CCGR3);
-	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
 }
 /***************************************************/
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 6b4772b684..0ffa03ac01 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -76,6 +76,9 @@ void spl_board_init(void)
 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
 	arch_misc_init();
 #endif
+#ifdef CONFIG_AM33XX
+	am33xx_spl_board_init();
+#endif
 }
 
 int board_mmc_init(bd_t *bis)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 7580594074..ab0c5680f5 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores)
 
 	val = optimize_vcore_voltage(&vcores->iva);
 	do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
-
-	 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
-		/* Configure LDO SRAM "magic" bits */
-		writel(2, (*prcm)->prm_sldo_core_setup);
-		writel(2, (*prcm)->prm_sldo_mpu_setup);
-		writel(2, (*prcm)->prm_sldo_mm_setup);
-	}
 }
 
 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 579818d559..5a3d52c11a 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = {
 	.prm_vc_val_bypass = 0x4ae07ba0,
 	.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
 	.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
-	.prm_sldo_core_setup = 0x4ae07bc4,
-	.prm_sldo_core_ctrl = 0x4ae07bc8,
-	.prm_sldo_mpu_setup = 0x4ae07bcc,
-	.prm_sldo_mpu_ctrl = 0x4ae07bd0,
-	.prm_sldo_mm_setup = 0x4ae07bd4,
-	.prm_sldo_mm_ctrl = 0x4ae07bd8,
 
 	/* SCRM stuff, used by some boards */
 	.scrm_auxclk0 = 0x4ae0a310,
@@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = {
 	.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
 	.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
 
-	.prm_sldo_core_setup = 0x4ae07cc4,
-	.prm_sldo_core_ctrl = 0x4ae07cc8,
-	.prm_sldo_mpu_setup = 0x4ae07ccc,
-	.prm_sldo_mpu_ctrl = 0x4ae07cd0,
-	.prm_sldo_mm_setup = 0x4ae07cd4,
-	.prm_sldo_mm_ctrl = 0x4ae07cd8,
 	.prm_abbldo_mpu_setup = 0x4ae07cdc,
 	.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
 
diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk
index 4f01610868..3a36ab65e1 100644
--- a/arch/arm/cpu/armv7/rmobile/config.mk
+++ b/arch/arm/cpu/armv7/rmobile/config.mk
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v7a.
 PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
index 0133565299..3b8d9497a0 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -57,7 +57,7 @@ int timer_init(void)
 			SCUTIMER_CONTROL_ENABLE_MASK;
 
 	/* Load the timer counter register */
-	writel(0xFFFFFFFF, &timer_base->counter);
+	writel(0xFFFFFFFF, &timer_base->load);
 
 	/*
 	 * Start the A9Timer device
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
index 0f12f8b1c7..fd47c60939 100644
--- a/arch/arm/cpu/ixp/config.mk
+++ b/arch/arm/cpu/ixp/config.mk
@@ -8,7 +8,7 @@
 
 BIG_ENDIAN = y
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
+PLATFORM_RELFLAGS += -mbig-endian
 
 PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
 
diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk
index 535bca3e9f..d8d263d404 100644
--- a/arch/arm/cpu/pxa/config.mk
+++ b/arch/arm/cpu/pxa/config.mk
@@ -6,8 +6,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -mcpu=xscale
 # =========================================================================
 #
diff --git a/arch/arm/cpu/s3c44b0/Makefile b/arch/arm/cpu/s3c44b0/Makefile
deleted file mode 100644
index 39fdbf86c9..0000000000
--- a/arch/arm/cpu/s3c44b0/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(CPU).o
-
-START	= start.o
-
-COBJS	+= cache.o
-COBJS	+= cpu.o
-COBJS	+= timer.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/s3c44b0/cache.c b/arch/arm/cpu/s3c44b0/cache.c
deleted file mode 100644
index aeee02d85d..0000000000
--- a/arch/arm/cpu/s3c44b0/cache.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-static void s3c44b0_flush_cache(void)
-{
-	volatile int i;
-	/* flush cycle */
-	for(i=0x10002000;i<0x10004800;i+=16)
-	{
-		*((int *)i)=0x0;
-	}
-}
-
-void icache_enable (void)
-{
-	ulong reg;
-
-	s3c44b0_flush_cache();
-
-	/*
-		Init cache
-		Non-cacheable area (everything outside RAM)
-		0x0000:0000 - 0x0C00:0000
-	 */
-	NCACHBE0 = 0xC0000000;
-	NCACHBE1 = 0x00000000;
-
-	/*
-		Enable chache
-	*/
-	reg = SYSCFG;
-	reg |= 0x00000006; /* 8kB */
-	SYSCFG = reg;
-}
-
-void icache_disable (void)
-{
-	ulong reg;
-
-	reg = SYSCFG;
-	reg &= ~0x00000006; /* 8kB */
-	SYSCFG = reg;
-}
-
-int icache_status (void)
-{
-	return 0;
-}
-
-void dcache_enable (void)
-{
-	icache_enable();
-}
-
-void dcache_disable (void)
-{
-	icache_disable();
-}
-
-int dcache_status (void)
-{
-	return dcache_status();
-}
diff --git a/arch/arm/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk
deleted file mode 100644
index b902ca36a8..0000000000
--- a/arch/arm/cpu/s3c44b0/config.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/s3c44b0/cpu.c b/arch/arm/cpu/s3c44b0/cpu.c
deleted file mode 100644
index fa931503a0..0000000000
--- a/arch/arm/cpu/s3c44b0/cpu.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * S3C44B0 CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-int arch_cpu_init (void)
-{
-	icache_enable();
-
-	return 0;
-}
-
-int cleanup_before_linux (void)
-{
-	/*
-		cache memory should be enabled before calling
-		Linux to make the kernel uncompression faster
-	*/
-	icache_enable();
-
-	disable_interrupts ();
-
-	return 0;
-}
-
-void reset_cpu (ulong addr)
-{
-	/*
-		reset the cpu using watchdog
-	*/
-
-	/* Disable the watchdog.*/
-	WTCON&=~(1<<5);
-
-	/* set the timeout value to a short time... */
-	WTCNT = 0x1;
-
-	/* Enable the watchdog. */
-	WTCON|=1;
-	WTCON|=(1<<5);
-
-	while(1) {
-		/*NOP*/
-	}
-}
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
deleted file mode 100644
index 6a59592f4c..0000000000
--- a/arch/arm/cpu/s3c44b0/start.S
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * Startup Code for S3C44B0 CPU-core
- *
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- * Jump vector table
- */
-
-
-.globl _start
-_start:	b       reset
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-	add	pc, pc, #0x0c000000
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate u-boot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-	.word	CONFIG_SPL_TEXT_BASE
-#else
-	.word	CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	bl	lowlevel_init
-#endif
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	bx	lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#define INTCON (0x01c00000+0x200000)
-#define INTMSK (0x01c00000+0x20000c)
-#define LOCKTIME (0x01c00000+0x18000c)
-#define PLLCON (0x01c00000+0x180000)
-#define CLKCON (0x01c00000+0x180004)
-#define WTCON (0x01c00000+0x130000)
-cpu_init_crit:
-	/* disable watch dog */
-	ldr	r0, =WTCON
-	ldr	r1, =0x0
-	str	r1, [r0]
-
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	ldr	r1,=INTMSK
-	ldr	r0, =0x03fffeff
-	str	r0, [r1]
-
-	ldr	r1, =INTCON
-	ldr	r0, =0x05
-	str	r0, [r1]
-
-	/* Set Clock Control Register */
-	ldr	r1, =LOCKTIME
-	ldrb	r0, =800
-	strb	r0, [r1]
-
-	ldr	r1, =PLLCON
-
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-	ldr	r0, =0x34031	/* 66MHz (Quartz=11MHz) */
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-	ldr	r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-
-	str	r0, [r1]
-
-	ldr	r1,=CLKCON
-	ldr	r0, =0x7ff8
-	str	r0, [r1]
-
-	mov	pc, lr
-
-
-/*************************************************/
-/*	interrupt vectors	*/
-/*************************************************/
-real_vectors:
-	b	reset
-	b	undefined_instruction
-	b	software_interrupt
-	b	prefetch_abort
-	b	data_abort
-	b	not_used
-	b	irq
-	b	fiq
-
-/*************************************************/
-
-undefined_instruction:
-	mov	r6, #3
-	b	reset
-
-software_interrupt:
-	mov	r6, #4
-	b	reset
-
-prefetch_abort:
-	mov	r6, #5
-	b	reset
-
-data_abort:
-	mov	r6, #6
-	b	reset
-
-not_used:
-	/* we *should* never reach this */
-	mov	r6, #7
-	b	reset
-
-irq:
-	mov	r6, #8
-	b	reset
-
-fiq:
-	mov	r6, #9
-	b	reset
diff --git a/arch/arm/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c
deleted file mode 100644
index f25af7a390..0000000000
--- a/arch/arm/cpu/s3c44b0/timer.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (TCNTO1 & 0xffff)
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ NOT supported
-#endif
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	TCFG0 = 0x000000E9;
-	TCFG1 = 0x00000004;
-	TCON = 0x00000900;
-	TCNTB1 = TIMER_LOAD_VAL;
-	TCMPB1 = 0;
-	TCON = 0x00000B00;
-	TCON = 0x00000900;
-
-
-	lastdec = TCNTB1 = TIMER_LOAD_VAL;
-	timestamp = 0;
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-
-	tmo = usec / 1000;
-	tmo *= CONFIG_SYS_HZ;
-	tmo /= 8;
-
-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
-		/*NOP*/;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 8;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*8);
-	}
-
-	endtime = get_timer(0) + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk
index 576f685c58..b3026cc50d 100644
--- a/arch/arm/cpu/sa1100/config.mk
+++ b/arch/arm/cpu/sa1100/config.mk
@@ -6,8 +6,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
 # =========================================================================
 #
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index 140379fb38..02ed5957e9 100644
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -11,9 +11,17 @@
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000	1000
+#define MPUPLL_M_800	800
+#define MPUPLL_M_720	720
+#define MPUPLL_M_600	600
+#define MPUPLL_M_550	550
+#define MPUPLL_M_300	300
+
 /* MAIN PLL Fdll = 550 MHz, by default */
 #ifndef CONFIG_SYS_MPUCLK
-#define CONFIG_SYS_MPUCLK	550
+#define CONFIG_SYS_MPUCLK	MPUPLL_M_550
 #endif
 
 #define UART_RESET		(0x1 << 1)
@@ -21,5 +29,7 @@
 #define UART_SMART_IDLE_EN	(0x1 << 0x3)
 
 extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
 
 #endif	/* endif _CLOCKS_AM33XX_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 73e6db8998..52fa128af9 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -38,6 +38,16 @@
 #define AM335X				0xB944
 #define TI81XX				0xB81E
 #define DEVICE_ID			(CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK			0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300			0x1FEF
+#define AM335X_ZCZ_600			0x1FAF
+#define AM335X_ZCZ_720			0x1F2F
+#define AM335X_ZCZ_800			0x1E2F
+#define AM335X_ZCZ_1000			0x1C2F
+#define AM335X_ZCE_300			0x1FDF
+#define AM335X_ZCE_600			0x1F9F
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
@@ -509,6 +519,8 @@ struct ctrl_dev {
 	unsigned int macid1h;		/* offset 0x3c */
 	unsigned int resv4[4];
 	unsigned int miisel;		/* offset 0x50 */
+	unsigned int resv5[106];
+	unsigned int efuse_sma;		/* offset 0x1FC */
 };
 
 /* gmii_sel register defines */
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index c6070a3fc9..87b7d367b9 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -10,6 +10,7 @@
 
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
+#include <asm/arch/cpu.h>
 
 #define BOARD_REV_ID	0x0
 
@@ -42,4 +43,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 #ifdef CONFIG_NOR_BOOT
 void enable_norboot_pin_mux(void);
 #endif
+void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
 #endif
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index a27145ba28..92c847e44a 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -169,7 +169,7 @@ struct iim_regs {
 	struct fuse_bank {
 		u32 fuse_regs[0x20];
 		u32 fuse_rsvd[0xe0];
-	} bank[1];
+	} bank[2];
 };
 
 struct fuse_bank0_regs {
@@ -209,9 +209,13 @@ struct fuse_bank0_regs {
 #define IIM_BASE_ADDR		IMX_IIM_BASE
 #define IMX_FEC_BASE		(0x2b000 + IMX_IO_BASE)
 
+#define IMX_NFC_BASE		(0xD8000000)
 #define IMX_ESD_BASE		(0xD8001000)
 #define IMX_WEIM_BASE		(0xD8002000)
 
+#define NFC_BASE_ADDR		IMX_NFC_BASE
+
+
 /* FMCR System Control bit definition*/
 #define UART4_RXD_CTL	(1 << 25)
 #define UART4_RTS_CTL	(1 << 24)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index c49368765b..93f29a780f 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -50,4 +50,5 @@ void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_ipu_clock(void);
+int enable_fec_anatop_clock(void);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 74aefe60f4..2813593e25 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -892,7 +892,7 @@ struct mxc_ccm_reg {
 
 #define PLL2_PFD0_FREQ		352000000
 #define PLL2_PFD1_FREQ		594000000
-#define PLL2_PFD2_FREQ		400000000
+#define PLL2_PFD2_FREQ		396000000
 #define PLL2_PFD2_DIV_FREQ	200000000
 #define PLL3_PFD0_FREQ		720000000
 #define PLL3_PFD1_FREQ		540000000
diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index f4cfd4f921..ff13a1ea9f 100644
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -27,6 +27,11 @@
 #define IOMUXC_GPR13_SATA_PHY_2_MASK	(0x1f<<2)
 #define IOMUXC_GPR13_SATA_PHY_1_MASK	(3<<0)
 
+#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC_MASK    (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
+				| IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
+
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB	(0<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB	(1<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB	(2<<24)
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index c3d0b70877..b5df68afc6 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -235,7 +235,7 @@ enum {
 	MX6_PAD_DISP0_DAT1__GPIO_4_22		= IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6	= IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12	= IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10	= IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10	= IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6_PAD_DISP0_DAT10__LCDIF_DAT_10	= IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6	= IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3	= IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
@@ -309,7 +309,7 @@ enum {
 	MX6_PAD_DISP0_DAT19__GPIO_5_13		= IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24	= IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3	= IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
-	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	= IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
+	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2	= IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
 	MX6_PAD_DISP0_DAT2__LCDIF_DAT_2		= IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT2__ECSPI3_MISO		= IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0),
 	MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2	= IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
@@ -1043,7 +1043,7 @@ enum {
 	MX6_PAD_GPIO_1__ESAI1_SCKR		= IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0),
 	MX6_PAD_GPIO_1__WDOG2_WDOG_B		= IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
 	MX6_PAD_GPIO_1__KPP_ROW_5		= IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0),
-	MX6_PAD_GPIO_1__USBOTG_ID		= IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
+	MX6_PAD_GPIO_1__USB_OTG_ID		= IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
 	MX6_PAD_GPIO_1__PWM2_PWMO		= IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0),
 	MX6_PAD_GPIO_1__GPIO_1_1		= IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_1__USDHC1_CD		= IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 94df0075b0..fe9a8c343d 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -984,6 +984,7 @@ enum {
 	MX6_PAD_GPIO_1__ESAI1_SCKR		= IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
 	MX6_PAD_GPIO_1__WDOG2_WDOG_B		= IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
 	MX6_PAD_GPIO_1__KPP_ROW_5		= IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
+	MX6_PAD_GPIO_1__USB_OTG_ID		= IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0),
 	MX6_PAD_GPIO_1__PWM2_PWMO		= IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
 	MX6_PAD_GPIO_1__GPIO_1_1		= IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO_1__USDHC1_CD		= IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index b39a354f39..5f9c90ad87 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -18,5 +18,17 @@ enum {
 	MX6_PAD_SD2_DAT3__USDHC2_DAT3				= IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
 	MX6_PAD_UART1_RXD__UART1_RXD				= IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
 	MX6_PAD_UART1_TXD__UART1_TXD				= IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+
+	MX6_PAD_FEC_MDC__FEC_MDC				= IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_MDIO__FEC_MDIO				= IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0),
+	MX6_PAD_FEC_CRS_DV__FEC_RX_DV				= IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0),
+	MX6_PAD_FEC_RXD0__FEC_RX_DATA0				= IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0),
+	MX6_PAD_FEC_RXD1__FEC_RX_DATA1				= IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
+	MX6_PAD_FEC_TX_EN__FEC_TX_EN				= IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_TXD0__FEC_TX_DATA0				= IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_TXD1__FEC_TX_DATA1				= IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0),
+	MX6_PAD_FEC_REF_CLK__FEC_REF_OUT			= IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
+	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
+	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
 };
 #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 1038592c92..43c7dd6bf1 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -28,8 +28,9 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
 #include <asm/arch/iomux-mx28.h>
 #endif
 
-void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
-			const unsigned int iomux_size);
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+			 const iomux_cfg_t *iomux_setup,
+			 const unsigned int iomux_size);
 #endif
 
 struct mxs_pair {
diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h
deleted file mode 100644
index 146e265d9a..0000000000
--- a/arch/arm/include/asm/arch-s3c44b0/hardware.h
+++ /dev/null
@@ -1,281 +0,0 @@
-/********************************************************/
-/*							*/
-/* Samsung S3C44B0					*/
-/* tpu <tapu@371.net>					*/
-/*							*/
-/********************************************************/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define REGBASE		0x01c00000
-#define REGL(addr)	(*(volatile unsigned int *)(REGBASE+addr))
-#define REGW(addr)	(*(volatile unsigned short *)(REGBASE+addr))
-#define REGB(addr)	(*(volatile unsigned char *)(REGBASE+addr))
-
-
-/*****************************/
-/* CPU Wrapper Registers     */
-/*****************************/
-
-#define SYSCFG		REGL(0x000000)
-#define NCACHBE0	REGL(0x000004)
-#define NCACHBE1	REGL(0x000008)
-#define SBUSCON		REGL(0x040000)
-
-/************************************/
-/* Memory Controller Registers      */
-/************************************/
-
-#define BWSCON		REGL(0x080000)
-#define BANKCON0	REGL(0x080004)
-#define BANKCON1	REGL(0x080008)
-#define BANKCON2	REGL(0x08000c)
-#define BANKCON3	REGL(0x080010)
-#define BANKCON4	REGL(0x080014)
-#define BANKCON5	REGL(0x080018)
-#define BANKCON6	REGL(0x08001c)
-#define BANKCON7	REGL(0x080020)
-#define REFRESH		REGL(0x080024)
-#define BANKSIZE	REGL(0x080028)
-#define MRSRB6		REGL(0x08002c)
-#define MRSRB7		REGL(0x080030)
-
-/*********************/
-/* UART Registers    */
-/*********************/
-
-#define ULCON0		REGL(0x100000)
-#define ULCON1		REGL(0x104000)
-#define UCON0		REGL(0x100004)
-#define UCON1		REGL(0x104004)
-#define UFCON0		REGL(0x100008)
-#define UFCON1		REGL(0x104008)
-#define UMCON0		REGL(0x10000c)
-#define UMCON1		REGL(0x10400c)
-#define UTRSTAT0	REGL(0x100010)
-#define UTRSTAT1	REGL(0x104010)
-#define UERSTAT0	REGL(0x100014)
-#define UERSTAT1	REGL(0x104014)
-#define UFSTAT0		REGL(0x100018)
-#define UFSTAT1		REGL(0x104018)
-#define UMSTAT0		REGL(0x10001c)
-#define UMSTAT1		REGL(0x10401c)
-#define UTXH0		REGB(0x100020)
-#define UTXH1		REGB(0x104020)
-#define URXH0		REGB(0x100024)
-#define URXH1		REGB(0x104024)
-#define UBRDIV0		REGL(0x100028)
-#define UBRDIV1		REGL(0x104028)
-
-/*******************/
-/* SIO Registers   */
-/*******************/
-
-#define SIOCON		REGL(0x114000)
-#define SIODAT		REGL(0x114004)
-#define SBRDR		REGL(0x114008)
-#define ITVCNT		REGL(0x11400c)
-#define DCNTZ		REGL(0x114010)
-
-/********************/
-/* IIS Registers    */
-/********************/
-
-#define IISCON		REGL(0x118000)
-#define IISMOD		REGL(0x118004)
-#define IISPSR		REGL(0x118008)
-#define IISFIFCON	REGL(0x11800c)
-#define IISFIF		REGW(0x118010)
-
-/**************************/
-/* I/O Ports Registers    */
-/**************************/
-
-#define PCONA		REGL(0x120000)
-#define PDATA		REGL(0x120004)
-#define PCONB		REGL(0x120008)
-#define PDATB		REGL(0x12000c)
-#define PCONC		REGL(0x120010)
-#define PDATC		REGL(0x120014)
-#define PUPC		REGL(0x120018)
-#define PCOND		REGL(0x12001c)
-#define PDATD		REGL(0x120020)
-#define PUPD		REGL(0x120024)
-#define PCONE		REGL(0x120028)
-#define PDATE		REGL(0x12002c)
-#define PUPE		REGL(0x120030)
-#define PCONF		REGL(0x120034)
-#define PDATF		REGL(0x120038)
-#define PUPF		REGL(0x12003c)
-#define PCONG		REGL(0x120040)
-#define PDATG		REGL(0x120044)
-#define PUPG		REGL(0x120048)
-#define SPUCR		REGL(0x12004c)
-#define EXTINT		REGL(0x120050)
-#define EXTINTPND	REGL(0x120054)
-
-/*********************************/
-/* WatchDog Timers Registers     */
-/*********************************/
-
-#define WTCON		REGL(0x130000)
-#define WTDAT		REGL(0x130004)
-#define WTCNT		REGL(0x130008)
-
-/*********************************/
-/* A/D Converter Registers       */
-/*********************************/
-
-#define ADCCON		REGL(0x140000)
-#define ADCPSR		REGL(0x140004)
-#define ADCDAT		REGL(0x140008)
-
-/***************************/
-/* PWM Timer Registers     */
-/***************************/
-
-#define TCFG0		REGL(0x150000)
-#define TCFG1		REGL(0x150004)
-#define TCON		REGL(0x150008)
-#define TCNTB0		REGL(0x15000c)
-#define TCMPB0		REGL(0x150010)
-#define TCNTO0		REGL(0x150014)
-#define TCNTB1		REGL(0x150018)
-#define TCMPB1		REGL(0x15001c)
-#define TCNTO1		REGL(0x150020)
-#define TCNTB2		REGL(0x150024)
-#define TCMPB2		REGL(0x150028)
-#define TCNTO2		REGL(0x15002c)
-#define TCNTB3		REGL(0x150030)
-#define TCMPB3		REGL(0x150034)
-#define TCNTO3		REGL(0x150038)
-#define TCNTB4		REGL(0x15003c)
-#define TCMPB4		REGL(0x150040)
-#define TCNTO4		REGL(0x150044)
-#define TCNTB5		REGL(0x150048)
-#define TCNTO5		REGL(0x15004c)
-
-/*********************/
-/* IIC Registers     */
-/*********************/
-
-#define IICCON		REGL(0x160000)
-#define IICSTAT		REGL(0x160004)
-#define IICADD		REGL(0x160008)
-#define IICDS		REGL(0x16000c)
-
-/*********************/
-/* RTC Registers     */
-/*********************/
-
-#define RTCCON		REGB(0x170040)
-#define RTCALM		REGB(0x170050)
-#define ALMSEC		REGB(0x170054)
-#define ALMMIN		REGB(0x170058)
-#define ALMHOUR		REGB(0x17005c)
-#define ALMDAY		REGB(0x170060)
-#define ALMMON		REGB(0x170064)
-#define ALMYEAR		REGB(0x170068)
-#define RTCRST		REGB(0x17006c)
-#define BCDSEC		REGB(0x170070)
-#define BCDMIN		REGB(0x170074)
-#define BCDHOUR		REGB(0x170078)
-#define BCDDAY		REGB(0x17007c)
-#define BCDDATE		REGB(0x170080)
-#define BCDMON		REGB(0x170084)
-#define BCDYEAR		REGB(0x170088)
-#define TICINT		REGB(0x17008c)
-
-/*********************************/
-/* Clock & Power Registers       */
-/*********************************/
-
-#define PLLCON		REGL(0x180000)
-#define CLKCON		REGL(0x180004)
-#define CLKSLOW		REGL(0x180008)
-#define LOCKTIME	REGL(0x18000c)
-
-/**************************************/
-/* Interrupt Controller Registers     */
-/**************************************/
-
-#define INTCON		REGL(0x200000)
-#define INTPND		REGL(0x200004)
-#define INTMOD		REGL(0x200008)
-#define INTMSK		REGL(0x20000c)
-#define I_PSLV		REGL(0x200010)
-#define I_PMST		REGL(0x200014)
-#define I_CSLV		REGL(0x200018)
-#define I_CMST		REGL(0x20001c)
-#define I_ISPR		REGL(0x200020)
-#define I_ISPC		REGL(0x200024)
-#define F_ISPR		REGL(0x200038)
-#define F_ISPC		REGL(0x20003c)
-
-/********************************/
-/* LCD Controller Registers     */
-/********************************/
-
-#define LCDCON1		REGL(0x300000)
-#define LCDCON2		REGL(0x300004)
-#define LCDSADDR1	REGL(0x300008)
-#define LCDSADDR2	REGL(0x30000c)
-#define LCDSADDR3	REGL(0x300010)
-#define REDLUT		REGL(0x300014)
-#define GREENLUT	REGL(0x300018)
-#define BLUELUT		REGL(0x30001c)
-#define DP1_2		REGL(0x300020)
-#define DP4_7		REGL(0x300024)
-#define DP3_5		REGL(0x300028)
-#define DP2_3		REGL(0x30002c)
-#define DP5_7		REGL(0x300030)
-#define DP3_4		REGL(0x300034)
-#define DP4_5		REGL(0x300038)
-#define DP6_7		REGL(0x30003c)
-#define LCDCON3		REGL(0x300040)
-#define DITHMODE	REGL(0x300044)
-
-/*********************/
-/* DMA Registers     */
-/*********************/
-
-#define ZDCON0		REGL(0x280000)
-#define ZDISRC0		REGL(0x280004)
-#define ZDIDES0		REGL(0x280008)
-#define ZDICNT0		REGL(0x28000c)
-#define ZDCSRC0		REGL(0x280010)
-#define ZDCDES0		REGL(0x280014)
-#define ZDCCNT0		REGL(0x280018)
-
-#define ZDCON1		REGL(0x280020)
-#define ZDISRC1		REGL(0x280024)
-#define ZDIDES1		REGL(0x280028)
-#define ZDICNT1		REGL(0x28002c)
-#define ZDCSRC1		REGL(0x280030)
-#define ZDCDES1		REGL(0x280034)
-#define ZDCCNT1		REGL(0x280038)
-
-#define BDCON0		REGL(0x380000)
-#define BDISRC0		REGL(0x380004)
-#define BDIDES0		REGL(0x380008)
-#define BDICNT0		REGL(0x38000c)
-#define BDCSRC0		REGL(0x380010)
-#define BDCDES0		REGL(0x380014)
-#define BDCCNT0		REGL(0x380018)
-
-#define BDCON1		REGL(0x380020)
-#define BDISRC1		REGL(0x380024)
-#define BDIDES1		REGL(0x380028)
-#define BDICNT1		REGL(0x38002c)
-#define BDCSRC1		REGL(0x380030)
-#define BDCDES1		REGL(0x380034)
-#define BDCCNT1		REGL(0x380038)
-
-
-#define CLEAR_PEND_INT(n)       I_ISPC = (1<<(n))
-#define INT_ENABLE(n)		INTMSK &= ~(1<<(n))
-#define INT_DISABLE(n)		INTMSK |= (1<<(n))
-
-#define HARD_RESET_NOW()
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 009863beec..55a4e266a0 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -16,7 +16,7 @@ enum dma_data_direction {
 
 static void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
-	*handle = (unsigned long)malloc(len);
+	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
 	return (void *)*handle;
 }
 
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 79a9597419..e126436093 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -47,6 +47,6 @@ struct arch_global_data {
 
 #include <asm-generic/global_data.h>
 
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r9")
 
 #endif /* __ASM_GBL_DATA_H */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 5e2f027ba4..61fee9f06d 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -310,12 +310,6 @@ struct prcm_regs {
 	u32 prm_vc_val_bypass;
 	u32 prm_vc_cfg_i2c_mode;
 	u32 prm_vc_cfg_i2c_clk;
-	u32 prm_sldo_core_setup;
-	u32 prm_sldo_core_ctrl;
-	u32 prm_sldo_mpu_setup;
-	u32 prm_sldo_mpu_ctrl;
-	u32 prm_sldo_mm_setup;
-	u32 prm_sldo_mm_ctrl;
 	u32 prm_abbldo_mpu_setup;
 	u32 prm_abbldo_mpu_ctrl;
 
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 960d12e732..ac54b9359a 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -69,7 +69,7 @@ ENTRY(_main)
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
 	sub	sp, #GD_SIZE	/* allocate one GD above SP */
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
-	mov	r8, sp		/* GD is above SP */
+	mov	r9, sp		/* GD is above SP */
 	mov	r0, #0
 	bl	board_init_f
 
@@ -81,15 +81,15 @@ ENTRY(_main)
  * 'here' but relocated.
  */
 
-	ldr	sp, [r8, #GD_START_ADDR_SP]	/* sp = gd->start_addr_sp */
+	ldr	sp, [r9, #GD_START_ADDR_SP]	/* sp = gd->start_addr_sp */
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
-	ldr	r8, [r8, #GD_BD]		/* r8 = gd->bd */
-	sub	r8, r8, #GD_SIZE		/* new GD is below bd */
+	ldr	r9, [r9, #GD_BD]		/* r9 = gd->bd */
+	sub	r9, r9, #GD_SIZE		/* new GD is below bd */
 
 	adr	lr, here
-	ldr	r0, [r8, #GD_RELOC_OFF]		/* r0 = gd->reloc_off */
+	ldr	r0, [r9, #GD_RELOC_OFF]		/* r0 = gd->reloc_off */
 	add	lr, lr, r0
-	ldr	r0, [r8, #GD_RELOCADDR]		/* r0 = gd->relocaddr */
+	ldr	r0, [r9, #GD_RELOCADDR]		/* r0 = gd->relocaddr */
 	b	relocate_code
 here:
 
@@ -111,8 +111,8 @@ clbss_l:cmp	r0, r1			/* while not at end of BSS */
 	bl red_led_on
 
 	/* call board_init_r(gd_t *id, ulong dest_addr) */
-	mov	r0, r8			/* gd_t */
-	ldr	r1, [r8, #GD_RELOCADDR]	/* dest_addr */
+	mov     r0, r9                  /* gd_t */
+	ldr	r1, [r9, #GD_RELOCADDR]	/* dest_addr */
 	/* call board_init_r */
 	ldr	pc, =board_init_r	/* this is auto-relocated! */
 
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index ab90430dce..a62a556561 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -22,7 +22,7 @@
 
 ENTRY(relocate_code)
 	ldr	r1, =__image_copy_start	/* r1 <- SRC &__image_copy_start */
-	subs	r9, r0, r1		/* r9 <- relocation offset */
+	subs	r4, r0, r1		/* r4 <- relocation offset */
 	beq	relocate_done		/* skip relocation */
 	ldr	r2, =__image_copy_end	/* r2 <- SRC &__image_copy_end */
 
@@ -44,9 +44,9 @@ fixloop:
 	bne	fixnext
 
 	/* relative fix: increase location by offset */
-	add	r0, r0, r9
+	add	r0, r0, r4
 	ldr	r1, [r0]
-	add	r1, r1, r9
+	add	r1, r1, r4
 	str	r1, [r0]
 fixnext:
 	cmp	r2, r3
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index 26d0be47e5..dfcc596815 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -25,9 +25,6 @@ gd_t gdata __attribute__ ((section(".data")));
  */
 void __weak board_init_f(ulong dummy)
 {
-	/* Set the stack pointer. */
-	asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);