Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

6 files changed, 89 insertions, 58 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index e61d8e0fc2..a70fb711c7 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1052,6 +1052,17 @@ create_init_ram_area:
 		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
 		CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
 		0, r6
+
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT)
+	/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+	 * to L3 Address configured by PBL for ISBC code
+	*/
+	create_tlb1_entry 15, \
+		1, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+		CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
+
 #else
 	/*
 	 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
index 132689b26e..8a1092ea65 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
@@ -51,11 +51,10 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 struct liodn_id_table fman1_liodn_tbl[] = {
-	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_10G_TYPE2_LIODN(1, 0, 88),
 	SET_FMAN_RX_1G_LIODN(1, 1, 89),
 	SET_FMAN_RX_1G_LIODN(1, 2, 90),
 	SET_FMAN_RX_1G_LIODN(1, 3, 91),
-	SET_FMAN_RX_10G_LIODN(1, 0, 94),
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 74c4c81887..7b43b282bb 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -214,8 +214,8 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
 	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
-	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
-	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -266,37 +266,30 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
 #elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
 static const struct serdes_config serdes1_cfg_tbl[] = {
 	/* SerDes 1 */
-	{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
-		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+	{1, {NONE, NONE, NONE, NONE,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
 		XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
-	{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+	{2, {NONE, NONE, NONE, NONE,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-	{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
-		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+	{4, {NONE, NONE, NONE, NONE,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
 		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
-	{27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+	{27, {NONE, NONE, NONE, NONE,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+	{28, {NONE, NONE, NONE, NONE,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-	{35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+	{35, {NONE, NONE, NONE, NONE,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
-		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+	{36, {NONE, NONE, NONE, NONE,
 		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
 		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
-	{37, {NONE, NONE, QSGMII_FM1_B, NONE,
+	{37, {NONE, NONE, NONE, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE} },
-	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
+	{38, {NONE, NONE, NONE, NONE,
 		NONE, NONE, QSGMII_FM1_A, NONE} },
 	{}
 };
@@ -363,45 +356,45 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
 		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
 	{37, {NONE, NONE, QSGMII_FM2_B, NONE,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
 		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
-		NONE, QSGMII_FM1_A, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-		NONE, NONE, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
 		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
-		NONE, NONE, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-		NONE, NONE, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-		NONE, NONE, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-		NONE, NONE, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
 		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
-		NONE, NONE, NONE, NONE} },
+		NONE, NONE, QSGMII_FM2_A, NONE} },
 	{55, {NONE, XFI_FM1_MAC10,
 		XFI_FM2_MAC10, NONE,
 		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -424,51 +417,51 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
 	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
 	{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
-	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
-	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
+	{7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
 	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
 	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
-	{11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+	{11, {NONE, NONE, NONE, NONE,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
-	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+	{12, {NONE, NONE, NONE, NONE,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
 	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		PCIE2, PCIE2, PCIE2, PCIE2} },
-	{15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+	{15, {NONE, NONE, NONE, NONE,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
-	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+	{16, {NONE, NONE, NONE, NONE,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
-	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+	{17, {NONE, NONE, NONE, NONE,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
 		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
-			NONE, NONE, NONE, NONE} },
+		SRIO1, SRIO1, SRIO1, SRIO1} },
 	{}
 };
 static const struct serdes_config serdes4_cfg_tbl[] = {
 	/* SerDes 4 */
-	{3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
-	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
-	{5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
-	{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
-	{11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
-	{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
-	{13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
-	{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
+	{3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+	{5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+	{9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+	{10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+	{11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+	{12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+	{13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+	{14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+	{15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+	{16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+	{18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
 	{}
 }
 ;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 9d56bc1773..7a5487be88 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -334,7 +334,7 @@
 #elif defined(CONFIG_P1025)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #define CONFIG_SYS_PPC_E500_DEBUG_TLB	2
 #define CONFIG_TSECV2
 #define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -806,6 +806,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define QE_MURAM_SIZE			0x6000UL
 #define MAX_QE_RISC			1
 #define QE_NUM_OF_SNUM			28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
 
 #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
 defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 811f034293..6206bee5d3 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -145,6 +145,12 @@ extern void fdt_fixup_liodn(void *blob);
 		FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
 
+/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
+	SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \
+		FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \
+
 /*
  * handle both old and new versioned SEC properties:
  * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 8f794ef381..d57bb55692 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -37,7 +37,9 @@
 	defined(CONFIG_T2080QDS) || \
 	defined(CONFIG_T2080RDB) || \
 	defined(CONFIG_T1040QDS) || \
+	defined(CONFIG_T104xD4QDS) || \
 	defined(CONFIG_T104xRDB) || \
+	defined(CONFIG_T104xD4RDB) || \
 	defined(CONFIG_PPC_T1023) || \
 	defined(CONFIG_PPC_T1024)
 #define CONFIG_SYS_CPC_REINIT_F
@@ -46,6 +48,11 @@
 #define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
 #endif
 
+#if defined(CONFIG_RAMBOOT_PBL)
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
+#endif
+
 #if defined(CONFIG_C29XPCIE)
 #define CONFIG_KEY_REVOCATION
 #endif
@@ -68,6 +75,18 @@
 #endif
 
 #ifndef CONFIG_FIT_SIGNATURE
+/* If Boot Script is not on NOR and is required to be copied on RAM */
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_HDR_ADDR_RAM		0x00010000
+#define CONFIG_BS_HDR_ADDR_FLASH	0x00800000
+#define CONFIG_BS_HDR_SIZE		0x00002000
+#define CONFIG_BS_ADDR_RAM		0x00012000
+#define CONFIG_BS_ADDR_FLASH		0x00802000
+#define CONFIG_BS_SIZE			0x00001000
+
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	CONFIG_BS_HDR_ADDR_RAM
+#else
+
 /* The bootscript header address is different for B4860 because the NOR
  * mapping is different on B4 due to reduced NOR size.
  */
@@ -83,6 +102,8 @@
 #define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
 #endif
 
+#endif
+
 #include <config_fsl_secboot.h>
 #endif