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| author | Thomas Chou <thomas@wytron.com.tw> | 2015-10-09 20:09:17 +0800 |
|---|---|---|
| committer | Thomas Chou <thomas@wytron.com.tw> | 2015-10-23 07:37:20 +0800 |
| commit | 55e2b4d4e5dd179d748dca9f8c44585b7319f2e2 (patch) | |
| tree | 7443193c43dc586b065c1c8026bf62a665d539cc /arch/nios2 | |
| parent | bbba0714b7ca2d2424c11193a7884da8ef05c520 (diff) | |
| download | blackbird-obmc-uboot-55e2b4d4e5dd179d748dca9f8c44585b7319f2e2.tar.gz blackbird-obmc-uboot-55e2b4d4e5dd179d748dca9f8c44585b7319f2e2.zip | |
nios2: set default cache configuration in start.S
Set default icache and dcache configuration for start.S.
We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE...
configuration macros. As we are just barely starting from
reset, there is no luxury of device tree.
We will set some maximum cache configuration so that it will
work for most configurations. This is used only in this
start.S. The speed penalty is only once here.
After start up, during board initialization, cpu information
will be extracted from device tree. Then cache flush operations
will have correct cache configurations.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/nios2')
| -rw-r--r-- | arch/nios2/cpu/start.S | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 501ac39e3f..91e9c31b70 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -9,6 +9,15 @@ #include <config.h> #include <version.h> +/* + * icache and dcache configuration used only for start.S. + * the values are chosen so that it will work for all configuration. + */ +#define ICACHE_LINE_SIZE 32 /* fixed 32 */ +#define ICACHE_SIZE_MAX 0x10000 /* 64k max */ +#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */ +#define DCACHE_SIZE_MAX 0x10000 /* 64k max */ + /* RESTART */ .text .global _start @@ -22,9 +31,9 @@ _start: * just be invalidating the cache a second time. If cache * is not implemented initi behaves as nop. */ - ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE) + ori r4, r0, %lo(ICACHE_LINE_SIZE) + movhi r5, %hi(ICACHE_SIZE_MAX) + ori r5, r5, %lo(ICACHE_SIZE_MAX) 0: initi r5 sub r5, r5, r4 bgt r5, r0, 0b @@ -51,10 +60,9 @@ _except_end: * DCACHE INIT -- if dcache not implemented, initd behaves as * nop. */ - movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE) - ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE) - movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE) - ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE) + ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN) + movhi r5, %hi(DCACHE_SIZE_MAX) + ori r5, r5, %lo(DCACHE_SIZE_MAX) mov r6, r0 1: initd 0(r6) add r6, r6, r4 |
