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authorAneesh V <aneesh@ti.com>2011-06-16 23:30:48 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-07-04 10:55:25 +0200
commite47f2db5371047eb9bcd115fee084e6a8a92a239 (patch)
treee20802d7ecb0586dc819f8f3a2e348c2f273dd69 /arch/arm/lib
parent2c451f7831208741d0ff7ca6046cffcd9ee49def (diff)
downloadblackbird-obmc-uboot-e47f2db5371047eb9bcd115fee084e6a8a92a239.tar.gz
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armv7: rename cache related CONFIG flags
Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: Aneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
Diffstat (limited to 'arch/arm/lib')
-rw-r--r--arch/arm/lib/Makefile2
-rw-r--r--arch/arm/lib/board.c2
-rw-r--r--arch/arm/lib/cache-cp15.c6
3 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 03b1b5e4af..f993d743e0 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -39,9 +39,7 @@ GLCOBJS += div0.o
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-y += cache.o
-ifndef CONFIG_SYS_NO_CP15_CACHE
COBJS-y += cache-cp15.o
-endif
COBJS-y += interrupts.o
COBJS-y += reset.o
SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 169dfebcf1..4f88f5823b 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -326,7 +326,7 @@ void board_init_f (ulong bootflag)
debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
addr -= (4096 * 4);
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index d9175f0583..ba73fb925c 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/system.h>
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
#define CACHE_SETUP 0x1a
@@ -118,7 +118,7 @@ static void cache_disable(uint32_t cache_bit)
}
#endif
-#ifdef CONFIG_SYS_NO_ICACHE
+#ifdef CONFIG_SYS_ICACHE_OFF
void icache_enable (void)
{
return;
@@ -150,7 +150,7 @@ int icache_status(void)
}
#endif
-#ifdef CONFIG_SYS_NO_DCACHE
+#ifdef CONFIG_SYS_DCACHE_OFF
void dcache_enable (void)
{
return;
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