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| author | Chandan Nath <chandan.nath@ti.com> | 2012-07-24 12:22:17 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:11 +0200 |
| commit | e79cd8eb9bc47b6bb40e5948c71a00785f764257 (patch) | |
| tree | 12049aa66b453d460af3884368ed21d11ae97eb4 /arch/arm/include | |
| parent | 2b62997ce931494da3f5836899a91ae3909a0c0c (diff) | |
| download | blackbird-obmc-uboot-e79cd8eb9bc47b6bb40e5948c71a00785f764257.tar.gz blackbird-obmc-uboot-e79cd8eb9bc47b6bb40e5948c71a00785f764257.zip | |
am33xx: CPSW init and definitions
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.
Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/cpu.h | 11 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware.h | 5 |
2 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index e63ab745f3..de9ee91496 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -255,6 +255,17 @@ struct ctrl_stat { #define OMAP_GPIO_CLEARDATAOUT 0x0190 #define OMAP_GPIO_SETDATAOUT 0x0194 +/* Control Device Register */ +struct ctrl_dev { + unsigned int deviceid; /* offset 0x00 */ + unsigned int resv1[11]; + unsigned int macid0l; /* offset 0x30 */ + unsigned int macid0h; /* offset 0x34 */ + unsigned int macid1l; /* offset 0x38 */ + unsigned int macid1h; /* offset 0x3c */ + unsigned int resv2[4]; + unsigned int miisel; /* offset 0x50 */ +}; #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 0ec22eb918..4b1c725743 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -46,6 +46,7 @@ /* Control Module Base Address */ #define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 /* PRCM Base Address */ #define PRCM_BASE 0x44E00000 @@ -78,4 +79,8 @@ #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE +/* CPSW Config space */ +#define AM335X_CPSW_BASE 0x4A100000 +#define AM335X_CPSW_MDIO_BASE 0x4A101000 + #endif /* __AM33XX_HARDWARE_H */ |
