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authorYunhui Cui <yunhui.cui@nxp.com>2016-06-08 10:31:42 +0800
committerYork Sun <york.sun@nxp.com>2016-06-10 13:43:12 -0700
commita758177f9b9a567df2e8e6e57ac905ada24d8d9c (patch)
treeb618ee8928ad9a9ff004a174d120f3066e3006e7 /arch/arm/include
parent6b3943f1b04be60f147ee540fbd72c4c7ea89f80 (diff)
downloadblackbird-obmc-uboot-a758177f9b9a567df2e8e6e57ac905ada24d8d9c.tar.gz
blackbird-obmc-uboot-a758177f9b9a567df2e8e6e57ac905ada24d8d9c.zip
armv8/ls2080a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 65b3357009..c6b9f1336b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,6 +26,7 @@
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
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